1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2018 3 */ 4 5 #include "ixgbe_common.h" 6 #include "ixgbe_phy.h" 7 #include "ixgbe_dcb.h" 8 #include "ixgbe_dcb_82599.h" 9 #include "ixgbe_api.h" 10 11 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 12 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 13 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 14 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 15 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 16 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 17 u16 count); 18 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 19 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 20 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 21 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw); 22 23 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 24 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 25 u16 *san_mac_offset); 26 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 27 u16 words, u16 *data); 28 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 29 u16 words, u16 *data); 30 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 31 u16 offset); 32 33 /** 34 * ixgbe_init_ops_generic - Inits function ptrs 35 * @hw: pointer to the hardware structure 36 * 37 * Initialize the function pointers. 38 **/ 39 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 40 { 41 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 42 struct ixgbe_mac_info *mac = &hw->mac; 43 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 44 45 DEBUGFUNC("ixgbe_init_ops_generic"); 46 47 /* EEPROM */ 48 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 49 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 50 if (eec & IXGBE_EEC_PRES) { 51 eeprom->ops.read = ixgbe_read_eerd_generic; 52 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 53 } else { 54 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 55 eeprom->ops.read_buffer = 56 ixgbe_read_eeprom_buffer_bit_bang_generic; 57 } 58 eeprom->ops.write = ixgbe_write_eeprom_generic; 59 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 60 eeprom->ops.validate_checksum = 61 ixgbe_validate_eeprom_checksum_generic; 62 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 63 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 64 65 /* MAC */ 66 mac->ops.init_hw = ixgbe_init_hw_generic; 67 mac->ops.reset_hw = NULL; 68 mac->ops.start_hw = ixgbe_start_hw_generic; 69 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 70 mac->ops.get_media_type = NULL; 71 mac->ops.get_supported_physical_layer = NULL; 72 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 73 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 74 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 75 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 76 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 77 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 78 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 79 mac->ops.prot_autoc_read = prot_autoc_read_generic; 80 mac->ops.prot_autoc_write = prot_autoc_write_generic; 81 82 /* LEDs */ 83 mac->ops.led_on = ixgbe_led_on_generic; 84 mac->ops.led_off = ixgbe_led_off_generic; 85 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 86 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 87 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 88 89 /* RAR, Multicast, VLAN */ 90 mac->ops.set_rar = ixgbe_set_rar_generic; 91 mac->ops.clear_rar = ixgbe_clear_rar_generic; 92 mac->ops.insert_mac_addr = NULL; 93 mac->ops.set_vmdq = NULL; 94 mac->ops.clear_vmdq = NULL; 95 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 96 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 97 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 98 mac->ops.enable_mc = ixgbe_enable_mc_generic; 99 mac->ops.disable_mc = ixgbe_disable_mc_generic; 100 mac->ops.clear_vfta = NULL; 101 mac->ops.set_vfta = NULL; 102 mac->ops.set_vlvf = NULL; 103 mac->ops.init_uta_tables = NULL; 104 mac->ops.enable_rx = ixgbe_enable_rx_generic; 105 mac->ops.disable_rx = ixgbe_disable_rx_generic; 106 107 /* Flow Control */ 108 mac->ops.fc_enable = ixgbe_fc_enable_generic; 109 mac->ops.setup_fc = ixgbe_setup_fc_generic; 110 mac->ops.fc_autoneg = ixgbe_fc_autoneg; 111 112 /* Link */ 113 mac->ops.get_link_capabilities = NULL; 114 mac->ops.setup_link = NULL; 115 mac->ops.check_link = NULL; 116 mac->ops.dmac_config = NULL; 117 mac->ops.dmac_update_tcs = NULL; 118 mac->ops.dmac_config_tcs = NULL; 119 120 return IXGBE_SUCCESS; 121 } 122 123 /** 124 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 125 * of flow control 126 * @hw: pointer to hardware structure 127 * 128 * This function returns true if the device supports flow control 129 * autonegotiation, and false if it does not. 130 * 131 **/ 132 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 133 { 134 bool supported = false; 135 ixgbe_link_speed speed; 136 bool link_up; 137 138 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 139 140 switch (hw->phy.media_type) { 141 case ixgbe_media_type_fiber_qsfp: 142 case ixgbe_media_type_fiber: 143 /* flow control autoneg black list */ 144 switch (hw->device_id) { 145 case IXGBE_DEV_ID_X550EM_A_SFP: 146 case IXGBE_DEV_ID_X550EM_A_SFP_N: 147 case IXGBE_DEV_ID_X550EM_A_QSFP: 148 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 149 supported = false; 150 break; 151 default: 152 hw->mac.ops.check_link(hw, &speed, &link_up, false); 153 /* if link is down, assume supported */ 154 if (link_up) 155 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 156 true : false; 157 else 158 supported = true; 159 } 160 161 break; 162 case ixgbe_media_type_backplane: 163 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 164 supported = false; 165 else 166 supported = true; 167 break; 168 case ixgbe_media_type_copper: 169 /* only some copper devices support flow control autoneg */ 170 switch (hw->device_id) { 171 case IXGBE_DEV_ID_82599_T3_LOM: 172 case IXGBE_DEV_ID_X540T: 173 case IXGBE_DEV_ID_X540T1: 174 case IXGBE_DEV_ID_X550T: 175 case IXGBE_DEV_ID_X550T1: 176 case IXGBE_DEV_ID_X550EM_X_10G_T: 177 case IXGBE_DEV_ID_X550EM_A_10G_T: 178 case IXGBE_DEV_ID_X550EM_A_1G_T: 179 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 180 supported = true; 181 break; 182 default: 183 supported = false; 184 } 185 default: 186 break; 187 } 188 189 if (!supported) 190 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 191 "Device %x does not support flow control autoneg", 192 hw->device_id); 193 return supported; 194 } 195 196 /** 197 * ixgbe_setup_fc_generic - Set up flow control 198 * @hw: pointer to hardware structure 199 * 200 * Called at init time to set up flow control. 201 **/ 202 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 203 { 204 s32 ret_val = IXGBE_SUCCESS; 205 u32 reg = 0, reg_bp = 0; 206 u16 reg_cu = 0; 207 bool locked = false; 208 209 DEBUGFUNC("ixgbe_setup_fc_generic"); 210 211 /* Validate the requested mode */ 212 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 213 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 214 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 215 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 216 goto out; 217 } 218 219 /* 220 * 10gig parts do not have a word in the EEPROM to determine the 221 * default flow control setting, so we explicitly set it to full. 222 */ 223 if (hw->fc.requested_mode == ixgbe_fc_default) 224 hw->fc.requested_mode = ixgbe_fc_full; 225 226 /* 227 * Set up the 1G and 10G flow control advertisement registers so the 228 * HW will be able to do fc autoneg once the cable is plugged in. If 229 * we link at 10G, the 1G advertisement is harmless and vice versa. 230 */ 231 switch (hw->phy.media_type) { 232 case ixgbe_media_type_backplane: 233 /* some MAC's need RMW protection on AUTOC */ 234 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 235 if (ret_val != IXGBE_SUCCESS) 236 goto out; 237 238 /* fall through - only backplane uses autoc */ 239 case ixgbe_media_type_fiber_qsfp: 240 case ixgbe_media_type_fiber: 241 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 242 243 break; 244 case ixgbe_media_type_copper: 245 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 246 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 247 break; 248 default: 249 break; 250 } 251 252 /* 253 * The possible values of fc.requested_mode are: 254 * 0: Flow control is completely disabled 255 * 1: Rx flow control is enabled (we can receive pause frames, 256 * but not send pause frames). 257 * 2: Tx flow control is enabled (we can send pause frames but 258 * we do not support receiving pause frames). 259 * 3: Both Rx and Tx flow control (symmetric) are enabled. 260 * other: Invalid. 261 */ 262 switch (hw->fc.requested_mode) { 263 case ixgbe_fc_none: 264 /* Flow control completely disabled by software override. */ 265 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 266 if (hw->phy.media_type == ixgbe_media_type_backplane) 267 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 268 IXGBE_AUTOC_ASM_PAUSE); 269 else if (hw->phy.media_type == ixgbe_media_type_copper) 270 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 271 break; 272 case ixgbe_fc_tx_pause: 273 /* 274 * Tx Flow control is enabled, and Rx Flow control is 275 * disabled by software override. 276 */ 277 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 278 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 279 if (hw->phy.media_type == ixgbe_media_type_backplane) { 280 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 281 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 282 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 283 reg_cu |= IXGBE_TAF_ASM_PAUSE; 284 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 285 } 286 break; 287 case ixgbe_fc_rx_pause: 288 /* 289 * Rx Flow control is enabled and Tx Flow control is 290 * disabled by software override. Since there really 291 * isn't a way to advertise that we are capable of RX 292 * Pause ONLY, we will advertise that we support both 293 * symmetric and asymmetric Rx PAUSE, as such we fall 294 * through to the fc_full statement. Later, we will 295 * disable the adapter's ability to send PAUSE frames. 296 */ 297 case ixgbe_fc_full: 298 /* Flow control (both Rx and Tx) is enabled by SW override. */ 299 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 300 if (hw->phy.media_type == ixgbe_media_type_backplane) 301 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 302 IXGBE_AUTOC_ASM_PAUSE; 303 else if (hw->phy.media_type == ixgbe_media_type_copper) 304 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 305 break; 306 default: 307 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 308 "Flow control param set incorrectly\n"); 309 ret_val = IXGBE_ERR_CONFIG; 310 goto out; 311 break; 312 } 313 314 if (hw->mac.type < ixgbe_mac_X540) { 315 /* 316 * Enable auto-negotiation between the MAC & PHY; 317 * the MAC will advertise clause 37 flow control. 318 */ 319 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 320 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 321 322 /* Disable AN timeout */ 323 if (hw->fc.strict_ieee) 324 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 325 326 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 327 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 328 } 329 330 /* 331 * AUTOC restart handles negotiation of 1G and 10G on backplane 332 * and copper. There is no need to set the PCS1GCTL register. 333 * 334 */ 335 if (hw->phy.media_type == ixgbe_media_type_backplane) { 336 reg_bp |= IXGBE_AUTOC_AN_RESTART; 337 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 338 if (ret_val) 339 goto out; 340 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 341 (ixgbe_device_supports_autoneg_fc(hw))) { 342 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 343 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 344 } 345 346 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 347 out: 348 return ret_val; 349 } 350 351 /** 352 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 353 * @hw: pointer to hardware structure 354 * 355 * Starts the hardware by filling the bus info structure and media type, clears 356 * all on chip counters, initializes receive address registers, multicast 357 * table, VLAN filter table, calls routine to set up link and flow control 358 * settings, and leaves transmit and receive units disabled and uninitialized 359 **/ 360 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 361 { 362 s32 ret_val; 363 u32 ctrl_ext; 364 u16 device_caps; 365 366 DEBUGFUNC("ixgbe_start_hw_generic"); 367 368 /* Set the media type */ 369 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 370 371 /* PHY ops initialization must be done in reset_hw() */ 372 373 /* Clear the VLAN filter table */ 374 hw->mac.ops.clear_vfta(hw); 375 376 /* Clear statistics registers */ 377 hw->mac.ops.clear_hw_cntrs(hw); 378 379 /* Set No Snoop Disable */ 380 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 381 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 382 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 383 IXGBE_WRITE_FLUSH(hw); 384 385 /* Setup flow control */ 386 ret_val = ixgbe_setup_fc(hw); 387 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 388 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 389 return ret_val; 390 } 391 392 /* Cache bit indicating need for crosstalk fix */ 393 switch (hw->mac.type) { 394 case ixgbe_mac_82599EB: 395 case ixgbe_mac_X550EM_x: 396 case ixgbe_mac_X550EM_a: 397 hw->mac.ops.get_device_caps(hw, &device_caps); 398 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 399 hw->need_crosstalk_fix = false; 400 else 401 hw->need_crosstalk_fix = true; 402 break; 403 default: 404 hw->need_crosstalk_fix = false; 405 break; 406 } 407 408 /* Clear adapter stopped flag */ 409 hw->adapter_stopped = false; 410 411 return IXGBE_SUCCESS; 412 } 413 414 /** 415 * ixgbe_start_hw_gen2 - Init sequence for common device family 416 * @hw: pointer to hw structure 417 * 418 * Performs the init sequence common to the second generation 419 * of 10 GbE devices. 420 * Devices in the second generation: 421 * 82599 422 * X540 423 **/ 424 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 425 { 426 u32 i; 427 u32 regval; 428 429 /* Clear the rate limiters */ 430 for (i = 0; i < hw->mac.max_tx_queues; i++) { 431 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 432 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 433 } 434 IXGBE_WRITE_FLUSH(hw); 435 436 /* Disable relaxed ordering */ 437 for (i = 0; i < hw->mac.max_tx_queues; i++) { 438 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 439 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 440 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 441 } 442 443 for (i = 0; i < hw->mac.max_rx_queues; i++) { 444 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 445 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 446 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 447 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 448 } 449 450 return IXGBE_SUCCESS; 451 } 452 453 /** 454 * ixgbe_init_hw_generic - Generic hardware initialization 455 * @hw: pointer to hardware structure 456 * 457 * Initialize the hardware by resetting the hardware, filling the bus info 458 * structure and media type, clears all on chip counters, initializes receive 459 * address registers, multicast table, VLAN filter table, calls routine to set 460 * up link and flow control settings, and leaves transmit and receive units 461 * disabled and uninitialized 462 **/ 463 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 464 { 465 s32 status; 466 467 DEBUGFUNC("ixgbe_init_hw_generic"); 468 469 /* Reset the hardware */ 470 status = hw->mac.ops.reset_hw(hw); 471 472 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { 473 /* Start the HW */ 474 status = hw->mac.ops.start_hw(hw); 475 } 476 477 /* Initialize the LED link active for LED blink support */ 478 if (hw->mac.ops.init_led_link_act) 479 hw->mac.ops.init_led_link_act(hw); 480 481 if (status != IXGBE_SUCCESS) 482 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 483 484 return status; 485 } 486 487 /** 488 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 489 * @hw: pointer to hardware structure 490 * 491 * Clears all hardware statistics counters by reading them from the hardware 492 * Statistics counters are clear on read. 493 **/ 494 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 495 { 496 u16 i = 0; 497 498 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 499 500 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 501 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 502 IXGBE_READ_REG(hw, IXGBE_ERRBC); 503 IXGBE_READ_REG(hw, IXGBE_MSPDC); 504 for (i = 0; i < 8; i++) 505 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 506 507 IXGBE_READ_REG(hw, IXGBE_MLFC); 508 IXGBE_READ_REG(hw, IXGBE_MRFC); 509 IXGBE_READ_REG(hw, IXGBE_RLEC); 510 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 511 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 512 if (hw->mac.type >= ixgbe_mac_82599EB) { 513 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 514 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 515 } else { 516 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 517 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 518 } 519 520 for (i = 0; i < 8; i++) { 521 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 522 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 523 if (hw->mac.type >= ixgbe_mac_82599EB) { 524 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 525 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 526 } else { 527 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 528 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 529 } 530 } 531 if (hw->mac.type >= ixgbe_mac_82599EB) 532 for (i = 0; i < 8; i++) 533 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 534 IXGBE_READ_REG(hw, IXGBE_PRC64); 535 IXGBE_READ_REG(hw, IXGBE_PRC127); 536 IXGBE_READ_REG(hw, IXGBE_PRC255); 537 IXGBE_READ_REG(hw, IXGBE_PRC511); 538 IXGBE_READ_REG(hw, IXGBE_PRC1023); 539 IXGBE_READ_REG(hw, IXGBE_PRC1522); 540 IXGBE_READ_REG(hw, IXGBE_GPRC); 541 IXGBE_READ_REG(hw, IXGBE_BPRC); 542 IXGBE_READ_REG(hw, IXGBE_MPRC); 543 IXGBE_READ_REG(hw, IXGBE_GPTC); 544 IXGBE_READ_REG(hw, IXGBE_GORCL); 545 IXGBE_READ_REG(hw, IXGBE_GORCH); 546 IXGBE_READ_REG(hw, IXGBE_GOTCL); 547 IXGBE_READ_REG(hw, IXGBE_GOTCH); 548 if (hw->mac.type == ixgbe_mac_82598EB) 549 for (i = 0; i < 8; i++) 550 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 551 IXGBE_READ_REG(hw, IXGBE_RUC); 552 IXGBE_READ_REG(hw, IXGBE_RFC); 553 IXGBE_READ_REG(hw, IXGBE_ROC); 554 IXGBE_READ_REG(hw, IXGBE_RJC); 555 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 556 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 557 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 558 IXGBE_READ_REG(hw, IXGBE_TORL); 559 IXGBE_READ_REG(hw, IXGBE_TORH); 560 IXGBE_READ_REG(hw, IXGBE_TPR); 561 IXGBE_READ_REG(hw, IXGBE_TPT); 562 IXGBE_READ_REG(hw, IXGBE_PTC64); 563 IXGBE_READ_REG(hw, IXGBE_PTC127); 564 IXGBE_READ_REG(hw, IXGBE_PTC255); 565 IXGBE_READ_REG(hw, IXGBE_PTC511); 566 IXGBE_READ_REG(hw, IXGBE_PTC1023); 567 IXGBE_READ_REG(hw, IXGBE_PTC1522); 568 IXGBE_READ_REG(hw, IXGBE_MPTC); 569 IXGBE_READ_REG(hw, IXGBE_BPTC); 570 for (i = 0; i < 16; i++) { 571 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 572 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 573 if (hw->mac.type >= ixgbe_mac_82599EB) { 574 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 575 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 576 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 577 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 578 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 579 } else { 580 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 581 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 582 } 583 } 584 585 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 586 if (hw->phy.id == 0) 587 ixgbe_identify_phy(hw); 588 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 589 IXGBE_MDIO_PCS_DEV_TYPE, &i); 590 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 591 IXGBE_MDIO_PCS_DEV_TYPE, &i); 592 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 593 IXGBE_MDIO_PCS_DEV_TYPE, &i); 594 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 595 IXGBE_MDIO_PCS_DEV_TYPE, &i); 596 } 597 598 return IXGBE_SUCCESS; 599 } 600 601 /** 602 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 603 * @hw: pointer to hardware structure 604 * @pba_num: stores the part number string from the EEPROM 605 * @pba_num_size: part number string buffer length 606 * 607 * Reads the part number string from the EEPROM. 608 **/ 609 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 610 u32 pba_num_size) 611 { 612 s32 ret_val; 613 u16 data; 614 u16 pba_ptr; 615 u16 offset; 616 u16 length; 617 618 DEBUGFUNC("ixgbe_read_pba_string_generic"); 619 620 if (pba_num == NULL) { 621 DEBUGOUT("PBA string buffer was null\n"); 622 return IXGBE_ERR_INVALID_ARGUMENT; 623 } 624 625 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 626 if (ret_val) { 627 DEBUGOUT("NVM Read Error\n"); 628 return ret_val; 629 } 630 631 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 632 if (ret_val) { 633 DEBUGOUT("NVM Read Error\n"); 634 return ret_val; 635 } 636 637 /* 638 * if data is not ptr guard the PBA must be in legacy format which 639 * means pba_ptr is actually our second data word for the PBA number 640 * and we can decode it into an ascii string 641 */ 642 if (data != IXGBE_PBANUM_PTR_GUARD) { 643 DEBUGOUT("NVM PBA number is not stored as string\n"); 644 645 /* we will need 11 characters to store the PBA */ 646 if (pba_num_size < 11) { 647 DEBUGOUT("PBA string buffer too small\n"); 648 return IXGBE_ERR_NO_SPACE; 649 } 650 651 /* extract hex string from data and pba_ptr */ 652 pba_num[0] = (data >> 12) & 0xF; 653 pba_num[1] = (data >> 8) & 0xF; 654 pba_num[2] = (data >> 4) & 0xF; 655 pba_num[3] = data & 0xF; 656 pba_num[4] = (pba_ptr >> 12) & 0xF; 657 pba_num[5] = (pba_ptr >> 8) & 0xF; 658 pba_num[6] = '-'; 659 pba_num[7] = 0; 660 pba_num[8] = (pba_ptr >> 4) & 0xF; 661 pba_num[9] = pba_ptr & 0xF; 662 663 /* put a null character on the end of our string */ 664 pba_num[10] = '\0'; 665 666 /* switch all the data but the '-' to hex char */ 667 for (offset = 0; offset < 10; offset++) { 668 if (pba_num[offset] < 0xA) 669 pba_num[offset] += '0'; 670 else if (pba_num[offset] < 0x10) 671 pba_num[offset] += 'A' - 0xA; 672 } 673 674 return IXGBE_SUCCESS; 675 } 676 677 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 678 if (ret_val) { 679 DEBUGOUT("NVM Read Error\n"); 680 return ret_val; 681 } 682 683 if (length == 0xFFFF || length == 0) { 684 DEBUGOUT("NVM PBA number section invalid length\n"); 685 return IXGBE_ERR_PBA_SECTION; 686 } 687 688 /* check if pba_num buffer is big enough */ 689 if (pba_num_size < (((u32)length * 2) - 1)) { 690 DEBUGOUT("PBA string buffer too small\n"); 691 return IXGBE_ERR_NO_SPACE; 692 } 693 694 /* trim pba length from start of string */ 695 pba_ptr++; 696 length--; 697 698 for (offset = 0; offset < length; offset++) { 699 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 700 if (ret_val) { 701 DEBUGOUT("NVM Read Error\n"); 702 return ret_val; 703 } 704 pba_num[offset * 2] = (u8)(data >> 8); 705 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 706 } 707 pba_num[offset * 2] = '\0'; 708 709 return IXGBE_SUCCESS; 710 } 711 712 /** 713 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 714 * @hw: pointer to hardware structure 715 * @pba_num: stores the part number from the EEPROM 716 * 717 * Reads the part number from the EEPROM. 718 **/ 719 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 720 { 721 s32 ret_val; 722 u16 data; 723 724 DEBUGFUNC("ixgbe_read_pba_num_generic"); 725 726 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 727 if (ret_val) { 728 DEBUGOUT("NVM Read Error\n"); 729 return ret_val; 730 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 731 DEBUGOUT("NVM Not supported\n"); 732 return IXGBE_NOT_IMPLEMENTED; 733 } 734 *pba_num = (u32)(data << 16); 735 736 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 737 if (ret_val) { 738 DEBUGOUT("NVM Read Error\n"); 739 return ret_val; 740 } 741 *pba_num |= data; 742 743 return IXGBE_SUCCESS; 744 } 745 746 /** 747 * ixgbe_read_pba_raw 748 * @hw: pointer to the HW structure 749 * @eeprom_buf: optional pointer to EEPROM image 750 * @eeprom_buf_size: size of EEPROM image in words 751 * @max_pba_block_size: PBA block size limit 752 * @pba: pointer to output PBA structure 753 * 754 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 755 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 756 * 757 **/ 758 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 759 u32 eeprom_buf_size, u16 max_pba_block_size, 760 struct ixgbe_pba *pba) 761 { 762 s32 ret_val; 763 u16 pba_block_size; 764 765 if (pba == NULL) 766 return IXGBE_ERR_PARAM; 767 768 if (eeprom_buf == NULL) { 769 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 770 &pba->word[0]); 771 if (ret_val) 772 return ret_val; 773 } else { 774 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 775 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 776 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 777 } else { 778 return IXGBE_ERR_PARAM; 779 } 780 } 781 782 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 783 if (pba->pba_block == NULL) 784 return IXGBE_ERR_PARAM; 785 786 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 787 eeprom_buf_size, 788 &pba_block_size); 789 if (ret_val) 790 return ret_val; 791 792 if (pba_block_size > max_pba_block_size) 793 return IXGBE_ERR_PARAM; 794 795 if (eeprom_buf == NULL) { 796 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 797 pba_block_size, 798 pba->pba_block); 799 if (ret_val) 800 return ret_val; 801 } else { 802 if (eeprom_buf_size > (u32)(pba->word[1] + 803 pba_block_size)) { 804 memcpy(pba->pba_block, 805 &eeprom_buf[pba->word[1]], 806 pba_block_size * sizeof(u16)); 807 } else { 808 return IXGBE_ERR_PARAM; 809 } 810 } 811 } 812 813 return IXGBE_SUCCESS; 814 } 815 816 /** 817 * ixgbe_write_pba_raw 818 * @hw: pointer to the HW structure 819 * @eeprom_buf: optional pointer to EEPROM image 820 * @eeprom_buf_size: size of EEPROM image in words 821 * @pba: pointer to PBA structure 822 * 823 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 824 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 825 * 826 **/ 827 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 828 u32 eeprom_buf_size, struct ixgbe_pba *pba) 829 { 830 s32 ret_val; 831 832 if (pba == NULL) 833 return IXGBE_ERR_PARAM; 834 835 if (eeprom_buf == NULL) { 836 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 837 &pba->word[0]); 838 if (ret_val) 839 return ret_val; 840 } else { 841 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 842 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 843 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 844 } else { 845 return IXGBE_ERR_PARAM; 846 } 847 } 848 849 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 850 if (pba->pba_block == NULL) 851 return IXGBE_ERR_PARAM; 852 853 if (eeprom_buf == NULL) { 854 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 855 pba->pba_block[0], 856 pba->pba_block); 857 if (ret_val) 858 return ret_val; 859 } else { 860 if (eeprom_buf_size > (u32)(pba->word[1] + 861 pba->pba_block[0])) { 862 memcpy(&eeprom_buf[pba->word[1]], 863 pba->pba_block, 864 pba->pba_block[0] * sizeof(u16)); 865 } else { 866 return IXGBE_ERR_PARAM; 867 } 868 } 869 } 870 871 return IXGBE_SUCCESS; 872 } 873 874 /** 875 * ixgbe_get_pba_block_size 876 * @hw: pointer to the HW structure 877 * @eeprom_buf: optional pointer to EEPROM image 878 * @eeprom_buf_size: size of EEPROM image in words 879 * @pba_data_size: pointer to output variable 880 * 881 * Returns the size of the PBA block in words. Function operates on EEPROM 882 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 883 * EEPROM device. 884 * 885 **/ 886 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 887 u32 eeprom_buf_size, u16 *pba_block_size) 888 { 889 s32 ret_val; 890 u16 pba_word[2]; 891 u16 length; 892 893 DEBUGFUNC("ixgbe_get_pba_block_size"); 894 895 if (eeprom_buf == NULL) { 896 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 897 &pba_word[0]); 898 if (ret_val) 899 return ret_val; 900 } else { 901 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 902 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 903 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 904 } else { 905 return IXGBE_ERR_PARAM; 906 } 907 } 908 909 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 910 if (eeprom_buf == NULL) { 911 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 912 &length); 913 if (ret_val) 914 return ret_val; 915 } else { 916 if (eeprom_buf_size > pba_word[1]) 917 length = eeprom_buf[pba_word[1] + 0]; 918 else 919 return IXGBE_ERR_PARAM; 920 } 921 922 if (length == 0xFFFF || length == 0) 923 return IXGBE_ERR_PBA_SECTION; 924 } else { 925 /* PBA number in legacy format, there is no PBA Block. */ 926 length = 0; 927 } 928 929 if (pba_block_size != NULL) 930 *pba_block_size = length; 931 932 return IXGBE_SUCCESS; 933 } 934 935 /** 936 * ixgbe_get_mac_addr_generic - Generic get MAC address 937 * @hw: pointer to hardware structure 938 * @mac_addr: Adapter MAC address 939 * 940 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 941 * A reset of the adapter must be performed prior to calling this function 942 * in order for the MAC address to have been loaded from the EEPROM into RAR0 943 **/ 944 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 945 { 946 u32 rar_high; 947 u32 rar_low; 948 u16 i; 949 950 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 951 952 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 953 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 954 955 for (i = 0; i < 4; i++) 956 mac_addr[i] = (u8)(rar_low >> (i*8)); 957 958 for (i = 0; i < 2; i++) 959 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 960 961 return IXGBE_SUCCESS; 962 } 963 964 /** 965 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 966 * @hw: pointer to hardware structure 967 * @link_status: the link status returned by the PCI config space 968 * 969 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 970 **/ 971 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 972 { 973 struct ixgbe_mac_info *mac = &hw->mac; 974 975 if (hw->bus.type == ixgbe_bus_type_unknown) 976 hw->bus.type = ixgbe_bus_type_pci_express; 977 978 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 979 case IXGBE_PCI_LINK_WIDTH_1: 980 hw->bus.width = ixgbe_bus_width_pcie_x1; 981 break; 982 case IXGBE_PCI_LINK_WIDTH_2: 983 hw->bus.width = ixgbe_bus_width_pcie_x2; 984 break; 985 case IXGBE_PCI_LINK_WIDTH_4: 986 hw->bus.width = ixgbe_bus_width_pcie_x4; 987 break; 988 case IXGBE_PCI_LINK_WIDTH_8: 989 hw->bus.width = ixgbe_bus_width_pcie_x8; 990 break; 991 default: 992 hw->bus.width = ixgbe_bus_width_unknown; 993 break; 994 } 995 996 switch (link_status & IXGBE_PCI_LINK_SPEED) { 997 case IXGBE_PCI_LINK_SPEED_2500: 998 hw->bus.speed = ixgbe_bus_speed_2500; 999 break; 1000 case IXGBE_PCI_LINK_SPEED_5000: 1001 hw->bus.speed = ixgbe_bus_speed_5000; 1002 break; 1003 case IXGBE_PCI_LINK_SPEED_8000: 1004 hw->bus.speed = ixgbe_bus_speed_8000; 1005 break; 1006 default: 1007 hw->bus.speed = ixgbe_bus_speed_unknown; 1008 break; 1009 } 1010 1011 mac->ops.set_lan_id(hw); 1012 } 1013 1014 /** 1015 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1016 * @hw: pointer to hardware structure 1017 * 1018 * Gets the PCI bus info (speed, width, type) then calls helper function to 1019 * store this data within the ixgbe_hw structure. 1020 **/ 1021 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1022 { 1023 u16 link_status; 1024 1025 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1026 1027 /* Get the negotiated link width and speed from PCI config space */ 1028 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1029 1030 ixgbe_set_pci_config_data_generic(hw, link_status); 1031 1032 return IXGBE_SUCCESS; 1033 } 1034 1035 /** 1036 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1037 * @hw: pointer to the HW structure 1038 * 1039 * Determines the LAN function id by reading memory-mapped registers and swaps 1040 * the port value if requested, and set MAC instance for devices that share 1041 * CS4227. 1042 **/ 1043 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1044 { 1045 struct ixgbe_bus_info *bus = &hw->bus; 1046 u32 reg; 1047 u16 ee_ctrl_4; 1048 1049 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1050 1051 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1052 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1053 bus->lan_id = (u8)bus->func; 1054 1055 /* check for a port swap */ 1056 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1057 if (reg & IXGBE_FACTPS_LFS) 1058 bus->func ^= 0x1; 1059 1060 /* Get MAC instance from EEPROM for configuring CS4227 */ 1061 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1062 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1063 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1064 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1065 } 1066 } 1067 1068 /** 1069 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1070 * @hw: pointer to hardware structure 1071 * 1072 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1073 * disables transmit and receive units. The adapter_stopped flag is used by 1074 * the shared code and drivers to determine if the adapter is in a stopped 1075 * state and should not touch the hardware. 1076 **/ 1077 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1078 { 1079 u32 reg_val; 1080 u16 i; 1081 1082 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1083 1084 /* 1085 * Set the adapter_stopped flag so other driver functions stop touching 1086 * the hardware 1087 */ 1088 hw->adapter_stopped = true; 1089 1090 /* Disable the receive unit */ 1091 ixgbe_disable_rx(hw); 1092 1093 /* Clear interrupt mask to stop interrupts from being generated */ 1094 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1095 1096 /* Clear any pending interrupts, flush previous writes */ 1097 IXGBE_READ_REG(hw, IXGBE_EICR); 1098 1099 /* Disable the transmit unit. Each queue must be disabled. */ 1100 for (i = 0; i < hw->mac.max_tx_queues; i++) 1101 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1102 1103 /* Disable the receive unit by stopping each queue */ 1104 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1105 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1106 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1107 reg_val |= IXGBE_RXDCTL_SWFLSH; 1108 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1109 } 1110 1111 /* flush all queues disables */ 1112 IXGBE_WRITE_FLUSH(hw); 1113 msec_delay(2); 1114 1115 /* 1116 * Prevent the PCI-E bus from hanging by disabling PCI-E master 1117 * access and verify no pending requests 1118 */ 1119 return ixgbe_disable_pcie_master(hw); 1120 } 1121 1122 /** 1123 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1124 * @hw: pointer to hardware structure 1125 * 1126 * Store the index for the link active LED. This will be used to support 1127 * blinking the LED. 1128 **/ 1129 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1130 { 1131 struct ixgbe_mac_info *mac = &hw->mac; 1132 u32 led_reg, led_mode; 1133 u8 i; 1134 1135 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1136 1137 /* Get LED link active from the LEDCTL register */ 1138 for (i = 0; i < 4; i++) { 1139 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1140 1141 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1142 IXGBE_LED_LINK_ACTIVE) { 1143 mac->led_link_act = i; 1144 return IXGBE_SUCCESS; 1145 } 1146 } 1147 1148 /* 1149 * If LEDCTL register does not have the LED link active set, then use 1150 * known MAC defaults. 1151 */ 1152 switch (hw->mac.type) { 1153 case ixgbe_mac_X550EM_a: 1154 case ixgbe_mac_X550EM_x: 1155 mac->led_link_act = 1; 1156 break; 1157 default: 1158 mac->led_link_act = 2; 1159 } 1160 return IXGBE_SUCCESS; 1161 } 1162 1163 /** 1164 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1165 * @hw: pointer to hardware structure 1166 * @index: led number to turn on 1167 **/ 1168 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1169 { 1170 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1171 1172 DEBUGFUNC("ixgbe_led_on_generic"); 1173 1174 if (index > 3) 1175 return IXGBE_ERR_PARAM; 1176 1177 /* To turn on the LED, set mode to ON. */ 1178 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1179 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1180 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1181 IXGBE_WRITE_FLUSH(hw); 1182 1183 return IXGBE_SUCCESS; 1184 } 1185 1186 /** 1187 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1188 * @hw: pointer to hardware structure 1189 * @index: led number to turn off 1190 **/ 1191 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1192 { 1193 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1194 1195 DEBUGFUNC("ixgbe_led_off_generic"); 1196 1197 if (index > 3) 1198 return IXGBE_ERR_PARAM; 1199 1200 /* To turn off the LED, set mode to OFF. */ 1201 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1202 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1203 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1204 IXGBE_WRITE_FLUSH(hw); 1205 1206 return IXGBE_SUCCESS; 1207 } 1208 1209 /** 1210 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1211 * @hw: pointer to hardware structure 1212 * 1213 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1214 * ixgbe_hw struct in order to set up EEPROM access. 1215 **/ 1216 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1217 { 1218 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1219 u32 eec; 1220 u16 eeprom_size; 1221 1222 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1223 1224 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1225 eeprom->type = ixgbe_eeprom_none; 1226 /* Set default semaphore delay to 10ms which is a well 1227 * tested value */ 1228 eeprom->semaphore_delay = 10; 1229 /* Clear EEPROM page size, it will be initialized as needed */ 1230 eeprom->word_page_size = 0; 1231 1232 /* 1233 * Check for EEPROM present first. 1234 * If not present leave as none 1235 */ 1236 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1237 if (eec & IXGBE_EEC_PRES) { 1238 eeprom->type = ixgbe_eeprom_spi; 1239 1240 /* 1241 * SPI EEPROM is assumed here. This code would need to 1242 * change if a future EEPROM is not SPI. 1243 */ 1244 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1245 IXGBE_EEC_SIZE_SHIFT); 1246 eeprom->word_size = 1 << (eeprom_size + 1247 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1248 } 1249 1250 if (eec & IXGBE_EEC_ADDR_SIZE) 1251 eeprom->address_bits = 16; 1252 else 1253 eeprom->address_bits = 8; 1254 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1255 "%d\n", eeprom->type, eeprom->word_size, 1256 eeprom->address_bits); 1257 } 1258 1259 return IXGBE_SUCCESS; 1260 } 1261 1262 /** 1263 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1264 * @hw: pointer to hardware structure 1265 * @offset: offset within the EEPROM to write 1266 * @words: number of word(s) 1267 * @data: 16 bit word(s) to write to EEPROM 1268 * 1269 * Reads 16 bit word(s) from EEPROM through bit-bang method 1270 **/ 1271 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1272 u16 words, u16 *data) 1273 { 1274 s32 status = IXGBE_SUCCESS; 1275 u16 i, count; 1276 1277 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1278 1279 hw->eeprom.ops.init_params(hw); 1280 1281 if (words == 0) { 1282 status = IXGBE_ERR_INVALID_ARGUMENT; 1283 goto out; 1284 } 1285 1286 if (offset + words > hw->eeprom.word_size) { 1287 status = IXGBE_ERR_EEPROM; 1288 goto out; 1289 } 1290 1291 /* 1292 * The EEPROM page size cannot be queried from the chip. We do lazy 1293 * initialization. It is worth to do that when we write large buffer. 1294 */ 1295 if ((hw->eeprom.word_page_size == 0) && 1296 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1297 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1298 1299 /* 1300 * We cannot hold synchronization semaphores for too long 1301 * to avoid other entity starvation. However it is more efficient 1302 * to read in bursts than synchronizing access for each word. 1303 */ 1304 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1305 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1306 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1307 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1308 count, &data[i]); 1309 1310 if (status != IXGBE_SUCCESS) 1311 break; 1312 } 1313 1314 out: 1315 return status; 1316 } 1317 1318 /** 1319 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1320 * @hw: pointer to hardware structure 1321 * @offset: offset within the EEPROM to be written to 1322 * @words: number of word(s) 1323 * @data: 16 bit word(s) to be written to the EEPROM 1324 * 1325 * If ixgbe_eeprom_update_checksum is not called after this function, the 1326 * EEPROM will most likely contain an invalid checksum. 1327 **/ 1328 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1329 u16 words, u16 *data) 1330 { 1331 s32 status; 1332 u16 word; 1333 u16 page_size; 1334 u16 i; 1335 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1336 1337 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1338 1339 /* Prepare the EEPROM for writing */ 1340 status = ixgbe_acquire_eeprom(hw); 1341 1342 if (status == IXGBE_SUCCESS) { 1343 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1344 ixgbe_release_eeprom(hw); 1345 status = IXGBE_ERR_EEPROM; 1346 } 1347 } 1348 1349 if (status == IXGBE_SUCCESS) { 1350 for (i = 0; i < words; i++) { 1351 ixgbe_standby_eeprom(hw); 1352 1353 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1354 ixgbe_shift_out_eeprom_bits(hw, 1355 IXGBE_EEPROM_WREN_OPCODE_SPI, 1356 IXGBE_EEPROM_OPCODE_BITS); 1357 1358 ixgbe_standby_eeprom(hw); 1359 1360 /* 1361 * Some SPI eeproms use the 8th address bit embedded 1362 * in the opcode 1363 */ 1364 if ((hw->eeprom.address_bits == 8) && 1365 ((offset + i) >= 128)) 1366 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1367 1368 /* Send the Write command (8-bit opcode + addr) */ 1369 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1370 IXGBE_EEPROM_OPCODE_BITS); 1371 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1372 hw->eeprom.address_bits); 1373 1374 page_size = hw->eeprom.word_page_size; 1375 1376 /* Send the data in burst via SPI*/ 1377 do { 1378 word = data[i]; 1379 word = (word >> 8) | (word << 8); 1380 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1381 1382 if (page_size == 0) 1383 break; 1384 1385 /* do not wrap around page */ 1386 if (((offset + i) & (page_size - 1)) == 1387 (page_size - 1)) 1388 break; 1389 } while (++i < words); 1390 1391 ixgbe_standby_eeprom(hw); 1392 msec_delay(10); 1393 } 1394 /* Done with writing - release the EEPROM */ 1395 ixgbe_release_eeprom(hw); 1396 } 1397 1398 return status; 1399 } 1400 1401 /** 1402 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1403 * @hw: pointer to hardware structure 1404 * @offset: offset within the EEPROM to be written to 1405 * @data: 16 bit word to be written to the EEPROM 1406 * 1407 * If ixgbe_eeprom_update_checksum is not called after this function, the 1408 * EEPROM will most likely contain an invalid checksum. 1409 **/ 1410 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1411 { 1412 s32 status; 1413 1414 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1415 1416 hw->eeprom.ops.init_params(hw); 1417 1418 if (offset >= hw->eeprom.word_size) { 1419 status = IXGBE_ERR_EEPROM; 1420 goto out; 1421 } 1422 1423 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1424 1425 out: 1426 return status; 1427 } 1428 1429 /** 1430 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1431 * @hw: pointer to hardware structure 1432 * @offset: offset within the EEPROM to be read 1433 * @data: read 16 bit words(s) from EEPROM 1434 * @words: number of word(s) 1435 * 1436 * Reads 16 bit word(s) from EEPROM through bit-bang method 1437 **/ 1438 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1439 u16 words, u16 *data) 1440 { 1441 s32 status = IXGBE_SUCCESS; 1442 u16 i, count; 1443 1444 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1445 1446 hw->eeprom.ops.init_params(hw); 1447 1448 if (words == 0) { 1449 status = IXGBE_ERR_INVALID_ARGUMENT; 1450 goto out; 1451 } 1452 1453 if (offset + words > hw->eeprom.word_size) { 1454 status = IXGBE_ERR_EEPROM; 1455 goto out; 1456 } 1457 1458 /* 1459 * We cannot hold synchronization semaphores for too long 1460 * to avoid other entity starvation. However it is more efficient 1461 * to read in bursts than synchronizing access for each word. 1462 */ 1463 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1464 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1465 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1466 1467 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1468 count, &data[i]); 1469 1470 if (status != IXGBE_SUCCESS) 1471 break; 1472 } 1473 1474 out: 1475 return status; 1476 } 1477 1478 /** 1479 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1480 * @hw: pointer to hardware structure 1481 * @offset: offset within the EEPROM to be read 1482 * @words: number of word(s) 1483 * @data: read 16 bit word(s) from EEPROM 1484 * 1485 * Reads 16 bit word(s) from EEPROM through bit-bang method 1486 **/ 1487 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1488 u16 words, u16 *data) 1489 { 1490 s32 status; 1491 u16 word_in; 1492 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1493 u16 i; 1494 1495 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1496 1497 /* Prepare the EEPROM for reading */ 1498 status = ixgbe_acquire_eeprom(hw); 1499 1500 if (status == IXGBE_SUCCESS) { 1501 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1502 ixgbe_release_eeprom(hw); 1503 status = IXGBE_ERR_EEPROM; 1504 } 1505 } 1506 1507 if (status == IXGBE_SUCCESS) { 1508 for (i = 0; i < words; i++) { 1509 ixgbe_standby_eeprom(hw); 1510 /* 1511 * Some SPI eeproms use the 8th address bit embedded 1512 * in the opcode 1513 */ 1514 if ((hw->eeprom.address_bits == 8) && 1515 ((offset + i) >= 128)) 1516 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1517 1518 /* Send the READ command (opcode + addr) */ 1519 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1520 IXGBE_EEPROM_OPCODE_BITS); 1521 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1522 hw->eeprom.address_bits); 1523 1524 /* Read the data. */ 1525 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1526 data[i] = (word_in >> 8) | (word_in << 8); 1527 } 1528 1529 /* End this read operation */ 1530 ixgbe_release_eeprom(hw); 1531 } 1532 1533 return status; 1534 } 1535 1536 /** 1537 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1538 * @hw: pointer to hardware structure 1539 * @offset: offset within the EEPROM to be read 1540 * @data: read 16 bit value from EEPROM 1541 * 1542 * Reads 16 bit value from EEPROM through bit-bang method 1543 **/ 1544 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1545 u16 *data) 1546 { 1547 s32 status; 1548 1549 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1550 1551 hw->eeprom.ops.init_params(hw); 1552 1553 if (offset >= hw->eeprom.word_size) { 1554 status = IXGBE_ERR_EEPROM; 1555 goto out; 1556 } 1557 1558 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1559 1560 out: 1561 return status; 1562 } 1563 1564 /** 1565 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1566 * @hw: pointer to hardware structure 1567 * @offset: offset of word in the EEPROM to read 1568 * @words: number of word(s) 1569 * @data: 16 bit word(s) from the EEPROM 1570 * 1571 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1572 **/ 1573 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1574 u16 words, u16 *data) 1575 { 1576 u32 eerd; 1577 s32 status = IXGBE_SUCCESS; 1578 u32 i; 1579 1580 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1581 1582 hw->eeprom.ops.init_params(hw); 1583 1584 if (words == 0) { 1585 status = IXGBE_ERR_INVALID_ARGUMENT; 1586 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1587 goto out; 1588 } 1589 1590 if (offset >= hw->eeprom.word_size) { 1591 status = IXGBE_ERR_EEPROM; 1592 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1593 goto out; 1594 } 1595 1596 for (i = 0; i < words; i++) { 1597 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1598 IXGBE_EEPROM_RW_REG_START; 1599 1600 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1601 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1602 1603 if (status == IXGBE_SUCCESS) { 1604 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1605 IXGBE_EEPROM_RW_REG_DATA); 1606 } else { 1607 DEBUGOUT("Eeprom read timed out\n"); 1608 goto out; 1609 } 1610 } 1611 out: 1612 return status; 1613 } 1614 1615 /** 1616 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1617 * @hw: pointer to hardware structure 1618 * @offset: offset within the EEPROM to be used as a scratch pad 1619 * 1620 * Discover EEPROM page size by writing marching data at given offset. 1621 * This function is called only when we are writing a new large buffer 1622 * at given offset so the data would be overwritten anyway. 1623 **/ 1624 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1625 u16 offset) 1626 { 1627 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1628 s32 status = IXGBE_SUCCESS; 1629 u16 i; 1630 1631 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1632 1633 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1634 data[i] = i; 1635 1636 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1637 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1638 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1639 hw->eeprom.word_page_size = 0; 1640 if (status != IXGBE_SUCCESS) 1641 goto out; 1642 1643 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1644 if (status != IXGBE_SUCCESS) 1645 goto out; 1646 1647 /* 1648 * When writing in burst more than the actual page size 1649 * EEPROM address wraps around current page. 1650 */ 1651 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1652 1653 DEBUGOUT1("Detected EEPROM page size = %d words.", 1654 hw->eeprom.word_page_size); 1655 out: 1656 return status; 1657 } 1658 1659 /** 1660 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1661 * @hw: pointer to hardware structure 1662 * @offset: offset of word in the EEPROM to read 1663 * @data: word read from the EEPROM 1664 * 1665 * Reads a 16 bit word from the EEPROM using the EERD register. 1666 **/ 1667 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1668 { 1669 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1670 } 1671 1672 /** 1673 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1674 * @hw: pointer to hardware structure 1675 * @offset: offset of word in the EEPROM to write 1676 * @words: number of word(s) 1677 * @data: word(s) write to the EEPROM 1678 * 1679 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1680 **/ 1681 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1682 u16 words, u16 *data) 1683 { 1684 u32 eewr; 1685 s32 status = IXGBE_SUCCESS; 1686 u16 i; 1687 1688 DEBUGFUNC("ixgbe_write_eewr_generic"); 1689 1690 hw->eeprom.ops.init_params(hw); 1691 1692 if (words == 0) { 1693 status = IXGBE_ERR_INVALID_ARGUMENT; 1694 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1695 goto out; 1696 } 1697 1698 if (offset >= hw->eeprom.word_size) { 1699 status = IXGBE_ERR_EEPROM; 1700 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1701 goto out; 1702 } 1703 1704 for (i = 0; i < words; i++) { 1705 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1706 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1707 IXGBE_EEPROM_RW_REG_START; 1708 1709 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1710 if (status != IXGBE_SUCCESS) { 1711 DEBUGOUT("Eeprom write EEWR timed out\n"); 1712 goto out; 1713 } 1714 1715 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1716 1717 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1718 if (status != IXGBE_SUCCESS) { 1719 DEBUGOUT("Eeprom write EEWR timed out\n"); 1720 goto out; 1721 } 1722 } 1723 1724 out: 1725 return status; 1726 } 1727 1728 /** 1729 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1730 * @hw: pointer to hardware structure 1731 * @offset: offset of word in the EEPROM to write 1732 * @data: word write to the EEPROM 1733 * 1734 * Write a 16 bit word to the EEPROM using the EEWR register. 1735 **/ 1736 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1737 { 1738 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1739 } 1740 1741 /** 1742 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1743 * @hw: pointer to hardware structure 1744 * @ee_reg: EEPROM flag for polling 1745 * 1746 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1747 * read or write is done respectively. 1748 **/ 1749 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1750 { 1751 u32 i; 1752 u32 reg; 1753 s32 status = IXGBE_ERR_EEPROM; 1754 1755 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1756 1757 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1758 if (ee_reg == IXGBE_NVM_POLL_READ) 1759 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1760 else 1761 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1762 1763 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1764 status = IXGBE_SUCCESS; 1765 break; 1766 } 1767 usec_delay(5); 1768 } 1769 1770 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1771 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1772 "EEPROM read/write done polling timed out"); 1773 1774 return status; 1775 } 1776 1777 /** 1778 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1779 * @hw: pointer to hardware structure 1780 * 1781 * Prepares EEPROM for access using bit-bang method. This function should 1782 * be called before issuing a command to the EEPROM. 1783 **/ 1784 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1785 { 1786 s32 status = IXGBE_SUCCESS; 1787 u32 eec; 1788 u32 i; 1789 1790 DEBUGFUNC("ixgbe_acquire_eeprom"); 1791 1792 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1793 != IXGBE_SUCCESS) 1794 status = IXGBE_ERR_SWFW_SYNC; 1795 1796 if (status == IXGBE_SUCCESS) { 1797 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1798 1799 /* Request EEPROM Access */ 1800 eec |= IXGBE_EEC_REQ; 1801 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1802 1803 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1804 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1805 if (eec & IXGBE_EEC_GNT) 1806 break; 1807 usec_delay(5); 1808 } 1809 1810 /* Release if grant not acquired */ 1811 if (!(eec & IXGBE_EEC_GNT)) { 1812 eec &= ~IXGBE_EEC_REQ; 1813 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1814 DEBUGOUT("Could not acquire EEPROM grant\n"); 1815 1816 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1817 status = IXGBE_ERR_EEPROM; 1818 } 1819 1820 /* Setup EEPROM for Read/Write */ 1821 if (status == IXGBE_SUCCESS) { 1822 /* Clear CS and SK */ 1823 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1824 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1825 IXGBE_WRITE_FLUSH(hw); 1826 usec_delay(1); 1827 } 1828 } 1829 return status; 1830 } 1831 1832 /** 1833 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1834 * @hw: pointer to hardware structure 1835 * 1836 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1837 **/ 1838 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1839 { 1840 s32 status = IXGBE_ERR_EEPROM; 1841 u32 timeout = 2000; 1842 u32 i; 1843 u32 swsm; 1844 1845 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1846 1847 1848 /* Get SMBI software semaphore between device drivers first */ 1849 for (i = 0; i < timeout; i++) { 1850 /* 1851 * If the SMBI bit is 0 when we read it, then the bit will be 1852 * set and we have the semaphore 1853 */ 1854 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1855 if (!(swsm & IXGBE_SWSM_SMBI)) { 1856 status = IXGBE_SUCCESS; 1857 break; 1858 } 1859 usec_delay(50); 1860 } 1861 1862 if (i == timeout) { 1863 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1864 "not granted.\n"); 1865 /* 1866 * this release is particularly important because our attempts 1867 * above to get the semaphore may have succeeded, and if there 1868 * was a timeout, we should unconditionally clear the semaphore 1869 * bits to free the driver to make progress 1870 */ 1871 ixgbe_release_eeprom_semaphore(hw); 1872 1873 usec_delay(50); 1874 /* 1875 * one last try 1876 * If the SMBI bit is 0 when we read it, then the bit will be 1877 * set and we have the semaphore 1878 */ 1879 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1880 if (!(swsm & IXGBE_SWSM_SMBI)) 1881 status = IXGBE_SUCCESS; 1882 } 1883 1884 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1885 if (status == IXGBE_SUCCESS) { 1886 for (i = 0; i < timeout; i++) { 1887 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1888 1889 /* Set the SW EEPROM semaphore bit to request access */ 1890 swsm |= IXGBE_SWSM_SWESMBI; 1891 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1892 1893 /* 1894 * If we set the bit successfully then we got the 1895 * semaphore. 1896 */ 1897 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1898 if (swsm & IXGBE_SWSM_SWESMBI) 1899 break; 1900 1901 usec_delay(50); 1902 } 1903 1904 /* 1905 * Release semaphores and return error if SW EEPROM semaphore 1906 * was not granted because we don't have access to the EEPROM 1907 */ 1908 if (i >= timeout) { 1909 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1910 "SWESMBI Software EEPROM semaphore not granted.\n"); 1911 ixgbe_release_eeprom_semaphore(hw); 1912 status = IXGBE_ERR_EEPROM; 1913 } 1914 } else { 1915 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1916 "Software semaphore SMBI between device drivers " 1917 "not granted.\n"); 1918 } 1919 1920 return status; 1921 } 1922 1923 /** 1924 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1925 * @hw: pointer to hardware structure 1926 * 1927 * This function clears hardware semaphore bits. 1928 **/ 1929 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1930 { 1931 u32 swsm; 1932 1933 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1934 1935 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1936 1937 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1938 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1939 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1940 IXGBE_WRITE_FLUSH(hw); 1941 } 1942 1943 /** 1944 * ixgbe_ready_eeprom - Polls for EEPROM ready 1945 * @hw: pointer to hardware structure 1946 **/ 1947 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1948 { 1949 s32 status = IXGBE_SUCCESS; 1950 u16 i; 1951 u8 spi_stat_reg; 1952 1953 DEBUGFUNC("ixgbe_ready_eeprom"); 1954 1955 /* 1956 * Read "Status Register" repeatedly until the LSB is cleared. The 1957 * EEPROM will signal that the command has been completed by clearing 1958 * bit 0 of the internal status register. If it's not cleared within 1959 * 5 milliseconds, then error out. 1960 */ 1961 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1962 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1963 IXGBE_EEPROM_OPCODE_BITS); 1964 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1965 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1966 break; 1967 1968 usec_delay(5); 1969 ixgbe_standby_eeprom(hw); 1970 }; 1971 1972 /* 1973 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1974 * devices (and only 0-5mSec on 5V devices) 1975 */ 1976 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1977 DEBUGOUT("SPI EEPROM Status error\n"); 1978 status = IXGBE_ERR_EEPROM; 1979 } 1980 1981 return status; 1982 } 1983 1984 /** 1985 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1986 * @hw: pointer to hardware structure 1987 **/ 1988 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1989 { 1990 u32 eec; 1991 1992 DEBUGFUNC("ixgbe_standby_eeprom"); 1993 1994 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1995 1996 /* Toggle CS to flush commands */ 1997 eec |= IXGBE_EEC_CS; 1998 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1999 IXGBE_WRITE_FLUSH(hw); 2000 usec_delay(1); 2001 eec &= ~IXGBE_EEC_CS; 2002 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2003 IXGBE_WRITE_FLUSH(hw); 2004 usec_delay(1); 2005 } 2006 2007 /** 2008 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2009 * @hw: pointer to hardware structure 2010 * @data: data to send to the EEPROM 2011 * @count: number of bits to shift out 2012 **/ 2013 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2014 u16 count) 2015 { 2016 u32 eec; 2017 u32 mask; 2018 u32 i; 2019 2020 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2021 2022 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2023 2024 /* 2025 * Mask is used to shift "count" bits of "data" out to the EEPROM 2026 * one bit at a time. Determine the starting bit based on count 2027 */ 2028 mask = 0x01 << (count - 1); 2029 2030 for (i = 0; i < count; i++) { 2031 /* 2032 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2033 * "1", and then raising and then lowering the clock (the SK 2034 * bit controls the clock input to the EEPROM). A "0" is 2035 * shifted out to the EEPROM by setting "DI" to "0" and then 2036 * raising and then lowering the clock. 2037 */ 2038 if (data & mask) 2039 eec |= IXGBE_EEC_DI; 2040 else 2041 eec &= ~IXGBE_EEC_DI; 2042 2043 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2044 IXGBE_WRITE_FLUSH(hw); 2045 2046 usec_delay(1); 2047 2048 ixgbe_raise_eeprom_clk(hw, &eec); 2049 ixgbe_lower_eeprom_clk(hw, &eec); 2050 2051 /* 2052 * Shift mask to signify next bit of data to shift in to the 2053 * EEPROM 2054 */ 2055 mask = mask >> 1; 2056 }; 2057 2058 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2059 eec &= ~IXGBE_EEC_DI; 2060 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2061 IXGBE_WRITE_FLUSH(hw); 2062 } 2063 2064 /** 2065 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2066 * @hw: pointer to hardware structure 2067 * @count: number of bits to shift 2068 **/ 2069 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2070 { 2071 u32 eec; 2072 u32 i; 2073 u16 data = 0; 2074 2075 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2076 2077 /* 2078 * In order to read a register from the EEPROM, we need to shift 2079 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2080 * the clock input to the EEPROM (setting the SK bit), and then reading 2081 * the value of the "DO" bit. During this "shifting in" process the 2082 * "DI" bit should always be clear. 2083 */ 2084 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2085 2086 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2087 2088 for (i = 0; i < count; i++) { 2089 data = data << 1; 2090 ixgbe_raise_eeprom_clk(hw, &eec); 2091 2092 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2093 2094 eec &= ~(IXGBE_EEC_DI); 2095 if (eec & IXGBE_EEC_DO) 2096 data |= 1; 2097 2098 ixgbe_lower_eeprom_clk(hw, &eec); 2099 } 2100 2101 return data; 2102 } 2103 2104 /** 2105 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2106 * @hw: pointer to hardware structure 2107 * @eec: EEC register's current value 2108 **/ 2109 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2110 { 2111 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2112 2113 /* 2114 * Raise the clock input to the EEPROM 2115 * (setting the SK bit), then delay 2116 */ 2117 *eec = *eec | IXGBE_EEC_SK; 2118 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2119 IXGBE_WRITE_FLUSH(hw); 2120 usec_delay(1); 2121 } 2122 2123 /** 2124 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2125 * @hw: pointer to hardware structure 2126 * @eec: EEC's current value 2127 **/ 2128 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2129 { 2130 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2131 2132 /* 2133 * Lower the clock input to the EEPROM (clearing the SK bit), then 2134 * delay 2135 */ 2136 *eec = *eec & ~IXGBE_EEC_SK; 2137 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2138 IXGBE_WRITE_FLUSH(hw); 2139 usec_delay(1); 2140 } 2141 2142 /** 2143 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2144 * @hw: pointer to hardware structure 2145 **/ 2146 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2147 { 2148 u32 eec; 2149 2150 DEBUGFUNC("ixgbe_release_eeprom"); 2151 2152 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2153 2154 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2155 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2156 2157 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2158 IXGBE_WRITE_FLUSH(hw); 2159 2160 usec_delay(1); 2161 2162 /* Stop requesting EEPROM access */ 2163 eec &= ~IXGBE_EEC_REQ; 2164 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2165 2166 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2167 2168 /* Delay before attempt to obtain semaphore again to allow FW access */ 2169 msec_delay(hw->eeprom.semaphore_delay); 2170 } 2171 2172 /** 2173 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2174 * @hw: pointer to hardware structure 2175 * 2176 * Returns a negative error code on error, or the 16-bit checksum 2177 **/ 2178 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2179 { 2180 u16 i; 2181 u16 j; 2182 u16 checksum = 0; 2183 u16 length = 0; 2184 u16 pointer = 0; 2185 u16 word = 0; 2186 2187 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2188 2189 /* Include 0x0-0x3F in the checksum */ 2190 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2191 if (hw->eeprom.ops.read(hw, i, &word)) { 2192 DEBUGOUT("EEPROM read failed\n"); 2193 return IXGBE_ERR_EEPROM; 2194 } 2195 checksum += word; 2196 } 2197 2198 /* Include all data from pointers except for the fw pointer */ 2199 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2200 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2201 DEBUGOUT("EEPROM read failed\n"); 2202 return IXGBE_ERR_EEPROM; 2203 } 2204 2205 /* If the pointer seems invalid */ 2206 if (pointer == 0xFFFF || pointer == 0) 2207 continue; 2208 2209 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2210 DEBUGOUT("EEPROM read failed\n"); 2211 return IXGBE_ERR_EEPROM; 2212 } 2213 2214 if (length == 0xFFFF || length == 0) 2215 continue; 2216 2217 for (j = pointer + 1; j <= pointer + length; j++) { 2218 if (hw->eeprom.ops.read(hw, j, &word)) { 2219 DEBUGOUT("EEPROM read failed\n"); 2220 return IXGBE_ERR_EEPROM; 2221 } 2222 checksum += word; 2223 } 2224 } 2225 2226 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2227 2228 return (s32)checksum; 2229 } 2230 2231 /** 2232 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2233 * @hw: pointer to hardware structure 2234 * @checksum_val: calculated checksum 2235 * 2236 * Performs checksum calculation and validates the EEPROM checksum. If the 2237 * caller does not need checksum_val, the value can be NULL. 2238 **/ 2239 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2240 u16 *checksum_val) 2241 { 2242 s32 status; 2243 u16 checksum; 2244 u16 read_checksum = 0; 2245 2246 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2247 2248 /* Read the first word from the EEPROM. If this times out or fails, do 2249 * not continue or we could be in for a very long wait while every 2250 * EEPROM read fails 2251 */ 2252 status = hw->eeprom.ops.read(hw, 0, &checksum); 2253 if (status) { 2254 DEBUGOUT("EEPROM read failed\n"); 2255 return status; 2256 } 2257 2258 status = hw->eeprom.ops.calc_checksum(hw); 2259 if (status < 0) 2260 return status; 2261 2262 checksum = (u16)(status & 0xffff); 2263 2264 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2265 if (status) { 2266 DEBUGOUT("EEPROM read failed\n"); 2267 return status; 2268 } 2269 2270 /* Verify read checksum from EEPROM is the same as 2271 * calculated checksum 2272 */ 2273 if (read_checksum != checksum) 2274 status = IXGBE_ERR_EEPROM_CHECKSUM; 2275 2276 /* If the user cares, return the calculated checksum */ 2277 if (checksum_val) 2278 *checksum_val = checksum; 2279 2280 return status; 2281 } 2282 2283 /** 2284 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2285 * @hw: pointer to hardware structure 2286 **/ 2287 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2288 { 2289 s32 status; 2290 u16 checksum; 2291 2292 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2293 2294 /* Read the first word from the EEPROM. If this times out or fails, do 2295 * not continue or we could be in for a very long wait while every 2296 * EEPROM read fails 2297 */ 2298 status = hw->eeprom.ops.read(hw, 0, &checksum); 2299 if (status) { 2300 DEBUGOUT("EEPROM read failed\n"); 2301 return status; 2302 } 2303 2304 status = hw->eeprom.ops.calc_checksum(hw); 2305 if (status < 0) 2306 return status; 2307 2308 checksum = (u16)(status & 0xffff); 2309 2310 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2311 2312 return status; 2313 } 2314 2315 /** 2316 * ixgbe_validate_mac_addr - Validate MAC address 2317 * @mac_addr: pointer to MAC address. 2318 * 2319 * Tests a MAC address to ensure it is a valid Individual Address. 2320 **/ 2321 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2322 { 2323 s32 status = IXGBE_SUCCESS; 2324 2325 DEBUGFUNC("ixgbe_validate_mac_addr"); 2326 2327 /* Make sure it is not a multicast address */ 2328 if (IXGBE_IS_MULTICAST(mac_addr)) { 2329 status = IXGBE_ERR_INVALID_MAC_ADDR; 2330 /* Not a broadcast address */ 2331 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2332 status = IXGBE_ERR_INVALID_MAC_ADDR; 2333 /* Reject the zero address */ 2334 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2335 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2336 status = IXGBE_ERR_INVALID_MAC_ADDR; 2337 } 2338 return status; 2339 } 2340 2341 /** 2342 * ixgbe_set_rar_generic - Set Rx address register 2343 * @hw: pointer to hardware structure 2344 * @index: Receive address register to write 2345 * @addr: Address to put into receive address register 2346 * @vmdq: VMDq "set" or "pool" index 2347 * @enable_addr: set flag that address is active 2348 * 2349 * Puts an ethernet address into a receive address register. 2350 **/ 2351 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2352 u32 enable_addr) 2353 { 2354 u32 rar_low, rar_high; 2355 u32 rar_entries = hw->mac.num_rar_entries; 2356 2357 DEBUGFUNC("ixgbe_set_rar_generic"); 2358 2359 /* Make sure we are using a valid rar index range */ 2360 if (index >= rar_entries) { 2361 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2362 "RAR index %d is out of range.\n", index); 2363 return IXGBE_ERR_INVALID_ARGUMENT; 2364 } 2365 2366 /* setup VMDq pool selection before this RAR gets enabled */ 2367 hw->mac.ops.set_vmdq(hw, index, vmdq); 2368 2369 /* 2370 * HW expects these in little endian so we reverse the byte 2371 * order from network order (big endian) to little endian 2372 */ 2373 rar_low = ((u32)addr[0] | 2374 ((u32)addr[1] << 8) | 2375 ((u32)addr[2] << 16) | 2376 ((u32)addr[3] << 24)); 2377 /* 2378 * Some parts put the VMDq setting in the extra RAH bits, 2379 * so save everything except the lower 16 bits that hold part 2380 * of the address and the address valid bit. 2381 */ 2382 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2383 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2384 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2385 2386 if (enable_addr != 0) 2387 rar_high |= IXGBE_RAH_AV; 2388 2389 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2390 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2391 2392 return IXGBE_SUCCESS; 2393 } 2394 2395 /** 2396 * ixgbe_clear_rar_generic - Remove Rx address register 2397 * @hw: pointer to hardware structure 2398 * @index: Receive address register to write 2399 * 2400 * Clears an ethernet address from a receive address register. 2401 **/ 2402 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2403 { 2404 u32 rar_high; 2405 u32 rar_entries = hw->mac.num_rar_entries; 2406 2407 DEBUGFUNC("ixgbe_clear_rar_generic"); 2408 2409 /* Make sure we are using a valid rar index range */ 2410 if (index >= rar_entries) { 2411 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2412 "RAR index %d is out of range.\n", index); 2413 return IXGBE_ERR_INVALID_ARGUMENT; 2414 } 2415 2416 /* 2417 * Some parts put the VMDq setting in the extra RAH bits, 2418 * so save everything except the lower 16 bits that hold part 2419 * of the address and the address valid bit. 2420 */ 2421 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2422 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2423 2424 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2425 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2426 2427 /* clear VMDq pool/queue selection for this RAR */ 2428 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2429 2430 return IXGBE_SUCCESS; 2431 } 2432 2433 /** 2434 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2435 * @hw: pointer to hardware structure 2436 * 2437 * Places the MAC address in receive address register 0 and clears the rest 2438 * of the receive address registers. Clears the multicast table. Assumes 2439 * the receiver is in reset when the routine is called. 2440 **/ 2441 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2442 { 2443 u32 i; 2444 u32 rar_entries = hw->mac.num_rar_entries; 2445 2446 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2447 2448 /* 2449 * If the current mac address is valid, assume it is a software override 2450 * to the permanent address. 2451 * Otherwise, use the permanent address from the eeprom. 2452 */ 2453 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2454 IXGBE_ERR_INVALID_MAC_ADDR) { 2455 /* Get the MAC address from the RAR0 for later reference */ 2456 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2457 2458 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2459 hw->mac.addr[0], hw->mac.addr[1], 2460 hw->mac.addr[2]); 2461 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2462 hw->mac.addr[4], hw->mac.addr[5]); 2463 } else { 2464 /* Setup the receive address. */ 2465 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2466 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2467 hw->mac.addr[0], hw->mac.addr[1], 2468 hw->mac.addr[2]); 2469 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2470 hw->mac.addr[4], hw->mac.addr[5]); 2471 2472 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2473 } 2474 2475 /* clear VMDq pool/queue selection for RAR 0 */ 2476 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2477 2478 hw->addr_ctrl.overflow_promisc = 0; 2479 2480 hw->addr_ctrl.rar_used_count = 1; 2481 2482 /* Zero out the other receive addresses. */ 2483 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2484 for (i = 1; i < rar_entries; i++) { 2485 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2486 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2487 } 2488 2489 /* Clear the MTA */ 2490 hw->addr_ctrl.mta_in_use = 0; 2491 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2492 2493 DEBUGOUT(" Clearing MTA\n"); 2494 for (i = 0; i < hw->mac.mcft_size; i++) 2495 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2496 2497 ixgbe_init_uta_tables(hw); 2498 2499 return IXGBE_SUCCESS; 2500 } 2501 2502 /** 2503 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2504 * @hw: pointer to hardware structure 2505 * @addr: new address 2506 * @vmdq: VMDq "set" or "pool" index 2507 * 2508 * Adds it to unused receive address register or goes into promiscuous mode. 2509 **/ 2510 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2511 { 2512 u32 rar_entries = hw->mac.num_rar_entries; 2513 u32 rar; 2514 2515 DEBUGFUNC("ixgbe_add_uc_addr"); 2516 2517 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2518 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2519 2520 /* 2521 * Place this address in the RAR if there is room, 2522 * else put the controller into promiscuous mode 2523 */ 2524 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2525 rar = hw->addr_ctrl.rar_used_count; 2526 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2527 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2528 hw->addr_ctrl.rar_used_count++; 2529 } else { 2530 hw->addr_ctrl.overflow_promisc++; 2531 } 2532 2533 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2534 } 2535 2536 /** 2537 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2538 * @hw: pointer to hardware structure 2539 * @addr_list: the list of new addresses 2540 * @addr_count: number of addresses 2541 * @next: iterator function to walk the address list 2542 * 2543 * The given list replaces any existing list. Clears the secondary addrs from 2544 * receive address registers. Uses unused receive address registers for the 2545 * first secondary addresses, and falls back to promiscuous mode as needed. 2546 * 2547 * Drivers using secondary unicast addresses must set user_set_promisc when 2548 * manually putting the device into promiscuous mode. 2549 **/ 2550 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2551 u32 addr_count, ixgbe_mc_addr_itr next) 2552 { 2553 u8 *addr; 2554 u32 i; 2555 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2556 u32 uc_addr_in_use; 2557 u32 fctrl; 2558 u32 vmdq; 2559 2560 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2561 2562 /* 2563 * Clear accounting of old secondary address list, 2564 * don't count RAR[0] 2565 */ 2566 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2567 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2568 hw->addr_ctrl.overflow_promisc = 0; 2569 2570 /* Zero out the other receive addresses */ 2571 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2572 for (i = 0; i < uc_addr_in_use; i++) { 2573 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2574 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2575 } 2576 2577 /* Add the new addresses */ 2578 for (i = 0; i < addr_count; i++) { 2579 DEBUGOUT(" Adding the secondary addresses:\n"); 2580 addr = next(hw, &addr_list, &vmdq); 2581 ixgbe_add_uc_addr(hw, addr, vmdq); 2582 } 2583 2584 if (hw->addr_ctrl.overflow_promisc) { 2585 /* enable promisc if not already in overflow or set by user */ 2586 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2587 DEBUGOUT(" Entering address overflow promisc mode\n"); 2588 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2589 fctrl |= IXGBE_FCTRL_UPE; 2590 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2591 } 2592 } else { 2593 /* only disable if set by overflow, not by user */ 2594 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2595 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2596 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2597 fctrl &= ~IXGBE_FCTRL_UPE; 2598 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2599 } 2600 } 2601 2602 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2603 return IXGBE_SUCCESS; 2604 } 2605 2606 /** 2607 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2608 * @hw: pointer to hardware structure 2609 * @mc_addr: the multicast address 2610 * 2611 * Extracts the 12 bits, from a multicast address, to determine which 2612 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2613 * incoming rx multicast addresses, to determine the bit-vector to check in 2614 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2615 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2616 * to mc_filter_type. 2617 **/ 2618 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2619 { 2620 u32 vector = 0; 2621 2622 DEBUGFUNC("ixgbe_mta_vector"); 2623 2624 switch (hw->mac.mc_filter_type) { 2625 case 0: /* use bits [47:36] of the address */ 2626 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2627 break; 2628 case 1: /* use bits [46:35] of the address */ 2629 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2630 break; 2631 case 2: /* use bits [45:34] of the address */ 2632 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2633 break; 2634 case 3: /* use bits [43:32] of the address */ 2635 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2636 break; 2637 default: /* Invalid mc_filter_type */ 2638 DEBUGOUT("MC filter type param set incorrectly\n"); 2639 ASSERT(0); 2640 break; 2641 } 2642 2643 /* vector can only be 12-bits or boundary will be exceeded */ 2644 vector &= 0xFFF; 2645 return vector; 2646 } 2647 2648 /** 2649 * ixgbe_set_mta - Set bit-vector in multicast table 2650 * @hw: pointer to hardware structure 2651 * @mc_addr: Multicast address 2652 * 2653 * Sets the bit-vector in the multicast table. 2654 **/ 2655 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2656 { 2657 u32 vector; 2658 u32 vector_bit; 2659 u32 vector_reg; 2660 2661 DEBUGFUNC("ixgbe_set_mta"); 2662 2663 hw->addr_ctrl.mta_in_use++; 2664 2665 vector = ixgbe_mta_vector(hw, mc_addr); 2666 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2667 2668 /* 2669 * The MTA is a register array of 128 32-bit registers. It is treated 2670 * like an array of 4096 bits. We want to set bit 2671 * BitArray[vector_value]. So we figure out what register the bit is 2672 * in, read it, OR in the new bit, then write back the new value. The 2673 * register is determined by the upper 7 bits of the vector value and 2674 * the bit within that register are determined by the lower 5 bits of 2675 * the value. 2676 */ 2677 vector_reg = (vector >> 5) & 0x7F; 2678 vector_bit = vector & 0x1F; 2679 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2680 } 2681 2682 /** 2683 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2684 * @hw: pointer to hardware structure 2685 * @mc_addr_list: the list of new multicast addresses 2686 * @mc_addr_count: number of addresses 2687 * @next: iterator function to walk the multicast address list 2688 * @clear: flag, when set clears the table beforehand 2689 * 2690 * When the clear flag is set, the given list replaces any existing list. 2691 * Hashes the given addresses into the multicast table. 2692 **/ 2693 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2694 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2695 bool clear) 2696 { 2697 u32 i; 2698 u32 vmdq; 2699 2700 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2701 2702 /* 2703 * Set the new number of MC addresses that we are being requested to 2704 * use. 2705 */ 2706 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2707 hw->addr_ctrl.mta_in_use = 0; 2708 2709 /* Clear mta_shadow */ 2710 if (clear) { 2711 DEBUGOUT(" Clearing MTA\n"); 2712 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2713 } 2714 2715 /* Update mta_shadow */ 2716 for (i = 0; i < mc_addr_count; i++) { 2717 DEBUGOUT(" Adding the multicast addresses:\n"); 2718 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2719 } 2720 2721 /* Enable mta */ 2722 for (i = 0; i < hw->mac.mcft_size; i++) 2723 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2724 hw->mac.mta_shadow[i]); 2725 2726 if (hw->addr_ctrl.mta_in_use > 0) 2727 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2728 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2729 2730 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2731 return IXGBE_SUCCESS; 2732 } 2733 2734 /** 2735 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2736 * @hw: pointer to hardware structure 2737 * 2738 * Enables multicast address in RAR and the use of the multicast hash table. 2739 **/ 2740 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2741 { 2742 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2743 2744 DEBUGFUNC("ixgbe_enable_mc_generic"); 2745 2746 if (a->mta_in_use > 0) 2747 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2748 hw->mac.mc_filter_type); 2749 2750 return IXGBE_SUCCESS; 2751 } 2752 2753 /** 2754 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2755 * @hw: pointer to hardware structure 2756 * 2757 * Disables multicast address in RAR and the use of the multicast hash table. 2758 **/ 2759 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2760 { 2761 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2762 2763 DEBUGFUNC("ixgbe_disable_mc_generic"); 2764 2765 if (a->mta_in_use > 0) 2766 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2767 2768 return IXGBE_SUCCESS; 2769 } 2770 2771 /** 2772 * ixgbe_fc_enable_generic - Enable flow control 2773 * @hw: pointer to hardware structure 2774 * 2775 * Enable flow control according to the current settings. 2776 **/ 2777 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2778 { 2779 s32 ret_val = IXGBE_SUCCESS; 2780 u32 mflcn_reg, fccfg_reg; 2781 u32 reg; 2782 u32 fcrtl, fcrth; 2783 int i; 2784 2785 DEBUGFUNC("ixgbe_fc_enable_generic"); 2786 2787 /* Validate the water mark configuration */ 2788 if (!hw->fc.pause_time) { 2789 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2790 goto out; 2791 } 2792 2793 /* Low water mark of zero causes XOFF floods */ 2794 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2795 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2796 hw->fc.high_water[i]) { 2797 if (!hw->fc.low_water[i] || 2798 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2799 DEBUGOUT("Invalid water mark configuration\n"); 2800 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2801 goto out; 2802 } 2803 } 2804 } 2805 2806 /* Negotiate the fc mode to use */ 2807 hw->mac.ops.fc_autoneg(hw); 2808 2809 /* Disable any previous flow control settings */ 2810 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2811 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2812 2813 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2814 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2815 2816 /* 2817 * The possible values of fc.current_mode are: 2818 * 0: Flow control is completely disabled 2819 * 1: Rx flow control is enabled (we can receive pause frames, 2820 * but not send pause frames). 2821 * 2: Tx flow control is enabled (we can send pause frames but 2822 * we do not support receiving pause frames). 2823 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2824 * other: Invalid. 2825 */ 2826 switch (hw->fc.current_mode) { 2827 case ixgbe_fc_none: 2828 /* 2829 * Flow control is disabled by software override or autoneg. 2830 * The code below will actually disable it in the HW. 2831 */ 2832 break; 2833 case ixgbe_fc_rx_pause: 2834 /* 2835 * Rx Flow control is enabled and Tx Flow control is 2836 * disabled by software override. Since there really 2837 * isn't a way to advertise that we are capable of RX 2838 * Pause ONLY, we will advertise that we support both 2839 * symmetric and asymmetric Rx PAUSE. Later, we will 2840 * disable the adapter's ability to send PAUSE frames. 2841 */ 2842 mflcn_reg |= IXGBE_MFLCN_RFCE; 2843 break; 2844 case ixgbe_fc_tx_pause: 2845 /* 2846 * Tx Flow control is enabled, and Rx Flow control is 2847 * disabled by software override. 2848 */ 2849 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2850 break; 2851 case ixgbe_fc_full: 2852 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2853 mflcn_reg |= IXGBE_MFLCN_RFCE; 2854 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2855 break; 2856 default: 2857 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2858 "Flow control param set incorrectly\n"); 2859 ret_val = IXGBE_ERR_CONFIG; 2860 goto out; 2861 break; 2862 } 2863 2864 /* Set 802.3x based flow control settings. */ 2865 mflcn_reg |= IXGBE_MFLCN_DPF; 2866 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2867 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2868 2869 2870 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2871 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2872 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2873 hw->fc.high_water[i]) { 2874 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2875 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2876 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2877 } else { 2878 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2879 /* 2880 * In order to prevent Tx hangs when the internal Tx 2881 * switch is enabled we must set the high water mark 2882 * to the Rx packet buffer size - 24KB. This allows 2883 * the Tx switch to function even under heavy Rx 2884 * workloads. 2885 */ 2886 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2887 } 2888 2889 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2890 } 2891 2892 /* Configure pause time (2 TCs per register) */ 2893 reg = hw->fc.pause_time * 0x00010001; 2894 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2895 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2896 2897 /* Configure flow control refresh threshold value */ 2898 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2899 2900 out: 2901 return ret_val; 2902 } 2903 2904 /** 2905 * ixgbe_negotiate_fc - Negotiate flow control 2906 * @hw: pointer to hardware structure 2907 * @adv_reg: flow control advertised settings 2908 * @lp_reg: link partner's flow control settings 2909 * @adv_sym: symmetric pause bit in advertisement 2910 * @adv_asm: asymmetric pause bit in advertisement 2911 * @lp_sym: symmetric pause bit in link partner advertisement 2912 * @lp_asm: asymmetric pause bit in link partner advertisement 2913 * 2914 * Find the intersection between advertised settings and link partner's 2915 * advertised settings 2916 **/ 2917 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2918 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2919 { 2920 if ((!(adv_reg)) || (!(lp_reg))) { 2921 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2922 "Local or link partner's advertised flow control " 2923 "settings are NULL. Local: %x, link partner: %x\n", 2924 adv_reg, lp_reg); 2925 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2926 } 2927 2928 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2929 /* 2930 * Now we need to check if the user selected Rx ONLY 2931 * of pause frames. In this case, we had to advertise 2932 * FULL flow control because we could not advertise RX 2933 * ONLY. Hence, we must now check to see if we need to 2934 * turn OFF the TRANSMISSION of PAUSE frames. 2935 */ 2936 if (hw->fc.requested_mode == ixgbe_fc_full) { 2937 hw->fc.current_mode = ixgbe_fc_full; 2938 DEBUGOUT("Flow Control = FULL.\n"); 2939 } else { 2940 hw->fc.current_mode = ixgbe_fc_rx_pause; 2941 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2942 } 2943 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2944 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2945 hw->fc.current_mode = ixgbe_fc_tx_pause; 2946 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2947 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2948 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2949 hw->fc.current_mode = ixgbe_fc_rx_pause; 2950 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2951 } else { 2952 hw->fc.current_mode = ixgbe_fc_none; 2953 DEBUGOUT("Flow Control = NONE.\n"); 2954 } 2955 return IXGBE_SUCCESS; 2956 } 2957 2958 /** 2959 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2960 * @hw: pointer to hardware structure 2961 * 2962 * Enable flow control according on 1 gig fiber. 2963 **/ 2964 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2965 { 2966 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2967 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2968 2969 /* 2970 * On multispeed fiber at 1g, bail out if 2971 * - link is up but AN did not complete, or if 2972 * - link is up and AN completed but timed out 2973 */ 2974 2975 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2976 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2977 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 2978 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 2979 goto out; 2980 } 2981 2982 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2983 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2984 2985 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2986 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2987 IXGBE_PCS1GANA_ASM_PAUSE, 2988 IXGBE_PCS1GANA_SYM_PAUSE, 2989 IXGBE_PCS1GANA_ASM_PAUSE); 2990 2991 out: 2992 return ret_val; 2993 } 2994 2995 /** 2996 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2997 * @hw: pointer to hardware structure 2998 * 2999 * Enable flow control according to IEEE clause 37. 3000 **/ 3001 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3002 { 3003 u32 links2, anlp1_reg, autoc_reg, links; 3004 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3005 3006 /* 3007 * On backplane, bail out if 3008 * - backplane autoneg was not completed, or if 3009 * - we are 82599 and link partner is not AN enabled 3010 */ 3011 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3012 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3013 DEBUGOUT("Auto-Negotiation did not complete\n"); 3014 goto out; 3015 } 3016 3017 if (hw->mac.type == ixgbe_mac_82599EB) { 3018 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3019 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3020 DEBUGOUT("Link partner is not AN enabled\n"); 3021 goto out; 3022 } 3023 } 3024 /* 3025 * Read the 10g AN autoc and LP ability registers and resolve 3026 * local flow control settings accordingly 3027 */ 3028 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3029 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3030 3031 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3032 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3033 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3034 3035 out: 3036 return ret_val; 3037 } 3038 3039 /** 3040 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3041 * @hw: pointer to hardware structure 3042 * 3043 * Enable flow control according to IEEE clause 37. 3044 **/ 3045 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3046 { 3047 u16 technology_ability_reg = 0; 3048 u16 lp_technology_ability_reg = 0; 3049 3050 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3051 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3052 &technology_ability_reg); 3053 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3054 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3055 &lp_technology_ability_reg); 3056 3057 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3058 (u32)lp_technology_ability_reg, 3059 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3060 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3061 } 3062 3063 /** 3064 * ixgbe_fc_autoneg - Configure flow control 3065 * @hw: pointer to hardware structure 3066 * 3067 * Compares our advertised flow control capabilities to those advertised by 3068 * our link partner, and determines the proper flow control mode to use. 3069 **/ 3070 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3071 { 3072 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3073 ixgbe_link_speed speed; 3074 bool link_up; 3075 3076 DEBUGFUNC("ixgbe_fc_autoneg"); 3077 3078 /* 3079 * AN should have completed when the cable was plugged in. 3080 * Look for reasons to bail out. Bail out if: 3081 * - FC autoneg is disabled, or if 3082 * - link is not up. 3083 */ 3084 if (hw->fc.disable_fc_autoneg) { 3085 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3086 "Flow control autoneg is disabled"); 3087 goto out; 3088 } 3089 3090 hw->mac.ops.check_link(hw, &speed, &link_up, false); 3091 if (!link_up) { 3092 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3093 goto out; 3094 } 3095 3096 switch (hw->phy.media_type) { 3097 /* Autoneg flow control on fiber adapters */ 3098 case ixgbe_media_type_fiber_qsfp: 3099 case ixgbe_media_type_fiber: 3100 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3101 ret_val = ixgbe_fc_autoneg_fiber(hw); 3102 break; 3103 3104 /* Autoneg flow control on backplane adapters */ 3105 case ixgbe_media_type_backplane: 3106 ret_val = ixgbe_fc_autoneg_backplane(hw); 3107 break; 3108 3109 /* Autoneg flow control on copper adapters */ 3110 case ixgbe_media_type_copper: 3111 if (ixgbe_device_supports_autoneg_fc(hw)) 3112 ret_val = ixgbe_fc_autoneg_copper(hw); 3113 break; 3114 3115 default: 3116 break; 3117 } 3118 3119 out: 3120 if (ret_val == IXGBE_SUCCESS) { 3121 hw->fc.fc_was_autonegged = true; 3122 } else { 3123 hw->fc.fc_was_autonegged = false; 3124 hw->fc.current_mode = hw->fc.requested_mode; 3125 } 3126 } 3127 3128 /* 3129 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3130 * @hw: pointer to hardware structure 3131 * 3132 * System-wide timeout range is encoded in PCIe Device Control2 register. 3133 * 3134 * Add 10% to specified maximum and return the number of times to poll for 3135 * completion timeout, in units of 100 microsec. Never return less than 3136 * 800 = 80 millisec. 3137 */ 3138 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3139 { 3140 s16 devctl2; 3141 u32 pollcnt; 3142 3143 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3144 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3145 3146 switch (devctl2) { 3147 case IXGBE_PCIDEVCTRL2_65_130ms: 3148 pollcnt = 1300; /* 130 millisec */ 3149 break; 3150 case IXGBE_PCIDEVCTRL2_260_520ms: 3151 pollcnt = 5200; /* 520 millisec */ 3152 break; 3153 case IXGBE_PCIDEVCTRL2_1_2s: 3154 pollcnt = 20000; /* 2 sec */ 3155 break; 3156 case IXGBE_PCIDEVCTRL2_4_8s: 3157 pollcnt = 80000; /* 8 sec */ 3158 break; 3159 case IXGBE_PCIDEVCTRL2_17_34s: 3160 pollcnt = 34000; /* 34 sec */ 3161 break; 3162 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3163 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3164 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3165 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3166 default: 3167 pollcnt = 800; /* 80 millisec minimum */ 3168 break; 3169 } 3170 3171 /* add 10% to spec maximum */ 3172 return (pollcnt * 11) / 10; 3173 } 3174 3175 /** 3176 * ixgbe_disable_pcie_master - Disable PCI-express master access 3177 * @hw: pointer to hardware structure 3178 * 3179 * Disables PCI-Express master access and verifies there are no pending 3180 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3181 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3182 * is returned signifying master requests disabled. 3183 **/ 3184 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3185 { 3186 s32 status = IXGBE_SUCCESS; 3187 u32 i, poll; 3188 u16 value; 3189 3190 DEBUGFUNC("ixgbe_disable_pcie_master"); 3191 3192 /* Always set this bit to ensure any future transactions are blocked */ 3193 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3194 3195 /* Exit if master requests are blocked */ 3196 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3197 IXGBE_REMOVED(hw->hw_addr)) 3198 goto out; 3199 3200 /* Poll for master request bit to clear */ 3201 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3202 usec_delay(100); 3203 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3204 goto out; 3205 } 3206 3207 /* 3208 * Two consecutive resets are required via CTRL.RST per datasheet 3209 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3210 * of this need. The first reset prevents new master requests from 3211 * being issued by our device. We then must wait 1usec or more for any 3212 * remaining completions from the PCIe bus to trickle in, and then reset 3213 * again to clear out any effects they may have had on our device. 3214 */ 3215 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3216 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3217 3218 if (hw->mac.type >= ixgbe_mac_X550) 3219 goto out; 3220 3221 /* 3222 * Before proceeding, make sure that the PCIe block does not have 3223 * transactions pending. 3224 */ 3225 poll = ixgbe_pcie_timeout_poll(hw); 3226 for (i = 0; i < poll; i++) { 3227 usec_delay(100); 3228 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3229 if (IXGBE_REMOVED(hw->hw_addr)) 3230 goto out; 3231 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3232 goto out; 3233 } 3234 3235 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3236 "PCIe transaction pending bit also did not clear.\n"); 3237 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3238 3239 out: 3240 return status; 3241 } 3242 3243 /** 3244 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3245 * @hw: pointer to hardware structure 3246 * @mask: Mask to specify which semaphore to acquire 3247 * 3248 * Acquires the SWFW semaphore through the GSSR register for the specified 3249 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3250 **/ 3251 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3252 { 3253 u32 gssr = 0; 3254 u32 swmask = mask; 3255 u32 fwmask = mask << 5; 3256 u32 timeout = 200; 3257 u32 i; 3258 3259 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3260 3261 for (i = 0; i < timeout; i++) { 3262 /* 3263 * SW NVM semaphore bit is used for access to all 3264 * SW_FW_SYNC bits (not just NVM) 3265 */ 3266 if (ixgbe_get_eeprom_semaphore(hw)) 3267 return IXGBE_ERR_SWFW_SYNC; 3268 3269 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3270 if (!(gssr & (fwmask | swmask))) { 3271 gssr |= swmask; 3272 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3273 ixgbe_release_eeprom_semaphore(hw); 3274 return IXGBE_SUCCESS; 3275 } else { 3276 /* Resource is currently in use by FW or SW */ 3277 ixgbe_release_eeprom_semaphore(hw); 3278 msec_delay(5); 3279 } 3280 } 3281 3282 /* If time expired clear the bits holding the lock and retry */ 3283 if (gssr & (fwmask | swmask)) 3284 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3285 3286 msec_delay(5); 3287 return IXGBE_ERR_SWFW_SYNC; 3288 } 3289 3290 /** 3291 * ixgbe_release_swfw_sync - Release SWFW semaphore 3292 * @hw: pointer to hardware structure 3293 * @mask: Mask to specify which semaphore to release 3294 * 3295 * Releases the SWFW semaphore through the GSSR register for the specified 3296 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3297 **/ 3298 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3299 { 3300 u32 gssr; 3301 u32 swmask = mask; 3302 3303 DEBUGFUNC("ixgbe_release_swfw_sync"); 3304 3305 ixgbe_get_eeprom_semaphore(hw); 3306 3307 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3308 gssr &= ~swmask; 3309 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3310 3311 ixgbe_release_eeprom_semaphore(hw); 3312 } 3313 3314 /** 3315 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3316 * @hw: pointer to hardware structure 3317 * 3318 * Stops the receive data path and waits for the HW to internally empty 3319 * the Rx security block 3320 **/ 3321 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3322 { 3323 #define IXGBE_MAX_SECRX_POLL 4000 3324 3325 int i; 3326 int secrxreg; 3327 3328 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3329 3330 3331 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3332 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3333 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3334 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3335 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3336 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3337 break; 3338 else 3339 /* Use interrupt-safe sleep just in case */ 3340 usec_delay(10); 3341 } 3342 3343 /* For informational purposes only */ 3344 if (i >= IXGBE_MAX_SECRX_POLL) 3345 DEBUGOUT("Rx unit being enabled before security " 3346 "path fully disabled. Continuing with init.\n"); 3347 3348 return IXGBE_SUCCESS; 3349 } 3350 3351 /** 3352 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3353 * @hw: pointer to hardware structure 3354 * @locked: bool to indicate whether the SW/FW lock was taken 3355 * @reg_val: Value we read from AUTOC 3356 * 3357 * The default case requires no protection so just to the register read. 3358 */ 3359 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3360 { 3361 *locked = false; 3362 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3363 return IXGBE_SUCCESS; 3364 } 3365 3366 /** 3367 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3368 * @hw: pointer to hardware structure 3369 * @reg_val: value to write to AUTOC 3370 * @locked: bool to indicate whether the SW/FW lock was already taken by 3371 * previous read. 3372 * 3373 * The default case requires no protection so just to the register write. 3374 */ 3375 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3376 { 3377 UNREFERENCED_1PARAMETER(locked); 3378 3379 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3380 return IXGBE_SUCCESS; 3381 } 3382 3383 /** 3384 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3385 * @hw: pointer to hardware structure 3386 * 3387 * Enables the receive data path. 3388 **/ 3389 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3390 { 3391 u32 secrxreg; 3392 3393 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3394 3395 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3396 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3397 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3398 IXGBE_WRITE_FLUSH(hw); 3399 3400 return IXGBE_SUCCESS; 3401 } 3402 3403 /** 3404 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3405 * @hw: pointer to hardware structure 3406 * @regval: register value to write to RXCTRL 3407 * 3408 * Enables the Rx DMA unit 3409 **/ 3410 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3411 { 3412 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3413 3414 if (regval & IXGBE_RXCTRL_RXEN) 3415 ixgbe_enable_rx(hw); 3416 else 3417 ixgbe_disable_rx(hw); 3418 3419 return IXGBE_SUCCESS; 3420 } 3421 3422 /** 3423 * ixgbe_blink_led_start_generic - Blink LED based on index. 3424 * @hw: pointer to hardware structure 3425 * @index: led number to blink 3426 **/ 3427 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3428 { 3429 ixgbe_link_speed speed = 0; 3430 bool link_up = 0; 3431 u32 autoc_reg = 0; 3432 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3433 s32 ret_val = IXGBE_SUCCESS; 3434 bool locked = false; 3435 3436 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3437 3438 if (index > 3) 3439 return IXGBE_ERR_PARAM; 3440 3441 /* 3442 * Link must be up to auto-blink the LEDs; 3443 * Force it if link is down. 3444 */ 3445 hw->mac.ops.check_link(hw, &speed, &link_up, false); 3446 3447 if (!link_up) { 3448 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3449 if (ret_val != IXGBE_SUCCESS) 3450 goto out; 3451 3452 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3453 autoc_reg |= IXGBE_AUTOC_FLU; 3454 3455 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3456 if (ret_val != IXGBE_SUCCESS) 3457 goto out; 3458 3459 IXGBE_WRITE_FLUSH(hw); 3460 msec_delay(10); 3461 } 3462 3463 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3464 led_reg |= IXGBE_LED_BLINK(index); 3465 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3466 IXGBE_WRITE_FLUSH(hw); 3467 3468 out: 3469 return ret_val; 3470 } 3471 3472 /** 3473 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3474 * @hw: pointer to hardware structure 3475 * @index: led number to stop blinking 3476 **/ 3477 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3478 { 3479 u32 autoc_reg = 0; 3480 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3481 s32 ret_val = IXGBE_SUCCESS; 3482 bool locked = false; 3483 3484 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3485 3486 if (index > 3) 3487 return IXGBE_ERR_PARAM; 3488 3489 3490 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3491 if (ret_val != IXGBE_SUCCESS) 3492 goto out; 3493 3494 autoc_reg &= ~IXGBE_AUTOC_FLU; 3495 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3496 3497 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3498 if (ret_val != IXGBE_SUCCESS) 3499 goto out; 3500 3501 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3502 led_reg &= ~IXGBE_LED_BLINK(index); 3503 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3504 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3505 IXGBE_WRITE_FLUSH(hw); 3506 3507 out: 3508 return ret_val; 3509 } 3510 3511 /** 3512 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3513 * @hw: pointer to hardware structure 3514 * @san_mac_offset: SAN MAC address offset 3515 * 3516 * This function will read the EEPROM location for the SAN MAC address 3517 * pointer, and returns the value at that location. This is used in both 3518 * get and set mac_addr routines. 3519 **/ 3520 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3521 u16 *san_mac_offset) 3522 { 3523 s32 ret_val; 3524 3525 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3526 3527 /* 3528 * First read the EEPROM pointer to see if the MAC addresses are 3529 * available. 3530 */ 3531 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3532 san_mac_offset); 3533 if (ret_val) { 3534 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3535 "eeprom at offset %d failed", 3536 IXGBE_SAN_MAC_ADDR_PTR); 3537 } 3538 3539 return ret_val; 3540 } 3541 3542 /** 3543 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3544 * @hw: pointer to hardware structure 3545 * @san_mac_addr: SAN MAC address 3546 * 3547 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3548 * per-port, so set_lan_id() must be called before reading the addresses. 3549 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3550 * upon for non-SFP connections, so we must call it here. 3551 **/ 3552 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3553 { 3554 u16 san_mac_data, san_mac_offset; 3555 u8 i; 3556 s32 ret_val; 3557 3558 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3559 3560 /* 3561 * First read the EEPROM pointer to see if the MAC addresses are 3562 * available. If they're not, no point in calling set_lan_id() here. 3563 */ 3564 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3565 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3566 goto san_mac_addr_out; 3567 3568 /* make sure we know which port we need to program */ 3569 hw->mac.ops.set_lan_id(hw); 3570 /* apply the port offset to the address offset */ 3571 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3572 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3573 for (i = 0; i < 3; i++) { 3574 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3575 &san_mac_data); 3576 if (ret_val) { 3577 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3578 "eeprom read at offset %d failed", 3579 san_mac_offset); 3580 goto san_mac_addr_out; 3581 } 3582 san_mac_addr[i * 2] = (u8)(san_mac_data); 3583 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3584 san_mac_offset++; 3585 } 3586 return IXGBE_SUCCESS; 3587 3588 san_mac_addr_out: 3589 /* 3590 * No addresses available in this EEPROM. It's not an 3591 * error though, so just wipe the local address and return. 3592 */ 3593 for (i = 0; i < 6; i++) 3594 san_mac_addr[i] = 0xFF; 3595 return IXGBE_SUCCESS; 3596 } 3597 3598 /** 3599 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3600 * @hw: pointer to hardware structure 3601 * @san_mac_addr: SAN MAC address 3602 * 3603 * Write a SAN MAC address to the EEPROM. 3604 **/ 3605 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3606 { 3607 s32 ret_val; 3608 u16 san_mac_data, san_mac_offset; 3609 u8 i; 3610 3611 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3612 3613 /* Look for SAN mac address pointer. If not defined, return */ 3614 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3615 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3616 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3617 3618 /* Make sure we know which port we need to write */ 3619 hw->mac.ops.set_lan_id(hw); 3620 /* Apply the port offset to the address offset */ 3621 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3622 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3623 3624 for (i = 0; i < 3; i++) { 3625 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3626 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3627 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3628 san_mac_offset++; 3629 } 3630 3631 return IXGBE_SUCCESS; 3632 } 3633 3634 /** 3635 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3636 * @hw: pointer to hardware structure 3637 * 3638 * Read PCIe configuration space, and get the MSI-X vector count from 3639 * the capabilities table. 3640 **/ 3641 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3642 { 3643 u16 msix_count = 1; 3644 u16 max_msix_count; 3645 u16 pcie_offset; 3646 3647 switch (hw->mac.type) { 3648 case ixgbe_mac_82598EB: 3649 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3650 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3651 break; 3652 case ixgbe_mac_82599EB: 3653 case ixgbe_mac_X540: 3654 case ixgbe_mac_X550: 3655 case ixgbe_mac_X550EM_x: 3656 case ixgbe_mac_X550EM_a: 3657 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3658 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3659 break; 3660 default: 3661 return msix_count; 3662 } 3663 3664 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3665 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3666 if (IXGBE_REMOVED(hw->hw_addr)) 3667 msix_count = 0; 3668 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3669 3670 /* MSI-X count is zero-based in HW */ 3671 msix_count++; 3672 3673 if (msix_count > max_msix_count) 3674 msix_count = max_msix_count; 3675 3676 return msix_count; 3677 } 3678 3679 /** 3680 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3681 * @hw: pointer to hardware structure 3682 * @addr: Address to put into receive address register 3683 * @vmdq: VMDq pool to assign 3684 * 3685 * Puts an ethernet address into a receive address register, or 3686 * finds the rar that it is aleady in; adds to the pool list 3687 **/ 3688 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3689 { 3690 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3691 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3692 u32 rar; 3693 u32 rar_low, rar_high; 3694 u32 addr_low, addr_high; 3695 3696 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3697 3698 /* swap bytes for HW little endian */ 3699 addr_low = addr[0] | (addr[1] << 8) 3700 | (addr[2] << 16) 3701 | (addr[3] << 24); 3702 addr_high = addr[4] | (addr[5] << 8); 3703 3704 /* 3705 * Either find the mac_id in rar or find the first empty space. 3706 * rar_highwater points to just after the highest currently used 3707 * rar in order to shorten the search. It grows when we add a new 3708 * rar to the top. 3709 */ 3710 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3711 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3712 3713 if (((IXGBE_RAH_AV & rar_high) == 0) 3714 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3715 first_empty_rar = rar; 3716 } else if ((rar_high & 0xFFFF) == addr_high) { 3717 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3718 if (rar_low == addr_low) 3719 break; /* found it already in the rars */ 3720 } 3721 } 3722 3723 if (rar < hw->mac.rar_highwater) { 3724 /* already there so just add to the pool bits */ 3725 ixgbe_set_vmdq(hw, rar, vmdq); 3726 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3727 /* stick it into first empty RAR slot we found */ 3728 rar = first_empty_rar; 3729 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3730 } else if (rar == hw->mac.rar_highwater) { 3731 /* add it to the top of the list and inc the highwater mark */ 3732 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3733 hw->mac.rar_highwater++; 3734 } else if (rar >= hw->mac.num_rar_entries) { 3735 return IXGBE_ERR_INVALID_MAC_ADDR; 3736 } 3737 3738 /* 3739 * If we found rar[0], make sure the default pool bit (we use pool 0) 3740 * remains cleared to be sure default pool packets will get delivered 3741 */ 3742 if (rar == 0) 3743 ixgbe_clear_vmdq(hw, rar, 0); 3744 3745 return rar; 3746 } 3747 3748 /** 3749 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3750 * @hw: pointer to hardware struct 3751 * @rar: receive address register index to disassociate 3752 * @vmdq: VMDq pool index to remove from the rar 3753 **/ 3754 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3755 { 3756 u32 mpsar_lo, mpsar_hi; 3757 u32 rar_entries = hw->mac.num_rar_entries; 3758 3759 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3760 3761 /* Make sure we are using a valid rar index range */ 3762 if (rar >= rar_entries) { 3763 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3764 "RAR index %d is out of range.\n", rar); 3765 return IXGBE_ERR_INVALID_ARGUMENT; 3766 } 3767 3768 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3769 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3770 3771 if (IXGBE_REMOVED(hw->hw_addr)) 3772 goto done; 3773 3774 if (!mpsar_lo && !mpsar_hi) 3775 goto done; 3776 3777 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3778 if (mpsar_lo) { 3779 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3780 mpsar_lo = 0; 3781 } 3782 if (mpsar_hi) { 3783 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3784 mpsar_hi = 0; 3785 } 3786 } else if (vmdq < 32) { 3787 mpsar_lo &= ~(1 << vmdq); 3788 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3789 } else { 3790 mpsar_hi &= ~(1 << (vmdq - 32)); 3791 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3792 } 3793 3794 /* was that the last pool using this rar? */ 3795 if (mpsar_lo == 0 && mpsar_hi == 0 && 3796 rar != 0 && rar != hw->mac.san_mac_rar_index) 3797 hw->mac.ops.clear_rar(hw, rar); 3798 done: 3799 return IXGBE_SUCCESS; 3800 } 3801 3802 /** 3803 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3804 * @hw: pointer to hardware struct 3805 * @rar: receive address register index to associate with a VMDq index 3806 * @vmdq: VMDq pool index 3807 **/ 3808 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3809 { 3810 u32 mpsar; 3811 u32 rar_entries = hw->mac.num_rar_entries; 3812 3813 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3814 3815 /* Make sure we are using a valid rar index range */ 3816 if (rar >= rar_entries) { 3817 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3818 "RAR index %d is out of range.\n", rar); 3819 return IXGBE_ERR_INVALID_ARGUMENT; 3820 } 3821 3822 if (vmdq < 32) { 3823 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3824 mpsar |= 1 << vmdq; 3825 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3826 } else { 3827 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3828 mpsar |= 1 << (vmdq - 32); 3829 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3830 } 3831 return IXGBE_SUCCESS; 3832 } 3833 3834 /** 3835 * This function should only be involved in the IOV mode. 3836 * In IOV mode, Default pool is next pool after the number of 3837 * VFs advertized and not 0. 3838 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3839 * 3840 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3841 * @hw: pointer to hardware struct 3842 * @vmdq: VMDq pool index 3843 **/ 3844 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3845 { 3846 u32 rar = hw->mac.san_mac_rar_index; 3847 3848 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3849 3850 if (vmdq < 32) { 3851 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3852 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3853 } else { 3854 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3855 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3856 } 3857 3858 return IXGBE_SUCCESS; 3859 } 3860 3861 /** 3862 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3863 * @hw: pointer to hardware structure 3864 **/ 3865 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3866 { 3867 int i; 3868 3869 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3870 DEBUGOUT(" Clearing UTA\n"); 3871 3872 for (i = 0; i < 128; i++) 3873 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3874 3875 return IXGBE_SUCCESS; 3876 } 3877 3878 /** 3879 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3880 * @hw: pointer to hardware structure 3881 * @vlan: VLAN id to write to VLAN filter 3882 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if 3883 * vlanid not found 3884 * 3885 * 3886 * return the VLVF index where this VLAN id should be placed 3887 * 3888 **/ 3889 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3890 { 3891 s32 regindex, first_empty_slot; 3892 u32 bits; 3893 3894 /* short cut the special case */ 3895 if (vlan == 0) 3896 return 0; 3897 3898 /* if vlvf_bypass is set we don't want to use an empty slot, we 3899 * will simply bypass the VLVF if there are no entries present in the 3900 * VLVF that contain our VLAN 3901 */ 3902 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3903 3904 /* add VLAN enable bit for comparison */ 3905 vlan |= IXGBE_VLVF_VIEN; 3906 3907 /* Search for the vlan id in the VLVF entries. Save off the first empty 3908 * slot found along the way. 3909 * 3910 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3911 */ 3912 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3913 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3914 if (bits == vlan) 3915 return regindex; 3916 if (!first_empty_slot && !bits) 3917 first_empty_slot = regindex; 3918 } 3919 3920 /* If we are here then we didn't find the VLAN. Return first empty 3921 * slot we found during our search, else error. 3922 */ 3923 if (!first_empty_slot) 3924 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3925 3926 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3927 } 3928 3929 /** 3930 * ixgbe_set_vfta_generic - Set VLAN filter table 3931 * @hw: pointer to hardware structure 3932 * @vlan: VLAN id to write to VLAN filter 3933 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3934 * @vlan_on: boolean flag to turn on/off VLAN 3935 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3936 * 3937 * Turn on/off specified VLAN in the VLAN filter table. 3938 **/ 3939 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3940 bool vlan_on, bool vlvf_bypass) 3941 { 3942 u32 regidx, vfta_delta, vfta; 3943 s32 ret_val; 3944 3945 DEBUGFUNC("ixgbe_set_vfta_generic"); 3946 3947 if (vlan > 4095 || vind > 63) 3948 return IXGBE_ERR_PARAM; 3949 3950 /* 3951 * this is a 2 part operation - first the VFTA, then the 3952 * VLVF and VLVFB if VT Mode is set 3953 * We don't write the VFTA until we know the VLVF part succeeded. 3954 */ 3955 3956 /* Part 1 3957 * The VFTA is a bitstring made up of 128 32-bit registers 3958 * that enable the particular VLAN id, much like the MTA: 3959 * bits[11-5]: which register 3960 * bits[4-0]: which bit in the register 3961 */ 3962 regidx = vlan / 32; 3963 vfta_delta = 1 << (vlan % 32); 3964 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3965 3966 /* 3967 * vfta_delta represents the difference between the current value 3968 * of vfta and the value we want in the register. Since the diff 3969 * is an XOR mask we can just update the vfta using an XOR 3970 */ 3971 vfta_delta &= vlan_on ? ~vfta : vfta; 3972 vfta ^= vfta_delta; 3973 3974 /* Part 2 3975 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 3976 */ 3977 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 3978 vfta, vlvf_bypass); 3979 if (ret_val != IXGBE_SUCCESS) { 3980 if (vlvf_bypass) 3981 goto vfta_update; 3982 return ret_val; 3983 } 3984 3985 vfta_update: 3986 /* Update VFTA now that we are ready for traffic */ 3987 if (vfta_delta) 3988 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3989 3990 return IXGBE_SUCCESS; 3991 } 3992 3993 /** 3994 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 3995 * @hw: pointer to hardware structure 3996 * @vlan: VLAN id to write to VLAN filter 3997 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3998 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 3999 * @vfta_delta: pointer to the difference between the current value of VFTA 4000 * and the desired value 4001 * @vfta: the desired value of the VFTA 4002 * @vlvf_bypass: boolean flag indicating updating default pool is okay 4003 * 4004 * Turn on/off specified bit in VLVF table. 4005 **/ 4006 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4007 bool vlan_on, u32 *vfta_delta, u32 vfta, 4008 bool vlvf_bypass) 4009 { 4010 u32 bits; 4011 s32 vlvf_index; 4012 4013 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4014 4015 if (vlan > 4095 || vind > 63) 4016 return IXGBE_ERR_PARAM; 4017 4018 /* If VT Mode is set 4019 * Either vlan_on 4020 * make sure the vlan is in VLVF 4021 * set the vind bit in the matching VLVFB 4022 * Or !vlan_on 4023 * clear the pool bit and possibly the vind 4024 */ 4025 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4026 return IXGBE_SUCCESS; 4027 4028 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4029 if (vlvf_index < 0) 4030 return vlvf_index; 4031 4032 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4033 4034 /* set the pool bit */ 4035 bits |= 1 << (vind % 32); 4036 if (vlan_on) 4037 goto vlvf_update; 4038 4039 /* clear the pool bit */ 4040 bits ^= 1 << (vind % 32); 4041 4042 if (!bits && 4043 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4044 /* Clear VFTA first, then disable VLVF. Otherwise 4045 * we run the risk of stray packets leaking into 4046 * the PF via the default pool 4047 */ 4048 if (*vfta_delta) 4049 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4050 4051 /* disable VLVF and clear remaining bit from pool */ 4052 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4053 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4054 4055 return IXGBE_SUCCESS; 4056 } 4057 4058 /* If there are still bits set in the VLVFB registers 4059 * for the VLAN ID indicated we need to see if the 4060 * caller is requesting that we clear the VFTA entry bit. 4061 * If the caller has requested that we clear the VFTA 4062 * entry bit but there are still pools/VFs using this VLAN 4063 * ID entry then ignore the request. We're not worried 4064 * about the case where we're turning the VFTA VLAN ID 4065 * entry bit on, only when requested to turn it off as 4066 * there may be multiple pools and/or VFs using the 4067 * VLAN ID entry. In that case we cannot clear the 4068 * VFTA bit until all pools/VFs using that VLAN ID have also 4069 * been cleared. This will be indicated by "bits" being 4070 * zero. 4071 */ 4072 *vfta_delta = 0; 4073 4074 vlvf_update: 4075 /* record pool change and enable VLAN ID if not already enabled */ 4076 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4077 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4078 4079 return IXGBE_SUCCESS; 4080 } 4081 4082 /** 4083 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4084 * @hw: pointer to hardware structure 4085 * 4086 * Clears the VLAN filer table, and the VMDq index associated with the filter 4087 **/ 4088 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4089 { 4090 u32 offset; 4091 4092 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4093 4094 for (offset = 0; offset < hw->mac.vft_size; offset++) 4095 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4096 4097 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4098 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4099 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4100 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 4101 } 4102 4103 return IXGBE_SUCCESS; 4104 } 4105 4106 /** 4107 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4108 * @hw: pointer to hardware structure 4109 * 4110 * Contains the logic to identify if we need to verify link for the 4111 * crosstalk fix 4112 **/ 4113 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4114 { 4115 4116 /* Does FW say we need the fix */ 4117 if (!hw->need_crosstalk_fix) 4118 return false; 4119 4120 /* Only consider SFP+ PHYs i.e. media type fiber */ 4121 switch (hw->mac.ops.get_media_type(hw)) { 4122 case ixgbe_media_type_fiber: 4123 case ixgbe_media_type_fiber_qsfp: 4124 break; 4125 default: 4126 return false; 4127 } 4128 4129 return true; 4130 } 4131 4132 /** 4133 * ixgbe_check_mac_link_generic - Determine link and speed status 4134 * @hw: pointer to hardware structure 4135 * @speed: pointer to link speed 4136 * @link_up: true when link is up 4137 * @link_up_wait_to_complete: bool used to wait for link up or not 4138 * 4139 * Reads the links register to determine if link is up and the current speed 4140 **/ 4141 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4142 bool *link_up, bool link_up_wait_to_complete) 4143 { 4144 u32 links_reg, links_orig; 4145 u32 i; 4146 4147 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4148 4149 /* If Crosstalk fix enabled do the sanity check of making sure 4150 * the SFP+ cage is full. 4151 */ 4152 if (ixgbe_need_crosstalk_fix(hw)) { 4153 u32 sfp_cage_full; 4154 4155 switch (hw->mac.type) { 4156 case ixgbe_mac_82599EB: 4157 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4158 IXGBE_ESDP_SDP2; 4159 break; 4160 case ixgbe_mac_X550EM_x: 4161 case ixgbe_mac_X550EM_a: 4162 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4163 IXGBE_ESDP_SDP0; 4164 break; 4165 default: 4166 /* sanity check - No SFP+ devices here */ 4167 sfp_cage_full = false; 4168 break; 4169 } 4170 4171 if (!sfp_cage_full) { 4172 *link_up = false; 4173 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4174 return IXGBE_SUCCESS; 4175 } 4176 } 4177 4178 /* clear the old state */ 4179 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4180 4181 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4182 4183 if (links_orig != links_reg) { 4184 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4185 links_orig, links_reg); 4186 } 4187 4188 if (link_up_wait_to_complete) { 4189 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4190 if (links_reg & IXGBE_LINKS_UP) { 4191 *link_up = true; 4192 break; 4193 } else { 4194 *link_up = false; 4195 } 4196 msec_delay(100); 4197 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4198 } 4199 } else { 4200 if (links_reg & IXGBE_LINKS_UP) 4201 *link_up = true; 4202 else 4203 *link_up = false; 4204 } 4205 4206 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4207 case IXGBE_LINKS_SPEED_10G_82599: 4208 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4209 if (hw->mac.type >= ixgbe_mac_X550) { 4210 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4211 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4212 } 4213 break; 4214 case IXGBE_LINKS_SPEED_1G_82599: 4215 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4216 break; 4217 case IXGBE_LINKS_SPEED_100_82599: 4218 *speed = IXGBE_LINK_SPEED_100_FULL; 4219 if (hw->mac.type == ixgbe_mac_X550) { 4220 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4221 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4222 } 4223 break; 4224 case IXGBE_LINKS_SPEED_10_X550EM_A: 4225 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4226 #ifdef PREBOOT_SUPPORT 4227 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4228 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L || 4229 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 4230 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 4231 *speed = IXGBE_LINK_SPEED_10_FULL; 4232 #else 4233 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4234 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4235 *speed = IXGBE_LINK_SPEED_10_FULL; 4236 #endif /* PREBOOT_SUPPORT */ 4237 break; 4238 default: 4239 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4240 } 4241 4242 return IXGBE_SUCCESS; 4243 } 4244 4245 /** 4246 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4247 * the EEPROM 4248 * @hw: pointer to hardware structure 4249 * @wwnn_prefix: the alternative WWNN prefix 4250 * @wwpn_prefix: the alternative WWPN prefix 4251 * 4252 * This function will read the EEPROM from the alternative SAN MAC address 4253 * block to check the support for the alternative WWNN/WWPN prefix support. 4254 **/ 4255 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4256 u16 *wwpn_prefix) 4257 { 4258 u16 offset, caps; 4259 u16 alt_san_mac_blk_offset; 4260 4261 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4262 4263 /* clear output first */ 4264 *wwnn_prefix = 0xFFFF; 4265 *wwpn_prefix = 0xFFFF; 4266 4267 /* check if alternative SAN MAC is supported */ 4268 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4269 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4270 goto wwn_prefix_err; 4271 4272 if ((alt_san_mac_blk_offset == 0) || 4273 (alt_san_mac_blk_offset == 0xFFFF)) 4274 goto wwn_prefix_out; 4275 4276 /* check capability in alternative san mac address block */ 4277 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4278 if (hw->eeprom.ops.read(hw, offset, &caps)) 4279 goto wwn_prefix_err; 4280 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4281 goto wwn_prefix_out; 4282 4283 /* get the corresponding prefix for WWNN/WWPN */ 4284 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4285 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4287 "eeprom read at offset %d failed", offset); 4288 } 4289 4290 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4291 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4292 goto wwn_prefix_err; 4293 4294 wwn_prefix_out: 4295 return IXGBE_SUCCESS; 4296 4297 wwn_prefix_err: 4298 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4299 "eeprom read at offset %d failed", offset); 4300 return IXGBE_SUCCESS; 4301 } 4302 4303 /** 4304 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4305 * @hw: pointer to hardware structure 4306 * @bs: the fcoe boot status 4307 * 4308 * This function will read the FCOE boot status from the iSCSI FCOE block 4309 **/ 4310 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4311 { 4312 u16 offset, caps, flags; 4313 s32 status; 4314 4315 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4316 4317 /* clear output first */ 4318 *bs = ixgbe_fcoe_bootstatus_unavailable; 4319 4320 /* check if FCOE IBA block is present */ 4321 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4322 status = hw->eeprom.ops.read(hw, offset, &caps); 4323 if (status != IXGBE_SUCCESS) 4324 goto out; 4325 4326 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4327 goto out; 4328 4329 /* check if iSCSI FCOE block is populated */ 4330 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4331 if (status != IXGBE_SUCCESS) 4332 goto out; 4333 4334 if ((offset == 0) || (offset == 0xFFFF)) 4335 goto out; 4336 4337 /* read fcoe flags in iSCSI FCOE block */ 4338 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4339 status = hw->eeprom.ops.read(hw, offset, &flags); 4340 if (status != IXGBE_SUCCESS) 4341 goto out; 4342 4343 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4344 *bs = ixgbe_fcoe_bootstatus_enabled; 4345 else 4346 *bs = ixgbe_fcoe_bootstatus_disabled; 4347 4348 out: 4349 return status; 4350 } 4351 4352 /** 4353 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4354 * @hw: pointer to hardware structure 4355 * @enable: enable or disable switch for MAC anti-spoofing 4356 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4357 * 4358 **/ 4359 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4360 { 4361 int vf_target_reg = vf >> 3; 4362 int vf_target_shift = vf % 8; 4363 u32 pfvfspoof; 4364 4365 if (hw->mac.type == ixgbe_mac_82598EB) 4366 return; 4367 4368 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4369 if (enable) 4370 pfvfspoof |= (1 << vf_target_shift); 4371 else 4372 pfvfspoof &= ~(1 << vf_target_shift); 4373 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4374 } 4375 4376 /** 4377 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4378 * @hw: pointer to hardware structure 4379 * @enable: enable or disable switch for VLAN anti-spoofing 4380 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4381 * 4382 **/ 4383 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4384 { 4385 int vf_target_reg = vf >> 3; 4386 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4387 u32 pfvfspoof; 4388 4389 if (hw->mac.type == ixgbe_mac_82598EB) 4390 return; 4391 4392 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4393 if (enable) 4394 pfvfspoof |= (1 << vf_target_shift); 4395 else 4396 pfvfspoof &= ~(1 << vf_target_shift); 4397 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4398 } 4399 4400 /** 4401 * ixgbe_get_device_caps_generic - Get additional device capabilities 4402 * @hw: pointer to hardware structure 4403 * @device_caps: the EEPROM word with the extra device capabilities 4404 * 4405 * This function will read the EEPROM location for the device capabilities, 4406 * and return the word through device_caps. 4407 **/ 4408 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4409 { 4410 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4411 4412 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4413 4414 return IXGBE_SUCCESS; 4415 } 4416 4417 /** 4418 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4419 * @hw: pointer to hardware structure 4420 * 4421 **/ 4422 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4423 { 4424 u32 regval; 4425 u32 i; 4426 4427 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4428 4429 /* Enable relaxed ordering */ 4430 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4431 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4432 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4433 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4434 } 4435 4436 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4437 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4438 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4439 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4440 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4441 } 4442 4443 } 4444 4445 /** 4446 * ixgbe_calculate_checksum - Calculate checksum for buffer 4447 * @buffer: pointer to EEPROM 4448 * @length: size of EEPROM to calculate a checksum for 4449 * Calculates the checksum for some buffer on a specified length. The 4450 * checksum calculated is returned. 4451 **/ 4452 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4453 { 4454 u32 i; 4455 u8 sum = 0; 4456 4457 DEBUGFUNC("ixgbe_calculate_checksum"); 4458 4459 if (!buffer) 4460 return 0; 4461 4462 for (i = 0; i < length; i++) 4463 sum += buffer[i]; 4464 4465 return (u8) (0 - sum); 4466 } 4467 4468 /** 4469 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4470 * @hw: pointer to the HW structure 4471 * @buffer: command to write and where the return status will be placed 4472 * @length: length of buffer, must be multiple of 4 bytes 4473 * @timeout: time in ms to wait for command completion 4474 * 4475 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4476 * else returns semaphore error when encountering an error acquiring 4477 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4478 * 4479 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4480 * by the caller. 4481 **/ 4482 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4483 u32 timeout) 4484 { 4485 u32 hicr, i, fwsts; 4486 u16 dword_len; 4487 4488 DEBUGFUNC("ixgbe_hic_unlocked"); 4489 4490 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4491 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4492 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4493 } 4494 4495 /* Set bit 9 of FWSTS clearing FW reset indication */ 4496 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4497 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4498 4499 /* Check that the host interface is enabled. */ 4500 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4501 if (!(hicr & IXGBE_HICR_EN)) { 4502 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4503 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4504 } 4505 4506 /* Calculate length in DWORDs. We must be DWORD aligned */ 4507 if (length % sizeof(u32)) { 4508 DEBUGOUT("Buffer length failure, not aligned to dword"); 4509 return IXGBE_ERR_INVALID_ARGUMENT; 4510 } 4511 4512 dword_len = length >> 2; 4513 4514 /* The device driver writes the relevant command block 4515 * into the ram area. 4516 */ 4517 for (i = 0; i < dword_len; i++) 4518 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4519 i, IXGBE_CPU_TO_LE32(buffer[i])); 4520 4521 /* Setting this bit tells the ARC that a new command is pending. */ 4522 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4523 4524 for (i = 0; i < timeout; i++) { 4525 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4526 if (!(hicr & IXGBE_HICR_C)) 4527 break; 4528 msec_delay(1); 4529 } 4530 4531 /* Check command completion */ 4532 if ((timeout && i == timeout) || 4533 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4534 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4535 "Command has failed with no status valid.\n"); 4536 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4537 } 4538 4539 return IXGBE_SUCCESS; 4540 } 4541 4542 /** 4543 * ixgbe_host_interface_command - Issue command to manageability block 4544 * @hw: pointer to the HW structure 4545 * @buffer: contains the command to write and where the return status will 4546 * be placed 4547 * @length: length of buffer, must be multiple of 4 bytes 4548 * @timeout: time in ms to wait for command completion 4549 * @return_data: read and return data from the buffer (true) or not (false) 4550 * Needed because FW structures are big endian and decoding of 4551 * these fields can be 8 bit or 16 bit based on command. Decoding 4552 * is not easily understood without making a table of commands. 4553 * So we will leave this up to the caller to read back the data 4554 * in these cases. 4555 * 4556 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4557 * else returns semaphore error when encountering an error acquiring 4558 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4559 **/ 4560 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4561 u32 length, u32 timeout, bool return_data) 4562 { 4563 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4564 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer; 4565 u16 buf_len; 4566 s32 status; 4567 u32 bi; 4568 u32 dword_len; 4569 4570 DEBUGFUNC("ixgbe_host_interface_command"); 4571 4572 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4573 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4574 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4575 } 4576 4577 /* Take management host interface semaphore */ 4578 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4579 if (status) 4580 return status; 4581 4582 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4583 if (status) 4584 goto rel_out; 4585 4586 if (!return_data) 4587 goto rel_out; 4588 4589 /* Calculate length in DWORDs */ 4590 dword_len = hdr_size >> 2; 4591 4592 /* first pull in the header so we know the buffer length */ 4593 for (bi = 0; bi < dword_len; bi++) { 4594 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4595 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]); 4596 } 4597 4598 /* 4599 * If there is any thing in data position pull it in 4600 * Read Flash command requires reading buffer length from 4601 * two byes instead of one byte 4602 */ 4603 if (resp->cmd == 0x30) { 4604 for (; bi < dword_len + 2; bi++) { 4605 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4606 bi); 4607 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4608 } 4609 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) 4610 & 0xF00) | resp->buf_len; 4611 hdr_size += (2 << 2); 4612 } else { 4613 buf_len = resp->buf_len; 4614 } 4615 if (!buf_len) 4616 goto rel_out; 4617 4618 if (length < buf_len + hdr_size) { 4619 DEBUGOUT("Buffer not large enough for reply message.\n"); 4620 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4621 goto rel_out; 4622 } 4623 4624 /* Calculate length in DWORDs, add 3 for odd lengths */ 4625 dword_len = (buf_len + 3) >> 2; 4626 4627 /* Pull in the rest of the buffer (bi is where we left off) */ 4628 for (; bi <= dword_len; bi++) { 4629 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4630 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]); 4631 } 4632 4633 rel_out: 4634 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4635 4636 return status; 4637 } 4638 4639 /** 4640 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4641 * @hw: pointer to the HW structure 4642 * @maj: driver version major number 4643 * @min: driver version minor number 4644 * @build: driver version build number 4645 * @sub: driver version sub build number 4646 * @len: unused 4647 * @driver_ver: unused 4648 * 4649 * Sends driver version number to firmware through the manageability 4650 * block. On success return IXGBE_SUCCESS 4651 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4652 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4653 **/ 4654 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 4655 u8 build, u8 sub, u16 len, 4656 const char *driver_ver) 4657 { 4658 struct ixgbe_hic_drv_info fw_cmd; 4659 int i; 4660 s32 ret_val = IXGBE_SUCCESS; 4661 4662 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4663 UNREFERENCED_2PARAMETER(len, driver_ver); 4664 4665 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4666 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4667 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4668 fw_cmd.port_num = (u8)hw->bus.func; 4669 fw_cmd.ver_maj = maj; 4670 fw_cmd.ver_min = min; 4671 fw_cmd.ver_build = build; 4672 fw_cmd.ver_sub = sub; 4673 fw_cmd.hdr.checksum = 0; 4674 fw_cmd.pad = 0; 4675 fw_cmd.pad2 = 0; 4676 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4677 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4678 4679 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4680 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4681 sizeof(fw_cmd), 4682 IXGBE_HI_COMMAND_TIMEOUT, 4683 true); 4684 if (ret_val != IXGBE_SUCCESS) 4685 continue; 4686 4687 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4688 FW_CEM_RESP_STATUS_SUCCESS) 4689 ret_val = IXGBE_SUCCESS; 4690 else 4691 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4692 4693 break; 4694 } 4695 4696 return ret_val; 4697 } 4698 4699 /** 4700 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4701 * @hw: pointer to hardware structure 4702 * @num_pb: number of packet buffers to allocate 4703 * @headroom: reserve n KB of headroom 4704 * @strategy: packet buffer allocation strategy 4705 **/ 4706 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4707 int strategy) 4708 { 4709 u32 pbsize = hw->mac.rx_pb_size; 4710 int i = 0; 4711 u32 rxpktsize, txpktsize, txpbthresh; 4712 4713 /* Reserve headroom */ 4714 pbsize -= headroom; 4715 4716 if (!num_pb) 4717 num_pb = 1; 4718 4719 /* Divide remaining packet buffer space amongst the number of packet 4720 * buffers requested using supplied strategy. 4721 */ 4722 switch (strategy) { 4723 case PBA_STRATEGY_WEIGHTED: 4724 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4725 * buffer with 5/8 of the packet buffer space. 4726 */ 4727 rxpktsize = (pbsize * 5) / (num_pb * 4); 4728 pbsize -= rxpktsize * (num_pb / 2); 4729 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4730 for (; i < (num_pb / 2); i++) 4731 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4732 /* fall through - configure remaining packet buffers */ 4733 case PBA_STRATEGY_EQUAL: 4734 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4735 for (; i < num_pb; i++) 4736 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4737 break; 4738 default: 4739 break; 4740 } 4741 4742 /* Only support an equally distributed Tx packet buffer strategy. */ 4743 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4744 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4745 for (i = 0; i < num_pb; i++) { 4746 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4747 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4748 } 4749 4750 /* Clear unused TCs, if any, to zero buffer size*/ 4751 for (; i < IXGBE_MAX_PB; i++) { 4752 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4753 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4754 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4755 } 4756 } 4757 4758 /** 4759 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4760 * @hw: pointer to the hardware structure 4761 * 4762 * The 82599 and x540 MACs can experience issues if TX work is still pending 4763 * when a reset occurs. This function prevents this by flushing the PCIe 4764 * buffers on the system. 4765 **/ 4766 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4767 { 4768 u32 gcr_ext, hlreg0, i, poll; 4769 u16 value; 4770 4771 /* 4772 * If double reset is not requested then all transactions should 4773 * already be clear and as such there is no work to do 4774 */ 4775 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4776 return; 4777 4778 /* 4779 * Set loopback enable to prevent any transmits from being sent 4780 * should the link come up. This assumes that the RXCTRL.RXEN bit 4781 * has already been cleared. 4782 */ 4783 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4784 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4785 4786 /* Wait for a last completion before clearing buffers */ 4787 IXGBE_WRITE_FLUSH(hw); 4788 msec_delay(3); 4789 4790 /* 4791 * Before proceeding, make sure that the PCIe block does not have 4792 * transactions pending. 4793 */ 4794 poll = ixgbe_pcie_timeout_poll(hw); 4795 for (i = 0; i < poll; i++) { 4796 usec_delay(100); 4797 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4798 if (IXGBE_REMOVED(hw->hw_addr)) 4799 goto out; 4800 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4801 goto out; 4802 } 4803 4804 out: 4805 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4806 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4807 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4808 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4809 4810 /* Flush all writes and allow 20usec for all transactions to clear */ 4811 IXGBE_WRITE_FLUSH(hw); 4812 usec_delay(20); 4813 4814 /* restore previous register values */ 4815 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4816 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4817 } 4818 4819 STATIC const u8 ixgbe_emc_temp_data[4] = { 4820 IXGBE_EMC_INTERNAL_DATA, 4821 IXGBE_EMC_DIODE1_DATA, 4822 IXGBE_EMC_DIODE2_DATA, 4823 IXGBE_EMC_DIODE3_DATA 4824 }; 4825 STATIC const u8 ixgbe_emc_therm_limit[4] = { 4826 IXGBE_EMC_INTERNAL_THERM_LIMIT, 4827 IXGBE_EMC_DIODE1_THERM_LIMIT, 4828 IXGBE_EMC_DIODE2_THERM_LIMIT, 4829 IXGBE_EMC_DIODE3_THERM_LIMIT 4830 }; 4831 4832 /** 4833 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 4834 * @hw: pointer to hardware structure 4835 * 4836 * Returns the thermal sensor data structure 4837 **/ 4838 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 4839 { 4840 s32 status = IXGBE_SUCCESS; 4841 u16 ets_offset; 4842 u16 ets_cfg; 4843 u16 ets_sensor; 4844 u8 num_sensors; 4845 u8 sensor_index; 4846 u8 sensor_location; 4847 u8 i; 4848 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 4849 4850 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic"); 4851 4852 /* Only support thermal sensors attached to 82599 physical port 0 */ 4853 if ((hw->mac.type != ixgbe_mac_82599EB) || 4854 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) { 4855 status = IXGBE_NOT_IMPLEMENTED; 4856 goto out; 4857 } 4858 4859 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset); 4860 if (status) 4861 goto out; 4862 4863 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) { 4864 status = IXGBE_NOT_IMPLEMENTED; 4865 goto out; 4866 } 4867 4868 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg); 4869 if (status) 4870 goto out; 4871 4872 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT) 4873 != IXGBE_ETS_TYPE_EMC) { 4874 status = IXGBE_NOT_IMPLEMENTED; 4875 goto out; 4876 } 4877 4878 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 4879 if (num_sensors > IXGBE_MAX_SENSORS) 4880 num_sensors = IXGBE_MAX_SENSORS; 4881 4882 for (i = 0; i < num_sensors; i++) { 4883 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 4884 &ets_sensor); 4885 if (status) 4886 goto out; 4887 4888 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 4889 IXGBE_ETS_DATA_INDEX_SHIFT); 4890 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 4891 IXGBE_ETS_DATA_LOC_SHIFT); 4892 4893 if (sensor_location != 0) { 4894 status = hw->phy.ops.read_i2c_byte(hw, 4895 ixgbe_emc_temp_data[sensor_index], 4896 IXGBE_I2C_THERMAL_SENSOR_ADDR, 4897 &data->sensor[i].temp); 4898 if (status) 4899 goto out; 4900 } 4901 } 4902 out: 4903 return status; 4904 } 4905 4906 /** 4907 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 4908 * @hw: pointer to hardware structure 4909 * 4910 * Inits the thermal sensor thresholds according to the NVM map 4911 * and save off the threshold and location values into mac.thermal_sensor_data 4912 **/ 4913 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 4914 { 4915 s32 status = IXGBE_SUCCESS; 4916 u16 offset; 4917 u16 ets_offset; 4918 u16 ets_cfg; 4919 u16 ets_sensor; 4920 u8 low_thresh_delta; 4921 u8 num_sensors; 4922 u8 sensor_index; 4923 u8 sensor_location; 4924 u8 therm_limit; 4925 u8 i; 4926 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 4927 4928 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic"); 4929 4930 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 4931 4932 /* Only support thermal sensors attached to 82599 physical port 0 */ 4933 if ((hw->mac.type != ixgbe_mac_82599EB) || 4934 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 4935 return IXGBE_NOT_IMPLEMENTED; 4936 4937 offset = IXGBE_ETS_CFG; 4938 if (hw->eeprom.ops.read(hw, offset, &ets_offset)) 4939 goto eeprom_err; 4940 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 4941 return IXGBE_NOT_IMPLEMENTED; 4942 4943 offset = ets_offset; 4944 if (hw->eeprom.ops.read(hw, offset, &ets_cfg)) 4945 goto eeprom_err; 4946 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT) 4947 != IXGBE_ETS_TYPE_EMC) 4948 return IXGBE_NOT_IMPLEMENTED; 4949 4950 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 4951 IXGBE_ETS_LTHRES_DELTA_SHIFT); 4952 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 4953 4954 for (i = 0; i < num_sensors; i++) { 4955 offset = ets_offset + 1 + i; 4956 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) { 4957 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4958 "eeprom read at offset %d failed", 4959 offset); 4960 continue; 4961 } 4962 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 4963 IXGBE_ETS_DATA_INDEX_SHIFT); 4964 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 4965 IXGBE_ETS_DATA_LOC_SHIFT); 4966 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 4967 4968 hw->phy.ops.write_i2c_byte(hw, 4969 ixgbe_emc_therm_limit[sensor_index], 4970 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 4971 4972 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) { 4973 data->sensor[i].location = sensor_location; 4974 data->sensor[i].caution_thresh = therm_limit; 4975 data->sensor[i].max_op_thresh = therm_limit - 4976 low_thresh_delta; 4977 } 4978 } 4979 return status; 4980 4981 eeprom_err: 4982 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4983 "eeprom read at offset %d failed", offset); 4984 return IXGBE_NOT_IMPLEMENTED; 4985 } 4986 4987 /** 4988 * ixgbe_get_orom_version - Return option ROM from EEPROM 4989 * 4990 * @hw: pointer to hardware structure 4991 * @nvm_ver: pointer to output structure 4992 * 4993 * if valid option ROM version, nvm_ver->or_valid set to true 4994 * else nvm_ver->or_valid is false. 4995 **/ 4996 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 4997 struct ixgbe_nvm_version *nvm_ver) 4998 { 4999 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 5000 5001 nvm_ver->or_valid = false; 5002 /* Option Rom may or may not be present. Start with pointer */ 5003 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 5004 5005 /* make sure offset is valid */ 5006 if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) 5007 return; 5008 5009 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 5010 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 5011 5012 /* option rom exists and is valid */ 5013 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 5014 eeprom_cfg_blkl == NVM_VER_INVALID || 5015 eeprom_cfg_blkh == NVM_VER_INVALID) 5016 return; 5017 5018 nvm_ver->or_valid = true; 5019 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 5020 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 5021 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 5022 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 5023 } 5024 5025 /** 5026 * ixgbe_get_oem_prod_version - Return OEM Product version 5027 * 5028 * @hw: pointer to hardware structure 5029 * @nvm_ver: pointer to output structure 5030 * 5031 * if valid OEM product version, nvm_ver->oem_valid set to true 5032 * else nvm_ver->oem_valid is false. 5033 **/ 5034 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 5035 struct ixgbe_nvm_version *nvm_ver) 5036 { 5037 u16 rel_num, prod_ver, mod_len, cap, offset; 5038 5039 nvm_ver->oem_valid = false; 5040 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 5041 5042 /* Return is offset to OEM Product Version block is invalid */ 5043 if (offset == 0x0 || offset == NVM_INVALID_PTR) 5044 return; 5045 5046 /* Read product version block */ 5047 hw->eeprom.ops.read(hw, offset, &mod_len); 5048 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 5049 5050 /* Return if OEM product version block is invalid */ 5051 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 5052 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 5053 return; 5054 5055 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 5056 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 5057 5058 /* Return if version is invalid */ 5059 if ((rel_num | prod_ver) == 0x0 || 5060 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 5061 return; 5062 5063 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 5064 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 5065 nvm_ver->oem_release = rel_num; 5066 nvm_ver->oem_valid = true; 5067 } 5068 5069 /** 5070 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 5071 * 5072 * @hw: pointer to hardware structure 5073 * @nvm_ver: pointer to output structure 5074 * 5075 * word read errors will return 0xFFFF 5076 **/ 5077 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) 5078 { 5079 u16 etk_id_l, etk_id_h; 5080 5081 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 5082 etk_id_l = NVM_VER_INVALID; 5083 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 5084 etk_id_h = NVM_VER_INVALID; 5085 5086 /* The word order for the version format is determined by high order 5087 * word bit 15. 5088 */ 5089 if ((etk_id_h & NVM_ETK_VALID) == 0) { 5090 nvm_ver->etk_id = etk_id_h; 5091 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 5092 } else { 5093 nvm_ver->etk_id = etk_id_l; 5094 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 5095 } 5096 } 5097 5098 5099 /** 5100 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5101 * @hw: pointer to hardware structure 5102 * @map: pointer to u8 arr for returning map 5103 * 5104 * Read the rtrup2tc HW register and resolve its content into map 5105 **/ 5106 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5107 { 5108 u32 reg, i; 5109 5110 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5111 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5112 map[i] = IXGBE_RTRUP2TC_UP_MASK & 5113 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5114 return; 5115 } 5116 5117 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5118 { 5119 u32 pfdtxgswc; 5120 u32 rxctrl; 5121 5122 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5123 if (rxctrl & IXGBE_RXCTRL_RXEN) { 5124 if (hw->mac.type != ixgbe_mac_82598EB) { 5125 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5126 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5127 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5128 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5129 hw->mac.set_lben = true; 5130 } else { 5131 hw->mac.set_lben = false; 5132 } 5133 } 5134 rxctrl &= ~IXGBE_RXCTRL_RXEN; 5135 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5136 } 5137 } 5138 5139 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5140 { 5141 u32 pfdtxgswc; 5142 u32 rxctrl; 5143 5144 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5145 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5146 5147 if (hw->mac.type != ixgbe_mac_82598EB) { 5148 if (hw->mac.set_lben) { 5149 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5150 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5151 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5152 hw->mac.set_lben = false; 5153 } 5154 } 5155 } 5156 5157 /** 5158 * ixgbe_mng_present - returns true when management capability is present 5159 * @hw: pointer to hardware structure 5160 */ 5161 bool ixgbe_mng_present(struct ixgbe_hw *hw) 5162 { 5163 u32 fwsm; 5164 5165 if (hw->mac.type < ixgbe_mac_82599EB) 5166 return false; 5167 5168 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5169 5170 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 5171 } 5172 5173 /** 5174 * ixgbe_mng_enabled - Is the manageability engine enabled? 5175 * @hw: pointer to hardware structure 5176 * 5177 * Returns true if the manageability engine is enabled. 5178 **/ 5179 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5180 { 5181 u32 fwsm, manc, factps; 5182 5183 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5184 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5185 return false; 5186 5187 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5188 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5189 return false; 5190 5191 if (hw->mac.type <= ixgbe_mac_X540) { 5192 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5193 if (factps & IXGBE_FACTPS_MNGCG) 5194 return false; 5195 } 5196 5197 return true; 5198 } 5199 5200 /** 5201 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5202 * @hw: pointer to hardware structure 5203 * @speed: new link speed 5204 * @autoneg_wait_to_complete: true when waiting for completion is needed 5205 * 5206 * Set the link speed in the MAC and/or PHY register and restarts link. 5207 **/ 5208 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5209 ixgbe_link_speed speed, 5210 bool autoneg_wait_to_complete) 5211 { 5212 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5213 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5214 s32 status = IXGBE_SUCCESS; 5215 u32 speedcnt = 0; 5216 u32 i = 0; 5217 bool autoneg, link_up = false; 5218 5219 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5220 5221 /* Mask off requested but non-supported speeds */ 5222 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5223 if (status != IXGBE_SUCCESS) 5224 return status; 5225 5226 speed &= link_speed; 5227 5228 /* Try each speed one by one, highest priority first. We do this in 5229 * software because 10Gb fiber doesn't support speed autonegotiation. 5230 */ 5231 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5232 speedcnt++; 5233 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5234 5235 /* Set the module link speed */ 5236 switch (hw->phy.media_type) { 5237 case ixgbe_media_type_fiber: 5238 ixgbe_set_rate_select_speed(hw, 5239 IXGBE_LINK_SPEED_10GB_FULL); 5240 break; 5241 case ixgbe_media_type_fiber_qsfp: 5242 /* QSFP module automatically detects MAC link speed */ 5243 break; 5244 default: 5245 DEBUGOUT("Unexpected media type.\n"); 5246 break; 5247 } 5248 5249 /* Allow module to change analog characteristics (1G->10G) */ 5250 msec_delay(40); 5251 5252 status = ixgbe_setup_mac_link(hw, 5253 IXGBE_LINK_SPEED_10GB_FULL, 5254 autoneg_wait_to_complete); 5255 if (status != IXGBE_SUCCESS) 5256 return status; 5257 5258 /* Flap the Tx laser if it has not already been done */ 5259 ixgbe_flap_tx_laser(hw); 5260 5261 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5262 * Section 73.10.2, we may have to wait up to 1000ms if KR is 5263 * attempted. 82599 uses the same timing for 10g SFI. 5264 */ 5265 for (i = 0; i < 10; i++) { 5266 /* Wait for the link partner to also set speed */ 5267 msec_delay(100); 5268 5269 /* If we have link, just jump out */ 5270 status = ixgbe_check_link(hw, &link_speed, 5271 &link_up, false); 5272 if (status != IXGBE_SUCCESS) 5273 return status; 5274 5275 if (link_up) 5276 goto out; 5277 } 5278 } 5279 5280 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5281 speedcnt++; 5282 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5283 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5284 5285 /* Set the module link speed */ 5286 switch (hw->phy.media_type) { 5287 case ixgbe_media_type_fiber: 5288 ixgbe_set_rate_select_speed(hw, 5289 IXGBE_LINK_SPEED_1GB_FULL); 5290 break; 5291 case ixgbe_media_type_fiber_qsfp: 5292 /* QSFP module automatically detects link speed */ 5293 break; 5294 default: 5295 DEBUGOUT("Unexpected media type.\n"); 5296 break; 5297 } 5298 5299 /* Allow module to change analog characteristics (10G->1G) */ 5300 msec_delay(40); 5301 5302 status = ixgbe_setup_mac_link(hw, 5303 IXGBE_LINK_SPEED_1GB_FULL, 5304 autoneg_wait_to_complete); 5305 if (status != IXGBE_SUCCESS) 5306 return status; 5307 5308 /* Flap the Tx laser if it has not already been done */ 5309 ixgbe_flap_tx_laser(hw); 5310 5311 /* Wait for the link partner to also set speed */ 5312 msec_delay(100); 5313 5314 /* If we have link, just jump out */ 5315 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 5316 if (status != IXGBE_SUCCESS) 5317 return status; 5318 5319 if (link_up) 5320 goto out; 5321 } 5322 5323 /* We didn't get link. Configure back to the highest speed we tried, 5324 * (if there was more than one). We call ourselves back with just the 5325 * single highest speed that the user requested. 5326 */ 5327 if (speedcnt > 1) 5328 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5329 highest_link_speed, 5330 autoneg_wait_to_complete); 5331 5332 out: 5333 /* Set autoneg_advertised value based on input link speed */ 5334 hw->phy.autoneg_advertised = 0; 5335 5336 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5337 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5338 5339 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5340 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5341 5342 return status; 5343 } 5344 5345 /** 5346 * ixgbe_set_soft_rate_select_speed - Set module link speed 5347 * @hw: pointer to hardware structure 5348 * @speed: link speed to set 5349 * 5350 * Set module link speed via the soft rate select. 5351 */ 5352 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5353 ixgbe_link_speed speed) 5354 { 5355 s32 status; 5356 u8 rs, eeprom_data; 5357 5358 switch (speed) { 5359 case IXGBE_LINK_SPEED_10GB_FULL: 5360 /* one bit mask same as setting on */ 5361 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5362 break; 5363 case IXGBE_LINK_SPEED_1GB_FULL: 5364 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5365 break; 5366 default: 5367 DEBUGOUT("Invalid fixed module speed\n"); 5368 return; 5369 } 5370 5371 /* Set RS0 */ 5372 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5373 IXGBE_I2C_EEPROM_DEV_ADDR2, 5374 &eeprom_data); 5375 if (status) { 5376 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5377 goto out; 5378 } 5379 5380 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5381 5382 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5383 IXGBE_I2C_EEPROM_DEV_ADDR2, 5384 eeprom_data); 5385 if (status) { 5386 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5387 goto out; 5388 } 5389 5390 /* Set RS1 */ 5391 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5392 IXGBE_I2C_EEPROM_DEV_ADDR2, 5393 &eeprom_data); 5394 if (status) { 5395 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5396 goto out; 5397 } 5398 5399 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5400 5401 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5402 IXGBE_I2C_EEPROM_DEV_ADDR2, 5403 eeprom_data); 5404 if (status) { 5405 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5406 goto out; 5407 } 5408 out: 5409 return; 5410 } 5411