1 /******************************************************************************* 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 #include "ixgbe_type.h" 35 #include "ixgbe_82599.h" 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 #include "ixgbe_phy.h" 39 40 #define IXGBE_82599_MAX_TX_QUEUES 128 41 #define IXGBE_82599_MAX_RX_QUEUES 128 42 #define IXGBE_82599_RAR_ENTRIES 128 43 #define IXGBE_82599_MC_TBL_SIZE 128 44 #define IXGBE_82599_VFT_TBL_SIZE 128 45 #define IXGBE_82599_RX_PB_SIZE 512 46 47 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 48 ixgbe_link_speed speed, 49 bool autoneg_wait_to_complete); 50 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 51 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 52 u16 offset, u16 *data); 53 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 54 u16 words, u16 *data); 55 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 56 u8 dev_addr, u8 *data); 57 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 58 u8 dev_addr, u8 data); 59 60 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 61 { 62 struct ixgbe_mac_info *mac = &hw->mac; 63 64 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 65 66 /* 67 * enable the laser control functions for SFP+ fiber 68 * and MNG not enabled 69 */ 70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 71 !ixgbe_mng_enabled(hw)) { 72 mac->ops.disable_tx_laser = 73 ixgbe_disable_tx_laser_multispeed_fiber; 74 mac->ops.enable_tx_laser = 75 ixgbe_enable_tx_laser_multispeed_fiber; 76 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; 77 78 } else { 79 mac->ops.disable_tx_laser = NULL; 80 mac->ops.enable_tx_laser = NULL; 81 mac->ops.flap_tx_laser = NULL; 82 } 83 84 if (hw->phy.multispeed_fiber) { 85 /* Set up dual speed SFP+ support */ 86 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 87 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 88 mac->ops.set_rate_select_speed = 89 ixgbe_set_hard_rate_select_speed; 90 } else { 91 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 92 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 93 hw->phy.smart_speed == ixgbe_smart_speed_on) && 94 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 95 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed; 96 } else { 97 mac->ops.setup_link = ixgbe_setup_mac_link_82599; 98 } 99 } 100 } 101 102 /** 103 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 104 * @hw: pointer to hardware structure 105 * 106 * Initialize any function pointers that were not able to be 107 * set during init_shared_code because the PHY/SFP type was 108 * not known. Perform the SFP init if necessary. 109 * 110 **/ 111 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 112 { 113 struct ixgbe_mac_info *mac = &hw->mac; 114 struct ixgbe_phy_info *phy = &hw->phy; 115 s32 ret_val = IXGBE_SUCCESS; 116 u32 esdp; 117 118 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 119 120 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 121 /* Store flag indicating I2C bus access control unit. */ 122 hw->phy.qsfp_shared_i2c_bus = TRUE; 123 124 /* Initialize access to QSFP+ I2C bus */ 125 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 126 esdp |= IXGBE_ESDP_SDP0_DIR; 127 esdp &= ~IXGBE_ESDP_SDP1_DIR; 128 esdp &= ~IXGBE_ESDP_SDP0; 129 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 130 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 131 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 132 IXGBE_WRITE_FLUSH(hw); 133 134 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; 135 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; 136 } 137 /* Identify the PHY or SFP module */ 138 ret_val = phy->ops.identify(hw); 139 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 140 goto init_phy_ops_out; 141 142 /* Setup function pointers based on detected SFP module and speeds */ 143 ixgbe_init_mac_link_ops_82599(hw); 144 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 145 hw->phy.ops.reset = NULL; 146 147 /* If copper media, overwrite with copper function pointers */ 148 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 149 mac->ops.setup_link = ixgbe_setup_copper_link_82599; 150 mac->ops.get_link_capabilities = 151 ixgbe_get_copper_link_capabilities_generic; 152 } 153 154 /* Set necessary function pointers based on PHY type */ 155 switch (hw->phy.type) { 156 case ixgbe_phy_tn: 157 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 158 phy->ops.check_link = ixgbe_check_phy_link_tnx; 159 phy->ops.get_firmware_version = 160 ixgbe_get_phy_firmware_version_tnx; 161 break; 162 default: 163 break; 164 } 165 init_phy_ops_out: 166 return ret_val; 167 } 168 169 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 170 { 171 s32 ret_val = IXGBE_SUCCESS; 172 u16 list_offset, data_offset, data_value; 173 174 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 175 176 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 177 ixgbe_init_mac_link_ops_82599(hw); 178 179 hw->phy.ops.reset = NULL; 180 181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 182 &data_offset); 183 if (ret_val != IXGBE_SUCCESS) 184 goto setup_sfp_out; 185 186 /* PHY config will finish before releasing the semaphore */ 187 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 188 IXGBE_GSSR_MAC_CSR_SM); 189 if (ret_val != IXGBE_SUCCESS) { 190 ret_val = IXGBE_ERR_SWFW_SYNC; 191 goto setup_sfp_out; 192 } 193 194 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 195 goto setup_sfp_err; 196 while (data_value != 0xffff) { 197 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 198 IXGBE_WRITE_FLUSH(hw); 199 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 200 goto setup_sfp_err; 201 } 202 203 /* Release the semaphore */ 204 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 205 /* Delay obtaining semaphore again to allow FW access 206 * prot_autoc_write uses the semaphore too. 207 */ 208 msec_delay(hw->eeprom.semaphore_delay); 209 210 /* Restart DSP and set SFI mode */ 211 ret_val = hw->mac.ops.prot_autoc_write(hw, 212 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 213 false); 214 215 if (ret_val) { 216 DEBUGOUT("sfp module setup not complete\n"); 217 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 218 goto setup_sfp_out; 219 } 220 221 } 222 223 setup_sfp_out: 224 return ret_val; 225 226 setup_sfp_err: 227 /* Release the semaphore */ 228 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 229 /* Delay obtaining semaphore again to allow FW access */ 230 msec_delay(hw->eeprom.semaphore_delay); 231 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 232 "eeprom read at offset %d failed", data_offset); 233 return IXGBE_ERR_PHY; 234 } 235 236 /** 237 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 238 * @hw: pointer to hardware structure 239 * @locked: Return the if we locked for this read. 240 * @reg_val: Value we read from AUTOC 241 * 242 * For this part (82599) we need to wrap read-modify-writes with a possible 243 * FW/SW lock. It is assumed this lock will be freed with the next 244 * prot_autoc_write_82599(). 245 */ 246 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 247 { 248 s32 ret_val; 249 250 *locked = false; 251 /* If LESM is on then we need to hold the SW/FW semaphore. */ 252 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 253 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 254 IXGBE_GSSR_MAC_CSR_SM); 255 if (ret_val != IXGBE_SUCCESS) 256 return IXGBE_ERR_SWFW_SYNC; 257 258 *locked = true; 259 } 260 261 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 262 return IXGBE_SUCCESS; 263 } 264 265 /** 266 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 267 * @hw: pointer to hardware structure 268 * @reg_val: value to write to AUTOC 269 * @locked: bool to indicate whether the SW/FW lock was already taken by 270 * previous proc_autoc_read_82599. 271 * 272 * This part (82599) may need to hold the SW/FW lock around all writes to 273 * AUTOC. Likewise after a write we need to do a pipeline reset. 274 */ 275 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 276 { 277 s32 ret_val = IXGBE_SUCCESS; 278 279 /* Blocked by MNG FW so bail */ 280 if (ixgbe_check_reset_blocked(hw)) 281 goto out; 282 283 /* We only need to get the lock if: 284 * - We didn't do it already (in the read part of a read-modify-write) 285 * - LESM is enabled. 286 */ 287 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 288 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 289 IXGBE_GSSR_MAC_CSR_SM); 290 if (ret_val != IXGBE_SUCCESS) 291 return IXGBE_ERR_SWFW_SYNC; 292 293 locked = true; 294 } 295 296 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 297 ret_val = ixgbe_reset_pipeline_82599(hw); 298 299 out: 300 /* Free the SW/FW semaphore as we either grabbed it here or 301 * already had it when this function was called. 302 */ 303 if (locked) 304 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 305 306 return ret_val; 307 } 308 309 /** 310 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 311 * @hw: pointer to hardware structure 312 * 313 * Initialize the function pointers and assign the MAC type for 82599. 314 * Does not touch the hardware. 315 **/ 316 317 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 318 { 319 struct ixgbe_mac_info *mac = &hw->mac; 320 struct ixgbe_phy_info *phy = &hw->phy; 321 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 322 s32 ret_val; 323 324 DEBUGFUNC("ixgbe_init_ops_82599"); 325 326 ixgbe_init_phy_ops_generic(hw); 327 ret_val = ixgbe_init_ops_generic(hw); 328 329 /* PHY */ 330 phy->ops.identify = ixgbe_identify_phy_82599; 331 phy->ops.init = ixgbe_init_phy_ops_82599; 332 333 /* MAC */ 334 mac->ops.reset_hw = ixgbe_reset_hw_82599; 335 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 336 mac->ops.get_media_type = ixgbe_get_media_type_82599; 337 mac->ops.get_supported_physical_layer = 338 ixgbe_get_supported_physical_layer_82599; 339 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 340 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 341 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599; 342 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599; 343 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599; 344 mac->ops.start_hw = ixgbe_start_hw_82599; 345 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 346 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 347 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 348 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 349 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 350 mac->ops.prot_autoc_read = prot_autoc_read_82599; 351 mac->ops.prot_autoc_write = prot_autoc_write_82599; 352 353 /* RAR, Multicast, VLAN */ 354 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 355 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 356 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 357 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 358 mac->rar_highwater = 1; 359 mac->ops.set_vfta = ixgbe_set_vfta_generic; 360 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 361 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 362 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 363 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599; 364 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 365 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 366 367 /* Link */ 368 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599; 369 mac->ops.check_link = ixgbe_check_mac_link_generic; 370 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 371 ixgbe_init_mac_link_ops_82599(hw); 372 373 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 374 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 375 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 376 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 377 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 378 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 379 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 380 381 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 382 & IXGBE_FWSM_MODE_MASK); 383 384 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 385 386 /* EEPROM */ 387 eeprom->ops.read = ixgbe_read_eeprom_82599; 388 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; 389 390 /* Manageability interface */ 391 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 392 393 mac->ops.get_thermal_sensor_data = 394 ixgbe_get_thermal_sensor_data_generic; 395 mac->ops.init_thermal_sensor_thresh = 396 ixgbe_init_thermal_sensor_thresh_generic; 397 398 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 399 400 return ret_val; 401 } 402 403 /** 404 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 405 * @hw: pointer to hardware structure 406 * @speed: pointer to link speed 407 * @autoneg: true when autoneg or autotry is enabled 408 * 409 * Determines the link capabilities by reading the AUTOC register. 410 **/ 411 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 412 ixgbe_link_speed *speed, 413 bool *autoneg) 414 { 415 s32 status = IXGBE_SUCCESS; 416 u32 autoc = 0; 417 418 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 419 420 421 /* Check if 1G SFP module. */ 422 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 423 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 424 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 425 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 426 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 427 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 428 *speed = IXGBE_LINK_SPEED_1GB_FULL; 429 *autoneg = true; 430 goto out; 431 } 432 433 /* 434 * Determine link capabilities based on the stored value of AUTOC, 435 * which represents EEPROM defaults. If AUTOC value has not 436 * been stored, use the current register values. 437 */ 438 if (hw->mac.orig_link_settings_stored) 439 autoc = hw->mac.orig_autoc; 440 else 441 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 442 443 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 444 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 445 *speed = IXGBE_LINK_SPEED_1GB_FULL; 446 *autoneg = false; 447 break; 448 449 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 450 *speed = IXGBE_LINK_SPEED_10GB_FULL; 451 *autoneg = false; 452 break; 453 454 case IXGBE_AUTOC_LMS_1G_AN: 455 *speed = IXGBE_LINK_SPEED_1GB_FULL; 456 *autoneg = true; 457 break; 458 459 case IXGBE_AUTOC_LMS_10G_SERIAL: 460 *speed = IXGBE_LINK_SPEED_10GB_FULL; 461 *autoneg = false; 462 break; 463 464 case IXGBE_AUTOC_LMS_KX4_KX_KR: 465 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 466 *speed = IXGBE_LINK_SPEED_UNKNOWN; 467 if (autoc & IXGBE_AUTOC_KR_SUPP) 468 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 469 if (autoc & IXGBE_AUTOC_KX4_SUPP) 470 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 471 if (autoc & IXGBE_AUTOC_KX_SUPP) 472 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 473 *autoneg = true; 474 break; 475 476 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 477 *speed = IXGBE_LINK_SPEED_100_FULL; 478 if (autoc & IXGBE_AUTOC_KR_SUPP) 479 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 480 if (autoc & IXGBE_AUTOC_KX4_SUPP) 481 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 482 if (autoc & IXGBE_AUTOC_KX_SUPP) 483 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 484 *autoneg = true; 485 break; 486 487 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 488 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 489 *autoneg = false; 490 break; 491 492 default: 493 status = IXGBE_ERR_LINK_SETUP; 494 goto out; 495 break; 496 } 497 498 if (hw->phy.multispeed_fiber) { 499 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 500 IXGBE_LINK_SPEED_1GB_FULL; 501 502 /* QSFP must not enable full auto-negotiation 503 * Limited autoneg is enabled at 1G 504 */ 505 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 506 *autoneg = false; 507 else 508 *autoneg = true; 509 } 510 511 out: 512 return status; 513 } 514 515 /** 516 * ixgbe_get_media_type_82599 - Get media type 517 * @hw: pointer to hardware structure 518 * 519 * Returns the media type (fiber, copper, backplane) 520 **/ 521 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 522 { 523 enum ixgbe_media_type media_type; 524 525 DEBUGFUNC("ixgbe_get_media_type_82599"); 526 527 /* Detect if there is a copper PHY attached. */ 528 switch (hw->phy.type) { 529 case ixgbe_phy_cu_unknown: 530 case ixgbe_phy_tn: 531 media_type = ixgbe_media_type_copper; 532 goto out; 533 default: 534 break; 535 } 536 537 switch (hw->device_id) { 538 case IXGBE_DEV_ID_82599_KX4: 539 case IXGBE_DEV_ID_82599_KX4_MEZZ: 540 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 541 case IXGBE_DEV_ID_82599_KR: 542 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 543 case IXGBE_DEV_ID_82599_XAUI_LOM: 544 /* Default device ID is mezzanine card KX/KX4 */ 545 media_type = ixgbe_media_type_backplane; 546 break; 547 case IXGBE_DEV_ID_82599_SFP: 548 case IXGBE_DEV_ID_82599_SFP_FCOE: 549 case IXGBE_DEV_ID_82599_SFP_EM: 550 case IXGBE_DEV_ID_82599_SFP_SF2: 551 case IXGBE_DEV_ID_82599_SFP_SF_QP: 552 case IXGBE_DEV_ID_82599EN_SFP: 553 media_type = ixgbe_media_type_fiber; 554 break; 555 case IXGBE_DEV_ID_82599_CX4: 556 media_type = ixgbe_media_type_cx4; 557 break; 558 case IXGBE_DEV_ID_82599_T3_LOM: 559 media_type = ixgbe_media_type_copper; 560 break; 561 case IXGBE_DEV_ID_82599_LS: 562 media_type = ixgbe_media_type_fiber_lco; 563 break; 564 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 565 media_type = ixgbe_media_type_fiber_qsfp; 566 break; 567 default: 568 media_type = ixgbe_media_type_unknown; 569 break; 570 } 571 out: 572 return media_type; 573 } 574 575 /** 576 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 577 * @hw: pointer to hardware structure 578 * 579 * Disables link during D3 power down sequence. 580 * 581 **/ 582 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 583 { 584 u32 autoc2_reg; 585 u16 ee_ctrl_2 = 0; 586 587 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); 588 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 589 590 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 591 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 592 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 593 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 594 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 595 } 596 } 597 598 /** 599 * ixgbe_start_mac_link_82599 - Setup MAC link settings 600 * @hw: pointer to hardware structure 601 * @autoneg_wait_to_complete: true when waiting for completion is needed 602 * 603 * Configures link settings based on values in the ixgbe_hw struct. 604 * Restarts the link. Performs autonegotiation if needed. 605 **/ 606 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 607 bool autoneg_wait_to_complete) 608 { 609 u32 autoc_reg; 610 u32 links_reg; 611 u32 i; 612 s32 status = IXGBE_SUCCESS; 613 bool got_lock = false; 614 615 DEBUGFUNC("ixgbe_start_mac_link_82599"); 616 617 618 /* reset_pipeline requires us to hold this lock as it writes to 619 * AUTOC. 620 */ 621 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 622 status = hw->mac.ops.acquire_swfw_sync(hw, 623 IXGBE_GSSR_MAC_CSR_SM); 624 if (status != IXGBE_SUCCESS) 625 goto out; 626 627 got_lock = true; 628 } 629 630 /* Restart link */ 631 ixgbe_reset_pipeline_82599(hw); 632 633 if (got_lock) 634 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 635 636 /* Only poll for autoneg to complete if specified to do so */ 637 if (autoneg_wait_to_complete) { 638 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 639 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 640 IXGBE_AUTOC_LMS_KX4_KX_KR || 641 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 642 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 643 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 644 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 645 links_reg = 0; /* Just in case Autoneg time = 0 */ 646 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 647 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 648 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 649 break; 650 msec_delay(100); 651 } 652 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 653 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 654 DEBUGOUT("Autoneg did not complete.\n"); 655 } 656 } 657 } 658 659 /* Add delay to filter out noises during initial link setup */ 660 msec_delay(50); 661 662 out: 663 return status; 664 } 665 666 /** 667 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 668 * @hw: pointer to hardware structure 669 * 670 * The base drivers may require better control over SFP+ module 671 * PHY states. This includes selectively shutting down the Tx 672 * laser on the PHY, effectively halting physical link. 673 **/ 674 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 675 { 676 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 677 678 /* Blocked by MNG FW so bail */ 679 if (ixgbe_check_reset_blocked(hw)) 680 return; 681 682 /* Disable Tx laser; allow 100us to go dark per spec */ 683 esdp_reg |= IXGBE_ESDP_SDP3; 684 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 685 IXGBE_WRITE_FLUSH(hw); 686 usec_delay(100); 687 } 688 689 /** 690 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 691 * @hw: pointer to hardware structure 692 * 693 * The base drivers may require better control over SFP+ module 694 * PHY states. This includes selectively turning on the Tx 695 * laser on the PHY, effectively starting physical link. 696 **/ 697 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 698 { 699 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 700 701 /* Enable Tx laser; allow 100ms to light up */ 702 esdp_reg &= ~IXGBE_ESDP_SDP3; 703 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 704 IXGBE_WRITE_FLUSH(hw); 705 msec_delay(100); 706 } 707 708 /** 709 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 710 * @hw: pointer to hardware structure 711 * 712 * When the driver changes the link speeds that it can support, 713 * it sets autotry_restart to true to indicate that we need to 714 * initiate a new autotry session with the link partner. To do 715 * so, we set the speed then disable and re-enable the Tx laser, to 716 * alert the link partner that it also needs to restart autotry on its 717 * end. This is consistent with true clause 37 autoneg, which also 718 * involves a loss of signal. 719 **/ 720 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 721 { 722 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 723 724 /* Blocked by MNG FW so bail */ 725 if (ixgbe_check_reset_blocked(hw)) 726 return; 727 728 if (hw->mac.autotry_restart) { 729 ixgbe_disable_tx_laser_multispeed_fiber(hw); 730 ixgbe_enable_tx_laser_multispeed_fiber(hw); 731 hw->mac.autotry_restart = false; 732 } 733 } 734 735 /** 736 * ixgbe_set_hard_rate_select_speed - Set module link speed 737 * @hw: pointer to hardware structure 738 * @speed: link speed to set 739 * 740 * Set module link speed via RS0/RS1 rate select pins. 741 */ 742 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, 743 ixgbe_link_speed speed) 744 { 745 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 746 747 switch (speed) { 748 case IXGBE_LINK_SPEED_10GB_FULL: 749 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 750 break; 751 case IXGBE_LINK_SPEED_1GB_FULL: 752 esdp_reg &= ~IXGBE_ESDP_SDP5; 753 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 754 break; 755 default: 756 DEBUGOUT("Invalid fixed module speed\n"); 757 return; 758 } 759 760 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 761 IXGBE_WRITE_FLUSH(hw); 762 } 763 764 /** 765 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 766 * @hw: pointer to hardware structure 767 * @speed: new link speed 768 * @autoneg_wait_to_complete: true when waiting for completion is needed 769 * 770 * Implements the Intel SmartSpeed algorithm. 771 **/ 772 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 773 ixgbe_link_speed speed, 774 bool autoneg_wait_to_complete) 775 { 776 s32 status = IXGBE_SUCCESS; 777 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 778 s32 i, j; 779 bool link_up = false; 780 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 781 782 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 783 784 /* Set autoneg_advertised value based on input link speed */ 785 hw->phy.autoneg_advertised = 0; 786 787 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 788 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 789 790 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 791 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 792 793 if (speed & IXGBE_LINK_SPEED_100_FULL) 794 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 795 796 /* 797 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 798 * autoneg advertisement if link is unable to be established at the 799 * highest negotiated rate. This can sometimes happen due to integrity 800 * issues with the physical media connection. 801 */ 802 803 /* First, try to get link with full advertisement */ 804 hw->phy.smart_speed_active = false; 805 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 806 status = ixgbe_setup_mac_link_82599(hw, speed, 807 autoneg_wait_to_complete); 808 if (status != IXGBE_SUCCESS) 809 goto out; 810 811 /* 812 * Wait for the controller to acquire link. Per IEEE 802.3ap, 813 * Section 73.10.2, we may have to wait up to 500ms if KR is 814 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 815 * Table 9 in the AN MAS. 816 */ 817 for (i = 0; i < 5; i++) { 818 msec_delay(100); 819 820 /* If we have link, just jump out */ 821 status = ixgbe_check_link(hw, &link_speed, &link_up, 822 false); 823 if (status != IXGBE_SUCCESS) 824 goto out; 825 826 if (link_up) 827 goto out; 828 } 829 } 830 831 /* 832 * We didn't get link. If we advertised KR plus one of KX4/KX 833 * (or BX4/BX), then disable KR and try again. 834 */ 835 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 836 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 837 goto out; 838 839 /* Turn SmartSpeed on to disable KR support */ 840 hw->phy.smart_speed_active = true; 841 status = ixgbe_setup_mac_link_82599(hw, speed, 842 autoneg_wait_to_complete); 843 if (status != IXGBE_SUCCESS) 844 goto out; 845 846 /* 847 * Wait for the controller to acquire link. 600ms will allow for 848 * the AN link_fail_inhibit_timer as well for multiple cycles of 849 * parallel detect, both 10g and 1g. This allows for the maximum 850 * connect attempts as defined in the AN MAS table 73-7. 851 */ 852 for (i = 0; i < 6; i++) { 853 msec_delay(100); 854 855 /* If we have link, just jump out */ 856 status = ixgbe_check_link(hw, &link_speed, &link_up, false); 857 if (status != IXGBE_SUCCESS) 858 goto out; 859 860 if (link_up) 861 goto out; 862 } 863 864 /* We didn't get link. Turn SmartSpeed back off. */ 865 hw->phy.smart_speed_active = false; 866 status = ixgbe_setup_mac_link_82599(hw, speed, 867 autoneg_wait_to_complete); 868 869 out: 870 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 871 DEBUGOUT("Smartspeed has downgraded the link speed " 872 "from the maximum advertised\n"); 873 return status; 874 } 875 876 /** 877 * ixgbe_setup_mac_link_82599 - Set MAC link speed 878 * @hw: pointer to hardware structure 879 * @speed: new link speed 880 * @autoneg_wait_to_complete: true when waiting for completion is needed 881 * 882 * Set the link speed in the AUTOC register and restarts link. 883 **/ 884 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 885 ixgbe_link_speed speed, 886 bool autoneg_wait_to_complete) 887 { 888 bool autoneg = false; 889 s32 status = IXGBE_SUCCESS; 890 u32 pma_pmd_1g, link_mode; 891 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */ 892 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */ 893 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */ 894 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 895 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 896 u32 links_reg; 897 u32 i; 898 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 899 900 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 901 902 /* Check to see if speed passed in is supported. */ 903 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 904 if (status) 905 goto out; 906 907 speed &= link_capabilities; 908 909 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 910 status = IXGBE_ERR_LINK_SETUP; 911 goto out; 912 } 913 914 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 915 if (hw->mac.orig_link_settings_stored) 916 orig_autoc = hw->mac.orig_autoc; 917 else 918 orig_autoc = autoc; 919 920 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 921 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 922 923 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 924 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 925 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 926 /* Set KX4/KX/KR support according to speed requested */ 927 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 928 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 929 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 930 autoc |= IXGBE_AUTOC_KX4_SUPP; 931 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 932 (hw->phy.smart_speed_active == false)) 933 autoc |= IXGBE_AUTOC_KR_SUPP; 934 } 935 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 936 autoc |= IXGBE_AUTOC_KX_SUPP; 937 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 938 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 939 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 940 /* Switch from 1G SFI to 10G SFI if requested */ 941 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 942 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 943 autoc &= ~IXGBE_AUTOC_LMS_MASK; 944 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 945 } 946 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 947 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 948 /* Switch from 10G SFI to 1G SFI if requested */ 949 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 950 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 951 autoc &= ~IXGBE_AUTOC_LMS_MASK; 952 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel) 953 autoc |= IXGBE_AUTOC_LMS_1G_AN; 954 else 955 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 956 } 957 } 958 959 if (autoc != current_autoc) { 960 /* Restart link */ 961 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); 962 if (status != IXGBE_SUCCESS) 963 goto out; 964 965 /* Only poll for autoneg to complete if specified to do so */ 966 if (autoneg_wait_to_complete) { 967 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 968 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 969 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 970 links_reg = 0; /*Just in case Autoneg time=0*/ 971 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 972 links_reg = 973 IXGBE_READ_REG(hw, IXGBE_LINKS); 974 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 975 break; 976 msec_delay(100); 977 } 978 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 979 status = 980 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 981 DEBUGOUT("Autoneg did not complete.\n"); 982 } 983 } 984 } 985 986 /* Add delay to filter out noises during initial link setup */ 987 msec_delay(50); 988 } 989 990 out: 991 return status; 992 } 993 994 /** 995 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 996 * @hw: pointer to hardware structure 997 * @speed: new link speed 998 * @autoneg_wait_to_complete: true if waiting is needed to complete 999 * 1000 * Restarts link on PHY and MAC based on settings passed in. 1001 **/ 1002 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 1003 ixgbe_link_speed speed, 1004 bool autoneg_wait_to_complete) 1005 { 1006 s32 status; 1007 1008 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 1009 1010 /* Setup the PHY according to input speed */ 1011 status = hw->phy.ops.setup_link_speed(hw, speed, 1012 autoneg_wait_to_complete); 1013 /* Set up MAC */ 1014 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 1015 1016 return status; 1017 } 1018 1019 /** 1020 * ixgbe_reset_hw_82599 - Perform hardware reset 1021 * @hw: pointer to hardware structure 1022 * 1023 * Resets the hardware by resetting the transmit and receive units, masks 1024 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1025 * reset. 1026 **/ 1027 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 1028 { 1029 ixgbe_link_speed link_speed; 1030 s32 status; 1031 u32 ctrl = 0; 1032 u32 i, autoc, autoc2; 1033 u32 curr_lms; 1034 bool link_up = false; 1035 1036 DEBUGFUNC("ixgbe_reset_hw_82599"); 1037 1038 /* Call adapter stop to disable tx/rx and clear interrupts */ 1039 status = hw->mac.ops.stop_adapter(hw); 1040 if (status != IXGBE_SUCCESS) 1041 goto reset_hw_out; 1042 1043 /* flush pending Tx transactions */ 1044 ixgbe_clear_tx_pending(hw); 1045 1046 /* PHY ops must be identified and initialized prior to reset */ 1047 1048 /* Identify PHY and related function pointers */ 1049 status = hw->phy.ops.init(hw); 1050 1051 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1052 goto reset_hw_out; 1053 1054 /* Setup SFP module if there is one present. */ 1055 if (hw->phy.sfp_setup_needed) { 1056 status = hw->mac.ops.setup_sfp(hw); 1057 hw->phy.sfp_setup_needed = false; 1058 } 1059 1060 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1061 goto reset_hw_out; 1062 1063 /* Reset PHY */ 1064 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 1065 hw->phy.ops.reset(hw); 1066 1067 /* remember AUTOC from before we reset */ 1068 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 1069 1070 mac_reset_top: 1071 /* 1072 * Issue global reset to the MAC. Needs to be SW reset if link is up. 1073 * If link reset is used when link is up, it might reset the PHY when 1074 * mng is using it. If link is down or the flag to force full link 1075 * reset is set, then perform link reset. 1076 */ 1077 ctrl = IXGBE_CTRL_LNK_RST; 1078 if (!hw->force_full_reset) { 1079 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 1080 if (link_up) 1081 ctrl = IXGBE_CTRL_RST; 1082 } 1083 1084 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1085 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1086 IXGBE_WRITE_FLUSH(hw); 1087 1088 /* Poll for reset bit to self-clear meaning reset is complete */ 1089 for (i = 0; i < 10; i++) { 1090 usec_delay(1); 1091 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1092 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1093 break; 1094 } 1095 1096 if (ctrl & IXGBE_CTRL_RST_MASK) { 1097 status = IXGBE_ERR_RESET_FAILED; 1098 DEBUGOUT("Reset polling failed to complete.\n"); 1099 } 1100 1101 msec_delay(50); 1102 1103 /* 1104 * Double resets are required for recovery from certain error 1105 * conditions. Between resets, it is necessary to stall to 1106 * allow time for any pending HW events to complete. 1107 */ 1108 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1109 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1110 goto mac_reset_top; 1111 } 1112 1113 /* 1114 * Store the original AUTOC/AUTOC2 values if they have not been 1115 * stored off yet. Otherwise restore the stored original 1116 * values since the reset operation sets back to defaults. 1117 */ 1118 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1119 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1120 1121 /* Enable link if disabled in NVM */ 1122 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1123 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1124 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1125 IXGBE_WRITE_FLUSH(hw); 1126 } 1127 1128 if (hw->mac.orig_link_settings_stored == false) { 1129 hw->mac.orig_autoc = autoc; 1130 hw->mac.orig_autoc2 = autoc2; 1131 hw->mac.orig_link_settings_stored = true; 1132 } else { 1133 1134 /* If MNG FW is running on a multi-speed device that 1135 * doesn't autoneg with out driver support we need to 1136 * leave LMS in the state it was before we MAC reset. 1137 * Likewise if we support WoL we don't want change the 1138 * LMS state. 1139 */ 1140 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1141 hw->wol_enabled) 1142 hw->mac.orig_autoc = 1143 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1144 curr_lms; 1145 1146 if (autoc != hw->mac.orig_autoc) { 1147 status = hw->mac.ops.prot_autoc_write(hw, 1148 hw->mac.orig_autoc, 1149 false); 1150 if (status != IXGBE_SUCCESS) 1151 goto reset_hw_out; 1152 } 1153 1154 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1155 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1156 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1157 autoc2 |= (hw->mac.orig_autoc2 & 1158 IXGBE_AUTOC2_UPPER_MASK); 1159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1160 } 1161 } 1162 1163 /* Store the permanent mac address */ 1164 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1165 1166 /* 1167 * Store MAC address from RAR0, clear receive address registers, and 1168 * clear the multicast table. Also reset num_rar_entries to 128, 1169 * since we modify this value when programming the SAN MAC address. 1170 */ 1171 hw->mac.num_rar_entries = 128; 1172 hw->mac.ops.init_rx_addrs(hw); 1173 1174 /* Store the permanent SAN mac address */ 1175 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1176 1177 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1178 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1179 /* Save the SAN MAC RAR index */ 1180 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1181 1182 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 1183 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1184 1185 /* clear VMDq pool/queue selection for this RAR */ 1186 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 1187 IXGBE_CLEAR_VMDQ_ALL); 1188 1189 /* Reserve the last RAR for the SAN MAC address */ 1190 hw->mac.num_rar_entries--; 1191 } 1192 1193 /* Store the alternative WWNN/WWPN prefix */ 1194 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1195 &hw->mac.wwpn_prefix); 1196 1197 reset_hw_out: 1198 return status; 1199 } 1200 1201 /** 1202 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1203 * @hw: pointer to hardware structure 1204 * @fdircmd: current value of FDIRCMD register 1205 */ 1206 STATIC s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1207 { 1208 int i; 1209 1210 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1211 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1212 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1213 return IXGBE_SUCCESS; 1214 usec_delay(10); 1215 } 1216 1217 return IXGBE_ERR_FDIR_CMD_INCOMPLETE; 1218 } 1219 1220 /** 1221 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1222 * @hw: pointer to hardware structure 1223 **/ 1224 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1225 { 1226 s32 err; 1227 int i; 1228 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1229 u32 fdircmd; 1230 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1231 1232 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1233 1234 /* 1235 * Before starting reinitialization process, 1236 * FDIRCMD.CMD must be zero. 1237 */ 1238 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1239 if (err) { 1240 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n"); 1241 return err; 1242 } 1243 1244 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1245 IXGBE_WRITE_FLUSH(hw); 1246 /* 1247 * 82599 adapters flow director init flow cannot be restarted, 1248 * Workaround 82599 silicon errata by performing the following steps 1249 * before re-writing the FDIRCTRL control register with the same value. 1250 * - write 1 to bit 8 of FDIRCMD register & 1251 * - write 0 to bit 8 of FDIRCMD register 1252 */ 1253 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1254 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1255 IXGBE_FDIRCMD_CLEARHT)); 1256 IXGBE_WRITE_FLUSH(hw); 1257 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1258 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1259 ~IXGBE_FDIRCMD_CLEARHT)); 1260 IXGBE_WRITE_FLUSH(hw); 1261 /* 1262 * Clear FDIR Hash register to clear any leftover hashes 1263 * waiting to be programmed. 1264 */ 1265 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1266 IXGBE_WRITE_FLUSH(hw); 1267 1268 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1269 IXGBE_WRITE_FLUSH(hw); 1270 1271 /* Poll init-done after we write FDIRCTRL register */ 1272 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1273 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1274 IXGBE_FDIRCTRL_INIT_DONE) 1275 break; 1276 msec_delay(1); 1277 } 1278 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1279 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1280 return IXGBE_ERR_FDIR_REINIT_FAILED; 1281 } 1282 1283 /* Clear FDIR statistics registers (read to clear) */ 1284 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1285 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1286 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1287 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1288 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1289 1290 return IXGBE_SUCCESS; 1291 } 1292 1293 /** 1294 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1295 * @hw: pointer to hardware structure 1296 * @fdirctrl: value to write to flow director control register 1297 **/ 1298 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1299 { 1300 int i; 1301 1302 DEBUGFUNC("ixgbe_fdir_enable_82599"); 1303 1304 /* Prime the keys for hashing */ 1305 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1306 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1307 1308 /* 1309 * Poll init-done after we write the register. Estimated times: 1310 * 10G: PBALLOC = 11b, timing is 60us 1311 * 1G: PBALLOC = 11b, timing is 600us 1312 * 100M: PBALLOC = 11b, timing is 6ms 1313 * 1314 * Multiple these timings by 4 if under full Rx load 1315 * 1316 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1317 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1318 * this might not finish in our poll time, but we can live with that 1319 * for now. 1320 */ 1321 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1322 IXGBE_WRITE_FLUSH(hw); 1323 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1324 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1325 IXGBE_FDIRCTRL_INIT_DONE) 1326 break; 1327 msec_delay(1); 1328 } 1329 1330 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1331 DEBUGOUT("Flow Director poll time exceeded!\n"); 1332 } 1333 1334 /** 1335 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1336 * @hw: pointer to hardware structure 1337 * @fdirctrl: value to write to flow director control register, initially 1338 * contains just the value of the Rx packet buffer allocation 1339 **/ 1340 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1341 { 1342 DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1343 1344 /* 1345 * Continue setup of fdirctrl register bits: 1346 * Move the flexible bytes to use the ethertype - shift 6 words 1347 * Set the maximum length per hash bucket to 0xA filters 1348 * Send interrupt when 64 filters are left 1349 */ 1350 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1351 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1352 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1353 1354 /* write hashes and fdirctrl register, poll for completion */ 1355 ixgbe_fdir_enable_82599(hw, fdirctrl); 1356 1357 return IXGBE_SUCCESS; 1358 } 1359 1360 /** 1361 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1362 * @hw: pointer to hardware structure 1363 * @fdirctrl: value to write to flow director control register, initially 1364 * contains just the value of the Rx packet buffer allocation 1365 * @cloud_mode: true - cloud mode, false - other mode 1366 **/ 1367 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl, 1368 bool cloud_mode) 1369 { 1370 DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1371 1372 /* 1373 * Continue setup of fdirctrl register bits: 1374 * Turn perfect match filtering on 1375 * Report hash in RSS field of Rx wb descriptor 1376 * Initialize the drop queue to queue 127 1377 * Move the flexible bytes to use the ethertype - shift 6 words 1378 * Set the maximum length per hash bucket to 0xA filters 1379 * Send interrupt when 64 (0x4 * 16) filters are left 1380 */ 1381 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1382 IXGBE_FDIRCTRL_REPORT_STATUS | 1383 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1384 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1385 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1386 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1387 1388 if (cloud_mode) 1389 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD << 1390 IXGBE_FDIRCTRL_FILTERMODE_SHIFT); 1391 1392 /* write hashes and fdirctrl register, poll for completion */ 1393 ixgbe_fdir_enable_82599(hw, fdirctrl); 1394 1395 return IXGBE_SUCCESS; 1396 } 1397 1398 /** 1399 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue 1400 * @hw: pointer to hardware structure 1401 * @dropqueue: Rx queue index used for the dropped packets 1402 **/ 1403 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue) 1404 { 1405 u32 fdirctrl; 1406 1407 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599"); 1408 /* Clear init done bit and drop queue field */ 1409 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1410 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE); 1411 1412 /* Set drop queue */ 1413 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); 1414 if ((hw->mac.type == ixgbe_mac_X550) || 1415 (hw->mac.type == ixgbe_mac_X550EM_x) || 1416 (hw->mac.type == ixgbe_mac_X550EM_a)) 1417 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; 1418 1419 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1420 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1421 IXGBE_FDIRCMD_CLEARHT)); 1422 IXGBE_WRITE_FLUSH(hw); 1423 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1424 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1425 ~IXGBE_FDIRCMD_CLEARHT)); 1426 IXGBE_WRITE_FLUSH(hw); 1427 1428 /* write hashes and fdirctrl register, poll for completion */ 1429 ixgbe_fdir_enable_82599(hw, fdirctrl); 1430 } 1431 1432 /* 1433 * These defines allow us to quickly generate all of the necessary instructions 1434 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1435 * for values 0 through 15 1436 */ 1437 #define IXGBE_ATR_COMMON_HASH_KEY \ 1438 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1439 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1440 do { \ 1441 u32 n = (_n); \ 1442 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1443 common_hash ^= lo_hash_dword >> n; \ 1444 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1445 bucket_hash ^= lo_hash_dword >> n; \ 1446 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1447 sig_hash ^= lo_hash_dword << (16 - n); \ 1448 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1449 common_hash ^= hi_hash_dword >> n; \ 1450 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1451 bucket_hash ^= hi_hash_dword >> n; \ 1452 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1453 sig_hash ^= hi_hash_dword << (16 - n); \ 1454 } while (0) 1455 1456 /** 1457 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1458 * @stream: input bitstream to compute the hash on 1459 * 1460 * This function is almost identical to the function above but contains 1461 * several optimizations such as unwinding all of the loops, letting the 1462 * compiler work out all of the conditional ifs since the keys are static 1463 * defines, and computing two keys at once since the hashed dword stream 1464 * will be the same for both keys. 1465 **/ 1466 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1467 union ixgbe_atr_hash_dword common) 1468 { 1469 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1470 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1471 1472 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1473 flow_vm_vlan = IXGBE_NTOHL(input.dword); 1474 1475 /* generate common hash dword */ 1476 hi_hash_dword = IXGBE_NTOHL(common.dword); 1477 1478 /* low dword is word swapped version of common */ 1479 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1480 1481 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1482 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1483 1484 /* Process bits 0 and 16 */ 1485 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1486 1487 /* 1488 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1489 * delay this because bit 0 of the stream should not be processed 1490 * so we do not add the VLAN until after bit 0 was processed 1491 */ 1492 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1493 1494 /* Process remaining 30 bit of the key */ 1495 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1496 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1497 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1498 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1499 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1500 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1501 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1502 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1503 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1504 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1505 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1506 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1507 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1508 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1509 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1510 1511 /* combine common_hash result with signature and bucket hashes */ 1512 bucket_hash ^= common_hash; 1513 bucket_hash &= IXGBE_ATR_HASH_MASK; 1514 1515 sig_hash ^= common_hash << 16; 1516 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1517 1518 /* return completed signature hash */ 1519 return sig_hash ^ bucket_hash; 1520 } 1521 1522 /** 1523 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1524 * @hw: pointer to hardware structure 1525 * @input: unique input dword 1526 * @common: compressed common input dword 1527 * @queue: queue index to direct traffic to 1528 * 1529 * Note that the tunnel bit in input must not be set when the hardware 1530 * tunneling support does not exist. 1531 **/ 1532 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1533 union ixgbe_atr_hash_dword input, 1534 union ixgbe_atr_hash_dword common, 1535 u8 queue) 1536 { 1537 u64 fdirhashcmd; 1538 u8 flow_type; 1539 bool tunnel; 1540 u32 fdircmd; 1541 1542 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1543 1544 /* 1545 * Get the flow_type in order to program FDIRCMD properly 1546 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1547 * fifth is FDIRCMD.TUNNEL_FILTER 1548 */ 1549 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1550 flow_type = input.formatted.flow_type & 1551 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1552 switch (flow_type) { 1553 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1554 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1555 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1556 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1557 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1558 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1559 break; 1560 default: 1561 DEBUGOUT(" Error on flow type input\n"); 1562 return; 1563 } 1564 1565 /* configure FDIRCMD register */ 1566 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1567 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1568 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1569 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1570 if (tunnel) 1571 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1572 1573 /* 1574 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1575 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1576 */ 1577 fdirhashcmd = (u64)fdircmd << 32; 1578 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1579 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1580 1581 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1582 1583 return; 1584 } 1585 1586 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1587 do { \ 1588 u32 n = (_n); \ 1589 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1590 bucket_hash ^= lo_hash_dword >> n; \ 1591 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1592 bucket_hash ^= hi_hash_dword >> n; \ 1593 } while (0) 1594 1595 /** 1596 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1597 * @atr_input: input bitstream to compute the hash on 1598 * @input_mask: mask for the input bitstream 1599 * 1600 * This function serves two main purposes. First it applies the input_mask 1601 * to the atr_input resulting in a cleaned up atr_input data stream. 1602 * Secondly it computes the hash and stores it in the bkt_hash field at 1603 * the end of the input byte stream. This way it will be available for 1604 * future use without needing to recompute the hash. 1605 **/ 1606 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1607 union ixgbe_atr_input *input_mask) 1608 { 1609 1610 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1611 u32 bucket_hash = 0; 1612 u32 hi_dword = 0; 1613 u32 i = 0; 1614 1615 /* Apply masks to input data */ 1616 for (i = 0; i < 14; i++) 1617 input->dword_stream[i] &= input_mask->dword_stream[i]; 1618 1619 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1620 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]); 1621 1622 /* generate common hash dword */ 1623 for (i = 1; i <= 13; i++) 1624 hi_dword ^= input->dword_stream[i]; 1625 hi_hash_dword = IXGBE_NTOHL(hi_dword); 1626 1627 /* low dword is word swapped version of common */ 1628 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1629 1630 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1631 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1632 1633 /* Process bits 0 and 16 */ 1634 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1635 1636 /* 1637 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1638 * delay this because bit 0 of the stream should not be processed 1639 * so we do not add the VLAN until after bit 0 was processed 1640 */ 1641 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1642 1643 /* Process remaining 30 bit of the key */ 1644 for (i = 1; i <= 15; i++) 1645 IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1646 1647 /* 1648 * Limit hash to 13 bits since max bucket count is 8K. 1649 * Store result at the end of the input stream. 1650 */ 1651 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1652 } 1653 1654 /** 1655 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks 1656 * @input_mask: mask to be bit swapped 1657 * 1658 * The source and destination port masks for flow director are bit swapped 1659 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1660 * generate a correctly swapped value we need to bit swap the mask and that 1661 * is what is accomplished by this function. 1662 **/ 1663 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1664 { 1665 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port); 1666 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1667 mask |= IXGBE_NTOHS(input_mask->formatted.src_port); 1668 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1669 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1670 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1671 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1672 } 1673 1674 /* 1675 * These two macros are meant to address the fact that we have registers 1676 * that are either all or in part big-endian. As a result on big-endian 1677 * systems we will end up byte swapping the value to little-endian before 1678 * it is byte swapped again and written to the hardware in the original 1679 * big-endian format. 1680 */ 1681 #define IXGBE_STORE_AS_BE32(_value) \ 1682 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1683 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1684 1685 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1686 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) 1687 1688 #define IXGBE_STORE_AS_BE16(_value) \ 1689 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1690 1691 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1692 union ixgbe_atr_input *input_mask, bool cloud_mode) 1693 { 1694 /* mask IPv6 since it is currently not supported */ 1695 u32 fdirm = IXGBE_FDIRM_DIPv6; 1696 u32 fdirtcpm; 1697 u32 fdirip6m; 1698 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599"); 1699 1700 /* 1701 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1702 * are zero, then assume a full mask for that field. Also assume that 1703 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1704 * cannot be masked out in this implementation. 1705 * 1706 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1707 * point in time. 1708 */ 1709 1710 /* verify bucket hash is cleared on hash generation */ 1711 if (input_mask->formatted.bkt_hash) 1712 DEBUGOUT(" bucket hash should always be 0 in mask\n"); 1713 1714 /* Program FDIRM and verify partial masks */ 1715 switch (input_mask->formatted.vm_pool & 0x7F) { 1716 case 0x0: 1717 fdirm |= IXGBE_FDIRM_POOL; 1718 case 0x7F: 1719 break; 1720 default: 1721 DEBUGOUT(" Error on vm pool mask\n"); 1722 return IXGBE_ERR_CONFIG; 1723 } 1724 1725 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1726 case 0x0: 1727 fdirm |= IXGBE_FDIRM_L4P; 1728 if (input_mask->formatted.dst_port || 1729 input_mask->formatted.src_port) { 1730 DEBUGOUT(" Error on src/dst port mask\n"); 1731 return IXGBE_ERR_CONFIG; 1732 } 1733 case IXGBE_ATR_L4TYPE_MASK: 1734 break; 1735 default: 1736 DEBUGOUT(" Error on flow type mask\n"); 1737 return IXGBE_ERR_CONFIG; 1738 } 1739 1740 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) { 1741 case 0x0000: 1742 /* mask VLAN ID, fall through to mask VLAN priority */ 1743 fdirm |= IXGBE_FDIRM_VLANID; 1744 case 0x0FFF: 1745 /* mask VLAN priority */ 1746 fdirm |= IXGBE_FDIRM_VLANP; 1747 break; 1748 case 0xE000: 1749 /* mask VLAN ID only, fall through */ 1750 fdirm |= IXGBE_FDIRM_VLANID; 1751 case 0xEFFF: 1752 /* no VLAN fields masked */ 1753 break; 1754 default: 1755 DEBUGOUT(" Error on VLAN mask\n"); 1756 return IXGBE_ERR_CONFIG; 1757 } 1758 1759 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1760 case 0x0000: 1761 /* Mask Flex Bytes, fall through */ 1762 fdirm |= IXGBE_FDIRM_FLEX; 1763 case 0xFFFF: 1764 break; 1765 default: 1766 DEBUGOUT(" Error on flexible byte mask\n"); 1767 return IXGBE_ERR_CONFIG; 1768 } 1769 1770 if (cloud_mode) { 1771 fdirm |= IXGBE_FDIRM_L3P; 1772 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT); 1773 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK; 1774 1775 switch (input_mask->formatted.inner_mac[0] & 0xFF) { 1776 case 0x00: 1777 /* Mask inner MAC, fall through */ 1778 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC; 1779 case 0xFF: 1780 break; 1781 default: 1782 DEBUGOUT(" Error on inner_mac byte mask\n"); 1783 return IXGBE_ERR_CONFIG; 1784 } 1785 1786 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) { 1787 case 0x0: 1788 /* Mask vxlan id */ 1789 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI; 1790 break; 1791 case 0x00FFFFFF: 1792 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24; 1793 break; 1794 case 0xFFFFFFFF: 1795 break; 1796 default: 1797 DEBUGOUT(" Error on TNI/VNI byte mask\n"); 1798 return IXGBE_ERR_CONFIG; 1799 } 1800 1801 switch (input_mask->formatted.tunnel_type & 0xFFFF) { 1802 case 0x0: 1803 /* Mask turnnel type, fall through */ 1804 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE; 1805 case 0xFFFF: 1806 break; 1807 default: 1808 DEBUGOUT(" Error on tunnel type byte mask\n"); 1809 return IXGBE_ERR_CONFIG; 1810 } 1811 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m); 1812 1813 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM, 1814 * FDIRSIP4M and FDIRDIP4M in cloud mode to allow 1815 * L3/L3 packets to tunnel. 1816 */ 1817 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); 1818 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); 1819 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); 1820 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); 1821 switch (hw->mac.type) { 1822 case ixgbe_mac_X550: 1823 case ixgbe_mac_X550EM_x: 1824 case ixgbe_mac_X550EM_a: 1825 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF); 1826 break; 1827 default: 1828 break; 1829 } 1830 } 1831 1832 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1833 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1834 1835 if (!cloud_mode) { 1836 /* store the TCP/UDP port masks, bit reversed from port 1837 * layout */ 1838 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1839 1840 /* write both the same so that UDP and TCP use the same mask */ 1841 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1842 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1843 /* also use it for SCTP */ 1844 switch (hw->mac.type) { 1845 case ixgbe_mac_X550: 1846 case ixgbe_mac_X550EM_x: 1847 case ixgbe_mac_X550EM_a: 1848 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 1849 break; 1850 default: 1851 break; 1852 } 1853 1854 /* store source and destination IP masks (big-enian) */ 1855 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1856 ~input_mask->formatted.src_ip[0]); 1857 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1858 ~input_mask->formatted.dst_ip[0]); 1859 } 1860 return IXGBE_SUCCESS; 1861 } 1862 1863 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1864 union ixgbe_atr_input *input, 1865 u16 soft_id, u8 queue, bool cloud_mode) 1866 { 1867 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1868 u32 addr_low, addr_high; 1869 u32 cloud_type = 0; 1870 s32 err; 1871 1872 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599"); 1873 if (!cloud_mode) { 1874 /* currently IPv6 is not supported, must be programmed with 0 */ 1875 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1876 input->formatted.src_ip[0]); 1877 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1878 input->formatted.src_ip[1]); 1879 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1880 input->formatted.src_ip[2]); 1881 1882 /* record the source address (big-endian) */ 1883 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, 1884 input->formatted.src_ip[0]); 1885 1886 /* record the first 32 bits of the destination address 1887 * (big-endian) */ 1888 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, 1889 input->formatted.dst_ip[0]); 1890 1891 /* record source and destination port (little-endian)*/ 1892 fdirport = IXGBE_NTOHS(input->formatted.dst_port); 1893 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1894 fdirport |= IXGBE_NTOHS(input->formatted.src_port); 1895 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1896 } 1897 1898 /* record VLAN (little-endian) and flex_bytes(big-endian) */ 1899 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1900 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1901 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); 1902 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1903 1904 if (cloud_mode) { 1905 if (input->formatted.tunnel_type != 0) 1906 cloud_type = 0x80000000; 1907 1908 addr_low = ((u32)input->formatted.inner_mac[0] | 1909 ((u32)input->formatted.inner_mac[1] << 8) | 1910 ((u32)input->formatted.inner_mac[2] << 16) | 1911 ((u32)input->formatted.inner_mac[3] << 24)); 1912 addr_high = ((u32)input->formatted.inner_mac[4] | 1913 ((u32)input->formatted.inner_mac[5] << 8)); 1914 cloud_type |= addr_high; 1915 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low); 1916 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type); 1917 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni); 1918 } 1919 1920 /* configure FDIRHASH register */ 1921 fdirhash = input->formatted.bkt_hash; 1922 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1923 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1924 1925 /* 1926 * flush all previous writes to make certain registers are 1927 * programmed prior to issuing the command 1928 */ 1929 IXGBE_WRITE_FLUSH(hw); 1930 1931 /* configure FDIRCMD register */ 1932 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1933 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1934 if (queue == IXGBE_FDIR_DROP_QUEUE) 1935 fdircmd |= IXGBE_FDIRCMD_DROP; 1936 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK) 1937 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1938 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1939 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1940 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1941 1942 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1943 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1944 if (err) { 1945 DEBUGOUT("Flow Director command did not complete!\n"); 1946 return err; 1947 } 1948 1949 return IXGBE_SUCCESS; 1950 } 1951 1952 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1953 union ixgbe_atr_input *input, 1954 u16 soft_id) 1955 { 1956 u32 fdirhash; 1957 u32 fdircmd; 1958 s32 err; 1959 1960 /* configure FDIRHASH register */ 1961 fdirhash = input->formatted.bkt_hash; 1962 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1963 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1964 1965 /* flush hash to HW */ 1966 IXGBE_WRITE_FLUSH(hw); 1967 1968 /* Query if filter is present */ 1969 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1970 1971 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1972 if (err) { 1973 DEBUGOUT("Flow Director command did not complete!\n"); 1974 return err; 1975 } 1976 1977 /* if filter exists in hardware then remove it */ 1978 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1979 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1980 IXGBE_WRITE_FLUSH(hw); 1981 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1982 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1983 } 1984 1985 return IXGBE_SUCCESS; 1986 } 1987 1988 /** 1989 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 1990 * @hw: pointer to hardware structure 1991 * @input: input bitstream 1992 * @input_mask: mask for the input bitstream 1993 * @soft_id: software index for the filters 1994 * @queue: queue index to direct traffic to 1995 * 1996 * Note that the caller to this function must lock before calling, since the 1997 * hardware writes must be protected from one another. 1998 **/ 1999 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 2000 union ixgbe_atr_input *input, 2001 union ixgbe_atr_input *input_mask, 2002 u16 soft_id, u8 queue, bool cloud_mode) 2003 { 2004 s32 err = IXGBE_ERR_CONFIG; 2005 2006 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 2007 2008 /* 2009 * Check flow_type formatting, and bail out before we touch the hardware 2010 * if there's a configuration issue 2011 */ 2012 switch (input->formatted.flow_type) { 2013 case IXGBE_ATR_FLOW_TYPE_IPV4: 2014 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4: 2015 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK; 2016 if (input->formatted.dst_port || input->formatted.src_port) { 2017 DEBUGOUT(" Error on src/dst port\n"); 2018 return IXGBE_ERR_CONFIG; 2019 } 2020 break; 2021 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2022 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4: 2023 if (input->formatted.dst_port || input->formatted.src_port) { 2024 DEBUGOUT(" Error on src/dst port\n"); 2025 return IXGBE_ERR_CONFIG; 2026 } 2027 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2028 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4: 2029 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2030 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4: 2031 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2032 IXGBE_ATR_L4TYPE_MASK; 2033 break; 2034 default: 2035 DEBUGOUT(" Error on flow type input\n"); 2036 return err; 2037 } 2038 2039 /* program input mask into the HW */ 2040 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode); 2041 if (err) 2042 return err; 2043 2044 /* apply mask and compute/store hash */ 2045 ixgbe_atr_compute_perfect_hash_82599(input, input_mask); 2046 2047 /* program filters to filter memory */ 2048 return ixgbe_fdir_write_perfect_filter_82599(hw, input, 2049 soft_id, queue, cloud_mode); 2050 } 2051 2052 /** 2053 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 2054 * @hw: pointer to hardware structure 2055 * @reg: analog register to read 2056 * @val: read value 2057 * 2058 * Performs read operation to Omer analog register specified. 2059 **/ 2060 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 2061 { 2062 u32 core_ctl; 2063 2064 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 2065 2066 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 2067 (reg << 8)); 2068 IXGBE_WRITE_FLUSH(hw); 2069 usec_delay(10); 2070 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 2071 *val = (u8)core_ctl; 2072 2073 return IXGBE_SUCCESS; 2074 } 2075 2076 /** 2077 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 2078 * @hw: pointer to hardware structure 2079 * @reg: atlas register to write 2080 * @val: value to write 2081 * 2082 * Performs write operation to Omer analog register specified. 2083 **/ 2084 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 2085 { 2086 u32 core_ctl; 2087 2088 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 2089 2090 core_ctl = (reg << 8) | val; 2091 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 2092 IXGBE_WRITE_FLUSH(hw); 2093 usec_delay(10); 2094 2095 return IXGBE_SUCCESS; 2096 } 2097 2098 /** 2099 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 2100 * @hw: pointer to hardware structure 2101 * 2102 * Starts the hardware using the generic start_hw function 2103 * and the generation start_hw function. 2104 * Then performs revision-specific operations, if any. 2105 **/ 2106 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 2107 { 2108 s32 ret_val = IXGBE_SUCCESS; 2109 2110 DEBUGFUNC("ixgbe_start_hw_82599"); 2111 2112 ret_val = ixgbe_start_hw_generic(hw); 2113 if (ret_val != IXGBE_SUCCESS) 2114 goto out; 2115 2116 ret_val = ixgbe_start_hw_gen2(hw); 2117 if (ret_val != IXGBE_SUCCESS) 2118 goto out; 2119 2120 /* We need to run link autotry after the driver loads */ 2121 hw->mac.autotry_restart = true; 2122 2123 if (ret_val == IXGBE_SUCCESS) 2124 ret_val = ixgbe_verify_fw_version_82599(hw); 2125 out: 2126 return ret_val; 2127 } 2128 2129 /** 2130 * ixgbe_identify_phy_82599 - Get physical layer module 2131 * @hw: pointer to hardware structure 2132 * 2133 * Determines the physical layer module found on the current adapter. 2134 * If PHY already detected, maintains current PHY type in hw struct, 2135 * otherwise executes the PHY detection routine. 2136 **/ 2137 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 2138 { 2139 s32 status; 2140 2141 DEBUGFUNC("ixgbe_identify_phy_82599"); 2142 2143 /* Detect PHY if not unknown - returns success if already detected. */ 2144 status = ixgbe_identify_phy_generic(hw); 2145 if (status != IXGBE_SUCCESS) { 2146 /* 82599 10GBASE-T requires an external PHY */ 2147 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 2148 return status; 2149 else 2150 status = ixgbe_identify_module_generic(hw); 2151 } 2152 2153 /* Set PHY type none if no PHY detected */ 2154 if (hw->phy.type == ixgbe_phy_unknown) { 2155 hw->phy.type = ixgbe_phy_none; 2156 return IXGBE_SUCCESS; 2157 } 2158 2159 /* Return error if SFP module has been detected but is not supported */ 2160 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 2161 return IXGBE_ERR_SFP_NOT_SUPPORTED; 2162 2163 return status; 2164 } 2165 2166 /** 2167 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 2168 * @hw: pointer to hardware structure 2169 * 2170 * Determines physical layer capabilities of the current configuration. 2171 **/ 2172 u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 2173 { 2174 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2175 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2176 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2177 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 2178 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 2179 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 2180 u16 ext_ability = 0; 2181 2182 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 2183 2184 hw->phy.ops.identify(hw); 2185 2186 switch (hw->phy.type) { 2187 case ixgbe_phy_tn: 2188 case ixgbe_phy_cu_unknown: 2189 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2190 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 2191 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2192 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2193 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2194 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2195 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 2196 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 2197 goto out; 2198 default: 2199 break; 2200 } 2201 2202 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 2203 case IXGBE_AUTOC_LMS_1G_AN: 2204 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 2205 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 2206 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 2207 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 2208 goto out; 2209 } else 2210 /* SFI mode so read SFP module */ 2211 goto sfp_check; 2212 break; 2213 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 2214 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 2215 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 2216 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 2217 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2218 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 2219 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 2220 goto out; 2221 break; 2222 case IXGBE_AUTOC_LMS_10G_SERIAL: 2223 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 2224 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2225 goto out; 2226 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 2227 goto sfp_check; 2228 break; 2229 case IXGBE_AUTOC_LMS_KX4_KX_KR: 2230 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 2231 if (autoc & IXGBE_AUTOC_KX_SUPP) 2232 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2233 if (autoc & IXGBE_AUTOC_KX4_SUPP) 2234 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2235 if (autoc & IXGBE_AUTOC_KR_SUPP) 2236 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2237 goto out; 2238 break; 2239 default: 2240 goto out; 2241 break; 2242 } 2243 2244 sfp_check: 2245 /* SFP check must be done last since DA modules are sometimes used to 2246 * test KR mode - we need to id KR mode correctly before SFP module. 2247 * Call identify_sfp because the pluggable module may have changed */ 2248 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2249 out: 2250 return physical_layer; 2251 } 2252 2253 /** 2254 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2255 * @hw: pointer to hardware structure 2256 * @regval: register value to write to RXCTRL 2257 * 2258 * Enables the Rx DMA unit for 82599 2259 **/ 2260 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2261 { 2262 2263 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2264 2265 /* 2266 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2267 * If traffic is incoming before we enable the Rx unit, it could hang 2268 * the Rx DMA unit. Therefore, make sure the security engine is 2269 * completely disabled prior to enabling the Rx unit. 2270 */ 2271 2272 hw->mac.ops.disable_sec_rx_path(hw); 2273 2274 if (regval & IXGBE_RXCTRL_RXEN) 2275 ixgbe_enable_rx(hw); 2276 else 2277 ixgbe_disable_rx(hw); 2278 2279 hw->mac.ops.enable_sec_rx_path(hw); 2280 2281 return IXGBE_SUCCESS; 2282 } 2283 2284 /** 2285 * ixgbe_verify_fw_version_82599 - verify FW version for 82599 2286 * @hw: pointer to hardware structure 2287 * 2288 * Verifies that installed the firmware version is 0.6 or higher 2289 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2290 * 2291 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2292 * if the FW version is not supported. 2293 **/ 2294 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2295 { 2296 s32 status = IXGBE_ERR_EEPROM_VERSION; 2297 u16 fw_offset, fw_ptp_cfg_offset; 2298 u16 fw_version; 2299 2300 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2301 2302 /* firmware check is only necessary for SFI devices */ 2303 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2304 status = IXGBE_SUCCESS; 2305 goto fw_version_out; 2306 } 2307 2308 /* get the offset to the Firmware Module block */ 2309 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { 2310 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2311 "eeprom read at offset %d failed", IXGBE_FW_PTR); 2312 return IXGBE_ERR_EEPROM_VERSION; 2313 } 2314 2315 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2316 goto fw_version_out; 2317 2318 /* get the offset to the Pass Through Patch Configuration block */ 2319 if (hw->eeprom.ops.read(hw, (fw_offset + 2320 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2321 &fw_ptp_cfg_offset)) { 2322 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2323 "eeprom read at offset %d failed", 2324 fw_offset + 2325 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR); 2326 return IXGBE_ERR_EEPROM_VERSION; 2327 } 2328 2329 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2330 goto fw_version_out; 2331 2332 /* get the firmware version */ 2333 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2334 IXGBE_FW_PATCH_VERSION_4), &fw_version)) { 2335 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2336 "eeprom read at offset %d failed", 2337 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4); 2338 return IXGBE_ERR_EEPROM_VERSION; 2339 } 2340 2341 if (fw_version > 0x5) 2342 status = IXGBE_SUCCESS; 2343 2344 fw_version_out: 2345 return status; 2346 } 2347 2348 /** 2349 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2350 * @hw: pointer to hardware structure 2351 * 2352 * Returns true if the LESM FW module is present and enabled. Otherwise 2353 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 2354 **/ 2355 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2356 { 2357 bool lesm_enabled = false; 2358 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2359 s32 status; 2360 2361 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 2362 2363 /* get the offset to the Firmware Module block */ 2364 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2365 2366 if ((status != IXGBE_SUCCESS) || 2367 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2368 goto out; 2369 2370 /* get the offset to the LESM Parameters block */ 2371 status = hw->eeprom.ops.read(hw, (fw_offset + 2372 IXGBE_FW_LESM_PARAMETERS_PTR), 2373 &fw_lesm_param_offset); 2374 2375 if ((status != IXGBE_SUCCESS) || 2376 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2377 goto out; 2378 2379 /* get the LESM state word */ 2380 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2381 IXGBE_FW_LESM_STATE_1), 2382 &fw_lesm_state); 2383 2384 if ((status == IXGBE_SUCCESS) && 2385 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2386 lesm_enabled = true; 2387 2388 out: 2389 return lesm_enabled; 2390 } 2391 2392 /** 2393 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2394 * fastest available method 2395 * 2396 * @hw: pointer to hardware structure 2397 * @offset: offset of word in EEPROM to read 2398 * @words: number of words 2399 * @data: word(s) read from the EEPROM 2400 * 2401 * Retrieves 16 bit word(s) read from EEPROM 2402 **/ 2403 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2404 u16 words, u16 *data) 2405 { 2406 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2407 s32 ret_val = IXGBE_ERR_CONFIG; 2408 2409 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599"); 2410 2411 /* 2412 * If EEPROM is detected and can be addressed using 14 bits, 2413 * use EERD otherwise use bit bang 2414 */ 2415 if ((eeprom->type == ixgbe_eeprom_spi) && 2416 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) 2417 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, 2418 data); 2419 else 2420 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, 2421 words, 2422 data); 2423 2424 return ret_val; 2425 } 2426 2427 /** 2428 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2429 * fastest available method 2430 * 2431 * @hw: pointer to hardware structure 2432 * @offset: offset of word in the EEPROM to read 2433 * @data: word read from the EEPROM 2434 * 2435 * Reads a 16 bit word from the EEPROM 2436 **/ 2437 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2438 u16 offset, u16 *data) 2439 { 2440 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2441 s32 ret_val = IXGBE_ERR_CONFIG; 2442 2443 DEBUGFUNC("ixgbe_read_eeprom_82599"); 2444 2445 /* 2446 * If EEPROM is detected and can be addressed using 14 bits, 2447 * use EERD otherwise use bit bang 2448 */ 2449 if ((eeprom->type == ixgbe_eeprom_spi) && 2450 (offset <= IXGBE_EERD_MAX_ADDR)) 2451 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 2452 else 2453 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2454 2455 return ret_val; 2456 } 2457 2458 /** 2459 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2460 * 2461 * @hw: pointer to hardware structure 2462 * 2463 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2464 * full pipeline reset. This function assumes the SW/FW lock is held. 2465 **/ 2466 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2467 { 2468 s32 ret_val; 2469 u32 anlp1_reg = 0; 2470 u32 i, autoc_reg, autoc2_reg; 2471 2472 /* Enable link if disabled in NVM */ 2473 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2474 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2475 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2476 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2477 IXGBE_WRITE_FLUSH(hw); 2478 } 2479 2480 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2481 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2482 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2483 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2484 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2485 /* Wait for AN to leave state 0 */ 2486 for (i = 0; i < 10; i++) { 2487 msec_delay(4); 2488 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2489 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2490 break; 2491 } 2492 2493 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2494 DEBUGOUT("auto negotiation not completed\n"); 2495 ret_val = IXGBE_ERR_RESET_FAILED; 2496 goto reset_pipeline_out; 2497 } 2498 2499 ret_val = IXGBE_SUCCESS; 2500 2501 reset_pipeline_out: 2502 /* Write AUTOC register with original LMS field and Restart_AN */ 2503 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2504 IXGBE_WRITE_FLUSH(hw); 2505 2506 return ret_val; 2507 } 2508 2509 /** 2510 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2511 * @hw: pointer to hardware structure 2512 * @byte_offset: byte offset to read 2513 * @data: value read 2514 * 2515 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2516 * a specified device address. 2517 **/ 2518 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2519 u8 dev_addr, u8 *data) 2520 { 2521 u32 esdp; 2522 s32 status; 2523 s32 timeout = 200; 2524 2525 DEBUGFUNC("ixgbe_read_i2c_byte_82599"); 2526 2527 if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 2528 /* Acquire I2C bus ownership. */ 2529 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2530 esdp |= IXGBE_ESDP_SDP0; 2531 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2532 IXGBE_WRITE_FLUSH(hw); 2533 2534 while (timeout) { 2535 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2536 if (esdp & IXGBE_ESDP_SDP1) 2537 break; 2538 2539 msec_delay(5); 2540 timeout--; 2541 } 2542 2543 if (!timeout) { 2544 DEBUGOUT("Driver can't access resource," 2545 " acquiring I2C bus timeout.\n"); 2546 status = IXGBE_ERR_I2C; 2547 goto release_i2c_access; 2548 } 2549 } 2550 2551 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2552 2553 release_i2c_access: 2554 2555 if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 2556 /* Release I2C bus ownership. */ 2557 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2558 esdp &= ~IXGBE_ESDP_SDP0; 2559 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2560 IXGBE_WRITE_FLUSH(hw); 2561 } 2562 2563 return status; 2564 } 2565 2566 /** 2567 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2568 * @hw: pointer to hardware structure 2569 * @byte_offset: byte offset to write 2570 * @data: value to write 2571 * 2572 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2573 * a specified device address. 2574 **/ 2575 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2576 u8 dev_addr, u8 data) 2577 { 2578 u32 esdp; 2579 s32 status; 2580 s32 timeout = 200; 2581 2582 DEBUGFUNC("ixgbe_write_i2c_byte_82599"); 2583 2584 if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 2585 /* Acquire I2C bus ownership. */ 2586 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2587 esdp |= IXGBE_ESDP_SDP0; 2588 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2589 IXGBE_WRITE_FLUSH(hw); 2590 2591 while (timeout) { 2592 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2593 if (esdp & IXGBE_ESDP_SDP1) 2594 break; 2595 2596 msec_delay(5); 2597 timeout--; 2598 } 2599 2600 if (!timeout) { 2601 DEBUGOUT("Driver can't access resource," 2602 " acquiring I2C bus timeout.\n"); 2603 status = IXGBE_ERR_I2C; 2604 goto release_i2c_access; 2605 } 2606 } 2607 2608 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2609 2610 release_i2c_access: 2611 2612 if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 2613 /* Release I2C bus ownership. */ 2614 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2615 esdp &= ~IXGBE_ESDP_SDP0; 2616 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2617 IXGBE_WRITE_FLUSH(hw); 2618 } 2619 2620 return status; 2621 } 2622