1*4418919fSjohnjiang /* SPDX-License-Identifier: BSD-3-Clause 2*4418919fSjohnjiang * Copyright(c) 2010-2018 Intel Corporation 3*4418919fSjohnjiang */ 4*4418919fSjohnjiang 5*4418919fSjohnjiang #ifndef _IFPGA_RAWDEV_API_H_ 6*4418919fSjohnjiang #define _IFPGA_RAWDEV_API_H_ 7*4418919fSjohnjiang 8*4418919fSjohnjiang #include <rte_ether.h> 9*4418919fSjohnjiang 10*4418919fSjohnjiang enum ifpga_rawdev_retimer_media_type { 11*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_UNKNOWN = 0, 12*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_100GBASE_LR4, 13*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_100GBASE_SR4, 14*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_100GBASE_CR4, 15*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_40GBASE_LR4, 16*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_400GBASE_SR4, 17*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_40GBASE_CR4, 18*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_25GBASE_SR, 19*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_25GBASE_CR, 20*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_10GBASE_LR, 21*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_10GBASE_SR, 22*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_10GBASE_DAC, 23*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MEDIA_TYPE_DEFAULT 24*4418919fSjohnjiang }; 25*4418919fSjohnjiang 26*4418919fSjohnjiang enum ifpga_rawdev_retimer_mac_type { 27*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN = 0, 28*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MAC_TYPE_100GE_CAUI, 29*4418919fSjohnjiang IFPGA_RAWDEVG_RETIMER_MAC_TYPE_40GE_XLAUI, 30*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI, 31*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI, 32*4418919fSjohnjiang IFPGA_RAWDEV_RETIMER_MAC_TYPE_DEFAULT 33*4418919fSjohnjiang }; 34*4418919fSjohnjiang 35*4418919fSjohnjiang #define IFPGA_RAWDEV_LINK_SPEED_10GB_SHIFT 0x0 36*4418919fSjohnjiang #define IFPGA_RAWDEV_LINK_SPEED_40GB_SHIFT 0x1 37*4418919fSjohnjiang #define IFPGA_RAWDEV_LINK_SPEED_25GB_SHIFT 0x2 38*4418919fSjohnjiang 39*4418919fSjohnjiang enum ifpga_rawdev_link_speed { 40*4418919fSjohnjiang IFPGA_RAWDEV_LINK_SPEED_UNKNOWN = 0, 41*4418919fSjohnjiang IFPGA_RAWDEV_LINK_SPEED_10GB = 42*4418919fSjohnjiang (1 << IFPGA_RAWDEV_LINK_SPEED_10GB_SHIFT), 43*4418919fSjohnjiang IFPGA_RAWDEV_LINK_SPEED_40GB = 44*4418919fSjohnjiang (1 << IFPGA_RAWDEV_LINK_SPEED_40GB_SHIFT), 45*4418919fSjohnjiang IFPGA_RAWDEV_LINK_SPEED_25GB = 46*4418919fSjohnjiang (1 << IFPGA_RAWDEV_LINK_SPEED_25GB_SHIFT), 47*4418919fSjohnjiang }; 48*4418919fSjohnjiang 49*4418919fSjohnjiang struct ifpga_rawdevg_retimer_info { 50*4418919fSjohnjiang int retimer_num; 51*4418919fSjohnjiang int port_num; 52*4418919fSjohnjiang enum ifpga_rawdev_retimer_media_type media_type; 53*4418919fSjohnjiang enum ifpga_rawdev_retimer_mac_type mac_type; 54*4418919fSjohnjiang }; 55*4418919fSjohnjiang 56*4418919fSjohnjiang struct ifpga_rawdevg_link_info { 57*4418919fSjohnjiang int port; 58*4418919fSjohnjiang int link_up; 59*4418919fSjohnjiang enum ifpga_rawdev_link_speed link_speed; 60*4418919fSjohnjiang }; 61*4418919fSjohnjiang 62*4418919fSjohnjiang struct ipn3ke_pub_func { 63*4418919fSjohnjiang struct ifpga_rawdev *(*get_ifpga_rawdev)(const struct rte_rawdev *rdv); 64*4418919fSjohnjiang int (*set_i40e_sw_dev)(uint16_t port_id, struct rte_eth_dev *sw_dev); 65*4418919fSjohnjiang }; 66*4418919fSjohnjiang 67*4418919fSjohnjiang /** 68*4418919fSjohnjiang * @internal 69*4418919fSjohnjiang * The publid functions of bridge PAC N3000 FPGA and I40e. 70*4418919fSjohnjiang */ 71*4418919fSjohnjiang extern struct ipn3ke_pub_func ipn3ke_bridge_func; 72*4418919fSjohnjiang 73*4418919fSjohnjiang 74*4418919fSjohnjiang #endif /* _IFPGA_RAWDEV_H_ */ 75