1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 5 #include <rte_string_fns.h> 6 #include <rte_ethdev_pci.h> 7 8 #include <stdio.h> 9 #include <sys/types.h> 10 #include <sys/stat.h> 11 #include <unistd.h> 12 13 #include "base/ice_sched.h" 14 #include "base/ice_flow.h" 15 #include "base/ice_dcb.h" 16 #include "base/ice_common.h" 17 18 #include "rte_pmd_ice.h" 19 #include "ice_ethdev.h" 20 #include "ice_rxtx.h" 21 #include "ice_generic_flow.h" 22 23 /* devargs */ 24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" 25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" 26 #define ICE_FLOW_MARK_SUPPORT_ARG "flow-mark-support" 27 #define ICE_PROTO_XTR_ARG "proto_xtr" 28 29 static const char * const ice_valid_args[] = { 30 ICE_SAFE_MODE_SUPPORT_ARG, 31 ICE_PIPELINE_MODE_SUPPORT_ARG, 32 ICE_FLOW_MARK_SUPPORT_ARG, 33 ICE_PROTO_XTR_ARG, 34 NULL 35 }; 36 37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = { 38 .name = "ice_dynfield_proto_xtr_metadata", 39 .size = sizeof(uint32_t), 40 .align = __alignof__(uint32_t), 41 .flags = 0, 42 }; 43 44 struct proto_xtr_ol_flag { 45 const struct rte_mbuf_dynflag param; 46 uint64_t *ol_flag; 47 bool required; 48 }; 49 50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = { 51 [PROTO_XTR_VLAN] = { 52 .param = { .name = "ice_dynflag_proto_xtr_vlan" }, 53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask }, 54 [PROTO_XTR_IPV4] = { 55 .param = { .name = "ice_dynflag_proto_xtr_ipv4" }, 56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask }, 57 [PROTO_XTR_IPV6] = { 58 .param = { .name = "ice_dynflag_proto_xtr_ipv6" }, 59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask }, 60 [PROTO_XTR_IPV6_FLOW] = { 61 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" }, 62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask }, 63 [PROTO_XTR_TCP] = { 64 .param = { .name = "ice_dynflag_proto_xtr_tcp" }, 65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask }, 66 }; 67 68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100 69 70 /* DDP package search path */ 71 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg" 72 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg" 73 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/" 74 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/" 75 76 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package" 77 #define ICE_COMMS_PKG_NAME "ICE COMMS Package" 78 #define ICE_MAX_PKG_FILENAME_SIZE 256 79 #define ICE_MAX_RES_DESC_NUM 1024 80 81 int ice_logtype_init; 82 int ice_logtype_driver; 83 #ifdef RTE_LIBRTE_ICE_DEBUG_RX 84 int ice_logtype_rx; 85 #endif 86 #ifdef RTE_LIBRTE_ICE_DEBUG_TX 87 int ice_logtype_tx; 88 #endif 89 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE 90 int ice_logtype_tx_free; 91 #endif 92 93 static int ice_dev_configure(struct rte_eth_dev *dev); 94 static int ice_dev_start(struct rte_eth_dev *dev); 95 static void ice_dev_stop(struct rte_eth_dev *dev); 96 static void ice_dev_close(struct rte_eth_dev *dev); 97 static int ice_dev_reset(struct rte_eth_dev *dev); 98 static int ice_dev_info_get(struct rte_eth_dev *dev, 99 struct rte_eth_dev_info *dev_info); 100 static int ice_link_update(struct rte_eth_dev *dev, 101 int wait_to_complete); 102 static int ice_dev_set_link_up(struct rte_eth_dev *dev); 103 static int ice_dev_set_link_down(struct rte_eth_dev *dev); 104 105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask); 107 static int ice_rss_reta_update(struct rte_eth_dev *dev, 108 struct rte_eth_rss_reta_entry64 *reta_conf, 109 uint16_t reta_size); 110 static int ice_rss_reta_query(struct rte_eth_dev *dev, 111 struct rte_eth_rss_reta_entry64 *reta_conf, 112 uint16_t reta_size); 113 static int ice_rss_hash_update(struct rte_eth_dev *dev, 114 struct rte_eth_rss_conf *rss_conf); 115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev, 116 struct rte_eth_rss_conf *rss_conf); 117 static int ice_promisc_enable(struct rte_eth_dev *dev); 118 static int ice_promisc_disable(struct rte_eth_dev *dev); 119 static int ice_allmulti_enable(struct rte_eth_dev *dev); 120 static int ice_allmulti_disable(struct rte_eth_dev *dev); 121 static int ice_vlan_filter_set(struct rte_eth_dev *dev, 122 uint16_t vlan_id, 123 int on); 124 static int ice_macaddr_set(struct rte_eth_dev *dev, 125 struct rte_ether_addr *mac_addr); 126 static int ice_macaddr_add(struct rte_eth_dev *dev, 127 struct rte_ether_addr *mac_addr, 128 __rte_unused uint32_t index, 129 uint32_t pool); 130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); 131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 132 uint16_t queue_id); 133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 134 uint16_t queue_id); 135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 136 size_t fw_size); 137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev, 138 uint16_t pvid, int on); 139 static int ice_get_eeprom_length(struct rte_eth_dev *dev); 140 static int ice_get_eeprom(struct rte_eth_dev *dev, 141 struct rte_dev_eeprom_info *eeprom); 142 static int ice_stats_get(struct rte_eth_dev *dev, 143 struct rte_eth_stats *stats); 144 static int ice_stats_reset(struct rte_eth_dev *dev); 145 static int ice_xstats_get(struct rte_eth_dev *dev, 146 struct rte_eth_xstat *xstats, unsigned int n); 147 static int ice_xstats_get_names(struct rte_eth_dev *dev, 148 struct rte_eth_xstat_name *xstats_names, 149 unsigned int limit); 150 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev, 151 enum rte_filter_type filter_type, 152 enum rte_filter_op filter_op, 153 void *arg); 154 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 155 struct rte_eth_udp_tunnel *udp_tunnel); 156 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 157 struct rte_eth_udp_tunnel *udp_tunnel); 158 159 static const struct rte_pci_id pci_id_ice_map[] = { 160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) }, 161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) }, 162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) }, 163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) }, 164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) }, 165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) }, 166 { .vendor_id = 0, /* sentinel */ }, 167 }; 168 169 static const struct eth_dev_ops ice_eth_dev_ops = { 170 .dev_configure = ice_dev_configure, 171 .dev_start = ice_dev_start, 172 .dev_stop = ice_dev_stop, 173 .dev_close = ice_dev_close, 174 .dev_reset = ice_dev_reset, 175 .dev_set_link_up = ice_dev_set_link_up, 176 .dev_set_link_down = ice_dev_set_link_down, 177 .rx_queue_start = ice_rx_queue_start, 178 .rx_queue_stop = ice_rx_queue_stop, 179 .tx_queue_start = ice_tx_queue_start, 180 .tx_queue_stop = ice_tx_queue_stop, 181 .rx_queue_setup = ice_rx_queue_setup, 182 .rx_queue_release = ice_rx_queue_release, 183 .tx_queue_setup = ice_tx_queue_setup, 184 .tx_queue_release = ice_tx_queue_release, 185 .dev_infos_get = ice_dev_info_get, 186 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get, 187 .link_update = ice_link_update, 188 .mtu_set = ice_mtu_set, 189 .mac_addr_set = ice_macaddr_set, 190 .mac_addr_add = ice_macaddr_add, 191 .mac_addr_remove = ice_macaddr_remove, 192 .vlan_filter_set = ice_vlan_filter_set, 193 .vlan_offload_set = ice_vlan_offload_set, 194 .reta_update = ice_rss_reta_update, 195 .reta_query = ice_rss_reta_query, 196 .rss_hash_update = ice_rss_hash_update, 197 .rss_hash_conf_get = ice_rss_hash_conf_get, 198 .promiscuous_enable = ice_promisc_enable, 199 .promiscuous_disable = ice_promisc_disable, 200 .allmulticast_enable = ice_allmulti_enable, 201 .allmulticast_disable = ice_allmulti_disable, 202 .rx_queue_intr_enable = ice_rx_queue_intr_enable, 203 .rx_queue_intr_disable = ice_rx_queue_intr_disable, 204 .fw_version_get = ice_fw_version_get, 205 .vlan_pvid_set = ice_vlan_pvid_set, 206 .rxq_info_get = ice_rxq_info_get, 207 .txq_info_get = ice_txq_info_get, 208 .rx_burst_mode_get = ice_rx_burst_mode_get, 209 .tx_burst_mode_get = ice_tx_burst_mode_get, 210 .get_eeprom_length = ice_get_eeprom_length, 211 .get_eeprom = ice_get_eeprom, 212 .rx_queue_count = ice_rx_queue_count, 213 .rx_descriptor_status = ice_rx_descriptor_status, 214 .tx_descriptor_status = ice_tx_descriptor_status, 215 .stats_get = ice_stats_get, 216 .stats_reset = ice_stats_reset, 217 .xstats_get = ice_xstats_get, 218 .xstats_get_names = ice_xstats_get_names, 219 .xstats_reset = ice_stats_reset, 220 .filter_ctrl = ice_dev_filter_ctrl, 221 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add, 222 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del, 223 }; 224 225 /* store statistics names and its offset in stats structure */ 226 struct ice_xstats_name_off { 227 char name[RTE_ETH_XSTATS_NAME_SIZE]; 228 unsigned int offset; 229 }; 230 231 static const struct ice_xstats_name_off ice_stats_strings[] = { 232 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)}, 233 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)}, 234 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)}, 235 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)}, 236 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats, 237 rx_unknown_protocol)}, 238 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)}, 239 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)}, 240 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)}, 241 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)}, 242 }; 243 244 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \ 245 sizeof(ice_stats_strings[0])) 246 247 static const struct ice_xstats_name_off ice_hw_port_strings[] = { 248 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats, 249 tx_dropped_link_down)}, 250 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)}, 251 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats, 252 illegal_bytes)}, 253 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)}, 254 {"mac_local_errors", offsetof(struct ice_hw_port_stats, 255 mac_local_faults)}, 256 {"mac_remote_errors", offsetof(struct ice_hw_port_stats, 257 mac_remote_faults)}, 258 {"rx_len_errors", offsetof(struct ice_hw_port_stats, 259 rx_len_errors)}, 260 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)}, 261 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)}, 262 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)}, 263 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)}, 264 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)}, 265 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 266 rx_size_127)}, 267 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 268 rx_size_255)}, 269 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 270 rx_size_511)}, 271 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 272 rx_size_1023)}, 273 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 274 rx_size_1522)}, 275 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 276 rx_size_big)}, 277 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats, 278 rx_undersize)}, 279 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats, 280 rx_oversize)}, 281 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats, 282 mac_short_pkt_dropped)}, 283 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats, 284 rx_fragments)}, 285 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)}, 286 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)}, 287 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats, 288 tx_size_127)}, 289 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats, 290 tx_size_255)}, 291 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats, 292 tx_size_511)}, 293 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats, 294 tx_size_1023)}, 295 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats, 296 tx_size_1522)}, 297 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats, 298 tx_size_big)}, 299 }; 300 301 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \ 302 sizeof(ice_hw_port_strings[0])) 303 304 static void 305 ice_init_controlq_parameter(struct ice_hw *hw) 306 { 307 /* fields for adminq */ 308 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN; 309 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN; 310 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ; 311 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ; 312 313 /* fields for mailboxq, DPDK used as PF host */ 314 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN; 315 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN; 316 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ; 317 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ; 318 } 319 320 static int 321 lookup_proto_xtr_type(const char *xtr_name) 322 { 323 static struct { 324 const char *name; 325 enum proto_xtr_type type; 326 } xtr_type_map[] = { 327 { "vlan", PROTO_XTR_VLAN }, 328 { "ipv4", PROTO_XTR_IPV4 }, 329 { "ipv6", PROTO_XTR_IPV6 }, 330 { "ipv6_flow", PROTO_XTR_IPV6_FLOW }, 331 { "tcp", PROTO_XTR_TCP }, 332 }; 333 uint32_t i; 334 335 for (i = 0; i < RTE_DIM(xtr_type_map); i++) { 336 if (strcmp(xtr_name, xtr_type_map[i].name) == 0) 337 return xtr_type_map[i].type; 338 } 339 340 return -1; 341 } 342 343 /* 344 * Parse elem, the elem could be single number/range or '(' ')' group 345 * 1) A single number elem, it's just a simple digit. e.g. 9 346 * 2) A single range elem, two digits with a '-' between. e.g. 2-6 347 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6) 348 * Within group elem, '-' used for a range separator; 349 * ',' used for a single number. 350 */ 351 static int 352 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs) 353 { 354 const char *str = input; 355 char *end = NULL; 356 uint32_t min, max; 357 uint32_t idx; 358 359 while (isblank(*str)) 360 str++; 361 362 if (!isdigit(*str) && *str != '(') 363 return -1; 364 365 /* process single number or single range of number */ 366 if (*str != '(') { 367 errno = 0; 368 idx = strtoul(str, &end, 10); 369 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 370 return -1; 371 372 while (isblank(*end)) 373 end++; 374 375 min = idx; 376 max = idx; 377 378 /* process single <number>-<number> */ 379 if (*end == '-') { 380 end++; 381 while (isblank(*end)) 382 end++; 383 if (!isdigit(*end)) 384 return -1; 385 386 errno = 0; 387 idx = strtoul(end, &end, 10); 388 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 389 return -1; 390 391 max = idx; 392 while (isblank(*end)) 393 end++; 394 } 395 396 if (*end != ':') 397 return -1; 398 399 for (idx = RTE_MIN(min, max); 400 idx <= RTE_MAX(min, max); idx++) 401 devargs->proto_xtr[idx] = xtr_type; 402 403 return 0; 404 } 405 406 /* process set within bracket */ 407 str++; 408 while (isblank(*str)) 409 str++; 410 if (*str == '\0') 411 return -1; 412 413 min = ICE_MAX_QUEUE_NUM; 414 do { 415 /* go ahead to the first digit */ 416 while (isblank(*str)) 417 str++; 418 if (!isdigit(*str)) 419 return -1; 420 421 /* get the digit value */ 422 errno = 0; 423 idx = strtoul(str, &end, 10); 424 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM) 425 return -1; 426 427 /* go ahead to separator '-',',' and ')' */ 428 while (isblank(*end)) 429 end++; 430 if (*end == '-') { 431 if (min == ICE_MAX_QUEUE_NUM) 432 min = idx; 433 else /* avoid continuous '-' */ 434 return -1; 435 } else if (*end == ',' || *end == ')') { 436 max = idx; 437 if (min == ICE_MAX_QUEUE_NUM) 438 min = idx; 439 440 for (idx = RTE_MIN(min, max); 441 idx <= RTE_MAX(min, max); idx++) 442 devargs->proto_xtr[idx] = xtr_type; 443 444 min = ICE_MAX_QUEUE_NUM; 445 } else { 446 return -1; 447 } 448 449 str = end + 1; 450 } while (*end != ')' && *end != '\0'); 451 452 return 0; 453 } 454 455 static int 456 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs) 457 { 458 const char *queue_start; 459 uint32_t idx; 460 int xtr_type; 461 char xtr_name[32]; 462 463 while (isblank(*queues)) 464 queues++; 465 466 if (*queues != '[') { 467 xtr_type = lookup_proto_xtr_type(queues); 468 if (xtr_type < 0) 469 return -1; 470 471 devargs->proto_xtr_dflt = xtr_type; 472 473 return 0; 474 } 475 476 queues++; 477 do { 478 while (isblank(*queues)) 479 queues++; 480 if (*queues == '\0') 481 return -1; 482 483 queue_start = queues; 484 485 /* go across a complete bracket */ 486 if (*queue_start == '(') { 487 queues += strcspn(queues, ")"); 488 if (*queues != ')') 489 return -1; 490 } 491 492 /* scan the separator ':' */ 493 queues += strcspn(queues, ":"); 494 if (*queues++ != ':') 495 return -1; 496 while (isblank(*queues)) 497 queues++; 498 499 for (idx = 0; ; idx++) { 500 if (isblank(queues[idx]) || 501 queues[idx] == ',' || 502 queues[idx] == ']' || 503 queues[idx] == '\0') 504 break; 505 506 if (idx > sizeof(xtr_name) - 2) 507 return -1; 508 509 xtr_name[idx] = queues[idx]; 510 } 511 xtr_name[idx] = '\0'; 512 xtr_type = lookup_proto_xtr_type(xtr_name); 513 if (xtr_type < 0) 514 return -1; 515 516 queues += idx; 517 518 while (isblank(*queues) || *queues == ',' || *queues == ']') 519 queues++; 520 521 if (parse_queue_set(queue_start, xtr_type, devargs) < 0) 522 return -1; 523 } while (*queues != '\0'); 524 525 return 0; 526 } 527 528 static int 529 handle_proto_xtr_arg(__rte_unused const char *key, const char *value, 530 void *extra_args) 531 { 532 struct ice_devargs *devargs = extra_args; 533 534 if (value == NULL || extra_args == NULL) 535 return -EINVAL; 536 537 if (parse_queue_proto_xtr(value, devargs) < 0) { 538 PMD_DRV_LOG(ERR, 539 "The protocol extraction parameter is wrong : '%s'", 540 value); 541 return -1; 542 } 543 544 return 0; 545 } 546 547 static bool 548 ice_proto_xtr_support(struct ice_hw *hw) 549 { 550 #define FLX_REG(val, fld, idx) \ 551 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \ 552 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S) 553 static struct { 554 uint32_t rxdid; 555 uint16_t protid_0; 556 uint16_t protid_1; 557 } xtr_sets[] = { 558 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O }, 559 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S, 560 ICE_PROT_IPV4_OF_OR_S }, 561 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S, 562 ICE_PROT_IPV6_OF_OR_S }, 563 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S, 564 ICE_PROT_IPV6_OF_OR_S }, 565 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL }, 566 }; 567 uint32_t i; 568 569 for (i = 0; i < RTE_DIM(xtr_sets); i++) { 570 uint32_t rxdid = xtr_sets[i].rxdid; 571 uint32_t v; 572 573 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) { 574 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid)); 575 576 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 || 577 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT) 578 return false; 579 } 580 581 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) { 582 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid)); 583 584 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 || 585 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT) 586 return false; 587 } 588 } 589 590 return true; 591 } 592 593 static int 594 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base, 595 uint32_t num) 596 { 597 struct pool_entry *entry; 598 599 if (!pool || !num) 600 return -EINVAL; 601 602 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 603 if (!entry) { 604 PMD_INIT_LOG(ERR, 605 "Failed to allocate memory for resource pool"); 606 return -ENOMEM; 607 } 608 609 /* queue heap initialize */ 610 pool->num_free = num; 611 pool->num_alloc = 0; 612 pool->base = base; 613 LIST_INIT(&pool->alloc_list); 614 LIST_INIT(&pool->free_list); 615 616 /* Initialize element */ 617 entry->base = 0; 618 entry->len = num; 619 620 LIST_INSERT_HEAD(&pool->free_list, entry, next); 621 return 0; 622 } 623 624 static int 625 ice_res_pool_alloc(struct ice_res_pool_info *pool, 626 uint16_t num) 627 { 628 struct pool_entry *entry, *valid_entry; 629 630 if (!pool || !num) { 631 PMD_INIT_LOG(ERR, "Invalid parameter"); 632 return -EINVAL; 633 } 634 635 if (pool->num_free < num) { 636 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u", 637 num, pool->num_free); 638 return -ENOMEM; 639 } 640 641 valid_entry = NULL; 642 /* Lookup in free list and find most fit one */ 643 LIST_FOREACH(entry, &pool->free_list, next) { 644 if (entry->len >= num) { 645 /* Find best one */ 646 if (entry->len == num) { 647 valid_entry = entry; 648 break; 649 } 650 if (!valid_entry || 651 valid_entry->len > entry->len) 652 valid_entry = entry; 653 } 654 } 655 656 /* Not find one to satisfy the request, return */ 657 if (!valid_entry) { 658 PMD_INIT_LOG(ERR, "No valid entry found"); 659 return -ENOMEM; 660 } 661 /** 662 * The entry have equal queue number as requested, 663 * remove it from alloc_list. 664 */ 665 if (valid_entry->len == num) { 666 LIST_REMOVE(valid_entry, next); 667 } else { 668 /** 669 * The entry have more numbers than requested, 670 * create a new entry for alloc_list and minus its 671 * queue base and number in free_list. 672 */ 673 entry = rte_zmalloc(NULL, sizeof(*entry), 0); 674 if (!entry) { 675 PMD_INIT_LOG(ERR, 676 "Failed to allocate memory for " 677 "resource pool"); 678 return -ENOMEM; 679 } 680 entry->base = valid_entry->base; 681 entry->len = num; 682 valid_entry->base += num; 683 valid_entry->len -= num; 684 valid_entry = entry; 685 } 686 687 /* Insert it into alloc list, not sorted */ 688 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next); 689 690 pool->num_free -= valid_entry->len; 691 pool->num_alloc += valid_entry->len; 692 693 return valid_entry->base + pool->base; 694 } 695 696 static void 697 ice_res_pool_destroy(struct ice_res_pool_info *pool) 698 { 699 struct pool_entry *entry, *next_entry; 700 701 if (!pool) 702 return; 703 704 for (entry = LIST_FIRST(&pool->alloc_list); 705 entry && (next_entry = LIST_NEXT(entry, next), 1); 706 entry = next_entry) { 707 LIST_REMOVE(entry, next); 708 rte_free(entry); 709 } 710 711 for (entry = LIST_FIRST(&pool->free_list); 712 entry && (next_entry = LIST_NEXT(entry, next), 1); 713 entry = next_entry) { 714 LIST_REMOVE(entry, next); 715 rte_free(entry); 716 } 717 718 pool->num_free = 0; 719 pool->num_alloc = 0; 720 pool->base = 0; 721 LIST_INIT(&pool->alloc_list); 722 LIST_INIT(&pool->free_list); 723 } 724 725 static void 726 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) 727 { 728 /* Set VSI LUT selection */ 729 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI & 730 ICE_AQ_VSI_Q_OPT_RSS_LUT_M; 731 /* Set Hash scheme */ 732 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ & 733 ICE_AQ_VSI_Q_OPT_RSS_HASH_M; 734 /* enable TC */ 735 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M; 736 } 737 738 static enum ice_status 739 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, 740 struct ice_aqc_vsi_props *info, 741 uint8_t enabled_tcmap) 742 { 743 uint16_t bsf, qp_idx; 744 745 /* default tc 0 now. Multi-TC supporting need to be done later. 746 * Configure TC and queue mapping parameters, for enabled TC, 747 * allocate qpnum_per_tc queues to this traffic. 748 */ 749 if (enabled_tcmap != 0x01) { 750 PMD_INIT_LOG(ERR, "only TC0 is supported"); 751 return -ENOTSUP; 752 } 753 754 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC); 755 bsf = rte_bsf32(vsi->nb_qps); 756 /* Adjust the queue number to actual queues that can be applied */ 757 vsi->nb_qps = 0x1 << bsf; 758 759 qp_idx = 0; 760 /* Set tc and queue mapping with VSI */ 761 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx << 762 ICE_AQ_VSI_TC_Q_OFFSET_S) | 763 (bsf << ICE_AQ_VSI_TC_Q_NUM_S)); 764 765 /* Associate queue number with VSI */ 766 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG); 767 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue); 768 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps); 769 info->valid_sections |= 770 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID); 771 /* Set the info.ingress_table and info.egress_table 772 * for UP translate table. Now just set it to 1:1 map by default 773 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688 774 */ 775 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688 776 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 777 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 778 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT); 779 return 0; 780 } 781 782 static int 783 ice_init_mac_address(struct rte_eth_dev *dev) 784 { 785 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 786 787 if (!rte_is_unicast_ether_addr 788 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) { 789 PMD_INIT_LOG(ERR, "Invalid MAC address"); 790 return -EINVAL; 791 } 792 793 rte_ether_addr_copy( 794 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr, 795 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr); 796 797 dev->data->mac_addrs = 798 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0); 799 if (!dev->data->mac_addrs) { 800 PMD_INIT_LOG(ERR, 801 "Failed to allocate memory to store mac address"); 802 return -ENOMEM; 803 } 804 /* store it to dev data */ 805 rte_ether_addr_copy( 806 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr, 807 &dev->data->mac_addrs[0]); 808 return 0; 809 } 810 811 /* Find out specific MAC filter */ 812 static struct ice_mac_filter * 813 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr) 814 { 815 struct ice_mac_filter *f; 816 817 TAILQ_FOREACH(f, &vsi->mac_list, next) { 818 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr)) 819 return f; 820 } 821 822 return NULL; 823 } 824 825 static int 826 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 827 { 828 struct ice_fltr_list_entry *m_list_itr = NULL; 829 struct ice_mac_filter *f; 830 struct LIST_HEAD_TYPE list_head; 831 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 832 int ret = 0; 833 834 /* If it's added and configured, return */ 835 f = ice_find_mac_filter(vsi, mac_addr); 836 if (f) { 837 PMD_DRV_LOG(INFO, "This MAC filter already exists."); 838 return 0; 839 } 840 841 INIT_LIST_HEAD(&list_head); 842 843 m_list_itr = (struct ice_fltr_list_entry *) 844 ice_malloc(hw, sizeof(*m_list_itr)); 845 if (!m_list_itr) { 846 ret = -ENOMEM; 847 goto DONE; 848 } 849 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 850 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 851 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 852 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 853 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 854 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 855 m_list_itr->fltr_info.vsi_handle = vsi->idx; 856 857 LIST_ADD(&m_list_itr->list_entry, &list_head); 858 859 /* Add the mac */ 860 ret = ice_add_mac(hw, &list_head); 861 if (ret != ICE_SUCCESS) { 862 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 863 ret = -EINVAL; 864 goto DONE; 865 } 866 /* Add the mac addr into mac list */ 867 f = rte_zmalloc(NULL, sizeof(*f), 0); 868 if (!f) { 869 PMD_DRV_LOG(ERR, "failed to allocate memory"); 870 ret = -ENOMEM; 871 goto DONE; 872 } 873 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr); 874 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next); 875 vsi->mac_num++; 876 877 ret = 0; 878 879 DONE: 880 rte_free(m_list_itr); 881 return ret; 882 } 883 884 static int 885 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) 886 { 887 struct ice_fltr_list_entry *m_list_itr = NULL; 888 struct ice_mac_filter *f; 889 struct LIST_HEAD_TYPE list_head; 890 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 891 int ret = 0; 892 893 /* Can't find it, return an error */ 894 f = ice_find_mac_filter(vsi, mac_addr); 895 if (!f) 896 return -EINVAL; 897 898 INIT_LIST_HEAD(&list_head); 899 900 m_list_itr = (struct ice_fltr_list_entry *) 901 ice_malloc(hw, sizeof(*m_list_itr)); 902 if (!m_list_itr) { 903 ret = -ENOMEM; 904 goto DONE; 905 } 906 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr, 907 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 908 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 909 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 910 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC; 911 m_list_itr->fltr_info.flag = ICE_FLTR_TX; 912 m_list_itr->fltr_info.vsi_handle = vsi->idx; 913 914 LIST_ADD(&m_list_itr->list_entry, &list_head); 915 916 /* remove the mac filter */ 917 ret = ice_remove_mac(hw, &list_head); 918 if (ret != ICE_SUCCESS) { 919 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 920 ret = -EINVAL; 921 goto DONE; 922 } 923 924 /* Remove the mac addr from mac list */ 925 TAILQ_REMOVE(&vsi->mac_list, f, next); 926 rte_free(f); 927 vsi->mac_num--; 928 929 ret = 0; 930 DONE: 931 rte_free(m_list_itr); 932 return ret; 933 } 934 935 /* Find out specific VLAN filter */ 936 static struct ice_vlan_filter * 937 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 938 { 939 struct ice_vlan_filter *f; 940 941 TAILQ_FOREACH(f, &vsi->vlan_list, next) { 942 if (vlan_id == f->vlan_info.vlan_id) 943 return f; 944 } 945 946 return NULL; 947 } 948 949 static int 950 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 951 { 952 struct ice_fltr_list_entry *v_list_itr = NULL; 953 struct ice_vlan_filter *f; 954 struct LIST_HEAD_TYPE list_head; 955 struct ice_hw *hw; 956 int ret = 0; 957 958 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID) 959 return -EINVAL; 960 961 hw = ICE_VSI_TO_HW(vsi); 962 963 /* If it's added and configured, return. */ 964 f = ice_find_vlan_filter(vsi, vlan_id); 965 if (f) { 966 PMD_DRV_LOG(INFO, "This VLAN filter already exists."); 967 return 0; 968 } 969 970 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) 971 return 0; 972 973 INIT_LIST_HEAD(&list_head); 974 975 v_list_itr = (struct ice_fltr_list_entry *) 976 ice_malloc(hw, sizeof(*v_list_itr)); 977 if (!v_list_itr) { 978 ret = -ENOMEM; 979 goto DONE; 980 } 981 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 982 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 983 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 984 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 985 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 986 v_list_itr->fltr_info.vsi_handle = vsi->idx; 987 988 LIST_ADD(&v_list_itr->list_entry, &list_head); 989 990 /* Add the vlan */ 991 ret = ice_add_vlan(hw, &list_head); 992 if (ret != ICE_SUCCESS) { 993 PMD_DRV_LOG(ERR, "Failed to add VLAN filter"); 994 ret = -EINVAL; 995 goto DONE; 996 } 997 998 /* Add vlan into vlan list */ 999 f = rte_zmalloc(NULL, sizeof(*f), 0); 1000 if (!f) { 1001 PMD_DRV_LOG(ERR, "failed to allocate memory"); 1002 ret = -ENOMEM; 1003 goto DONE; 1004 } 1005 f->vlan_info.vlan_id = vlan_id; 1006 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next); 1007 vsi->vlan_num++; 1008 1009 ret = 0; 1010 1011 DONE: 1012 rte_free(v_list_itr); 1013 return ret; 1014 } 1015 1016 static int 1017 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id) 1018 { 1019 struct ice_fltr_list_entry *v_list_itr = NULL; 1020 struct ice_vlan_filter *f; 1021 struct LIST_HEAD_TYPE list_head; 1022 struct ice_hw *hw; 1023 int ret = 0; 1024 1025 /** 1026 * Vlan 0 is the generic filter for untagged packets 1027 * and can't be removed. 1028 */ 1029 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID) 1030 return -EINVAL; 1031 1032 hw = ICE_VSI_TO_HW(vsi); 1033 1034 /* Can't find it, return an error */ 1035 f = ice_find_vlan_filter(vsi, vlan_id); 1036 if (!f) 1037 return -EINVAL; 1038 1039 INIT_LIST_HEAD(&list_head); 1040 1041 v_list_itr = (struct ice_fltr_list_entry *) 1042 ice_malloc(hw, sizeof(*v_list_itr)); 1043 if (!v_list_itr) { 1044 ret = -ENOMEM; 1045 goto DONE; 1046 } 1047 1048 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id; 1049 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI; 1050 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 1051 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN; 1052 v_list_itr->fltr_info.flag = ICE_FLTR_TX; 1053 v_list_itr->fltr_info.vsi_handle = vsi->idx; 1054 1055 LIST_ADD(&v_list_itr->list_entry, &list_head); 1056 1057 /* remove the vlan filter */ 1058 ret = ice_remove_vlan(hw, &list_head); 1059 if (ret != ICE_SUCCESS) { 1060 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter"); 1061 ret = -EINVAL; 1062 goto DONE; 1063 } 1064 1065 /* Remove the vlan id from vlan list */ 1066 TAILQ_REMOVE(&vsi->vlan_list, f, next); 1067 rte_free(f); 1068 vsi->vlan_num--; 1069 1070 ret = 0; 1071 DONE: 1072 rte_free(v_list_itr); 1073 return ret; 1074 } 1075 1076 static int 1077 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi) 1078 { 1079 struct ice_mac_filter *m_f; 1080 struct ice_vlan_filter *v_f; 1081 int ret = 0; 1082 1083 if (!vsi || !vsi->mac_num) 1084 return -EINVAL; 1085 1086 TAILQ_FOREACH(m_f, &vsi->mac_list, next) { 1087 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr); 1088 if (ret != ICE_SUCCESS) { 1089 ret = -EINVAL; 1090 goto DONE; 1091 } 1092 } 1093 1094 if (vsi->vlan_num == 0) 1095 return 0; 1096 1097 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) { 1098 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id); 1099 if (ret != ICE_SUCCESS) { 1100 ret = -EINVAL; 1101 goto DONE; 1102 } 1103 } 1104 1105 DONE: 1106 return ret; 1107 } 1108 1109 static int 1110 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) 1111 { 1112 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1113 struct ice_vsi_ctx ctxt; 1114 uint8_t qinq_flags; 1115 int ret = 0; 1116 1117 /* Check if it has been already on or off */ 1118 if (vsi->info.valid_sections & 1119 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1120 if (on) { 1121 if ((vsi->info.outer_tag_flags & 1122 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == 1123 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) 1124 return 0; /* already on */ 1125 } else { 1126 if (!(vsi->info.outer_tag_flags & 1127 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) 1128 return 0; /* already off */ 1129 } 1130 } 1131 1132 if (on) 1133 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; 1134 else 1135 qinq_flags = 0; 1136 /* clear global insertion and use per packet insertion */ 1137 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); 1138 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); 1139 vsi->info.outer_tag_flags |= qinq_flags; 1140 /* use default vlan type 0x8100 */ 1141 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1142 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1143 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1144 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1145 ctxt.info.valid_sections = 1146 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1147 ctxt.vsi_num = vsi->vsi_id; 1148 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1149 if (ret) { 1150 PMD_DRV_LOG(INFO, 1151 "Update VSI failed to %s qinq stripping", 1152 on ? "enable" : "disable"); 1153 return -EINVAL; 1154 } 1155 1156 vsi->info.valid_sections |= 1157 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1158 1159 return ret; 1160 } 1161 1162 static int 1163 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) 1164 { 1165 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 1166 struct ice_vsi_ctx ctxt; 1167 uint8_t qinq_flags; 1168 int ret = 0; 1169 1170 /* Check if it has been already on or off */ 1171 if (vsi->info.valid_sections & 1172 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { 1173 if (on) { 1174 if ((vsi->info.outer_tag_flags & 1175 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 1176 ICE_AQ_VSI_OUTER_TAG_COPY) 1177 return 0; /* already on */ 1178 } else { 1179 if ((vsi->info.outer_tag_flags & 1180 ICE_AQ_VSI_OUTER_TAG_MODE_M) == 1181 ICE_AQ_VSI_OUTER_TAG_NOTHING) 1182 return 0; /* already off */ 1183 } 1184 } 1185 1186 if (on) 1187 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; 1188 else 1189 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; 1190 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); 1191 vsi->info.outer_tag_flags |= qinq_flags; 1192 /* use default vlan type 0x8100 */ 1193 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); 1194 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << 1195 ICE_AQ_VSI_OUTER_TAG_TYPE_S; 1196 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 1197 ctxt.info.valid_sections = 1198 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1199 ctxt.vsi_num = vsi->vsi_id; 1200 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 1201 if (ret) { 1202 PMD_DRV_LOG(INFO, 1203 "Update VSI failed to %s qinq stripping", 1204 on ? "enable" : "disable"); 1205 return -EINVAL; 1206 } 1207 1208 vsi->info.valid_sections |= 1209 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID); 1210 1211 return ret; 1212 } 1213 1214 static int 1215 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on) 1216 { 1217 int ret; 1218 1219 ret = ice_vsi_config_qinq_stripping(vsi, on); 1220 if (ret) 1221 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret); 1222 1223 ret = ice_vsi_config_qinq_insertion(vsi, on); 1224 if (ret) 1225 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret); 1226 1227 return ret; 1228 } 1229 1230 /* Enable IRQ0 */ 1231 static void 1232 ice_pf_enable_irq0(struct ice_hw *hw) 1233 { 1234 /* reset the registers */ 1235 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0); 1236 ICE_READ_REG(hw, PFINT_OICR); 1237 1238 #ifdef ICE_LSE_SPT 1239 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 1240 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M & 1241 (~PFINT_OICR_LINK_STAT_CHANGE_M))); 1242 1243 ICE_WRITE_REG(hw, PFINT_OICR_CTL, 1244 (0 & PFINT_OICR_CTL_MSIX_INDX_M) | 1245 ((0 << PFINT_OICR_CTL_ITR_INDX_S) & 1246 PFINT_OICR_CTL_ITR_INDX_M) | 1247 PFINT_OICR_CTL_CAUSE_ENA_M); 1248 1249 ICE_WRITE_REG(hw, PFINT_FW_CTL, 1250 (0 & PFINT_FW_CTL_MSIX_INDX_M) | 1251 ((0 << PFINT_FW_CTL_ITR_INDX_S) & 1252 PFINT_FW_CTL_ITR_INDX_M) | 1253 PFINT_FW_CTL_CAUSE_ENA_M); 1254 #else 1255 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M); 1256 #endif 1257 1258 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 1259 GLINT_DYN_CTL_INTENA_M | 1260 GLINT_DYN_CTL_CLEARPBA_M | 1261 GLINT_DYN_CTL_ITR_INDX_M); 1262 1263 ice_flush(hw); 1264 } 1265 1266 /* Disable IRQ0 */ 1267 static void 1268 ice_pf_disable_irq0(struct ice_hw *hw) 1269 { 1270 /* Disable all interrupt types */ 1271 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 1272 ice_flush(hw); 1273 } 1274 1275 #ifdef ICE_LSE_SPT 1276 static void 1277 ice_handle_aq_msg(struct rte_eth_dev *dev) 1278 { 1279 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1280 struct ice_ctl_q_info *cq = &hw->adminq; 1281 struct ice_rq_event_info event; 1282 uint16_t pending, opcode; 1283 int ret; 1284 1285 event.buf_len = ICE_AQ_MAX_BUF_LEN; 1286 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0); 1287 if (!event.msg_buf) { 1288 PMD_DRV_LOG(ERR, "Failed to allocate mem"); 1289 return; 1290 } 1291 1292 pending = 1; 1293 while (pending) { 1294 ret = ice_clean_rq_elem(hw, cq, &event, &pending); 1295 1296 if (ret != ICE_SUCCESS) { 1297 PMD_DRV_LOG(INFO, 1298 "Failed to read msg from AdminQ, " 1299 "adminq_err: %u", 1300 hw->adminq.sq_last_status); 1301 break; 1302 } 1303 opcode = rte_le_to_cpu_16(event.desc.opcode); 1304 1305 switch (opcode) { 1306 case ice_aqc_opc_get_link_status: 1307 ret = ice_link_update(dev, 0); 1308 if (!ret) 1309 _rte_eth_dev_callback_process 1310 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1311 break; 1312 default: 1313 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet", 1314 opcode); 1315 break; 1316 } 1317 } 1318 rte_free(event.msg_buf); 1319 } 1320 #endif 1321 1322 /** 1323 * Interrupt handler triggered by NIC for handling 1324 * specific interrupt. 1325 * 1326 * @param handle 1327 * Pointer to interrupt handle. 1328 * @param param 1329 * The address of parameter (struct rte_eth_dev *) regsitered before. 1330 * 1331 * @return 1332 * void 1333 */ 1334 static void 1335 ice_interrupt_handler(void *param) 1336 { 1337 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1338 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1339 uint32_t oicr; 1340 uint32_t reg; 1341 uint8_t pf_num; 1342 uint8_t event; 1343 uint16_t queue; 1344 int ret; 1345 #ifdef ICE_LSE_SPT 1346 uint32_t int_fw_ctl; 1347 #endif 1348 1349 /* Disable interrupt */ 1350 ice_pf_disable_irq0(hw); 1351 1352 /* read out interrupt causes */ 1353 oicr = ICE_READ_REG(hw, PFINT_OICR); 1354 #ifdef ICE_LSE_SPT 1355 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL); 1356 #endif 1357 1358 /* No interrupt event indicated */ 1359 if (!(oicr & PFINT_OICR_INTEVENT_M)) { 1360 PMD_DRV_LOG(INFO, "No interrupt event"); 1361 goto done; 1362 } 1363 1364 #ifdef ICE_LSE_SPT 1365 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) { 1366 PMD_DRV_LOG(INFO, "FW_CTL: link state change event"); 1367 ice_handle_aq_msg(dev); 1368 } 1369 #else 1370 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) { 1371 PMD_DRV_LOG(INFO, "OICR: link state change event"); 1372 ret = ice_link_update(dev, 0); 1373 if (!ret) 1374 _rte_eth_dev_callback_process 1375 (dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1376 } 1377 #endif 1378 1379 if (oicr & PFINT_OICR_MAL_DETECT_M) { 1380 PMD_DRV_LOG(WARNING, "OICR: MDD event"); 1381 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM); 1382 if (reg & GL_MDET_TX_PQM_VALID_M) { 1383 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1384 GL_MDET_TX_PQM_PF_NUM_S; 1385 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1386 GL_MDET_TX_PQM_MAL_TYPE_S; 1387 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> 1388 GL_MDET_TX_PQM_QNUM_S; 1389 1390 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1391 "%d by PQM on TX queue %d PF# %d", 1392 event, queue, pf_num); 1393 } 1394 1395 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN); 1396 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1397 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1398 GL_MDET_TX_TCLAN_PF_NUM_S; 1399 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1400 GL_MDET_TX_TCLAN_MAL_TYPE_S; 1401 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1402 GL_MDET_TX_TCLAN_QNUM_S; 1403 1404 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event " 1405 "%d by TCLAN on TX queue %d PF# %d", 1406 event, queue, pf_num); 1407 } 1408 } 1409 done: 1410 /* Enable interrupt */ 1411 ice_pf_enable_irq0(hw); 1412 rte_intr_ack(dev->intr_handle); 1413 } 1414 1415 static void 1416 ice_init_proto_xtr(struct rte_eth_dev *dev) 1417 { 1418 struct ice_adapter *ad = 1419 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1420 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1421 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1422 const struct proto_xtr_ol_flag *ol_flag; 1423 bool proto_xtr_enable = false; 1424 int offset; 1425 uint16_t i; 1426 1427 if (!ice_proto_xtr_support(hw)) { 1428 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported"); 1429 return; 1430 } 1431 1432 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0); 1433 if (unlikely(pf->proto_xtr == NULL)) { 1434 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table"); 1435 return; 1436 } 1437 1438 for (i = 0; i < pf->lan_nb_qps; i++) { 1439 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ? 1440 ad->devargs.proto_xtr[i] : 1441 ad->devargs.proto_xtr_dflt; 1442 1443 if (pf->proto_xtr[i] != PROTO_XTR_NONE) { 1444 uint8_t type = pf->proto_xtr[i]; 1445 1446 ice_proto_xtr_ol_flag_params[type].required = true; 1447 proto_xtr_enable = true; 1448 } 1449 } 1450 1451 if (likely(!proto_xtr_enable)) 1452 return; 1453 1454 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param); 1455 if (unlikely(offset == -1)) { 1456 PMD_DRV_LOG(ERR, 1457 "Protocol extraction metadata is disabled in mbuf with error %d", 1458 -rte_errno); 1459 return; 1460 } 1461 1462 PMD_DRV_LOG(DEBUG, 1463 "Protocol extraction metadata offset in mbuf is : %d", 1464 offset); 1465 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset; 1466 1467 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) { 1468 ol_flag = &ice_proto_xtr_ol_flag_params[i]; 1469 1470 if (!ol_flag->required) 1471 continue; 1472 1473 offset = rte_mbuf_dynflag_register(&ol_flag->param); 1474 if (unlikely(offset == -1)) { 1475 PMD_DRV_LOG(ERR, 1476 "Protocol extraction offload '%s' failed to register with error %d", 1477 ol_flag->param.name, -rte_errno); 1478 1479 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1; 1480 break; 1481 } 1482 1483 PMD_DRV_LOG(DEBUG, 1484 "Protocol extraction offload '%s' offset in mbuf is : %d", 1485 ol_flag->param.name, offset); 1486 *ol_flag->ol_flag = 1ULL << offset; 1487 } 1488 } 1489 1490 /* Initialize SW parameters of PF */ 1491 static int 1492 ice_pf_sw_init(struct rte_eth_dev *dev) 1493 { 1494 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 1495 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1496 1497 pf->lan_nb_qp_max = 1498 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq, 1499 hw->func_caps.common_cap.num_rxq); 1500 1501 pf->lan_nb_qps = pf->lan_nb_qp_max; 1502 1503 ice_init_proto_xtr(dev); 1504 1505 if (hw->func_caps.fd_fltr_guar > 0 || 1506 hw->func_caps.fd_fltr_best_effort > 0) { 1507 pf->flags |= ICE_FLAG_FDIR; 1508 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR; 1509 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps; 1510 } else { 1511 pf->fdir_nb_qps = 0; 1512 } 1513 pf->fdir_qp_offset = 0; 1514 1515 return 0; 1516 } 1517 1518 struct ice_vsi * 1519 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) 1520 { 1521 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1522 struct ice_vsi *vsi = NULL; 1523 struct ice_vsi_ctx vsi_ctx; 1524 int ret; 1525 struct rte_ether_addr broadcast = { 1526 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} }; 1527 struct rte_ether_addr mac_addr; 1528 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 }; 1529 uint8_t tc_bitmap = 0x1; 1530 uint16_t cfg; 1531 1532 /* hw->num_lports = 1 in NIC mode */ 1533 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0); 1534 if (!vsi) 1535 return NULL; 1536 1537 vsi->idx = pf->next_vsi_idx; 1538 pf->next_vsi_idx++; 1539 vsi->type = type; 1540 vsi->adapter = ICE_PF_TO_ADAPTER(pf); 1541 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX; 1542 vsi->vlan_anti_spoof_on = 0; 1543 vsi->vlan_filter_on = 1; 1544 TAILQ_INIT(&vsi->mac_list); 1545 TAILQ_INIT(&vsi->vlan_list); 1546 1547 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */ 1548 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size > 1549 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 : 1550 hw->func_caps.common_cap.rss_table_size; 1551 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE; 1552 1553 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 1554 switch (type) { 1555 case ICE_VSI_PF: 1556 vsi->nb_qps = pf->lan_nb_qps; 1557 vsi->base_queue = 1; 1558 ice_vsi_config_default_rss(&vsi_ctx.info); 1559 vsi_ctx.alloc_from_pool = true; 1560 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1561 /* switch_id is queried by get_switch_config aq, which is done 1562 * by ice_init_hw 1563 */ 1564 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1565 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1566 /* Allow all untagged or tagged packets */ 1567 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; 1568 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; 1569 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | 1570 ICE_AQ_VSI_Q_OPT_RSS_TPLZ; 1571 1572 /* FDIR */ 1573 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID | 1574 ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1575 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1576 cfg = ICE_AQ_VSI_FD_ENABLE; 1577 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1578 vsi_ctx.info.max_fd_fltr_dedicated = 1579 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar); 1580 vsi_ctx.info.max_fd_fltr_shared = 1581 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort); 1582 1583 /* Enable VLAN/UP trip */ 1584 ret = ice_vsi_config_tc_queue_mapping(vsi, 1585 &vsi_ctx.info, 1586 ICE_DEFAULT_TCMAP); 1587 if (ret) { 1588 PMD_INIT_LOG(ERR, 1589 "tc queue mapping with vsi failed, " 1590 "err = %d", 1591 ret); 1592 goto fail_mem; 1593 } 1594 1595 break; 1596 case ICE_VSI_CTRL: 1597 vsi->nb_qps = pf->fdir_nb_qps; 1598 vsi->base_queue = ICE_FDIR_QUEUE_ID; 1599 vsi_ctx.alloc_from_pool = true; 1600 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF; 1601 1602 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID; 1603 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg); 1604 cfg = ICE_AQ_VSI_FD_PROG_ENABLE; 1605 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); 1606 vsi_ctx.info.sw_id = hw->port_info->sw_id; 1607 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 1608 ret = ice_vsi_config_tc_queue_mapping(vsi, 1609 &vsi_ctx.info, 1610 ICE_DEFAULT_TCMAP); 1611 if (ret) { 1612 PMD_INIT_LOG(ERR, 1613 "tc queue mapping with vsi failed, " 1614 "err = %d", 1615 ret); 1616 goto fail_mem; 1617 } 1618 break; 1619 default: 1620 /* for other types of VSI */ 1621 PMD_INIT_LOG(ERR, "other types of VSI not supported"); 1622 goto fail_mem; 1623 } 1624 1625 /* VF has MSIX interrupt in VF range, don't allocate here */ 1626 if (type == ICE_VSI_PF) { 1627 ret = ice_res_pool_alloc(&pf->msix_pool, 1628 RTE_MIN(vsi->nb_qps, 1629 RTE_MAX_RXTX_INTR_VEC_ID)); 1630 if (ret < 0) { 1631 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d", 1632 vsi->vsi_id, ret); 1633 } 1634 vsi->msix_intr = ret; 1635 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID); 1636 } else if (type == ICE_VSI_CTRL) { 1637 ret = ice_res_pool_alloc(&pf->msix_pool, 1); 1638 if (ret < 0) { 1639 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", 1640 vsi->vsi_id, ret); 1641 } 1642 vsi->msix_intr = ret; 1643 vsi->nb_msix = 1; 1644 } else { 1645 vsi->msix_intr = 0; 1646 vsi->nb_msix = 0; 1647 } 1648 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL); 1649 if (ret != ICE_SUCCESS) { 1650 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret); 1651 goto fail_mem; 1652 } 1653 /* store vsi information is SW structure */ 1654 vsi->vsi_id = vsi_ctx.vsi_num; 1655 vsi->info = vsi_ctx.info; 1656 pf->vsis_allocated = vsi_ctx.vsis_allocd; 1657 pf->vsis_unallocated = vsi_ctx.vsis_unallocated; 1658 1659 if (type == ICE_VSI_PF) { 1660 /* MAC configuration */ 1661 rte_ether_addr_copy((struct rte_ether_addr *) 1662 hw->port_info->mac.perm_addr, 1663 &pf->dev_addr); 1664 1665 rte_ether_addr_copy(&pf->dev_addr, &mac_addr); 1666 ret = ice_add_mac_filter(vsi, &mac_addr); 1667 if (ret != ICE_SUCCESS) 1668 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter"); 1669 1670 rte_ether_addr_copy(&broadcast, &mac_addr); 1671 ret = ice_add_mac_filter(vsi, &mac_addr); 1672 if (ret != ICE_SUCCESS) 1673 PMD_INIT_LOG(ERR, "Failed to add MAC filter"); 1674 } 1675 1676 /* At the beginning, only TC0. */ 1677 /* What we need here is the maximam number of the TX queues. 1678 * Currently vsi->nb_qps means it. 1679 * Correct it if any change. 1680 */ 1681 max_txqs[0] = vsi->nb_qps; 1682 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx, 1683 tc_bitmap, max_txqs); 1684 if (ret != ICE_SUCCESS) 1685 PMD_INIT_LOG(ERR, "Failed to config vsi sched"); 1686 1687 return vsi; 1688 fail_mem: 1689 rte_free(vsi); 1690 pf->next_vsi_idx--; 1691 return NULL; 1692 } 1693 1694 static int 1695 ice_send_driver_ver(struct ice_hw *hw) 1696 { 1697 struct ice_driver_ver dv; 1698 1699 /* we don't have driver version use 0 for dummy */ 1700 dv.major_ver = 0; 1701 dv.minor_ver = 0; 1702 dv.build_ver = 0; 1703 dv.subbuild_ver = 0; 1704 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string)); 1705 1706 return ice_aq_send_driver_ver(hw, &dv, NULL); 1707 } 1708 1709 static int 1710 ice_pf_setup(struct ice_pf *pf) 1711 { 1712 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1713 struct ice_vsi *vsi; 1714 uint16_t unused; 1715 1716 /* Clear all stats counters */ 1717 pf->offset_loaded = FALSE; 1718 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats)); 1719 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats)); 1720 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats)); 1721 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats)); 1722 1723 /* force guaranteed filter pool for PF */ 1724 ice_alloc_fd_guar_item(hw, &unused, 1725 hw->func_caps.fd_fltr_guar); 1726 /* force shared filter pool for PF */ 1727 ice_alloc_fd_shrd_item(hw, &unused, 1728 hw->func_caps.fd_fltr_best_effort); 1729 1730 vsi = ice_setup_vsi(pf, ICE_VSI_PF); 1731 if (!vsi) { 1732 PMD_INIT_LOG(ERR, "Failed to add vsi for PF"); 1733 return -EINVAL; 1734 } 1735 1736 pf->main_vsi = vsi; 1737 1738 return 0; 1739 } 1740 1741 /* PCIe configuration space setting */ 1742 #define PCI_CFG_SPACE_SIZE 256 1743 #define PCI_CFG_SPACE_EXP_SIZE 4096 1744 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff) 1745 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) 1746 #define PCI_EXT_CAP_ID_DSN 0x03 1747 1748 static int 1749 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) 1750 { 1751 uint32_t header; 1752 int ttl; 1753 int pos = PCI_CFG_SPACE_SIZE; 1754 1755 /* minimum 8 bytes per capability */ 1756 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 1757 1758 if (rte_pci_read_config(dev, &header, 4, pos) < 0) { 1759 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); 1760 return -1; 1761 } 1762 1763 /* 1764 * If we have no capabilities, this is indicated by cap ID, 1765 * cap version and next pointer all being 0. 1766 */ 1767 if (header == 0) 1768 return 0; 1769 1770 while (ttl-- > 0) { 1771 if (PCI_EXT_CAP_ID(header) == cap) 1772 return pos; 1773 1774 pos = PCI_EXT_CAP_NEXT(header); 1775 1776 if (pos < PCI_CFG_SPACE_SIZE) 1777 break; 1778 1779 if (rte_pci_read_config(dev, &header, 4, pos) < 0) { 1780 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); 1781 return -1; 1782 } 1783 } 1784 1785 return 0; 1786 } 1787 1788 /* 1789 * Extract device serial number from PCIe Configuration Space and 1790 * determine the pkg file path according to the DSN. 1791 */ 1792 static int 1793 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file) 1794 { 1795 int pos; 1796 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE]; 1797 uint32_t dsn_low, dsn_high; 1798 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); 1799 1800 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN); 1801 1802 if (pos) { 1803 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4); 1804 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8); 1805 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, 1806 "ice-%08x%08x.pkg", dsn_high, dsn_low); 1807 } else { 1808 PMD_INIT_LOG(ERR, "Failed to read device serial number\n"); 1809 goto fail_dsn; 1810 } 1811 1812 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES, 1813 ICE_MAX_PKG_FILENAME_SIZE); 1814 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1815 return 0; 1816 1817 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT, 1818 ICE_MAX_PKG_FILENAME_SIZE); 1819 if (!access(strcat(pkg_file, opt_ddp_filename), 0)) 1820 return 0; 1821 1822 fail_dsn: 1823 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE); 1824 if (!access(pkg_file, 0)) 1825 return 0; 1826 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE); 1827 return 0; 1828 } 1829 1830 static enum ice_pkg_type 1831 ice_load_pkg_type(struct ice_hw *hw) 1832 { 1833 enum ice_pkg_type package_type; 1834 1835 /* store the activated package type (OS default or Comms) */ 1836 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME, 1837 ICE_PKG_NAME_SIZE)) 1838 package_type = ICE_PKG_TYPE_OS_DEFAULT; 1839 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME, 1840 ICE_PKG_NAME_SIZE)) 1841 package_type = ICE_PKG_TYPE_COMMS; 1842 else 1843 package_type = ICE_PKG_TYPE_UNKNOWN; 1844 1845 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s", 1846 hw->active_pkg_ver.major, hw->active_pkg_ver.minor, 1847 hw->active_pkg_ver.update, hw->active_pkg_ver.draft, 1848 hw->active_pkg_name); 1849 1850 return package_type; 1851 } 1852 1853 static int ice_load_pkg(struct rte_eth_dev *dev) 1854 { 1855 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1856 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE]; 1857 int err; 1858 uint8_t *buf; 1859 int buf_len; 1860 FILE *file; 1861 struct stat fstat; 1862 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1863 struct ice_adapter *ad = 1864 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1865 1866 ice_pkg_file_search_path(pci_dev, pkg_file); 1867 1868 file = fopen(pkg_file, "rb"); 1869 if (!file) { 1870 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file); 1871 return -1; 1872 } 1873 1874 err = stat(pkg_file, &fstat); 1875 if (err) { 1876 PMD_INIT_LOG(ERR, "failed to get file stats\n"); 1877 fclose(file); 1878 return err; 1879 } 1880 1881 buf_len = fstat.st_size; 1882 buf = rte_malloc(NULL, buf_len, 0); 1883 1884 if (!buf) { 1885 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n", 1886 buf_len); 1887 fclose(file); 1888 return -1; 1889 } 1890 1891 err = fread(buf, buf_len, 1, file); 1892 if (err != 1) { 1893 PMD_INIT_LOG(ERR, "failed to read package data\n"); 1894 fclose(file); 1895 err = -1; 1896 goto fail_exit; 1897 } 1898 1899 fclose(file); 1900 1901 err = ice_copy_and_init_pkg(hw, buf, buf_len); 1902 if (err) { 1903 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err); 1904 goto fail_exit; 1905 } 1906 1907 /* store the loaded pkg type info */ 1908 ad->active_pkg_type = ice_load_pkg_type(hw); 1909 1910 err = ice_init_hw_tbls(hw); 1911 if (err) { 1912 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err); 1913 goto fail_init_tbls; 1914 } 1915 1916 return 0; 1917 1918 fail_init_tbls: 1919 rte_free(hw->pkg_copy); 1920 fail_exit: 1921 rte_free(buf); 1922 return err; 1923 } 1924 1925 static void 1926 ice_base_queue_get(struct ice_pf *pf) 1927 { 1928 uint32_t reg; 1929 struct ice_hw *hw = ICE_PF_TO_HW(pf); 1930 1931 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC); 1932 if (reg & PFLAN_RX_QALLOC_VALID_M) { 1933 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M; 1934 } else { 1935 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue" 1936 " index"); 1937 } 1938 } 1939 1940 static int 1941 parse_bool(const char *key, const char *value, void *args) 1942 { 1943 int *i = (int *)args; 1944 char *end; 1945 int num; 1946 1947 num = strtoul(value, &end, 10); 1948 1949 if (num != 0 && num != 1) { 1950 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", " 1951 "value must be 0 or 1", 1952 value, key); 1953 return -1; 1954 } 1955 1956 *i = num; 1957 return 0; 1958 } 1959 1960 static int ice_parse_devargs(struct rte_eth_dev *dev) 1961 { 1962 struct ice_adapter *ad = 1963 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1964 struct rte_devargs *devargs = dev->device->devargs; 1965 struct rte_kvargs *kvlist; 1966 int ret; 1967 1968 if (devargs == NULL) 1969 return 0; 1970 1971 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args); 1972 if (kvlist == NULL) { 1973 PMD_INIT_LOG(ERR, "Invalid kvargs key\n"); 1974 return -EINVAL; 1975 } 1976 1977 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE; 1978 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE, 1979 sizeof(ad->devargs.proto_xtr)); 1980 1981 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG, 1982 &handle_proto_xtr_arg, &ad->devargs); 1983 if (ret) 1984 goto bail; 1985 1986 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, 1987 &parse_bool, &ad->devargs.safe_mode_support); 1988 if (ret) 1989 goto bail; 1990 1991 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG, 1992 &parse_bool, &ad->devargs.pipe_mode_support); 1993 if (ret) 1994 goto bail; 1995 1996 ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG, 1997 &parse_bool, &ad->devargs.flow_mark_support); 1998 if (ret) 1999 goto bail; 2000 2001 bail: 2002 rte_kvargs_free(kvlist); 2003 return ret; 2004 } 2005 2006 /* Forward LLDP packets to default VSI by set switch rules */ 2007 static int 2008 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on) 2009 { 2010 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2011 struct ice_fltr_list_entry *s_list_itr = NULL; 2012 struct LIST_HEAD_TYPE list_head; 2013 int ret = 0; 2014 2015 INIT_LIST_HEAD(&list_head); 2016 2017 s_list_itr = (struct ice_fltr_list_entry *) 2018 ice_malloc(hw, sizeof(*s_list_itr)); 2019 if (!s_list_itr) 2020 return -ENOMEM; 2021 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE; 2022 s_list_itr->fltr_info.vsi_handle = vsi->idx; 2023 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype = 2024 RTE_ETHER_TYPE_LLDP; 2025 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI; 2026 s_list_itr->fltr_info.flag = ICE_FLTR_RX; 2027 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT; 2028 LIST_ADD(&s_list_itr->list_entry, &list_head); 2029 if (on) 2030 ret = ice_add_eth_mac(hw, &list_head); 2031 else 2032 ret = ice_remove_eth_mac(hw, &list_head); 2033 2034 rte_free(s_list_itr); 2035 return ret; 2036 } 2037 2038 static enum ice_status 2039 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type, 2040 uint16_t num, uint16_t desc_id, 2041 uint16_t *prof_buf, uint16_t *num_prof) 2042 { 2043 struct ice_aqc_get_allocd_res_desc_resp *resp_buf; 2044 int ret; 2045 uint16_t buf_len; 2046 bool res_shared = 1; 2047 struct ice_aq_desc aq_desc; 2048 struct ice_sq_cd *cd = NULL; 2049 struct ice_aqc_get_allocd_res_desc *cmd = 2050 &aq_desc.params.get_res_desc; 2051 2052 buf_len = sizeof(resp_buf->elem) * num; 2053 resp_buf = ice_malloc(hw, buf_len); 2054 if (!resp_buf) 2055 return -ENOMEM; 2056 2057 ice_fill_dflt_direct_cmd_desc(&aq_desc, 2058 ice_aqc_opc_get_allocd_res_desc); 2059 2060 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) & 2061 ICE_AQC_RES_TYPE_M) | (res_shared ? 2062 ICE_AQC_RES_TYPE_FLAG_SHARED : 0)); 2063 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id); 2064 2065 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd); 2066 if (!ret) 2067 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc); 2068 else 2069 goto exit; 2070 2071 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) * 2072 (*num_prof), ICE_NONDMA_TO_NONDMA); 2073 2074 exit: 2075 rte_free(resp_buf); 2076 return ret; 2077 } 2078 static int 2079 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type) 2080 { 2081 int ret; 2082 uint16_t prof_id; 2083 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM]; 2084 uint16_t first_desc = 1; 2085 uint16_t num_prof = 0; 2086 2087 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM, 2088 first_desc, prof_buf, &num_prof); 2089 if (ret) { 2090 PMD_INIT_LOG(ERR, "Failed to get fxp resource"); 2091 return ret; 2092 } 2093 2094 for (prof_id = 0; prof_id < num_prof; prof_id++) { 2095 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]); 2096 if (ret) { 2097 PMD_INIT_LOG(ERR, "Failed to free fxp resource"); 2098 return ret; 2099 } 2100 } 2101 return 0; 2102 } 2103 2104 static int 2105 ice_reset_fxp_resource(struct ice_hw *hw) 2106 { 2107 int ret; 2108 2109 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID); 2110 if (ret) { 2111 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource"); 2112 return ret; 2113 } 2114 2115 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID); 2116 if (ret) { 2117 PMD_INIT_LOG(ERR, "Failed to clearup rss resource"); 2118 return ret; 2119 } 2120 2121 return 0; 2122 } 2123 2124 static int 2125 ice_dev_init(struct rte_eth_dev *dev) 2126 { 2127 struct rte_pci_device *pci_dev; 2128 struct rte_intr_handle *intr_handle; 2129 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2130 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2131 struct ice_adapter *ad = 2132 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2133 struct ice_vsi *vsi; 2134 int ret; 2135 2136 dev->dev_ops = &ice_eth_dev_ops; 2137 dev->rx_pkt_burst = ice_recv_pkts; 2138 dev->tx_pkt_burst = ice_xmit_pkts; 2139 dev->tx_pkt_prepare = ice_prep_pkts; 2140 2141 /* for secondary processes, we don't initialise any further as primary 2142 * has already done this work. 2143 */ 2144 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2145 ice_set_rx_function(dev); 2146 ice_set_tx_function(dev); 2147 return 0; 2148 } 2149 2150 ice_set_default_ptype_table(dev); 2151 pci_dev = RTE_DEV_TO_PCI(dev->device); 2152 intr_handle = &pci_dev->intr_handle; 2153 2154 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2155 pf->adapter->eth_dev = dev; 2156 pf->dev_data = dev->data; 2157 hw->back = pf->adapter; 2158 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr; 2159 hw->vendor_id = pci_dev->id.vendor_id; 2160 hw->device_id = pci_dev->id.device_id; 2161 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2162 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 2163 hw->bus.device = pci_dev->addr.devid; 2164 hw->bus.func = pci_dev->addr.function; 2165 2166 ret = ice_parse_devargs(dev); 2167 if (ret) { 2168 PMD_INIT_LOG(ERR, "Failed to parse devargs"); 2169 return -EINVAL; 2170 } 2171 2172 ice_init_controlq_parameter(hw); 2173 2174 ret = ice_init_hw(hw); 2175 if (ret) { 2176 PMD_INIT_LOG(ERR, "Failed to initialize HW"); 2177 return -EINVAL; 2178 } 2179 2180 ret = ice_load_pkg(dev); 2181 if (ret) { 2182 if (ad->devargs.safe_mode_support == 0) { 2183 PMD_INIT_LOG(ERR, "Failed to load the DDP package," 2184 "Use safe-mode-support=1 to enter Safe Mode"); 2185 return ret; 2186 } 2187 2188 PMD_INIT_LOG(WARNING, "Failed to load the DDP package," 2189 "Entering Safe Mode"); 2190 ad->is_safe_mode = 1; 2191 } 2192 2193 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d", 2194 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build, 2195 hw->api_maj_ver, hw->api_min_ver); 2196 2197 ice_pf_sw_init(dev); 2198 ret = ice_init_mac_address(dev); 2199 if (ret) { 2200 PMD_INIT_LOG(ERR, "Failed to initialize mac address"); 2201 goto err_init_mac; 2202 } 2203 2204 /* Pass the information to the rte_eth_dev_close() that it should also 2205 * release the private port resources. 2206 */ 2207 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 2208 2209 ret = ice_res_pool_init(&pf->msix_pool, 1, 2210 hw->func_caps.common_cap.num_msix_vectors - 1); 2211 if (ret) { 2212 PMD_INIT_LOG(ERR, "Failed to init MSIX pool"); 2213 goto err_msix_pool_init; 2214 } 2215 2216 ret = ice_pf_setup(pf); 2217 if (ret) { 2218 PMD_INIT_LOG(ERR, "Failed to setup PF"); 2219 goto err_pf_setup; 2220 } 2221 2222 ret = ice_send_driver_ver(hw); 2223 if (ret) { 2224 PMD_INIT_LOG(ERR, "Failed to send driver version"); 2225 goto err_pf_setup; 2226 } 2227 2228 vsi = pf->main_vsi; 2229 2230 /* Disable double vlan by default */ 2231 ice_vsi_config_double_vlan(vsi, FALSE); 2232 2233 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL); 2234 if (ret != ICE_SUCCESS) 2235 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n"); 2236 ret = ice_init_dcb(hw, TRUE); 2237 if (ret != ICE_SUCCESS) 2238 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n"); 2239 /* Forward LLDP packets to default VSI */ 2240 ret = ice_vsi_config_sw_lldp(vsi, TRUE); 2241 if (ret != ICE_SUCCESS) 2242 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n"); 2243 /* register callback func to eal lib */ 2244 rte_intr_callback_register(intr_handle, 2245 ice_interrupt_handler, dev); 2246 2247 ice_pf_enable_irq0(hw); 2248 2249 /* enable uio intr after callback register */ 2250 rte_intr_enable(intr_handle); 2251 2252 /* get base queue pairs index in the device */ 2253 ice_base_queue_get(pf); 2254 2255 if (!ad->is_safe_mode) { 2256 ret = ice_flow_init(ad); 2257 if (ret) { 2258 PMD_INIT_LOG(ERR, "Failed to initialize flow"); 2259 return ret; 2260 } 2261 } 2262 2263 ret = ice_reset_fxp_resource(hw); 2264 if (ret) { 2265 PMD_INIT_LOG(ERR, "Failed to reset fxp resource"); 2266 return ret; 2267 } 2268 2269 return 0; 2270 2271 err_pf_setup: 2272 ice_res_pool_destroy(&pf->msix_pool); 2273 err_msix_pool_init: 2274 rte_free(dev->data->mac_addrs); 2275 dev->data->mac_addrs = NULL; 2276 err_init_mac: 2277 ice_sched_cleanup_all(hw); 2278 rte_free(hw->port_info); 2279 ice_shutdown_all_ctrlq(hw); 2280 rte_free(pf->proto_xtr); 2281 2282 return ret; 2283 } 2284 2285 int 2286 ice_release_vsi(struct ice_vsi *vsi) 2287 { 2288 struct ice_hw *hw; 2289 struct ice_vsi_ctx vsi_ctx; 2290 enum ice_status ret; 2291 int error = 0; 2292 2293 if (!vsi) 2294 return error; 2295 2296 hw = ICE_VSI_TO_HW(vsi); 2297 2298 ice_remove_all_mac_vlan_filters(vsi); 2299 2300 memset(&vsi_ctx, 0, sizeof(vsi_ctx)); 2301 2302 vsi_ctx.vsi_num = vsi->vsi_id; 2303 vsi_ctx.info = vsi->info; 2304 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL); 2305 if (ret != ICE_SUCCESS) { 2306 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id); 2307 error = -1; 2308 } 2309 2310 rte_free(vsi->rss_lut); 2311 rte_free(vsi->rss_key); 2312 rte_free(vsi); 2313 return error; 2314 } 2315 2316 void 2317 ice_vsi_disable_queues_intr(struct ice_vsi *vsi) 2318 { 2319 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2320 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2321 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2322 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2323 uint16_t msix_intr, i; 2324 2325 /* disable interrupt and also clear all the exist config */ 2326 for (i = 0; i < vsi->nb_qps; i++) { 2327 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 2328 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 2329 rte_wmb(); 2330 } 2331 2332 if (rte_intr_allow_others(intr_handle)) 2333 /* vfio-pci */ 2334 for (i = 0; i < vsi->nb_msix; i++) { 2335 msix_intr = vsi->msix_intr + i; 2336 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 2337 GLINT_DYN_CTL_WB_ON_ITR_M); 2338 } 2339 else 2340 /* igb_uio */ 2341 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); 2342 } 2343 2344 static void 2345 ice_dev_stop(struct rte_eth_dev *dev) 2346 { 2347 struct rte_eth_dev_data *data = dev->data; 2348 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2349 struct ice_vsi *main_vsi = pf->main_vsi; 2350 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2351 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2352 uint16_t i; 2353 2354 /* avoid stopping again */ 2355 if (pf->adapter_stopped) 2356 return; 2357 2358 /* stop and clear all Rx queues */ 2359 for (i = 0; i < data->nb_rx_queues; i++) 2360 ice_rx_queue_stop(dev, i); 2361 2362 /* stop and clear all Tx queues */ 2363 for (i = 0; i < data->nb_tx_queues; i++) 2364 ice_tx_queue_stop(dev, i); 2365 2366 /* disable all queue interrupts */ 2367 ice_vsi_disable_queues_intr(main_vsi); 2368 2369 /* Clear all queues and release mbufs */ 2370 ice_clear_queues(dev); 2371 2372 if (pf->init_link_up) 2373 ice_dev_set_link_up(dev); 2374 else 2375 ice_dev_set_link_down(dev); 2376 2377 /* Clean datapath event and queue/vec mapping */ 2378 rte_intr_efd_disable(intr_handle); 2379 if (intr_handle->intr_vec) { 2380 rte_free(intr_handle->intr_vec); 2381 intr_handle->intr_vec = NULL; 2382 } 2383 2384 pf->adapter_stopped = true; 2385 } 2386 2387 static void 2388 ice_dev_close(struct rte_eth_dev *dev) 2389 { 2390 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2391 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2392 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2393 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2394 struct ice_adapter *ad = 2395 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2396 2397 /* Since stop will make link down, then the link event will be 2398 * triggered, disable the irq firstly to avoid the port_infoe etc 2399 * resources deallocation causing the interrupt service thread 2400 * crash. 2401 */ 2402 ice_pf_disable_irq0(hw); 2403 2404 ice_dev_stop(dev); 2405 2406 if (!ad->is_safe_mode) 2407 ice_flow_uninit(ad); 2408 2409 /* release all queue resource */ 2410 ice_free_queues(dev); 2411 2412 ice_res_pool_destroy(&pf->msix_pool); 2413 ice_release_vsi(pf->main_vsi); 2414 ice_sched_cleanup_all(hw); 2415 ice_free_hw_tbls(hw); 2416 rte_free(hw->port_info); 2417 hw->port_info = NULL; 2418 ice_shutdown_all_ctrlq(hw); 2419 rte_free(pf->proto_xtr); 2420 pf->proto_xtr = NULL; 2421 2422 dev->dev_ops = NULL; 2423 dev->rx_pkt_burst = NULL; 2424 dev->tx_pkt_burst = NULL; 2425 2426 rte_free(dev->data->mac_addrs); 2427 dev->data->mac_addrs = NULL; 2428 2429 /* disable uio intr before callback unregister */ 2430 rte_intr_disable(intr_handle); 2431 2432 /* unregister callback func from eal lib */ 2433 rte_intr_callback_unregister(intr_handle, 2434 ice_interrupt_handler, dev); 2435 } 2436 2437 static int 2438 ice_dev_uninit(struct rte_eth_dev *dev) 2439 { 2440 ice_dev_close(dev); 2441 2442 return 0; 2443 } 2444 2445 static int ice_init_rss(struct ice_pf *pf) 2446 { 2447 struct ice_hw *hw = ICE_PF_TO_HW(pf); 2448 struct ice_vsi *vsi = pf->main_vsi; 2449 struct rte_eth_dev *dev = pf->adapter->eth_dev; 2450 struct rte_eth_rss_conf *rss_conf; 2451 struct ice_aqc_get_set_rss_keys key; 2452 uint16_t i, nb_q; 2453 int ret = 0; 2454 bool is_safe_mode = pf->adapter->is_safe_mode; 2455 uint32_t reg; 2456 2457 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; 2458 nb_q = dev->data->nb_rx_queues; 2459 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE; 2460 vsi->rss_lut_size = pf->hash_lut_size; 2461 2462 if (is_safe_mode) { 2463 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n"); 2464 return 0; 2465 } 2466 2467 if (!vsi->rss_key) { 2468 vsi->rss_key = rte_zmalloc(NULL, 2469 vsi->rss_key_size, 0); 2470 if (vsi->rss_key == NULL) { 2471 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 2472 return -ENOMEM; 2473 } 2474 } 2475 if (!vsi->rss_lut) { 2476 vsi->rss_lut = rte_zmalloc(NULL, 2477 vsi->rss_lut_size, 0); 2478 if (vsi->rss_lut == NULL) { 2479 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key"); 2480 rte_free(vsi->rss_key); 2481 vsi->rss_key = NULL; 2482 return -ENOMEM; 2483 } 2484 } 2485 /* configure RSS key */ 2486 if (!rss_conf->rss_key) { 2487 /* Calculate the default hash key */ 2488 for (i = 0; i <= vsi->rss_key_size; i++) 2489 vsi->rss_key[i] = (uint8_t)rte_rand(); 2490 } else { 2491 rte_memcpy(vsi->rss_key, rss_conf->rss_key, 2492 RTE_MIN(rss_conf->rss_key_len, 2493 vsi->rss_key_size)); 2494 } 2495 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size); 2496 ret = ice_aq_set_rss_key(hw, vsi->idx, &key); 2497 if (ret) 2498 goto out; 2499 2500 /* init RSS LUT table */ 2501 for (i = 0; i < vsi->rss_lut_size; i++) 2502 vsi->rss_lut[i] = i % nb_q; 2503 2504 ret = ice_aq_set_rss_lut(hw, vsi->idx, 2505 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, 2506 vsi->rss_lut, vsi->rss_lut_size); 2507 if (ret) 2508 goto out; 2509 2510 /* Enable registers for symmetric_toeplitz function. */ 2511 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id)); 2512 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) | 2513 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S); 2514 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg); 2515 2516 /* configure RSS for IPv4 with input set IPv4 src/dst */ 2517 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 2518 ICE_FLOW_SEG_HDR_IPV4, 0); 2519 if (ret) 2520 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret); 2521 2522 /* configure RSS for IPv6 with input set IPv6 src/dst */ 2523 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 2524 ICE_FLOW_SEG_HDR_IPV6, 0); 2525 if (ret) 2526 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret); 2527 2528 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */ 2529 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6, 2530 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0); 2531 if (ret) 2532 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret); 2533 2534 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */ 2535 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6, 2536 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0); 2537 if (ret) 2538 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret); 2539 2540 /* configure RSS for sctp6 with input set IPv6 src/dst */ 2541 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6, 2542 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0); 2543 if (ret) 2544 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d", 2545 __func__, ret); 2546 2547 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */ 2548 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4, 2549 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0); 2550 if (ret) 2551 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret); 2552 2553 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */ 2554 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4, 2555 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0); 2556 if (ret) 2557 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret); 2558 2559 /* configure RSS for sctp4 with input set IP src/dst */ 2560 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4, 2561 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0); 2562 if (ret) 2563 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d", 2564 __func__, ret); 2565 2566 /* configure RSS for gtpu with input set TEID */ 2567 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID, 2568 ICE_FLOW_SEG_HDR_GTPU_IP, 0); 2569 if (ret) 2570 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d", 2571 __func__, ret); 2572 2573 /** 2574 * configure RSS for pppoe/pppod with input set 2575 * Source MAC and Session ID 2576 */ 2577 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH, 2578 ICE_FLOW_SEG_HDR_PPPOE, 0); 2579 if (ret) 2580 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d", 2581 __func__, ret); 2582 2583 return 0; 2584 out: 2585 rte_free(vsi->rss_key); 2586 vsi->rss_key = NULL; 2587 rte_free(vsi->rss_lut); 2588 vsi->rss_lut = NULL; 2589 return -EINVAL; 2590 } 2591 2592 static int 2593 ice_dev_configure(struct rte_eth_dev *dev) 2594 { 2595 struct ice_adapter *ad = 2596 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 2597 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2598 int ret; 2599 2600 /* Initialize to TRUE. If any of Rx queues doesn't meet the 2601 * bulk allocation or vector Rx preconditions we will reset it. 2602 */ 2603 ad->rx_bulk_alloc_allowed = true; 2604 ad->tx_simple_allowed = true; 2605 2606 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 2607 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2608 2609 ret = ice_init_rss(pf); 2610 if (ret) { 2611 PMD_DRV_LOG(ERR, "Failed to enable rss for PF"); 2612 return ret; 2613 } 2614 2615 return 0; 2616 } 2617 2618 static void 2619 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, 2620 int base_queue, int nb_queue) 2621 { 2622 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2623 uint32_t val, val_tx; 2624 int i; 2625 2626 for (i = 0; i < nb_queue; i++) { 2627 /*do actual bind*/ 2628 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | 2629 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; 2630 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | 2631 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; 2632 2633 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", 2634 base_queue + i, msix_vect); 2635 /* set ITR0 value */ 2636 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); 2637 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); 2638 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); 2639 } 2640 } 2641 2642 void 2643 ice_vsi_queues_bind_intr(struct ice_vsi *vsi) 2644 { 2645 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2646 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2647 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2648 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2649 uint16_t msix_vect = vsi->msix_intr; 2650 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd); 2651 uint16_t queue_idx = 0; 2652 int record = 0; 2653 int i; 2654 2655 /* clear Rx/Tx queue interrupt */ 2656 for (i = 0; i < vsi->nb_used_qps; i++) { 2657 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0); 2658 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0); 2659 } 2660 2661 /* PF bind interrupt */ 2662 if (rte_intr_dp_is_en(intr_handle)) { 2663 queue_idx = 0; 2664 record = 1; 2665 } 2666 2667 for (i = 0; i < vsi->nb_used_qps; i++) { 2668 if (nb_msix <= 1) { 2669 if (!rte_intr_allow_others(intr_handle)) 2670 msix_vect = ICE_MISC_VEC_ID; 2671 2672 /* uio mapping all queue to one msix_vect */ 2673 __vsi_queues_bind_intr(vsi, msix_vect, 2674 vsi->base_queue + i, 2675 vsi->nb_used_qps - i); 2676 2677 for (; !!record && i < vsi->nb_used_qps; i++) 2678 intr_handle->intr_vec[queue_idx + i] = 2679 msix_vect; 2680 break; 2681 } 2682 2683 /* vfio 1:1 queue/msix_vect mapping */ 2684 __vsi_queues_bind_intr(vsi, msix_vect, 2685 vsi->base_queue + i, 1); 2686 2687 if (!!record) 2688 intr_handle->intr_vec[queue_idx + i] = msix_vect; 2689 2690 msix_vect++; 2691 nb_msix--; 2692 } 2693 } 2694 2695 void 2696 ice_vsi_enable_queues_intr(struct ice_vsi *vsi) 2697 { 2698 struct rte_eth_dev *dev = vsi->adapter->eth_dev; 2699 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2700 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2701 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 2702 uint16_t msix_intr, i; 2703 2704 if (rte_intr_allow_others(intr_handle)) 2705 for (i = 0; i < vsi->nb_used_qps; i++) { 2706 msix_intr = vsi->msix_intr + i; 2707 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), 2708 GLINT_DYN_CTL_INTENA_M | 2709 GLINT_DYN_CTL_CLEARPBA_M | 2710 GLINT_DYN_CTL_ITR_INDX_M | 2711 GLINT_DYN_CTL_WB_ON_ITR_M); 2712 } 2713 else 2714 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), 2715 GLINT_DYN_CTL_INTENA_M | 2716 GLINT_DYN_CTL_CLEARPBA_M | 2717 GLINT_DYN_CTL_ITR_INDX_M | 2718 GLINT_DYN_CTL_WB_ON_ITR_M); 2719 } 2720 2721 static int 2722 ice_rxq_intr_setup(struct rte_eth_dev *dev) 2723 { 2724 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2725 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 2726 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2727 struct ice_vsi *vsi = pf->main_vsi; 2728 uint32_t intr_vector = 0; 2729 2730 rte_intr_disable(intr_handle); 2731 2732 /* check and configure queue intr-vector mapping */ 2733 if ((rte_intr_cap_multiple(intr_handle) || 2734 !RTE_ETH_DEV_SRIOV(dev).active) && 2735 dev->data->dev_conf.intr_conf.rxq != 0) { 2736 intr_vector = dev->data->nb_rx_queues; 2737 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { 2738 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 2739 ICE_MAX_INTR_QUEUE_NUM); 2740 return -ENOTSUP; 2741 } 2742 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2743 return -1; 2744 } 2745 2746 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2747 intr_handle->intr_vec = 2748 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int), 2749 0); 2750 if (!intr_handle->intr_vec) { 2751 PMD_DRV_LOG(ERR, 2752 "Failed to allocate %d rx_queues intr_vec", 2753 dev->data->nb_rx_queues); 2754 return -ENOMEM; 2755 } 2756 } 2757 2758 /* Map queues with MSIX interrupt */ 2759 vsi->nb_used_qps = dev->data->nb_rx_queues; 2760 ice_vsi_queues_bind_intr(vsi); 2761 2762 /* Enable interrupts for all the queues */ 2763 ice_vsi_enable_queues_intr(vsi); 2764 2765 rte_intr_enable(intr_handle); 2766 2767 return 0; 2768 } 2769 2770 static void 2771 ice_get_init_link_status(struct rte_eth_dev *dev) 2772 { 2773 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2774 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2775 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 2776 struct ice_link_status link_status; 2777 int ret; 2778 2779 ret = ice_aq_get_link_info(hw->port_info, enable_lse, 2780 &link_status, NULL); 2781 if (ret != ICE_SUCCESS) { 2782 PMD_DRV_LOG(ERR, "Failed to get link info"); 2783 pf->init_link_up = false; 2784 return; 2785 } 2786 2787 if (link_status.link_info & ICE_AQ_LINK_UP) 2788 pf->init_link_up = true; 2789 } 2790 2791 static int 2792 ice_dev_start(struct rte_eth_dev *dev) 2793 { 2794 struct rte_eth_dev_data *data = dev->data; 2795 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2796 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2797 struct ice_vsi *vsi = pf->main_vsi; 2798 uint16_t nb_rxq = 0; 2799 uint16_t nb_txq, i; 2800 uint16_t max_frame_size; 2801 int mask, ret; 2802 2803 /* program Tx queues' context in hardware */ 2804 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) { 2805 ret = ice_tx_queue_start(dev, nb_txq); 2806 if (ret) { 2807 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq); 2808 goto tx_err; 2809 } 2810 } 2811 2812 /* program Rx queues' context in hardware*/ 2813 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) { 2814 ret = ice_rx_queue_start(dev, nb_rxq); 2815 if (ret) { 2816 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq); 2817 goto rx_err; 2818 } 2819 } 2820 2821 ice_set_rx_function(dev); 2822 ice_set_tx_function(dev); 2823 2824 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2825 ETH_VLAN_EXTEND_MASK; 2826 ret = ice_vlan_offload_set(dev, mask); 2827 if (ret) { 2828 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2829 goto rx_err; 2830 } 2831 2832 /* enable Rx interrput and mapping Rx queue to interrupt vector */ 2833 if (ice_rxq_intr_setup(dev)) 2834 return -EIO; 2835 2836 /* Enable receiving broadcast packets and transmitting packets */ 2837 ret = ice_set_vsi_promisc(hw, vsi->idx, 2838 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX | 2839 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX, 2840 0); 2841 if (ret != ICE_SUCCESS) 2842 PMD_DRV_LOG(INFO, "fail to set vsi broadcast"); 2843 2844 ret = ice_aq_set_event_mask(hw, hw->port_info->lport, 2845 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT | 2846 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM | 2847 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS | 2848 ICE_AQ_LINK_EVENT_SIGNAL_DETECT | 2849 ICE_AQ_LINK_EVENT_AN_COMPLETED | 2850 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)), 2851 NULL); 2852 if (ret != ICE_SUCCESS) 2853 PMD_DRV_LOG(WARNING, "Fail to set phy mask"); 2854 2855 ice_get_init_link_status(dev); 2856 2857 ice_dev_set_link_up(dev); 2858 2859 /* Call get_link_info aq commond to enable/disable LSE */ 2860 ice_link_update(dev, 0); 2861 2862 pf->adapter_stopped = false; 2863 2864 /* Set the max frame size to default value*/ 2865 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ? 2866 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len : 2867 ICE_FRAME_SIZE_MAX; 2868 2869 /* Set the max frame size to HW*/ 2870 ice_aq_set_mac_cfg(hw, max_frame_size, NULL); 2871 2872 return 0; 2873 2874 /* stop the started queues if failed to start all queues */ 2875 rx_err: 2876 for (i = 0; i < nb_rxq; i++) 2877 ice_rx_queue_stop(dev, i); 2878 tx_err: 2879 for (i = 0; i < nb_txq; i++) 2880 ice_tx_queue_stop(dev, i); 2881 2882 return -EIO; 2883 } 2884 2885 static int 2886 ice_dev_reset(struct rte_eth_dev *dev) 2887 { 2888 int ret; 2889 2890 if (dev->data->sriov.active) 2891 return -ENOTSUP; 2892 2893 ret = ice_dev_uninit(dev); 2894 if (ret) { 2895 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret); 2896 return -ENXIO; 2897 } 2898 2899 ret = ice_dev_init(dev); 2900 if (ret) { 2901 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret); 2902 return -ENXIO; 2903 } 2904 2905 return 0; 2906 } 2907 2908 static int 2909 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2910 { 2911 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2912 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2913 struct ice_vsi *vsi = pf->main_vsi; 2914 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 2915 bool is_safe_mode = pf->adapter->is_safe_mode; 2916 u64 phy_type_low; 2917 u64 phy_type_high; 2918 2919 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN; 2920 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX; 2921 dev_info->max_rx_queues = vsi->nb_qps; 2922 dev_info->max_tx_queues = vsi->nb_qps; 2923 dev_info->max_mac_addrs = vsi->max_macaddrs; 2924 dev_info->max_vfs = pci_dev->max_vfs; 2925 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; 2926 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 2927 2928 dev_info->rx_offload_capa = 2929 DEV_RX_OFFLOAD_VLAN_STRIP | 2930 DEV_RX_OFFLOAD_JUMBO_FRAME | 2931 DEV_RX_OFFLOAD_KEEP_CRC | 2932 DEV_RX_OFFLOAD_SCATTER | 2933 DEV_RX_OFFLOAD_VLAN_FILTER; 2934 dev_info->tx_offload_capa = 2935 DEV_TX_OFFLOAD_VLAN_INSERT | 2936 DEV_TX_OFFLOAD_TCP_TSO | 2937 DEV_TX_OFFLOAD_MULTI_SEGS | 2938 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 2939 dev_info->flow_type_rss_offloads = 0; 2940 2941 if (!is_safe_mode) { 2942 dev_info->rx_offload_capa |= 2943 DEV_RX_OFFLOAD_IPV4_CKSUM | 2944 DEV_RX_OFFLOAD_UDP_CKSUM | 2945 DEV_RX_OFFLOAD_TCP_CKSUM | 2946 DEV_RX_OFFLOAD_QINQ_STRIP | 2947 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2948 DEV_RX_OFFLOAD_VLAN_EXTEND | 2949 DEV_RX_OFFLOAD_RSS_HASH; 2950 dev_info->tx_offload_capa |= 2951 DEV_TX_OFFLOAD_QINQ_INSERT | 2952 DEV_TX_OFFLOAD_IPV4_CKSUM | 2953 DEV_TX_OFFLOAD_UDP_CKSUM | 2954 DEV_TX_OFFLOAD_TCP_CKSUM | 2955 DEV_TX_OFFLOAD_SCTP_CKSUM | 2956 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2957 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 2958 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL; 2959 } 2960 2961 dev_info->rx_queue_offload_capa = 0; 2962 dev_info->tx_queue_offload_capa = 0; 2963 2964 dev_info->reta_size = pf->hash_lut_size; 2965 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2966 2967 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2968 .rx_thresh = { 2969 .pthresh = ICE_DEFAULT_RX_PTHRESH, 2970 .hthresh = ICE_DEFAULT_RX_HTHRESH, 2971 .wthresh = ICE_DEFAULT_RX_WTHRESH, 2972 }, 2973 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH, 2974 .rx_drop_en = 0, 2975 .offloads = 0, 2976 }; 2977 2978 dev_info->default_txconf = (struct rte_eth_txconf) { 2979 .tx_thresh = { 2980 .pthresh = ICE_DEFAULT_TX_PTHRESH, 2981 .hthresh = ICE_DEFAULT_TX_HTHRESH, 2982 .wthresh = ICE_DEFAULT_TX_WTHRESH, 2983 }, 2984 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH, 2985 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH, 2986 .offloads = 0, 2987 }; 2988 2989 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 2990 .nb_max = ICE_MAX_RING_DESC, 2991 .nb_min = ICE_MIN_RING_DESC, 2992 .nb_align = ICE_ALIGN_RING_DESC, 2993 }; 2994 2995 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 2996 .nb_max = ICE_MAX_RING_DESC, 2997 .nb_min = ICE_MIN_RING_DESC, 2998 .nb_align = ICE_ALIGN_RING_DESC, 2999 }; 3000 3001 dev_info->speed_capa = ETH_LINK_SPEED_10M | 3002 ETH_LINK_SPEED_100M | 3003 ETH_LINK_SPEED_1G | 3004 ETH_LINK_SPEED_2_5G | 3005 ETH_LINK_SPEED_5G | 3006 ETH_LINK_SPEED_10G | 3007 ETH_LINK_SPEED_20G | 3008 ETH_LINK_SPEED_25G; 3009 3010 phy_type_low = hw->port_info->phy.phy_type_low; 3011 phy_type_high = hw->port_info->phy.phy_type_high; 3012 3013 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low)) 3014 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 3015 3016 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) || 3017 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high)) 3018 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 3019 3020 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 3021 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 3022 3023 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; 3024 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; 3025 dev_info->default_rxportconf.nb_queues = 1; 3026 dev_info->default_txportconf.nb_queues = 1; 3027 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; 3028 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; 3029 3030 return 0; 3031 } 3032 3033 static inline int 3034 ice_atomic_read_link_status(struct rte_eth_dev *dev, 3035 struct rte_eth_link *link) 3036 { 3037 struct rte_eth_link *dst = link; 3038 struct rte_eth_link *src = &dev->data->dev_link; 3039 3040 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3041 *(uint64_t *)src) == 0) 3042 return -1; 3043 3044 return 0; 3045 } 3046 3047 static inline int 3048 ice_atomic_write_link_status(struct rte_eth_dev *dev, 3049 struct rte_eth_link *link) 3050 { 3051 struct rte_eth_link *dst = &dev->data->dev_link; 3052 struct rte_eth_link *src = link; 3053 3054 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 3055 *(uint64_t *)src) == 0) 3056 return -1; 3057 3058 return 0; 3059 } 3060 3061 static int 3062 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete) 3063 { 3064 #define CHECK_INTERVAL 100 /* 100ms */ 3065 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */ 3066 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3067 struct ice_link_status link_status; 3068 struct rte_eth_link link, old; 3069 int status; 3070 unsigned int rep_cnt = MAX_REPEAT_TIME; 3071 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false; 3072 3073 memset(&link, 0, sizeof(link)); 3074 memset(&old, 0, sizeof(old)); 3075 memset(&link_status, 0, sizeof(link_status)); 3076 ice_atomic_read_link_status(dev, &old); 3077 3078 do { 3079 /* Get link status information from hardware */ 3080 status = ice_aq_get_link_info(hw->port_info, enable_lse, 3081 &link_status, NULL); 3082 if (status != ICE_SUCCESS) { 3083 link.link_speed = ETH_SPEED_NUM_100M; 3084 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3085 PMD_DRV_LOG(ERR, "Failed to get link info"); 3086 goto out; 3087 } 3088 3089 link.link_status = link_status.link_info & ICE_AQ_LINK_UP; 3090 if (!wait_to_complete || link.link_status) 3091 break; 3092 3093 rte_delay_ms(CHECK_INTERVAL); 3094 } while (--rep_cnt); 3095 3096 if (!link.link_status) 3097 goto out; 3098 3099 /* Full-duplex operation at all supported speeds */ 3100 link.link_duplex = ETH_LINK_FULL_DUPLEX; 3101 3102 /* Parse the link status */ 3103 switch (link_status.link_speed) { 3104 case ICE_AQ_LINK_SPEED_10MB: 3105 link.link_speed = ETH_SPEED_NUM_10M; 3106 break; 3107 case ICE_AQ_LINK_SPEED_100MB: 3108 link.link_speed = ETH_SPEED_NUM_100M; 3109 break; 3110 case ICE_AQ_LINK_SPEED_1000MB: 3111 link.link_speed = ETH_SPEED_NUM_1G; 3112 break; 3113 case ICE_AQ_LINK_SPEED_2500MB: 3114 link.link_speed = ETH_SPEED_NUM_2_5G; 3115 break; 3116 case ICE_AQ_LINK_SPEED_5GB: 3117 link.link_speed = ETH_SPEED_NUM_5G; 3118 break; 3119 case ICE_AQ_LINK_SPEED_10GB: 3120 link.link_speed = ETH_SPEED_NUM_10G; 3121 break; 3122 case ICE_AQ_LINK_SPEED_20GB: 3123 link.link_speed = ETH_SPEED_NUM_20G; 3124 break; 3125 case ICE_AQ_LINK_SPEED_25GB: 3126 link.link_speed = ETH_SPEED_NUM_25G; 3127 break; 3128 case ICE_AQ_LINK_SPEED_40GB: 3129 link.link_speed = ETH_SPEED_NUM_40G; 3130 break; 3131 case ICE_AQ_LINK_SPEED_50GB: 3132 link.link_speed = ETH_SPEED_NUM_50G; 3133 break; 3134 case ICE_AQ_LINK_SPEED_100GB: 3135 link.link_speed = ETH_SPEED_NUM_100G; 3136 break; 3137 case ICE_AQ_LINK_SPEED_UNKNOWN: 3138 default: 3139 PMD_DRV_LOG(ERR, "Unknown link speed"); 3140 link.link_speed = ETH_SPEED_NUM_NONE; 3141 break; 3142 } 3143 3144 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 3145 ETH_LINK_SPEED_FIXED); 3146 3147 out: 3148 ice_atomic_write_link_status(dev, &link); 3149 if (link.link_status == old.link_status) 3150 return -1; 3151 3152 return 0; 3153 } 3154 3155 /* Force the physical link state by getting the current PHY capabilities from 3156 * hardware and setting the PHY config based on the determined capabilities. If 3157 * link changes, link event will be triggered because both the Enable Automatic 3158 * Link Update and LESM Enable bits are set when setting the PHY capabilities. 3159 */ 3160 static enum ice_status 3161 ice_force_phys_link_state(struct ice_hw *hw, bool link_up) 3162 { 3163 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3164 struct ice_aqc_get_phy_caps_data *pcaps; 3165 struct ice_port_info *pi; 3166 enum ice_status status; 3167 3168 if (!hw || !hw->port_info) 3169 return ICE_ERR_PARAM; 3170 3171 pi = hw->port_info; 3172 3173 pcaps = (struct ice_aqc_get_phy_caps_data *) 3174 ice_malloc(hw, sizeof(*pcaps)); 3175 if (!pcaps) 3176 return ICE_ERR_NO_MEMORY; 3177 3178 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 3179 NULL); 3180 if (status) 3181 goto out; 3182 3183 /* No change in link */ 3184 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) && 3185 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP)) 3186 goto out; 3187 3188 cfg.phy_type_low = pcaps->phy_type_low; 3189 cfg.phy_type_high = pcaps->phy_type_high; 3190 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3191 cfg.low_power_ctrl = pcaps->low_power_ctrl; 3192 cfg.eee_cap = pcaps->eee_cap; 3193 cfg.eeer_value = pcaps->eeer_value; 3194 cfg.link_fec_opt = pcaps->link_fec_options; 3195 if (link_up) 3196 cfg.caps |= ICE_AQ_PHY_ENA_LINK; 3197 else 3198 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK; 3199 3200 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3201 3202 out: 3203 ice_free(hw, pcaps); 3204 return status; 3205 } 3206 3207 static int 3208 ice_dev_set_link_up(struct rte_eth_dev *dev) 3209 { 3210 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3211 3212 return ice_force_phys_link_state(hw, true); 3213 } 3214 3215 static int 3216 ice_dev_set_link_down(struct rte_eth_dev *dev) 3217 { 3218 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3219 3220 return ice_force_phys_link_state(hw, false); 3221 } 3222 3223 static int 3224 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3225 { 3226 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3227 struct rte_eth_dev_data *dev_data = pf->dev_data; 3228 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD; 3229 3230 /* check if mtu is within the allowed range */ 3231 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX) 3232 return -EINVAL; 3233 3234 /* mtu setting is forbidden if port is start */ 3235 if (dev_data->dev_started) { 3236 PMD_DRV_LOG(ERR, 3237 "port %d must be stopped before configuration", 3238 dev_data->port_id); 3239 return -EBUSY; 3240 } 3241 3242 if (frame_size > RTE_ETHER_MAX_LEN) 3243 dev_data->dev_conf.rxmode.offloads |= 3244 DEV_RX_OFFLOAD_JUMBO_FRAME; 3245 else 3246 dev_data->dev_conf.rxmode.offloads &= 3247 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 3248 3249 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 3250 3251 return 0; 3252 } 3253 3254 static int ice_macaddr_set(struct rte_eth_dev *dev, 3255 struct rte_ether_addr *mac_addr) 3256 { 3257 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3258 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3259 struct ice_vsi *vsi = pf->main_vsi; 3260 struct ice_mac_filter *f; 3261 uint8_t flags = 0; 3262 int ret; 3263 3264 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 3265 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 3266 return -EINVAL; 3267 } 3268 3269 TAILQ_FOREACH(f, &vsi->mac_list, next) { 3270 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr)) 3271 break; 3272 } 3273 3274 if (!f) { 3275 PMD_DRV_LOG(ERR, "Failed to find filter for default mac"); 3276 return -EIO; 3277 } 3278 3279 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr); 3280 if (ret != ICE_SUCCESS) { 3281 PMD_DRV_LOG(ERR, "Failed to delete mac filter"); 3282 return -EIO; 3283 } 3284 ret = ice_add_mac_filter(vsi, mac_addr); 3285 if (ret != ICE_SUCCESS) { 3286 PMD_DRV_LOG(ERR, "Failed to add mac filter"); 3287 return -EIO; 3288 } 3289 rte_ether_addr_copy(mac_addr, &pf->dev_addr); 3290 3291 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL; 3292 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL); 3293 if (ret != ICE_SUCCESS) 3294 PMD_DRV_LOG(ERR, "Failed to set manage mac"); 3295 3296 return 0; 3297 } 3298 3299 /* Add a MAC address, and update filters */ 3300 static int 3301 ice_macaddr_add(struct rte_eth_dev *dev, 3302 struct rte_ether_addr *mac_addr, 3303 __rte_unused uint32_t index, 3304 __rte_unused uint32_t pool) 3305 { 3306 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3307 struct ice_vsi *vsi = pf->main_vsi; 3308 int ret; 3309 3310 ret = ice_add_mac_filter(vsi, mac_addr); 3311 if (ret != ICE_SUCCESS) { 3312 PMD_DRV_LOG(ERR, "Failed to add MAC filter"); 3313 return -EINVAL; 3314 } 3315 3316 return ICE_SUCCESS; 3317 } 3318 3319 /* Remove a MAC address, and update filters */ 3320 static void 3321 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) 3322 { 3323 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3324 struct ice_vsi *vsi = pf->main_vsi; 3325 struct rte_eth_dev_data *data = dev->data; 3326 struct rte_ether_addr *macaddr; 3327 int ret; 3328 3329 macaddr = &data->mac_addrs[index]; 3330 ret = ice_remove_mac_filter(vsi, macaddr); 3331 if (ret) { 3332 PMD_DRV_LOG(ERR, "Failed to remove MAC filter"); 3333 return; 3334 } 3335 } 3336 3337 static int 3338 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 3339 { 3340 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3341 struct ice_vsi *vsi = pf->main_vsi; 3342 int ret; 3343 3344 PMD_INIT_FUNC_TRACE(); 3345 3346 if (on) { 3347 ret = ice_add_vlan_filter(vsi, vlan_id); 3348 if (ret < 0) { 3349 PMD_DRV_LOG(ERR, "Failed to add vlan filter"); 3350 return -EINVAL; 3351 } 3352 } else { 3353 ret = ice_remove_vlan_filter(vsi, vlan_id); 3354 if (ret < 0) { 3355 PMD_DRV_LOG(ERR, "Failed to remove vlan filter"); 3356 return -EINVAL; 3357 } 3358 } 3359 3360 return 0; 3361 } 3362 3363 /* Configure vlan filter on or off */ 3364 static int 3365 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on) 3366 { 3367 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3368 struct ice_vsi_ctx ctxt; 3369 uint8_t sec_flags, sw_flags2; 3370 int ret = 0; 3371 3372 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA << 3373 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S; 3374 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA; 3375 3376 if (on) { 3377 vsi->info.sec_flags |= sec_flags; 3378 vsi->info.sw_flags2 |= sw_flags2; 3379 } else { 3380 vsi->info.sec_flags &= ~sec_flags; 3381 vsi->info.sw_flags2 &= ~sw_flags2; 3382 } 3383 vsi->info.sw_id = hw->port_info->sw_id; 3384 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 3385 ctxt.info.valid_sections = 3386 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 3387 ICE_AQ_VSI_PROP_SECURITY_VALID); 3388 ctxt.vsi_num = vsi->vsi_id; 3389 3390 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 3391 if (ret) { 3392 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning", 3393 on ? "enable" : "disable"); 3394 return -EINVAL; 3395 } else { 3396 vsi->info.valid_sections |= 3397 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID | 3398 ICE_AQ_VSI_PROP_SECURITY_VALID); 3399 } 3400 3401 /* consist with other drivers, allow untagged packet when vlan filter on */ 3402 if (on) 3403 ret = ice_add_vlan_filter(vsi, 0); 3404 else 3405 ret = ice_remove_vlan_filter(vsi, 0); 3406 3407 return 0; 3408 } 3409 3410 static int 3411 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) 3412 { 3413 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3414 struct ice_vsi_ctx ctxt; 3415 uint8_t vlan_flags; 3416 int ret = 0; 3417 3418 /* Check if it has been already on or off */ 3419 if (vsi->info.valid_sections & 3420 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { 3421 if (on) { 3422 if ((vsi->info.vlan_flags & 3423 ICE_AQ_VSI_VLAN_EMOD_M) == 3424 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) 3425 return 0; /* already on */ 3426 } else { 3427 if ((vsi->info.vlan_flags & 3428 ICE_AQ_VSI_VLAN_EMOD_M) == 3429 ICE_AQ_VSI_VLAN_EMOD_NOTHING) 3430 return 0; /* already off */ 3431 } 3432 } 3433 3434 if (on) 3435 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; 3436 else 3437 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; 3438 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); 3439 vsi->info.vlan_flags |= vlan_flags; 3440 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 3441 ctxt.info.valid_sections = 3442 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3443 ctxt.vsi_num = vsi->vsi_id; 3444 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 3445 if (ret) { 3446 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping", 3447 on ? "enable" : "disable"); 3448 return -EINVAL; 3449 } 3450 3451 vsi->info.valid_sections |= 3452 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3453 3454 return ret; 3455 } 3456 3457 static int 3458 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask) 3459 { 3460 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3461 struct ice_vsi *vsi = pf->main_vsi; 3462 struct rte_eth_rxmode *rxmode; 3463 3464 rxmode = &dev->data->dev_conf.rxmode; 3465 if (mask & ETH_VLAN_FILTER_MASK) { 3466 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 3467 ice_vsi_config_vlan_filter(vsi, TRUE); 3468 else 3469 ice_vsi_config_vlan_filter(vsi, FALSE); 3470 } 3471 3472 if (mask & ETH_VLAN_STRIP_MASK) { 3473 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 3474 ice_vsi_config_vlan_stripping(vsi, TRUE); 3475 else 3476 ice_vsi_config_vlan_stripping(vsi, FALSE); 3477 } 3478 3479 if (mask & ETH_VLAN_EXTEND_MASK) { 3480 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 3481 ice_vsi_config_double_vlan(vsi, TRUE); 3482 else 3483 ice_vsi_config_double_vlan(vsi, FALSE); 3484 } 3485 3486 return 0; 3487 } 3488 3489 static int 3490 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 3491 { 3492 struct ice_pf *pf = ICE_VSI_TO_PF(vsi); 3493 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3494 int ret; 3495 3496 if (!lut) 3497 return -EINVAL; 3498 3499 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 3500 ret = ice_aq_get_rss_lut(hw, vsi->idx, 3501 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); 3502 if (ret) { 3503 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 3504 return -EINVAL; 3505 } 3506 } else { 3507 uint64_t *lut_dw = (uint64_t *)lut; 3508 uint16_t i, lut_size_dw = lut_size / 4; 3509 3510 for (i = 0; i < lut_size_dw; i++) 3511 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i)); 3512 } 3513 3514 return 0; 3515 } 3516 3517 static int 3518 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size) 3519 { 3520 struct ice_pf *pf; 3521 struct ice_hw *hw; 3522 int ret; 3523 3524 if (!vsi || !lut) 3525 return -EINVAL; 3526 3527 pf = ICE_VSI_TO_PF(vsi); 3528 hw = ICE_VSI_TO_HW(vsi); 3529 3530 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) { 3531 ret = ice_aq_set_rss_lut(hw, vsi->idx, 3532 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size); 3533 if (ret) { 3534 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 3535 return -EINVAL; 3536 } 3537 } else { 3538 uint64_t *lut_dw = (uint64_t *)lut; 3539 uint16_t i, lut_size_dw = lut_size / 4; 3540 3541 for (i = 0; i < lut_size_dw; i++) 3542 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]); 3543 3544 ice_flush(hw); 3545 } 3546 3547 return 0; 3548 } 3549 3550 static int 3551 ice_rss_reta_update(struct rte_eth_dev *dev, 3552 struct rte_eth_rss_reta_entry64 *reta_conf, 3553 uint16_t reta_size) 3554 { 3555 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3556 uint16_t i, lut_size = pf->hash_lut_size; 3557 uint16_t idx, shift; 3558 uint8_t *lut; 3559 int ret; 3560 3561 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 && 3562 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 && 3563 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) { 3564 PMD_DRV_LOG(ERR, 3565 "The size of hash lookup table configured (%d)" 3566 "doesn't match the number hardware can " 3567 "supported (128, 512, 2048)", 3568 reta_size); 3569 return -EINVAL; 3570 } 3571 3572 /* It MUST use the current LUT size to get the RSS lookup table, 3573 * otherwise if will fail with -100 error code. 3574 */ 3575 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0); 3576 if (!lut) { 3577 PMD_DRV_LOG(ERR, "No memory can be allocated"); 3578 return -ENOMEM; 3579 } 3580 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size); 3581 if (ret) 3582 goto out; 3583 3584 for (i = 0; i < reta_size; i++) { 3585 idx = i / RTE_RETA_GROUP_SIZE; 3586 shift = i % RTE_RETA_GROUP_SIZE; 3587 if (reta_conf[idx].mask & (1ULL << shift)) 3588 lut[i] = reta_conf[idx].reta[shift]; 3589 } 3590 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size); 3591 if (ret == 0 && lut_size != reta_size) { 3592 PMD_DRV_LOG(INFO, 3593 "The size of hash lookup table is changed from (%d) to (%d)", 3594 lut_size, reta_size); 3595 pf->hash_lut_size = reta_size; 3596 } 3597 3598 out: 3599 rte_free(lut); 3600 3601 return ret; 3602 } 3603 3604 static int 3605 ice_rss_reta_query(struct rte_eth_dev *dev, 3606 struct rte_eth_rss_reta_entry64 *reta_conf, 3607 uint16_t reta_size) 3608 { 3609 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3610 uint16_t i, lut_size = pf->hash_lut_size; 3611 uint16_t idx, shift; 3612 uint8_t *lut; 3613 int ret; 3614 3615 if (reta_size != lut_size) { 3616 PMD_DRV_LOG(ERR, 3617 "The size of hash lookup table configured (%d)" 3618 "doesn't match the number hardware can " 3619 "supported (%d)", 3620 reta_size, lut_size); 3621 return -EINVAL; 3622 } 3623 3624 lut = rte_zmalloc(NULL, reta_size, 0); 3625 if (!lut) { 3626 PMD_DRV_LOG(ERR, "No memory can be allocated"); 3627 return -ENOMEM; 3628 } 3629 3630 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size); 3631 if (ret) 3632 goto out; 3633 3634 for (i = 0; i < reta_size; i++) { 3635 idx = i / RTE_RETA_GROUP_SIZE; 3636 shift = i % RTE_RETA_GROUP_SIZE; 3637 if (reta_conf[idx].mask & (1ULL << shift)) 3638 reta_conf[idx].reta[shift] = lut[i]; 3639 } 3640 3641 out: 3642 rte_free(lut); 3643 3644 return ret; 3645 } 3646 3647 static int 3648 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len) 3649 { 3650 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3651 int ret = 0; 3652 3653 if (!key || key_len == 0) { 3654 PMD_DRV_LOG(DEBUG, "No key to be configured"); 3655 return 0; 3656 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) * 3657 sizeof(uint32_t)) { 3658 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 3659 return -EINVAL; 3660 } 3661 3662 struct ice_aqc_get_set_rss_keys *key_dw = 3663 (struct ice_aqc_get_set_rss_keys *)key; 3664 3665 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw); 3666 if (ret) { 3667 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ"); 3668 ret = -EINVAL; 3669 } 3670 3671 return ret; 3672 } 3673 3674 static int 3675 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len) 3676 { 3677 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 3678 int ret; 3679 3680 if (!key || !key_len) 3681 return -EINVAL; 3682 3683 ret = ice_aq_get_rss_key 3684 (hw, vsi->idx, 3685 (struct ice_aqc_get_set_rss_keys *)key); 3686 if (ret) { 3687 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ"); 3688 return -EINVAL; 3689 } 3690 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 3691 3692 return 0; 3693 } 3694 3695 static int 3696 ice_rss_hash_update(struct rte_eth_dev *dev, 3697 struct rte_eth_rss_conf *rss_conf) 3698 { 3699 enum ice_status status = ICE_SUCCESS; 3700 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3701 struct ice_vsi *vsi = pf->main_vsi; 3702 3703 /* set hash key */ 3704 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len); 3705 if (status) 3706 return status; 3707 3708 /* TODO: hash enable config, ice_add_rss_cfg */ 3709 return 0; 3710 } 3711 3712 static int 3713 ice_rss_hash_conf_get(struct rte_eth_dev *dev, 3714 struct rte_eth_rss_conf *rss_conf) 3715 { 3716 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3717 struct ice_vsi *vsi = pf->main_vsi; 3718 3719 ice_get_rss_key(vsi, rss_conf->rss_key, 3720 &rss_conf->rss_key_len); 3721 3722 /* TODO: default set to 0 as hf config is not supported now */ 3723 rss_conf->rss_hf = 0; 3724 return 0; 3725 } 3726 3727 static int 3728 ice_promisc_enable(struct rte_eth_dev *dev) 3729 { 3730 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3731 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3732 struct ice_vsi *vsi = pf->main_vsi; 3733 enum ice_status status; 3734 uint8_t pmask; 3735 int ret = 0; 3736 3737 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 3738 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3739 3740 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 3741 switch (status) { 3742 case ICE_ERR_ALREADY_EXISTS: 3743 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled"); 3744 case ICE_SUCCESS: 3745 break; 3746 default: 3747 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status); 3748 ret = -EAGAIN; 3749 } 3750 3751 return ret; 3752 } 3753 3754 static int 3755 ice_promisc_disable(struct rte_eth_dev *dev) 3756 { 3757 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3758 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3759 struct ice_vsi *vsi = pf->main_vsi; 3760 enum ice_status status; 3761 uint8_t pmask; 3762 int ret = 0; 3763 3764 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX | 3765 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3766 3767 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 3768 if (status != ICE_SUCCESS) { 3769 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status); 3770 ret = -EAGAIN; 3771 } 3772 3773 return ret; 3774 } 3775 3776 static int 3777 ice_allmulti_enable(struct rte_eth_dev *dev) 3778 { 3779 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3780 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3781 struct ice_vsi *vsi = pf->main_vsi; 3782 enum ice_status status; 3783 uint8_t pmask; 3784 int ret = 0; 3785 3786 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3787 3788 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0); 3789 3790 switch (status) { 3791 case ICE_ERR_ALREADY_EXISTS: 3792 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled"); 3793 case ICE_SUCCESS: 3794 break; 3795 default: 3796 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status); 3797 ret = -EAGAIN; 3798 } 3799 3800 return ret; 3801 } 3802 3803 static int 3804 ice_allmulti_disable(struct rte_eth_dev *dev) 3805 { 3806 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3807 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3808 struct ice_vsi *vsi = pf->main_vsi; 3809 enum ice_status status; 3810 uint8_t pmask; 3811 int ret = 0; 3812 3813 if (dev->data->promiscuous == 1) 3814 return 0; /* must remain in all_multicast mode */ 3815 3816 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX; 3817 3818 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0); 3819 if (status != ICE_SUCCESS) { 3820 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status); 3821 ret = -EAGAIN; 3822 } 3823 3824 return ret; 3825 } 3826 3827 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev, 3828 uint16_t queue_id) 3829 { 3830 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3831 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3832 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3833 uint32_t val; 3834 uint16_t msix_intr; 3835 3836 msix_intr = intr_handle->intr_vec[queue_id]; 3837 3838 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 3839 GLINT_DYN_CTL_ITR_INDX_M; 3840 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; 3841 3842 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val); 3843 rte_intr_ack(&pci_dev->intr_handle); 3844 3845 return 0; 3846 } 3847 3848 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev, 3849 uint16_t queue_id) 3850 { 3851 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); 3852 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3853 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3854 uint16_t msix_intr; 3855 3856 msix_intr = intr_handle->intr_vec[queue_id]; 3857 3858 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); 3859 3860 return 0; 3861 } 3862 3863 static int 3864 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3865 { 3866 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3867 u32 full_ver; 3868 u8 ver, patch; 3869 u16 build; 3870 int ret; 3871 3872 full_ver = hw->nvm.oem_ver; 3873 ver = (u8)(full_ver >> 24); 3874 build = (u16)((full_ver >> 8) & 0xffff); 3875 patch = (u8)(full_ver & 0xff); 3876 3877 ret = snprintf(fw_version, fw_size, 3878 "%d.%d%d 0x%08x %d.%d.%d", 3879 ((hw->nvm.ver >> 12) & 0xf), 3880 ((hw->nvm.ver >> 4) & 0xff), 3881 (hw->nvm.ver & 0xf), hw->nvm.eetrack, 3882 ver, build, patch); 3883 3884 /* add the size of '\0' */ 3885 ret += 1; 3886 if (fw_size < (u32)ret) 3887 return ret; 3888 else 3889 return 0; 3890 } 3891 3892 static int 3893 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) 3894 { 3895 struct ice_hw *hw; 3896 struct ice_vsi_ctx ctxt; 3897 uint8_t vlan_flags = 0; 3898 int ret; 3899 3900 if (!vsi || !info) { 3901 PMD_DRV_LOG(ERR, "invalid parameters"); 3902 return -EINVAL; 3903 } 3904 3905 if (info->on) { 3906 vsi->info.pvid = info->config.pvid; 3907 /** 3908 * If insert pvid is enabled, only tagged pkts are 3909 * allowed to be sent out. 3910 */ 3911 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | 3912 ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 3913 } else { 3914 vsi->info.pvid = 0; 3915 if (info->config.reject.tagged == 0) 3916 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; 3917 3918 if (info->config.reject.untagged == 0) 3919 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; 3920 } 3921 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | 3922 ICE_AQ_VSI_VLAN_MODE_M); 3923 vsi->info.vlan_flags |= vlan_flags; 3924 memset(&ctxt, 0, sizeof(ctxt)); 3925 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); 3926 ctxt.info.valid_sections = 3927 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3928 ctxt.vsi_num = vsi->vsi_id; 3929 3930 hw = ICE_VSI_TO_HW(vsi); 3931 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL); 3932 if (ret != ICE_SUCCESS) { 3933 PMD_DRV_LOG(ERR, 3934 "update VSI for VLAN insert failed, err %d", 3935 ret); 3936 return -EINVAL; 3937 } 3938 3939 vsi->info.valid_sections |= 3940 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); 3941 3942 return ret; 3943 } 3944 3945 static int 3946 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 3947 { 3948 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3949 struct ice_vsi *vsi = pf->main_vsi; 3950 struct rte_eth_dev_data *data = pf->dev_data; 3951 struct ice_vsi_vlan_pvid_info info; 3952 int ret; 3953 3954 memset(&info, 0, sizeof(info)); 3955 info.on = on; 3956 if (info.on) { 3957 info.config.pvid = pvid; 3958 } else { 3959 info.config.reject.tagged = 3960 data->dev_conf.txmode.hw_vlan_reject_tagged; 3961 info.config.reject.untagged = 3962 data->dev_conf.txmode.hw_vlan_reject_untagged; 3963 } 3964 3965 ret = ice_vsi_vlan_pvid_set(vsi, &info); 3966 if (ret < 0) { 3967 PMD_DRV_LOG(ERR, "Failed to set pvid."); 3968 return -EINVAL; 3969 } 3970 3971 return 0; 3972 } 3973 3974 static int 3975 ice_get_eeprom_length(struct rte_eth_dev *dev) 3976 { 3977 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3978 3979 /* Convert word count to byte count */ 3980 return hw->nvm.sr_words << 1; 3981 } 3982 3983 static int 3984 ice_get_eeprom(struct rte_eth_dev *dev, 3985 struct rte_dev_eeprom_info *eeprom) 3986 { 3987 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3988 uint16_t *data = eeprom->data; 3989 uint16_t first_word, last_word, nwords; 3990 enum ice_status status = ICE_SUCCESS; 3991 3992 first_word = eeprom->offset >> 1; 3993 last_word = (eeprom->offset + eeprom->length - 1) >> 1; 3994 nwords = last_word - first_word + 1; 3995 3996 if (first_word >= hw->nvm.sr_words || 3997 last_word >= hw->nvm.sr_words) { 3998 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range."); 3999 return -EINVAL; 4000 } 4001 4002 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4003 4004 status = ice_read_sr_buf(hw, first_word, &nwords, data); 4005 if (status) { 4006 PMD_DRV_LOG(ERR, "EEPROM read failed."); 4007 eeprom->length = sizeof(uint16_t) * nwords; 4008 return -EIO; 4009 } 4010 4011 return 0; 4012 } 4013 4014 static void 4015 ice_stat_update_32(struct ice_hw *hw, 4016 uint32_t reg, 4017 bool offset_loaded, 4018 uint64_t *offset, 4019 uint64_t *stat) 4020 { 4021 uint64_t new_data; 4022 4023 new_data = (uint64_t)ICE_READ_REG(hw, reg); 4024 if (!offset_loaded) 4025 *offset = new_data; 4026 4027 if (new_data >= *offset) 4028 *stat = (uint64_t)(new_data - *offset); 4029 else 4030 *stat = (uint64_t)((new_data + 4031 ((uint64_t)1 << ICE_32_BIT_WIDTH)) 4032 - *offset); 4033 } 4034 4035 static void 4036 ice_stat_update_40(struct ice_hw *hw, 4037 uint32_t hireg, 4038 uint32_t loreg, 4039 bool offset_loaded, 4040 uint64_t *offset, 4041 uint64_t *stat) 4042 { 4043 uint64_t new_data; 4044 4045 new_data = (uint64_t)ICE_READ_REG(hw, loreg); 4046 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) << 4047 ICE_32_BIT_WIDTH; 4048 4049 if (!offset_loaded) 4050 *offset = new_data; 4051 4052 if (new_data >= *offset) 4053 *stat = new_data - *offset; 4054 else 4055 *stat = (uint64_t)((new_data + 4056 ((uint64_t)1 << ICE_40_BIT_WIDTH)) - 4057 *offset); 4058 4059 *stat &= ICE_40_BIT_MASK; 4060 } 4061 4062 /* Get all the statistics of a VSI */ 4063 static void 4064 ice_update_vsi_stats(struct ice_vsi *vsi) 4065 { 4066 struct ice_eth_stats *oes = &vsi->eth_stats_offset; 4067 struct ice_eth_stats *nes = &vsi->eth_stats; 4068 struct ice_hw *hw = ICE_VSI_TO_HW(vsi); 4069 int idx = rte_le_to_cpu_16(vsi->vsi_id); 4070 4071 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx), 4072 vsi->offset_loaded, &oes->rx_bytes, 4073 &nes->rx_bytes); 4074 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx), 4075 vsi->offset_loaded, &oes->rx_unicast, 4076 &nes->rx_unicast); 4077 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx), 4078 vsi->offset_loaded, &oes->rx_multicast, 4079 &nes->rx_multicast); 4080 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), 4081 vsi->offset_loaded, &oes->rx_broadcast, 4082 &nes->rx_broadcast); 4083 /* enlarge the limitation when rx_bytes overflowed */ 4084 if (vsi->offset_loaded) { 4085 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes) 4086 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4087 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes); 4088 } 4089 vsi->old_rx_bytes = nes->rx_bytes; 4090 /* exclude CRC bytes */ 4091 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + 4092 nes->rx_broadcast) * RTE_ETHER_CRC_LEN; 4093 4094 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded, 4095 &oes->rx_discards, &nes->rx_discards); 4096 /* GLV_REPC not supported */ 4097 /* GLV_RMPC not supported */ 4098 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded, 4099 &oes->rx_unknown_protocol, 4100 &nes->rx_unknown_protocol); 4101 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx), 4102 vsi->offset_loaded, &oes->tx_bytes, 4103 &nes->tx_bytes); 4104 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx), 4105 vsi->offset_loaded, &oes->tx_unicast, 4106 &nes->tx_unicast); 4107 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx), 4108 vsi->offset_loaded, &oes->tx_multicast, 4109 &nes->tx_multicast); 4110 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx), 4111 vsi->offset_loaded, &oes->tx_broadcast, 4112 &nes->tx_broadcast); 4113 /* GLV_TDPC not supported */ 4114 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, 4115 &oes->tx_errors, &nes->tx_errors); 4116 /* enlarge the limitation when tx_bytes overflowed */ 4117 if (vsi->offset_loaded) { 4118 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes) 4119 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4120 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes); 4121 } 4122 vsi->old_tx_bytes = nes->tx_bytes; 4123 vsi->offset_loaded = true; 4124 4125 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", 4126 vsi->vsi_id); 4127 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes); 4128 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast); 4129 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast); 4130 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast); 4131 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards); 4132 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 4133 nes->rx_unknown_protocol); 4134 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes); 4135 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast); 4136 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast); 4137 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast); 4138 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards); 4139 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors); 4140 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************", 4141 vsi->vsi_id); 4142 } 4143 4144 static void 4145 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) 4146 { 4147 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 4148 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */ 4149 4150 /* Get statistics of struct ice_eth_stats */ 4151 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport), 4152 GLPRT_GORCL(hw->port_info->lport), 4153 pf->offset_loaded, &os->eth.rx_bytes, 4154 &ns->eth.rx_bytes); 4155 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport), 4156 GLPRT_UPRCL(hw->port_info->lport), 4157 pf->offset_loaded, &os->eth.rx_unicast, 4158 &ns->eth.rx_unicast); 4159 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport), 4160 GLPRT_MPRCL(hw->port_info->lport), 4161 pf->offset_loaded, &os->eth.rx_multicast, 4162 &ns->eth.rx_multicast); 4163 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport), 4164 GLPRT_BPRCL(hw->port_info->lport), 4165 pf->offset_loaded, &os->eth.rx_broadcast, 4166 &ns->eth.rx_broadcast); 4167 ice_stat_update_32(hw, PRTRPB_RDPC, 4168 pf->offset_loaded, &os->eth.rx_discards, 4169 &ns->eth.rx_discards); 4170 /* enlarge the limitation when rx_bytes overflowed */ 4171 if (pf->offset_loaded) { 4172 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes) 4173 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4174 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes); 4175 } 4176 pf->old_rx_bytes = ns->eth.rx_bytes; 4177 4178 /* Workaround: CRC size should not be included in byte statistics, 4179 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx 4180 * packet. 4181 */ 4182 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast + 4183 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN; 4184 4185 /* GLPRT_REPC not supported */ 4186 /* GLPRT_RMPC not supported */ 4187 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport), 4188 pf->offset_loaded, 4189 &os->eth.rx_unknown_protocol, 4190 &ns->eth.rx_unknown_protocol); 4191 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport), 4192 GLPRT_GOTCL(hw->port_info->lport), 4193 pf->offset_loaded, &os->eth.tx_bytes, 4194 &ns->eth.tx_bytes); 4195 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport), 4196 GLPRT_UPTCL(hw->port_info->lport), 4197 pf->offset_loaded, &os->eth.tx_unicast, 4198 &ns->eth.tx_unicast); 4199 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport), 4200 GLPRT_MPTCL(hw->port_info->lport), 4201 pf->offset_loaded, &os->eth.tx_multicast, 4202 &ns->eth.tx_multicast); 4203 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport), 4204 GLPRT_BPTCL(hw->port_info->lport), 4205 pf->offset_loaded, &os->eth.tx_broadcast, 4206 &ns->eth.tx_broadcast); 4207 /* enlarge the limitation when tx_bytes overflowed */ 4208 if (pf->offset_loaded) { 4209 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes) 4210 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; 4211 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes); 4212 } 4213 pf->old_tx_bytes = ns->eth.tx_bytes; 4214 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + 4215 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; 4216 4217 /* GLPRT_TEPC not supported */ 4218 4219 /* additional port specific stats */ 4220 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport), 4221 pf->offset_loaded, &os->tx_dropped_link_down, 4222 &ns->tx_dropped_link_down); 4223 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport), 4224 pf->offset_loaded, &os->crc_errors, 4225 &ns->crc_errors); 4226 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport), 4227 pf->offset_loaded, &os->illegal_bytes, 4228 &ns->illegal_bytes); 4229 /* GLPRT_ERRBC not supported */ 4230 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport), 4231 pf->offset_loaded, &os->mac_local_faults, 4232 &ns->mac_local_faults); 4233 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport), 4234 pf->offset_loaded, &os->mac_remote_faults, 4235 &ns->mac_remote_faults); 4236 4237 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport), 4238 pf->offset_loaded, &os->rx_len_errors, 4239 &ns->rx_len_errors); 4240 4241 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport), 4242 pf->offset_loaded, &os->link_xon_rx, 4243 &ns->link_xon_rx); 4244 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport), 4245 pf->offset_loaded, &os->link_xoff_rx, 4246 &ns->link_xoff_rx); 4247 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport), 4248 pf->offset_loaded, &os->link_xon_tx, 4249 &ns->link_xon_tx); 4250 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport), 4251 pf->offset_loaded, &os->link_xoff_tx, 4252 &ns->link_xoff_tx); 4253 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport), 4254 GLPRT_PRC64L(hw->port_info->lport), 4255 pf->offset_loaded, &os->rx_size_64, 4256 &ns->rx_size_64); 4257 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport), 4258 GLPRT_PRC127L(hw->port_info->lport), 4259 pf->offset_loaded, &os->rx_size_127, 4260 &ns->rx_size_127); 4261 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport), 4262 GLPRT_PRC255L(hw->port_info->lport), 4263 pf->offset_loaded, &os->rx_size_255, 4264 &ns->rx_size_255); 4265 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport), 4266 GLPRT_PRC511L(hw->port_info->lport), 4267 pf->offset_loaded, &os->rx_size_511, 4268 &ns->rx_size_511); 4269 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport), 4270 GLPRT_PRC1023L(hw->port_info->lport), 4271 pf->offset_loaded, &os->rx_size_1023, 4272 &ns->rx_size_1023); 4273 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport), 4274 GLPRT_PRC1522L(hw->port_info->lport), 4275 pf->offset_loaded, &os->rx_size_1522, 4276 &ns->rx_size_1522); 4277 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport), 4278 GLPRT_PRC9522L(hw->port_info->lport), 4279 pf->offset_loaded, &os->rx_size_big, 4280 &ns->rx_size_big); 4281 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport), 4282 pf->offset_loaded, &os->rx_undersize, 4283 &ns->rx_undersize); 4284 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport), 4285 pf->offset_loaded, &os->rx_fragments, 4286 &ns->rx_fragments); 4287 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport), 4288 pf->offset_loaded, &os->rx_oversize, 4289 &ns->rx_oversize); 4290 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport), 4291 pf->offset_loaded, &os->rx_jabber, 4292 &ns->rx_jabber); 4293 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport), 4294 GLPRT_PTC64L(hw->port_info->lport), 4295 pf->offset_loaded, &os->tx_size_64, 4296 &ns->tx_size_64); 4297 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport), 4298 GLPRT_PTC127L(hw->port_info->lport), 4299 pf->offset_loaded, &os->tx_size_127, 4300 &ns->tx_size_127); 4301 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport), 4302 GLPRT_PTC255L(hw->port_info->lport), 4303 pf->offset_loaded, &os->tx_size_255, 4304 &ns->tx_size_255); 4305 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport), 4306 GLPRT_PTC511L(hw->port_info->lport), 4307 pf->offset_loaded, &os->tx_size_511, 4308 &ns->tx_size_511); 4309 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport), 4310 GLPRT_PTC1023L(hw->port_info->lport), 4311 pf->offset_loaded, &os->tx_size_1023, 4312 &ns->tx_size_1023); 4313 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport), 4314 GLPRT_PTC1522L(hw->port_info->lport), 4315 pf->offset_loaded, &os->tx_size_1522, 4316 &ns->tx_size_1522); 4317 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport), 4318 GLPRT_PTC9522L(hw->port_info->lport), 4319 pf->offset_loaded, &os->tx_size_big, 4320 &ns->tx_size_big); 4321 4322 /* GLPRT_MSPDC not supported */ 4323 /* GLPRT_XEC not supported */ 4324 4325 pf->offset_loaded = true; 4326 4327 if (pf->main_vsi) 4328 ice_update_vsi_stats(pf->main_vsi); 4329 } 4330 4331 /* Get all statistics of a port */ 4332 static int 4333 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 4334 { 4335 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4336 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4337 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */ 4338 4339 /* call read registers - updates values, now write them to struct */ 4340 ice_read_stats_registers(pf, hw); 4341 4342 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast + 4343 pf->main_vsi->eth_stats.rx_multicast + 4344 pf->main_vsi->eth_stats.rx_broadcast - 4345 pf->main_vsi->eth_stats.rx_discards; 4346 stats->opackets = ns->eth.tx_unicast + 4347 ns->eth.tx_multicast + 4348 ns->eth.tx_broadcast; 4349 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes; 4350 stats->obytes = ns->eth.tx_bytes; 4351 stats->oerrors = ns->eth.tx_errors + 4352 pf->main_vsi->eth_stats.tx_errors; 4353 4354 /* Rx Errors */ 4355 stats->imissed = ns->eth.rx_discards + 4356 pf->main_vsi->eth_stats.rx_discards; 4357 stats->ierrors = ns->crc_errors + 4358 ns->rx_undersize + 4359 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber; 4360 4361 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************"); 4362 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes); 4363 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast); 4364 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast); 4365 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast); 4366 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards); 4367 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"", 4368 pf->main_vsi->eth_stats.rx_discards); 4369 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"", 4370 ns->eth.rx_unknown_protocol); 4371 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes); 4372 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast); 4373 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast); 4374 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast); 4375 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards); 4376 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"", 4377 pf->main_vsi->eth_stats.tx_discards); 4378 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors); 4379 4380 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"", 4381 ns->tx_dropped_link_down); 4382 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors); 4383 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"", 4384 ns->illegal_bytes); 4385 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes); 4386 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"", 4387 ns->mac_local_faults); 4388 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"", 4389 ns->mac_remote_faults); 4390 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx); 4391 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx); 4392 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx); 4393 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx); 4394 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64); 4395 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127); 4396 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255); 4397 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511); 4398 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023); 4399 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522); 4400 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big); 4401 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize); 4402 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments); 4403 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize); 4404 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber); 4405 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64); 4406 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127); 4407 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255); 4408 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511); 4409 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023); 4410 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522); 4411 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big); 4412 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors); 4413 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************"); 4414 return 0; 4415 } 4416 4417 /* Reset the statistics */ 4418 static int 4419 ice_stats_reset(struct rte_eth_dev *dev) 4420 { 4421 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4422 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4423 4424 /* Mark PF and VSI stats to update the offset, aka "reset" */ 4425 pf->offset_loaded = false; 4426 if (pf->main_vsi) 4427 pf->main_vsi->offset_loaded = false; 4428 4429 /* read the stats, reading current register values into offset */ 4430 ice_read_stats_registers(pf, hw); 4431 4432 return 0; 4433 } 4434 4435 static uint32_t 4436 ice_xstats_calc_num(void) 4437 { 4438 uint32_t num; 4439 4440 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS; 4441 4442 return num; 4443 } 4444 4445 static int 4446 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 4447 unsigned int n) 4448 { 4449 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4450 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4451 unsigned int i; 4452 unsigned int count; 4453 struct ice_hw_port_stats *hw_stats = &pf->stats; 4454 4455 count = ice_xstats_calc_num(); 4456 if (n < count) 4457 return count; 4458 4459 ice_read_stats_registers(pf, hw); 4460 4461 if (!xstats) 4462 return 0; 4463 4464 count = 0; 4465 4466 /* Get stats from ice_eth_stats struct */ 4467 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 4468 xstats[count].value = 4469 *(uint64_t *)((char *)&hw_stats->eth + 4470 ice_stats_strings[i].offset); 4471 xstats[count].id = count; 4472 count++; 4473 } 4474 4475 /* Get individiual stats from ice_hw_port struct */ 4476 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 4477 xstats[count].value = 4478 *(uint64_t *)((char *)hw_stats + 4479 ice_hw_port_strings[i].offset); 4480 xstats[count].id = count; 4481 count++; 4482 } 4483 4484 return count; 4485 } 4486 4487 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 4488 struct rte_eth_xstat_name *xstats_names, 4489 __rte_unused unsigned int limit) 4490 { 4491 unsigned int count = 0; 4492 unsigned int i; 4493 4494 if (!xstats_names) 4495 return ice_xstats_calc_num(); 4496 4497 /* Note: limit checked in rte_eth_xstats_names() */ 4498 4499 /* Get stats from ice_eth_stats struct */ 4500 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) { 4501 strlcpy(xstats_names[count].name, ice_stats_strings[i].name, 4502 sizeof(xstats_names[count].name)); 4503 count++; 4504 } 4505 4506 /* Get individiual stats from ice_hw_port struct */ 4507 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) { 4508 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name, 4509 sizeof(xstats_names[count].name)); 4510 count++; 4511 } 4512 4513 return count; 4514 } 4515 4516 static int 4517 ice_dev_filter_ctrl(struct rte_eth_dev *dev, 4518 enum rte_filter_type filter_type, 4519 enum rte_filter_op filter_op, 4520 void *arg) 4521 { 4522 int ret = 0; 4523 4524 if (!dev) 4525 return -EINVAL; 4526 4527 switch (filter_type) { 4528 case RTE_ETH_FILTER_GENERIC: 4529 if (filter_op != RTE_ETH_FILTER_GET) 4530 return -EINVAL; 4531 *(const void **)arg = &ice_flow_ops; 4532 break; 4533 default: 4534 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 4535 filter_type); 4536 ret = -EINVAL; 4537 break; 4538 } 4539 4540 return ret; 4541 } 4542 4543 /* Add UDP tunneling port */ 4544 static int 4545 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 4546 struct rte_eth_udp_tunnel *udp_tunnel) 4547 { 4548 int ret = 0; 4549 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4550 4551 if (udp_tunnel == NULL) 4552 return -EINVAL; 4553 4554 switch (udp_tunnel->prot_type) { 4555 case RTE_TUNNEL_TYPE_VXLAN: 4556 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port); 4557 break; 4558 default: 4559 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4560 ret = -EINVAL; 4561 break; 4562 } 4563 4564 return ret; 4565 } 4566 4567 /* Delete UDP tunneling port */ 4568 static int 4569 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 4570 struct rte_eth_udp_tunnel *udp_tunnel) 4571 { 4572 int ret = 0; 4573 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4574 4575 if (udp_tunnel == NULL) 4576 return -EINVAL; 4577 4578 switch (udp_tunnel->prot_type) { 4579 case RTE_TUNNEL_TYPE_VXLAN: 4580 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0); 4581 break; 4582 default: 4583 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4584 ret = -EINVAL; 4585 break; 4586 } 4587 4588 return ret; 4589 } 4590 4591 static int 4592 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 4593 struct rte_pci_device *pci_dev) 4594 { 4595 return rte_eth_dev_pci_generic_probe(pci_dev, 4596 sizeof(struct ice_adapter), 4597 ice_dev_init); 4598 } 4599 4600 static int 4601 ice_pci_remove(struct rte_pci_device *pci_dev) 4602 { 4603 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit); 4604 } 4605 4606 static struct rte_pci_driver rte_ice_pmd = { 4607 .id_table = pci_id_ice_map, 4608 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 4609 .probe = ice_pci_probe, 4610 .remove = ice_pci_remove, 4611 }; 4612 4613 /** 4614 * Driver initialization routine. 4615 * Invoked once at EAL init time. 4616 * Register itself as the [Poll Mode] Driver of PCI devices. 4617 */ 4618 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); 4619 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); 4620 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); 4621 RTE_PMD_REGISTER_PARAM_STRING(net_ice, 4622 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>" 4623 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" 4624 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>" 4625 ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>"); 4626 4627 RTE_INIT(ice_init_log) 4628 { 4629 ice_logtype_init = rte_log_register("pmd.net.ice.init"); 4630 if (ice_logtype_init >= 0) 4631 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE); 4632 ice_logtype_driver = rte_log_register("pmd.net.ice.driver"); 4633 if (ice_logtype_driver >= 0) 4634 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE); 4635 4636 #ifdef RTE_LIBRTE_ICE_DEBUG_RX 4637 ice_logtype_rx = rte_log_register("pmd.net.ice.rx"); 4638 if (ice_logtype_rx >= 0) 4639 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG); 4640 #endif 4641 4642 #ifdef RTE_LIBRTE_ICE_DEBUG_TX 4643 ice_logtype_tx = rte_log_register("pmd.net.ice.tx"); 4644 if (ice_logtype_tx >= 0) 4645 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG); 4646 #endif 4647 4648 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE 4649 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free"); 4650 if (ice_logtype_tx_free >= 0) 4651 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG); 4652 #endif 4653 } 4654