1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 13 #include <rte_debug.h> 14 #include <rte_ether.h> 15 #include <rte_ethdev_driver.h> 16 #include <rte_log.h> 17 #include <rte_malloc.h> 18 #include <rte_eth_ctrl.h> 19 #include <rte_tailq.h> 20 #include <rte_flow_driver.h> 21 22 #include "i40e_logs.h" 23 #include "base/i40e_type.h" 24 #include "base/i40e_prototype.h" 25 #include "i40e_ethdev.h" 26 27 #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET) 28 #define I40E_IPV6_FRAG_HEADER 44 29 #define I40E_TENANT_ARRAY_NUM 3 30 #define I40E_TCI_MASK 0xFFFF 31 32 static int i40e_flow_validate(struct rte_eth_dev *dev, 33 const struct rte_flow_attr *attr, 34 const struct rte_flow_item pattern[], 35 const struct rte_flow_action actions[], 36 struct rte_flow_error *error); 37 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev, 38 const struct rte_flow_attr *attr, 39 const struct rte_flow_item pattern[], 40 const struct rte_flow_action actions[], 41 struct rte_flow_error *error); 42 static int i40e_flow_destroy(struct rte_eth_dev *dev, 43 struct rte_flow *flow, 44 struct rte_flow_error *error); 45 static int i40e_flow_flush(struct rte_eth_dev *dev, 46 struct rte_flow_error *error); 47 static int 48 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev, 49 const struct rte_flow_item *pattern, 50 struct rte_flow_error *error, 51 struct rte_eth_ethertype_filter *filter); 52 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev, 53 const struct rte_flow_action *actions, 54 struct rte_flow_error *error, 55 struct rte_eth_ethertype_filter *filter); 56 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev, 57 const struct rte_flow_attr *attr, 58 const struct rte_flow_item *pattern, 59 struct rte_flow_error *error, 60 struct i40e_fdir_filter_conf *filter); 61 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev, 62 const struct rte_flow_action *actions, 63 struct rte_flow_error *error, 64 struct i40e_fdir_filter_conf *filter); 65 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev, 66 const struct rte_flow_action *actions, 67 struct rte_flow_error *error, 68 struct i40e_tunnel_filter_conf *filter); 69 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr, 70 struct rte_flow_error *error); 71 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev, 72 const struct rte_flow_attr *attr, 73 const struct rte_flow_item pattern[], 74 const struct rte_flow_action actions[], 75 struct rte_flow_error *error, 76 union i40e_filter_t *filter); 77 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev, 78 const struct rte_flow_attr *attr, 79 const struct rte_flow_item pattern[], 80 const struct rte_flow_action actions[], 81 struct rte_flow_error *error, 82 union i40e_filter_t *filter); 83 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev, 84 const struct rte_flow_attr *attr, 85 const struct rte_flow_item pattern[], 86 const struct rte_flow_action actions[], 87 struct rte_flow_error *error, 88 union i40e_filter_t *filter); 89 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev, 90 const struct rte_flow_attr *attr, 91 const struct rte_flow_item pattern[], 92 const struct rte_flow_action actions[], 93 struct rte_flow_error *error, 94 union i40e_filter_t *filter); 95 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev, 96 const struct rte_flow_attr *attr, 97 const struct rte_flow_item pattern[], 98 const struct rte_flow_action actions[], 99 struct rte_flow_error *error, 100 union i40e_filter_t *filter); 101 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev, 102 const struct rte_flow_attr *attr, 103 const struct rte_flow_item pattern[], 104 const struct rte_flow_action actions[], 105 struct rte_flow_error *error, 106 union i40e_filter_t *filter); 107 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf, 108 struct i40e_ethertype_filter *filter); 109 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf, 110 struct i40e_tunnel_filter *filter); 111 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf); 112 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf); 113 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf); 114 static int 115 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev); 116 static int 117 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev, 118 const struct rte_flow_attr *attr, 119 const struct rte_flow_item pattern[], 120 const struct rte_flow_action actions[], 121 struct rte_flow_error *error, 122 union i40e_filter_t *filter); 123 static int 124 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev, 125 const struct rte_flow_item *pattern, 126 struct rte_flow_error *error, 127 struct i40e_tunnel_filter_conf *filter); 128 129 const struct rte_flow_ops i40e_flow_ops = { 130 .validate = i40e_flow_validate, 131 .create = i40e_flow_create, 132 .destroy = i40e_flow_destroy, 133 .flush = i40e_flow_flush, 134 }; 135 136 static union i40e_filter_t cons_filter; 137 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE; 138 139 /* Pattern matched ethertype filter */ 140 static enum rte_flow_item_type pattern_ethertype[] = { 141 RTE_FLOW_ITEM_TYPE_ETH, 142 RTE_FLOW_ITEM_TYPE_END, 143 }; 144 145 /* Pattern matched flow director filter */ 146 static enum rte_flow_item_type pattern_fdir_ipv4[] = { 147 RTE_FLOW_ITEM_TYPE_ETH, 148 RTE_FLOW_ITEM_TYPE_IPV4, 149 RTE_FLOW_ITEM_TYPE_END, 150 }; 151 152 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = { 153 RTE_FLOW_ITEM_TYPE_ETH, 154 RTE_FLOW_ITEM_TYPE_IPV4, 155 RTE_FLOW_ITEM_TYPE_UDP, 156 RTE_FLOW_ITEM_TYPE_END, 157 }; 158 159 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = { 160 RTE_FLOW_ITEM_TYPE_ETH, 161 RTE_FLOW_ITEM_TYPE_IPV4, 162 RTE_FLOW_ITEM_TYPE_TCP, 163 RTE_FLOW_ITEM_TYPE_END, 164 }; 165 166 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = { 167 RTE_FLOW_ITEM_TYPE_ETH, 168 RTE_FLOW_ITEM_TYPE_IPV4, 169 RTE_FLOW_ITEM_TYPE_SCTP, 170 RTE_FLOW_ITEM_TYPE_END, 171 }; 172 173 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = { 174 RTE_FLOW_ITEM_TYPE_ETH, 175 RTE_FLOW_ITEM_TYPE_IPV4, 176 RTE_FLOW_ITEM_TYPE_UDP, 177 RTE_FLOW_ITEM_TYPE_GTPC, 178 RTE_FLOW_ITEM_TYPE_END, 179 }; 180 181 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = { 182 RTE_FLOW_ITEM_TYPE_ETH, 183 RTE_FLOW_ITEM_TYPE_IPV4, 184 RTE_FLOW_ITEM_TYPE_UDP, 185 RTE_FLOW_ITEM_TYPE_GTPU, 186 RTE_FLOW_ITEM_TYPE_END, 187 }; 188 189 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = { 190 RTE_FLOW_ITEM_TYPE_ETH, 191 RTE_FLOW_ITEM_TYPE_IPV4, 192 RTE_FLOW_ITEM_TYPE_UDP, 193 RTE_FLOW_ITEM_TYPE_GTPU, 194 RTE_FLOW_ITEM_TYPE_IPV4, 195 RTE_FLOW_ITEM_TYPE_END, 196 }; 197 198 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = { 199 RTE_FLOW_ITEM_TYPE_ETH, 200 RTE_FLOW_ITEM_TYPE_IPV4, 201 RTE_FLOW_ITEM_TYPE_UDP, 202 RTE_FLOW_ITEM_TYPE_GTPU, 203 RTE_FLOW_ITEM_TYPE_IPV6, 204 RTE_FLOW_ITEM_TYPE_END, 205 }; 206 207 static enum rte_flow_item_type pattern_fdir_ipv6[] = { 208 RTE_FLOW_ITEM_TYPE_ETH, 209 RTE_FLOW_ITEM_TYPE_IPV6, 210 RTE_FLOW_ITEM_TYPE_END, 211 }; 212 213 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = { 214 RTE_FLOW_ITEM_TYPE_ETH, 215 RTE_FLOW_ITEM_TYPE_IPV6, 216 RTE_FLOW_ITEM_TYPE_UDP, 217 RTE_FLOW_ITEM_TYPE_END, 218 }; 219 220 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = { 221 RTE_FLOW_ITEM_TYPE_ETH, 222 RTE_FLOW_ITEM_TYPE_IPV6, 223 RTE_FLOW_ITEM_TYPE_TCP, 224 RTE_FLOW_ITEM_TYPE_END, 225 }; 226 227 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = { 228 RTE_FLOW_ITEM_TYPE_ETH, 229 RTE_FLOW_ITEM_TYPE_IPV6, 230 RTE_FLOW_ITEM_TYPE_SCTP, 231 RTE_FLOW_ITEM_TYPE_END, 232 }; 233 234 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = { 235 RTE_FLOW_ITEM_TYPE_ETH, 236 RTE_FLOW_ITEM_TYPE_IPV6, 237 RTE_FLOW_ITEM_TYPE_UDP, 238 RTE_FLOW_ITEM_TYPE_GTPC, 239 RTE_FLOW_ITEM_TYPE_END, 240 }; 241 242 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = { 243 RTE_FLOW_ITEM_TYPE_ETH, 244 RTE_FLOW_ITEM_TYPE_IPV6, 245 RTE_FLOW_ITEM_TYPE_UDP, 246 RTE_FLOW_ITEM_TYPE_GTPU, 247 RTE_FLOW_ITEM_TYPE_END, 248 }; 249 250 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = { 251 RTE_FLOW_ITEM_TYPE_ETH, 252 RTE_FLOW_ITEM_TYPE_IPV6, 253 RTE_FLOW_ITEM_TYPE_UDP, 254 RTE_FLOW_ITEM_TYPE_GTPU, 255 RTE_FLOW_ITEM_TYPE_IPV4, 256 RTE_FLOW_ITEM_TYPE_END, 257 }; 258 259 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = { 260 RTE_FLOW_ITEM_TYPE_ETH, 261 RTE_FLOW_ITEM_TYPE_IPV6, 262 RTE_FLOW_ITEM_TYPE_UDP, 263 RTE_FLOW_ITEM_TYPE_GTPU, 264 RTE_FLOW_ITEM_TYPE_IPV6, 265 RTE_FLOW_ITEM_TYPE_END, 266 }; 267 268 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = { 269 RTE_FLOW_ITEM_TYPE_ETH, 270 RTE_FLOW_ITEM_TYPE_RAW, 271 RTE_FLOW_ITEM_TYPE_END, 272 }; 273 274 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = { 275 RTE_FLOW_ITEM_TYPE_ETH, 276 RTE_FLOW_ITEM_TYPE_RAW, 277 RTE_FLOW_ITEM_TYPE_RAW, 278 RTE_FLOW_ITEM_TYPE_END, 279 }; 280 281 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = { 282 RTE_FLOW_ITEM_TYPE_ETH, 283 RTE_FLOW_ITEM_TYPE_RAW, 284 RTE_FLOW_ITEM_TYPE_RAW, 285 RTE_FLOW_ITEM_TYPE_RAW, 286 RTE_FLOW_ITEM_TYPE_END, 287 }; 288 289 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = { 290 RTE_FLOW_ITEM_TYPE_ETH, 291 RTE_FLOW_ITEM_TYPE_IPV4, 292 RTE_FLOW_ITEM_TYPE_RAW, 293 RTE_FLOW_ITEM_TYPE_END, 294 }; 295 296 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = { 297 RTE_FLOW_ITEM_TYPE_ETH, 298 RTE_FLOW_ITEM_TYPE_IPV4, 299 RTE_FLOW_ITEM_TYPE_RAW, 300 RTE_FLOW_ITEM_TYPE_RAW, 301 RTE_FLOW_ITEM_TYPE_END, 302 }; 303 304 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = { 305 RTE_FLOW_ITEM_TYPE_ETH, 306 RTE_FLOW_ITEM_TYPE_IPV4, 307 RTE_FLOW_ITEM_TYPE_RAW, 308 RTE_FLOW_ITEM_TYPE_RAW, 309 RTE_FLOW_ITEM_TYPE_RAW, 310 RTE_FLOW_ITEM_TYPE_END, 311 }; 312 313 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = { 314 RTE_FLOW_ITEM_TYPE_ETH, 315 RTE_FLOW_ITEM_TYPE_IPV4, 316 RTE_FLOW_ITEM_TYPE_UDP, 317 RTE_FLOW_ITEM_TYPE_RAW, 318 RTE_FLOW_ITEM_TYPE_END, 319 }; 320 321 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = { 322 RTE_FLOW_ITEM_TYPE_ETH, 323 RTE_FLOW_ITEM_TYPE_IPV4, 324 RTE_FLOW_ITEM_TYPE_UDP, 325 RTE_FLOW_ITEM_TYPE_RAW, 326 RTE_FLOW_ITEM_TYPE_RAW, 327 RTE_FLOW_ITEM_TYPE_END, 328 }; 329 330 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = { 331 RTE_FLOW_ITEM_TYPE_ETH, 332 RTE_FLOW_ITEM_TYPE_IPV4, 333 RTE_FLOW_ITEM_TYPE_UDP, 334 RTE_FLOW_ITEM_TYPE_RAW, 335 RTE_FLOW_ITEM_TYPE_RAW, 336 RTE_FLOW_ITEM_TYPE_RAW, 337 RTE_FLOW_ITEM_TYPE_END, 338 }; 339 340 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = { 341 RTE_FLOW_ITEM_TYPE_ETH, 342 RTE_FLOW_ITEM_TYPE_IPV4, 343 RTE_FLOW_ITEM_TYPE_TCP, 344 RTE_FLOW_ITEM_TYPE_RAW, 345 RTE_FLOW_ITEM_TYPE_END, 346 }; 347 348 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = { 349 RTE_FLOW_ITEM_TYPE_ETH, 350 RTE_FLOW_ITEM_TYPE_IPV4, 351 RTE_FLOW_ITEM_TYPE_TCP, 352 RTE_FLOW_ITEM_TYPE_RAW, 353 RTE_FLOW_ITEM_TYPE_RAW, 354 RTE_FLOW_ITEM_TYPE_END, 355 }; 356 357 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = { 358 RTE_FLOW_ITEM_TYPE_ETH, 359 RTE_FLOW_ITEM_TYPE_IPV4, 360 RTE_FLOW_ITEM_TYPE_TCP, 361 RTE_FLOW_ITEM_TYPE_RAW, 362 RTE_FLOW_ITEM_TYPE_RAW, 363 RTE_FLOW_ITEM_TYPE_RAW, 364 RTE_FLOW_ITEM_TYPE_END, 365 }; 366 367 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = { 368 RTE_FLOW_ITEM_TYPE_ETH, 369 RTE_FLOW_ITEM_TYPE_IPV4, 370 RTE_FLOW_ITEM_TYPE_SCTP, 371 RTE_FLOW_ITEM_TYPE_RAW, 372 RTE_FLOW_ITEM_TYPE_END, 373 }; 374 375 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = { 376 RTE_FLOW_ITEM_TYPE_ETH, 377 RTE_FLOW_ITEM_TYPE_IPV4, 378 RTE_FLOW_ITEM_TYPE_SCTP, 379 RTE_FLOW_ITEM_TYPE_RAW, 380 RTE_FLOW_ITEM_TYPE_RAW, 381 RTE_FLOW_ITEM_TYPE_END, 382 }; 383 384 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = { 385 RTE_FLOW_ITEM_TYPE_ETH, 386 RTE_FLOW_ITEM_TYPE_IPV4, 387 RTE_FLOW_ITEM_TYPE_SCTP, 388 RTE_FLOW_ITEM_TYPE_RAW, 389 RTE_FLOW_ITEM_TYPE_RAW, 390 RTE_FLOW_ITEM_TYPE_RAW, 391 RTE_FLOW_ITEM_TYPE_END, 392 }; 393 394 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = { 395 RTE_FLOW_ITEM_TYPE_ETH, 396 RTE_FLOW_ITEM_TYPE_IPV6, 397 RTE_FLOW_ITEM_TYPE_RAW, 398 RTE_FLOW_ITEM_TYPE_END, 399 }; 400 401 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = { 402 RTE_FLOW_ITEM_TYPE_ETH, 403 RTE_FLOW_ITEM_TYPE_IPV6, 404 RTE_FLOW_ITEM_TYPE_RAW, 405 RTE_FLOW_ITEM_TYPE_RAW, 406 RTE_FLOW_ITEM_TYPE_END, 407 }; 408 409 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = { 410 RTE_FLOW_ITEM_TYPE_ETH, 411 RTE_FLOW_ITEM_TYPE_IPV6, 412 RTE_FLOW_ITEM_TYPE_RAW, 413 RTE_FLOW_ITEM_TYPE_RAW, 414 RTE_FLOW_ITEM_TYPE_RAW, 415 RTE_FLOW_ITEM_TYPE_END, 416 }; 417 418 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = { 419 RTE_FLOW_ITEM_TYPE_ETH, 420 RTE_FLOW_ITEM_TYPE_IPV6, 421 RTE_FLOW_ITEM_TYPE_UDP, 422 RTE_FLOW_ITEM_TYPE_RAW, 423 RTE_FLOW_ITEM_TYPE_END, 424 }; 425 426 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = { 427 RTE_FLOW_ITEM_TYPE_ETH, 428 RTE_FLOW_ITEM_TYPE_IPV6, 429 RTE_FLOW_ITEM_TYPE_UDP, 430 RTE_FLOW_ITEM_TYPE_RAW, 431 RTE_FLOW_ITEM_TYPE_RAW, 432 RTE_FLOW_ITEM_TYPE_END, 433 }; 434 435 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = { 436 RTE_FLOW_ITEM_TYPE_ETH, 437 RTE_FLOW_ITEM_TYPE_IPV6, 438 RTE_FLOW_ITEM_TYPE_UDP, 439 RTE_FLOW_ITEM_TYPE_RAW, 440 RTE_FLOW_ITEM_TYPE_RAW, 441 RTE_FLOW_ITEM_TYPE_RAW, 442 RTE_FLOW_ITEM_TYPE_END, 443 }; 444 445 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = { 446 RTE_FLOW_ITEM_TYPE_ETH, 447 RTE_FLOW_ITEM_TYPE_IPV6, 448 RTE_FLOW_ITEM_TYPE_TCP, 449 RTE_FLOW_ITEM_TYPE_RAW, 450 RTE_FLOW_ITEM_TYPE_END, 451 }; 452 453 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = { 454 RTE_FLOW_ITEM_TYPE_ETH, 455 RTE_FLOW_ITEM_TYPE_IPV6, 456 RTE_FLOW_ITEM_TYPE_TCP, 457 RTE_FLOW_ITEM_TYPE_RAW, 458 RTE_FLOW_ITEM_TYPE_RAW, 459 RTE_FLOW_ITEM_TYPE_END, 460 }; 461 462 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = { 463 RTE_FLOW_ITEM_TYPE_ETH, 464 RTE_FLOW_ITEM_TYPE_IPV6, 465 RTE_FLOW_ITEM_TYPE_TCP, 466 RTE_FLOW_ITEM_TYPE_RAW, 467 RTE_FLOW_ITEM_TYPE_RAW, 468 RTE_FLOW_ITEM_TYPE_RAW, 469 RTE_FLOW_ITEM_TYPE_END, 470 }; 471 472 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = { 473 RTE_FLOW_ITEM_TYPE_ETH, 474 RTE_FLOW_ITEM_TYPE_IPV6, 475 RTE_FLOW_ITEM_TYPE_SCTP, 476 RTE_FLOW_ITEM_TYPE_RAW, 477 RTE_FLOW_ITEM_TYPE_END, 478 }; 479 480 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = { 481 RTE_FLOW_ITEM_TYPE_ETH, 482 RTE_FLOW_ITEM_TYPE_IPV6, 483 RTE_FLOW_ITEM_TYPE_SCTP, 484 RTE_FLOW_ITEM_TYPE_RAW, 485 RTE_FLOW_ITEM_TYPE_RAW, 486 RTE_FLOW_ITEM_TYPE_END, 487 }; 488 489 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = { 490 RTE_FLOW_ITEM_TYPE_ETH, 491 RTE_FLOW_ITEM_TYPE_IPV6, 492 RTE_FLOW_ITEM_TYPE_SCTP, 493 RTE_FLOW_ITEM_TYPE_RAW, 494 RTE_FLOW_ITEM_TYPE_RAW, 495 RTE_FLOW_ITEM_TYPE_RAW, 496 RTE_FLOW_ITEM_TYPE_END, 497 }; 498 499 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = { 500 RTE_FLOW_ITEM_TYPE_ETH, 501 RTE_FLOW_ITEM_TYPE_VLAN, 502 RTE_FLOW_ITEM_TYPE_END, 503 }; 504 505 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = { 506 RTE_FLOW_ITEM_TYPE_ETH, 507 RTE_FLOW_ITEM_TYPE_VLAN, 508 RTE_FLOW_ITEM_TYPE_IPV4, 509 RTE_FLOW_ITEM_TYPE_END, 510 }; 511 512 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = { 513 RTE_FLOW_ITEM_TYPE_ETH, 514 RTE_FLOW_ITEM_TYPE_VLAN, 515 RTE_FLOW_ITEM_TYPE_IPV4, 516 RTE_FLOW_ITEM_TYPE_UDP, 517 RTE_FLOW_ITEM_TYPE_END, 518 }; 519 520 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = { 521 RTE_FLOW_ITEM_TYPE_ETH, 522 RTE_FLOW_ITEM_TYPE_VLAN, 523 RTE_FLOW_ITEM_TYPE_IPV4, 524 RTE_FLOW_ITEM_TYPE_TCP, 525 RTE_FLOW_ITEM_TYPE_END, 526 }; 527 528 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = { 529 RTE_FLOW_ITEM_TYPE_ETH, 530 RTE_FLOW_ITEM_TYPE_VLAN, 531 RTE_FLOW_ITEM_TYPE_IPV4, 532 RTE_FLOW_ITEM_TYPE_SCTP, 533 RTE_FLOW_ITEM_TYPE_END, 534 }; 535 536 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = { 537 RTE_FLOW_ITEM_TYPE_ETH, 538 RTE_FLOW_ITEM_TYPE_VLAN, 539 RTE_FLOW_ITEM_TYPE_IPV6, 540 RTE_FLOW_ITEM_TYPE_END, 541 }; 542 543 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = { 544 RTE_FLOW_ITEM_TYPE_ETH, 545 RTE_FLOW_ITEM_TYPE_VLAN, 546 RTE_FLOW_ITEM_TYPE_IPV6, 547 RTE_FLOW_ITEM_TYPE_UDP, 548 RTE_FLOW_ITEM_TYPE_END, 549 }; 550 551 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = { 552 RTE_FLOW_ITEM_TYPE_ETH, 553 RTE_FLOW_ITEM_TYPE_VLAN, 554 RTE_FLOW_ITEM_TYPE_IPV6, 555 RTE_FLOW_ITEM_TYPE_TCP, 556 RTE_FLOW_ITEM_TYPE_END, 557 }; 558 559 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = { 560 RTE_FLOW_ITEM_TYPE_ETH, 561 RTE_FLOW_ITEM_TYPE_VLAN, 562 RTE_FLOW_ITEM_TYPE_IPV6, 563 RTE_FLOW_ITEM_TYPE_SCTP, 564 RTE_FLOW_ITEM_TYPE_END, 565 }; 566 567 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = { 568 RTE_FLOW_ITEM_TYPE_ETH, 569 RTE_FLOW_ITEM_TYPE_VLAN, 570 RTE_FLOW_ITEM_TYPE_RAW, 571 RTE_FLOW_ITEM_TYPE_END, 572 }; 573 574 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = { 575 RTE_FLOW_ITEM_TYPE_ETH, 576 RTE_FLOW_ITEM_TYPE_VLAN, 577 RTE_FLOW_ITEM_TYPE_RAW, 578 RTE_FLOW_ITEM_TYPE_RAW, 579 RTE_FLOW_ITEM_TYPE_END, 580 }; 581 582 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = { 583 RTE_FLOW_ITEM_TYPE_ETH, 584 RTE_FLOW_ITEM_TYPE_VLAN, 585 RTE_FLOW_ITEM_TYPE_RAW, 586 RTE_FLOW_ITEM_TYPE_RAW, 587 RTE_FLOW_ITEM_TYPE_RAW, 588 RTE_FLOW_ITEM_TYPE_END, 589 }; 590 591 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = { 592 RTE_FLOW_ITEM_TYPE_ETH, 593 RTE_FLOW_ITEM_TYPE_VLAN, 594 RTE_FLOW_ITEM_TYPE_IPV4, 595 RTE_FLOW_ITEM_TYPE_RAW, 596 RTE_FLOW_ITEM_TYPE_END, 597 }; 598 599 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = { 600 RTE_FLOW_ITEM_TYPE_ETH, 601 RTE_FLOW_ITEM_TYPE_VLAN, 602 RTE_FLOW_ITEM_TYPE_IPV4, 603 RTE_FLOW_ITEM_TYPE_RAW, 604 RTE_FLOW_ITEM_TYPE_RAW, 605 RTE_FLOW_ITEM_TYPE_END, 606 }; 607 608 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = { 609 RTE_FLOW_ITEM_TYPE_ETH, 610 RTE_FLOW_ITEM_TYPE_VLAN, 611 RTE_FLOW_ITEM_TYPE_IPV4, 612 RTE_FLOW_ITEM_TYPE_RAW, 613 RTE_FLOW_ITEM_TYPE_RAW, 614 RTE_FLOW_ITEM_TYPE_RAW, 615 RTE_FLOW_ITEM_TYPE_END, 616 }; 617 618 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = { 619 RTE_FLOW_ITEM_TYPE_ETH, 620 RTE_FLOW_ITEM_TYPE_VLAN, 621 RTE_FLOW_ITEM_TYPE_IPV4, 622 RTE_FLOW_ITEM_TYPE_UDP, 623 RTE_FLOW_ITEM_TYPE_RAW, 624 RTE_FLOW_ITEM_TYPE_END, 625 }; 626 627 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = { 628 RTE_FLOW_ITEM_TYPE_ETH, 629 RTE_FLOW_ITEM_TYPE_VLAN, 630 RTE_FLOW_ITEM_TYPE_IPV4, 631 RTE_FLOW_ITEM_TYPE_UDP, 632 RTE_FLOW_ITEM_TYPE_RAW, 633 RTE_FLOW_ITEM_TYPE_RAW, 634 RTE_FLOW_ITEM_TYPE_END, 635 }; 636 637 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = { 638 RTE_FLOW_ITEM_TYPE_ETH, 639 RTE_FLOW_ITEM_TYPE_VLAN, 640 RTE_FLOW_ITEM_TYPE_IPV4, 641 RTE_FLOW_ITEM_TYPE_UDP, 642 RTE_FLOW_ITEM_TYPE_RAW, 643 RTE_FLOW_ITEM_TYPE_RAW, 644 RTE_FLOW_ITEM_TYPE_RAW, 645 RTE_FLOW_ITEM_TYPE_END, 646 }; 647 648 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = { 649 RTE_FLOW_ITEM_TYPE_ETH, 650 RTE_FLOW_ITEM_TYPE_VLAN, 651 RTE_FLOW_ITEM_TYPE_IPV4, 652 RTE_FLOW_ITEM_TYPE_TCP, 653 RTE_FLOW_ITEM_TYPE_RAW, 654 RTE_FLOW_ITEM_TYPE_END, 655 }; 656 657 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = { 658 RTE_FLOW_ITEM_TYPE_ETH, 659 RTE_FLOW_ITEM_TYPE_VLAN, 660 RTE_FLOW_ITEM_TYPE_IPV4, 661 RTE_FLOW_ITEM_TYPE_TCP, 662 RTE_FLOW_ITEM_TYPE_RAW, 663 RTE_FLOW_ITEM_TYPE_RAW, 664 RTE_FLOW_ITEM_TYPE_END, 665 }; 666 667 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = { 668 RTE_FLOW_ITEM_TYPE_ETH, 669 RTE_FLOW_ITEM_TYPE_VLAN, 670 RTE_FLOW_ITEM_TYPE_IPV4, 671 RTE_FLOW_ITEM_TYPE_TCP, 672 RTE_FLOW_ITEM_TYPE_RAW, 673 RTE_FLOW_ITEM_TYPE_RAW, 674 RTE_FLOW_ITEM_TYPE_RAW, 675 RTE_FLOW_ITEM_TYPE_END, 676 }; 677 678 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = { 679 RTE_FLOW_ITEM_TYPE_ETH, 680 RTE_FLOW_ITEM_TYPE_VLAN, 681 RTE_FLOW_ITEM_TYPE_IPV4, 682 RTE_FLOW_ITEM_TYPE_SCTP, 683 RTE_FLOW_ITEM_TYPE_RAW, 684 RTE_FLOW_ITEM_TYPE_END, 685 }; 686 687 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = { 688 RTE_FLOW_ITEM_TYPE_ETH, 689 RTE_FLOW_ITEM_TYPE_VLAN, 690 RTE_FLOW_ITEM_TYPE_IPV4, 691 RTE_FLOW_ITEM_TYPE_SCTP, 692 RTE_FLOW_ITEM_TYPE_RAW, 693 RTE_FLOW_ITEM_TYPE_RAW, 694 RTE_FLOW_ITEM_TYPE_END, 695 }; 696 697 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = { 698 RTE_FLOW_ITEM_TYPE_ETH, 699 RTE_FLOW_ITEM_TYPE_VLAN, 700 RTE_FLOW_ITEM_TYPE_IPV4, 701 RTE_FLOW_ITEM_TYPE_SCTP, 702 RTE_FLOW_ITEM_TYPE_RAW, 703 RTE_FLOW_ITEM_TYPE_RAW, 704 RTE_FLOW_ITEM_TYPE_RAW, 705 RTE_FLOW_ITEM_TYPE_END, 706 }; 707 708 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = { 709 RTE_FLOW_ITEM_TYPE_ETH, 710 RTE_FLOW_ITEM_TYPE_VLAN, 711 RTE_FLOW_ITEM_TYPE_IPV6, 712 RTE_FLOW_ITEM_TYPE_RAW, 713 RTE_FLOW_ITEM_TYPE_END, 714 }; 715 716 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = { 717 RTE_FLOW_ITEM_TYPE_ETH, 718 RTE_FLOW_ITEM_TYPE_VLAN, 719 RTE_FLOW_ITEM_TYPE_IPV6, 720 RTE_FLOW_ITEM_TYPE_RAW, 721 RTE_FLOW_ITEM_TYPE_RAW, 722 RTE_FLOW_ITEM_TYPE_END, 723 }; 724 725 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = { 726 RTE_FLOW_ITEM_TYPE_ETH, 727 RTE_FLOW_ITEM_TYPE_VLAN, 728 RTE_FLOW_ITEM_TYPE_IPV6, 729 RTE_FLOW_ITEM_TYPE_RAW, 730 RTE_FLOW_ITEM_TYPE_RAW, 731 RTE_FLOW_ITEM_TYPE_RAW, 732 RTE_FLOW_ITEM_TYPE_END, 733 }; 734 735 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = { 736 RTE_FLOW_ITEM_TYPE_ETH, 737 RTE_FLOW_ITEM_TYPE_VLAN, 738 RTE_FLOW_ITEM_TYPE_IPV6, 739 RTE_FLOW_ITEM_TYPE_UDP, 740 RTE_FLOW_ITEM_TYPE_RAW, 741 RTE_FLOW_ITEM_TYPE_END, 742 }; 743 744 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = { 745 RTE_FLOW_ITEM_TYPE_ETH, 746 RTE_FLOW_ITEM_TYPE_VLAN, 747 RTE_FLOW_ITEM_TYPE_IPV6, 748 RTE_FLOW_ITEM_TYPE_UDP, 749 RTE_FLOW_ITEM_TYPE_RAW, 750 RTE_FLOW_ITEM_TYPE_RAW, 751 RTE_FLOW_ITEM_TYPE_END, 752 }; 753 754 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = { 755 RTE_FLOW_ITEM_TYPE_ETH, 756 RTE_FLOW_ITEM_TYPE_VLAN, 757 RTE_FLOW_ITEM_TYPE_IPV6, 758 RTE_FLOW_ITEM_TYPE_UDP, 759 RTE_FLOW_ITEM_TYPE_RAW, 760 RTE_FLOW_ITEM_TYPE_RAW, 761 RTE_FLOW_ITEM_TYPE_RAW, 762 RTE_FLOW_ITEM_TYPE_END, 763 }; 764 765 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = { 766 RTE_FLOW_ITEM_TYPE_ETH, 767 RTE_FLOW_ITEM_TYPE_VLAN, 768 RTE_FLOW_ITEM_TYPE_IPV6, 769 RTE_FLOW_ITEM_TYPE_TCP, 770 RTE_FLOW_ITEM_TYPE_RAW, 771 RTE_FLOW_ITEM_TYPE_END, 772 }; 773 774 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = { 775 RTE_FLOW_ITEM_TYPE_ETH, 776 RTE_FLOW_ITEM_TYPE_VLAN, 777 RTE_FLOW_ITEM_TYPE_IPV6, 778 RTE_FLOW_ITEM_TYPE_TCP, 779 RTE_FLOW_ITEM_TYPE_RAW, 780 RTE_FLOW_ITEM_TYPE_RAW, 781 RTE_FLOW_ITEM_TYPE_END, 782 }; 783 784 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = { 785 RTE_FLOW_ITEM_TYPE_ETH, 786 RTE_FLOW_ITEM_TYPE_VLAN, 787 RTE_FLOW_ITEM_TYPE_IPV6, 788 RTE_FLOW_ITEM_TYPE_TCP, 789 RTE_FLOW_ITEM_TYPE_RAW, 790 RTE_FLOW_ITEM_TYPE_RAW, 791 RTE_FLOW_ITEM_TYPE_RAW, 792 RTE_FLOW_ITEM_TYPE_END, 793 }; 794 795 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = { 796 RTE_FLOW_ITEM_TYPE_ETH, 797 RTE_FLOW_ITEM_TYPE_VLAN, 798 RTE_FLOW_ITEM_TYPE_IPV6, 799 RTE_FLOW_ITEM_TYPE_SCTP, 800 RTE_FLOW_ITEM_TYPE_RAW, 801 RTE_FLOW_ITEM_TYPE_END, 802 }; 803 804 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = { 805 RTE_FLOW_ITEM_TYPE_ETH, 806 RTE_FLOW_ITEM_TYPE_VLAN, 807 RTE_FLOW_ITEM_TYPE_IPV6, 808 RTE_FLOW_ITEM_TYPE_SCTP, 809 RTE_FLOW_ITEM_TYPE_RAW, 810 RTE_FLOW_ITEM_TYPE_RAW, 811 RTE_FLOW_ITEM_TYPE_END, 812 }; 813 814 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = { 815 RTE_FLOW_ITEM_TYPE_ETH, 816 RTE_FLOW_ITEM_TYPE_VLAN, 817 RTE_FLOW_ITEM_TYPE_IPV6, 818 RTE_FLOW_ITEM_TYPE_SCTP, 819 RTE_FLOW_ITEM_TYPE_RAW, 820 RTE_FLOW_ITEM_TYPE_RAW, 821 RTE_FLOW_ITEM_TYPE_RAW, 822 RTE_FLOW_ITEM_TYPE_END, 823 }; 824 825 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = { 826 RTE_FLOW_ITEM_TYPE_ETH, 827 RTE_FLOW_ITEM_TYPE_IPV4, 828 RTE_FLOW_ITEM_TYPE_VF, 829 RTE_FLOW_ITEM_TYPE_END, 830 }; 831 832 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = { 833 RTE_FLOW_ITEM_TYPE_ETH, 834 RTE_FLOW_ITEM_TYPE_IPV4, 835 RTE_FLOW_ITEM_TYPE_UDP, 836 RTE_FLOW_ITEM_TYPE_VF, 837 RTE_FLOW_ITEM_TYPE_END, 838 }; 839 840 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = { 841 RTE_FLOW_ITEM_TYPE_ETH, 842 RTE_FLOW_ITEM_TYPE_IPV4, 843 RTE_FLOW_ITEM_TYPE_TCP, 844 RTE_FLOW_ITEM_TYPE_VF, 845 RTE_FLOW_ITEM_TYPE_END, 846 }; 847 848 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = { 849 RTE_FLOW_ITEM_TYPE_ETH, 850 RTE_FLOW_ITEM_TYPE_IPV4, 851 RTE_FLOW_ITEM_TYPE_SCTP, 852 RTE_FLOW_ITEM_TYPE_VF, 853 RTE_FLOW_ITEM_TYPE_END, 854 }; 855 856 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = { 857 RTE_FLOW_ITEM_TYPE_ETH, 858 RTE_FLOW_ITEM_TYPE_IPV6, 859 RTE_FLOW_ITEM_TYPE_VF, 860 RTE_FLOW_ITEM_TYPE_END, 861 }; 862 863 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = { 864 RTE_FLOW_ITEM_TYPE_ETH, 865 RTE_FLOW_ITEM_TYPE_IPV6, 866 RTE_FLOW_ITEM_TYPE_UDP, 867 RTE_FLOW_ITEM_TYPE_VF, 868 RTE_FLOW_ITEM_TYPE_END, 869 }; 870 871 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = { 872 RTE_FLOW_ITEM_TYPE_ETH, 873 RTE_FLOW_ITEM_TYPE_IPV6, 874 RTE_FLOW_ITEM_TYPE_TCP, 875 RTE_FLOW_ITEM_TYPE_VF, 876 RTE_FLOW_ITEM_TYPE_END, 877 }; 878 879 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = { 880 RTE_FLOW_ITEM_TYPE_ETH, 881 RTE_FLOW_ITEM_TYPE_IPV6, 882 RTE_FLOW_ITEM_TYPE_SCTP, 883 RTE_FLOW_ITEM_TYPE_VF, 884 RTE_FLOW_ITEM_TYPE_END, 885 }; 886 887 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = { 888 RTE_FLOW_ITEM_TYPE_ETH, 889 RTE_FLOW_ITEM_TYPE_RAW, 890 RTE_FLOW_ITEM_TYPE_VF, 891 RTE_FLOW_ITEM_TYPE_END, 892 }; 893 894 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = { 895 RTE_FLOW_ITEM_TYPE_ETH, 896 RTE_FLOW_ITEM_TYPE_RAW, 897 RTE_FLOW_ITEM_TYPE_RAW, 898 RTE_FLOW_ITEM_TYPE_VF, 899 RTE_FLOW_ITEM_TYPE_END, 900 }; 901 902 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = { 903 RTE_FLOW_ITEM_TYPE_ETH, 904 RTE_FLOW_ITEM_TYPE_RAW, 905 RTE_FLOW_ITEM_TYPE_RAW, 906 RTE_FLOW_ITEM_TYPE_RAW, 907 RTE_FLOW_ITEM_TYPE_VF, 908 RTE_FLOW_ITEM_TYPE_END, 909 }; 910 911 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = { 912 RTE_FLOW_ITEM_TYPE_ETH, 913 RTE_FLOW_ITEM_TYPE_IPV4, 914 RTE_FLOW_ITEM_TYPE_RAW, 915 RTE_FLOW_ITEM_TYPE_VF, 916 RTE_FLOW_ITEM_TYPE_END, 917 }; 918 919 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = { 920 RTE_FLOW_ITEM_TYPE_ETH, 921 RTE_FLOW_ITEM_TYPE_IPV4, 922 RTE_FLOW_ITEM_TYPE_RAW, 923 RTE_FLOW_ITEM_TYPE_RAW, 924 RTE_FLOW_ITEM_TYPE_VF, 925 RTE_FLOW_ITEM_TYPE_END, 926 }; 927 928 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = { 929 RTE_FLOW_ITEM_TYPE_ETH, 930 RTE_FLOW_ITEM_TYPE_IPV4, 931 RTE_FLOW_ITEM_TYPE_RAW, 932 RTE_FLOW_ITEM_TYPE_RAW, 933 RTE_FLOW_ITEM_TYPE_RAW, 934 RTE_FLOW_ITEM_TYPE_VF, 935 RTE_FLOW_ITEM_TYPE_END, 936 }; 937 938 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = { 939 RTE_FLOW_ITEM_TYPE_ETH, 940 RTE_FLOW_ITEM_TYPE_IPV4, 941 RTE_FLOW_ITEM_TYPE_UDP, 942 RTE_FLOW_ITEM_TYPE_RAW, 943 RTE_FLOW_ITEM_TYPE_VF, 944 RTE_FLOW_ITEM_TYPE_END, 945 }; 946 947 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = { 948 RTE_FLOW_ITEM_TYPE_ETH, 949 RTE_FLOW_ITEM_TYPE_IPV4, 950 RTE_FLOW_ITEM_TYPE_UDP, 951 RTE_FLOW_ITEM_TYPE_RAW, 952 RTE_FLOW_ITEM_TYPE_RAW, 953 RTE_FLOW_ITEM_TYPE_VF, 954 RTE_FLOW_ITEM_TYPE_END, 955 }; 956 957 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = { 958 RTE_FLOW_ITEM_TYPE_ETH, 959 RTE_FLOW_ITEM_TYPE_IPV4, 960 RTE_FLOW_ITEM_TYPE_UDP, 961 RTE_FLOW_ITEM_TYPE_RAW, 962 RTE_FLOW_ITEM_TYPE_RAW, 963 RTE_FLOW_ITEM_TYPE_RAW, 964 RTE_FLOW_ITEM_TYPE_VF, 965 RTE_FLOW_ITEM_TYPE_END, 966 }; 967 968 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = { 969 RTE_FLOW_ITEM_TYPE_ETH, 970 RTE_FLOW_ITEM_TYPE_IPV4, 971 RTE_FLOW_ITEM_TYPE_TCP, 972 RTE_FLOW_ITEM_TYPE_RAW, 973 RTE_FLOW_ITEM_TYPE_VF, 974 RTE_FLOW_ITEM_TYPE_END, 975 }; 976 977 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = { 978 RTE_FLOW_ITEM_TYPE_ETH, 979 RTE_FLOW_ITEM_TYPE_IPV4, 980 RTE_FLOW_ITEM_TYPE_TCP, 981 RTE_FLOW_ITEM_TYPE_RAW, 982 RTE_FLOW_ITEM_TYPE_RAW, 983 RTE_FLOW_ITEM_TYPE_VF, 984 RTE_FLOW_ITEM_TYPE_END, 985 }; 986 987 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = { 988 RTE_FLOW_ITEM_TYPE_ETH, 989 RTE_FLOW_ITEM_TYPE_IPV4, 990 RTE_FLOW_ITEM_TYPE_TCP, 991 RTE_FLOW_ITEM_TYPE_RAW, 992 RTE_FLOW_ITEM_TYPE_RAW, 993 RTE_FLOW_ITEM_TYPE_RAW, 994 RTE_FLOW_ITEM_TYPE_VF, 995 RTE_FLOW_ITEM_TYPE_END, 996 }; 997 998 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = { 999 RTE_FLOW_ITEM_TYPE_ETH, 1000 RTE_FLOW_ITEM_TYPE_IPV4, 1001 RTE_FLOW_ITEM_TYPE_SCTP, 1002 RTE_FLOW_ITEM_TYPE_RAW, 1003 RTE_FLOW_ITEM_TYPE_VF, 1004 RTE_FLOW_ITEM_TYPE_END, 1005 }; 1006 1007 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = { 1008 RTE_FLOW_ITEM_TYPE_ETH, 1009 RTE_FLOW_ITEM_TYPE_IPV4, 1010 RTE_FLOW_ITEM_TYPE_SCTP, 1011 RTE_FLOW_ITEM_TYPE_RAW, 1012 RTE_FLOW_ITEM_TYPE_RAW, 1013 RTE_FLOW_ITEM_TYPE_VF, 1014 RTE_FLOW_ITEM_TYPE_END, 1015 }; 1016 1017 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = { 1018 RTE_FLOW_ITEM_TYPE_ETH, 1019 RTE_FLOW_ITEM_TYPE_IPV4, 1020 RTE_FLOW_ITEM_TYPE_SCTP, 1021 RTE_FLOW_ITEM_TYPE_RAW, 1022 RTE_FLOW_ITEM_TYPE_RAW, 1023 RTE_FLOW_ITEM_TYPE_RAW, 1024 RTE_FLOW_ITEM_TYPE_VF, 1025 RTE_FLOW_ITEM_TYPE_END, 1026 }; 1027 1028 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = { 1029 RTE_FLOW_ITEM_TYPE_ETH, 1030 RTE_FLOW_ITEM_TYPE_IPV6, 1031 RTE_FLOW_ITEM_TYPE_RAW, 1032 RTE_FLOW_ITEM_TYPE_VF, 1033 RTE_FLOW_ITEM_TYPE_END, 1034 }; 1035 1036 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = { 1037 RTE_FLOW_ITEM_TYPE_ETH, 1038 RTE_FLOW_ITEM_TYPE_IPV6, 1039 RTE_FLOW_ITEM_TYPE_RAW, 1040 RTE_FLOW_ITEM_TYPE_RAW, 1041 RTE_FLOW_ITEM_TYPE_VF, 1042 RTE_FLOW_ITEM_TYPE_END, 1043 }; 1044 1045 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = { 1046 RTE_FLOW_ITEM_TYPE_ETH, 1047 RTE_FLOW_ITEM_TYPE_IPV6, 1048 RTE_FLOW_ITEM_TYPE_RAW, 1049 RTE_FLOW_ITEM_TYPE_RAW, 1050 RTE_FLOW_ITEM_TYPE_RAW, 1051 RTE_FLOW_ITEM_TYPE_VF, 1052 RTE_FLOW_ITEM_TYPE_END, 1053 }; 1054 1055 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = { 1056 RTE_FLOW_ITEM_TYPE_ETH, 1057 RTE_FLOW_ITEM_TYPE_IPV6, 1058 RTE_FLOW_ITEM_TYPE_UDP, 1059 RTE_FLOW_ITEM_TYPE_RAW, 1060 RTE_FLOW_ITEM_TYPE_VF, 1061 RTE_FLOW_ITEM_TYPE_END, 1062 }; 1063 1064 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = { 1065 RTE_FLOW_ITEM_TYPE_ETH, 1066 RTE_FLOW_ITEM_TYPE_IPV6, 1067 RTE_FLOW_ITEM_TYPE_UDP, 1068 RTE_FLOW_ITEM_TYPE_RAW, 1069 RTE_FLOW_ITEM_TYPE_RAW, 1070 RTE_FLOW_ITEM_TYPE_VF, 1071 RTE_FLOW_ITEM_TYPE_END, 1072 }; 1073 1074 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = { 1075 RTE_FLOW_ITEM_TYPE_ETH, 1076 RTE_FLOW_ITEM_TYPE_IPV6, 1077 RTE_FLOW_ITEM_TYPE_UDP, 1078 RTE_FLOW_ITEM_TYPE_RAW, 1079 RTE_FLOW_ITEM_TYPE_RAW, 1080 RTE_FLOW_ITEM_TYPE_RAW, 1081 RTE_FLOW_ITEM_TYPE_VF, 1082 RTE_FLOW_ITEM_TYPE_END, 1083 }; 1084 1085 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = { 1086 RTE_FLOW_ITEM_TYPE_ETH, 1087 RTE_FLOW_ITEM_TYPE_IPV6, 1088 RTE_FLOW_ITEM_TYPE_TCP, 1089 RTE_FLOW_ITEM_TYPE_RAW, 1090 RTE_FLOW_ITEM_TYPE_VF, 1091 RTE_FLOW_ITEM_TYPE_END, 1092 }; 1093 1094 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = { 1095 RTE_FLOW_ITEM_TYPE_ETH, 1096 RTE_FLOW_ITEM_TYPE_IPV6, 1097 RTE_FLOW_ITEM_TYPE_TCP, 1098 RTE_FLOW_ITEM_TYPE_RAW, 1099 RTE_FLOW_ITEM_TYPE_RAW, 1100 RTE_FLOW_ITEM_TYPE_VF, 1101 RTE_FLOW_ITEM_TYPE_END, 1102 }; 1103 1104 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = { 1105 RTE_FLOW_ITEM_TYPE_ETH, 1106 RTE_FLOW_ITEM_TYPE_IPV6, 1107 RTE_FLOW_ITEM_TYPE_TCP, 1108 RTE_FLOW_ITEM_TYPE_RAW, 1109 RTE_FLOW_ITEM_TYPE_RAW, 1110 RTE_FLOW_ITEM_TYPE_RAW, 1111 RTE_FLOW_ITEM_TYPE_VF, 1112 RTE_FLOW_ITEM_TYPE_END, 1113 }; 1114 1115 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = { 1116 RTE_FLOW_ITEM_TYPE_ETH, 1117 RTE_FLOW_ITEM_TYPE_IPV6, 1118 RTE_FLOW_ITEM_TYPE_SCTP, 1119 RTE_FLOW_ITEM_TYPE_RAW, 1120 RTE_FLOW_ITEM_TYPE_VF, 1121 RTE_FLOW_ITEM_TYPE_END, 1122 }; 1123 1124 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = { 1125 RTE_FLOW_ITEM_TYPE_ETH, 1126 RTE_FLOW_ITEM_TYPE_IPV6, 1127 RTE_FLOW_ITEM_TYPE_SCTP, 1128 RTE_FLOW_ITEM_TYPE_RAW, 1129 RTE_FLOW_ITEM_TYPE_RAW, 1130 RTE_FLOW_ITEM_TYPE_VF, 1131 RTE_FLOW_ITEM_TYPE_END, 1132 }; 1133 1134 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = { 1135 RTE_FLOW_ITEM_TYPE_ETH, 1136 RTE_FLOW_ITEM_TYPE_IPV6, 1137 RTE_FLOW_ITEM_TYPE_SCTP, 1138 RTE_FLOW_ITEM_TYPE_RAW, 1139 RTE_FLOW_ITEM_TYPE_RAW, 1140 RTE_FLOW_ITEM_TYPE_RAW, 1141 RTE_FLOW_ITEM_TYPE_VF, 1142 RTE_FLOW_ITEM_TYPE_END, 1143 }; 1144 1145 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = { 1146 RTE_FLOW_ITEM_TYPE_ETH, 1147 RTE_FLOW_ITEM_TYPE_VLAN, 1148 RTE_FLOW_ITEM_TYPE_VF, 1149 RTE_FLOW_ITEM_TYPE_END, 1150 }; 1151 1152 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = { 1153 RTE_FLOW_ITEM_TYPE_ETH, 1154 RTE_FLOW_ITEM_TYPE_VLAN, 1155 RTE_FLOW_ITEM_TYPE_IPV4, 1156 RTE_FLOW_ITEM_TYPE_VF, 1157 RTE_FLOW_ITEM_TYPE_END, 1158 }; 1159 1160 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = { 1161 RTE_FLOW_ITEM_TYPE_ETH, 1162 RTE_FLOW_ITEM_TYPE_VLAN, 1163 RTE_FLOW_ITEM_TYPE_IPV4, 1164 RTE_FLOW_ITEM_TYPE_UDP, 1165 RTE_FLOW_ITEM_TYPE_VF, 1166 RTE_FLOW_ITEM_TYPE_END, 1167 }; 1168 1169 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = { 1170 RTE_FLOW_ITEM_TYPE_ETH, 1171 RTE_FLOW_ITEM_TYPE_VLAN, 1172 RTE_FLOW_ITEM_TYPE_IPV4, 1173 RTE_FLOW_ITEM_TYPE_TCP, 1174 RTE_FLOW_ITEM_TYPE_VF, 1175 RTE_FLOW_ITEM_TYPE_END, 1176 }; 1177 1178 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = { 1179 RTE_FLOW_ITEM_TYPE_ETH, 1180 RTE_FLOW_ITEM_TYPE_VLAN, 1181 RTE_FLOW_ITEM_TYPE_IPV4, 1182 RTE_FLOW_ITEM_TYPE_SCTP, 1183 RTE_FLOW_ITEM_TYPE_VF, 1184 RTE_FLOW_ITEM_TYPE_END, 1185 }; 1186 1187 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = { 1188 RTE_FLOW_ITEM_TYPE_ETH, 1189 RTE_FLOW_ITEM_TYPE_VLAN, 1190 RTE_FLOW_ITEM_TYPE_IPV6, 1191 RTE_FLOW_ITEM_TYPE_VF, 1192 RTE_FLOW_ITEM_TYPE_END, 1193 }; 1194 1195 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = { 1196 RTE_FLOW_ITEM_TYPE_ETH, 1197 RTE_FLOW_ITEM_TYPE_VLAN, 1198 RTE_FLOW_ITEM_TYPE_IPV6, 1199 RTE_FLOW_ITEM_TYPE_UDP, 1200 RTE_FLOW_ITEM_TYPE_VF, 1201 RTE_FLOW_ITEM_TYPE_END, 1202 }; 1203 1204 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = { 1205 RTE_FLOW_ITEM_TYPE_ETH, 1206 RTE_FLOW_ITEM_TYPE_VLAN, 1207 RTE_FLOW_ITEM_TYPE_IPV6, 1208 RTE_FLOW_ITEM_TYPE_TCP, 1209 RTE_FLOW_ITEM_TYPE_VF, 1210 RTE_FLOW_ITEM_TYPE_END, 1211 }; 1212 1213 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = { 1214 RTE_FLOW_ITEM_TYPE_ETH, 1215 RTE_FLOW_ITEM_TYPE_VLAN, 1216 RTE_FLOW_ITEM_TYPE_IPV6, 1217 RTE_FLOW_ITEM_TYPE_SCTP, 1218 RTE_FLOW_ITEM_TYPE_VF, 1219 RTE_FLOW_ITEM_TYPE_END, 1220 }; 1221 1222 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = { 1223 RTE_FLOW_ITEM_TYPE_ETH, 1224 RTE_FLOW_ITEM_TYPE_VLAN, 1225 RTE_FLOW_ITEM_TYPE_RAW, 1226 RTE_FLOW_ITEM_TYPE_VF, 1227 RTE_FLOW_ITEM_TYPE_END, 1228 }; 1229 1230 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = { 1231 RTE_FLOW_ITEM_TYPE_ETH, 1232 RTE_FLOW_ITEM_TYPE_VLAN, 1233 RTE_FLOW_ITEM_TYPE_RAW, 1234 RTE_FLOW_ITEM_TYPE_RAW, 1235 RTE_FLOW_ITEM_TYPE_VF, 1236 RTE_FLOW_ITEM_TYPE_END, 1237 }; 1238 1239 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = { 1240 RTE_FLOW_ITEM_TYPE_ETH, 1241 RTE_FLOW_ITEM_TYPE_VLAN, 1242 RTE_FLOW_ITEM_TYPE_RAW, 1243 RTE_FLOW_ITEM_TYPE_RAW, 1244 RTE_FLOW_ITEM_TYPE_RAW, 1245 RTE_FLOW_ITEM_TYPE_VF, 1246 RTE_FLOW_ITEM_TYPE_END, 1247 }; 1248 1249 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = { 1250 RTE_FLOW_ITEM_TYPE_ETH, 1251 RTE_FLOW_ITEM_TYPE_VLAN, 1252 RTE_FLOW_ITEM_TYPE_IPV4, 1253 RTE_FLOW_ITEM_TYPE_RAW, 1254 RTE_FLOW_ITEM_TYPE_VF, 1255 RTE_FLOW_ITEM_TYPE_END, 1256 }; 1257 1258 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = { 1259 RTE_FLOW_ITEM_TYPE_ETH, 1260 RTE_FLOW_ITEM_TYPE_VLAN, 1261 RTE_FLOW_ITEM_TYPE_IPV4, 1262 RTE_FLOW_ITEM_TYPE_RAW, 1263 RTE_FLOW_ITEM_TYPE_RAW, 1264 RTE_FLOW_ITEM_TYPE_VF, 1265 RTE_FLOW_ITEM_TYPE_END, 1266 }; 1267 1268 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = { 1269 RTE_FLOW_ITEM_TYPE_ETH, 1270 RTE_FLOW_ITEM_TYPE_VLAN, 1271 RTE_FLOW_ITEM_TYPE_IPV4, 1272 RTE_FLOW_ITEM_TYPE_RAW, 1273 RTE_FLOW_ITEM_TYPE_RAW, 1274 RTE_FLOW_ITEM_TYPE_RAW, 1275 RTE_FLOW_ITEM_TYPE_VF, 1276 RTE_FLOW_ITEM_TYPE_END, 1277 }; 1278 1279 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = { 1280 RTE_FLOW_ITEM_TYPE_ETH, 1281 RTE_FLOW_ITEM_TYPE_VLAN, 1282 RTE_FLOW_ITEM_TYPE_IPV4, 1283 RTE_FLOW_ITEM_TYPE_UDP, 1284 RTE_FLOW_ITEM_TYPE_RAW, 1285 RTE_FLOW_ITEM_TYPE_VF, 1286 RTE_FLOW_ITEM_TYPE_END, 1287 }; 1288 1289 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = { 1290 RTE_FLOW_ITEM_TYPE_ETH, 1291 RTE_FLOW_ITEM_TYPE_VLAN, 1292 RTE_FLOW_ITEM_TYPE_IPV4, 1293 RTE_FLOW_ITEM_TYPE_UDP, 1294 RTE_FLOW_ITEM_TYPE_RAW, 1295 RTE_FLOW_ITEM_TYPE_RAW, 1296 RTE_FLOW_ITEM_TYPE_VF, 1297 RTE_FLOW_ITEM_TYPE_END, 1298 }; 1299 1300 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = { 1301 RTE_FLOW_ITEM_TYPE_ETH, 1302 RTE_FLOW_ITEM_TYPE_VLAN, 1303 RTE_FLOW_ITEM_TYPE_IPV4, 1304 RTE_FLOW_ITEM_TYPE_UDP, 1305 RTE_FLOW_ITEM_TYPE_RAW, 1306 RTE_FLOW_ITEM_TYPE_RAW, 1307 RTE_FLOW_ITEM_TYPE_RAW, 1308 RTE_FLOW_ITEM_TYPE_VF, 1309 RTE_FLOW_ITEM_TYPE_END, 1310 }; 1311 1312 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = { 1313 RTE_FLOW_ITEM_TYPE_ETH, 1314 RTE_FLOW_ITEM_TYPE_VLAN, 1315 RTE_FLOW_ITEM_TYPE_IPV4, 1316 RTE_FLOW_ITEM_TYPE_TCP, 1317 RTE_FLOW_ITEM_TYPE_RAW, 1318 RTE_FLOW_ITEM_TYPE_VF, 1319 RTE_FLOW_ITEM_TYPE_END, 1320 }; 1321 1322 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = { 1323 RTE_FLOW_ITEM_TYPE_ETH, 1324 RTE_FLOW_ITEM_TYPE_VLAN, 1325 RTE_FLOW_ITEM_TYPE_IPV4, 1326 RTE_FLOW_ITEM_TYPE_TCP, 1327 RTE_FLOW_ITEM_TYPE_RAW, 1328 RTE_FLOW_ITEM_TYPE_RAW, 1329 RTE_FLOW_ITEM_TYPE_VF, 1330 RTE_FLOW_ITEM_TYPE_END, 1331 }; 1332 1333 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = { 1334 RTE_FLOW_ITEM_TYPE_ETH, 1335 RTE_FLOW_ITEM_TYPE_VLAN, 1336 RTE_FLOW_ITEM_TYPE_IPV4, 1337 RTE_FLOW_ITEM_TYPE_TCP, 1338 RTE_FLOW_ITEM_TYPE_RAW, 1339 RTE_FLOW_ITEM_TYPE_RAW, 1340 RTE_FLOW_ITEM_TYPE_RAW, 1341 RTE_FLOW_ITEM_TYPE_VF, 1342 RTE_FLOW_ITEM_TYPE_END, 1343 }; 1344 1345 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = { 1346 RTE_FLOW_ITEM_TYPE_ETH, 1347 RTE_FLOW_ITEM_TYPE_VLAN, 1348 RTE_FLOW_ITEM_TYPE_IPV4, 1349 RTE_FLOW_ITEM_TYPE_SCTP, 1350 RTE_FLOW_ITEM_TYPE_RAW, 1351 RTE_FLOW_ITEM_TYPE_VF, 1352 RTE_FLOW_ITEM_TYPE_END, 1353 }; 1354 1355 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = { 1356 RTE_FLOW_ITEM_TYPE_ETH, 1357 RTE_FLOW_ITEM_TYPE_VLAN, 1358 RTE_FLOW_ITEM_TYPE_IPV4, 1359 RTE_FLOW_ITEM_TYPE_SCTP, 1360 RTE_FLOW_ITEM_TYPE_RAW, 1361 RTE_FLOW_ITEM_TYPE_RAW, 1362 RTE_FLOW_ITEM_TYPE_VF, 1363 RTE_FLOW_ITEM_TYPE_END, 1364 }; 1365 1366 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = { 1367 RTE_FLOW_ITEM_TYPE_ETH, 1368 RTE_FLOW_ITEM_TYPE_VLAN, 1369 RTE_FLOW_ITEM_TYPE_IPV4, 1370 RTE_FLOW_ITEM_TYPE_SCTP, 1371 RTE_FLOW_ITEM_TYPE_RAW, 1372 RTE_FLOW_ITEM_TYPE_RAW, 1373 RTE_FLOW_ITEM_TYPE_RAW, 1374 RTE_FLOW_ITEM_TYPE_VF, 1375 RTE_FLOW_ITEM_TYPE_END, 1376 }; 1377 1378 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = { 1379 RTE_FLOW_ITEM_TYPE_ETH, 1380 RTE_FLOW_ITEM_TYPE_VLAN, 1381 RTE_FLOW_ITEM_TYPE_IPV6, 1382 RTE_FLOW_ITEM_TYPE_RAW, 1383 RTE_FLOW_ITEM_TYPE_VF, 1384 RTE_FLOW_ITEM_TYPE_END, 1385 }; 1386 1387 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = { 1388 RTE_FLOW_ITEM_TYPE_ETH, 1389 RTE_FLOW_ITEM_TYPE_VLAN, 1390 RTE_FLOW_ITEM_TYPE_IPV6, 1391 RTE_FLOW_ITEM_TYPE_RAW, 1392 RTE_FLOW_ITEM_TYPE_RAW, 1393 RTE_FLOW_ITEM_TYPE_VF, 1394 RTE_FLOW_ITEM_TYPE_END, 1395 }; 1396 1397 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = { 1398 RTE_FLOW_ITEM_TYPE_ETH, 1399 RTE_FLOW_ITEM_TYPE_VLAN, 1400 RTE_FLOW_ITEM_TYPE_IPV6, 1401 RTE_FLOW_ITEM_TYPE_RAW, 1402 RTE_FLOW_ITEM_TYPE_RAW, 1403 RTE_FLOW_ITEM_TYPE_RAW, 1404 RTE_FLOW_ITEM_TYPE_VF, 1405 RTE_FLOW_ITEM_TYPE_END, 1406 }; 1407 1408 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = { 1409 RTE_FLOW_ITEM_TYPE_ETH, 1410 RTE_FLOW_ITEM_TYPE_VLAN, 1411 RTE_FLOW_ITEM_TYPE_IPV6, 1412 RTE_FLOW_ITEM_TYPE_UDP, 1413 RTE_FLOW_ITEM_TYPE_RAW, 1414 RTE_FLOW_ITEM_TYPE_VF, 1415 RTE_FLOW_ITEM_TYPE_END, 1416 }; 1417 1418 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = { 1419 RTE_FLOW_ITEM_TYPE_ETH, 1420 RTE_FLOW_ITEM_TYPE_VLAN, 1421 RTE_FLOW_ITEM_TYPE_IPV6, 1422 RTE_FLOW_ITEM_TYPE_UDP, 1423 RTE_FLOW_ITEM_TYPE_RAW, 1424 RTE_FLOW_ITEM_TYPE_RAW, 1425 RTE_FLOW_ITEM_TYPE_VF, 1426 RTE_FLOW_ITEM_TYPE_END, 1427 }; 1428 1429 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = { 1430 RTE_FLOW_ITEM_TYPE_ETH, 1431 RTE_FLOW_ITEM_TYPE_VLAN, 1432 RTE_FLOW_ITEM_TYPE_IPV6, 1433 RTE_FLOW_ITEM_TYPE_UDP, 1434 RTE_FLOW_ITEM_TYPE_RAW, 1435 RTE_FLOW_ITEM_TYPE_RAW, 1436 RTE_FLOW_ITEM_TYPE_RAW, 1437 RTE_FLOW_ITEM_TYPE_VF, 1438 RTE_FLOW_ITEM_TYPE_END, 1439 }; 1440 1441 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = { 1442 RTE_FLOW_ITEM_TYPE_ETH, 1443 RTE_FLOW_ITEM_TYPE_VLAN, 1444 RTE_FLOW_ITEM_TYPE_IPV6, 1445 RTE_FLOW_ITEM_TYPE_TCP, 1446 RTE_FLOW_ITEM_TYPE_RAW, 1447 RTE_FLOW_ITEM_TYPE_VF, 1448 RTE_FLOW_ITEM_TYPE_END, 1449 }; 1450 1451 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = { 1452 RTE_FLOW_ITEM_TYPE_ETH, 1453 RTE_FLOW_ITEM_TYPE_VLAN, 1454 RTE_FLOW_ITEM_TYPE_IPV6, 1455 RTE_FLOW_ITEM_TYPE_TCP, 1456 RTE_FLOW_ITEM_TYPE_RAW, 1457 RTE_FLOW_ITEM_TYPE_RAW, 1458 RTE_FLOW_ITEM_TYPE_VF, 1459 RTE_FLOW_ITEM_TYPE_END, 1460 }; 1461 1462 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = { 1463 RTE_FLOW_ITEM_TYPE_ETH, 1464 RTE_FLOW_ITEM_TYPE_VLAN, 1465 RTE_FLOW_ITEM_TYPE_IPV6, 1466 RTE_FLOW_ITEM_TYPE_TCP, 1467 RTE_FLOW_ITEM_TYPE_RAW, 1468 RTE_FLOW_ITEM_TYPE_RAW, 1469 RTE_FLOW_ITEM_TYPE_RAW, 1470 RTE_FLOW_ITEM_TYPE_VF, 1471 RTE_FLOW_ITEM_TYPE_END, 1472 }; 1473 1474 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = { 1475 RTE_FLOW_ITEM_TYPE_ETH, 1476 RTE_FLOW_ITEM_TYPE_VLAN, 1477 RTE_FLOW_ITEM_TYPE_IPV6, 1478 RTE_FLOW_ITEM_TYPE_SCTP, 1479 RTE_FLOW_ITEM_TYPE_RAW, 1480 RTE_FLOW_ITEM_TYPE_VF, 1481 RTE_FLOW_ITEM_TYPE_END, 1482 }; 1483 1484 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = { 1485 RTE_FLOW_ITEM_TYPE_ETH, 1486 RTE_FLOW_ITEM_TYPE_VLAN, 1487 RTE_FLOW_ITEM_TYPE_IPV6, 1488 RTE_FLOW_ITEM_TYPE_SCTP, 1489 RTE_FLOW_ITEM_TYPE_RAW, 1490 RTE_FLOW_ITEM_TYPE_RAW, 1491 RTE_FLOW_ITEM_TYPE_VF, 1492 RTE_FLOW_ITEM_TYPE_END, 1493 }; 1494 1495 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = { 1496 RTE_FLOW_ITEM_TYPE_ETH, 1497 RTE_FLOW_ITEM_TYPE_VLAN, 1498 RTE_FLOW_ITEM_TYPE_IPV6, 1499 RTE_FLOW_ITEM_TYPE_SCTP, 1500 RTE_FLOW_ITEM_TYPE_RAW, 1501 RTE_FLOW_ITEM_TYPE_RAW, 1502 RTE_FLOW_ITEM_TYPE_RAW, 1503 RTE_FLOW_ITEM_TYPE_VF, 1504 RTE_FLOW_ITEM_TYPE_END, 1505 }; 1506 1507 /* Pattern matched tunnel filter */ 1508 static enum rte_flow_item_type pattern_vxlan_1[] = { 1509 RTE_FLOW_ITEM_TYPE_ETH, 1510 RTE_FLOW_ITEM_TYPE_IPV4, 1511 RTE_FLOW_ITEM_TYPE_UDP, 1512 RTE_FLOW_ITEM_TYPE_VXLAN, 1513 RTE_FLOW_ITEM_TYPE_ETH, 1514 RTE_FLOW_ITEM_TYPE_END, 1515 }; 1516 1517 static enum rte_flow_item_type pattern_vxlan_2[] = { 1518 RTE_FLOW_ITEM_TYPE_ETH, 1519 RTE_FLOW_ITEM_TYPE_IPV6, 1520 RTE_FLOW_ITEM_TYPE_UDP, 1521 RTE_FLOW_ITEM_TYPE_VXLAN, 1522 RTE_FLOW_ITEM_TYPE_ETH, 1523 RTE_FLOW_ITEM_TYPE_END, 1524 }; 1525 1526 static enum rte_flow_item_type pattern_vxlan_3[] = { 1527 RTE_FLOW_ITEM_TYPE_ETH, 1528 RTE_FLOW_ITEM_TYPE_IPV4, 1529 RTE_FLOW_ITEM_TYPE_UDP, 1530 RTE_FLOW_ITEM_TYPE_VXLAN, 1531 RTE_FLOW_ITEM_TYPE_ETH, 1532 RTE_FLOW_ITEM_TYPE_VLAN, 1533 RTE_FLOW_ITEM_TYPE_END, 1534 }; 1535 1536 static enum rte_flow_item_type pattern_vxlan_4[] = { 1537 RTE_FLOW_ITEM_TYPE_ETH, 1538 RTE_FLOW_ITEM_TYPE_IPV6, 1539 RTE_FLOW_ITEM_TYPE_UDP, 1540 RTE_FLOW_ITEM_TYPE_VXLAN, 1541 RTE_FLOW_ITEM_TYPE_ETH, 1542 RTE_FLOW_ITEM_TYPE_VLAN, 1543 RTE_FLOW_ITEM_TYPE_END, 1544 }; 1545 1546 static enum rte_flow_item_type pattern_nvgre_1[] = { 1547 RTE_FLOW_ITEM_TYPE_ETH, 1548 RTE_FLOW_ITEM_TYPE_IPV4, 1549 RTE_FLOW_ITEM_TYPE_NVGRE, 1550 RTE_FLOW_ITEM_TYPE_ETH, 1551 RTE_FLOW_ITEM_TYPE_END, 1552 }; 1553 1554 static enum rte_flow_item_type pattern_nvgre_2[] = { 1555 RTE_FLOW_ITEM_TYPE_ETH, 1556 RTE_FLOW_ITEM_TYPE_IPV6, 1557 RTE_FLOW_ITEM_TYPE_NVGRE, 1558 RTE_FLOW_ITEM_TYPE_ETH, 1559 RTE_FLOW_ITEM_TYPE_END, 1560 }; 1561 1562 static enum rte_flow_item_type pattern_nvgre_3[] = { 1563 RTE_FLOW_ITEM_TYPE_ETH, 1564 RTE_FLOW_ITEM_TYPE_IPV4, 1565 RTE_FLOW_ITEM_TYPE_NVGRE, 1566 RTE_FLOW_ITEM_TYPE_ETH, 1567 RTE_FLOW_ITEM_TYPE_VLAN, 1568 RTE_FLOW_ITEM_TYPE_END, 1569 }; 1570 1571 static enum rte_flow_item_type pattern_nvgre_4[] = { 1572 RTE_FLOW_ITEM_TYPE_ETH, 1573 RTE_FLOW_ITEM_TYPE_IPV6, 1574 RTE_FLOW_ITEM_TYPE_NVGRE, 1575 RTE_FLOW_ITEM_TYPE_ETH, 1576 RTE_FLOW_ITEM_TYPE_VLAN, 1577 RTE_FLOW_ITEM_TYPE_END, 1578 }; 1579 1580 static enum rte_flow_item_type pattern_mpls_1[] = { 1581 RTE_FLOW_ITEM_TYPE_ETH, 1582 RTE_FLOW_ITEM_TYPE_IPV4, 1583 RTE_FLOW_ITEM_TYPE_UDP, 1584 RTE_FLOW_ITEM_TYPE_MPLS, 1585 RTE_FLOW_ITEM_TYPE_END, 1586 }; 1587 1588 static enum rte_flow_item_type pattern_mpls_2[] = { 1589 RTE_FLOW_ITEM_TYPE_ETH, 1590 RTE_FLOW_ITEM_TYPE_IPV6, 1591 RTE_FLOW_ITEM_TYPE_UDP, 1592 RTE_FLOW_ITEM_TYPE_MPLS, 1593 RTE_FLOW_ITEM_TYPE_END, 1594 }; 1595 1596 static enum rte_flow_item_type pattern_mpls_3[] = { 1597 RTE_FLOW_ITEM_TYPE_ETH, 1598 RTE_FLOW_ITEM_TYPE_IPV4, 1599 RTE_FLOW_ITEM_TYPE_GRE, 1600 RTE_FLOW_ITEM_TYPE_MPLS, 1601 RTE_FLOW_ITEM_TYPE_END, 1602 }; 1603 1604 static enum rte_flow_item_type pattern_mpls_4[] = { 1605 RTE_FLOW_ITEM_TYPE_ETH, 1606 RTE_FLOW_ITEM_TYPE_IPV6, 1607 RTE_FLOW_ITEM_TYPE_GRE, 1608 RTE_FLOW_ITEM_TYPE_MPLS, 1609 RTE_FLOW_ITEM_TYPE_END, 1610 }; 1611 1612 static enum rte_flow_item_type pattern_qinq_1[] = { 1613 RTE_FLOW_ITEM_TYPE_ETH, 1614 RTE_FLOW_ITEM_TYPE_VLAN, 1615 RTE_FLOW_ITEM_TYPE_VLAN, 1616 RTE_FLOW_ITEM_TYPE_END, 1617 }; 1618 1619 static struct i40e_valid_pattern i40e_supported_patterns[] = { 1620 /* Ethertype */ 1621 { pattern_ethertype, i40e_flow_parse_ethertype_filter }, 1622 /* FDIR - support default flow type without flexible payload*/ 1623 { pattern_ethertype, i40e_flow_parse_fdir_filter }, 1624 { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter }, 1625 { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter }, 1626 { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter }, 1627 { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter }, 1628 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter }, 1629 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter }, 1630 { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter }, 1631 { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter }, 1632 { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter }, 1633 { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter }, 1634 { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter }, 1635 { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter }, 1636 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter }, 1637 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter }, 1638 { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter }, 1639 { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter }, 1640 /* FDIR - support default flow type with flexible payload */ 1641 { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter }, 1642 { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter }, 1643 { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter }, 1644 { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter }, 1645 { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter }, 1646 { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter }, 1647 { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter }, 1648 { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter }, 1649 { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter }, 1650 { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter }, 1651 { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter }, 1652 { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter }, 1653 { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter }, 1654 { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter }, 1655 { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter }, 1656 { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter }, 1657 { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter }, 1658 { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter }, 1659 { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter }, 1660 { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter }, 1661 { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter }, 1662 { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter }, 1663 { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter }, 1664 { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter }, 1665 { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter }, 1666 { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter }, 1667 { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter }, 1668 /* FDIR - support single vlan input set */ 1669 { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter }, 1670 { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter }, 1671 { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter }, 1672 { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter }, 1673 { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter }, 1674 { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter }, 1675 { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter }, 1676 { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter }, 1677 { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter }, 1678 { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter }, 1679 { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter }, 1680 { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter }, 1681 { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter }, 1682 { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter }, 1683 { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter }, 1684 { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter }, 1685 { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter }, 1686 { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter }, 1687 { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter }, 1688 { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter }, 1689 { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter }, 1690 { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter }, 1691 { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter }, 1692 { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter }, 1693 { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter }, 1694 { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter }, 1695 { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter }, 1696 { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter }, 1697 { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter }, 1698 { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter }, 1699 { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter }, 1700 { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter }, 1701 { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter }, 1702 { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter }, 1703 { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter }, 1704 { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter }, 1705 /* FDIR - support VF item */ 1706 { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter }, 1707 { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter }, 1708 { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter }, 1709 { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter }, 1710 { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter }, 1711 { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter }, 1712 { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter }, 1713 { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter }, 1714 { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter }, 1715 { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter }, 1716 { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter }, 1717 { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter }, 1718 { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter }, 1719 { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter }, 1720 { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1721 { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1722 { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1723 { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1724 { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1725 { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1726 { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1727 { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1728 { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1729 { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter }, 1730 { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter }, 1731 { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter }, 1732 { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1733 { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1734 { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1735 { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1736 { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1737 { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1738 { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1739 { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1740 { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1741 { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter }, 1742 { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter }, 1743 { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter }, 1744 { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter }, 1745 { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter }, 1746 { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter }, 1747 { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter }, 1748 { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter }, 1749 { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter }, 1750 { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter }, 1751 { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter }, 1752 { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter }, 1753 { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter }, 1754 { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter }, 1755 { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter }, 1756 { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1757 { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1758 { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1759 { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1760 { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1761 { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1762 { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1763 { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1764 { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1765 { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter }, 1766 { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter }, 1767 { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter }, 1768 { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1769 { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1770 { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1771 { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1772 { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1773 { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1774 { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter }, 1775 { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter }, 1776 { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter }, 1777 /* VXLAN */ 1778 { pattern_vxlan_1, i40e_flow_parse_vxlan_filter }, 1779 { pattern_vxlan_2, i40e_flow_parse_vxlan_filter }, 1780 { pattern_vxlan_3, i40e_flow_parse_vxlan_filter }, 1781 { pattern_vxlan_4, i40e_flow_parse_vxlan_filter }, 1782 /* NVGRE */ 1783 { pattern_nvgre_1, i40e_flow_parse_nvgre_filter }, 1784 { pattern_nvgre_2, i40e_flow_parse_nvgre_filter }, 1785 { pattern_nvgre_3, i40e_flow_parse_nvgre_filter }, 1786 { pattern_nvgre_4, i40e_flow_parse_nvgre_filter }, 1787 /* MPLSoUDP & MPLSoGRE */ 1788 { pattern_mpls_1, i40e_flow_parse_mpls_filter }, 1789 { pattern_mpls_2, i40e_flow_parse_mpls_filter }, 1790 { pattern_mpls_3, i40e_flow_parse_mpls_filter }, 1791 { pattern_mpls_4, i40e_flow_parse_mpls_filter }, 1792 /* GTP-C & GTP-U */ 1793 { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter }, 1794 { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter }, 1795 { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter }, 1796 { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter }, 1797 /* QINQ */ 1798 { pattern_qinq_1, i40e_flow_parse_qinq_filter }, 1799 }; 1800 1801 #define NEXT_ITEM_OF_ACTION(act, actions, index) \ 1802 do { \ 1803 act = actions + index; \ 1804 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \ 1805 index++; \ 1806 act = actions + index; \ 1807 } \ 1808 } while (0) 1809 1810 /* Find the first VOID or non-VOID item pointer */ 1811 static const struct rte_flow_item * 1812 i40e_find_first_item(const struct rte_flow_item *item, bool is_void) 1813 { 1814 bool is_find; 1815 1816 while (item->type != RTE_FLOW_ITEM_TYPE_END) { 1817 if (is_void) 1818 is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID; 1819 else 1820 is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID; 1821 if (is_find) 1822 break; 1823 item++; 1824 } 1825 return item; 1826 } 1827 1828 /* Skip all VOID items of the pattern */ 1829 static void 1830 i40e_pattern_skip_void_item(struct rte_flow_item *items, 1831 const struct rte_flow_item *pattern) 1832 { 1833 uint32_t cpy_count = 0; 1834 const struct rte_flow_item *pb = pattern, *pe = pattern; 1835 1836 for (;;) { 1837 /* Find a non-void item first */ 1838 pb = i40e_find_first_item(pb, false); 1839 if (pb->type == RTE_FLOW_ITEM_TYPE_END) { 1840 pe = pb; 1841 break; 1842 } 1843 1844 /* Find a void item */ 1845 pe = i40e_find_first_item(pb + 1, true); 1846 1847 cpy_count = pe - pb; 1848 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count); 1849 1850 items += cpy_count; 1851 1852 if (pe->type == RTE_FLOW_ITEM_TYPE_END) { 1853 pb = pe; 1854 break; 1855 } 1856 1857 pb = pe + 1; 1858 } 1859 /* Copy the END item. */ 1860 rte_memcpy(items, pe, sizeof(struct rte_flow_item)); 1861 } 1862 1863 /* Check if the pattern matches a supported item type array */ 1864 static bool 1865 i40e_match_pattern(enum rte_flow_item_type *item_array, 1866 struct rte_flow_item *pattern) 1867 { 1868 struct rte_flow_item *item = pattern; 1869 1870 while ((*item_array == item->type) && 1871 (*item_array != RTE_FLOW_ITEM_TYPE_END)) { 1872 item_array++; 1873 item++; 1874 } 1875 1876 return (*item_array == RTE_FLOW_ITEM_TYPE_END && 1877 item->type == RTE_FLOW_ITEM_TYPE_END); 1878 } 1879 1880 /* Find if there's parse filter function matched */ 1881 static parse_filter_t 1882 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx) 1883 { 1884 parse_filter_t parse_filter = NULL; 1885 uint8_t i = *idx; 1886 1887 for (; i < RTE_DIM(i40e_supported_patterns); i++) { 1888 if (i40e_match_pattern(i40e_supported_patterns[i].items, 1889 pattern)) { 1890 parse_filter = i40e_supported_patterns[i].parse_filter; 1891 break; 1892 } 1893 } 1894 1895 *idx = ++i; 1896 1897 return parse_filter; 1898 } 1899 1900 /* Parse attributes */ 1901 static int 1902 i40e_flow_parse_attr(const struct rte_flow_attr *attr, 1903 struct rte_flow_error *error) 1904 { 1905 /* Must be input direction */ 1906 if (!attr->ingress) { 1907 rte_flow_error_set(error, EINVAL, 1908 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1909 attr, "Only support ingress."); 1910 return -rte_errno; 1911 } 1912 1913 /* Not supported */ 1914 if (attr->egress) { 1915 rte_flow_error_set(error, EINVAL, 1916 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, 1917 attr, "Not support egress."); 1918 return -rte_errno; 1919 } 1920 1921 /* Not supported */ 1922 if (attr->priority) { 1923 rte_flow_error_set(error, EINVAL, 1924 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1925 attr, "Not support priority."); 1926 return -rte_errno; 1927 } 1928 1929 /* Not supported */ 1930 if (attr->group) { 1931 rte_flow_error_set(error, EINVAL, 1932 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 1933 attr, "Not support group."); 1934 return -rte_errno; 1935 } 1936 1937 return 0; 1938 } 1939 1940 static uint16_t 1941 i40e_get_outer_vlan(struct rte_eth_dev *dev) 1942 { 1943 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1944 int qinq = dev->data->dev_conf.rxmode.offloads & 1945 DEV_RX_OFFLOAD_VLAN_EXTEND; 1946 uint64_t reg_r = 0; 1947 uint16_t reg_id; 1948 uint16_t tpid; 1949 1950 if (qinq) 1951 reg_id = 2; 1952 else 1953 reg_id = 3; 1954 1955 i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), 1956 ®_r, NULL); 1957 1958 tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF; 1959 1960 return tpid; 1961 } 1962 1963 /* 1. Last in item should be NULL as range is not supported. 1964 * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE. 1965 * 3. SRC mac_addr mask should be 00:00:00:00:00:00. 1966 * 4. DST mac_addr mask should be 00:00:00:00:00:00 or 1967 * FF:FF:FF:FF:FF:FF 1968 * 5. Ether_type mask should be 0xFFFF. 1969 */ 1970 static int 1971 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev, 1972 const struct rte_flow_item *pattern, 1973 struct rte_flow_error *error, 1974 struct rte_eth_ethertype_filter *filter) 1975 { 1976 const struct rte_flow_item *item = pattern; 1977 const struct rte_flow_item_eth *eth_spec; 1978 const struct rte_flow_item_eth *eth_mask; 1979 enum rte_flow_item_type item_type; 1980 uint16_t outer_tpid; 1981 1982 outer_tpid = i40e_get_outer_vlan(dev); 1983 1984 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 1985 if (item->last) { 1986 rte_flow_error_set(error, EINVAL, 1987 RTE_FLOW_ERROR_TYPE_ITEM, 1988 item, 1989 "Not support range"); 1990 return -rte_errno; 1991 } 1992 item_type = item->type; 1993 switch (item_type) { 1994 case RTE_FLOW_ITEM_TYPE_ETH: 1995 eth_spec = item->spec; 1996 eth_mask = item->mask; 1997 /* Get the MAC info. */ 1998 if (!eth_spec || !eth_mask) { 1999 rte_flow_error_set(error, EINVAL, 2000 RTE_FLOW_ERROR_TYPE_ITEM, 2001 item, 2002 "NULL ETH spec/mask"); 2003 return -rte_errno; 2004 } 2005 2006 /* Mask bits of source MAC address must be full of 0. 2007 * Mask bits of destination MAC address must be full 2008 * of 1 or full of 0. 2009 */ 2010 if (!is_zero_ether_addr(ð_mask->src) || 2011 (!is_zero_ether_addr(ð_mask->dst) && 2012 !is_broadcast_ether_addr(ð_mask->dst))) { 2013 rte_flow_error_set(error, EINVAL, 2014 RTE_FLOW_ERROR_TYPE_ITEM, 2015 item, 2016 "Invalid MAC_addr mask"); 2017 return -rte_errno; 2018 } 2019 2020 if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) { 2021 rte_flow_error_set(error, EINVAL, 2022 RTE_FLOW_ERROR_TYPE_ITEM, 2023 item, 2024 "Invalid ethertype mask"); 2025 return -rte_errno; 2026 } 2027 2028 /* If mask bits of destination MAC address 2029 * are full of 1, set RTE_ETHTYPE_FLAGS_MAC. 2030 */ 2031 if (is_broadcast_ether_addr(ð_mask->dst)) { 2032 filter->mac_addr = eth_spec->dst; 2033 filter->flags |= RTE_ETHTYPE_FLAGS_MAC; 2034 } else { 2035 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC; 2036 } 2037 filter->ether_type = rte_be_to_cpu_16(eth_spec->type); 2038 2039 if (filter->ether_type == ETHER_TYPE_IPv4 || 2040 filter->ether_type == ETHER_TYPE_IPv6 || 2041 filter->ether_type == ETHER_TYPE_LLDP || 2042 filter->ether_type == outer_tpid) { 2043 rte_flow_error_set(error, EINVAL, 2044 RTE_FLOW_ERROR_TYPE_ITEM, 2045 item, 2046 "Unsupported ether_type in" 2047 " control packet filter."); 2048 return -rte_errno; 2049 } 2050 break; 2051 default: 2052 break; 2053 } 2054 } 2055 2056 return 0; 2057 } 2058 2059 /* Ethertype action only supports QUEUE or DROP. */ 2060 static int 2061 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev, 2062 const struct rte_flow_action *actions, 2063 struct rte_flow_error *error, 2064 struct rte_eth_ethertype_filter *filter) 2065 { 2066 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2067 const struct rte_flow_action *act; 2068 const struct rte_flow_action_queue *act_q; 2069 uint32_t index = 0; 2070 2071 /* Check if the first non-void action is QUEUE or DROP. */ 2072 NEXT_ITEM_OF_ACTION(act, actions, index); 2073 if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE && 2074 act->type != RTE_FLOW_ACTION_TYPE_DROP) { 2075 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 2076 act, "Not supported action."); 2077 return -rte_errno; 2078 } 2079 2080 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 2081 act_q = act->conf; 2082 filter->queue = act_q->index; 2083 if (filter->queue >= pf->dev_data->nb_rx_queues) { 2084 rte_flow_error_set(error, EINVAL, 2085 RTE_FLOW_ERROR_TYPE_ACTION, 2086 act, "Invalid queue ID for" 2087 " ethertype_filter."); 2088 return -rte_errno; 2089 } 2090 } else { 2091 filter->flags |= RTE_ETHTYPE_FLAGS_DROP; 2092 } 2093 2094 /* Check if the next non-void item is END */ 2095 index++; 2096 NEXT_ITEM_OF_ACTION(act, actions, index); 2097 if (act->type != RTE_FLOW_ACTION_TYPE_END) { 2098 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 2099 act, "Not supported action."); 2100 return -rte_errno; 2101 } 2102 2103 return 0; 2104 } 2105 2106 static int 2107 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev, 2108 const struct rte_flow_attr *attr, 2109 const struct rte_flow_item pattern[], 2110 const struct rte_flow_action actions[], 2111 struct rte_flow_error *error, 2112 union i40e_filter_t *filter) 2113 { 2114 struct rte_eth_ethertype_filter *ethertype_filter = 2115 &filter->ethertype_filter; 2116 int ret; 2117 2118 ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error, 2119 ethertype_filter); 2120 if (ret) 2121 return ret; 2122 2123 ret = i40e_flow_parse_ethertype_action(dev, actions, error, 2124 ethertype_filter); 2125 if (ret) 2126 return ret; 2127 2128 ret = i40e_flow_parse_attr(attr, error); 2129 if (ret) 2130 return ret; 2131 2132 cons_filter_type = RTE_ETH_FILTER_ETHERTYPE; 2133 2134 return ret; 2135 } 2136 2137 static int 2138 i40e_flow_check_raw_item(const struct rte_flow_item *item, 2139 const struct rte_flow_item_raw *raw_spec, 2140 struct rte_flow_error *error) 2141 { 2142 if (!raw_spec->relative) { 2143 rte_flow_error_set(error, EINVAL, 2144 RTE_FLOW_ERROR_TYPE_ITEM, 2145 item, 2146 "Relative should be 1."); 2147 return -rte_errno; 2148 } 2149 2150 if (raw_spec->offset % sizeof(uint16_t)) { 2151 rte_flow_error_set(error, EINVAL, 2152 RTE_FLOW_ERROR_TYPE_ITEM, 2153 item, 2154 "Offset should be even."); 2155 return -rte_errno; 2156 } 2157 2158 if (raw_spec->search || raw_spec->limit) { 2159 rte_flow_error_set(error, EINVAL, 2160 RTE_FLOW_ERROR_TYPE_ITEM, 2161 item, 2162 "search or limit is not supported."); 2163 return -rte_errno; 2164 } 2165 2166 if (raw_spec->offset < 0) { 2167 rte_flow_error_set(error, EINVAL, 2168 RTE_FLOW_ERROR_TYPE_ITEM, 2169 item, 2170 "Offset should be non-negative."); 2171 return -rte_errno; 2172 } 2173 return 0; 2174 } 2175 2176 static int 2177 i40e_flow_store_flex_pit(struct i40e_pf *pf, 2178 struct i40e_fdir_flex_pit *flex_pit, 2179 enum i40e_flxpld_layer_idx layer_idx, 2180 uint8_t raw_id) 2181 { 2182 uint8_t field_idx; 2183 2184 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id; 2185 /* Check if the configuration is conflicted */ 2186 if (pf->fdir.flex_pit_flag[layer_idx] && 2187 (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset || 2188 pf->fdir.flex_set[field_idx].size != flex_pit->size || 2189 pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset)) 2190 return -1; 2191 2192 /* Check if the configuration exists. */ 2193 if (pf->fdir.flex_pit_flag[layer_idx] && 2194 (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset && 2195 pf->fdir.flex_set[field_idx].size == flex_pit->size && 2196 pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset)) 2197 return 1; 2198 2199 pf->fdir.flex_set[field_idx].src_offset = 2200 flex_pit->src_offset; 2201 pf->fdir.flex_set[field_idx].size = 2202 flex_pit->size; 2203 pf->fdir.flex_set[field_idx].dst_offset = 2204 flex_pit->dst_offset; 2205 2206 return 0; 2207 } 2208 2209 static int 2210 i40e_flow_store_flex_mask(struct i40e_pf *pf, 2211 enum i40e_filter_pctype pctype, 2212 uint8_t *mask) 2213 { 2214 struct i40e_fdir_flex_mask flex_mask; 2215 uint16_t mask_tmp; 2216 uint8_t i, nb_bitmask = 0; 2217 2218 memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask)); 2219 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) { 2220 mask_tmp = I40E_WORD(mask[i], mask[i + 1]); 2221 if (mask_tmp) { 2222 flex_mask.word_mask |= 2223 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t)); 2224 if (mask_tmp != UINT16_MAX) { 2225 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp; 2226 flex_mask.bitmask[nb_bitmask].offset = 2227 i / sizeof(uint16_t); 2228 nb_bitmask++; 2229 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) 2230 return -1; 2231 } 2232 } 2233 } 2234 flex_mask.nb_bitmask = nb_bitmask; 2235 2236 if (pf->fdir.flex_mask_flag[pctype] && 2237 (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype], 2238 sizeof(struct i40e_fdir_flex_mask)))) 2239 return -2; 2240 else if (pf->fdir.flex_mask_flag[pctype] && 2241 !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype], 2242 sizeof(struct i40e_fdir_flex_mask)))) 2243 return 1; 2244 2245 memcpy(&pf->fdir.flex_mask[pctype], &flex_mask, 2246 sizeof(struct i40e_fdir_flex_mask)); 2247 return 0; 2248 } 2249 2250 static void 2251 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf, 2252 enum i40e_flxpld_layer_idx layer_idx, 2253 uint8_t raw_id) 2254 { 2255 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 2256 uint32_t flx_pit, flx_ort; 2257 uint8_t field_idx; 2258 uint16_t min_next_off = 0; /* in words */ 2259 uint8_t i; 2260 2261 if (raw_id) { 2262 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) | 2263 (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) | 2264 (layer_idx * I40E_MAX_FLXPLD_FIED); 2265 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort); 2266 } 2267 2268 /* Set flex pit */ 2269 for (i = 0; i < raw_id; i++) { 2270 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i; 2271 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset, 2272 pf->fdir.flex_set[field_idx].size, 2273 pf->fdir.flex_set[field_idx].dst_offset); 2274 2275 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit); 2276 min_next_off = pf->fdir.flex_set[field_idx].src_offset + 2277 pf->fdir.flex_set[field_idx].size; 2278 } 2279 2280 for (; i < I40E_MAX_FLXPLD_FIED; i++) { 2281 /* set the non-used register obeying register's constrain */ 2282 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i; 2283 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE, 2284 NONUSE_FLX_PIT_DEST_OFF); 2285 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit); 2286 min_next_off++; 2287 } 2288 2289 pf->fdir.flex_pit_flag[layer_idx] = 1; 2290 } 2291 2292 static void 2293 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf, 2294 enum i40e_filter_pctype pctype) 2295 { 2296 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 2297 struct i40e_fdir_flex_mask *flex_mask; 2298 uint32_t flxinset, fd_mask; 2299 uint8_t i; 2300 2301 /* Set flex mask */ 2302 flex_mask = &pf->fdir.flex_mask[pctype]; 2303 flxinset = (flex_mask->word_mask << 2304 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) & 2305 I40E_PRTQF_FD_FLXINSET_INSET_MASK; 2306 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset); 2307 2308 for (i = 0; i < flex_mask->nb_bitmask; i++) { 2309 fd_mask = (flex_mask->bitmask[i].mask << 2310 I40E_PRTQF_FD_MSK_MASK_SHIFT) & 2311 I40E_PRTQF_FD_MSK_MASK_MASK; 2312 fd_mask |= ((flex_mask->bitmask[i].offset + 2313 I40E_FLX_OFFSET_IN_FIELD_VECTOR) << 2314 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) & 2315 I40E_PRTQF_FD_MSK_OFFSET_MASK; 2316 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask); 2317 } 2318 2319 pf->fdir.flex_mask_flag[pctype] = 1; 2320 } 2321 2322 static int 2323 i40e_flow_set_fdir_inset(struct i40e_pf *pf, 2324 enum i40e_filter_pctype pctype, 2325 uint64_t input_set) 2326 { 2327 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 2328 uint64_t inset_reg = 0; 2329 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; 2330 int i, num; 2331 2332 /* Check if the input set is valid */ 2333 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR, 2334 input_set) != 0) { 2335 PMD_DRV_LOG(ERR, "Invalid input set"); 2336 return -EINVAL; 2337 } 2338 2339 /* Check if the configuration is conflicted */ 2340 if (pf->fdir.inset_flag[pctype] && 2341 memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t))) 2342 return -1; 2343 2344 if (pf->fdir.inset_flag[pctype] && 2345 !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t))) 2346 return 0; 2347 2348 num = i40e_generate_inset_mask_reg(input_set, mask_reg, 2349 I40E_INSET_MASK_NUM_REG); 2350 if (num < 0) 2351 return -EINVAL; 2352 2353 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); 2354 2355 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), 2356 (uint32_t)(inset_reg & UINT32_MAX)); 2357 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), 2358 (uint32_t)((inset_reg >> 2359 I40E_32_BIT_WIDTH) & UINT32_MAX)); 2360 2361 for (i = 0; i < num; i++) 2362 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 2363 mask_reg[i]); 2364 2365 /*clear unused mask registers of the pctype */ 2366 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) 2367 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0); 2368 I40E_WRITE_FLUSH(hw); 2369 2370 pf->fdir.input_set[pctype] = input_set; 2371 pf->fdir.inset_flag[pctype] = 1; 2372 return 0; 2373 } 2374 2375 static uint8_t 2376 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf, 2377 enum rte_flow_item_type item_type, 2378 struct i40e_fdir_filter_conf *filter) 2379 { 2380 struct i40e_customized_pctype *cus_pctype = NULL; 2381 2382 switch (item_type) { 2383 case RTE_FLOW_ITEM_TYPE_GTPC: 2384 cus_pctype = i40e_find_customized_pctype(pf, 2385 I40E_CUSTOMIZED_GTPC); 2386 break; 2387 case RTE_FLOW_ITEM_TYPE_GTPU: 2388 if (!filter->input.flow_ext.inner_ip) 2389 cus_pctype = i40e_find_customized_pctype(pf, 2390 I40E_CUSTOMIZED_GTPU); 2391 else if (filter->input.flow_ext.iip_type == 2392 I40E_FDIR_IPTYPE_IPV4) 2393 cus_pctype = i40e_find_customized_pctype(pf, 2394 I40E_CUSTOMIZED_GTPU_IPV4); 2395 else if (filter->input.flow_ext.iip_type == 2396 I40E_FDIR_IPTYPE_IPV6) 2397 cus_pctype = i40e_find_customized_pctype(pf, 2398 I40E_CUSTOMIZED_GTPU_IPV6); 2399 break; 2400 default: 2401 PMD_DRV_LOG(ERR, "Unsupported item type"); 2402 break; 2403 } 2404 2405 if (cus_pctype && cus_pctype->valid) 2406 return cus_pctype->pctype; 2407 2408 return I40E_FILTER_PCTYPE_INVALID; 2409 } 2410 2411 /* 1. Last in item should be NULL as range is not supported. 2412 * 2. Supported patterns: refer to array i40e_supported_patterns. 2413 * 3. Default supported flow type and input set: refer to array 2414 * valid_fdir_inset_table in i40e_ethdev.c. 2415 * 4. Mask of fields which need to be matched should be 2416 * filled with 1. 2417 * 5. Mask of fields which needn't to be matched should be 2418 * filled with 0. 2419 * 6. GTP profile supports GTPv1 only. 2420 * 7. GTP-C response message ('source_port' = 2123) is not supported. 2421 */ 2422 static int 2423 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev, 2424 const struct rte_flow_attr *attr, 2425 const struct rte_flow_item *pattern, 2426 struct rte_flow_error *error, 2427 struct i40e_fdir_filter_conf *filter) 2428 { 2429 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2430 const struct rte_flow_item *item = pattern; 2431 const struct rte_flow_item_eth *eth_spec, *eth_mask; 2432 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask; 2433 const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask; 2434 const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask; 2435 const struct rte_flow_item_tcp *tcp_spec, *tcp_mask; 2436 const struct rte_flow_item_udp *udp_spec, *udp_mask; 2437 const struct rte_flow_item_sctp *sctp_spec, *sctp_mask; 2438 const struct rte_flow_item_gtp *gtp_spec, *gtp_mask; 2439 const struct rte_flow_item_raw *raw_spec, *raw_mask; 2440 const struct rte_flow_item_vf *vf_spec; 2441 2442 uint8_t pctype = 0; 2443 uint64_t input_set = I40E_INSET_NONE; 2444 uint16_t frag_off; 2445 enum rte_flow_item_type item_type; 2446 enum rte_flow_item_type next_type; 2447 enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END; 2448 enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END; 2449 uint32_t i, j; 2450 uint8_t ipv6_addr_mask[16] = { 2451 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 2452 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 2453 enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX; 2454 uint8_t raw_id = 0; 2455 int32_t off_arr[I40E_MAX_FLXPLD_FIED]; 2456 uint16_t len_arr[I40E_MAX_FLXPLD_FIED]; 2457 struct i40e_fdir_flex_pit flex_pit; 2458 uint8_t next_dst_off = 0; 2459 uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN]; 2460 uint16_t flex_size; 2461 bool cfg_flex_pit = true; 2462 bool cfg_flex_msk = true; 2463 uint16_t outer_tpid; 2464 uint16_t ether_type; 2465 uint32_t vtc_flow_cpu; 2466 bool outer_ip = true; 2467 int ret; 2468 2469 memset(off_arr, 0, sizeof(off_arr)); 2470 memset(len_arr, 0, sizeof(len_arr)); 2471 memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN); 2472 outer_tpid = i40e_get_outer_vlan(dev); 2473 filter->input.flow_ext.customized_pctype = false; 2474 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 2475 if (item->last) { 2476 rte_flow_error_set(error, EINVAL, 2477 RTE_FLOW_ERROR_TYPE_ITEM, 2478 item, 2479 "Not support range"); 2480 return -rte_errno; 2481 } 2482 item_type = item->type; 2483 switch (item_type) { 2484 case RTE_FLOW_ITEM_TYPE_ETH: 2485 eth_spec = item->spec; 2486 eth_mask = item->mask; 2487 next_type = (item + 1)->type; 2488 2489 if (next_type == RTE_FLOW_ITEM_TYPE_END && 2490 (!eth_spec || !eth_mask)) { 2491 rte_flow_error_set(error, EINVAL, 2492 RTE_FLOW_ERROR_TYPE_ITEM, 2493 item, 2494 "NULL eth spec/mask."); 2495 return -rte_errno; 2496 } 2497 2498 if (eth_spec && eth_mask) { 2499 if (!is_zero_ether_addr(ð_mask->src) || 2500 !is_zero_ether_addr(ð_mask->dst)) { 2501 rte_flow_error_set(error, EINVAL, 2502 RTE_FLOW_ERROR_TYPE_ITEM, 2503 item, 2504 "Invalid MAC_addr mask."); 2505 return -rte_errno; 2506 } 2507 } 2508 if (eth_spec && eth_mask && eth_mask->type) { 2509 if (eth_mask->type != RTE_BE16(0xffff)) { 2510 rte_flow_error_set(error, EINVAL, 2511 RTE_FLOW_ERROR_TYPE_ITEM, 2512 item, 2513 "Invalid type mask."); 2514 return -rte_errno; 2515 } 2516 2517 ether_type = rte_be_to_cpu_16(eth_spec->type); 2518 2519 if (next_type == RTE_FLOW_ITEM_TYPE_VLAN || 2520 ether_type == ETHER_TYPE_IPv4 || 2521 ether_type == ETHER_TYPE_IPv6 || 2522 ether_type == ETHER_TYPE_ARP || 2523 ether_type == outer_tpid) { 2524 rte_flow_error_set(error, EINVAL, 2525 RTE_FLOW_ERROR_TYPE_ITEM, 2526 item, 2527 "Unsupported ether_type."); 2528 return -rte_errno; 2529 } 2530 input_set |= I40E_INSET_LAST_ETHER_TYPE; 2531 filter->input.flow.l2_flow.ether_type = 2532 eth_spec->type; 2533 } 2534 2535 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD; 2536 layer_idx = I40E_FLXPLD_L2_IDX; 2537 2538 break; 2539 case RTE_FLOW_ITEM_TYPE_VLAN: 2540 vlan_spec = item->spec; 2541 vlan_mask = item->mask; 2542 2543 RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE)); 2544 if (vlan_spec && vlan_mask) { 2545 if (vlan_mask->tci == 2546 rte_cpu_to_be_16(I40E_TCI_MASK)) { 2547 input_set |= I40E_INSET_VLAN_INNER; 2548 filter->input.flow_ext.vlan_tci = 2549 vlan_spec->tci; 2550 } 2551 } 2552 if (vlan_spec && vlan_mask && vlan_mask->inner_type) { 2553 if (vlan_mask->inner_type != RTE_BE16(0xffff)) { 2554 rte_flow_error_set(error, EINVAL, 2555 RTE_FLOW_ERROR_TYPE_ITEM, 2556 item, 2557 "Invalid inner_type" 2558 " mask."); 2559 return -rte_errno; 2560 } 2561 2562 ether_type = 2563 rte_be_to_cpu_16(vlan_spec->inner_type); 2564 2565 if (ether_type == ETHER_TYPE_IPv4 || 2566 ether_type == ETHER_TYPE_IPv6 || 2567 ether_type == ETHER_TYPE_ARP || 2568 ether_type == outer_tpid) { 2569 rte_flow_error_set(error, EINVAL, 2570 RTE_FLOW_ERROR_TYPE_ITEM, 2571 item, 2572 "Unsupported inner_type."); 2573 return -rte_errno; 2574 } 2575 input_set |= I40E_INSET_LAST_ETHER_TYPE; 2576 filter->input.flow.l2_flow.ether_type = 2577 vlan_spec->inner_type; 2578 } 2579 2580 pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD; 2581 layer_idx = I40E_FLXPLD_L2_IDX; 2582 2583 break; 2584 case RTE_FLOW_ITEM_TYPE_IPV4: 2585 l3 = RTE_FLOW_ITEM_TYPE_IPV4; 2586 ipv4_spec = item->spec; 2587 ipv4_mask = item->mask; 2588 pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; 2589 layer_idx = I40E_FLXPLD_L3_IDX; 2590 2591 if (ipv4_spec && ipv4_mask && outer_ip) { 2592 /* Check IPv4 mask and update input set */ 2593 if (ipv4_mask->hdr.version_ihl || 2594 ipv4_mask->hdr.total_length || 2595 ipv4_mask->hdr.packet_id || 2596 ipv4_mask->hdr.fragment_offset || 2597 ipv4_mask->hdr.hdr_checksum) { 2598 rte_flow_error_set(error, EINVAL, 2599 RTE_FLOW_ERROR_TYPE_ITEM, 2600 item, 2601 "Invalid IPv4 mask."); 2602 return -rte_errno; 2603 } 2604 2605 if (ipv4_mask->hdr.src_addr == UINT32_MAX) 2606 input_set |= I40E_INSET_IPV4_SRC; 2607 if (ipv4_mask->hdr.dst_addr == UINT32_MAX) 2608 input_set |= I40E_INSET_IPV4_DST; 2609 if (ipv4_mask->hdr.type_of_service == UINT8_MAX) 2610 input_set |= I40E_INSET_IPV4_TOS; 2611 if (ipv4_mask->hdr.time_to_live == UINT8_MAX) 2612 input_set |= I40E_INSET_IPV4_TTL; 2613 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX) 2614 input_set |= I40E_INSET_IPV4_PROTO; 2615 2616 /* Check if it is fragment. */ 2617 frag_off = ipv4_spec->hdr.fragment_offset; 2618 frag_off = rte_be_to_cpu_16(frag_off); 2619 if (frag_off & IPV4_HDR_OFFSET_MASK || 2620 frag_off & IPV4_HDR_MF_FLAG) 2621 pctype = I40E_FILTER_PCTYPE_FRAG_IPV4; 2622 2623 /* Get the filter info */ 2624 filter->input.flow.ip4_flow.proto = 2625 ipv4_spec->hdr.next_proto_id; 2626 filter->input.flow.ip4_flow.tos = 2627 ipv4_spec->hdr.type_of_service; 2628 filter->input.flow.ip4_flow.ttl = 2629 ipv4_spec->hdr.time_to_live; 2630 filter->input.flow.ip4_flow.src_ip = 2631 ipv4_spec->hdr.src_addr; 2632 filter->input.flow.ip4_flow.dst_ip = 2633 ipv4_spec->hdr.dst_addr; 2634 } else if (!ipv4_spec && !ipv4_mask && !outer_ip) { 2635 filter->input.flow_ext.inner_ip = true; 2636 filter->input.flow_ext.iip_type = 2637 I40E_FDIR_IPTYPE_IPV4; 2638 } else if ((ipv4_spec || ipv4_mask) && !outer_ip) { 2639 rte_flow_error_set(error, EINVAL, 2640 RTE_FLOW_ERROR_TYPE_ITEM, 2641 item, 2642 "Invalid inner IPv4 mask."); 2643 return -rte_errno; 2644 } 2645 2646 if (outer_ip) 2647 outer_ip = false; 2648 2649 break; 2650 case RTE_FLOW_ITEM_TYPE_IPV6: 2651 l3 = RTE_FLOW_ITEM_TYPE_IPV6; 2652 ipv6_spec = item->spec; 2653 ipv6_mask = item->mask; 2654 pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER; 2655 layer_idx = I40E_FLXPLD_L3_IDX; 2656 2657 if (ipv6_spec && ipv6_mask && outer_ip) { 2658 /* Check IPv6 mask and update input set */ 2659 if (ipv6_mask->hdr.payload_len) { 2660 rte_flow_error_set(error, EINVAL, 2661 RTE_FLOW_ERROR_TYPE_ITEM, 2662 item, 2663 "Invalid IPv6 mask"); 2664 return -rte_errno; 2665 } 2666 2667 if (!memcmp(ipv6_mask->hdr.src_addr, 2668 ipv6_addr_mask, 2669 RTE_DIM(ipv6_mask->hdr.src_addr))) 2670 input_set |= I40E_INSET_IPV6_SRC; 2671 if (!memcmp(ipv6_mask->hdr.dst_addr, 2672 ipv6_addr_mask, 2673 RTE_DIM(ipv6_mask->hdr.dst_addr))) 2674 input_set |= I40E_INSET_IPV6_DST; 2675 2676 if ((ipv6_mask->hdr.vtc_flow & 2677 rte_cpu_to_be_32(I40E_IPV6_TC_MASK)) 2678 == rte_cpu_to_be_32(I40E_IPV6_TC_MASK)) 2679 input_set |= I40E_INSET_IPV6_TC; 2680 if (ipv6_mask->hdr.proto == UINT8_MAX) 2681 input_set |= I40E_INSET_IPV6_NEXT_HDR; 2682 if (ipv6_mask->hdr.hop_limits == UINT8_MAX) 2683 input_set |= I40E_INSET_IPV6_HOP_LIMIT; 2684 2685 /* Get filter info */ 2686 vtc_flow_cpu = 2687 rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow); 2688 filter->input.flow.ipv6_flow.tc = 2689 (uint8_t)(vtc_flow_cpu >> 2690 I40E_FDIR_IPv6_TC_OFFSET); 2691 filter->input.flow.ipv6_flow.proto = 2692 ipv6_spec->hdr.proto; 2693 filter->input.flow.ipv6_flow.hop_limits = 2694 ipv6_spec->hdr.hop_limits; 2695 2696 rte_memcpy(filter->input.flow.ipv6_flow.src_ip, 2697 ipv6_spec->hdr.src_addr, 16); 2698 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip, 2699 ipv6_spec->hdr.dst_addr, 16); 2700 2701 /* Check if it is fragment. */ 2702 if (ipv6_spec->hdr.proto == 2703 I40E_IPV6_FRAG_HEADER) 2704 pctype = I40E_FILTER_PCTYPE_FRAG_IPV6; 2705 } else if (!ipv6_spec && !ipv6_mask && !outer_ip) { 2706 filter->input.flow_ext.inner_ip = true; 2707 filter->input.flow_ext.iip_type = 2708 I40E_FDIR_IPTYPE_IPV6; 2709 } else if ((ipv6_spec || ipv6_mask) && !outer_ip) { 2710 rte_flow_error_set(error, EINVAL, 2711 RTE_FLOW_ERROR_TYPE_ITEM, 2712 item, 2713 "Invalid inner IPv6 mask"); 2714 return -rte_errno; 2715 } 2716 2717 if (outer_ip) 2718 outer_ip = false; 2719 break; 2720 case RTE_FLOW_ITEM_TYPE_TCP: 2721 tcp_spec = item->spec; 2722 tcp_mask = item->mask; 2723 2724 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) 2725 pctype = 2726 I40E_FILTER_PCTYPE_NONF_IPV4_TCP; 2727 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) 2728 pctype = 2729 I40E_FILTER_PCTYPE_NONF_IPV6_TCP; 2730 if (tcp_spec && tcp_mask) { 2731 /* Check TCP mask and update input set */ 2732 if (tcp_mask->hdr.sent_seq || 2733 tcp_mask->hdr.recv_ack || 2734 tcp_mask->hdr.data_off || 2735 tcp_mask->hdr.tcp_flags || 2736 tcp_mask->hdr.rx_win || 2737 tcp_mask->hdr.cksum || 2738 tcp_mask->hdr.tcp_urp) { 2739 rte_flow_error_set(error, EINVAL, 2740 RTE_FLOW_ERROR_TYPE_ITEM, 2741 item, 2742 "Invalid TCP mask"); 2743 return -rte_errno; 2744 } 2745 2746 if (tcp_mask->hdr.src_port == UINT16_MAX) 2747 input_set |= I40E_INSET_SRC_PORT; 2748 if (tcp_mask->hdr.dst_port == UINT16_MAX) 2749 input_set |= I40E_INSET_DST_PORT; 2750 2751 /* Get filter info */ 2752 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) { 2753 filter->input.flow.tcp4_flow.src_port = 2754 tcp_spec->hdr.src_port; 2755 filter->input.flow.tcp4_flow.dst_port = 2756 tcp_spec->hdr.dst_port; 2757 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) { 2758 filter->input.flow.tcp6_flow.src_port = 2759 tcp_spec->hdr.src_port; 2760 filter->input.flow.tcp6_flow.dst_port = 2761 tcp_spec->hdr.dst_port; 2762 } 2763 } 2764 2765 layer_idx = I40E_FLXPLD_L4_IDX; 2766 2767 break; 2768 case RTE_FLOW_ITEM_TYPE_UDP: 2769 udp_spec = item->spec; 2770 udp_mask = item->mask; 2771 2772 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) 2773 pctype = 2774 I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 2775 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) 2776 pctype = 2777 I40E_FILTER_PCTYPE_NONF_IPV6_UDP; 2778 2779 if (udp_spec && udp_mask) { 2780 /* Check UDP mask and update input set*/ 2781 if (udp_mask->hdr.dgram_len || 2782 udp_mask->hdr.dgram_cksum) { 2783 rte_flow_error_set(error, EINVAL, 2784 RTE_FLOW_ERROR_TYPE_ITEM, 2785 item, 2786 "Invalid UDP mask"); 2787 return -rte_errno; 2788 } 2789 2790 if (udp_mask->hdr.src_port == UINT16_MAX) 2791 input_set |= I40E_INSET_SRC_PORT; 2792 if (udp_mask->hdr.dst_port == UINT16_MAX) 2793 input_set |= I40E_INSET_DST_PORT; 2794 2795 /* Get filter info */ 2796 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) { 2797 filter->input.flow.udp4_flow.src_port = 2798 udp_spec->hdr.src_port; 2799 filter->input.flow.udp4_flow.dst_port = 2800 udp_spec->hdr.dst_port; 2801 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) { 2802 filter->input.flow.udp6_flow.src_port = 2803 udp_spec->hdr.src_port; 2804 filter->input.flow.udp6_flow.dst_port = 2805 udp_spec->hdr.dst_port; 2806 } 2807 } 2808 2809 layer_idx = I40E_FLXPLD_L4_IDX; 2810 2811 break; 2812 case RTE_FLOW_ITEM_TYPE_GTPC: 2813 case RTE_FLOW_ITEM_TYPE_GTPU: 2814 if (!pf->gtp_support) { 2815 rte_flow_error_set(error, EINVAL, 2816 RTE_FLOW_ERROR_TYPE_ITEM, 2817 item, 2818 "Unsupported protocol"); 2819 return -rte_errno; 2820 } 2821 2822 gtp_spec = item->spec; 2823 gtp_mask = item->mask; 2824 2825 if (gtp_spec && gtp_mask) { 2826 if (gtp_mask->v_pt_rsv_flags || 2827 gtp_mask->msg_type || 2828 gtp_mask->msg_len || 2829 gtp_mask->teid != UINT32_MAX) { 2830 rte_flow_error_set(error, EINVAL, 2831 RTE_FLOW_ERROR_TYPE_ITEM, 2832 item, 2833 "Invalid GTP mask"); 2834 return -rte_errno; 2835 } 2836 2837 filter->input.flow.gtp_flow.teid = 2838 gtp_spec->teid; 2839 filter->input.flow_ext.customized_pctype = true; 2840 cus_proto = item_type; 2841 } 2842 break; 2843 case RTE_FLOW_ITEM_TYPE_SCTP: 2844 sctp_spec = item->spec; 2845 sctp_mask = item->mask; 2846 2847 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) 2848 pctype = 2849 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP; 2850 else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) 2851 pctype = 2852 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP; 2853 2854 if (sctp_spec && sctp_mask) { 2855 /* Check SCTP mask and update input set */ 2856 if (sctp_mask->hdr.cksum) { 2857 rte_flow_error_set(error, EINVAL, 2858 RTE_FLOW_ERROR_TYPE_ITEM, 2859 item, 2860 "Invalid UDP mask"); 2861 return -rte_errno; 2862 } 2863 2864 if (sctp_mask->hdr.src_port == UINT16_MAX) 2865 input_set |= I40E_INSET_SRC_PORT; 2866 if (sctp_mask->hdr.dst_port == UINT16_MAX) 2867 input_set |= I40E_INSET_DST_PORT; 2868 if (sctp_mask->hdr.tag == UINT32_MAX) 2869 input_set |= I40E_INSET_SCTP_VT; 2870 2871 /* Get filter info */ 2872 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) { 2873 filter->input.flow.sctp4_flow.src_port = 2874 sctp_spec->hdr.src_port; 2875 filter->input.flow.sctp4_flow.dst_port = 2876 sctp_spec->hdr.dst_port; 2877 filter->input.flow.sctp4_flow.verify_tag 2878 = sctp_spec->hdr.tag; 2879 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) { 2880 filter->input.flow.sctp6_flow.src_port = 2881 sctp_spec->hdr.src_port; 2882 filter->input.flow.sctp6_flow.dst_port = 2883 sctp_spec->hdr.dst_port; 2884 filter->input.flow.sctp6_flow.verify_tag 2885 = sctp_spec->hdr.tag; 2886 } 2887 } 2888 2889 layer_idx = I40E_FLXPLD_L4_IDX; 2890 2891 break; 2892 case RTE_FLOW_ITEM_TYPE_RAW: 2893 raw_spec = item->spec; 2894 raw_mask = item->mask; 2895 2896 if (!raw_spec || !raw_mask) { 2897 rte_flow_error_set(error, EINVAL, 2898 RTE_FLOW_ERROR_TYPE_ITEM, 2899 item, 2900 "NULL RAW spec/mask"); 2901 return -rte_errno; 2902 } 2903 2904 if (pf->support_multi_driver) { 2905 rte_flow_error_set(error, ENOTSUP, 2906 RTE_FLOW_ERROR_TYPE_ITEM, 2907 item, 2908 "Unsupported flexible payload."); 2909 return -rte_errno; 2910 } 2911 2912 ret = i40e_flow_check_raw_item(item, raw_spec, error); 2913 if (ret < 0) 2914 return ret; 2915 2916 off_arr[raw_id] = raw_spec->offset; 2917 len_arr[raw_id] = raw_spec->length; 2918 2919 flex_size = 0; 2920 memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit)); 2921 flex_pit.size = 2922 raw_spec->length / sizeof(uint16_t); 2923 flex_pit.dst_offset = 2924 next_dst_off / sizeof(uint16_t); 2925 2926 for (i = 0; i <= raw_id; i++) { 2927 if (i == raw_id) 2928 flex_pit.src_offset += 2929 raw_spec->offset / 2930 sizeof(uint16_t); 2931 else 2932 flex_pit.src_offset += 2933 (off_arr[i] + len_arr[i]) / 2934 sizeof(uint16_t); 2935 flex_size += len_arr[i]; 2936 } 2937 if (((flex_pit.src_offset + flex_pit.size) >= 2938 I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) || 2939 flex_size > I40E_FDIR_MAX_FLEXLEN) { 2940 rte_flow_error_set(error, EINVAL, 2941 RTE_FLOW_ERROR_TYPE_ITEM, 2942 item, 2943 "Exceeds maxmial payload limit."); 2944 return -rte_errno; 2945 } 2946 2947 /* Store flex pit to SW */ 2948 ret = i40e_flow_store_flex_pit(pf, &flex_pit, 2949 layer_idx, raw_id); 2950 if (ret < 0) { 2951 rte_flow_error_set(error, EINVAL, 2952 RTE_FLOW_ERROR_TYPE_ITEM, 2953 item, 2954 "Conflict with the first flexible rule."); 2955 return -rte_errno; 2956 } else if (ret > 0) 2957 cfg_flex_pit = false; 2958 2959 for (i = 0; i < raw_spec->length; i++) { 2960 j = i + next_dst_off; 2961 filter->input.flow_ext.flexbytes[j] = 2962 raw_spec->pattern[i]; 2963 flex_mask[j] = raw_mask->pattern[i]; 2964 } 2965 2966 next_dst_off += raw_spec->length; 2967 raw_id++; 2968 break; 2969 case RTE_FLOW_ITEM_TYPE_VF: 2970 vf_spec = item->spec; 2971 if (!attr->transfer) { 2972 rte_flow_error_set(error, ENOTSUP, 2973 RTE_FLOW_ERROR_TYPE_ITEM, 2974 item, 2975 "Matching VF traffic" 2976 " without affecting it" 2977 " (transfer attribute)" 2978 " is unsupported"); 2979 return -rte_errno; 2980 } 2981 filter->input.flow_ext.is_vf = 1; 2982 filter->input.flow_ext.dst_id = vf_spec->id; 2983 if (filter->input.flow_ext.is_vf && 2984 filter->input.flow_ext.dst_id >= pf->vf_num) { 2985 rte_flow_error_set(error, EINVAL, 2986 RTE_FLOW_ERROR_TYPE_ITEM, 2987 item, 2988 "Invalid VF ID for FDIR."); 2989 return -rte_errno; 2990 } 2991 break; 2992 default: 2993 break; 2994 } 2995 } 2996 2997 /* Get customized pctype value */ 2998 if (filter->input.flow_ext.customized_pctype) { 2999 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter); 3000 if (pctype == I40E_FILTER_PCTYPE_INVALID) { 3001 rte_flow_error_set(error, EINVAL, 3002 RTE_FLOW_ERROR_TYPE_ITEM, 3003 item, 3004 "Unsupported pctype"); 3005 return -rte_errno; 3006 } 3007 } 3008 3009 /* If customized pctype is not used, set fdir configuration.*/ 3010 if (!filter->input.flow_ext.customized_pctype) { 3011 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set); 3012 if (ret == -1) { 3013 rte_flow_error_set(error, EINVAL, 3014 RTE_FLOW_ERROR_TYPE_ITEM, item, 3015 "Conflict with the first rule's input set."); 3016 return -rte_errno; 3017 } else if (ret == -EINVAL) { 3018 rte_flow_error_set(error, EINVAL, 3019 RTE_FLOW_ERROR_TYPE_ITEM, item, 3020 "Invalid pattern mask."); 3021 return -rte_errno; 3022 } 3023 3024 /* Store flex mask to SW */ 3025 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask); 3026 if (ret == -1) { 3027 rte_flow_error_set(error, EINVAL, 3028 RTE_FLOW_ERROR_TYPE_ITEM, 3029 item, 3030 "Exceed maximal number of bitmasks"); 3031 return -rte_errno; 3032 } else if (ret == -2) { 3033 rte_flow_error_set(error, EINVAL, 3034 RTE_FLOW_ERROR_TYPE_ITEM, 3035 item, 3036 "Conflict with the first flexible rule"); 3037 return -rte_errno; 3038 } else if (ret > 0) 3039 cfg_flex_msk = false; 3040 3041 if (cfg_flex_pit) 3042 i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id); 3043 3044 if (cfg_flex_msk) 3045 i40e_flow_set_fdir_flex_msk(pf, pctype); 3046 } 3047 3048 filter->input.pctype = pctype; 3049 3050 return 0; 3051 } 3052 3053 /* Parse to get the action info of a FDIR filter. 3054 * FDIR action supports QUEUE or (QUEUE + MARK). 3055 */ 3056 static int 3057 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev, 3058 const struct rte_flow_action *actions, 3059 struct rte_flow_error *error, 3060 struct i40e_fdir_filter_conf *filter) 3061 { 3062 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3063 const struct rte_flow_action *act; 3064 const struct rte_flow_action_queue *act_q; 3065 const struct rte_flow_action_mark *mark_spec; 3066 uint32_t index = 0; 3067 3068 /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */ 3069 NEXT_ITEM_OF_ACTION(act, actions, index); 3070 switch (act->type) { 3071 case RTE_FLOW_ACTION_TYPE_QUEUE: 3072 act_q = act->conf; 3073 filter->action.rx_queue = act_q->index; 3074 if ((!filter->input.flow_ext.is_vf && 3075 filter->action.rx_queue >= pf->dev_data->nb_rx_queues) || 3076 (filter->input.flow_ext.is_vf && 3077 filter->action.rx_queue >= pf->vf_nb_qps)) { 3078 rte_flow_error_set(error, EINVAL, 3079 RTE_FLOW_ERROR_TYPE_ACTION, act, 3080 "Invalid queue ID for FDIR."); 3081 return -rte_errno; 3082 } 3083 filter->action.behavior = I40E_FDIR_ACCEPT; 3084 break; 3085 case RTE_FLOW_ACTION_TYPE_DROP: 3086 filter->action.behavior = I40E_FDIR_REJECT; 3087 break; 3088 case RTE_FLOW_ACTION_TYPE_PASSTHRU: 3089 filter->action.behavior = I40E_FDIR_PASSTHRU; 3090 break; 3091 default: 3092 rte_flow_error_set(error, EINVAL, 3093 RTE_FLOW_ERROR_TYPE_ACTION, act, 3094 "Invalid action."); 3095 return -rte_errno; 3096 } 3097 3098 /* Check if the next non-void item is MARK or FLAG or END. */ 3099 index++; 3100 NEXT_ITEM_OF_ACTION(act, actions, index); 3101 switch (act->type) { 3102 case RTE_FLOW_ACTION_TYPE_MARK: 3103 mark_spec = act->conf; 3104 filter->action.report_status = I40E_FDIR_REPORT_ID; 3105 filter->soft_id = mark_spec->id; 3106 break; 3107 case RTE_FLOW_ACTION_TYPE_FLAG: 3108 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS; 3109 break; 3110 case RTE_FLOW_ACTION_TYPE_END: 3111 return 0; 3112 default: 3113 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3114 act, "Invalid action."); 3115 return -rte_errno; 3116 } 3117 3118 /* Check if the next non-void item is END */ 3119 index++; 3120 NEXT_ITEM_OF_ACTION(act, actions, index); 3121 if (act->type != RTE_FLOW_ACTION_TYPE_END) { 3122 rte_flow_error_set(error, EINVAL, 3123 RTE_FLOW_ERROR_TYPE_ACTION, 3124 act, "Invalid action."); 3125 return -rte_errno; 3126 } 3127 3128 return 0; 3129 } 3130 3131 static int 3132 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev, 3133 const struct rte_flow_attr *attr, 3134 const struct rte_flow_item pattern[], 3135 const struct rte_flow_action actions[], 3136 struct rte_flow_error *error, 3137 union i40e_filter_t *filter) 3138 { 3139 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3140 struct i40e_fdir_filter_conf *fdir_filter = 3141 &filter->fdir_filter; 3142 int ret; 3143 3144 ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error, 3145 fdir_filter); 3146 if (ret) 3147 return ret; 3148 3149 ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter); 3150 if (ret) 3151 return ret; 3152 3153 ret = i40e_flow_parse_attr(attr, error); 3154 if (ret) 3155 return ret; 3156 3157 cons_filter_type = RTE_ETH_FILTER_FDIR; 3158 3159 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT || 3160 pf->fdir.fdir_vsi == NULL) { 3161 /* Enable fdir when fdir flow is added at first time. */ 3162 ret = i40e_fdir_setup(pf); 3163 if (ret != I40E_SUCCESS) { 3164 rte_flow_error_set(error, ENOTSUP, 3165 RTE_FLOW_ERROR_TYPE_HANDLE, 3166 NULL, "Failed to setup fdir."); 3167 return -rte_errno; 3168 } 3169 ret = i40e_fdir_configure(dev); 3170 if (ret < 0) { 3171 rte_flow_error_set(error, ENOTSUP, 3172 RTE_FLOW_ERROR_TYPE_HANDLE, 3173 NULL, "Failed to configure fdir."); 3174 goto err; 3175 } 3176 3177 dev->data->dev_conf.fdir_conf.mode = RTE_FDIR_MODE_PERFECT; 3178 } 3179 3180 return 0; 3181 err: 3182 i40e_fdir_teardown(pf); 3183 return -rte_errno; 3184 } 3185 3186 /* Parse to get the action info of a tunnel filter 3187 * Tunnel action only supports PF, VF and QUEUE. 3188 */ 3189 static int 3190 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev, 3191 const struct rte_flow_action *actions, 3192 struct rte_flow_error *error, 3193 struct i40e_tunnel_filter_conf *filter) 3194 { 3195 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3196 const struct rte_flow_action *act; 3197 const struct rte_flow_action_queue *act_q; 3198 const struct rte_flow_action_vf *act_vf; 3199 uint32_t index = 0; 3200 3201 /* Check if the first non-void action is PF or VF. */ 3202 NEXT_ITEM_OF_ACTION(act, actions, index); 3203 if (act->type != RTE_FLOW_ACTION_TYPE_PF && 3204 act->type != RTE_FLOW_ACTION_TYPE_VF) { 3205 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3206 act, "Not supported action."); 3207 return -rte_errno; 3208 } 3209 3210 if (act->type == RTE_FLOW_ACTION_TYPE_VF) { 3211 act_vf = act->conf; 3212 filter->vf_id = act_vf->id; 3213 filter->is_to_vf = 1; 3214 if (filter->vf_id >= pf->vf_num) { 3215 rte_flow_error_set(error, EINVAL, 3216 RTE_FLOW_ERROR_TYPE_ACTION, 3217 act, "Invalid VF ID for tunnel filter"); 3218 return -rte_errno; 3219 } 3220 } 3221 3222 /* Check if the next non-void item is QUEUE */ 3223 index++; 3224 NEXT_ITEM_OF_ACTION(act, actions, index); 3225 if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 3226 act_q = act->conf; 3227 filter->queue_id = act_q->index; 3228 if ((!filter->is_to_vf) && 3229 (filter->queue_id >= pf->dev_data->nb_rx_queues)) { 3230 rte_flow_error_set(error, EINVAL, 3231 RTE_FLOW_ERROR_TYPE_ACTION, 3232 act, "Invalid queue ID for tunnel filter"); 3233 return -rte_errno; 3234 } else if (filter->is_to_vf && 3235 (filter->queue_id >= pf->vf_nb_qps)) { 3236 rte_flow_error_set(error, EINVAL, 3237 RTE_FLOW_ERROR_TYPE_ACTION, 3238 act, "Invalid queue ID for tunnel filter"); 3239 return -rte_errno; 3240 } 3241 } 3242 3243 /* Check if the next non-void item is END */ 3244 index++; 3245 NEXT_ITEM_OF_ACTION(act, actions, index); 3246 if (act->type != RTE_FLOW_ACTION_TYPE_END) { 3247 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3248 act, "Not supported action."); 3249 return -rte_errno; 3250 } 3251 3252 return 0; 3253 } 3254 3255 static uint16_t i40e_supported_tunnel_filter_types[] = { 3256 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID | 3257 ETH_TUNNEL_FILTER_IVLAN, 3258 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN, 3259 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID, 3260 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID | 3261 ETH_TUNNEL_FILTER_IMAC, 3262 ETH_TUNNEL_FILTER_IMAC, 3263 }; 3264 3265 static int 3266 i40e_check_tunnel_filter_type(uint8_t filter_type) 3267 { 3268 uint8_t i; 3269 3270 for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) { 3271 if (filter_type == i40e_supported_tunnel_filter_types[i]) 3272 return 0; 3273 } 3274 3275 return -1; 3276 } 3277 3278 /* 1. Last in item should be NULL as range is not supported. 3279 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN, 3280 * IMAC_TENID, OMAC_TENID_IMAC and IMAC. 3281 * 3. Mask of fields which need to be matched should be 3282 * filled with 1. 3283 * 4. Mask of fields which needn't to be matched should be 3284 * filled with 0. 3285 */ 3286 static int 3287 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev, 3288 const struct rte_flow_item *pattern, 3289 struct rte_flow_error *error, 3290 struct i40e_tunnel_filter_conf *filter) 3291 { 3292 const struct rte_flow_item *item = pattern; 3293 const struct rte_flow_item_eth *eth_spec; 3294 const struct rte_flow_item_eth *eth_mask; 3295 const struct rte_flow_item_vxlan *vxlan_spec; 3296 const struct rte_flow_item_vxlan *vxlan_mask; 3297 const struct rte_flow_item_vlan *vlan_spec; 3298 const struct rte_flow_item_vlan *vlan_mask; 3299 uint8_t filter_type = 0; 3300 bool is_vni_masked = 0; 3301 uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF}; 3302 enum rte_flow_item_type item_type; 3303 bool vxlan_flag = 0; 3304 uint32_t tenant_id_be = 0; 3305 int ret; 3306 3307 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3308 if (item->last) { 3309 rte_flow_error_set(error, EINVAL, 3310 RTE_FLOW_ERROR_TYPE_ITEM, 3311 item, 3312 "Not support range"); 3313 return -rte_errno; 3314 } 3315 item_type = item->type; 3316 switch (item_type) { 3317 case RTE_FLOW_ITEM_TYPE_ETH: 3318 eth_spec = item->spec; 3319 eth_mask = item->mask; 3320 3321 /* Check if ETH item is used for place holder. 3322 * If yes, both spec and mask should be NULL. 3323 * If no, both spec and mask shouldn't be NULL. 3324 */ 3325 if ((!eth_spec && eth_mask) || 3326 (eth_spec && !eth_mask)) { 3327 rte_flow_error_set(error, EINVAL, 3328 RTE_FLOW_ERROR_TYPE_ITEM, 3329 item, 3330 "Invalid ether spec/mask"); 3331 return -rte_errno; 3332 } 3333 3334 if (eth_spec && eth_mask) { 3335 /* DST address of inner MAC shouldn't be masked. 3336 * SRC address of Inner MAC should be masked. 3337 */ 3338 if (!is_broadcast_ether_addr(ð_mask->dst) || 3339 !is_zero_ether_addr(ð_mask->src) || 3340 eth_mask->type) { 3341 rte_flow_error_set(error, EINVAL, 3342 RTE_FLOW_ERROR_TYPE_ITEM, 3343 item, 3344 "Invalid ether spec/mask"); 3345 return -rte_errno; 3346 } 3347 3348 if (!vxlan_flag) { 3349 rte_memcpy(&filter->outer_mac, 3350 ð_spec->dst, 3351 ETHER_ADDR_LEN); 3352 filter_type |= ETH_TUNNEL_FILTER_OMAC; 3353 } else { 3354 rte_memcpy(&filter->inner_mac, 3355 ð_spec->dst, 3356 ETHER_ADDR_LEN); 3357 filter_type |= ETH_TUNNEL_FILTER_IMAC; 3358 } 3359 } 3360 break; 3361 case RTE_FLOW_ITEM_TYPE_VLAN: 3362 vlan_spec = item->spec; 3363 vlan_mask = item->mask; 3364 if (!(vlan_spec && vlan_mask) || 3365 vlan_mask->inner_type) { 3366 rte_flow_error_set(error, EINVAL, 3367 RTE_FLOW_ERROR_TYPE_ITEM, 3368 item, 3369 "Invalid vlan item"); 3370 return -rte_errno; 3371 } 3372 3373 if (vlan_spec && vlan_mask) { 3374 if (vlan_mask->tci == 3375 rte_cpu_to_be_16(I40E_TCI_MASK)) 3376 filter->inner_vlan = 3377 rte_be_to_cpu_16(vlan_spec->tci) & 3378 I40E_TCI_MASK; 3379 filter_type |= ETH_TUNNEL_FILTER_IVLAN; 3380 } 3381 break; 3382 case RTE_FLOW_ITEM_TYPE_IPV4: 3383 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4; 3384 /* IPv4 is used to describe protocol, 3385 * spec and mask should be NULL. 3386 */ 3387 if (item->spec || item->mask) { 3388 rte_flow_error_set(error, EINVAL, 3389 RTE_FLOW_ERROR_TYPE_ITEM, 3390 item, 3391 "Invalid IPv4 item"); 3392 return -rte_errno; 3393 } 3394 break; 3395 case RTE_FLOW_ITEM_TYPE_IPV6: 3396 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6; 3397 /* IPv6 is used to describe protocol, 3398 * spec and mask should be NULL. 3399 */ 3400 if (item->spec || item->mask) { 3401 rte_flow_error_set(error, EINVAL, 3402 RTE_FLOW_ERROR_TYPE_ITEM, 3403 item, 3404 "Invalid IPv6 item"); 3405 return -rte_errno; 3406 } 3407 break; 3408 case RTE_FLOW_ITEM_TYPE_UDP: 3409 /* UDP is used to describe protocol, 3410 * spec and mask should be NULL. 3411 */ 3412 if (item->spec || item->mask) { 3413 rte_flow_error_set(error, EINVAL, 3414 RTE_FLOW_ERROR_TYPE_ITEM, 3415 item, 3416 "Invalid UDP item"); 3417 return -rte_errno; 3418 } 3419 break; 3420 case RTE_FLOW_ITEM_TYPE_VXLAN: 3421 vxlan_spec = item->spec; 3422 vxlan_mask = item->mask; 3423 /* Check if VXLAN item is used to describe protocol. 3424 * If yes, both spec and mask should be NULL. 3425 * If no, both spec and mask shouldn't be NULL. 3426 */ 3427 if ((!vxlan_spec && vxlan_mask) || 3428 (vxlan_spec && !vxlan_mask)) { 3429 rte_flow_error_set(error, EINVAL, 3430 RTE_FLOW_ERROR_TYPE_ITEM, 3431 item, 3432 "Invalid VXLAN item"); 3433 return -rte_errno; 3434 } 3435 3436 /* Check if VNI is masked. */ 3437 if (vxlan_spec && vxlan_mask) { 3438 is_vni_masked = 3439 !!memcmp(vxlan_mask->vni, vni_mask, 3440 RTE_DIM(vni_mask)); 3441 if (is_vni_masked) { 3442 rte_flow_error_set(error, EINVAL, 3443 RTE_FLOW_ERROR_TYPE_ITEM, 3444 item, 3445 "Invalid VNI mask"); 3446 return -rte_errno; 3447 } 3448 3449 rte_memcpy(((uint8_t *)&tenant_id_be + 1), 3450 vxlan_spec->vni, 3); 3451 filter->tenant_id = 3452 rte_be_to_cpu_32(tenant_id_be); 3453 filter_type |= ETH_TUNNEL_FILTER_TENID; 3454 } 3455 3456 vxlan_flag = 1; 3457 break; 3458 default: 3459 break; 3460 } 3461 } 3462 3463 ret = i40e_check_tunnel_filter_type(filter_type); 3464 if (ret < 0) { 3465 rte_flow_error_set(error, EINVAL, 3466 RTE_FLOW_ERROR_TYPE_ITEM, 3467 NULL, 3468 "Invalid filter type"); 3469 return -rte_errno; 3470 } 3471 filter->filter_type = filter_type; 3472 3473 filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN; 3474 3475 return 0; 3476 } 3477 3478 static int 3479 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev, 3480 const struct rte_flow_attr *attr, 3481 const struct rte_flow_item pattern[], 3482 const struct rte_flow_action actions[], 3483 struct rte_flow_error *error, 3484 union i40e_filter_t *filter) 3485 { 3486 struct i40e_tunnel_filter_conf *tunnel_filter = 3487 &filter->consistent_tunnel_filter; 3488 int ret; 3489 3490 ret = i40e_flow_parse_vxlan_pattern(dev, pattern, 3491 error, tunnel_filter); 3492 if (ret) 3493 return ret; 3494 3495 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 3496 if (ret) 3497 return ret; 3498 3499 ret = i40e_flow_parse_attr(attr, error); 3500 if (ret) 3501 return ret; 3502 3503 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 3504 3505 return ret; 3506 } 3507 3508 /* 1. Last in item should be NULL as range is not supported. 3509 * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN, 3510 * IMAC_TENID, OMAC_TENID_IMAC and IMAC. 3511 * 3. Mask of fields which need to be matched should be 3512 * filled with 1. 3513 * 4. Mask of fields which needn't to be matched should be 3514 * filled with 0. 3515 */ 3516 static int 3517 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev, 3518 const struct rte_flow_item *pattern, 3519 struct rte_flow_error *error, 3520 struct i40e_tunnel_filter_conf *filter) 3521 { 3522 const struct rte_flow_item *item = pattern; 3523 const struct rte_flow_item_eth *eth_spec; 3524 const struct rte_flow_item_eth *eth_mask; 3525 const struct rte_flow_item_nvgre *nvgre_spec; 3526 const struct rte_flow_item_nvgre *nvgre_mask; 3527 const struct rte_flow_item_vlan *vlan_spec; 3528 const struct rte_flow_item_vlan *vlan_mask; 3529 enum rte_flow_item_type item_type; 3530 uint8_t filter_type = 0; 3531 bool is_tni_masked = 0; 3532 uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF}; 3533 bool nvgre_flag = 0; 3534 uint32_t tenant_id_be = 0; 3535 int ret; 3536 3537 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3538 if (item->last) { 3539 rte_flow_error_set(error, EINVAL, 3540 RTE_FLOW_ERROR_TYPE_ITEM, 3541 item, 3542 "Not support range"); 3543 return -rte_errno; 3544 } 3545 item_type = item->type; 3546 switch (item_type) { 3547 case RTE_FLOW_ITEM_TYPE_ETH: 3548 eth_spec = item->spec; 3549 eth_mask = item->mask; 3550 3551 /* Check if ETH item is used for place holder. 3552 * If yes, both spec and mask should be NULL. 3553 * If no, both spec and mask shouldn't be NULL. 3554 */ 3555 if ((!eth_spec && eth_mask) || 3556 (eth_spec && !eth_mask)) { 3557 rte_flow_error_set(error, EINVAL, 3558 RTE_FLOW_ERROR_TYPE_ITEM, 3559 item, 3560 "Invalid ether spec/mask"); 3561 return -rte_errno; 3562 } 3563 3564 if (eth_spec && eth_mask) { 3565 /* DST address of inner MAC shouldn't be masked. 3566 * SRC address of Inner MAC should be masked. 3567 */ 3568 if (!is_broadcast_ether_addr(ð_mask->dst) || 3569 !is_zero_ether_addr(ð_mask->src) || 3570 eth_mask->type) { 3571 rte_flow_error_set(error, EINVAL, 3572 RTE_FLOW_ERROR_TYPE_ITEM, 3573 item, 3574 "Invalid ether spec/mask"); 3575 return -rte_errno; 3576 } 3577 3578 if (!nvgre_flag) { 3579 rte_memcpy(&filter->outer_mac, 3580 ð_spec->dst, 3581 ETHER_ADDR_LEN); 3582 filter_type |= ETH_TUNNEL_FILTER_OMAC; 3583 } else { 3584 rte_memcpy(&filter->inner_mac, 3585 ð_spec->dst, 3586 ETHER_ADDR_LEN); 3587 filter_type |= ETH_TUNNEL_FILTER_IMAC; 3588 } 3589 } 3590 3591 break; 3592 case RTE_FLOW_ITEM_TYPE_VLAN: 3593 vlan_spec = item->spec; 3594 vlan_mask = item->mask; 3595 if (!(vlan_spec && vlan_mask) || 3596 vlan_mask->inner_type) { 3597 rte_flow_error_set(error, EINVAL, 3598 RTE_FLOW_ERROR_TYPE_ITEM, 3599 item, 3600 "Invalid vlan item"); 3601 return -rte_errno; 3602 } 3603 3604 if (vlan_spec && vlan_mask) { 3605 if (vlan_mask->tci == 3606 rte_cpu_to_be_16(I40E_TCI_MASK)) 3607 filter->inner_vlan = 3608 rte_be_to_cpu_16(vlan_spec->tci) & 3609 I40E_TCI_MASK; 3610 filter_type |= ETH_TUNNEL_FILTER_IVLAN; 3611 } 3612 break; 3613 case RTE_FLOW_ITEM_TYPE_IPV4: 3614 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4; 3615 /* IPv4 is used to describe protocol, 3616 * spec and mask should be NULL. 3617 */ 3618 if (item->spec || item->mask) { 3619 rte_flow_error_set(error, EINVAL, 3620 RTE_FLOW_ERROR_TYPE_ITEM, 3621 item, 3622 "Invalid IPv4 item"); 3623 return -rte_errno; 3624 } 3625 break; 3626 case RTE_FLOW_ITEM_TYPE_IPV6: 3627 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6; 3628 /* IPv6 is used to describe protocol, 3629 * spec and mask should be NULL. 3630 */ 3631 if (item->spec || item->mask) { 3632 rte_flow_error_set(error, EINVAL, 3633 RTE_FLOW_ERROR_TYPE_ITEM, 3634 item, 3635 "Invalid IPv6 item"); 3636 return -rte_errno; 3637 } 3638 break; 3639 case RTE_FLOW_ITEM_TYPE_NVGRE: 3640 nvgre_spec = item->spec; 3641 nvgre_mask = item->mask; 3642 /* Check if NVGRE item is used to describe protocol. 3643 * If yes, both spec and mask should be NULL. 3644 * If no, both spec and mask shouldn't be NULL. 3645 */ 3646 if ((!nvgre_spec && nvgre_mask) || 3647 (nvgre_spec && !nvgre_mask)) { 3648 rte_flow_error_set(error, EINVAL, 3649 RTE_FLOW_ERROR_TYPE_ITEM, 3650 item, 3651 "Invalid NVGRE item"); 3652 return -rte_errno; 3653 } 3654 3655 if (nvgre_spec && nvgre_mask) { 3656 is_tni_masked = 3657 !!memcmp(nvgre_mask->tni, tni_mask, 3658 RTE_DIM(tni_mask)); 3659 if (is_tni_masked) { 3660 rte_flow_error_set(error, EINVAL, 3661 RTE_FLOW_ERROR_TYPE_ITEM, 3662 item, 3663 "Invalid TNI mask"); 3664 return -rte_errno; 3665 } 3666 if (nvgre_mask->protocol && 3667 nvgre_mask->protocol != 0xFFFF) { 3668 rte_flow_error_set(error, EINVAL, 3669 RTE_FLOW_ERROR_TYPE_ITEM, 3670 item, 3671 "Invalid NVGRE item"); 3672 return -rte_errno; 3673 } 3674 if (nvgre_mask->c_k_s_rsvd0_ver && 3675 nvgre_mask->c_k_s_rsvd0_ver != 3676 rte_cpu_to_be_16(0xFFFF)) { 3677 rte_flow_error_set(error, EINVAL, 3678 RTE_FLOW_ERROR_TYPE_ITEM, 3679 item, 3680 "Invalid NVGRE item"); 3681 return -rte_errno; 3682 } 3683 if (nvgre_spec->c_k_s_rsvd0_ver != 3684 rte_cpu_to_be_16(0x2000) && 3685 nvgre_mask->c_k_s_rsvd0_ver) { 3686 rte_flow_error_set(error, EINVAL, 3687 RTE_FLOW_ERROR_TYPE_ITEM, 3688 item, 3689 "Invalid NVGRE item"); 3690 return -rte_errno; 3691 } 3692 if (nvgre_mask->protocol && 3693 nvgre_spec->protocol != 3694 rte_cpu_to_be_16(0x6558)) { 3695 rte_flow_error_set(error, EINVAL, 3696 RTE_FLOW_ERROR_TYPE_ITEM, 3697 item, 3698 "Invalid NVGRE item"); 3699 return -rte_errno; 3700 } 3701 rte_memcpy(((uint8_t *)&tenant_id_be + 1), 3702 nvgre_spec->tni, 3); 3703 filter->tenant_id = 3704 rte_be_to_cpu_32(tenant_id_be); 3705 filter_type |= ETH_TUNNEL_FILTER_TENID; 3706 } 3707 3708 nvgre_flag = 1; 3709 break; 3710 default: 3711 break; 3712 } 3713 } 3714 3715 ret = i40e_check_tunnel_filter_type(filter_type); 3716 if (ret < 0) { 3717 rte_flow_error_set(error, EINVAL, 3718 RTE_FLOW_ERROR_TYPE_ITEM, 3719 NULL, 3720 "Invalid filter type"); 3721 return -rte_errno; 3722 } 3723 filter->filter_type = filter_type; 3724 3725 filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE; 3726 3727 return 0; 3728 } 3729 3730 static int 3731 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev, 3732 const struct rte_flow_attr *attr, 3733 const struct rte_flow_item pattern[], 3734 const struct rte_flow_action actions[], 3735 struct rte_flow_error *error, 3736 union i40e_filter_t *filter) 3737 { 3738 struct i40e_tunnel_filter_conf *tunnel_filter = 3739 &filter->consistent_tunnel_filter; 3740 int ret; 3741 3742 ret = i40e_flow_parse_nvgre_pattern(dev, pattern, 3743 error, tunnel_filter); 3744 if (ret) 3745 return ret; 3746 3747 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 3748 if (ret) 3749 return ret; 3750 3751 ret = i40e_flow_parse_attr(attr, error); 3752 if (ret) 3753 return ret; 3754 3755 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 3756 3757 return ret; 3758 } 3759 3760 /* 1. Last in item should be NULL as range is not supported. 3761 * 2. Supported filter types: MPLS label. 3762 * 3. Mask of fields which need to be matched should be 3763 * filled with 1. 3764 * 4. Mask of fields which needn't to be matched should be 3765 * filled with 0. 3766 */ 3767 static int 3768 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev, 3769 const struct rte_flow_item *pattern, 3770 struct rte_flow_error *error, 3771 struct i40e_tunnel_filter_conf *filter) 3772 { 3773 const struct rte_flow_item *item = pattern; 3774 const struct rte_flow_item_mpls *mpls_spec; 3775 const struct rte_flow_item_mpls *mpls_mask; 3776 enum rte_flow_item_type item_type; 3777 bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */ 3778 const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0}; 3779 uint32_t label_be = 0; 3780 3781 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3782 if (item->last) { 3783 rte_flow_error_set(error, EINVAL, 3784 RTE_FLOW_ERROR_TYPE_ITEM, 3785 item, 3786 "Not support range"); 3787 return -rte_errno; 3788 } 3789 item_type = item->type; 3790 switch (item_type) { 3791 case RTE_FLOW_ITEM_TYPE_ETH: 3792 if (item->spec || item->mask) { 3793 rte_flow_error_set(error, EINVAL, 3794 RTE_FLOW_ERROR_TYPE_ITEM, 3795 item, 3796 "Invalid ETH item"); 3797 return -rte_errno; 3798 } 3799 break; 3800 case RTE_FLOW_ITEM_TYPE_IPV4: 3801 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4; 3802 /* IPv4 is used to describe protocol, 3803 * spec and mask should be NULL. 3804 */ 3805 if (item->spec || item->mask) { 3806 rte_flow_error_set(error, EINVAL, 3807 RTE_FLOW_ERROR_TYPE_ITEM, 3808 item, 3809 "Invalid IPv4 item"); 3810 return -rte_errno; 3811 } 3812 break; 3813 case RTE_FLOW_ITEM_TYPE_IPV6: 3814 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6; 3815 /* IPv6 is used to describe protocol, 3816 * spec and mask should be NULL. 3817 */ 3818 if (item->spec || item->mask) { 3819 rte_flow_error_set(error, EINVAL, 3820 RTE_FLOW_ERROR_TYPE_ITEM, 3821 item, 3822 "Invalid IPv6 item"); 3823 return -rte_errno; 3824 } 3825 break; 3826 case RTE_FLOW_ITEM_TYPE_UDP: 3827 /* UDP is used to describe protocol, 3828 * spec and mask should be NULL. 3829 */ 3830 if (item->spec || item->mask) { 3831 rte_flow_error_set(error, EINVAL, 3832 RTE_FLOW_ERROR_TYPE_ITEM, 3833 item, 3834 "Invalid UDP item"); 3835 return -rte_errno; 3836 } 3837 is_mplsoudp = 1; 3838 break; 3839 case RTE_FLOW_ITEM_TYPE_GRE: 3840 /* GRE is used to describe protocol, 3841 * spec and mask should be NULL. 3842 */ 3843 if (item->spec || item->mask) { 3844 rte_flow_error_set(error, EINVAL, 3845 RTE_FLOW_ERROR_TYPE_ITEM, 3846 item, 3847 "Invalid GRE item"); 3848 return -rte_errno; 3849 } 3850 break; 3851 case RTE_FLOW_ITEM_TYPE_MPLS: 3852 mpls_spec = item->spec; 3853 mpls_mask = item->mask; 3854 3855 if (!mpls_spec || !mpls_mask) { 3856 rte_flow_error_set(error, EINVAL, 3857 RTE_FLOW_ERROR_TYPE_ITEM, 3858 item, 3859 "Invalid MPLS item"); 3860 return -rte_errno; 3861 } 3862 3863 if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) { 3864 rte_flow_error_set(error, EINVAL, 3865 RTE_FLOW_ERROR_TYPE_ITEM, 3866 item, 3867 "Invalid MPLS label mask"); 3868 return -rte_errno; 3869 } 3870 rte_memcpy(((uint8_t *)&label_be + 1), 3871 mpls_spec->label_tc_s, 3); 3872 filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4; 3873 break; 3874 default: 3875 break; 3876 } 3877 } 3878 3879 if (is_mplsoudp) 3880 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP; 3881 else 3882 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE; 3883 3884 return 0; 3885 } 3886 3887 static int 3888 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev, 3889 const struct rte_flow_attr *attr, 3890 const struct rte_flow_item pattern[], 3891 const struct rte_flow_action actions[], 3892 struct rte_flow_error *error, 3893 union i40e_filter_t *filter) 3894 { 3895 struct i40e_tunnel_filter_conf *tunnel_filter = 3896 &filter->consistent_tunnel_filter; 3897 int ret; 3898 3899 ret = i40e_flow_parse_mpls_pattern(dev, pattern, 3900 error, tunnel_filter); 3901 if (ret) 3902 return ret; 3903 3904 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 3905 if (ret) 3906 return ret; 3907 3908 ret = i40e_flow_parse_attr(attr, error); 3909 if (ret) 3910 return ret; 3911 3912 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 3913 3914 return ret; 3915 } 3916 3917 /* 1. Last in item should be NULL as range is not supported. 3918 * 2. Supported filter types: GTP TEID. 3919 * 3. Mask of fields which need to be matched should be 3920 * filled with 1. 3921 * 4. Mask of fields which needn't to be matched should be 3922 * filled with 0. 3923 * 5. GTP profile supports GTPv1 only. 3924 * 6. GTP-C response message ('source_port' = 2123) is not supported. 3925 */ 3926 static int 3927 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev, 3928 const struct rte_flow_item *pattern, 3929 struct rte_flow_error *error, 3930 struct i40e_tunnel_filter_conf *filter) 3931 { 3932 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 3933 const struct rte_flow_item *item = pattern; 3934 const struct rte_flow_item_gtp *gtp_spec; 3935 const struct rte_flow_item_gtp *gtp_mask; 3936 enum rte_flow_item_type item_type; 3937 3938 if (!pf->gtp_support) { 3939 rte_flow_error_set(error, EINVAL, 3940 RTE_FLOW_ERROR_TYPE_ITEM, 3941 item, 3942 "GTP is not supported by default."); 3943 return -rte_errno; 3944 } 3945 3946 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3947 if (item->last) { 3948 rte_flow_error_set(error, EINVAL, 3949 RTE_FLOW_ERROR_TYPE_ITEM, 3950 item, 3951 "Not support range"); 3952 return -rte_errno; 3953 } 3954 item_type = item->type; 3955 switch (item_type) { 3956 case RTE_FLOW_ITEM_TYPE_ETH: 3957 if (item->spec || item->mask) { 3958 rte_flow_error_set(error, EINVAL, 3959 RTE_FLOW_ERROR_TYPE_ITEM, 3960 item, 3961 "Invalid ETH item"); 3962 return -rte_errno; 3963 } 3964 break; 3965 case RTE_FLOW_ITEM_TYPE_IPV4: 3966 filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4; 3967 /* IPv4 is used to describe protocol, 3968 * spec and mask should be NULL. 3969 */ 3970 if (item->spec || item->mask) { 3971 rte_flow_error_set(error, EINVAL, 3972 RTE_FLOW_ERROR_TYPE_ITEM, 3973 item, 3974 "Invalid IPv4 item"); 3975 return -rte_errno; 3976 } 3977 break; 3978 case RTE_FLOW_ITEM_TYPE_UDP: 3979 if (item->spec || item->mask) { 3980 rte_flow_error_set(error, EINVAL, 3981 RTE_FLOW_ERROR_TYPE_ITEM, 3982 item, 3983 "Invalid UDP item"); 3984 return -rte_errno; 3985 } 3986 break; 3987 case RTE_FLOW_ITEM_TYPE_GTPC: 3988 case RTE_FLOW_ITEM_TYPE_GTPU: 3989 gtp_spec = item->spec; 3990 gtp_mask = item->mask; 3991 3992 if (!gtp_spec || !gtp_mask) { 3993 rte_flow_error_set(error, EINVAL, 3994 RTE_FLOW_ERROR_TYPE_ITEM, 3995 item, 3996 "Invalid GTP item"); 3997 return -rte_errno; 3998 } 3999 4000 if (gtp_mask->v_pt_rsv_flags || 4001 gtp_mask->msg_type || 4002 gtp_mask->msg_len || 4003 gtp_mask->teid != UINT32_MAX) { 4004 rte_flow_error_set(error, EINVAL, 4005 RTE_FLOW_ERROR_TYPE_ITEM, 4006 item, 4007 "Invalid GTP mask"); 4008 return -rte_errno; 4009 } 4010 4011 if (item_type == RTE_FLOW_ITEM_TYPE_GTPC) 4012 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC; 4013 else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU) 4014 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU; 4015 4016 filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid); 4017 4018 break; 4019 default: 4020 break; 4021 } 4022 } 4023 4024 return 0; 4025 } 4026 4027 static int 4028 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev, 4029 const struct rte_flow_attr *attr, 4030 const struct rte_flow_item pattern[], 4031 const struct rte_flow_action actions[], 4032 struct rte_flow_error *error, 4033 union i40e_filter_t *filter) 4034 { 4035 struct i40e_tunnel_filter_conf *tunnel_filter = 4036 &filter->consistent_tunnel_filter; 4037 int ret; 4038 4039 ret = i40e_flow_parse_gtp_pattern(dev, pattern, 4040 error, tunnel_filter); 4041 if (ret) 4042 return ret; 4043 4044 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 4045 if (ret) 4046 return ret; 4047 4048 ret = i40e_flow_parse_attr(attr, error); 4049 if (ret) 4050 return ret; 4051 4052 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 4053 4054 return ret; 4055 } 4056 4057 /* 1. Last in item should be NULL as range is not supported. 4058 * 2. Supported filter types: QINQ. 4059 * 3. Mask of fields which need to be matched should be 4060 * filled with 1. 4061 * 4. Mask of fields which needn't to be matched should be 4062 * filled with 0. 4063 */ 4064 static int 4065 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev, 4066 const struct rte_flow_item *pattern, 4067 struct rte_flow_error *error, 4068 struct i40e_tunnel_filter_conf *filter) 4069 { 4070 const struct rte_flow_item *item = pattern; 4071 const struct rte_flow_item_vlan *vlan_spec = NULL; 4072 const struct rte_flow_item_vlan *vlan_mask = NULL; 4073 const struct rte_flow_item_vlan *i_vlan_spec = NULL; 4074 const struct rte_flow_item_vlan *i_vlan_mask = NULL; 4075 const struct rte_flow_item_vlan *o_vlan_spec = NULL; 4076 const struct rte_flow_item_vlan *o_vlan_mask = NULL; 4077 4078 enum rte_flow_item_type item_type; 4079 bool vlan_flag = 0; 4080 4081 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 4082 if (item->last) { 4083 rte_flow_error_set(error, EINVAL, 4084 RTE_FLOW_ERROR_TYPE_ITEM, 4085 item, 4086 "Not support range"); 4087 return -rte_errno; 4088 } 4089 item_type = item->type; 4090 switch (item_type) { 4091 case RTE_FLOW_ITEM_TYPE_ETH: 4092 if (item->spec || item->mask) { 4093 rte_flow_error_set(error, EINVAL, 4094 RTE_FLOW_ERROR_TYPE_ITEM, 4095 item, 4096 "Invalid ETH item"); 4097 return -rte_errno; 4098 } 4099 break; 4100 case RTE_FLOW_ITEM_TYPE_VLAN: 4101 vlan_spec = item->spec; 4102 vlan_mask = item->mask; 4103 4104 if (!(vlan_spec && vlan_mask) || 4105 vlan_mask->inner_type) { 4106 rte_flow_error_set(error, EINVAL, 4107 RTE_FLOW_ERROR_TYPE_ITEM, 4108 item, 4109 "Invalid vlan item"); 4110 return -rte_errno; 4111 } 4112 4113 if (!vlan_flag) { 4114 o_vlan_spec = vlan_spec; 4115 o_vlan_mask = vlan_mask; 4116 vlan_flag = 1; 4117 } else { 4118 i_vlan_spec = vlan_spec; 4119 i_vlan_mask = vlan_mask; 4120 vlan_flag = 0; 4121 } 4122 break; 4123 4124 default: 4125 break; 4126 } 4127 } 4128 4129 /* Get filter specification */ 4130 if ((o_vlan_mask != NULL) && (o_vlan_mask->tci == 4131 rte_cpu_to_be_16(I40E_TCI_MASK)) && 4132 (i_vlan_mask != NULL) && 4133 (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) { 4134 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci) 4135 & I40E_TCI_MASK; 4136 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci) 4137 & I40E_TCI_MASK; 4138 } else { 4139 rte_flow_error_set(error, EINVAL, 4140 RTE_FLOW_ERROR_TYPE_ITEM, 4141 NULL, 4142 "Invalid filter type"); 4143 return -rte_errno; 4144 } 4145 4146 filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ; 4147 return 0; 4148 } 4149 4150 static int 4151 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev, 4152 const struct rte_flow_attr *attr, 4153 const struct rte_flow_item pattern[], 4154 const struct rte_flow_action actions[], 4155 struct rte_flow_error *error, 4156 union i40e_filter_t *filter) 4157 { 4158 struct i40e_tunnel_filter_conf *tunnel_filter = 4159 &filter->consistent_tunnel_filter; 4160 int ret; 4161 4162 ret = i40e_flow_parse_qinq_pattern(dev, pattern, 4163 error, tunnel_filter); 4164 if (ret) 4165 return ret; 4166 4167 ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter); 4168 if (ret) 4169 return ret; 4170 4171 ret = i40e_flow_parse_attr(attr, error); 4172 if (ret) 4173 return ret; 4174 4175 cons_filter_type = RTE_ETH_FILTER_TUNNEL; 4176 4177 return ret; 4178 } 4179 4180 /** 4181 * This function is used to do configuration i40e existing RSS with rte_flow. 4182 * It also enable queue region configuration using flow API for i40e. 4183 * pattern can be used indicate what parameters will be include in flow, 4184 * like user_priority or flowtype for queue region or HASH function for RSS. 4185 * Action is used to transmit parameter like queue index and HASH 4186 * function for RSS, or flowtype for queue region configuration. 4187 * For example: 4188 * pattern: 4189 * Case 1: only ETH, indicate flowtype for queue region will be parsed. 4190 * Case 2: only VLAN, indicate user_priority for queue region will be parsed. 4191 * Case 3: none, indicate RSS related will be parsed in action. 4192 * Any pattern other the ETH or VLAN will be treated as invalid except END. 4193 * So, pattern choice is depened on the purpose of configuration of 4194 * that flow. 4195 * action: 4196 * action RSS will be uaed to transmit valid parameter with 4197 * struct rte_flow_action_rss for all the 3 case. 4198 */ 4199 static int 4200 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev, 4201 const struct rte_flow_item *pattern, 4202 struct rte_flow_error *error, 4203 uint8_t *action_flag, 4204 struct i40e_queue_regions *info) 4205 { 4206 const struct rte_flow_item_vlan *vlan_spec, *vlan_mask; 4207 const struct rte_flow_item *item = pattern; 4208 enum rte_flow_item_type item_type; 4209 4210 if (item->type == RTE_FLOW_ITEM_TYPE_END) 4211 return 0; 4212 4213 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 4214 if (item->last) { 4215 rte_flow_error_set(error, EINVAL, 4216 RTE_FLOW_ERROR_TYPE_ITEM, 4217 item, 4218 "Not support range"); 4219 return -rte_errno; 4220 } 4221 item_type = item->type; 4222 switch (item_type) { 4223 case RTE_FLOW_ITEM_TYPE_ETH: 4224 *action_flag = 1; 4225 break; 4226 case RTE_FLOW_ITEM_TYPE_VLAN: 4227 vlan_spec = item->spec; 4228 vlan_mask = item->mask; 4229 if (vlan_spec && vlan_mask) { 4230 if (vlan_mask->tci == 4231 rte_cpu_to_be_16(I40E_TCI_MASK)) { 4232 info->region[0].user_priority[0] = 4233 (rte_be_to_cpu_16( 4234 vlan_spec->tci) >> 13) & 0x7; 4235 info->region[0].user_priority_num = 1; 4236 info->queue_region_number = 1; 4237 *action_flag = 0; 4238 } 4239 } 4240 break; 4241 default: 4242 rte_flow_error_set(error, EINVAL, 4243 RTE_FLOW_ERROR_TYPE_ITEM, 4244 item, 4245 "Not support range"); 4246 return -rte_errno; 4247 } 4248 } 4249 4250 return 0; 4251 } 4252 4253 /** 4254 * This function is used to parse rss queue index, total queue number and 4255 * hash functions, If the purpose of this configuration is for queue region 4256 * configuration, it will set queue_region_conf flag to TRUE, else to FALSE. 4257 * In queue region configuration, it also need to parse hardware flowtype 4258 * and user_priority from configuration, it will also cheeck the validity 4259 * of these parameters. For example, The queue region sizes should 4260 * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the 4261 * hw_flowtype or PCTYPE max index should be 63, the user priority 4262 * max index should be 7, and so on. And also, queue index should be 4263 * continuous sequence and queue region index should be part of rss 4264 * queue index for this port. 4265 */ 4266 static int 4267 i40e_flow_parse_rss_action(struct rte_eth_dev *dev, 4268 const struct rte_flow_action *actions, 4269 struct rte_flow_error *error, 4270 uint8_t action_flag, 4271 struct i40e_queue_regions *conf_info, 4272 union i40e_filter_t *filter) 4273 { 4274 const struct rte_flow_action *act; 4275 const struct rte_flow_action_rss *rss; 4276 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4277 struct i40e_queue_regions *info = &pf->queue_region; 4278 struct i40e_rte_flow_rss_conf *rss_config = 4279 &filter->rss_conf; 4280 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info; 4281 uint16_t i, j, n, tmp; 4282 uint32_t index = 0; 4283 uint64_t hf_bit = 1; 4284 4285 NEXT_ITEM_OF_ACTION(act, actions, index); 4286 rss = act->conf; 4287 4288 /** 4289 * rss only supports forwarding, 4290 * check if the first not void action is RSS. 4291 */ 4292 if (act->type != RTE_FLOW_ACTION_TYPE_RSS) { 4293 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf)); 4294 rte_flow_error_set(error, EINVAL, 4295 RTE_FLOW_ERROR_TYPE_ACTION, 4296 act, "Not supported action."); 4297 return -rte_errno; 4298 } 4299 4300 if (action_flag) { 4301 for (n = 0; n < 64; n++) { 4302 if (rss->types & (hf_bit << n)) { 4303 conf_info->region[0].hw_flowtype[0] = n; 4304 conf_info->region[0].flowtype_num = 1; 4305 conf_info->queue_region_number = 1; 4306 break; 4307 } 4308 } 4309 } 4310 4311 /** 4312 * Do some queue region related parameters check 4313 * in order to keep queue index for queue region to be 4314 * continuous sequence and also to be part of RSS 4315 * queue index for this port. 4316 */ 4317 if (conf_info->queue_region_number) { 4318 for (i = 0; i < rss->queue_num; i++) { 4319 for (j = 0; j < rss_info->conf.queue_num; j++) { 4320 if (rss->queue[i] == rss_info->conf.queue[j]) 4321 break; 4322 } 4323 if (j == rss_info->conf.queue_num) { 4324 rte_flow_error_set(error, EINVAL, 4325 RTE_FLOW_ERROR_TYPE_ACTION, 4326 act, 4327 "no valid queues"); 4328 return -rte_errno; 4329 } 4330 } 4331 4332 for (i = 0; i < rss->queue_num - 1; i++) { 4333 if (rss->queue[i + 1] != rss->queue[i] + 1) { 4334 rte_flow_error_set(error, EINVAL, 4335 RTE_FLOW_ERROR_TYPE_ACTION, 4336 act, 4337 "no valid queues"); 4338 return -rte_errno; 4339 } 4340 } 4341 } 4342 4343 /* Parse queue region related parameters from configuration */ 4344 for (n = 0; n < conf_info->queue_region_number; n++) { 4345 if (conf_info->region[n].user_priority_num || 4346 conf_info->region[n].flowtype_num) { 4347 if (!((rte_is_power_of_2(rss->queue_num)) && 4348 rss->queue_num <= 64)) { 4349 rte_flow_error_set(error, EINVAL, 4350 RTE_FLOW_ERROR_TYPE_ACTION, 4351 act, 4352 "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the " 4353 "total number of queues do not exceed the VSI allocation"); 4354 return -rte_errno; 4355 } 4356 4357 if (conf_info->region[n].user_priority[n] >= 4358 I40E_MAX_USER_PRIORITY) { 4359 rte_flow_error_set(error, EINVAL, 4360 RTE_FLOW_ERROR_TYPE_ACTION, 4361 act, 4362 "the user priority max index is 7"); 4363 return -rte_errno; 4364 } 4365 4366 if (conf_info->region[n].hw_flowtype[n] >= 4367 I40E_FILTER_PCTYPE_MAX) { 4368 rte_flow_error_set(error, EINVAL, 4369 RTE_FLOW_ERROR_TYPE_ACTION, 4370 act, 4371 "the hw_flowtype or PCTYPE max index is 63"); 4372 return -rte_errno; 4373 } 4374 4375 for (i = 0; i < info->queue_region_number; i++) { 4376 if (info->region[i].queue_num == 4377 rss->queue_num && 4378 info->region[i].queue_start_index == 4379 rss->queue[0]) 4380 break; 4381 } 4382 4383 if (i == info->queue_region_number) { 4384 if (i > I40E_REGION_MAX_INDEX) { 4385 rte_flow_error_set(error, EINVAL, 4386 RTE_FLOW_ERROR_TYPE_ACTION, 4387 act, 4388 "the queue region max index is 7"); 4389 return -rte_errno; 4390 } 4391 4392 info->region[i].queue_num = 4393 rss->queue_num; 4394 info->region[i].queue_start_index = 4395 rss->queue[0]; 4396 info->region[i].region_id = 4397 info->queue_region_number; 4398 4399 j = info->region[i].user_priority_num; 4400 tmp = conf_info->region[n].user_priority[0]; 4401 if (conf_info->region[n].user_priority_num) { 4402 info->region[i].user_priority[j] = tmp; 4403 info->region[i].user_priority_num++; 4404 } 4405 4406 j = info->region[i].flowtype_num; 4407 tmp = conf_info->region[n].hw_flowtype[0]; 4408 if (conf_info->region[n].flowtype_num) { 4409 info->region[i].hw_flowtype[j] = tmp; 4410 info->region[i].flowtype_num++; 4411 } 4412 info->queue_region_number++; 4413 } else { 4414 j = info->region[i].user_priority_num; 4415 tmp = conf_info->region[n].user_priority[0]; 4416 if (conf_info->region[n].user_priority_num) { 4417 info->region[i].user_priority[j] = tmp; 4418 info->region[i].user_priority_num++; 4419 } 4420 4421 j = info->region[i].flowtype_num; 4422 tmp = conf_info->region[n].hw_flowtype[0]; 4423 if (conf_info->region[n].flowtype_num) { 4424 info->region[i].hw_flowtype[j] = tmp; 4425 info->region[i].flowtype_num++; 4426 } 4427 } 4428 } 4429 4430 rss_config->queue_region_conf = TRUE; 4431 } 4432 4433 /** 4434 * Return function if this flow is used for queue region configuration 4435 */ 4436 if (rss_config->queue_region_conf) 4437 return 0; 4438 4439 if (!rss || !rss->queue_num) { 4440 rte_flow_error_set(error, EINVAL, 4441 RTE_FLOW_ERROR_TYPE_ACTION, 4442 act, 4443 "no valid queues"); 4444 return -rte_errno; 4445 } 4446 4447 for (n = 0; n < rss->queue_num; n++) { 4448 if (rss->queue[n] >= dev->data->nb_rx_queues) { 4449 rte_flow_error_set(error, EINVAL, 4450 RTE_FLOW_ERROR_TYPE_ACTION, 4451 act, 4452 "queue id > max number of queues"); 4453 return -rte_errno; 4454 } 4455 } 4456 4457 if (rss_info->conf.queue_num) { 4458 rte_flow_error_set(error, EINVAL, 4459 RTE_FLOW_ERROR_TYPE_ACTION, 4460 act, 4461 "rss only allow one valid rule"); 4462 return -rte_errno; 4463 } 4464 4465 /* Parse RSS related parameters from configuration */ 4466 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT) 4467 return rte_flow_error_set 4468 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act, 4469 "non-default RSS hash functions are not supported"); 4470 if (rss->level) 4471 return rte_flow_error_set 4472 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act, 4473 "a nonzero RSS encapsulation level is not supported"); 4474 if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key)) 4475 return rte_flow_error_set 4476 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act, 4477 "RSS hash key too large"); 4478 if (rss->queue_num > RTE_DIM(rss_config->queue)) 4479 return rte_flow_error_set 4480 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act, 4481 "too many queues for RSS context"); 4482 if (i40e_rss_conf_init(rss_config, rss)) 4483 return rte_flow_error_set 4484 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act, 4485 "RSS context initialization failure"); 4486 4487 index++; 4488 4489 /* check if the next not void action is END */ 4490 NEXT_ITEM_OF_ACTION(act, actions, index); 4491 if (act->type != RTE_FLOW_ACTION_TYPE_END) { 4492 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf)); 4493 rte_flow_error_set(error, EINVAL, 4494 RTE_FLOW_ERROR_TYPE_ACTION, 4495 act, "Not supported action."); 4496 return -rte_errno; 4497 } 4498 rss_config->queue_region_conf = FALSE; 4499 4500 return 0; 4501 } 4502 4503 static int 4504 i40e_parse_rss_filter(struct rte_eth_dev *dev, 4505 const struct rte_flow_attr *attr, 4506 const struct rte_flow_item pattern[], 4507 const struct rte_flow_action actions[], 4508 union i40e_filter_t *filter, 4509 struct rte_flow_error *error) 4510 { 4511 int ret; 4512 struct i40e_queue_regions info; 4513 uint8_t action_flag = 0; 4514 4515 memset(&info, 0, sizeof(struct i40e_queue_regions)); 4516 4517 ret = i40e_flow_parse_rss_pattern(dev, pattern, 4518 error, &action_flag, &info); 4519 if (ret) 4520 return ret; 4521 4522 ret = i40e_flow_parse_rss_action(dev, actions, error, 4523 action_flag, &info, filter); 4524 if (ret) 4525 return ret; 4526 4527 ret = i40e_flow_parse_attr(attr, error); 4528 if (ret) 4529 return ret; 4530 4531 cons_filter_type = RTE_ETH_FILTER_HASH; 4532 4533 return 0; 4534 } 4535 4536 static int 4537 i40e_config_rss_filter_set(struct rte_eth_dev *dev, 4538 struct i40e_rte_flow_rss_conf *conf) 4539 { 4540 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4541 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4542 int ret; 4543 4544 if (conf->queue_region_conf) { 4545 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1); 4546 conf->queue_region_conf = 0; 4547 } else { 4548 ret = i40e_config_rss_filter(pf, conf, 1); 4549 } 4550 return ret; 4551 } 4552 4553 static int 4554 i40e_config_rss_filter_del(struct rte_eth_dev *dev, 4555 struct i40e_rte_flow_rss_conf *conf) 4556 { 4557 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4558 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4559 4560 i40e_flush_queue_region_all_conf(dev, hw, pf, 0); 4561 4562 i40e_config_rss_filter(pf, conf, 0); 4563 return 0; 4564 } 4565 4566 static int 4567 i40e_flow_validate(struct rte_eth_dev *dev, 4568 const struct rte_flow_attr *attr, 4569 const struct rte_flow_item pattern[], 4570 const struct rte_flow_action actions[], 4571 struct rte_flow_error *error) 4572 { 4573 struct rte_flow_item *items; /* internal pattern w/o VOID items */ 4574 parse_filter_t parse_filter; 4575 uint32_t item_num = 0; /* non-void item number of pattern*/ 4576 uint32_t i = 0; 4577 bool flag = false; 4578 int ret = I40E_NOT_SUPPORTED; 4579 4580 if (!pattern) { 4581 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM, 4582 NULL, "NULL pattern."); 4583 return -rte_errno; 4584 } 4585 4586 if (!actions) { 4587 rte_flow_error_set(error, EINVAL, 4588 RTE_FLOW_ERROR_TYPE_ACTION_NUM, 4589 NULL, "NULL action."); 4590 return -rte_errno; 4591 } 4592 4593 if (!attr) { 4594 rte_flow_error_set(error, EINVAL, 4595 RTE_FLOW_ERROR_TYPE_ATTR, 4596 NULL, "NULL attribute."); 4597 return -rte_errno; 4598 } 4599 4600 memset(&cons_filter, 0, sizeof(cons_filter)); 4601 4602 /* Get the non-void item of action */ 4603 while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID) 4604 i++; 4605 4606 if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) { 4607 ret = i40e_parse_rss_filter(dev, attr, pattern, 4608 actions, &cons_filter, error); 4609 return ret; 4610 } 4611 4612 i = 0; 4613 /* Get the non-void item number of pattern */ 4614 while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) { 4615 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID) 4616 item_num++; 4617 i++; 4618 } 4619 item_num++; 4620 4621 items = rte_zmalloc("i40e_pattern", 4622 item_num * sizeof(struct rte_flow_item), 0); 4623 if (!items) { 4624 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM, 4625 NULL, "No memory for PMD internal items."); 4626 return -ENOMEM; 4627 } 4628 4629 i40e_pattern_skip_void_item(items, pattern); 4630 4631 i = 0; 4632 do { 4633 parse_filter = i40e_find_parse_filter_func(items, &i); 4634 if (!parse_filter && !flag) { 4635 rte_flow_error_set(error, EINVAL, 4636 RTE_FLOW_ERROR_TYPE_ITEM, 4637 pattern, "Unsupported pattern"); 4638 rte_free(items); 4639 return -rte_errno; 4640 } 4641 if (parse_filter) 4642 ret = parse_filter(dev, attr, items, actions, 4643 error, &cons_filter); 4644 flag = true; 4645 } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns))); 4646 4647 rte_free(items); 4648 4649 return ret; 4650 } 4651 4652 static struct rte_flow * 4653 i40e_flow_create(struct rte_eth_dev *dev, 4654 const struct rte_flow_attr *attr, 4655 const struct rte_flow_item pattern[], 4656 const struct rte_flow_action actions[], 4657 struct rte_flow_error *error) 4658 { 4659 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4660 struct rte_flow *flow; 4661 int ret; 4662 4663 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0); 4664 if (!flow) { 4665 rte_flow_error_set(error, ENOMEM, 4666 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4667 "Failed to allocate memory"); 4668 return flow; 4669 } 4670 4671 ret = i40e_flow_validate(dev, attr, pattern, actions, error); 4672 if (ret < 0) 4673 return NULL; 4674 4675 switch (cons_filter_type) { 4676 case RTE_ETH_FILTER_ETHERTYPE: 4677 ret = i40e_ethertype_filter_set(pf, 4678 &cons_filter.ethertype_filter, 1); 4679 if (ret) 4680 goto free_flow; 4681 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list, 4682 i40e_ethertype_filter_list); 4683 break; 4684 case RTE_ETH_FILTER_FDIR: 4685 ret = i40e_flow_add_del_fdir_filter(dev, 4686 &cons_filter.fdir_filter, 1); 4687 if (ret) 4688 goto free_flow; 4689 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list, 4690 i40e_fdir_filter_list); 4691 break; 4692 case RTE_ETH_FILTER_TUNNEL: 4693 ret = i40e_dev_consistent_tunnel_filter_set(pf, 4694 &cons_filter.consistent_tunnel_filter, 1); 4695 if (ret) 4696 goto free_flow; 4697 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list, 4698 i40e_tunnel_filter_list); 4699 break; 4700 case RTE_ETH_FILTER_HASH: 4701 ret = i40e_config_rss_filter_set(dev, 4702 &cons_filter.rss_conf); 4703 if (ret) 4704 goto free_flow; 4705 flow->rule = &pf->rss_info; 4706 break; 4707 default: 4708 goto free_flow; 4709 } 4710 4711 flow->filter_type = cons_filter_type; 4712 TAILQ_INSERT_TAIL(&pf->flow_list, flow, node); 4713 return flow; 4714 4715 free_flow: 4716 rte_flow_error_set(error, -ret, 4717 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4718 "Failed to create flow."); 4719 rte_free(flow); 4720 return NULL; 4721 } 4722 4723 static int 4724 i40e_flow_destroy(struct rte_eth_dev *dev, 4725 struct rte_flow *flow, 4726 struct rte_flow_error *error) 4727 { 4728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4729 enum rte_filter_type filter_type = flow->filter_type; 4730 int ret = 0; 4731 4732 switch (filter_type) { 4733 case RTE_ETH_FILTER_ETHERTYPE: 4734 ret = i40e_flow_destroy_ethertype_filter(pf, 4735 (struct i40e_ethertype_filter *)flow->rule); 4736 break; 4737 case RTE_ETH_FILTER_TUNNEL: 4738 ret = i40e_flow_destroy_tunnel_filter(pf, 4739 (struct i40e_tunnel_filter *)flow->rule); 4740 break; 4741 case RTE_ETH_FILTER_FDIR: 4742 ret = i40e_flow_add_del_fdir_filter(dev, 4743 &((struct i40e_fdir_filter *)flow->rule)->fdir, 0); 4744 4745 /* If the last flow is destroyed, disable fdir. */ 4746 if (!ret && TAILQ_EMPTY(&pf->fdir.fdir_list)) { 4747 i40e_fdir_teardown(pf); 4748 dev->data->dev_conf.fdir_conf.mode = 4749 RTE_FDIR_MODE_NONE; 4750 } 4751 break; 4752 case RTE_ETH_FILTER_HASH: 4753 ret = i40e_config_rss_filter_del(dev, 4754 (struct i40e_rte_flow_rss_conf *)flow->rule); 4755 break; 4756 default: 4757 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 4758 filter_type); 4759 ret = -EINVAL; 4760 break; 4761 } 4762 4763 if (!ret) { 4764 TAILQ_REMOVE(&pf->flow_list, flow, node); 4765 rte_free(flow); 4766 } else 4767 rte_flow_error_set(error, -ret, 4768 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4769 "Failed to destroy flow."); 4770 4771 return ret; 4772 } 4773 4774 static int 4775 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf, 4776 struct i40e_ethertype_filter *filter) 4777 { 4778 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4779 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype; 4780 struct i40e_ethertype_filter *node; 4781 struct i40e_control_filter_stats stats; 4782 uint16_t flags = 0; 4783 int ret = 0; 4784 4785 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC)) 4786 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC; 4787 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) 4788 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP; 4789 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE; 4790 4791 memset(&stats, 0, sizeof(stats)); 4792 ret = i40e_aq_add_rem_control_packet_filter(hw, 4793 filter->input.mac_addr.addr_bytes, 4794 filter->input.ether_type, 4795 flags, pf->main_vsi->seid, 4796 filter->queue, 0, &stats, NULL); 4797 if (ret < 0) 4798 return ret; 4799 4800 node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input); 4801 if (!node) 4802 return -EINVAL; 4803 4804 ret = i40e_sw_ethertype_filter_del(pf, &node->input); 4805 4806 return ret; 4807 } 4808 4809 static int 4810 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf, 4811 struct i40e_tunnel_filter *filter) 4812 { 4813 struct i40e_hw *hw = I40E_PF_TO_HW(pf); 4814 struct i40e_vsi *vsi; 4815 struct i40e_pf_vf *vf; 4816 struct i40e_aqc_cloud_filters_element_bb cld_filter; 4817 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; 4818 struct i40e_tunnel_filter *node; 4819 bool big_buffer = 0; 4820 int ret = 0; 4821 4822 memset(&cld_filter, 0, sizeof(cld_filter)); 4823 ether_addr_copy((struct ether_addr *)&filter->input.outer_mac, 4824 (struct ether_addr *)&cld_filter.element.outer_mac); 4825 ether_addr_copy((struct ether_addr *)&filter->input.inner_mac, 4826 (struct ether_addr *)&cld_filter.element.inner_mac); 4827 cld_filter.element.inner_vlan = filter->input.inner_vlan; 4828 cld_filter.element.flags = filter->input.flags; 4829 cld_filter.element.tenant_id = filter->input.tenant_id; 4830 cld_filter.element.queue_number = filter->queue; 4831 rte_memcpy(cld_filter.general_fields, 4832 filter->input.general_fields, 4833 sizeof(cld_filter.general_fields)); 4834 4835 if (!filter->is_to_vf) 4836 vsi = pf->main_vsi; 4837 else { 4838 vf = &pf->vfs[filter->vf_id]; 4839 vsi = vf->vsi; 4840 } 4841 4842 if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) == 4843 I40E_AQC_ADD_CLOUD_FILTER_0X11) || 4844 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) == 4845 I40E_AQC_ADD_CLOUD_FILTER_0X12) || 4846 ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) == 4847 I40E_AQC_ADD_CLOUD_FILTER_0X10)) 4848 big_buffer = 1; 4849 4850 if (big_buffer) 4851 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid, 4852 &cld_filter, 1); 4853 else 4854 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid, 4855 &cld_filter.element, 1); 4856 if (ret < 0) 4857 return -ENOTSUP; 4858 4859 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input); 4860 if (!node) 4861 return -EINVAL; 4862 4863 ret = i40e_sw_tunnel_filter_del(pf, &node->input); 4864 4865 return ret; 4866 } 4867 4868 static int 4869 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error) 4870 { 4871 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4872 int ret; 4873 4874 ret = i40e_flow_flush_fdir_filter(pf); 4875 if (ret) { 4876 rte_flow_error_set(error, -ret, 4877 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4878 "Failed to flush FDIR flows."); 4879 return -rte_errno; 4880 } 4881 4882 ret = i40e_flow_flush_ethertype_filter(pf); 4883 if (ret) { 4884 rte_flow_error_set(error, -ret, 4885 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4886 "Failed to ethertype flush flows."); 4887 return -rte_errno; 4888 } 4889 4890 ret = i40e_flow_flush_tunnel_filter(pf); 4891 if (ret) { 4892 rte_flow_error_set(error, -ret, 4893 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4894 "Failed to flush tunnel flows."); 4895 return -rte_errno; 4896 } 4897 4898 ret = i40e_flow_flush_rss_filter(dev); 4899 if (ret) { 4900 rte_flow_error_set(error, -ret, 4901 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 4902 "Failed to flush rss flows."); 4903 return -rte_errno; 4904 } 4905 4906 return ret; 4907 } 4908 4909 static int 4910 i40e_flow_flush_fdir_filter(struct i40e_pf *pf) 4911 { 4912 struct rte_eth_dev *dev = pf->adapter->eth_dev; 4913 struct i40e_fdir_info *fdir_info = &pf->fdir; 4914 struct i40e_fdir_filter *fdir_filter; 4915 enum i40e_filter_pctype pctype; 4916 struct rte_flow *flow; 4917 void *temp; 4918 int ret; 4919 4920 ret = i40e_fdir_flush(dev); 4921 if (!ret) { 4922 /* Delete FDIR filters in FDIR list. */ 4923 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 4924 ret = i40e_sw_fdir_filter_del(pf, 4925 &fdir_filter->fdir.input); 4926 if (ret < 0) 4927 return ret; 4928 } 4929 4930 /* Delete FDIR flows in flow list. */ 4931 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) { 4932 if (flow->filter_type == RTE_ETH_FILTER_FDIR) { 4933 TAILQ_REMOVE(&pf->flow_list, flow, node); 4934 rte_free(flow); 4935 } 4936 } 4937 4938 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 4939 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) 4940 pf->fdir.inset_flag[pctype] = 0; 4941 } 4942 4943 i40e_fdir_teardown(pf); 4944 4945 return ret; 4946 } 4947 4948 /* Flush all ethertype filters */ 4949 static int 4950 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf) 4951 { 4952 struct i40e_ethertype_filter_list 4953 *ethertype_list = &pf->ethertype.ethertype_list; 4954 struct i40e_ethertype_filter *filter; 4955 struct rte_flow *flow; 4956 void *temp; 4957 int ret = 0; 4958 4959 while ((filter = TAILQ_FIRST(ethertype_list))) { 4960 ret = i40e_flow_destroy_ethertype_filter(pf, filter); 4961 if (ret) 4962 return ret; 4963 } 4964 4965 /* Delete ethertype flows in flow list. */ 4966 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) { 4967 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) { 4968 TAILQ_REMOVE(&pf->flow_list, flow, node); 4969 rte_free(flow); 4970 } 4971 } 4972 4973 return ret; 4974 } 4975 4976 /* Flush all tunnel filters */ 4977 static int 4978 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf) 4979 { 4980 struct i40e_tunnel_filter_list 4981 *tunnel_list = &pf->tunnel.tunnel_list; 4982 struct i40e_tunnel_filter *filter; 4983 struct rte_flow *flow; 4984 void *temp; 4985 int ret = 0; 4986 4987 while ((filter = TAILQ_FIRST(tunnel_list))) { 4988 ret = i40e_flow_destroy_tunnel_filter(pf, filter); 4989 if (ret) 4990 return ret; 4991 } 4992 4993 /* Delete tunnel flows in flow list. */ 4994 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) { 4995 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) { 4996 TAILQ_REMOVE(&pf->flow_list, flow, node); 4997 rte_free(flow); 4998 } 4999 } 5000 5001 return ret; 5002 } 5003 5004 /* remove the rss filter */ 5005 static int 5006 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev) 5007 { 5008 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5009 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info; 5010 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5011 int32_t ret = -EINVAL; 5012 5013 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0); 5014 5015 if (rss_info->conf.queue_num) 5016 ret = i40e_config_rss_filter(pf, rss_info, FALSE); 5017 return ret; 5018 } 5019