1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2016 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <rte_byteorder.h> 14 #include <rte_common.h> 15 #include <rte_cycles.h> 16 17 #include <rte_interrupts.h> 18 #include <rte_log.h> 19 #include <rte_debug.h> 20 #include <rte_pci.h> 21 #include <rte_bus_pci.h> 22 #include <rte_atomic.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_eal.h> 26 #include <rte_alarm.h> 27 #include <rte_ether.h> 28 #include <rte_ethdev_driver.h> 29 #include <rte_ethdev_pci.h> 30 #include <rte_malloc.h> 31 #include <rte_dev.h> 32 33 #include "i40e_logs.h" 34 #include "base/i40e_prototype.h" 35 #include "base/i40e_adminq_cmd.h" 36 #include "base/i40e_type.h" 37 38 #include "i40e_rxtx.h" 39 #include "i40e_ethdev.h" 40 #include "i40e_pf.h" 41 42 /* busy wait delay in msec */ 43 #define I40EVF_BUSY_WAIT_DELAY 10 44 #define I40EVF_BUSY_WAIT_COUNT 50 45 #define MAX_RESET_WAIT_CNT 20 46 47 #define I40EVF_ALARM_INTERVAL 50000 /* us */ 48 49 struct i40evf_arq_msg_info { 50 enum virtchnl_ops ops; 51 enum i40e_status_code result; 52 uint16_t buf_len; 53 uint16_t msg_len; 54 uint8_t *msg; 55 }; 56 57 struct vf_cmd_info { 58 enum virtchnl_ops ops; 59 uint8_t *in_args; 60 uint32_t in_args_size; 61 uint8_t *out_buffer; 62 /* Input & output type. pass in buffer size and pass out 63 * actual return result 64 */ 65 uint32_t out_size; 66 }; 67 68 enum i40evf_aq_result { 69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */ 70 I40EVF_MSG_NON, /* Read nothing from admin queue */ 71 I40EVF_MSG_SYS, /* Read system msg from admin queue */ 72 I40EVF_MSG_CMD, /* Read async command result */ 73 }; 74 75 static int i40evf_dev_configure(struct rte_eth_dev *dev); 76 static int i40evf_dev_start(struct rte_eth_dev *dev); 77 static void i40evf_dev_stop(struct rte_eth_dev *dev); 78 static void i40evf_dev_info_get(struct rte_eth_dev *dev, 79 struct rte_eth_dev_info *dev_info); 80 static int i40evf_dev_link_update(struct rte_eth_dev *dev, 81 int wait_to_complete); 82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev, 83 struct rte_eth_stats *stats); 84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev, 85 struct rte_eth_xstat *xstats, unsigned n); 86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev, 87 struct rte_eth_xstat_name *xstats_names, 88 unsigned limit); 89 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev); 90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev, 91 uint16_t vlan_id, int on); 92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 93 static void i40evf_dev_close(struct rte_eth_dev *dev); 94 static int i40evf_dev_reset(struct rte_eth_dev *dev); 95 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev); 96 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev); 97 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev); 98 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev); 99 static int i40evf_init_vlan(struct rte_eth_dev *dev); 100 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, 101 uint16_t rx_queue_id); 102 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, 103 uint16_t rx_queue_id); 104 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, 105 uint16_t tx_queue_id); 106 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, 107 uint16_t tx_queue_id); 108 static int i40evf_add_mac_addr(struct rte_eth_dev *dev, 109 struct ether_addr *addr, 110 uint32_t index, 111 uint32_t pool); 112 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index); 113 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev, 114 struct rte_eth_rss_reta_entry64 *reta_conf, 115 uint16_t reta_size); 116 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev, 117 struct rte_eth_rss_reta_entry64 *reta_conf, 118 uint16_t reta_size); 119 static int i40evf_config_rss(struct i40e_vf *vf); 120 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev, 121 struct rte_eth_rss_conf *rss_conf); 122 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 123 struct rte_eth_rss_conf *rss_conf); 124 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 125 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev, 126 struct ether_addr *mac_addr); 127 static int 128 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id); 129 static int 130 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id); 131 static void i40evf_handle_pf_event(struct rte_eth_dev *dev, 132 uint8_t *msg, 133 uint16_t msglen); 134 135 static int 136 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev, 137 struct ether_addr *mc_addr_set, 138 uint32_t nb_mc_addr, bool add); 139 static int 140 i40evf_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addr_set, 141 uint32_t nb_mc_addr); 142 143 /* Default hash key buffer for RSS */ 144 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1]; 145 146 struct rte_i40evf_xstats_name_off { 147 char name[RTE_ETH_XSTATS_NAME_SIZE]; 148 unsigned offset; 149 }; 150 151 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = { 152 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)}, 153 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)}, 154 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)}, 155 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)}, 156 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)}, 157 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats, 158 rx_unknown_protocol)}, 159 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)}, 160 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)}, 161 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)}, 162 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)}, 163 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)}, 164 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)}, 165 }; 166 167 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \ 168 sizeof(rte_i40evf_stats_strings[0])) 169 170 static const struct eth_dev_ops i40evf_eth_dev_ops = { 171 .dev_configure = i40evf_dev_configure, 172 .dev_start = i40evf_dev_start, 173 .dev_stop = i40evf_dev_stop, 174 .promiscuous_enable = i40evf_dev_promiscuous_enable, 175 .promiscuous_disable = i40evf_dev_promiscuous_disable, 176 .allmulticast_enable = i40evf_dev_allmulticast_enable, 177 .allmulticast_disable = i40evf_dev_allmulticast_disable, 178 .link_update = i40evf_dev_link_update, 179 .stats_get = i40evf_dev_stats_get, 180 .stats_reset = i40evf_dev_xstats_reset, 181 .xstats_get = i40evf_dev_xstats_get, 182 .xstats_get_names = i40evf_dev_xstats_get_names, 183 .xstats_reset = i40evf_dev_xstats_reset, 184 .dev_close = i40evf_dev_close, 185 .dev_reset = i40evf_dev_reset, 186 .dev_infos_get = i40evf_dev_info_get, 187 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get, 188 .vlan_filter_set = i40evf_vlan_filter_set, 189 .vlan_offload_set = i40evf_vlan_offload_set, 190 .rx_queue_start = i40evf_dev_rx_queue_start, 191 .rx_queue_stop = i40evf_dev_rx_queue_stop, 192 .tx_queue_start = i40evf_dev_tx_queue_start, 193 .tx_queue_stop = i40evf_dev_tx_queue_stop, 194 .rx_queue_setup = i40e_dev_rx_queue_setup, 195 .rx_queue_release = i40e_dev_rx_queue_release, 196 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable, 197 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable, 198 .rx_descriptor_done = i40e_dev_rx_descriptor_done, 199 .rx_descriptor_status = i40e_dev_rx_descriptor_status, 200 .tx_descriptor_status = i40e_dev_tx_descriptor_status, 201 .tx_queue_setup = i40e_dev_tx_queue_setup, 202 .tx_queue_release = i40e_dev_tx_queue_release, 203 .rx_queue_count = i40e_dev_rx_queue_count, 204 .rxq_info_get = i40e_rxq_info_get, 205 .txq_info_get = i40e_txq_info_get, 206 .mac_addr_add = i40evf_add_mac_addr, 207 .mac_addr_remove = i40evf_del_mac_addr, 208 .set_mc_addr_list = i40evf_set_mc_addr_list, 209 .reta_update = i40evf_dev_rss_reta_update, 210 .reta_query = i40evf_dev_rss_reta_query, 211 .rss_hash_update = i40evf_dev_rss_hash_update, 212 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get, 213 .mtu_set = i40evf_dev_mtu_set, 214 .mac_addr_set = i40evf_set_default_mac_addr, 215 }; 216 217 /* 218 * Read data in admin queue to get msg from pf driver 219 */ 220 static enum i40evf_aq_result 221 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data) 222 { 223 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 224 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 225 struct i40e_arq_event_info event; 226 enum virtchnl_ops opcode; 227 enum i40e_status_code retval; 228 int ret; 229 enum i40evf_aq_result result = I40EVF_MSG_NON; 230 231 event.buf_len = data->buf_len; 232 event.msg_buf = data->msg; 233 ret = i40e_clean_arq_element(hw, &event, NULL); 234 /* Can't read any msg from adminQ */ 235 if (ret) { 236 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK) 237 result = I40EVF_MSG_ERR; 238 return result; 239 } 240 241 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high); 242 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low); 243 /* pf sys event */ 244 if (opcode == VIRTCHNL_OP_EVENT) { 245 struct virtchnl_pf_event *vpe = 246 (struct virtchnl_pf_event *)event.msg_buf; 247 248 result = I40EVF_MSG_SYS; 249 switch (vpe->event) { 250 case VIRTCHNL_EVENT_LINK_CHANGE: 251 vf->link_up = 252 vpe->event_data.link_event.link_status; 253 vf->link_speed = 254 vpe->event_data.link_event.link_speed; 255 vf->pend_msg |= PFMSG_LINK_CHANGE; 256 PMD_DRV_LOG(INFO, "Link status update:%s", 257 vf->link_up ? "up" : "down"); 258 break; 259 case VIRTCHNL_EVENT_RESET_IMPENDING: 260 vf->vf_reset = true; 261 vf->pend_msg |= PFMSG_RESET_IMPENDING; 262 PMD_DRV_LOG(INFO, "vf is reseting"); 263 break; 264 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE: 265 vf->dev_closed = true; 266 vf->pend_msg |= PFMSG_DRIVER_CLOSE; 267 PMD_DRV_LOG(INFO, "PF driver closed"); 268 break; 269 default: 270 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf", 271 __func__, vpe->event); 272 } 273 } else { 274 /* async reply msg on command issued by vf previously */ 275 result = I40EVF_MSG_CMD; 276 /* Actual data length read from PF */ 277 data->msg_len = event.msg_len; 278 } 279 280 data->result = retval; 281 data->ops = opcode; 282 283 return result; 284 } 285 286 /** 287 * clear current command. Only call in case execute 288 * _atomic_set_cmd successfully. 289 */ 290 static inline void 291 _clear_cmd(struct i40e_vf *vf) 292 { 293 rte_wmb(); 294 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN; 295 } 296 297 /* 298 * Check there is pending cmd in execution. If none, set new command. 299 */ 300 static inline int 301 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops) 302 { 303 int ret = rte_atomic32_cmpset(&vf->pend_cmd, 304 VIRTCHNL_OP_UNKNOWN, ops); 305 306 if (!ret) 307 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd); 308 309 return !ret; 310 } 311 312 #define MAX_TRY_TIMES 200 313 #define ASQ_DELAY_MS 10 314 315 static int 316 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args) 317 { 318 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 319 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 320 struct i40evf_arq_msg_info info; 321 enum i40evf_aq_result ret; 322 int err, i = 0; 323 324 if (_atomic_set_cmd(vf, args->ops)) 325 return -1; 326 327 info.msg = args->out_buffer; 328 info.buf_len = args->out_size; 329 info.ops = VIRTCHNL_OP_UNKNOWN; 330 info.result = I40E_SUCCESS; 331 332 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS, 333 args->in_args, args->in_args_size, NULL); 334 if (err) { 335 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops); 336 _clear_cmd(vf); 337 return err; 338 } 339 340 switch (args->ops) { 341 case VIRTCHNL_OP_RESET_VF: 342 /*no need to process in this function */ 343 err = 0; 344 break; 345 case VIRTCHNL_OP_VERSION: 346 case VIRTCHNL_OP_GET_VF_RESOURCES: 347 /* for init adminq commands, need to poll the response */ 348 err = -1; 349 do { 350 ret = i40evf_read_pfmsg(dev, &info); 351 vf->cmd_retval = info.result; 352 if (ret == I40EVF_MSG_CMD) { 353 err = 0; 354 break; 355 } else if (ret == I40EVF_MSG_ERR) 356 break; 357 rte_delay_ms(ASQ_DELAY_MS); 358 /* If don't read msg or read sys event, continue */ 359 } while (i++ < MAX_TRY_TIMES); 360 _clear_cmd(vf); 361 break; 362 363 default: 364 /* for other adminq in running time, waiting the cmd done flag */ 365 err = -1; 366 do { 367 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) { 368 err = 0; 369 break; 370 } 371 rte_delay_ms(ASQ_DELAY_MS); 372 /* If don't read msg or read sys event, continue */ 373 } while (i++ < MAX_TRY_TIMES); 374 /* If there's no response is received, clear command */ 375 if (i >= MAX_TRY_TIMES) { 376 PMD_DRV_LOG(WARNING, "No response for %d", args->ops); 377 _clear_cmd(vf); 378 } 379 break; 380 } 381 382 return err | vf->cmd_retval; 383 } 384 385 /* 386 * Check API version with sync wait until version read or fail from admin queue 387 */ 388 static int 389 i40evf_check_api_version(struct rte_eth_dev *dev) 390 { 391 struct virtchnl_version_info version, *pver; 392 int err; 393 struct vf_cmd_info args; 394 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 395 396 version.major = VIRTCHNL_VERSION_MAJOR; 397 version.minor = VIRTCHNL_VERSION_MINOR; 398 399 args.ops = VIRTCHNL_OP_VERSION; 400 args.in_args = (uint8_t *)&version; 401 args.in_args_size = sizeof(version); 402 args.out_buffer = vf->aq_resp; 403 args.out_size = I40E_AQ_BUF_SZ; 404 405 err = i40evf_execute_vf_cmd(dev, &args); 406 if (err) { 407 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION"); 408 return err; 409 } 410 411 pver = (struct virtchnl_version_info *)args.out_buffer; 412 vf->version_major = pver->major; 413 vf->version_minor = pver->minor; 414 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) && 415 (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) 416 PMD_DRV_LOG(INFO, "Peer is Linux PF host"); 417 else { 418 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)", 419 vf->version_major, vf->version_minor, 420 VIRTCHNL_VERSION_MAJOR, 421 VIRTCHNL_VERSION_MINOR); 422 return -1; 423 } 424 425 return 0; 426 } 427 428 static int 429 i40evf_get_vf_resource(struct rte_eth_dev *dev) 430 { 431 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 432 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 433 int err; 434 struct vf_cmd_info args; 435 uint32_t caps, len; 436 437 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES; 438 args.out_buffer = vf->aq_resp; 439 args.out_size = I40E_AQ_BUF_SZ; 440 if (PF_IS_V11(vf)) { 441 caps = VIRTCHNL_VF_OFFLOAD_L2 | 442 VIRTCHNL_VF_OFFLOAD_RSS_AQ | 443 VIRTCHNL_VF_OFFLOAD_RSS_REG | 444 VIRTCHNL_VF_OFFLOAD_VLAN | 445 VIRTCHNL_VF_OFFLOAD_RX_POLLING; 446 args.in_args = (uint8_t *)∩︀ 447 args.in_args_size = sizeof(caps); 448 } else { 449 args.in_args = NULL; 450 args.in_args_size = 0; 451 } 452 err = i40evf_execute_vf_cmd(dev, &args); 453 454 if (err) { 455 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE"); 456 return err; 457 } 458 459 len = sizeof(struct virtchnl_vf_resource) + 460 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource); 461 462 rte_memcpy(vf->vf_res, args.out_buffer, 463 RTE_MIN(args.out_size, len)); 464 i40e_vf_parse_hw_config(hw, vf->vf_res); 465 466 return 0; 467 } 468 469 static int 470 i40evf_config_promisc(struct rte_eth_dev *dev, 471 bool enable_unicast, 472 bool enable_multicast) 473 { 474 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 475 int err; 476 struct vf_cmd_info args; 477 struct virtchnl_promisc_info promisc; 478 479 promisc.flags = 0; 480 promisc.vsi_id = vf->vsi_res->vsi_id; 481 482 if (enable_unicast) 483 promisc.flags |= FLAG_VF_UNICAST_PROMISC; 484 485 if (enable_multicast) 486 promisc.flags |= FLAG_VF_MULTICAST_PROMISC; 487 488 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE; 489 args.in_args = (uint8_t *)&promisc; 490 args.in_args_size = sizeof(promisc); 491 args.out_buffer = vf->aq_resp; 492 args.out_size = I40E_AQ_BUF_SZ; 493 494 err = i40evf_execute_vf_cmd(dev, &args); 495 496 if (err) 497 PMD_DRV_LOG(ERR, "fail to execute command " 498 "CONFIG_PROMISCUOUS_MODE"); 499 return err; 500 } 501 502 static int 503 i40evf_enable_vlan_strip(struct rte_eth_dev *dev) 504 { 505 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 506 struct vf_cmd_info args; 507 int ret; 508 509 memset(&args, 0, sizeof(args)); 510 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING; 511 args.in_args = NULL; 512 args.in_args_size = 0; 513 args.out_buffer = vf->aq_resp; 514 args.out_size = I40E_AQ_BUF_SZ; 515 ret = i40evf_execute_vf_cmd(dev, &args); 516 if (ret) 517 PMD_DRV_LOG(ERR, "Failed to execute command of " 518 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING"); 519 520 return ret; 521 } 522 523 static int 524 i40evf_disable_vlan_strip(struct rte_eth_dev *dev) 525 { 526 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 527 struct vf_cmd_info args; 528 int ret; 529 530 memset(&args, 0, sizeof(args)); 531 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING; 532 args.in_args = NULL; 533 args.in_args_size = 0; 534 args.out_buffer = vf->aq_resp; 535 args.out_size = I40E_AQ_BUF_SZ; 536 ret = i40evf_execute_vf_cmd(dev, &args); 537 if (ret) 538 PMD_DRV_LOG(ERR, "Failed to execute command of " 539 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING"); 540 541 return ret; 542 } 543 544 static void 545 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info, 546 uint16_t vsi_id, 547 uint16_t queue_id, 548 uint16_t nb_txq, 549 struct i40e_tx_queue *txq) 550 { 551 txq_info->vsi_id = vsi_id; 552 txq_info->queue_id = queue_id; 553 if (queue_id < nb_txq) { 554 txq_info->ring_len = txq->nb_tx_desc; 555 txq_info->dma_ring_addr = txq->tx_ring_phys_addr; 556 } 557 } 558 559 static void 560 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info, 561 uint16_t vsi_id, 562 uint16_t queue_id, 563 uint16_t nb_rxq, 564 uint32_t max_pkt_size, 565 struct i40e_rx_queue *rxq) 566 { 567 rxq_info->vsi_id = vsi_id; 568 rxq_info->queue_id = queue_id; 569 rxq_info->max_pkt_size = max_pkt_size; 570 if (queue_id < nb_rxq) { 571 rxq_info->ring_len = rxq->nb_rx_desc; 572 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr; 573 rxq_info->databuffer_size = 574 (rte_pktmbuf_data_room_size(rxq->mp) - 575 RTE_PKTMBUF_HEADROOM); 576 } 577 } 578 579 static int 580 i40evf_configure_vsi_queues(struct rte_eth_dev *dev) 581 { 582 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 583 struct i40e_rx_queue **rxq = 584 (struct i40e_rx_queue **)dev->data->rx_queues; 585 struct i40e_tx_queue **txq = 586 (struct i40e_tx_queue **)dev->data->tx_queues; 587 struct virtchnl_vsi_queue_config_info *vc_vqci; 588 struct virtchnl_queue_pair_info *vc_qpi; 589 struct vf_cmd_info args; 590 uint16_t i, nb_qp = vf->num_queue_pairs; 591 const uint32_t size = 592 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp); 593 uint8_t buff[size]; 594 int ret; 595 596 memset(buff, 0, sizeof(buff)); 597 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff; 598 vc_vqci->vsi_id = vf->vsi_res->vsi_id; 599 vc_vqci->num_queue_pairs = nb_qp; 600 601 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) { 602 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq, 603 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]); 604 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq, 605 vc_vqci->vsi_id, i, dev->data->nb_rx_queues, 606 vf->max_pkt_len, rxq[i]); 607 } 608 memset(&args, 0, sizeof(args)); 609 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES; 610 args.in_args = (uint8_t *)vc_vqci; 611 args.in_args_size = size; 612 args.out_buffer = vf->aq_resp; 613 args.out_size = I40E_AQ_BUF_SZ; 614 ret = i40evf_execute_vf_cmd(dev, &args); 615 if (ret) 616 PMD_DRV_LOG(ERR, "Failed to execute command of " 617 "VIRTCHNL_OP_CONFIG_VSI_QUEUES"); 618 619 return ret; 620 } 621 622 static int 623 i40evf_config_irq_map(struct rte_eth_dev *dev) 624 { 625 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 626 struct vf_cmd_info args; 627 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \ 628 sizeof(struct virtchnl_vector_map)]; 629 struct virtchnl_irq_map_info *map_info; 630 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 631 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 632 uint32_t vector_id; 633 int i, err; 634 635 if (dev->data->dev_conf.intr_conf.rxq != 0 && 636 rte_intr_allow_others(intr_handle)) 637 vector_id = I40E_RX_VEC_START; 638 else 639 vector_id = I40E_MISC_VEC_ID; 640 641 map_info = (struct virtchnl_irq_map_info *)cmd_buffer; 642 map_info->num_vectors = 1; 643 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT; 644 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id; 645 /* Alway use default dynamic MSIX interrupt */ 646 map_info->vecmap[0].vector_id = vector_id; 647 /* Don't map any tx queue */ 648 map_info->vecmap[0].txq_map = 0; 649 map_info->vecmap[0].rxq_map = 0; 650 for (i = 0; i < dev->data->nb_rx_queues; i++) { 651 map_info->vecmap[0].rxq_map |= 1 << i; 652 if (rte_intr_dp_is_en(intr_handle)) 653 intr_handle->intr_vec[i] = vector_id; 654 } 655 656 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP; 657 args.in_args = (u8 *)cmd_buffer; 658 args.in_args_size = sizeof(cmd_buffer); 659 args.out_buffer = vf->aq_resp; 660 args.out_size = I40E_AQ_BUF_SZ; 661 err = i40evf_execute_vf_cmd(dev, &args); 662 if (err) 663 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES"); 664 665 return err; 666 } 667 668 static int 669 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid, 670 bool on) 671 { 672 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 673 struct virtchnl_queue_select queue_select; 674 int err; 675 struct vf_cmd_info args; 676 memset(&queue_select, 0, sizeof(queue_select)); 677 queue_select.vsi_id = vf->vsi_res->vsi_id; 678 679 if (isrx) 680 queue_select.rx_queues |= 1 << qid; 681 else 682 queue_select.tx_queues |= 1 << qid; 683 684 if (on) 685 args.ops = VIRTCHNL_OP_ENABLE_QUEUES; 686 else 687 args.ops = VIRTCHNL_OP_DISABLE_QUEUES; 688 args.in_args = (u8 *)&queue_select; 689 args.in_args_size = sizeof(queue_select); 690 args.out_buffer = vf->aq_resp; 691 args.out_size = I40E_AQ_BUF_SZ; 692 err = i40evf_execute_vf_cmd(dev, &args); 693 if (err) 694 PMD_DRV_LOG(ERR, "fail to switch %s %u %s", 695 isrx ? "RX" : "TX", qid, on ? "on" : "off"); 696 697 return err; 698 } 699 700 static int 701 i40evf_start_queues(struct rte_eth_dev *dev) 702 { 703 struct rte_eth_dev_data *dev_data = dev->data; 704 int i; 705 struct i40e_rx_queue *rxq; 706 struct i40e_tx_queue *txq; 707 708 for (i = 0; i < dev->data->nb_rx_queues; i++) { 709 rxq = dev_data->rx_queues[i]; 710 if (rxq->rx_deferred_start) 711 continue; 712 if (i40evf_dev_rx_queue_start(dev, i) != 0) { 713 PMD_DRV_LOG(ERR, "Fail to start queue %u", i); 714 return -1; 715 } 716 } 717 718 for (i = 0; i < dev->data->nb_tx_queues; i++) { 719 txq = dev_data->tx_queues[i]; 720 if (txq->tx_deferred_start) 721 continue; 722 if (i40evf_dev_tx_queue_start(dev, i) != 0) { 723 PMD_DRV_LOG(ERR, "Fail to start queue %u", i); 724 return -1; 725 } 726 } 727 728 return 0; 729 } 730 731 static int 732 i40evf_stop_queues(struct rte_eth_dev *dev) 733 { 734 int i; 735 736 /* Stop TX queues first */ 737 for (i = 0; i < dev->data->nb_tx_queues; i++) { 738 if (i40evf_dev_tx_queue_stop(dev, i) != 0) { 739 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i); 740 return -1; 741 } 742 } 743 744 /* Then stop RX queues */ 745 for (i = 0; i < dev->data->nb_rx_queues; i++) { 746 if (i40evf_dev_rx_queue_stop(dev, i) != 0) { 747 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i); 748 return -1; 749 } 750 } 751 752 return 0; 753 } 754 755 static int 756 i40evf_add_mac_addr(struct rte_eth_dev *dev, 757 struct ether_addr *addr, 758 __rte_unused uint32_t index, 759 __rte_unused uint32_t pool) 760 { 761 struct virtchnl_ether_addr_list *list; 762 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 763 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \ 764 sizeof(struct virtchnl_ether_addr)]; 765 int err; 766 struct vf_cmd_info args; 767 768 if (is_zero_ether_addr(addr)) { 769 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x", 770 addr->addr_bytes[0], addr->addr_bytes[1], 771 addr->addr_bytes[2], addr->addr_bytes[3], 772 addr->addr_bytes[4], addr->addr_bytes[5]); 773 return I40E_ERR_INVALID_MAC_ADDR; 774 } 775 776 list = (struct virtchnl_ether_addr_list *)cmd_buffer; 777 list->vsi_id = vf->vsi_res->vsi_id; 778 list->num_elements = 1; 779 rte_memcpy(list->list[0].addr, addr->addr_bytes, 780 sizeof(addr->addr_bytes)); 781 782 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR; 783 args.in_args = cmd_buffer; 784 args.in_args_size = sizeof(cmd_buffer); 785 args.out_buffer = vf->aq_resp; 786 args.out_size = I40E_AQ_BUF_SZ; 787 err = i40evf_execute_vf_cmd(dev, &args); 788 if (err) 789 PMD_DRV_LOG(ERR, "fail to execute command " 790 "OP_ADD_ETHER_ADDRESS"); 791 else 792 vf->vsi.mac_num++; 793 794 return err; 795 } 796 797 static void 798 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev, 799 struct ether_addr *addr) 800 { 801 struct virtchnl_ether_addr_list *list; 802 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 803 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \ 804 sizeof(struct virtchnl_ether_addr)]; 805 int err; 806 struct vf_cmd_info args; 807 808 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) { 809 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x", 810 addr->addr_bytes[0], addr->addr_bytes[1], 811 addr->addr_bytes[2], addr->addr_bytes[3], 812 addr->addr_bytes[4], addr->addr_bytes[5]); 813 return; 814 } 815 816 list = (struct virtchnl_ether_addr_list *)cmd_buffer; 817 list->vsi_id = vf->vsi_res->vsi_id; 818 list->num_elements = 1; 819 rte_memcpy(list->list[0].addr, addr->addr_bytes, 820 sizeof(addr->addr_bytes)); 821 822 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR; 823 args.in_args = cmd_buffer; 824 args.in_args_size = sizeof(cmd_buffer); 825 args.out_buffer = vf->aq_resp; 826 args.out_size = I40E_AQ_BUF_SZ; 827 err = i40evf_execute_vf_cmd(dev, &args); 828 if (err) 829 PMD_DRV_LOG(ERR, "fail to execute command " 830 "OP_DEL_ETHER_ADDRESS"); 831 else 832 vf->vsi.mac_num--; 833 return; 834 } 835 836 static void 837 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index) 838 { 839 struct rte_eth_dev_data *data = dev->data; 840 struct ether_addr *addr; 841 842 addr = &data->mac_addrs[index]; 843 844 i40evf_del_mac_addr_by_addr(dev, addr); 845 } 846 847 static int 848 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats) 849 { 850 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 851 struct virtchnl_queue_select q_stats; 852 int err; 853 struct vf_cmd_info args; 854 855 memset(&q_stats, 0, sizeof(q_stats)); 856 q_stats.vsi_id = vf->vsi_res->vsi_id; 857 args.ops = VIRTCHNL_OP_GET_STATS; 858 args.in_args = (u8 *)&q_stats; 859 args.in_args_size = sizeof(q_stats); 860 args.out_buffer = vf->aq_resp; 861 args.out_size = I40E_AQ_BUF_SZ; 862 863 err = i40evf_execute_vf_cmd(dev, &args); 864 if (err) { 865 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS"); 866 *pstats = NULL; 867 return err; 868 } 869 *pstats = (struct i40e_eth_stats *)args.out_buffer; 870 return 0; 871 } 872 873 static void 874 i40evf_stat_update_48(uint64_t *offset, 875 uint64_t *stat) 876 { 877 if (*stat >= *offset) 878 *stat = *stat - *offset; 879 else 880 *stat = (uint64_t)((*stat + 881 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset); 882 883 *stat &= I40E_48_BIT_MASK; 884 } 885 886 static void 887 i40evf_stat_update_32(uint64_t *offset, 888 uint64_t *stat) 889 { 890 if (*stat >= *offset) 891 *stat = (uint64_t)(*stat - *offset); 892 else 893 *stat = (uint64_t)((*stat + 894 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset); 895 } 896 897 static void 898 i40evf_update_stats(struct i40e_vsi *vsi, 899 struct i40e_eth_stats *nes) 900 { 901 struct i40e_eth_stats *oes = &vsi->eth_stats_offset; 902 903 i40evf_stat_update_48(&oes->rx_bytes, 904 &nes->rx_bytes); 905 i40evf_stat_update_48(&oes->rx_unicast, 906 &nes->rx_unicast); 907 i40evf_stat_update_48(&oes->rx_multicast, 908 &nes->rx_multicast); 909 i40evf_stat_update_48(&oes->rx_broadcast, 910 &nes->rx_broadcast); 911 i40evf_stat_update_32(&oes->rx_discards, 912 &nes->rx_discards); 913 i40evf_stat_update_32(&oes->rx_unknown_protocol, 914 &nes->rx_unknown_protocol); 915 i40evf_stat_update_48(&oes->tx_bytes, 916 &nes->tx_bytes); 917 i40evf_stat_update_48(&oes->tx_unicast, 918 &nes->tx_unicast); 919 i40evf_stat_update_48(&oes->tx_multicast, 920 &nes->tx_multicast); 921 i40evf_stat_update_48(&oes->tx_broadcast, 922 &nes->tx_broadcast); 923 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors); 924 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards); 925 } 926 927 static void 928 i40evf_dev_xstats_reset(struct rte_eth_dev *dev) 929 { 930 int ret; 931 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 932 struct i40e_eth_stats *pstats = NULL; 933 934 /* read stat values to clear hardware registers */ 935 ret = i40evf_query_stats(dev, &pstats); 936 937 /* set stats offset base on current values */ 938 if (ret == 0) 939 vf->vsi.eth_stats_offset = *pstats; 940 } 941 942 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 943 struct rte_eth_xstat_name *xstats_names, 944 __rte_unused unsigned limit) 945 { 946 unsigned i; 947 948 if (xstats_names != NULL) 949 for (i = 0; i < I40EVF_NB_XSTATS; i++) { 950 snprintf(xstats_names[i].name, 951 sizeof(xstats_names[i].name), 952 "%s", rte_i40evf_stats_strings[i].name); 953 } 954 return I40EVF_NB_XSTATS; 955 } 956 957 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev, 958 struct rte_eth_xstat *xstats, unsigned n) 959 { 960 int ret; 961 unsigned i; 962 struct i40e_eth_stats *pstats = NULL; 963 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 964 struct i40e_vsi *vsi = &vf->vsi; 965 966 if (n < I40EVF_NB_XSTATS) 967 return I40EVF_NB_XSTATS; 968 969 ret = i40evf_query_stats(dev, &pstats); 970 if (ret != 0) 971 return 0; 972 973 if (!xstats) 974 return 0; 975 976 i40evf_update_stats(vsi, pstats); 977 978 /* loop over xstats array and values from pstats */ 979 for (i = 0; i < I40EVF_NB_XSTATS; i++) { 980 xstats[i].id = i; 981 xstats[i].value = *(uint64_t *)(((char *)pstats) + 982 rte_i40evf_stats_strings[i].offset); 983 } 984 985 return I40EVF_NB_XSTATS; 986 } 987 988 static int 989 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid) 990 { 991 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 992 struct virtchnl_vlan_filter_list *vlan_list; 993 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) + 994 sizeof(uint16_t)]; 995 int err; 996 struct vf_cmd_info args; 997 998 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer; 999 vlan_list->vsi_id = vf->vsi_res->vsi_id; 1000 vlan_list->num_elements = 1; 1001 vlan_list->vlan_id[0] = vlanid; 1002 1003 args.ops = VIRTCHNL_OP_ADD_VLAN; 1004 args.in_args = (u8 *)&cmd_buffer; 1005 args.in_args_size = sizeof(cmd_buffer); 1006 args.out_buffer = vf->aq_resp; 1007 args.out_size = I40E_AQ_BUF_SZ; 1008 err = i40evf_execute_vf_cmd(dev, &args); 1009 if (err) 1010 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN"); 1011 1012 return err; 1013 } 1014 1015 static int 1016 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid) 1017 { 1018 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1019 struct virtchnl_vlan_filter_list *vlan_list; 1020 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) + 1021 sizeof(uint16_t)]; 1022 int err; 1023 struct vf_cmd_info args; 1024 1025 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer; 1026 vlan_list->vsi_id = vf->vsi_res->vsi_id; 1027 vlan_list->num_elements = 1; 1028 vlan_list->vlan_id[0] = vlanid; 1029 1030 args.ops = VIRTCHNL_OP_DEL_VLAN; 1031 args.in_args = (u8 *)&cmd_buffer; 1032 args.in_args_size = sizeof(cmd_buffer); 1033 args.out_buffer = vf->aq_resp; 1034 args.out_size = I40E_AQ_BUF_SZ; 1035 err = i40evf_execute_vf_cmd(dev, &args); 1036 if (err) 1037 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN"); 1038 1039 return err; 1040 } 1041 1042 static const struct rte_pci_id pci_id_i40evf_map[] = { 1043 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) }, 1044 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) }, 1045 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) }, 1046 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) }, 1047 { .vendor_id = 0, /* sentinel */ }, 1048 }; 1049 1050 /* Disable IRQ0 */ 1051 static inline void 1052 i40evf_disable_irq0(struct i40e_hw *hw) 1053 { 1054 /* Disable all interrupt types */ 1055 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0); 1056 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 1057 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); 1058 I40EVF_WRITE_FLUSH(hw); 1059 } 1060 1061 /* Enable IRQ0 */ 1062 static inline void 1063 i40evf_enable_irq0(struct i40e_hw *hw) 1064 { 1065 /* Enable admin queue interrupt trigger */ 1066 uint32_t val; 1067 1068 i40evf_disable_irq0(hw); 1069 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1); 1070 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK | 1071 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK; 1072 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val); 1073 1074 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 1075 I40E_VFINT_DYN_CTL01_INTENA_MASK | 1076 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK | 1077 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); 1078 1079 I40EVF_WRITE_FLUSH(hw); 1080 } 1081 1082 static int 1083 i40evf_check_vf_reset_done(struct rte_eth_dev *dev) 1084 { 1085 int i, reset; 1086 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1087 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1088 1089 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) { 1090 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) & 1091 I40E_VFGEN_RSTAT_VFR_STATE_MASK; 1092 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT; 1093 if (reset == VIRTCHNL_VFR_VFACTIVE || 1094 reset == VIRTCHNL_VFR_COMPLETED) 1095 break; 1096 rte_delay_ms(50); 1097 } 1098 1099 if (i >= MAX_RESET_WAIT_CNT) 1100 return -1; 1101 1102 vf->vf_reset = false; 1103 vf->pend_msg &= ~PFMSG_RESET_IMPENDING; 1104 1105 return 0; 1106 } 1107 static int 1108 i40evf_reset_vf(struct rte_eth_dev *dev) 1109 { 1110 int ret; 1111 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1112 1113 if (i40e_vf_reset(hw) != I40E_SUCCESS) { 1114 PMD_INIT_LOG(ERR, "Reset VF NIC failed"); 1115 return -1; 1116 } 1117 /** 1118 * After issuing vf reset command to pf, pf won't necessarily 1119 * reset vf, it depends on what state it exactly is. If it's not 1120 * initialized yet, it won't have vf reset since it's in a certain 1121 * state. If not, it will try to reset. Even vf is reset, pf will 1122 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set 1123 * it to ACTIVE. In this duration, vf may not catch the moment that 1124 * COMPLETE is set. So, for vf, we'll try to wait a long time. 1125 */ 1126 rte_delay_ms(200); 1127 1128 ret = i40evf_check_vf_reset_done(dev); 1129 if (ret) { 1130 PMD_INIT_LOG(ERR, "VF is still resetting"); 1131 return ret; 1132 } 1133 1134 return 0; 1135 } 1136 1137 static int 1138 i40evf_init_vf(struct rte_eth_dev *dev) 1139 { 1140 int i, err, bufsz; 1141 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1142 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1143 uint16_t interval = 1144 i40e_calc_itr_interval(0, 0); 1145 1146 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1147 vf->dev_data = dev->data; 1148 err = i40e_set_mac_type(hw); 1149 if (err) { 1150 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err); 1151 goto err; 1152 } 1153 1154 err = i40evf_check_vf_reset_done(dev); 1155 if (err) 1156 goto err; 1157 1158 i40e_init_adminq_parameter(hw); 1159 err = i40e_init_adminq(hw); 1160 if (err) { 1161 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err); 1162 goto err; 1163 } 1164 1165 /* Reset VF and wait until it's complete */ 1166 if (i40evf_reset_vf(dev)) { 1167 PMD_INIT_LOG(ERR, "reset NIC failed"); 1168 goto err_aq; 1169 } 1170 1171 /* VF reset, shutdown admin queue and initialize again */ 1172 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) { 1173 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed"); 1174 goto err; 1175 } 1176 1177 i40e_init_adminq_parameter(hw); 1178 if (i40e_init_adminq(hw) != I40E_SUCCESS) { 1179 PMD_INIT_LOG(ERR, "init_adminq failed"); 1180 goto err; 1181 } 1182 1183 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0); 1184 if (!vf->aq_resp) { 1185 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory"); 1186 goto err_aq; 1187 } 1188 if (i40evf_check_api_version(dev) != 0) { 1189 PMD_INIT_LOG(ERR, "check_api version failed"); 1190 goto err_api; 1191 } 1192 bufsz = sizeof(struct virtchnl_vf_resource) + 1193 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource)); 1194 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0); 1195 if (!vf->vf_res) { 1196 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory"); 1197 goto err_api; 1198 } 1199 1200 if (i40evf_get_vf_resource(dev) != 0) { 1201 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed"); 1202 goto err_alloc; 1203 } 1204 1205 /* got VF config message back from PF, now we can parse it */ 1206 for (i = 0; i < vf->vf_res->num_vsis; i++) { 1207 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV) 1208 vf->vsi_res = &vf->vf_res->vsi_res[i]; 1209 } 1210 1211 if (!vf->vsi_res) { 1212 PMD_INIT_LOG(ERR, "no LAN VSI found"); 1213 goto err_alloc; 1214 } 1215 1216 if (hw->mac.type == I40E_MAC_X722_VF) 1217 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE; 1218 vf->vsi.vsi_id = vf->vsi_res->vsi_id; 1219 1220 switch (vf->vsi_res->vsi_type) { 1221 case VIRTCHNL_VSI_SRIOV: 1222 vf->vsi.type = I40E_VSI_SRIOV; 1223 break; 1224 default: 1225 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN; 1226 break; 1227 } 1228 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs; 1229 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1230 1231 /* Store the MAC address configured by host, or generate random one */ 1232 if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr)) 1233 vf->flags |= I40E_FLAG_VF_MAC_BY_PF; 1234 else 1235 eth_random_addr(hw->mac.addr); /* Generate a random one */ 1236 1237 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 1238 (I40E_ITR_INDEX_DEFAULT << 1239 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) | 1240 (interval << 1241 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT)); 1242 I40EVF_WRITE_FLUSH(hw); 1243 1244 return 0; 1245 1246 err_alloc: 1247 rte_free(vf->vf_res); 1248 vf->vsi_res = NULL; 1249 err_api: 1250 rte_free(vf->aq_resp); 1251 err_aq: 1252 i40e_shutdown_adminq(hw); /* ignore error */ 1253 err: 1254 return -1; 1255 } 1256 1257 static int 1258 i40evf_uninit_vf(struct rte_eth_dev *dev) 1259 { 1260 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1261 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1262 1263 PMD_INIT_FUNC_TRACE(); 1264 1265 if (hw->adapter_closed == 0) 1266 i40evf_dev_close(dev); 1267 rte_free(vf->vf_res); 1268 vf->vf_res = NULL; 1269 rte_free(vf->aq_resp); 1270 vf->aq_resp = NULL; 1271 1272 return 0; 1273 } 1274 1275 static void 1276 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg, 1277 __rte_unused uint16_t msglen) 1278 { 1279 struct virtchnl_pf_event *pf_msg = 1280 (struct virtchnl_pf_event *)msg; 1281 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1282 1283 switch (pf_msg->event) { 1284 case VIRTCHNL_EVENT_RESET_IMPENDING: 1285 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event"); 1286 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1287 NULL); 1288 break; 1289 case VIRTCHNL_EVENT_LINK_CHANGE: 1290 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event"); 1291 vf->link_up = pf_msg->event_data.link_event.link_status; 1292 vf->link_speed = pf_msg->event_data.link_event.link_speed; 1293 break; 1294 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE: 1295 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event"); 1296 break; 1297 default: 1298 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event); 1299 break; 1300 } 1301 } 1302 1303 static void 1304 i40evf_handle_aq_msg(struct rte_eth_dev *dev) 1305 { 1306 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1307 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1308 struct i40e_arq_event_info info; 1309 uint16_t pending, aq_opc; 1310 enum virtchnl_ops msg_opc; 1311 enum i40e_status_code msg_ret; 1312 int ret; 1313 1314 info.buf_len = I40E_AQ_BUF_SZ; 1315 if (!vf->aq_resp) { 1316 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL"); 1317 return; 1318 } 1319 info.msg_buf = vf->aq_resp; 1320 1321 pending = 1; 1322 while (pending) { 1323 ret = i40e_clean_arq_element(hw, &info, &pending); 1324 1325 if (ret != I40E_SUCCESS) { 1326 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ," 1327 "ret: %d", ret); 1328 break; 1329 } 1330 aq_opc = rte_le_to_cpu_16(info.desc.opcode); 1331 /* For the message sent from pf to vf, opcode is stored in 1332 * cookie_high of struct i40e_aq_desc, while return error code 1333 * are stored in cookie_low, Which is done by 1334 * i40e_aq_send_msg_to_vf in PF driver.*/ 1335 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32( 1336 info.desc.cookie_high); 1337 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32( 1338 info.desc.cookie_low); 1339 switch (aq_opc) { 1340 case i40e_aqc_opc_send_msg_to_vf: 1341 if (msg_opc == VIRTCHNL_OP_EVENT) 1342 /* process event*/ 1343 i40evf_handle_pf_event(dev, info.msg_buf, 1344 info.msg_len); 1345 else { 1346 /* read message and it's expected one */ 1347 if (msg_opc == vf->pend_cmd) { 1348 vf->cmd_retval = msg_ret; 1349 /* prevent compiler reordering */ 1350 rte_compiler_barrier(); 1351 _clear_cmd(vf); 1352 } else 1353 PMD_DRV_LOG(ERR, "command mismatch," 1354 "expect %u, get %u", 1355 vf->pend_cmd, msg_opc); 1356 PMD_DRV_LOG(DEBUG, "adminq response is received," 1357 " opcode = %d", msg_opc); 1358 } 1359 break; 1360 default: 1361 PMD_DRV_LOG(ERR, "Request %u is not supported yet", 1362 aq_opc); 1363 break; 1364 } 1365 } 1366 } 1367 1368 /** 1369 * Interrupt handler triggered by NIC for handling 1370 * specific interrupt. Only adminq interrupt is processed in VF. 1371 * 1372 * @param handle 1373 * Pointer to interrupt handle. 1374 * @param param 1375 * The address of parameter (struct rte_eth_dev *) regsitered before. 1376 * 1377 * @return 1378 * void 1379 */ 1380 static void 1381 i40evf_dev_alarm_handler(void *param) 1382 { 1383 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1384 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1385 uint32_t icr0; 1386 1387 i40evf_disable_irq0(hw); 1388 1389 /* read out interrupt causes */ 1390 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01); 1391 1392 /* No interrupt event indicated */ 1393 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) 1394 goto done; 1395 1396 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) { 1397 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported"); 1398 i40evf_handle_aq_msg(dev); 1399 } 1400 1401 /* Link Status Change interrupt */ 1402 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK) 1403 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported," 1404 " do nothing"); 1405 1406 done: 1407 i40evf_enable_irq0(hw); 1408 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL, 1409 i40evf_dev_alarm_handler, dev); 1410 } 1411 1412 static int 1413 i40evf_dev_init(struct rte_eth_dev *eth_dev) 1414 { 1415 struct i40e_hw *hw 1416 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1417 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1418 1419 PMD_INIT_FUNC_TRACE(); 1420 1421 /* assign ops func pointer */ 1422 eth_dev->dev_ops = &i40evf_eth_dev_ops; 1423 eth_dev->rx_pkt_burst = &i40e_recv_pkts; 1424 eth_dev->tx_pkt_burst = &i40e_xmit_pkts; 1425 1426 /* 1427 * For secondary processes, we don't initialise any further as primary 1428 * has already done this work. 1429 */ 1430 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 1431 i40e_set_rx_function(eth_dev); 1432 i40e_set_tx_function(eth_dev); 1433 return 0; 1434 } 1435 i40e_set_default_ptype_table(eth_dev); 1436 i40e_set_default_pctype_table(eth_dev); 1437 rte_eth_copy_pci_info(eth_dev, pci_dev); 1438 1439 hw->vendor_id = pci_dev->id.vendor_id; 1440 hw->device_id = pci_dev->id.device_id; 1441 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1442 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 1443 hw->bus.device = pci_dev->addr.devid; 1444 hw->bus.func = pci_dev->addr.function; 1445 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1446 hw->adapter_stopped = 0; 1447 hw->adapter_closed = 0; 1448 1449 if(i40evf_init_vf(eth_dev) != 0) { 1450 PMD_INIT_LOG(ERR, "Init vf failed"); 1451 return -1; 1452 } 1453 1454 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL, 1455 i40evf_dev_alarm_handler, eth_dev); 1456 1457 /* configure and enable device interrupt */ 1458 i40evf_enable_irq0(hw); 1459 1460 /* copy mac addr */ 1461 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac", 1462 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX, 1463 0); 1464 if (eth_dev->data->mac_addrs == NULL) { 1465 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to" 1466 " store MAC addresses", 1467 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX); 1468 return -ENOMEM; 1469 } 1470 ether_addr_copy((struct ether_addr *)hw->mac.addr, 1471 ð_dev->data->mac_addrs[0]); 1472 1473 return 0; 1474 } 1475 1476 static int 1477 i40evf_dev_uninit(struct rte_eth_dev *eth_dev) 1478 { 1479 PMD_INIT_FUNC_TRACE(); 1480 1481 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1482 return -EPERM; 1483 1484 eth_dev->dev_ops = NULL; 1485 eth_dev->rx_pkt_burst = NULL; 1486 eth_dev->tx_pkt_burst = NULL; 1487 1488 if (i40evf_uninit_vf(eth_dev) != 0) { 1489 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed"); 1490 return -1; 1491 } 1492 1493 return 0; 1494 } 1495 1496 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1497 struct rte_pci_device *pci_dev) 1498 { 1499 return rte_eth_dev_pci_generic_probe(pci_dev, 1500 sizeof(struct i40e_adapter), i40evf_dev_init); 1501 } 1502 1503 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev) 1504 { 1505 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit); 1506 } 1507 1508 /* 1509 * virtual function driver struct 1510 */ 1511 static struct rte_pci_driver rte_i40evf_pmd = { 1512 .id_table = pci_id_i40evf_map, 1513 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, 1514 .probe = eth_i40evf_pci_probe, 1515 .remove = eth_i40evf_pci_remove, 1516 }; 1517 1518 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd); 1519 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map); 1520 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci"); 1521 1522 static int 1523 i40evf_dev_configure(struct rte_eth_dev *dev) 1524 { 1525 struct i40e_adapter *ad = 1526 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); 1527 1528 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk 1529 * allocation or vector Rx preconditions we will reset it. 1530 */ 1531 ad->rx_bulk_alloc_allowed = true; 1532 ad->rx_vec_allowed = true; 1533 ad->tx_simple_allowed = true; 1534 ad->tx_vec_allowed = true; 1535 1536 return i40evf_init_vlan(dev); 1537 } 1538 1539 static int 1540 i40evf_init_vlan(struct rte_eth_dev *dev) 1541 { 1542 /* Apply vlan offload setting */ 1543 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK); 1544 1545 return 0; 1546 } 1547 1548 static int 1549 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1550 { 1551 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1552 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1553 1554 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN)) 1555 return -ENOTSUP; 1556 1557 /* Vlan stripping setting */ 1558 if (mask & ETH_VLAN_STRIP_MASK) { 1559 /* Enable or disable VLAN stripping */ 1560 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1561 i40evf_enable_vlan_strip(dev); 1562 else 1563 i40evf_disable_vlan_strip(dev); 1564 } 1565 1566 return 0; 1567 } 1568 1569 static int 1570 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1571 { 1572 struct i40e_rx_queue *rxq; 1573 int err; 1574 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1575 1576 PMD_INIT_FUNC_TRACE(); 1577 1578 rxq = dev->data->rx_queues[rx_queue_id]; 1579 1580 err = i40e_alloc_rx_queue_mbufs(rxq); 1581 if (err) { 1582 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf"); 1583 return err; 1584 } 1585 1586 rte_wmb(); 1587 1588 /* Init the RX tail register. */ 1589 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); 1590 I40EVF_WRITE_FLUSH(hw); 1591 1592 /* Ready to switch the queue on */ 1593 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE); 1594 if (err) { 1595 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on", 1596 rx_queue_id); 1597 return err; 1598 } 1599 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 1600 1601 return 0; 1602 } 1603 1604 static int 1605 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1606 { 1607 struct i40e_rx_queue *rxq; 1608 int err; 1609 1610 rxq = dev->data->rx_queues[rx_queue_id]; 1611 1612 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE); 1613 if (err) { 1614 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off", 1615 rx_queue_id); 1616 return err; 1617 } 1618 1619 i40e_rx_queue_release_mbufs(rxq); 1620 i40e_reset_rx_queue(rxq); 1621 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 1622 1623 return 0; 1624 } 1625 1626 static int 1627 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) 1628 { 1629 int err; 1630 1631 PMD_INIT_FUNC_TRACE(); 1632 1633 /* Ready to switch the queue on */ 1634 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE); 1635 if (err) { 1636 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on", 1637 tx_queue_id); 1638 return err; 1639 } 1640 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 1641 1642 return 0; 1643 } 1644 1645 static int 1646 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) 1647 { 1648 struct i40e_tx_queue *txq; 1649 int err; 1650 1651 txq = dev->data->tx_queues[tx_queue_id]; 1652 1653 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE); 1654 if (err) { 1655 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off", 1656 tx_queue_id); 1657 return err; 1658 } 1659 1660 i40e_tx_queue_release_mbufs(txq); 1661 i40e_reset_tx_queue(txq); 1662 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 1663 1664 return 0; 1665 } 1666 1667 static int 1668 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1669 { 1670 int ret; 1671 1672 if (on) 1673 ret = i40evf_add_vlan(dev, vlan_id); 1674 else 1675 ret = i40evf_del_vlan(dev,vlan_id); 1676 1677 return ret; 1678 } 1679 1680 static int 1681 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq) 1682 { 1683 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1684 struct rte_eth_dev_data *dev_data = dev->data; 1685 struct rte_pktmbuf_pool_private *mbp_priv; 1686 uint16_t buf_size, len; 1687 1688 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id); 1689 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); 1690 I40EVF_WRITE_FLUSH(hw); 1691 1692 /* Calculate the maximum packet length allowed */ 1693 mbp_priv = rte_mempool_get_priv(rxq->mp); 1694 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size - 1695 RTE_PKTMBUF_HEADROOM); 1696 rxq->hs_mode = i40e_header_split_none; 1697 rxq->rx_hdr_len = 0; 1698 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT)); 1699 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS; 1700 rxq->max_pkt_len = RTE_MIN(len, 1701 dev_data->dev_conf.rxmode.max_rx_pkt_len); 1702 1703 /** 1704 * Check if the jumbo frame and maximum packet length are set correctly 1705 */ 1706 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1707 if (rxq->max_pkt_len <= ETHER_MAX_LEN || 1708 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) { 1709 PMD_DRV_LOG(ERR, "maximum packet length must be " 1710 "larger than %u and smaller than %u, as jumbo " 1711 "frame is enabled", (uint32_t)ETHER_MAX_LEN, 1712 (uint32_t)I40E_FRAME_SIZE_MAX); 1713 return I40E_ERR_CONFIG; 1714 } 1715 } else { 1716 if (rxq->max_pkt_len < ETHER_MIN_LEN || 1717 rxq->max_pkt_len > ETHER_MAX_LEN) { 1718 PMD_DRV_LOG(ERR, "maximum packet length must be " 1719 "larger than %u and smaller than %u, as jumbo " 1720 "frame is disabled", (uint32_t)ETHER_MIN_LEN, 1721 (uint32_t)ETHER_MAX_LEN); 1722 return I40E_ERR_CONFIG; 1723 } 1724 } 1725 1726 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) || 1727 rxq->max_pkt_len > buf_size) 1728 dev_data->scattered_rx = 1; 1729 1730 return 0; 1731 } 1732 1733 static int 1734 i40evf_rx_init(struct rte_eth_dev *dev) 1735 { 1736 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1737 uint16_t i; 1738 int ret = I40E_SUCCESS; 1739 struct i40e_rx_queue **rxq = 1740 (struct i40e_rx_queue **)dev->data->rx_queues; 1741 1742 i40evf_config_rss(vf); 1743 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1744 if (!rxq[i] || !rxq[i]->q_set) 1745 continue; 1746 ret = i40evf_rxq_init(dev, rxq[i]); 1747 if (ret != I40E_SUCCESS) 1748 break; 1749 } 1750 if (ret == I40E_SUCCESS) 1751 i40e_set_rx_function(dev); 1752 1753 return ret; 1754 } 1755 1756 static void 1757 i40evf_tx_init(struct rte_eth_dev *dev) 1758 { 1759 uint16_t i; 1760 struct i40e_tx_queue **txq = 1761 (struct i40e_tx_queue **)dev->data->tx_queues; 1762 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1763 1764 for (i = 0; i < dev->data->nb_tx_queues; i++) 1765 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i); 1766 1767 i40e_set_tx_function(dev); 1768 } 1769 1770 static inline void 1771 i40evf_enable_queues_intr(struct rte_eth_dev *dev) 1772 { 1773 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1774 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1775 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1776 1777 if (!rte_intr_allow_others(intr_handle)) { 1778 I40E_WRITE_REG(hw, 1779 I40E_VFINT_DYN_CTL01, 1780 I40E_VFINT_DYN_CTL01_INTENA_MASK | 1781 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK | 1782 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); 1783 I40EVF_WRITE_FLUSH(hw); 1784 return; 1785 } 1786 1787 I40EVF_WRITE_FLUSH(hw); 1788 } 1789 1790 static inline void 1791 i40evf_disable_queues_intr(struct rte_eth_dev *dev) 1792 { 1793 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1794 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1795 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1796 1797 if (!rte_intr_allow_others(intr_handle)) { 1798 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 1799 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); 1800 I40EVF_WRITE_FLUSH(hw); 1801 return; 1802 } 1803 1804 I40EVF_WRITE_FLUSH(hw); 1805 } 1806 1807 static int 1808 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 1809 { 1810 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1811 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1812 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1813 uint16_t interval = 1814 i40e_calc_itr_interval(0, 0); 1815 uint16_t msix_intr; 1816 1817 msix_intr = intr_handle->intr_vec[queue_id]; 1818 if (msix_intr == I40E_MISC_VEC_ID) 1819 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 1820 I40E_VFINT_DYN_CTL01_INTENA_MASK | 1821 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK | 1822 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) | 1823 (interval << 1824 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)); 1825 else 1826 I40E_WRITE_REG(hw, 1827 I40E_VFINT_DYN_CTLN1(msix_intr - 1828 I40E_RX_VEC_START), 1829 I40E_VFINT_DYN_CTLN1_INTENA_MASK | 1830 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK | 1831 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | 1832 (interval << 1833 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)); 1834 1835 I40EVF_WRITE_FLUSH(hw); 1836 1837 return 0; 1838 } 1839 1840 static int 1841 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 1842 { 1843 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1844 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1845 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1846 uint16_t msix_intr; 1847 1848 msix_intr = intr_handle->intr_vec[queue_id]; 1849 if (msix_intr == I40E_MISC_VEC_ID) 1850 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0); 1851 else 1852 I40E_WRITE_REG(hw, 1853 I40E_VFINT_DYN_CTLN1(msix_intr - 1854 I40E_RX_VEC_START), 1855 0); 1856 1857 I40EVF_WRITE_FLUSH(hw); 1858 1859 return 0; 1860 } 1861 1862 static void 1863 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add) 1864 { 1865 struct virtchnl_ether_addr_list *list; 1866 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1867 int err, i, j; 1868 int next_begin = 0; 1869 int begin = 0; 1870 uint32_t len; 1871 struct ether_addr *addr; 1872 struct vf_cmd_info args; 1873 1874 do { 1875 j = 0; 1876 len = sizeof(struct virtchnl_ether_addr_list); 1877 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) { 1878 if (is_zero_ether_addr(&dev->data->mac_addrs[i])) 1879 continue; 1880 len += sizeof(struct virtchnl_ether_addr); 1881 if (len >= I40E_AQ_BUF_SZ) { 1882 next_begin = i + 1; 1883 break; 1884 } 1885 } 1886 1887 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0); 1888 if (!list) { 1889 PMD_DRV_LOG(ERR, "fail to allocate memory"); 1890 return; 1891 } 1892 1893 for (i = begin; i < next_begin; i++) { 1894 addr = &dev->data->mac_addrs[i]; 1895 if (is_zero_ether_addr(addr)) 1896 continue; 1897 rte_memcpy(list->list[j].addr, addr->addr_bytes, 1898 sizeof(addr->addr_bytes)); 1899 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x", 1900 addr->addr_bytes[0], addr->addr_bytes[1], 1901 addr->addr_bytes[2], addr->addr_bytes[3], 1902 addr->addr_bytes[4], addr->addr_bytes[5]); 1903 j++; 1904 } 1905 list->vsi_id = vf->vsi_res->vsi_id; 1906 list->num_elements = j; 1907 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : 1908 VIRTCHNL_OP_DEL_ETH_ADDR; 1909 args.in_args = (uint8_t *)list; 1910 args.in_args_size = len; 1911 args.out_buffer = vf->aq_resp; 1912 args.out_size = I40E_AQ_BUF_SZ; 1913 err = i40evf_execute_vf_cmd(dev, &args); 1914 if (err) { 1915 PMD_DRV_LOG(ERR, "fail to execute command %s", 1916 add ? "OP_ADD_ETHER_ADDRESS" : 1917 "OP_DEL_ETHER_ADDRESS"); 1918 } else { 1919 if (add) 1920 vf->vsi.mac_num++; 1921 else 1922 vf->vsi.mac_num--; 1923 } 1924 rte_free(list); 1925 begin = next_begin; 1926 } while (begin < I40E_NUM_MACADDR_MAX); 1927 } 1928 1929 static int 1930 i40evf_dev_start(struct rte_eth_dev *dev) 1931 { 1932 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 1933 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1934 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1935 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1936 uint32_t intr_vector = 0; 1937 1938 PMD_INIT_FUNC_TRACE(); 1939 1940 hw->adapter_stopped = 0; 1941 1942 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 1943 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues, 1944 dev->data->nb_tx_queues); 1945 1946 /* check and configure queue intr-vector mapping */ 1947 if (rte_intr_cap_multiple(intr_handle) && 1948 dev->data->dev_conf.intr_conf.rxq) { 1949 intr_vector = dev->data->nb_rx_queues; 1950 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1951 return -1; 1952 } 1953 1954 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1955 intr_handle->intr_vec = 1956 rte_zmalloc("intr_vec", 1957 dev->data->nb_rx_queues * sizeof(int), 0); 1958 if (!intr_handle->intr_vec) { 1959 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 1960 " intr_vec", dev->data->nb_rx_queues); 1961 return -ENOMEM; 1962 } 1963 } 1964 1965 if (i40evf_rx_init(dev) != 0){ 1966 PMD_DRV_LOG(ERR, "failed to do RX init"); 1967 return -1; 1968 } 1969 1970 i40evf_tx_init(dev); 1971 1972 if (i40evf_configure_vsi_queues(dev) != 0) { 1973 PMD_DRV_LOG(ERR, "configure queues failed"); 1974 goto err_queue; 1975 } 1976 if (i40evf_config_irq_map(dev)) { 1977 PMD_DRV_LOG(ERR, "config_irq_map failed"); 1978 goto err_queue; 1979 } 1980 1981 /* Set all mac addrs */ 1982 i40evf_add_del_all_mac_addr(dev, TRUE); 1983 /* Set all multicast addresses */ 1984 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num, 1985 TRUE); 1986 1987 if (i40evf_start_queues(dev) != 0) { 1988 PMD_DRV_LOG(ERR, "enable queues failed"); 1989 goto err_mac; 1990 } 1991 1992 /* only enable interrupt in rx interrupt mode */ 1993 if (dev->data->dev_conf.intr_conf.rxq != 0) 1994 rte_intr_enable(intr_handle); 1995 1996 i40evf_enable_queues_intr(dev); 1997 1998 return 0; 1999 2000 err_mac: 2001 i40evf_add_del_all_mac_addr(dev, FALSE); 2002 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num, 2003 FALSE); 2004 err_queue: 2005 return -1; 2006 } 2007 2008 static void 2009 i40evf_dev_stop(struct rte_eth_dev *dev) 2010 { 2011 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2012 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2013 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2014 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2015 2016 PMD_INIT_FUNC_TRACE(); 2017 2018 if (dev->data->dev_conf.intr_conf.rxq != 0) 2019 rte_intr_disable(intr_handle); 2020 2021 if (hw->adapter_stopped == 1) 2022 return; 2023 i40evf_stop_queues(dev); 2024 i40evf_disable_queues_intr(dev); 2025 i40e_dev_clear_queues(dev); 2026 2027 /* Clean datapath event and queue/vec mapping */ 2028 rte_intr_efd_disable(intr_handle); 2029 if (intr_handle->intr_vec) { 2030 rte_free(intr_handle->intr_vec); 2031 intr_handle->intr_vec = NULL; 2032 } 2033 /* remove all mac addrs */ 2034 i40evf_add_del_all_mac_addr(dev, FALSE); 2035 /* remove all multicast addresses */ 2036 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num, 2037 FALSE); 2038 hw->adapter_stopped = 1; 2039 2040 } 2041 2042 static int 2043 i40evf_dev_link_update(struct rte_eth_dev *dev, 2044 __rte_unused int wait_to_complete) 2045 { 2046 struct rte_eth_link new_link; 2047 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2048 /* 2049 * DPDK pf host provide interfacet to acquire link status 2050 * while Linux driver does not 2051 */ 2052 2053 memset(&new_link, 0, sizeof(new_link)); 2054 /* Linux driver PF host */ 2055 switch (vf->link_speed) { 2056 case I40E_LINK_SPEED_100MB: 2057 new_link.link_speed = ETH_SPEED_NUM_100M; 2058 break; 2059 case I40E_LINK_SPEED_1GB: 2060 new_link.link_speed = ETH_SPEED_NUM_1G; 2061 break; 2062 case I40E_LINK_SPEED_10GB: 2063 new_link.link_speed = ETH_SPEED_NUM_10G; 2064 break; 2065 case I40E_LINK_SPEED_20GB: 2066 new_link.link_speed = ETH_SPEED_NUM_20G; 2067 break; 2068 case I40E_LINK_SPEED_25GB: 2069 new_link.link_speed = ETH_SPEED_NUM_25G; 2070 break; 2071 case I40E_LINK_SPEED_40GB: 2072 new_link.link_speed = ETH_SPEED_NUM_40G; 2073 break; 2074 default: 2075 new_link.link_speed = ETH_SPEED_NUM_100M; 2076 break; 2077 } 2078 /* full duplex only */ 2079 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 2080 new_link.link_status = vf->link_up ? ETH_LINK_UP : 2081 ETH_LINK_DOWN; 2082 new_link.link_autoneg = 2083 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2084 2085 return rte_eth_linkstatus_set(dev, &new_link); 2086 } 2087 2088 static void 2089 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev) 2090 { 2091 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2092 int ret; 2093 2094 /* If enabled, just return */ 2095 if (vf->promisc_unicast_enabled) 2096 return; 2097 2098 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled); 2099 if (ret == 0) 2100 vf->promisc_unicast_enabled = TRUE; 2101 } 2102 2103 static void 2104 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev) 2105 { 2106 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2107 int ret; 2108 2109 /* If disabled, just return */ 2110 if (!vf->promisc_unicast_enabled) 2111 return; 2112 2113 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled); 2114 if (ret == 0) 2115 vf->promisc_unicast_enabled = FALSE; 2116 } 2117 2118 static void 2119 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev) 2120 { 2121 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2122 int ret; 2123 2124 /* If enabled, just return */ 2125 if (vf->promisc_multicast_enabled) 2126 return; 2127 2128 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1); 2129 if (ret == 0) 2130 vf->promisc_multicast_enabled = TRUE; 2131 } 2132 2133 static void 2134 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev) 2135 { 2136 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2137 int ret; 2138 2139 /* If enabled, just return */ 2140 if (!vf->promisc_multicast_enabled) 2141 return; 2142 2143 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0); 2144 if (ret == 0) 2145 vf->promisc_multicast_enabled = FALSE; 2146 } 2147 2148 static void 2149 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2150 { 2151 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2152 2153 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs; 2154 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs; 2155 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN; 2156 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX; 2157 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2158 dev_info->reta_size = ETH_RSS_RETA_SIZE_64; 2159 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask; 2160 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX; 2161 dev_info->rx_queue_offload_capa = 0; 2162 dev_info->rx_offload_capa = 2163 DEV_RX_OFFLOAD_VLAN_STRIP | 2164 DEV_RX_OFFLOAD_QINQ_STRIP | 2165 DEV_RX_OFFLOAD_IPV4_CKSUM | 2166 DEV_RX_OFFLOAD_UDP_CKSUM | 2167 DEV_RX_OFFLOAD_TCP_CKSUM | 2168 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2169 DEV_RX_OFFLOAD_SCATTER | 2170 DEV_RX_OFFLOAD_JUMBO_FRAME | 2171 DEV_RX_OFFLOAD_VLAN_FILTER; 2172 2173 dev_info->tx_queue_offload_capa = 0; 2174 dev_info->tx_offload_capa = 2175 DEV_TX_OFFLOAD_VLAN_INSERT | 2176 DEV_TX_OFFLOAD_QINQ_INSERT | 2177 DEV_TX_OFFLOAD_IPV4_CKSUM | 2178 DEV_TX_OFFLOAD_UDP_CKSUM | 2179 DEV_TX_OFFLOAD_TCP_CKSUM | 2180 DEV_TX_OFFLOAD_SCTP_CKSUM | 2181 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2182 DEV_TX_OFFLOAD_TCP_TSO | 2183 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 2184 DEV_TX_OFFLOAD_GRE_TNL_TSO | 2185 DEV_TX_OFFLOAD_IPIP_TNL_TSO | 2186 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 2187 DEV_TX_OFFLOAD_MULTI_SEGS; 2188 2189 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2190 .rx_thresh = { 2191 .pthresh = I40E_DEFAULT_RX_PTHRESH, 2192 .hthresh = I40E_DEFAULT_RX_HTHRESH, 2193 .wthresh = I40E_DEFAULT_RX_WTHRESH, 2194 }, 2195 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH, 2196 .rx_drop_en = 0, 2197 .offloads = 0, 2198 }; 2199 2200 dev_info->default_txconf = (struct rte_eth_txconf) { 2201 .tx_thresh = { 2202 .pthresh = I40E_DEFAULT_TX_PTHRESH, 2203 .hthresh = I40E_DEFAULT_TX_HTHRESH, 2204 .wthresh = I40E_DEFAULT_TX_WTHRESH, 2205 }, 2206 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH, 2207 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH, 2208 .offloads = 0, 2209 }; 2210 2211 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 2212 .nb_max = I40E_MAX_RING_DESC, 2213 .nb_min = I40E_MIN_RING_DESC, 2214 .nb_align = I40E_ALIGN_RING_DESC, 2215 }; 2216 2217 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 2218 .nb_max = I40E_MAX_RING_DESC, 2219 .nb_min = I40E_MIN_RING_DESC, 2220 .nb_align = I40E_ALIGN_RING_DESC, 2221 }; 2222 } 2223 2224 static int 2225 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 2226 { 2227 int ret; 2228 struct i40e_eth_stats *pstats = NULL; 2229 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2230 struct i40e_vsi *vsi = &vf->vsi; 2231 2232 ret = i40evf_query_stats(dev, &pstats); 2233 if (ret == 0) { 2234 i40evf_update_stats(vsi, pstats); 2235 2236 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast + 2237 pstats->rx_broadcast; 2238 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast + 2239 pstats->tx_unicast; 2240 stats->imissed = pstats->rx_discards; 2241 stats->oerrors = pstats->tx_errors + pstats->tx_discards; 2242 stats->ibytes = pstats->rx_bytes; 2243 stats->obytes = pstats->tx_bytes; 2244 } else { 2245 PMD_DRV_LOG(ERR, "Get statistics failed"); 2246 } 2247 return ret; 2248 } 2249 2250 static void 2251 i40evf_dev_close(struct rte_eth_dev *dev) 2252 { 2253 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2254 2255 i40evf_dev_stop(dev); 2256 i40e_dev_free_queues(dev); 2257 /* 2258 * disable promiscuous mode before reset vf 2259 * it is a workaround solution when work with kernel driver 2260 * and it is not the normal way 2261 */ 2262 i40evf_dev_promiscuous_disable(dev); 2263 i40evf_dev_allmulticast_disable(dev); 2264 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev); 2265 2266 i40evf_reset_vf(dev); 2267 i40e_shutdown_adminq(hw); 2268 i40evf_disable_irq0(hw); 2269 hw->adapter_closed = 1; 2270 } 2271 2272 /* 2273 * Reset VF device only to re-initialize resources in PMD layer 2274 */ 2275 static int 2276 i40evf_dev_reset(struct rte_eth_dev *dev) 2277 { 2278 int ret; 2279 2280 ret = i40evf_dev_uninit(dev); 2281 if (ret) 2282 return ret; 2283 2284 ret = i40evf_dev_init(dev); 2285 2286 return ret; 2287 } 2288 2289 static int 2290 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2291 { 2292 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi); 2293 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2294 int ret; 2295 2296 if (!lut) 2297 return -EINVAL; 2298 2299 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 2300 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE, 2301 lut, lut_size); 2302 if (ret) { 2303 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); 2304 return ret; 2305 } 2306 } else { 2307 uint32_t *lut_dw = (uint32_t *)lut; 2308 uint16_t i, lut_size_dw = lut_size / 4; 2309 2310 for (i = 0; i < lut_size_dw; i++) 2311 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i)); 2312 } 2313 2314 return 0; 2315 } 2316 2317 static int 2318 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) 2319 { 2320 struct i40e_vf *vf; 2321 struct i40e_hw *hw; 2322 int ret; 2323 2324 if (!vsi || !lut) 2325 return -EINVAL; 2326 2327 vf = I40E_VSI_TO_VF(vsi); 2328 hw = I40E_VSI_TO_HW(vsi); 2329 2330 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 2331 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE, 2332 lut, lut_size); 2333 if (ret) { 2334 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); 2335 return ret; 2336 } 2337 } else { 2338 uint32_t *lut_dw = (uint32_t *)lut; 2339 uint16_t i, lut_size_dw = lut_size / 4; 2340 2341 for (i = 0; i < lut_size_dw; i++) 2342 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]); 2343 I40EVF_WRITE_FLUSH(hw); 2344 } 2345 2346 return 0; 2347 } 2348 2349 static int 2350 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev, 2351 struct rte_eth_rss_reta_entry64 *reta_conf, 2352 uint16_t reta_size) 2353 { 2354 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2355 uint8_t *lut; 2356 uint16_t i, idx, shift; 2357 int ret; 2358 2359 if (reta_size != ETH_RSS_RETA_SIZE_64) { 2360 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 2361 "(%d) doesn't match the number of hardware can " 2362 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64); 2363 return -EINVAL; 2364 } 2365 2366 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 2367 if (!lut) { 2368 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2369 return -ENOMEM; 2370 } 2371 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size); 2372 if (ret) 2373 goto out; 2374 for (i = 0; i < reta_size; i++) { 2375 idx = i / RTE_RETA_GROUP_SIZE; 2376 shift = i % RTE_RETA_GROUP_SIZE; 2377 if (reta_conf[idx].mask & (1ULL << shift)) 2378 lut[i] = reta_conf[idx].reta[shift]; 2379 } 2380 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size); 2381 2382 out: 2383 rte_free(lut); 2384 2385 return ret; 2386 } 2387 2388 static int 2389 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev, 2390 struct rte_eth_rss_reta_entry64 *reta_conf, 2391 uint16_t reta_size) 2392 { 2393 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2394 uint16_t i, idx, shift; 2395 uint8_t *lut; 2396 int ret; 2397 2398 if (reta_size != ETH_RSS_RETA_SIZE_64) { 2399 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 2400 "(%d) doesn't match the number of hardware can " 2401 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64); 2402 return -EINVAL; 2403 } 2404 2405 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); 2406 if (!lut) { 2407 PMD_DRV_LOG(ERR, "No memory can be allocated"); 2408 return -ENOMEM; 2409 } 2410 2411 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size); 2412 if (ret) 2413 goto out; 2414 for (i = 0; i < reta_size; i++) { 2415 idx = i / RTE_RETA_GROUP_SIZE; 2416 shift = i % RTE_RETA_GROUP_SIZE; 2417 if (reta_conf[idx].mask & (1ULL << shift)) 2418 reta_conf[idx].reta[shift] = lut[i]; 2419 } 2420 2421 out: 2422 rte_free(lut); 2423 2424 return ret; 2425 } 2426 2427 static int 2428 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len) 2429 { 2430 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi); 2431 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2432 int ret = 0; 2433 2434 if (!key || key_len == 0) { 2435 PMD_DRV_LOG(DEBUG, "No key to be configured"); 2436 return 0; 2437 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) * 2438 sizeof(uint32_t)) { 2439 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); 2440 return -EINVAL; 2441 } 2442 2443 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 2444 struct i40e_aqc_get_set_rss_key_data *key_dw = 2445 (struct i40e_aqc_get_set_rss_key_data *)key; 2446 2447 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw); 2448 if (ret) 2449 PMD_INIT_LOG(ERR, "Failed to configure RSS key " 2450 "via AQ"); 2451 } else { 2452 uint32_t *hash_key = (uint32_t *)key; 2453 uint16_t i; 2454 2455 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) 2456 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]); 2457 I40EVF_WRITE_FLUSH(hw); 2458 } 2459 2460 return ret; 2461 } 2462 2463 static int 2464 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len) 2465 { 2466 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi); 2467 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); 2468 int ret; 2469 2470 if (!key || !key_len) 2471 return -EINVAL; 2472 2473 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { 2474 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id, 2475 (struct i40e_aqc_get_set_rss_key_data *)key); 2476 if (ret) { 2477 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ"); 2478 return ret; 2479 } 2480 } else { 2481 uint32_t *key_dw = (uint32_t *)key; 2482 uint16_t i; 2483 2484 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) 2485 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i)); 2486 } 2487 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); 2488 2489 return 0; 2490 } 2491 2492 static int 2493 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf) 2494 { 2495 struct i40e_hw *hw = I40E_VF_TO_HW(vf); 2496 uint64_t hena; 2497 int ret; 2498 2499 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key, 2500 rss_conf->rss_key_len); 2501 if (ret) 2502 return ret; 2503 2504 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf); 2505 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena); 2506 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32)); 2507 I40EVF_WRITE_FLUSH(hw); 2508 2509 return 0; 2510 } 2511 2512 static void 2513 i40evf_disable_rss(struct i40e_vf *vf) 2514 { 2515 struct i40e_hw *hw = I40E_VF_TO_HW(vf); 2516 2517 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0); 2518 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0); 2519 I40EVF_WRITE_FLUSH(hw); 2520 } 2521 2522 static int 2523 i40evf_config_rss(struct i40e_vf *vf) 2524 { 2525 struct i40e_hw *hw = I40E_VF_TO_HW(vf); 2526 struct rte_eth_rss_conf rss_conf; 2527 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4; 2528 uint16_t num; 2529 2530 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { 2531 i40evf_disable_rss(vf); 2532 PMD_DRV_LOG(DEBUG, "RSS not configured"); 2533 return 0; 2534 } 2535 2536 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF); 2537 /* Fill out the look up table */ 2538 for (i = 0, j = 0; i < nb_q; i++, j++) { 2539 if (j >= num) 2540 j = 0; 2541 lut = (lut << 8) | j; 2542 if ((i & 3) == 3) 2543 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut); 2544 } 2545 2546 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf; 2547 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) { 2548 i40evf_disable_rss(vf); 2549 PMD_DRV_LOG(DEBUG, "No hash flag is set"); 2550 return 0; 2551 } 2552 2553 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < 2554 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { 2555 /* Calculate the default hash key */ 2556 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) 2557 rss_key_default[i] = (uint32_t)rte_rand(); 2558 rss_conf.rss_key = (uint8_t *)rss_key_default; 2559 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * 2560 sizeof(uint32_t); 2561 } 2562 2563 return i40evf_hw_rss_hash_set(vf, &rss_conf); 2564 } 2565 2566 static int 2567 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev, 2568 struct rte_eth_rss_conf *rss_conf) 2569 { 2570 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2571 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2572 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask; 2573 uint64_t hena; 2574 2575 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); 2576 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; 2577 2578 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */ 2579 if (rss_hf != 0) /* Enable RSS */ 2580 return -EINVAL; 2581 return 0; 2582 } 2583 2584 /* RSS enabled */ 2585 if (rss_hf == 0) /* Disable RSS */ 2586 return -EINVAL; 2587 2588 return i40evf_hw_rss_hash_set(vf, rss_conf); 2589 } 2590 2591 static int 2592 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2593 struct rte_eth_rss_conf *rss_conf) 2594 { 2595 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2596 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2597 uint64_t hena; 2598 2599 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key, 2600 &rss_conf->rss_key_len); 2601 2602 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); 2603 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; 2604 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena); 2605 2606 return 0; 2607 } 2608 2609 static int 2610 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2611 { 2612 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2613 struct rte_eth_dev_data *dev_data = vf->dev_data; 2614 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD; 2615 int ret = 0; 2616 2617 /* check if mtu is within the allowed range */ 2618 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX)) 2619 return -EINVAL; 2620 2621 /* mtu setting is forbidden if port is start */ 2622 if (dev_data->dev_started) { 2623 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 2624 dev_data->port_id); 2625 return -EBUSY; 2626 } 2627 2628 if (frame_size > ETHER_MAX_LEN) 2629 dev_data->dev_conf.rxmode.offloads |= 2630 DEV_RX_OFFLOAD_JUMBO_FRAME; 2631 else 2632 dev_data->dev_conf.rxmode.offloads &= 2633 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2634 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2635 2636 return ret; 2637 } 2638 2639 static int 2640 i40evf_set_default_mac_addr(struct rte_eth_dev *dev, 2641 struct ether_addr *mac_addr) 2642 { 2643 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2645 2646 if (!is_valid_assigned_ether_addr(mac_addr)) { 2647 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address."); 2648 return -EINVAL; 2649 } 2650 2651 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF) 2652 return -EPERM; 2653 2654 i40evf_del_mac_addr_by_addr(dev, (struct ether_addr *)hw->mac.addr); 2655 2656 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0) 2657 return -EIO; 2658 2659 ether_addr_copy(mac_addr, (struct ether_addr *)hw->mac.addr); 2660 return 0; 2661 } 2662 2663 static int 2664 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev, 2665 struct ether_addr *mc_addrs, 2666 uint32_t mc_addrs_num, bool add) 2667 { 2668 struct virtchnl_ether_addr_list *list; 2669 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2670 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + 2671 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))]; 2672 uint32_t i; 2673 int err; 2674 struct vf_cmd_info args; 2675 2676 if (mc_addrs == NULL || mc_addrs_num == 0) 2677 return 0; 2678 2679 if (mc_addrs_num > I40E_NUM_MACADDR_MAX) 2680 return -EINVAL; 2681 2682 list = (struct virtchnl_ether_addr_list *)cmd_buffer; 2683 list->vsi_id = vf->vsi_res->vsi_id; 2684 list->num_elements = mc_addrs_num; 2685 2686 for (i = 0; i < mc_addrs_num; i++) { 2687 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) { 2688 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x", 2689 mc_addrs[i].addr_bytes[0], 2690 mc_addrs[i].addr_bytes[1], 2691 mc_addrs[i].addr_bytes[2], 2692 mc_addrs[i].addr_bytes[3], 2693 mc_addrs[i].addr_bytes[4], 2694 mc_addrs[i].addr_bytes[5]); 2695 return -EINVAL; 2696 } 2697 2698 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes, 2699 sizeof(list->list[i].addr)); 2700 } 2701 2702 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR; 2703 args.in_args = cmd_buffer; 2704 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) + 2705 i * sizeof(struct virtchnl_ether_addr); 2706 args.out_buffer = vf->aq_resp; 2707 args.out_size = I40E_AQ_BUF_SZ; 2708 err = i40evf_execute_vf_cmd(dev, &args); 2709 if (err) { 2710 PMD_DRV_LOG(ERR, "fail to execute command %s", 2711 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR"); 2712 return err; 2713 } 2714 2715 return 0; 2716 } 2717 2718 static int 2719 i40evf_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addrs, 2720 uint32_t mc_addrs_num) 2721 { 2722 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); 2723 int err; 2724 2725 /* flush previous addresses */ 2726 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num, 2727 FALSE); 2728 if (err) 2729 return err; 2730 2731 vf->mc_addrs_num = 0; 2732 2733 /* add new ones */ 2734 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num, 2735 TRUE); 2736 if (err) 2737 return err; 2738 2739 vf->mc_addrs_num = mc_addrs_num; 2740 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs)); 2741 2742 return 0; 2743 } 2744