1 /******************************************************************************* 2 3 Copyright (c) 2013 - 2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 #ifndef _I40E_DCB_H_ 35 #define _I40E_DCB_H_ 36 37 #include "i40e_type.h" 38 39 #define I40E_DCBX_OFFLOAD_DISABLED 0 40 #define I40E_DCBX_OFFLOAD_ENABLED 1 41 42 #define I40E_DCBX_STATUS_NOT_STARTED 0 43 #define I40E_DCBX_STATUS_IN_PROGRESS 1 44 #define I40E_DCBX_STATUS_DONE 2 45 #define I40E_DCBX_STATUS_MULTIPLE_PEERS 3 46 #define I40E_DCBX_STATUS_DISABLED 7 47 48 #define I40E_TLV_TYPE_END 0 49 #define I40E_TLV_TYPE_ORG 127 50 51 #define I40E_IEEE_8021QAZ_OUI 0x0080C2 52 #define I40E_IEEE_SUBTYPE_ETS_CFG 9 53 #define I40E_IEEE_SUBTYPE_ETS_REC 10 54 #define I40E_IEEE_SUBTYPE_PFC_CFG 11 55 #define I40E_IEEE_SUBTYPE_APP_PRI 12 56 57 #define I40E_CEE_DCBX_OUI 0x001b21 58 #define I40E_CEE_DCBX_TYPE 2 59 60 #define I40E_CEE_SUBTYPE_CTRL 1 61 #define I40E_CEE_SUBTYPE_PG_CFG 2 62 #define I40E_CEE_SUBTYPE_PFC_CFG 3 63 #define I40E_CEE_SUBTYPE_APP_PRI 4 64 65 #define I40E_CEE_MAX_FEAT_TYPE 3 66 #define I40E_LLDP_ADMINSTATUS_DISABLED 0 67 #define I40E_LLDP_ADMINSTATUS_ENABLED_RX 1 68 #define I40E_LLDP_ADMINSTATUS_ENABLED_TX 2 69 #define I40E_LLDP_ADMINSTATUS_ENABLED_RXTX 3 70 71 /* Defines for LLDP TLV header */ 72 #define I40E_LLDP_MIB_HLEN 14 73 #define I40E_LLDP_TLV_LEN_SHIFT 0 74 #define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT) 75 #define I40E_LLDP_TLV_TYPE_SHIFT 9 76 #define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT) 77 #define I40E_LLDP_TLV_SUBTYPE_SHIFT 0 78 #define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT) 79 #define I40E_LLDP_TLV_OUI_SHIFT 8 80 #define I40E_LLDP_TLV_OUI_MASK (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT) 81 82 /* Defines for IEEE ETS TLV */ 83 #define I40E_IEEE_ETS_MAXTC_SHIFT 0 84 #define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT) 85 #define I40E_IEEE_ETS_CBS_SHIFT 6 86 #define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT) 87 #define I40E_IEEE_ETS_WILLING_SHIFT 7 88 #define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT) 89 #define I40E_IEEE_ETS_PRIO_0_SHIFT 0 90 #define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT) 91 #define I40E_IEEE_ETS_PRIO_1_SHIFT 4 92 #define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT) 93 #define I40E_CEE_PGID_PRIO_0_SHIFT 0 94 #define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT) 95 #define I40E_CEE_PGID_PRIO_1_SHIFT 4 96 #define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT) 97 #define I40E_CEE_PGID_STRICT 15 98 99 /* Defines for IEEE TSA types */ 100 #define I40E_IEEE_TSA_STRICT 0 101 #define I40E_IEEE_TSA_CBS 1 102 #define I40E_IEEE_TSA_ETS 2 103 #define I40E_IEEE_TSA_VENDOR 255 104 105 /* Defines for IEEE PFC TLV */ 106 #define I40E_IEEE_PFC_CAP_SHIFT 0 107 #define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT) 108 #define I40E_IEEE_PFC_MBC_SHIFT 6 109 #define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT) 110 #define I40E_IEEE_PFC_WILLING_SHIFT 7 111 #define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT) 112 113 /* Defines for IEEE APP TLV */ 114 #define I40E_IEEE_APP_SEL_SHIFT 0 115 #define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT) 116 #define I40E_IEEE_APP_PRIO_SHIFT 5 117 #define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT) 118 119 /* TLV definitions for preparing MIB */ 120 #define I40E_TLV_ID_CHASSIS_ID 0 121 #define I40E_TLV_ID_PORT_ID 1 122 #define I40E_TLV_ID_TIME_TO_LIVE 2 123 #define I40E_IEEE_TLV_ID_ETS_CFG 3 124 #define I40E_IEEE_TLV_ID_ETS_REC 4 125 #define I40E_IEEE_TLV_ID_PFC_CFG 5 126 #define I40E_IEEE_TLV_ID_APP_PRI 6 127 #define I40E_TLV_ID_END_OF_LLDPPDU 7 128 #define I40E_TLV_ID_START I40E_IEEE_TLV_ID_ETS_CFG 129 130 #define I40E_IEEE_ETS_TLV_LENGTH 25 131 #define I40E_IEEE_PFC_TLV_LENGTH 6 132 #define I40E_IEEE_APP_TLV_LENGTH 11 133 134 #pragma pack(1) 135 136 /* IEEE 802.1AB LLDP TLV structure */ 137 struct i40e_lldp_generic_tlv { 138 __be16 typelength; 139 u8 tlvinfo[1]; 140 }; 141 142 /* IEEE 802.1AB LLDP Organization specific TLV */ 143 struct i40e_lldp_org_tlv { 144 __be16 typelength; 145 __be32 ouisubtype; 146 u8 tlvinfo[1]; 147 }; 148 149 struct i40e_cee_tlv_hdr { 150 __be16 typelen; 151 u8 operver; 152 u8 maxver; 153 }; 154 155 struct i40e_cee_ctrl_tlv { 156 struct i40e_cee_tlv_hdr hdr; 157 __be32 seqno; 158 __be32 ackno; 159 }; 160 161 struct i40e_cee_feat_tlv { 162 struct i40e_cee_tlv_hdr hdr; 163 u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */ 164 #define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80 165 #define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40 166 #define I40E_CEE_FEAT_TLV_ERR_MASK 0x20 167 u8 subtype; 168 u8 tlvinfo[1]; 169 }; 170 171 struct i40e_cee_app_prio { 172 __be16 protocol; 173 u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */ 174 #define I40E_CEE_APP_SELECTOR_MASK 0x03 175 __be16 lower_oui; 176 u8 prio_map; 177 }; 178 #pragma pack() 179 180 /* 181 * TODO: The below structures related LLDP/DCBX variables 182 * and statistics are defined but need to find how to get 183 * the required information from the Firmware to use them 184 */ 185 186 /* IEEE 802.1AB LLDP Agent Statistics */ 187 struct i40e_lldp_stats { 188 u64 remtablelastchangetime; 189 u64 remtableinserts; 190 u64 remtabledeletes; 191 u64 remtabledrops; 192 u64 remtableageouts; 193 u64 txframestotal; 194 u64 rxframesdiscarded; 195 u64 rxportframeerrors; 196 u64 rxportframestotal; 197 u64 rxporttlvsdiscardedtotal; 198 u64 rxporttlvsunrecognizedtotal; 199 u64 remtoomanyneighbors; 200 }; 201 202 /* IEEE 802.1Qaz DCBX variables */ 203 struct i40e_dcbx_variables { 204 u32 defmaxtrafficclasses; 205 u32 defprioritytcmapping; 206 u32 deftcbandwidth; 207 u32 deftsaassignment; 208 }; 209 210 enum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw, 211 u16 *status); 212 enum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib, 213 struct i40e_dcbx_config *dcbcfg); 214 enum i40e_status_code i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type, 215 u8 bridgetype, 216 struct i40e_dcbx_config *dcbcfg); 217 enum i40e_status_code i40e_get_dcb_config(struct i40e_hw *hw); 218 enum i40e_status_code i40e_init_dcb(struct i40e_hw *hw); 219 enum i40e_status_code i40e_set_dcb_config(struct i40e_hw *hw); 220 enum i40e_status_code i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen, 221 struct i40e_dcbx_config *dcbcfg); 222 223 #endif /* _I40E_DCB_H_ */ 224