1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2018 3 */ 4 5 #include "i40e_type.h" 6 #include "i40e_adminq.h" 7 #include "i40e_prototype.h" 8 #include "virtchnl.h" 9 10 /** 11 * i40e_set_mac_type - Sets MAC type 12 * @hw: pointer to the HW structure 13 * 14 * This function sets the mac type of the adapter based on the 15 * vendor ID and device ID stored in the hw structure. 16 **/ 17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 19 #else 20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 21 #endif 22 { 23 enum i40e_status_code status = I40E_SUCCESS; 24 25 DEBUGFUNC("i40e_set_mac_type\n"); 26 27 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 28 switch (hw->device_id) { 29 case I40E_DEV_ID_SFP_XL710: 30 case I40E_DEV_ID_QEMU: 31 case I40E_DEV_ID_KX_B: 32 case I40E_DEV_ID_KX_C: 33 case I40E_DEV_ID_QSFP_A: 34 case I40E_DEV_ID_QSFP_B: 35 case I40E_DEV_ID_QSFP_C: 36 case I40E_DEV_ID_10G_BASE_T: 37 case I40E_DEV_ID_10G_BASE_T4: 38 #ifdef CARLSVILLE_HW 39 case I40E_DEV_ID_10G_BASE_T_BC: 40 #endif 41 case I40E_DEV_ID_20G_KR2: 42 case I40E_DEV_ID_20G_KR2_A: 43 case I40E_DEV_ID_25G_B: 44 case I40E_DEV_ID_25G_SFP28: 45 hw->mac.type = I40E_MAC_XL710; 46 break; 47 #ifdef X722_A0_SUPPORT 48 case I40E_DEV_ID_X722_A0: 49 #endif 50 case I40E_DEV_ID_KX_X722: 51 case I40E_DEV_ID_QSFP_X722: 52 case I40E_DEV_ID_SFP_X722: 53 case I40E_DEV_ID_1G_BASE_T_X722: 54 case I40E_DEV_ID_10G_BASE_T_X722: 55 case I40E_DEV_ID_SFP_I_X722: 56 hw->mac.type = I40E_MAC_X722; 57 break; 58 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 59 case I40E_DEV_ID_X722_VF: 60 #ifdef X722_A0_SUPPORT 61 case I40E_DEV_ID_X722_A0_VF: 62 #endif 63 hw->mac.type = I40E_MAC_X722_VF; 64 break; 65 #endif /* INTEGRATED_VF || VF_DRIVER */ 66 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 67 case I40E_DEV_ID_VF: 68 case I40E_DEV_ID_VF_HV: 69 case I40E_DEV_ID_ADAPTIVE_VF: 70 hw->mac.type = I40E_MAC_VF; 71 break; 72 #endif 73 default: 74 hw->mac.type = I40E_MAC_GENERIC; 75 break; 76 } 77 } else { 78 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 79 } 80 81 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 82 hw->mac.type, status); 83 return status; 84 } 85 86 /** 87 * i40e_aq_str - convert AQ err code to a string 88 * @hw: pointer to the HW structure 89 * @aq_err: the AQ error code to convert 90 **/ 91 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 92 { 93 switch (aq_err) { 94 case I40E_AQ_RC_OK: 95 return "OK"; 96 case I40E_AQ_RC_EPERM: 97 return "I40E_AQ_RC_EPERM"; 98 case I40E_AQ_RC_ENOENT: 99 return "I40E_AQ_RC_ENOENT"; 100 case I40E_AQ_RC_ESRCH: 101 return "I40E_AQ_RC_ESRCH"; 102 case I40E_AQ_RC_EINTR: 103 return "I40E_AQ_RC_EINTR"; 104 case I40E_AQ_RC_EIO: 105 return "I40E_AQ_RC_EIO"; 106 case I40E_AQ_RC_ENXIO: 107 return "I40E_AQ_RC_ENXIO"; 108 case I40E_AQ_RC_E2BIG: 109 return "I40E_AQ_RC_E2BIG"; 110 case I40E_AQ_RC_EAGAIN: 111 return "I40E_AQ_RC_EAGAIN"; 112 case I40E_AQ_RC_ENOMEM: 113 return "I40E_AQ_RC_ENOMEM"; 114 case I40E_AQ_RC_EACCES: 115 return "I40E_AQ_RC_EACCES"; 116 case I40E_AQ_RC_EFAULT: 117 return "I40E_AQ_RC_EFAULT"; 118 case I40E_AQ_RC_EBUSY: 119 return "I40E_AQ_RC_EBUSY"; 120 case I40E_AQ_RC_EEXIST: 121 return "I40E_AQ_RC_EEXIST"; 122 case I40E_AQ_RC_EINVAL: 123 return "I40E_AQ_RC_EINVAL"; 124 case I40E_AQ_RC_ENOTTY: 125 return "I40E_AQ_RC_ENOTTY"; 126 case I40E_AQ_RC_ENOSPC: 127 return "I40E_AQ_RC_ENOSPC"; 128 case I40E_AQ_RC_ENOSYS: 129 return "I40E_AQ_RC_ENOSYS"; 130 case I40E_AQ_RC_ERANGE: 131 return "I40E_AQ_RC_ERANGE"; 132 case I40E_AQ_RC_EFLUSHED: 133 return "I40E_AQ_RC_EFLUSHED"; 134 case I40E_AQ_RC_BAD_ADDR: 135 return "I40E_AQ_RC_BAD_ADDR"; 136 case I40E_AQ_RC_EMODE: 137 return "I40E_AQ_RC_EMODE"; 138 case I40E_AQ_RC_EFBIG: 139 return "I40E_AQ_RC_EFBIG"; 140 } 141 142 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 143 return hw->err_str; 144 } 145 146 /** 147 * i40e_stat_str - convert status err code to a string 148 * @hw: pointer to the HW structure 149 * @stat_err: the status error code to convert 150 **/ 151 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 152 { 153 switch (stat_err) { 154 case I40E_SUCCESS: 155 return "OK"; 156 case I40E_ERR_NVM: 157 return "I40E_ERR_NVM"; 158 case I40E_ERR_NVM_CHECKSUM: 159 return "I40E_ERR_NVM_CHECKSUM"; 160 case I40E_ERR_PHY: 161 return "I40E_ERR_PHY"; 162 case I40E_ERR_CONFIG: 163 return "I40E_ERR_CONFIG"; 164 case I40E_ERR_PARAM: 165 return "I40E_ERR_PARAM"; 166 case I40E_ERR_MAC_TYPE: 167 return "I40E_ERR_MAC_TYPE"; 168 case I40E_ERR_UNKNOWN_PHY: 169 return "I40E_ERR_UNKNOWN_PHY"; 170 case I40E_ERR_LINK_SETUP: 171 return "I40E_ERR_LINK_SETUP"; 172 case I40E_ERR_ADAPTER_STOPPED: 173 return "I40E_ERR_ADAPTER_STOPPED"; 174 case I40E_ERR_INVALID_MAC_ADDR: 175 return "I40E_ERR_INVALID_MAC_ADDR"; 176 case I40E_ERR_DEVICE_NOT_SUPPORTED: 177 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 178 case I40E_ERR_MASTER_REQUESTS_PENDING: 179 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 180 case I40E_ERR_INVALID_LINK_SETTINGS: 181 return "I40E_ERR_INVALID_LINK_SETTINGS"; 182 case I40E_ERR_AUTONEG_NOT_COMPLETE: 183 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 184 case I40E_ERR_RESET_FAILED: 185 return "I40E_ERR_RESET_FAILED"; 186 case I40E_ERR_SWFW_SYNC: 187 return "I40E_ERR_SWFW_SYNC"; 188 case I40E_ERR_NO_AVAILABLE_VSI: 189 return "I40E_ERR_NO_AVAILABLE_VSI"; 190 case I40E_ERR_NO_MEMORY: 191 return "I40E_ERR_NO_MEMORY"; 192 case I40E_ERR_BAD_PTR: 193 return "I40E_ERR_BAD_PTR"; 194 case I40E_ERR_RING_FULL: 195 return "I40E_ERR_RING_FULL"; 196 case I40E_ERR_INVALID_PD_ID: 197 return "I40E_ERR_INVALID_PD_ID"; 198 case I40E_ERR_INVALID_QP_ID: 199 return "I40E_ERR_INVALID_QP_ID"; 200 case I40E_ERR_INVALID_CQ_ID: 201 return "I40E_ERR_INVALID_CQ_ID"; 202 case I40E_ERR_INVALID_CEQ_ID: 203 return "I40E_ERR_INVALID_CEQ_ID"; 204 case I40E_ERR_INVALID_AEQ_ID: 205 return "I40E_ERR_INVALID_AEQ_ID"; 206 case I40E_ERR_INVALID_SIZE: 207 return "I40E_ERR_INVALID_SIZE"; 208 case I40E_ERR_INVALID_ARP_INDEX: 209 return "I40E_ERR_INVALID_ARP_INDEX"; 210 case I40E_ERR_INVALID_FPM_FUNC_ID: 211 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 212 case I40E_ERR_QP_INVALID_MSG_SIZE: 213 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 214 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 215 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 216 case I40E_ERR_INVALID_FRAG_COUNT: 217 return "I40E_ERR_INVALID_FRAG_COUNT"; 218 case I40E_ERR_QUEUE_EMPTY: 219 return "I40E_ERR_QUEUE_EMPTY"; 220 case I40E_ERR_INVALID_ALIGNMENT: 221 return "I40E_ERR_INVALID_ALIGNMENT"; 222 case I40E_ERR_FLUSHED_QUEUE: 223 return "I40E_ERR_FLUSHED_QUEUE"; 224 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 225 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 226 case I40E_ERR_INVALID_IMM_DATA_SIZE: 227 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 228 case I40E_ERR_TIMEOUT: 229 return "I40E_ERR_TIMEOUT"; 230 case I40E_ERR_OPCODE_MISMATCH: 231 return "I40E_ERR_OPCODE_MISMATCH"; 232 case I40E_ERR_CQP_COMPL_ERROR: 233 return "I40E_ERR_CQP_COMPL_ERROR"; 234 case I40E_ERR_INVALID_VF_ID: 235 return "I40E_ERR_INVALID_VF_ID"; 236 case I40E_ERR_INVALID_HMCFN_ID: 237 return "I40E_ERR_INVALID_HMCFN_ID"; 238 case I40E_ERR_BACKING_PAGE_ERROR: 239 return "I40E_ERR_BACKING_PAGE_ERROR"; 240 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 241 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 242 case I40E_ERR_INVALID_PBLE_INDEX: 243 return "I40E_ERR_INVALID_PBLE_INDEX"; 244 case I40E_ERR_INVALID_SD_INDEX: 245 return "I40E_ERR_INVALID_SD_INDEX"; 246 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 247 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 248 case I40E_ERR_INVALID_SD_TYPE: 249 return "I40E_ERR_INVALID_SD_TYPE"; 250 case I40E_ERR_MEMCPY_FAILED: 251 return "I40E_ERR_MEMCPY_FAILED"; 252 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 253 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 254 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 255 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 256 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 257 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 258 case I40E_ERR_SRQ_ENABLED: 259 return "I40E_ERR_SRQ_ENABLED"; 260 case I40E_ERR_ADMIN_QUEUE_ERROR: 261 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 262 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 263 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 264 case I40E_ERR_BUF_TOO_SHORT: 265 return "I40E_ERR_BUF_TOO_SHORT"; 266 case I40E_ERR_ADMIN_QUEUE_FULL: 267 return "I40E_ERR_ADMIN_QUEUE_FULL"; 268 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 269 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 270 case I40E_ERR_BAD_IWARP_CQE: 271 return "I40E_ERR_BAD_IWARP_CQE"; 272 case I40E_ERR_NVM_BLANK_MODE: 273 return "I40E_ERR_NVM_BLANK_MODE"; 274 case I40E_ERR_NOT_IMPLEMENTED: 275 return "I40E_ERR_NOT_IMPLEMENTED"; 276 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 277 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 278 case I40E_ERR_DIAG_TEST_FAILED: 279 return "I40E_ERR_DIAG_TEST_FAILED"; 280 case I40E_ERR_NOT_READY: 281 return "I40E_ERR_NOT_READY"; 282 case I40E_NOT_SUPPORTED: 283 return "I40E_NOT_SUPPORTED"; 284 case I40E_ERR_FIRMWARE_API_VERSION: 285 return "I40E_ERR_FIRMWARE_API_VERSION"; 286 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 287 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 288 } 289 290 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 291 return hw->err_str; 292 } 293 294 /** 295 * i40e_debug_aq 296 * @hw: debug mask related to admin queue 297 * @mask: debug mask 298 * @desc: pointer to admin queue descriptor 299 * @buffer: pointer to command buffer 300 * @buf_len: max length of buffer 301 * 302 * Dumps debug log about adminq command with descriptor contents. 303 **/ 304 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 305 void *buffer, u16 buf_len) 306 { 307 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 308 u8 *buf = (u8 *)buffer; 309 u16 len; 310 u16 i = 0; 311 312 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 313 return; 314 315 len = LE16_TO_CPU(aq_desc->datalen); 316 317 i40e_debug(hw, mask, 318 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 319 LE16_TO_CPU(aq_desc->opcode), 320 LE16_TO_CPU(aq_desc->flags), 321 LE16_TO_CPU(aq_desc->datalen), 322 LE16_TO_CPU(aq_desc->retval)); 323 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 324 LE32_TO_CPU(aq_desc->cookie_high), 325 LE32_TO_CPU(aq_desc->cookie_low)); 326 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 327 LE32_TO_CPU(aq_desc->params.internal.param0), 328 LE32_TO_CPU(aq_desc->params.internal.param1)); 329 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 330 LE32_TO_CPU(aq_desc->params.external.addr_high), 331 LE32_TO_CPU(aq_desc->params.external.addr_low)); 332 333 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 334 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 335 if (buf_len < len) 336 len = buf_len; 337 /* write the full 16-byte chunks */ 338 for (i = 0; i < (len - 16); i += 16) 339 i40e_debug(hw, mask, 340 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 341 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 342 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 343 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 344 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 345 /* the most we could have left is 16 bytes, pad with zeros */ 346 if (i < len) { 347 char d_buf[16]; 348 int j, i_sav; 349 350 i_sav = i; 351 memset(d_buf, 0, sizeof(d_buf)); 352 for (j = 0; i < len; j++, i++) 353 d_buf[j] = buf[i]; 354 i40e_debug(hw, mask, 355 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 356 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 357 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 358 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 359 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 360 } 361 } 362 } 363 364 /** 365 * i40e_check_asq_alive 366 * @hw: pointer to the hw struct 367 * 368 * Returns true if Queue is enabled else false. 369 **/ 370 bool i40e_check_asq_alive(struct i40e_hw *hw) 371 { 372 if (hw->aq.asq.len) 373 #ifdef PF_DRIVER 374 #ifdef INTEGRATED_VF 375 if (!i40e_is_vf(hw)) 376 return !!(rd32(hw, hw->aq.asq.len) & 377 I40E_PF_ATQLEN_ATQENABLE_MASK); 378 #else 379 return !!(rd32(hw, hw->aq.asq.len) & 380 I40E_PF_ATQLEN_ATQENABLE_MASK); 381 #endif /* INTEGRATED_VF */ 382 #endif /* PF_DRIVER */ 383 #ifdef VF_DRIVER 384 #ifdef INTEGRATED_VF 385 if (i40e_is_vf(hw)) 386 return !!(rd32(hw, hw->aq.asq.len) & 387 I40E_VF_ATQLEN1_ATQENABLE_MASK); 388 #else 389 return !!(rd32(hw, hw->aq.asq.len) & 390 I40E_VF_ATQLEN1_ATQENABLE_MASK); 391 #endif /* INTEGRATED_VF */ 392 #endif /* VF_DRIVER */ 393 return false; 394 } 395 396 /** 397 * i40e_aq_queue_shutdown 398 * @hw: pointer to the hw struct 399 * @unloading: is the driver unloading itself 400 * 401 * Tell the Firmware that we're shutting down the AdminQ and whether 402 * or not the driver is unloading as well. 403 **/ 404 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 405 bool unloading) 406 { 407 struct i40e_aq_desc desc; 408 struct i40e_aqc_queue_shutdown *cmd = 409 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 410 enum i40e_status_code status; 411 412 i40e_fill_default_direct_cmd_desc(&desc, 413 i40e_aqc_opc_queue_shutdown); 414 415 if (unloading) 416 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 417 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 418 419 return status; 420 } 421 422 /** 423 * i40e_aq_get_set_rss_lut 424 * @hw: pointer to the hardware structure 425 * @vsi_id: vsi fw index 426 * @pf_lut: for PF table set true, for VSI table set false 427 * @lut: pointer to the lut buffer provided by the caller 428 * @lut_size: size of the lut buffer 429 * @set: set true to set the table, false to get the table 430 * 431 * Internal function to get or set RSS look up table 432 **/ 433 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 434 u16 vsi_id, bool pf_lut, 435 u8 *lut, u16 lut_size, 436 bool set) 437 { 438 enum i40e_status_code status; 439 struct i40e_aq_desc desc; 440 struct i40e_aqc_get_set_rss_lut *cmd_resp = 441 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 442 443 if (set) 444 i40e_fill_default_direct_cmd_desc(&desc, 445 i40e_aqc_opc_set_rss_lut); 446 else 447 i40e_fill_default_direct_cmd_desc(&desc, 448 i40e_aqc_opc_get_rss_lut); 449 450 /* Indirect command */ 451 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 452 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 453 454 cmd_resp->vsi_id = 455 CPU_TO_LE16((u16)((vsi_id << 456 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 457 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 458 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 459 460 if (pf_lut) 461 cmd_resp->flags |= CPU_TO_LE16((u16) 462 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 463 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 464 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 465 else 466 cmd_resp->flags |= CPU_TO_LE16((u16) 467 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 468 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 469 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 470 471 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 472 473 return status; 474 } 475 476 /** 477 * i40e_aq_get_rss_lut 478 * @hw: pointer to the hardware structure 479 * @vsi_id: vsi fw index 480 * @pf_lut: for PF table set true, for VSI table set false 481 * @lut: pointer to the lut buffer provided by the caller 482 * @lut_size: size of the lut buffer 483 * 484 * get the RSS lookup table, PF or VSI type 485 **/ 486 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 487 bool pf_lut, u8 *lut, u16 lut_size) 488 { 489 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 490 false); 491 } 492 493 /** 494 * i40e_aq_set_rss_lut 495 * @hw: pointer to the hardware structure 496 * @vsi_id: vsi fw index 497 * @pf_lut: for PF table set true, for VSI table set false 498 * @lut: pointer to the lut buffer provided by the caller 499 * @lut_size: size of the lut buffer 500 * 501 * set the RSS lookup table, PF or VSI type 502 **/ 503 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 504 bool pf_lut, u8 *lut, u16 lut_size) 505 { 506 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 507 } 508 509 /** 510 * i40e_aq_get_set_rss_key 511 * @hw: pointer to the hw struct 512 * @vsi_id: vsi fw index 513 * @key: pointer to key info struct 514 * @set: set true to set the key, false to get the key 515 * 516 * get the RSS key per VSI 517 **/ 518 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 519 u16 vsi_id, 520 struct i40e_aqc_get_set_rss_key_data *key, 521 bool set) 522 { 523 enum i40e_status_code status; 524 struct i40e_aq_desc desc; 525 struct i40e_aqc_get_set_rss_key *cmd_resp = 526 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 527 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 528 529 if (set) 530 i40e_fill_default_direct_cmd_desc(&desc, 531 i40e_aqc_opc_set_rss_key); 532 else 533 i40e_fill_default_direct_cmd_desc(&desc, 534 i40e_aqc_opc_get_rss_key); 535 536 /* Indirect command */ 537 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 538 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 539 540 cmd_resp->vsi_id = 541 CPU_TO_LE16((u16)((vsi_id << 542 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 543 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 544 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 545 546 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 547 548 return status; 549 } 550 551 /** 552 * i40e_aq_get_rss_key 553 * @hw: pointer to the hw struct 554 * @vsi_id: vsi fw index 555 * @key: pointer to key info struct 556 * 557 **/ 558 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 559 u16 vsi_id, 560 struct i40e_aqc_get_set_rss_key_data *key) 561 { 562 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 563 } 564 565 /** 566 * i40e_aq_set_rss_key 567 * @hw: pointer to the hw struct 568 * @vsi_id: vsi fw index 569 * @key: pointer to key info struct 570 * 571 * set the RSS key per VSI 572 **/ 573 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 574 u16 vsi_id, 575 struct i40e_aqc_get_set_rss_key_data *key) 576 { 577 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 578 } 579 580 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 581 * hardware to a bit-field that can be used by SW to more easily determine the 582 * packet type. 583 * 584 * Macros are used to shorten the table lines and make this table human 585 * readable. 586 * 587 * We store the PTYPE in the top byte of the bit field - this is just so that 588 * we can check that the table doesn't have a row missing, as the index into 589 * the table should be the PTYPE. 590 * 591 * Typical work flow: 592 * 593 * IF NOT i40e_ptype_lookup[ptype].known 594 * THEN 595 * Packet is unknown 596 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 597 * Use the rest of the fields to look at the tunnels, inner protocols, etc 598 * ELSE 599 * Use the enum i40e_rx_l2_ptype to decode the packet type 600 * ENDIF 601 */ 602 603 /* macro to make the table lines short */ 604 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 605 { PTYPE, \ 606 1, \ 607 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 608 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 609 I40E_RX_PTYPE_##OUTER_FRAG, \ 610 I40E_RX_PTYPE_TUNNEL_##T, \ 611 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 612 I40E_RX_PTYPE_##TEF, \ 613 I40E_RX_PTYPE_INNER_PROT_##I, \ 614 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 615 616 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 617 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 618 619 /* shorter macros makes the table fit but are terse */ 620 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 621 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 622 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 623 624 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 625 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 626 /* L2 Packet types */ 627 I40E_PTT_UNUSED_ENTRY(0), 628 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 629 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 630 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 631 I40E_PTT_UNUSED_ENTRY(4), 632 I40E_PTT_UNUSED_ENTRY(5), 633 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 634 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 635 I40E_PTT_UNUSED_ENTRY(8), 636 I40E_PTT_UNUSED_ENTRY(9), 637 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 638 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 639 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 640 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 641 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 642 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 643 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 644 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 645 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 646 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 647 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 648 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 649 650 /* Non Tunneled IPv4 */ 651 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 652 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 653 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 654 I40E_PTT_UNUSED_ENTRY(25), 655 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 656 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 657 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 658 659 /* IPv4 --> IPv4 */ 660 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 661 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 662 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 663 I40E_PTT_UNUSED_ENTRY(32), 664 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 665 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 666 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 667 668 /* IPv4 --> IPv6 */ 669 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 670 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 671 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 672 I40E_PTT_UNUSED_ENTRY(39), 673 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 674 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 675 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 676 677 /* IPv4 --> GRE/NAT */ 678 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 679 680 /* IPv4 --> GRE/NAT --> IPv4 */ 681 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 682 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 683 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 684 I40E_PTT_UNUSED_ENTRY(47), 685 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 686 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 687 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 688 689 /* IPv4 --> GRE/NAT --> IPv6 */ 690 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 691 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 692 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 693 I40E_PTT_UNUSED_ENTRY(54), 694 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 695 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 696 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 697 698 /* IPv4 --> GRE/NAT --> MAC */ 699 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 700 701 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 702 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 703 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 704 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 705 I40E_PTT_UNUSED_ENTRY(62), 706 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 707 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 708 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 709 710 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 711 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 712 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 713 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 714 I40E_PTT_UNUSED_ENTRY(69), 715 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 716 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 717 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 718 719 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 720 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 721 722 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 723 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 724 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 725 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 726 I40E_PTT_UNUSED_ENTRY(77), 727 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 728 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 729 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 730 731 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 732 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 733 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 734 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 735 I40E_PTT_UNUSED_ENTRY(84), 736 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 737 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 738 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 739 740 /* Non Tunneled IPv6 */ 741 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 742 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 743 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 744 I40E_PTT_UNUSED_ENTRY(91), 745 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 746 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 747 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 748 749 /* IPv6 --> IPv4 */ 750 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 751 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 752 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 753 I40E_PTT_UNUSED_ENTRY(98), 754 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 755 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 756 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 757 758 /* IPv6 --> IPv6 */ 759 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 760 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 761 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 762 I40E_PTT_UNUSED_ENTRY(105), 763 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 764 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 765 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 766 767 /* IPv6 --> GRE/NAT */ 768 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 769 770 /* IPv6 --> GRE/NAT -> IPv4 */ 771 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 772 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 773 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 774 I40E_PTT_UNUSED_ENTRY(113), 775 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 776 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 777 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 778 779 /* IPv6 --> GRE/NAT -> IPv6 */ 780 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 781 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 782 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 783 I40E_PTT_UNUSED_ENTRY(120), 784 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 785 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 786 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 787 788 /* IPv6 --> GRE/NAT -> MAC */ 789 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 790 791 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 792 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 793 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 794 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 795 I40E_PTT_UNUSED_ENTRY(128), 796 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 797 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 798 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 799 800 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 801 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 802 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 803 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 804 I40E_PTT_UNUSED_ENTRY(135), 805 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 806 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 807 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 808 809 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 810 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 811 812 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 813 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 814 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 815 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 816 I40E_PTT_UNUSED_ENTRY(143), 817 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 818 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 819 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 820 821 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 822 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 823 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 824 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 825 I40E_PTT_UNUSED_ENTRY(150), 826 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 827 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 828 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 829 830 /* unused entries */ 831 I40E_PTT_UNUSED_ENTRY(154), 832 I40E_PTT_UNUSED_ENTRY(155), 833 I40E_PTT_UNUSED_ENTRY(156), 834 I40E_PTT_UNUSED_ENTRY(157), 835 I40E_PTT_UNUSED_ENTRY(158), 836 I40E_PTT_UNUSED_ENTRY(159), 837 838 I40E_PTT_UNUSED_ENTRY(160), 839 I40E_PTT_UNUSED_ENTRY(161), 840 I40E_PTT_UNUSED_ENTRY(162), 841 I40E_PTT_UNUSED_ENTRY(163), 842 I40E_PTT_UNUSED_ENTRY(164), 843 I40E_PTT_UNUSED_ENTRY(165), 844 I40E_PTT_UNUSED_ENTRY(166), 845 I40E_PTT_UNUSED_ENTRY(167), 846 I40E_PTT_UNUSED_ENTRY(168), 847 I40E_PTT_UNUSED_ENTRY(169), 848 849 I40E_PTT_UNUSED_ENTRY(170), 850 I40E_PTT_UNUSED_ENTRY(171), 851 I40E_PTT_UNUSED_ENTRY(172), 852 I40E_PTT_UNUSED_ENTRY(173), 853 I40E_PTT_UNUSED_ENTRY(174), 854 I40E_PTT_UNUSED_ENTRY(175), 855 I40E_PTT_UNUSED_ENTRY(176), 856 I40E_PTT_UNUSED_ENTRY(177), 857 I40E_PTT_UNUSED_ENTRY(178), 858 I40E_PTT_UNUSED_ENTRY(179), 859 860 I40E_PTT_UNUSED_ENTRY(180), 861 I40E_PTT_UNUSED_ENTRY(181), 862 I40E_PTT_UNUSED_ENTRY(182), 863 I40E_PTT_UNUSED_ENTRY(183), 864 I40E_PTT_UNUSED_ENTRY(184), 865 I40E_PTT_UNUSED_ENTRY(185), 866 I40E_PTT_UNUSED_ENTRY(186), 867 I40E_PTT_UNUSED_ENTRY(187), 868 I40E_PTT_UNUSED_ENTRY(188), 869 I40E_PTT_UNUSED_ENTRY(189), 870 871 I40E_PTT_UNUSED_ENTRY(190), 872 I40E_PTT_UNUSED_ENTRY(191), 873 I40E_PTT_UNUSED_ENTRY(192), 874 I40E_PTT_UNUSED_ENTRY(193), 875 I40E_PTT_UNUSED_ENTRY(194), 876 I40E_PTT_UNUSED_ENTRY(195), 877 I40E_PTT_UNUSED_ENTRY(196), 878 I40E_PTT_UNUSED_ENTRY(197), 879 I40E_PTT_UNUSED_ENTRY(198), 880 I40E_PTT_UNUSED_ENTRY(199), 881 882 I40E_PTT_UNUSED_ENTRY(200), 883 I40E_PTT_UNUSED_ENTRY(201), 884 I40E_PTT_UNUSED_ENTRY(202), 885 I40E_PTT_UNUSED_ENTRY(203), 886 I40E_PTT_UNUSED_ENTRY(204), 887 I40E_PTT_UNUSED_ENTRY(205), 888 I40E_PTT_UNUSED_ENTRY(206), 889 I40E_PTT_UNUSED_ENTRY(207), 890 I40E_PTT_UNUSED_ENTRY(208), 891 I40E_PTT_UNUSED_ENTRY(209), 892 893 I40E_PTT_UNUSED_ENTRY(210), 894 I40E_PTT_UNUSED_ENTRY(211), 895 I40E_PTT_UNUSED_ENTRY(212), 896 I40E_PTT_UNUSED_ENTRY(213), 897 I40E_PTT_UNUSED_ENTRY(214), 898 I40E_PTT_UNUSED_ENTRY(215), 899 I40E_PTT_UNUSED_ENTRY(216), 900 I40E_PTT_UNUSED_ENTRY(217), 901 I40E_PTT_UNUSED_ENTRY(218), 902 I40E_PTT_UNUSED_ENTRY(219), 903 904 I40E_PTT_UNUSED_ENTRY(220), 905 I40E_PTT_UNUSED_ENTRY(221), 906 I40E_PTT_UNUSED_ENTRY(222), 907 I40E_PTT_UNUSED_ENTRY(223), 908 I40E_PTT_UNUSED_ENTRY(224), 909 I40E_PTT_UNUSED_ENTRY(225), 910 I40E_PTT_UNUSED_ENTRY(226), 911 I40E_PTT_UNUSED_ENTRY(227), 912 I40E_PTT_UNUSED_ENTRY(228), 913 I40E_PTT_UNUSED_ENTRY(229), 914 915 I40E_PTT_UNUSED_ENTRY(230), 916 I40E_PTT_UNUSED_ENTRY(231), 917 I40E_PTT_UNUSED_ENTRY(232), 918 I40E_PTT_UNUSED_ENTRY(233), 919 I40E_PTT_UNUSED_ENTRY(234), 920 I40E_PTT_UNUSED_ENTRY(235), 921 I40E_PTT_UNUSED_ENTRY(236), 922 I40E_PTT_UNUSED_ENTRY(237), 923 I40E_PTT_UNUSED_ENTRY(238), 924 I40E_PTT_UNUSED_ENTRY(239), 925 926 I40E_PTT_UNUSED_ENTRY(240), 927 I40E_PTT_UNUSED_ENTRY(241), 928 I40E_PTT_UNUSED_ENTRY(242), 929 I40E_PTT_UNUSED_ENTRY(243), 930 I40E_PTT_UNUSED_ENTRY(244), 931 I40E_PTT_UNUSED_ENTRY(245), 932 I40E_PTT_UNUSED_ENTRY(246), 933 I40E_PTT_UNUSED_ENTRY(247), 934 I40E_PTT_UNUSED_ENTRY(248), 935 I40E_PTT_UNUSED_ENTRY(249), 936 937 I40E_PTT_UNUSED_ENTRY(250), 938 I40E_PTT_UNUSED_ENTRY(251), 939 I40E_PTT_UNUSED_ENTRY(252), 940 I40E_PTT_UNUSED_ENTRY(253), 941 I40E_PTT_UNUSED_ENTRY(254), 942 I40E_PTT_UNUSED_ENTRY(255) 943 }; 944 945 946 /** 947 * i40e_validate_mac_addr - Validate unicast MAC address 948 * @mac_addr: pointer to MAC address 949 * 950 * Tests a MAC address to ensure it is a valid Individual Address 951 **/ 952 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 953 { 954 enum i40e_status_code status = I40E_SUCCESS; 955 956 DEBUGFUNC("i40e_validate_mac_addr"); 957 958 /* Broadcast addresses ARE multicast addresses 959 * Make sure it is not a multicast address 960 * Reject the zero address 961 */ 962 if (I40E_IS_MULTICAST(mac_addr) || 963 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 964 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 965 status = I40E_ERR_INVALID_MAC_ADDR; 966 967 return status; 968 } 969 #ifdef PF_DRIVER 970 971 /** 972 * i40e_init_shared_code - Initialize the shared code 973 * @hw: pointer to hardware structure 974 * 975 * This assigns the MAC type and PHY code and inits the NVM. 976 * Does not touch the hardware. This function must be called prior to any 977 * other function in the shared code. The i40e_hw structure should be 978 * memset to 0 prior to calling this function. The following fields in 979 * hw structure should be filled in prior to calling this function: 980 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 981 * subsystem_vendor_id, and revision_id 982 **/ 983 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 984 { 985 enum i40e_status_code status = I40E_SUCCESS; 986 u32 port, ari, func_rid; 987 988 DEBUGFUNC("i40e_init_shared_code"); 989 990 i40e_set_mac_type(hw); 991 992 switch (hw->mac.type) { 993 case I40E_MAC_XL710: 994 case I40E_MAC_X722: 995 break; 996 default: 997 return I40E_ERR_DEVICE_NOT_SUPPORTED; 998 } 999 1000 hw->phy.get_link_info = true; 1001 1002 /* Determine port number and PF number*/ 1003 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 1004 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1005 hw->port = (u8)port; 1006 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 1007 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1008 func_rid = rd32(hw, I40E_PF_FUNC_RID); 1009 if (ari) 1010 hw->pf_id = (u8)(func_rid & 0xff); 1011 else 1012 hw->pf_id = (u8)(func_rid & 0x7); 1013 1014 if (hw->mac.type == I40E_MAC_X722) 1015 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 1016 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 1017 1018 status = i40e_init_nvm(hw); 1019 return status; 1020 } 1021 1022 /** 1023 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1024 * @hw: pointer to the hw struct 1025 * @flags: a return indicator of what addresses were added to the addr store 1026 * @addrs: the requestor's mac addr store 1027 * @cmd_details: pointer to command details structure or NULL 1028 **/ 1029 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1030 u16 *flags, 1031 struct i40e_aqc_mac_address_read_data *addrs, 1032 struct i40e_asq_cmd_details *cmd_details) 1033 { 1034 struct i40e_aq_desc desc; 1035 struct i40e_aqc_mac_address_read *cmd_data = 1036 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1037 enum i40e_status_code status; 1038 1039 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1040 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1041 1042 status = i40e_asq_send_command(hw, &desc, addrs, 1043 sizeof(*addrs), cmd_details); 1044 *flags = LE16_TO_CPU(cmd_data->command_flags); 1045 1046 return status; 1047 } 1048 1049 /** 1050 * i40e_aq_mac_address_write - Change the MAC addresses 1051 * @hw: pointer to the hw struct 1052 * @flags: indicates which MAC to be written 1053 * @mac_addr: address to write 1054 * @cmd_details: pointer to command details structure or NULL 1055 **/ 1056 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1057 u16 flags, u8 *mac_addr, 1058 struct i40e_asq_cmd_details *cmd_details) 1059 { 1060 struct i40e_aq_desc desc; 1061 struct i40e_aqc_mac_address_write *cmd_data = 1062 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1063 enum i40e_status_code status; 1064 1065 i40e_fill_default_direct_cmd_desc(&desc, 1066 i40e_aqc_opc_mac_address_write); 1067 cmd_data->command_flags = CPU_TO_LE16(flags); 1068 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1069 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1070 ((u32)mac_addr[3] << 16) | 1071 ((u32)mac_addr[4] << 8) | 1072 mac_addr[5]); 1073 1074 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1075 1076 return status; 1077 } 1078 1079 /** 1080 * i40e_get_mac_addr - get MAC address 1081 * @hw: pointer to the HW structure 1082 * @mac_addr: pointer to MAC address 1083 * 1084 * Reads the adapter's MAC address from register 1085 **/ 1086 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1087 { 1088 struct i40e_aqc_mac_address_read_data addrs; 1089 enum i40e_status_code status; 1090 u16 flags = 0; 1091 1092 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1093 1094 if (flags & I40E_AQC_LAN_ADDR_VALID) 1095 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1096 I40E_NONDMA_TO_NONDMA); 1097 1098 return status; 1099 } 1100 1101 /** 1102 * i40e_get_port_mac_addr - get Port MAC address 1103 * @hw: pointer to the HW structure 1104 * @mac_addr: pointer to Port MAC address 1105 * 1106 * Reads the adapter's Port MAC address 1107 **/ 1108 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1109 { 1110 struct i40e_aqc_mac_address_read_data addrs; 1111 enum i40e_status_code status; 1112 u16 flags = 0; 1113 1114 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1115 if (status) 1116 return status; 1117 1118 if (flags & I40E_AQC_PORT_ADDR_VALID) 1119 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1120 I40E_NONDMA_TO_NONDMA); 1121 else 1122 status = I40E_ERR_INVALID_MAC_ADDR; 1123 1124 return status; 1125 } 1126 1127 /** 1128 * i40e_pre_tx_queue_cfg - pre tx queue configure 1129 * @hw: pointer to the HW structure 1130 * @queue: target pf queue index 1131 * @enable: state change request 1132 * 1133 * Handles hw requirement to indicate intention to enable 1134 * or disable target queue. 1135 **/ 1136 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1137 { 1138 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1139 u32 reg_block = 0; 1140 u32 reg_val; 1141 1142 if (abs_queue_idx >= 128) { 1143 reg_block = abs_queue_idx / 128; 1144 abs_queue_idx %= 128; 1145 } 1146 1147 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1148 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1149 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1150 1151 if (enable) 1152 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1153 else 1154 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1155 1156 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1157 } 1158 1159 /** 1160 * i40e_get_san_mac_addr - get SAN MAC address 1161 * @hw: pointer to the HW structure 1162 * @mac_addr: pointer to SAN MAC address 1163 * 1164 * Reads the adapter's SAN MAC address from NVM 1165 **/ 1166 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw, 1167 u8 *mac_addr) 1168 { 1169 struct i40e_aqc_mac_address_read_data addrs; 1170 enum i40e_status_code status; 1171 u16 flags = 0; 1172 1173 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1174 if (status) 1175 return status; 1176 1177 if (flags & I40E_AQC_SAN_ADDR_VALID) 1178 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac), 1179 I40E_NONDMA_TO_NONDMA); 1180 else 1181 status = I40E_ERR_INVALID_MAC_ADDR; 1182 1183 return status; 1184 } 1185 1186 /** 1187 * i40e_read_pba_string - Reads part number string from EEPROM 1188 * @hw: pointer to hardware structure 1189 * @pba_num: stores the part number string from the EEPROM 1190 * @pba_num_size: part number string buffer length 1191 * 1192 * Reads the part number string from the EEPROM. 1193 **/ 1194 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1195 u32 pba_num_size) 1196 { 1197 enum i40e_status_code status = I40E_SUCCESS; 1198 u16 pba_word = 0; 1199 u16 pba_size = 0; 1200 u16 pba_ptr = 0; 1201 u16 i = 0; 1202 1203 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1204 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1205 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1206 return status; 1207 } 1208 1209 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1210 if (status != I40E_SUCCESS) { 1211 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1212 return status; 1213 } 1214 1215 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1216 if (status != I40E_SUCCESS) { 1217 DEBUGOUT("Failed to read PBA Block size.\n"); 1218 return status; 1219 } 1220 1221 /* Subtract one to get PBA word count (PBA Size word is included in 1222 * total size) 1223 */ 1224 pba_size--; 1225 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1226 DEBUGOUT("Buffer to small for PBA data.\n"); 1227 return I40E_ERR_PARAM; 1228 } 1229 1230 for (i = 0; i < pba_size; i++) { 1231 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1232 if (status != I40E_SUCCESS) { 1233 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1234 return status; 1235 } 1236 1237 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1238 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1239 } 1240 pba_num[(pba_size * 2)] = '\0'; 1241 1242 return status; 1243 } 1244 1245 /** 1246 * i40e_get_media_type - Gets media type 1247 * @hw: pointer to the hardware structure 1248 **/ 1249 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1250 { 1251 enum i40e_media_type media; 1252 1253 switch (hw->phy.link_info.phy_type) { 1254 case I40E_PHY_TYPE_10GBASE_SR: 1255 case I40E_PHY_TYPE_10GBASE_LR: 1256 case I40E_PHY_TYPE_1000BASE_SX: 1257 case I40E_PHY_TYPE_1000BASE_LX: 1258 case I40E_PHY_TYPE_40GBASE_SR4: 1259 case I40E_PHY_TYPE_40GBASE_LR4: 1260 case I40E_PHY_TYPE_25GBASE_LR: 1261 case I40E_PHY_TYPE_25GBASE_SR: 1262 media = I40E_MEDIA_TYPE_FIBER; 1263 break; 1264 case I40E_PHY_TYPE_100BASE_TX: 1265 case I40E_PHY_TYPE_1000BASE_T: 1266 #ifdef CARLSVILLE_HW 1267 case I40E_PHY_TYPE_2_5GBASE_T: 1268 case I40E_PHY_TYPE_5GBASE_T: 1269 #endif 1270 case I40E_PHY_TYPE_10GBASE_T: 1271 media = I40E_MEDIA_TYPE_BASET; 1272 break; 1273 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1274 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1275 case I40E_PHY_TYPE_10GBASE_CR1: 1276 case I40E_PHY_TYPE_40GBASE_CR4: 1277 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1278 case I40E_PHY_TYPE_40GBASE_AOC: 1279 case I40E_PHY_TYPE_10GBASE_AOC: 1280 case I40E_PHY_TYPE_25GBASE_CR: 1281 case I40E_PHY_TYPE_25GBASE_AOC: 1282 case I40E_PHY_TYPE_25GBASE_ACC: 1283 media = I40E_MEDIA_TYPE_DA; 1284 break; 1285 case I40E_PHY_TYPE_1000BASE_KX: 1286 case I40E_PHY_TYPE_10GBASE_KX4: 1287 case I40E_PHY_TYPE_10GBASE_KR: 1288 case I40E_PHY_TYPE_40GBASE_KR4: 1289 case I40E_PHY_TYPE_20GBASE_KR2: 1290 case I40E_PHY_TYPE_25GBASE_KR: 1291 media = I40E_MEDIA_TYPE_BACKPLANE; 1292 break; 1293 case I40E_PHY_TYPE_SGMII: 1294 case I40E_PHY_TYPE_XAUI: 1295 case I40E_PHY_TYPE_XFI: 1296 case I40E_PHY_TYPE_XLAUI: 1297 case I40E_PHY_TYPE_XLPPI: 1298 default: 1299 media = I40E_MEDIA_TYPE_UNKNOWN; 1300 break; 1301 } 1302 1303 return media; 1304 } 1305 1306 /** 1307 * i40e_poll_globr - Poll for Global Reset completion 1308 * @hw: pointer to the hardware structure 1309 * @retry_limit: how many times to retry before failure 1310 **/ 1311 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw, 1312 u32 retry_limit) 1313 { 1314 u32 cnt, reg = 0; 1315 1316 for (cnt = 0; cnt < retry_limit; cnt++) { 1317 reg = rd32(hw, I40E_GLGEN_RSTAT); 1318 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1319 return I40E_SUCCESS; 1320 i40e_msec_delay(100); 1321 } 1322 1323 DEBUGOUT("Global reset failed.\n"); 1324 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg); 1325 1326 return I40E_ERR_RESET_FAILED; 1327 } 1328 1329 #define I40E_PF_RESET_WAIT_COUNT 200 1330 /** 1331 * i40e_pf_reset - Reset the PF 1332 * @hw: pointer to the hardware structure 1333 * 1334 * Assuming someone else has triggered a global reset, 1335 * assure the global reset is complete and then reset the PF 1336 **/ 1337 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1338 { 1339 u32 cnt = 0; 1340 u32 cnt1 = 0; 1341 u32 reg = 0; 1342 u32 grst_del; 1343 1344 /* Poll for Global Reset steady state in case of recent GRST. 1345 * The grst delay value is in 100ms units, and we'll wait a 1346 * couple counts longer to be sure we don't just miss the end. 1347 */ 1348 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1349 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1350 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1351 1352 grst_del = min(grst_del * 20, 160U); 1353 1354 for (cnt = 0; cnt < grst_del; cnt++) { 1355 reg = rd32(hw, I40E_GLGEN_RSTAT); 1356 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1357 break; 1358 i40e_msec_delay(100); 1359 } 1360 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1361 DEBUGOUT("Global reset polling failed to complete.\n"); 1362 return I40E_ERR_RESET_FAILED; 1363 } 1364 1365 /* Now Wait for the FW to be ready */ 1366 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1367 reg = rd32(hw, I40E_GLNVM_ULD); 1368 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1369 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1370 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1371 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1372 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1373 break; 1374 } 1375 i40e_msec_delay(10); 1376 } 1377 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1378 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1379 DEBUGOUT("wait for FW Reset complete timedout\n"); 1380 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1381 return I40E_ERR_RESET_FAILED; 1382 } 1383 1384 /* If there was a Global Reset in progress when we got here, 1385 * we don't need to do the PF Reset 1386 */ 1387 if (!cnt) { 1388 u32 reg2 = 0; 1389 1390 reg = rd32(hw, I40E_PFGEN_CTRL); 1391 wr32(hw, I40E_PFGEN_CTRL, 1392 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1393 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1394 reg = rd32(hw, I40E_PFGEN_CTRL); 1395 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1396 break; 1397 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1398 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 1399 break; 1400 i40e_msec_delay(1); 1401 } 1402 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1403 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS) 1404 return I40E_ERR_RESET_FAILED; 1405 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1406 DEBUGOUT("PF reset polling failed to complete.\n"); 1407 return I40E_ERR_RESET_FAILED; 1408 } 1409 } 1410 1411 i40e_clear_pxe_mode(hw); 1412 1413 1414 return I40E_SUCCESS; 1415 } 1416 1417 /** 1418 * i40e_clear_hw - clear out any left over hw state 1419 * @hw: pointer to the hw struct 1420 * 1421 * Clear queues and interrupts, typically called at init time, 1422 * but after the capabilities have been found so we know how many 1423 * queues and msix vectors have been allocated. 1424 **/ 1425 void i40e_clear_hw(struct i40e_hw *hw) 1426 { 1427 u32 num_queues, base_queue; 1428 u32 num_pf_int; 1429 u32 num_vf_int; 1430 u32 num_vfs; 1431 u32 i, j; 1432 u32 val; 1433 u32 eol = 0x7ff; 1434 1435 /* get number of interrupts, queues, and vfs */ 1436 val = rd32(hw, I40E_GLPCI_CNF2); 1437 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1438 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1439 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1440 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1441 1442 val = rd32(hw, I40E_PFLAN_QALLOC); 1443 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1444 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1445 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1446 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1447 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1448 num_queues = (j - base_queue) + 1; 1449 else 1450 num_queues = 0; 1451 1452 val = rd32(hw, I40E_PF_VT_PFALLOC); 1453 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1454 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1455 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1456 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1457 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1458 num_vfs = (j - i) + 1; 1459 else 1460 num_vfs = 0; 1461 1462 /* stop all the interrupts */ 1463 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1464 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1465 for (i = 0; i < num_pf_int - 2; i++) 1466 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1467 1468 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1469 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1470 wr32(hw, I40E_PFINT_LNKLST0, val); 1471 for (i = 0; i < num_pf_int - 2; i++) 1472 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1473 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1474 for (i = 0; i < num_vfs; i++) 1475 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1476 for (i = 0; i < num_vf_int - 2; i++) 1477 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1478 1479 /* warn the HW of the coming Tx disables */ 1480 for (i = 0; i < num_queues; i++) { 1481 u32 abs_queue_idx = base_queue + i; 1482 u32 reg_block = 0; 1483 1484 if (abs_queue_idx >= 128) { 1485 reg_block = abs_queue_idx / 128; 1486 abs_queue_idx %= 128; 1487 } 1488 1489 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1490 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1491 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1492 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1493 1494 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1495 } 1496 i40e_usec_delay(400); 1497 1498 /* stop all the queues */ 1499 for (i = 0; i < num_queues; i++) { 1500 wr32(hw, I40E_QINT_TQCTL(i), 0); 1501 wr32(hw, I40E_QTX_ENA(i), 0); 1502 wr32(hw, I40E_QINT_RQCTL(i), 0); 1503 wr32(hw, I40E_QRX_ENA(i), 0); 1504 } 1505 1506 /* short wait for all queue disables to settle */ 1507 i40e_usec_delay(50); 1508 } 1509 1510 /** 1511 * i40e_clear_pxe_mode - clear pxe operations mode 1512 * @hw: pointer to the hw struct 1513 * 1514 * Make sure all PXE mode settings are cleared, including things 1515 * like descriptor fetch/write-back mode. 1516 **/ 1517 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1518 { 1519 if (i40e_check_asq_alive(hw)) 1520 i40e_aq_clear_pxe_mode(hw, NULL); 1521 } 1522 1523 /** 1524 * i40e_led_is_mine - helper to find matching led 1525 * @hw: pointer to the hw struct 1526 * @idx: index into GPIO registers 1527 * 1528 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1529 */ 1530 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1531 { 1532 u32 gpio_val = 0; 1533 u32 port; 1534 1535 if (!hw->func_caps.led[idx]) 1536 return 0; 1537 1538 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1539 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1540 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1541 1542 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1543 * if it is not our port then ignore 1544 */ 1545 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1546 (port != hw->port)) 1547 return 0; 1548 1549 return gpio_val; 1550 } 1551 1552 #define I40E_COMBINED_ACTIVITY 0xA 1553 #define I40E_FILTER_ACTIVITY 0xE 1554 #define I40E_LINK_ACTIVITY 0xC 1555 #define I40E_MAC_ACTIVITY 0xD 1556 #define I40E_LED0 22 1557 1558 /** 1559 * i40e_led_get - return current on/off mode 1560 * @hw: pointer to the hw struct 1561 * 1562 * The value returned is the 'mode' field as defined in the 1563 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1564 * values are variations of possible behaviors relating to 1565 * blink, link, and wire. 1566 **/ 1567 u32 i40e_led_get(struct i40e_hw *hw) 1568 { 1569 u32 current_mode = 0; 1570 u32 mode = 0; 1571 int i; 1572 1573 /* as per the documentation GPIO 22-29 are the LED 1574 * GPIO pins named LED0..LED7 1575 */ 1576 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1577 u32 gpio_val = i40e_led_is_mine(hw, i); 1578 1579 if (!gpio_val) 1580 continue; 1581 1582 /* ignore gpio LED src mode entries related to the activity 1583 * LEDs 1584 */ 1585 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1586 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1587 switch (current_mode) { 1588 case I40E_COMBINED_ACTIVITY: 1589 case I40E_FILTER_ACTIVITY: 1590 case I40E_MAC_ACTIVITY: 1591 case I40E_LINK_ACTIVITY: 1592 continue; 1593 default: 1594 break; 1595 } 1596 1597 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1598 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1599 break; 1600 } 1601 1602 return mode; 1603 } 1604 1605 /** 1606 * i40e_led_set - set new on/off mode 1607 * @hw: pointer to the hw struct 1608 * @mode: 0=off, 0xf=on (else see manual for mode details) 1609 * @blink: true if the LED should blink when on, false if steady 1610 * 1611 * if this function is used to turn on the blink it should 1612 * be used to disable the blink when restoring the original state. 1613 **/ 1614 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1615 { 1616 u32 current_mode = 0; 1617 int i; 1618 1619 if (mode & 0xfffffff0) 1620 DEBUGOUT1("invalid mode passed in %X\n", mode); 1621 1622 /* as per the documentation GPIO 22-29 are the LED 1623 * GPIO pins named LED0..LED7 1624 */ 1625 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1626 u32 gpio_val = i40e_led_is_mine(hw, i); 1627 1628 if (!gpio_val) 1629 continue; 1630 1631 /* ignore gpio LED src mode entries related to the activity 1632 * LEDs 1633 */ 1634 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1635 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1636 switch (current_mode) { 1637 case I40E_COMBINED_ACTIVITY: 1638 case I40E_FILTER_ACTIVITY: 1639 case I40E_MAC_ACTIVITY: 1640 case I40E_LINK_ACTIVITY: 1641 continue; 1642 default: 1643 break; 1644 } 1645 1646 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1647 /* this & is a bit of paranoia, but serves as a range check */ 1648 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1649 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1650 1651 if (blink) 1652 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1653 else 1654 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1655 1656 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1657 break; 1658 } 1659 } 1660 1661 /* Admin command wrappers */ 1662 1663 /** 1664 * i40e_aq_get_phy_capabilities 1665 * @hw: pointer to the hw struct 1666 * @abilities: structure for PHY capabilities to be filled 1667 * @qualified_modules: report Qualified Modules 1668 * @report_init: report init capabilities (active are default) 1669 * @cmd_details: pointer to command details structure or NULL 1670 * 1671 * Returns the various PHY abilities supported on the Port. 1672 **/ 1673 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1674 bool qualified_modules, bool report_init, 1675 struct i40e_aq_get_phy_abilities_resp *abilities, 1676 struct i40e_asq_cmd_details *cmd_details) 1677 { 1678 struct i40e_aq_desc desc; 1679 enum i40e_status_code status; 1680 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1681 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1682 1683 if (!abilities) 1684 return I40E_ERR_PARAM; 1685 1686 do { 1687 i40e_fill_default_direct_cmd_desc(&desc, 1688 i40e_aqc_opc_get_phy_abilities); 1689 1690 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1691 if (abilities_size > I40E_AQ_LARGE_BUF) 1692 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1693 1694 if (qualified_modules) 1695 desc.params.external.param0 |= 1696 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1697 1698 if (report_init) 1699 desc.params.external.param0 |= 1700 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1701 1702 status = i40e_asq_send_command(hw, &desc, abilities, 1703 abilities_size, cmd_details); 1704 1705 if (status != I40E_SUCCESS) 1706 break; 1707 1708 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { 1709 status = I40E_ERR_UNKNOWN_PHY; 1710 break; 1711 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { 1712 i40e_msec_delay(1); 1713 total_delay++; 1714 status = I40E_ERR_TIMEOUT; 1715 } 1716 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && 1717 (total_delay < max_delay)); 1718 1719 if (status != I40E_SUCCESS) 1720 return status; 1721 1722 if (report_init) { 1723 if (hw->mac.type == I40E_MAC_XL710 && 1724 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1725 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1726 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1727 } else { 1728 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1729 hw->phy.phy_types |= 1730 ((u64)abilities->phy_type_ext << 32); 1731 } 1732 } 1733 1734 return status; 1735 } 1736 1737 /** 1738 * i40e_aq_set_phy_config 1739 * @hw: pointer to the hw struct 1740 * @config: structure with PHY configuration to be set 1741 * @cmd_details: pointer to command details structure or NULL 1742 * 1743 * Set the various PHY configuration parameters 1744 * supported on the Port.One or more of the Set PHY config parameters may be 1745 * ignored in an MFP mode as the PF may not have the privilege to set some 1746 * of the PHY Config parameters. This status will be indicated by the 1747 * command response. 1748 **/ 1749 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1750 struct i40e_aq_set_phy_config *config, 1751 struct i40e_asq_cmd_details *cmd_details) 1752 { 1753 struct i40e_aq_desc desc; 1754 struct i40e_aq_set_phy_config *cmd = 1755 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1756 enum i40e_status_code status; 1757 1758 if (!config) 1759 return I40E_ERR_PARAM; 1760 1761 i40e_fill_default_direct_cmd_desc(&desc, 1762 i40e_aqc_opc_set_phy_config); 1763 1764 *cmd = *config; 1765 1766 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1767 1768 return status; 1769 } 1770 1771 /** 1772 * i40e_set_fc 1773 * @hw: pointer to the hw struct 1774 * @aq_failures: buffer to return AdminQ failure information 1775 * @atomic_restart: whether to enable atomic link restart 1776 * 1777 * Set the requested flow control mode using set_phy_config. 1778 **/ 1779 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1780 bool atomic_restart) 1781 { 1782 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1783 struct i40e_aq_get_phy_abilities_resp abilities; 1784 struct i40e_aq_set_phy_config config; 1785 enum i40e_status_code status; 1786 u8 pause_mask = 0x0; 1787 1788 *aq_failures = 0x0; 1789 1790 switch (fc_mode) { 1791 case I40E_FC_FULL: 1792 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1793 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1794 break; 1795 case I40E_FC_RX_PAUSE: 1796 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1797 break; 1798 case I40E_FC_TX_PAUSE: 1799 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1800 break; 1801 default: 1802 break; 1803 } 1804 1805 /* Get the current phy config */ 1806 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1807 NULL); 1808 if (status) { 1809 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1810 return status; 1811 } 1812 1813 memset(&config, 0, sizeof(config)); 1814 /* clear the old pause settings */ 1815 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1816 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1817 /* set the new abilities */ 1818 config.abilities |= pause_mask; 1819 /* If the abilities have changed, then set the new config */ 1820 if (config.abilities != abilities.abilities) { 1821 /* Auto restart link so settings take effect */ 1822 if (atomic_restart) 1823 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1824 /* Copy over all the old settings */ 1825 config.phy_type = abilities.phy_type; 1826 config.phy_type_ext = abilities.phy_type_ext; 1827 config.link_speed = abilities.link_speed; 1828 config.eee_capability = abilities.eee_capability; 1829 config.eeer = abilities.eeer_val; 1830 config.low_power_ctrl = abilities.d3_lpan; 1831 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1832 I40E_AQ_PHY_FEC_CONFIG_MASK; 1833 status = i40e_aq_set_phy_config(hw, &config, NULL); 1834 1835 if (status) 1836 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1837 } 1838 /* Update the link info */ 1839 status = i40e_update_link_info(hw); 1840 if (status) { 1841 /* Wait a little bit (on 40G cards it sometimes takes a really 1842 * long time for link to come back from the atomic reset) 1843 * and try once more 1844 */ 1845 i40e_msec_delay(1000); 1846 status = i40e_update_link_info(hw); 1847 } 1848 if (status) 1849 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1850 1851 return status; 1852 } 1853 1854 /** 1855 * i40e_aq_set_mac_config 1856 * @hw: pointer to the hw struct 1857 * @max_frame_size: Maximum Frame Size to be supported by the port 1858 * @crc_en: Tell HW to append a CRC to outgoing frames 1859 * @pacing: Pacing configurations 1860 * @cmd_details: pointer to command details structure or NULL 1861 * 1862 * Configure MAC settings for frame size, jumbo frame support and the 1863 * addition of a CRC by the hardware. 1864 **/ 1865 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1866 u16 max_frame_size, 1867 bool crc_en, u16 pacing, 1868 struct i40e_asq_cmd_details *cmd_details) 1869 { 1870 struct i40e_aq_desc desc; 1871 struct i40e_aq_set_mac_config *cmd = 1872 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1873 enum i40e_status_code status; 1874 1875 if (max_frame_size == 0) 1876 return I40E_ERR_PARAM; 1877 1878 i40e_fill_default_direct_cmd_desc(&desc, 1879 i40e_aqc_opc_set_mac_config); 1880 1881 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1882 cmd->params = ((u8)pacing & 0x0F) << 3; 1883 if (crc_en) 1884 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1885 1886 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF 1887 cmd->fc_refresh_threshold = 1888 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD); 1889 1890 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1891 1892 return status; 1893 } 1894 1895 /** 1896 * i40e_aq_clear_pxe_mode 1897 * @hw: pointer to the hw struct 1898 * @cmd_details: pointer to command details structure or NULL 1899 * 1900 * Tell the firmware that the driver is taking over from PXE 1901 **/ 1902 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1903 struct i40e_asq_cmd_details *cmd_details) 1904 { 1905 enum i40e_status_code status; 1906 struct i40e_aq_desc desc; 1907 struct i40e_aqc_clear_pxe *cmd = 1908 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1909 1910 i40e_fill_default_direct_cmd_desc(&desc, 1911 i40e_aqc_opc_clear_pxe_mode); 1912 1913 cmd->rx_cnt = 0x2; 1914 1915 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1916 1917 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1918 1919 return status; 1920 } 1921 1922 /** 1923 * i40e_aq_set_link_restart_an 1924 * @hw: pointer to the hw struct 1925 * @enable_link: if true: enable link, if false: disable link 1926 * @cmd_details: pointer to command details structure or NULL 1927 * 1928 * Sets up the link and restarts the Auto-Negotiation over the link. 1929 **/ 1930 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1931 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1932 { 1933 struct i40e_aq_desc desc; 1934 struct i40e_aqc_set_link_restart_an *cmd = 1935 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1936 enum i40e_status_code status; 1937 1938 i40e_fill_default_direct_cmd_desc(&desc, 1939 i40e_aqc_opc_set_link_restart_an); 1940 1941 cmd->command = I40E_AQ_PHY_RESTART_AN; 1942 if (enable_link) 1943 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1944 else 1945 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1946 1947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1948 1949 return status; 1950 } 1951 1952 /** 1953 * i40e_aq_get_link_info 1954 * @hw: pointer to the hw struct 1955 * @enable_lse: enable/disable LinkStatusEvent reporting 1956 * @link: pointer to link status structure - optional 1957 * @cmd_details: pointer to command details structure or NULL 1958 * 1959 * Returns the link status of the adapter. 1960 **/ 1961 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1962 bool enable_lse, struct i40e_link_status *link, 1963 struct i40e_asq_cmd_details *cmd_details) 1964 { 1965 struct i40e_aq_desc desc; 1966 struct i40e_aqc_get_link_status *resp = 1967 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1968 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1969 enum i40e_status_code status; 1970 bool tx_pause, rx_pause; 1971 u16 command_flags; 1972 1973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1974 1975 if (enable_lse) 1976 command_flags = I40E_AQ_LSE_ENABLE; 1977 else 1978 command_flags = I40E_AQ_LSE_DISABLE; 1979 resp->command_flags = CPU_TO_LE16(command_flags); 1980 1981 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1982 1983 if (status != I40E_SUCCESS) 1984 goto aq_get_link_info_exit; 1985 1986 /* save off old link status information */ 1987 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1988 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1989 1990 /* update link status */ 1991 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1992 hw->phy.media_type = i40e_get_media_type(hw); 1993 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1994 hw_link_info->link_info = resp->link_info; 1995 hw_link_info->an_info = resp->an_info; 1996 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1997 I40E_AQ_CONFIG_FEC_RS_ENA); 1998 hw_link_info->ext_info = resp->ext_info; 1999 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 2000 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 2001 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 2002 2003 /* update fc info */ 2004 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 2005 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 2006 if (tx_pause & rx_pause) 2007 hw->fc.current_mode = I40E_FC_FULL; 2008 else if (tx_pause) 2009 hw->fc.current_mode = I40E_FC_TX_PAUSE; 2010 else if (rx_pause) 2011 hw->fc.current_mode = I40E_FC_RX_PAUSE; 2012 else 2013 hw->fc.current_mode = I40E_FC_NONE; 2014 2015 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 2016 hw_link_info->crc_enable = true; 2017 else 2018 hw_link_info->crc_enable = false; 2019 2020 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 2021 hw_link_info->lse_enable = true; 2022 else 2023 hw_link_info->lse_enable = false; 2024 2025 if ((hw->mac.type == I40E_MAC_XL710) && 2026 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 2027 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 2028 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 2029 2030 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 2031 hw->aq.api_min_ver >= 7) { 2032 __le32 tmp; 2033 2034 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), 2035 I40E_NONDMA_TO_NONDMA); 2036 hw->phy.phy_types = LE32_TO_CPU(tmp); 2037 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 2038 } 2039 2040 /* save link status information */ 2041 if (link) 2042 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 2043 I40E_NONDMA_TO_NONDMA); 2044 2045 /* flag cleared so helper functions don't call AQ again */ 2046 hw->phy.get_link_info = false; 2047 2048 aq_get_link_info_exit: 2049 return status; 2050 } 2051 2052 /** 2053 * i40e_aq_set_phy_int_mask 2054 * @hw: pointer to the hw struct 2055 * @mask: interrupt mask to be set 2056 * @cmd_details: pointer to command details structure or NULL 2057 * 2058 * Set link interrupt mask. 2059 **/ 2060 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 2061 u16 mask, 2062 struct i40e_asq_cmd_details *cmd_details) 2063 { 2064 struct i40e_aq_desc desc; 2065 struct i40e_aqc_set_phy_int_mask *cmd = 2066 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 2067 enum i40e_status_code status; 2068 2069 i40e_fill_default_direct_cmd_desc(&desc, 2070 i40e_aqc_opc_set_phy_int_mask); 2071 2072 cmd->event_mask = CPU_TO_LE16(mask); 2073 2074 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2075 2076 return status; 2077 } 2078 2079 /** 2080 * i40e_aq_get_local_advt_reg 2081 * @hw: pointer to the hw struct 2082 * @advt_reg: local AN advertisement register value 2083 * @cmd_details: pointer to command details structure or NULL 2084 * 2085 * Get the Local AN advertisement register value. 2086 **/ 2087 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 2088 u64 *advt_reg, 2089 struct i40e_asq_cmd_details *cmd_details) 2090 { 2091 struct i40e_aq_desc desc; 2092 struct i40e_aqc_an_advt_reg *resp = 2093 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2094 enum i40e_status_code status; 2095 2096 i40e_fill_default_direct_cmd_desc(&desc, 2097 i40e_aqc_opc_get_local_advt_reg); 2098 2099 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2100 2101 if (status != I40E_SUCCESS) 2102 goto aq_get_local_advt_reg_exit; 2103 2104 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2105 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2106 2107 aq_get_local_advt_reg_exit: 2108 return status; 2109 } 2110 2111 /** 2112 * i40e_aq_set_local_advt_reg 2113 * @hw: pointer to the hw struct 2114 * @advt_reg: local AN advertisement register value 2115 * @cmd_details: pointer to command details structure or NULL 2116 * 2117 * Get the Local AN advertisement register value. 2118 **/ 2119 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2120 u64 advt_reg, 2121 struct i40e_asq_cmd_details *cmd_details) 2122 { 2123 struct i40e_aq_desc desc; 2124 struct i40e_aqc_an_advt_reg *cmd = 2125 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2126 enum i40e_status_code status; 2127 2128 i40e_fill_default_direct_cmd_desc(&desc, 2129 i40e_aqc_opc_get_local_advt_reg); 2130 2131 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2132 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2133 2134 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2135 2136 return status; 2137 } 2138 2139 /** 2140 * i40e_aq_get_partner_advt 2141 * @hw: pointer to the hw struct 2142 * @advt_reg: AN partner advertisement register value 2143 * @cmd_details: pointer to command details structure or NULL 2144 * 2145 * Get the link partner AN advertisement register value. 2146 **/ 2147 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2148 u64 *advt_reg, 2149 struct i40e_asq_cmd_details *cmd_details) 2150 { 2151 struct i40e_aq_desc desc; 2152 struct i40e_aqc_an_advt_reg *resp = 2153 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2154 enum i40e_status_code status; 2155 2156 i40e_fill_default_direct_cmd_desc(&desc, 2157 i40e_aqc_opc_get_partner_advt); 2158 2159 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2160 2161 if (status != I40E_SUCCESS) 2162 goto aq_get_partner_advt_exit; 2163 2164 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2165 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2166 2167 aq_get_partner_advt_exit: 2168 return status; 2169 } 2170 2171 /** 2172 * i40e_aq_set_lb_modes 2173 * @hw: pointer to the hw struct 2174 * @lb_modes: loopback mode to be set 2175 * @cmd_details: pointer to command details structure or NULL 2176 * 2177 * Sets loopback modes. 2178 **/ 2179 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 2180 u16 lb_modes, 2181 struct i40e_asq_cmd_details *cmd_details) 2182 { 2183 struct i40e_aq_desc desc; 2184 struct i40e_aqc_set_lb_mode *cmd = 2185 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2186 enum i40e_status_code status; 2187 2188 i40e_fill_default_direct_cmd_desc(&desc, 2189 i40e_aqc_opc_set_lb_modes); 2190 2191 cmd->lb_mode = CPU_TO_LE16(lb_modes); 2192 2193 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2194 2195 return status; 2196 } 2197 2198 /** 2199 * i40e_aq_set_phy_debug 2200 * @hw: pointer to the hw struct 2201 * @cmd_flags: debug command flags 2202 * @cmd_details: pointer to command details structure or NULL 2203 * 2204 * Reset the external PHY. 2205 **/ 2206 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2207 struct i40e_asq_cmd_details *cmd_details) 2208 { 2209 struct i40e_aq_desc desc; 2210 struct i40e_aqc_set_phy_debug *cmd = 2211 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2212 enum i40e_status_code status; 2213 2214 i40e_fill_default_direct_cmd_desc(&desc, 2215 i40e_aqc_opc_set_phy_debug); 2216 2217 cmd->command_flags = cmd_flags; 2218 2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2220 2221 return status; 2222 } 2223 2224 /** 2225 * i40e_aq_add_vsi 2226 * @hw: pointer to the hw struct 2227 * @vsi_ctx: pointer to a vsi context struct 2228 * @cmd_details: pointer to command details structure or NULL 2229 * 2230 * Add a VSI context to the hardware. 2231 **/ 2232 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2233 struct i40e_vsi_context *vsi_ctx, 2234 struct i40e_asq_cmd_details *cmd_details) 2235 { 2236 struct i40e_aq_desc desc; 2237 struct i40e_aqc_add_get_update_vsi *cmd = 2238 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2239 struct i40e_aqc_add_get_update_vsi_completion *resp = 2240 (struct i40e_aqc_add_get_update_vsi_completion *) 2241 &desc.params.raw; 2242 enum i40e_status_code status; 2243 2244 i40e_fill_default_direct_cmd_desc(&desc, 2245 i40e_aqc_opc_add_vsi); 2246 2247 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2248 cmd->connection_type = vsi_ctx->connection_type; 2249 cmd->vf_id = vsi_ctx->vf_num; 2250 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2251 2252 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2253 2254 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2255 sizeof(vsi_ctx->info), cmd_details); 2256 2257 if (status != I40E_SUCCESS) 2258 goto aq_add_vsi_exit; 2259 2260 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2261 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2262 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2263 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2264 2265 aq_add_vsi_exit: 2266 return status; 2267 } 2268 2269 /** 2270 * i40e_aq_set_default_vsi 2271 * @hw: pointer to the hw struct 2272 * @seid: vsi number 2273 * @cmd_details: pointer to command details structure or NULL 2274 **/ 2275 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2276 u16 seid, 2277 struct i40e_asq_cmd_details *cmd_details) 2278 { 2279 struct i40e_aq_desc desc; 2280 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2281 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2282 &desc.params.raw; 2283 enum i40e_status_code status; 2284 2285 i40e_fill_default_direct_cmd_desc(&desc, 2286 i40e_aqc_opc_set_vsi_promiscuous_modes); 2287 2288 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2289 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2290 cmd->seid = CPU_TO_LE16(seid); 2291 2292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2293 2294 return status; 2295 } 2296 2297 /** 2298 * i40e_aq_clear_default_vsi 2299 * @hw: pointer to the hw struct 2300 * @seid: vsi number 2301 * @cmd_details: pointer to command details structure or NULL 2302 **/ 2303 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2304 u16 seid, 2305 struct i40e_asq_cmd_details *cmd_details) 2306 { 2307 struct i40e_aq_desc desc; 2308 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2309 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2310 &desc.params.raw; 2311 enum i40e_status_code status; 2312 2313 i40e_fill_default_direct_cmd_desc(&desc, 2314 i40e_aqc_opc_set_vsi_promiscuous_modes); 2315 2316 cmd->promiscuous_flags = CPU_TO_LE16(0); 2317 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2318 cmd->seid = CPU_TO_LE16(seid); 2319 2320 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2321 2322 return status; 2323 } 2324 2325 /** 2326 * i40e_aq_set_vsi_unicast_promiscuous 2327 * @hw: pointer to the hw struct 2328 * @seid: vsi number 2329 * @set: set unicast promiscuous enable/disable 2330 * @cmd_details: pointer to command details structure or NULL 2331 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2332 **/ 2333 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2334 u16 seid, bool set, 2335 struct i40e_asq_cmd_details *cmd_details, 2336 bool rx_only_promisc) 2337 { 2338 struct i40e_aq_desc desc; 2339 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2340 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2341 enum i40e_status_code status; 2342 u16 flags = 0; 2343 2344 i40e_fill_default_direct_cmd_desc(&desc, 2345 i40e_aqc_opc_set_vsi_promiscuous_modes); 2346 2347 if (set) { 2348 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2349 if (rx_only_promisc && 2350 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2351 (hw->aq.api_maj_ver > 1))) 2352 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2353 } 2354 2355 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2356 2357 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2358 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2359 (hw->aq.api_maj_ver > 1)) 2360 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2361 2362 cmd->seid = CPU_TO_LE16(seid); 2363 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2364 2365 return status; 2366 } 2367 2368 /** 2369 * i40e_aq_set_vsi_multicast_promiscuous 2370 * @hw: pointer to the hw struct 2371 * @seid: vsi number 2372 * @set: set multicast promiscuous enable/disable 2373 * @cmd_details: pointer to command details structure or NULL 2374 **/ 2375 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2376 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2377 { 2378 struct i40e_aq_desc desc; 2379 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2380 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2381 enum i40e_status_code status; 2382 u16 flags = 0; 2383 2384 i40e_fill_default_direct_cmd_desc(&desc, 2385 i40e_aqc_opc_set_vsi_promiscuous_modes); 2386 2387 if (set) 2388 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2389 2390 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2391 2392 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2393 2394 cmd->seid = CPU_TO_LE16(seid); 2395 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2396 2397 return status; 2398 } 2399 2400 /** 2401 * i40e_aq_set_vsi_full_promiscuous 2402 * @hw: pointer to the hw struct 2403 * @seid: VSI number 2404 * @set: set promiscuous enable/disable 2405 * @cmd_details: pointer to command details structure or NULL 2406 **/ 2407 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw, 2408 u16 seid, bool set, 2409 struct i40e_asq_cmd_details *cmd_details) 2410 { 2411 struct i40e_aq_desc desc; 2412 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2413 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2414 enum i40e_status_code status; 2415 u16 flags = 0; 2416 2417 i40e_fill_default_direct_cmd_desc(&desc, 2418 i40e_aqc_opc_set_vsi_promiscuous_modes); 2419 2420 if (set) 2421 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST | 2422 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2423 I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2424 2425 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2426 2427 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST | 2428 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2429 I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2430 2431 cmd->seid = CPU_TO_LE16(seid); 2432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2433 2434 return status; 2435 } 2436 2437 /** 2438 * i40e_aq_set_vsi_mc_promisc_on_vlan 2439 * @hw: pointer to the hw struct 2440 * @seid: vsi number 2441 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2442 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2443 * @cmd_details: pointer to command details structure or NULL 2444 **/ 2445 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2446 u16 seid, bool enable, u16 vid, 2447 struct i40e_asq_cmd_details *cmd_details) 2448 { 2449 struct i40e_aq_desc desc; 2450 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2451 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2452 enum i40e_status_code status; 2453 u16 flags = 0; 2454 2455 i40e_fill_default_direct_cmd_desc(&desc, 2456 i40e_aqc_opc_set_vsi_promiscuous_modes); 2457 2458 if (enable) 2459 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2460 2461 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2462 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2463 cmd->seid = CPU_TO_LE16(seid); 2464 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2465 2466 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2467 2468 return status; 2469 } 2470 2471 /** 2472 * i40e_aq_set_vsi_uc_promisc_on_vlan 2473 * @hw: pointer to the hw struct 2474 * @seid: vsi number 2475 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2476 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2477 * @cmd_details: pointer to command details structure or NULL 2478 **/ 2479 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2480 u16 seid, bool enable, u16 vid, 2481 struct i40e_asq_cmd_details *cmd_details) 2482 { 2483 struct i40e_aq_desc desc; 2484 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2485 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2486 enum i40e_status_code status; 2487 u16 flags = 0; 2488 2489 i40e_fill_default_direct_cmd_desc(&desc, 2490 i40e_aqc_opc_set_vsi_promiscuous_modes); 2491 2492 if (enable) 2493 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2494 2495 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2496 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2497 cmd->seid = CPU_TO_LE16(seid); 2498 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2499 2500 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2501 2502 return status; 2503 } 2504 2505 /** 2506 * i40e_aq_set_vsi_bc_promisc_on_vlan 2507 * @hw: pointer to the hw struct 2508 * @seid: vsi number 2509 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2510 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2511 * @cmd_details: pointer to command details structure or NULL 2512 **/ 2513 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2514 u16 seid, bool enable, u16 vid, 2515 struct i40e_asq_cmd_details *cmd_details) 2516 { 2517 struct i40e_aq_desc desc; 2518 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2519 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2520 enum i40e_status_code status; 2521 u16 flags = 0; 2522 2523 i40e_fill_default_direct_cmd_desc(&desc, 2524 i40e_aqc_opc_set_vsi_promiscuous_modes); 2525 2526 if (enable) 2527 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2528 2529 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2530 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2531 cmd->seid = CPU_TO_LE16(seid); 2532 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2533 2534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2535 2536 return status; 2537 } 2538 2539 /** 2540 * i40e_aq_set_vsi_broadcast 2541 * @hw: pointer to the hw struct 2542 * @seid: vsi number 2543 * @set_filter: true to set filter, false to clear filter 2544 * @cmd_details: pointer to command details structure or NULL 2545 * 2546 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2547 **/ 2548 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2549 u16 seid, bool set_filter, 2550 struct i40e_asq_cmd_details *cmd_details) 2551 { 2552 struct i40e_aq_desc desc; 2553 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2554 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2555 enum i40e_status_code status; 2556 2557 i40e_fill_default_direct_cmd_desc(&desc, 2558 i40e_aqc_opc_set_vsi_promiscuous_modes); 2559 2560 if (set_filter) 2561 cmd->promiscuous_flags 2562 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2563 else 2564 cmd->promiscuous_flags 2565 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2566 2567 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2568 cmd->seid = CPU_TO_LE16(seid); 2569 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2570 2571 return status; 2572 } 2573 2574 /** 2575 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2576 * @hw: pointer to the hw struct 2577 * @seid: vsi number 2578 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2579 * @cmd_details: pointer to command details structure or NULL 2580 **/ 2581 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2582 u16 seid, bool enable, 2583 struct i40e_asq_cmd_details *cmd_details) 2584 { 2585 struct i40e_aq_desc desc; 2586 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2587 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2588 enum i40e_status_code status; 2589 u16 flags = 0; 2590 2591 i40e_fill_default_direct_cmd_desc(&desc, 2592 i40e_aqc_opc_set_vsi_promiscuous_modes); 2593 if (enable) 2594 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2595 2596 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2597 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2598 cmd->seid = CPU_TO_LE16(seid); 2599 2600 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2601 2602 return status; 2603 } 2604 2605 /** 2606 * i40e_get_vsi_params - get VSI configuration info 2607 * @hw: pointer to the hw struct 2608 * @vsi_ctx: pointer to a vsi context struct 2609 * @cmd_details: pointer to command details structure or NULL 2610 **/ 2611 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2612 struct i40e_vsi_context *vsi_ctx, 2613 struct i40e_asq_cmd_details *cmd_details) 2614 { 2615 struct i40e_aq_desc desc; 2616 struct i40e_aqc_add_get_update_vsi *cmd = 2617 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2618 struct i40e_aqc_add_get_update_vsi_completion *resp = 2619 (struct i40e_aqc_add_get_update_vsi_completion *) 2620 &desc.params.raw; 2621 enum i40e_status_code status; 2622 2623 UNREFERENCED_1PARAMETER(cmd_details); 2624 i40e_fill_default_direct_cmd_desc(&desc, 2625 i40e_aqc_opc_get_vsi_parameters); 2626 2627 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2628 2629 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2630 2631 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2632 sizeof(vsi_ctx->info), NULL); 2633 2634 if (status != I40E_SUCCESS) 2635 goto aq_get_vsi_params_exit; 2636 2637 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2638 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2639 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2640 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2641 2642 aq_get_vsi_params_exit: 2643 return status; 2644 } 2645 2646 /** 2647 * i40e_aq_update_vsi_params 2648 * @hw: pointer to the hw struct 2649 * @vsi_ctx: pointer to a vsi context struct 2650 * @cmd_details: pointer to command details structure or NULL 2651 * 2652 * Update a VSI context. 2653 **/ 2654 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2655 struct i40e_vsi_context *vsi_ctx, 2656 struct i40e_asq_cmd_details *cmd_details) 2657 { 2658 struct i40e_aq_desc desc; 2659 struct i40e_aqc_add_get_update_vsi *cmd = 2660 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2661 struct i40e_aqc_add_get_update_vsi_completion *resp = 2662 (struct i40e_aqc_add_get_update_vsi_completion *) 2663 &desc.params.raw; 2664 enum i40e_status_code status; 2665 2666 i40e_fill_default_direct_cmd_desc(&desc, 2667 i40e_aqc_opc_update_vsi_parameters); 2668 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2669 2670 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2671 2672 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2673 sizeof(vsi_ctx->info), cmd_details); 2674 2675 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2676 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2677 2678 return status; 2679 } 2680 2681 /** 2682 * i40e_aq_get_switch_config 2683 * @hw: pointer to the hardware structure 2684 * @buf: pointer to the result buffer 2685 * @buf_size: length of input buffer 2686 * @start_seid: seid to start for the report, 0 == beginning 2687 * @cmd_details: pointer to command details structure or NULL 2688 * 2689 * Fill the buf with switch configuration returned from AdminQ command 2690 **/ 2691 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2692 struct i40e_aqc_get_switch_config_resp *buf, 2693 u16 buf_size, u16 *start_seid, 2694 struct i40e_asq_cmd_details *cmd_details) 2695 { 2696 struct i40e_aq_desc desc; 2697 struct i40e_aqc_switch_seid *scfg = 2698 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2699 enum i40e_status_code status; 2700 2701 i40e_fill_default_direct_cmd_desc(&desc, 2702 i40e_aqc_opc_get_switch_config); 2703 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2704 if (buf_size > I40E_AQ_LARGE_BUF) 2705 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2706 scfg->seid = CPU_TO_LE16(*start_seid); 2707 2708 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2709 *start_seid = LE16_TO_CPU(scfg->seid); 2710 2711 return status; 2712 } 2713 2714 /** 2715 * i40e_aq_set_switch_config 2716 * @hw: pointer to the hardware structure 2717 * @flags: bit flag values to set 2718 * @mode: cloud filter mode 2719 * @valid_flags: which bit flags to set 2720 * @cmd_details: pointer to command details structure or NULL 2721 * 2722 * Set switch configuration bits 2723 **/ 2724 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2725 u16 flags, u16 valid_flags, u8 mode, 2726 struct i40e_asq_cmd_details *cmd_details) 2727 { 2728 struct i40e_aq_desc desc; 2729 struct i40e_aqc_set_switch_config *scfg = 2730 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2731 enum i40e_status_code status; 2732 2733 i40e_fill_default_direct_cmd_desc(&desc, 2734 i40e_aqc_opc_set_switch_config); 2735 scfg->flags = CPU_TO_LE16(flags); 2736 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2737 scfg->mode = mode; 2738 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2739 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag); 2740 scfg->first_tag = CPU_TO_LE16(hw->first_tag); 2741 scfg->second_tag = CPU_TO_LE16(hw->second_tag); 2742 } 2743 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2744 2745 return status; 2746 } 2747 2748 /** 2749 * i40e_aq_get_firmware_version 2750 * @hw: pointer to the hw struct 2751 * @fw_major_version: firmware major version 2752 * @fw_minor_version: firmware minor version 2753 * @fw_build: firmware build number 2754 * @api_major_version: major queue version 2755 * @api_minor_version: minor queue version 2756 * @cmd_details: pointer to command details structure or NULL 2757 * 2758 * Get the firmware version from the admin queue commands 2759 **/ 2760 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2761 u16 *fw_major_version, u16 *fw_minor_version, 2762 u32 *fw_build, 2763 u16 *api_major_version, u16 *api_minor_version, 2764 struct i40e_asq_cmd_details *cmd_details) 2765 { 2766 struct i40e_aq_desc desc; 2767 struct i40e_aqc_get_version *resp = 2768 (struct i40e_aqc_get_version *)&desc.params.raw; 2769 enum i40e_status_code status; 2770 2771 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2772 2773 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2774 2775 if (status == I40E_SUCCESS) { 2776 if (fw_major_version != NULL) 2777 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2778 if (fw_minor_version != NULL) 2779 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2780 if (fw_build != NULL) 2781 *fw_build = LE32_TO_CPU(resp->fw_build); 2782 if (api_major_version != NULL) 2783 *api_major_version = LE16_TO_CPU(resp->api_major); 2784 if (api_minor_version != NULL) 2785 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2786 2787 /* A workaround to fix the API version in SW */ 2788 if (api_major_version && api_minor_version && 2789 fw_major_version && fw_minor_version && 2790 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2791 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2792 (*fw_major_version > 4))) 2793 *api_minor_version = 2; 2794 } 2795 2796 return status; 2797 } 2798 2799 /** 2800 * i40e_aq_send_driver_version 2801 * @hw: pointer to the hw struct 2802 * @dv: driver's major, minor version 2803 * @cmd_details: pointer to command details structure or NULL 2804 * 2805 * Send the driver version to the firmware 2806 **/ 2807 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2808 struct i40e_driver_version *dv, 2809 struct i40e_asq_cmd_details *cmd_details) 2810 { 2811 struct i40e_aq_desc desc; 2812 struct i40e_aqc_driver_version *cmd = 2813 (struct i40e_aqc_driver_version *)&desc.params.raw; 2814 enum i40e_status_code status; 2815 u16 len; 2816 2817 if (dv == NULL) 2818 return I40E_ERR_PARAM; 2819 2820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2821 2822 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2823 cmd->driver_major_ver = dv->major_version; 2824 cmd->driver_minor_ver = dv->minor_version; 2825 cmd->driver_build_ver = dv->build_version; 2826 cmd->driver_subbuild_ver = dv->subbuild_version; 2827 2828 len = 0; 2829 while (len < sizeof(dv->driver_string) && 2830 (dv->driver_string[len] < 0x80) && 2831 dv->driver_string[len]) 2832 len++; 2833 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2834 len, cmd_details); 2835 2836 return status; 2837 } 2838 2839 /** 2840 * i40e_get_link_status - get status of the HW network link 2841 * @hw: pointer to the hw struct 2842 * @link_up: pointer to bool (true/false = linkup/linkdown) 2843 * 2844 * Variable link_up true if link is up, false if link is down. 2845 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2846 * 2847 * Side effect: LinkStatusEvent reporting becomes enabled 2848 **/ 2849 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2850 { 2851 enum i40e_status_code status = I40E_SUCCESS; 2852 2853 if (hw->phy.get_link_info) { 2854 status = i40e_update_link_info(hw); 2855 2856 if (status != I40E_SUCCESS) 2857 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2858 status); 2859 } 2860 2861 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2862 2863 return status; 2864 } 2865 2866 /** 2867 * i40e_updatelink_status - update status of the HW network link 2868 * @hw: pointer to the hw struct 2869 **/ 2870 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2871 { 2872 struct i40e_aq_get_phy_abilities_resp abilities; 2873 enum i40e_status_code status = I40E_SUCCESS; 2874 2875 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2876 if (status) 2877 return status; 2878 2879 /* extra checking needed to ensure link info to user is timely */ 2880 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2881 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2882 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2883 status = i40e_aq_get_phy_capabilities(hw, false, false, 2884 &abilities, NULL); 2885 if (status) 2886 return status; 2887 2888 hw->phy.link_info.req_fec_info = 2889 abilities.fec_cfg_curr_mod_ext_info & 2890 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2891 2892 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2893 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2894 } 2895 return status; 2896 } 2897 2898 2899 /** 2900 * i40e_get_link_speed 2901 * @hw: pointer to the hw struct 2902 * 2903 * Returns the link speed of the adapter. 2904 **/ 2905 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2906 { 2907 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2908 enum i40e_status_code status = I40E_SUCCESS; 2909 2910 if (hw->phy.get_link_info) { 2911 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2912 2913 if (status != I40E_SUCCESS) 2914 goto i40e_link_speed_exit; 2915 } 2916 2917 speed = hw->phy.link_info.link_speed; 2918 2919 i40e_link_speed_exit: 2920 return speed; 2921 } 2922 2923 /** 2924 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2925 * @hw: pointer to the hw struct 2926 * @uplink_seid: the MAC or other gizmo SEID 2927 * @downlink_seid: the VSI SEID 2928 * @enabled_tc: bitmap of TCs to be enabled 2929 * @default_port: true for default port VSI, false for control port 2930 * @veb_seid: pointer to where to put the resulting VEB SEID 2931 * @enable_stats: true to turn on VEB stats 2932 * @cmd_details: pointer to command details structure or NULL 2933 * 2934 * This asks the FW to add a VEB between the uplink and downlink 2935 * elements. If the uplink SEID is 0, this will be a floating VEB. 2936 **/ 2937 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2938 u16 downlink_seid, u8 enabled_tc, 2939 bool default_port, u16 *veb_seid, 2940 bool enable_stats, 2941 struct i40e_asq_cmd_details *cmd_details) 2942 { 2943 struct i40e_aq_desc desc; 2944 struct i40e_aqc_add_veb *cmd = 2945 (struct i40e_aqc_add_veb *)&desc.params.raw; 2946 struct i40e_aqc_add_veb_completion *resp = 2947 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2948 enum i40e_status_code status; 2949 u16 veb_flags = 0; 2950 2951 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2952 if (!!uplink_seid != !!downlink_seid) 2953 return I40E_ERR_PARAM; 2954 2955 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2956 2957 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2958 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2959 cmd->enable_tcs = enabled_tc; 2960 if (!uplink_seid) 2961 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2962 if (default_port) 2963 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2964 else 2965 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2966 2967 /* reverse logic here: set the bitflag to disable the stats */ 2968 if (!enable_stats) 2969 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2970 2971 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2972 2973 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2974 2975 if (!status && veb_seid) 2976 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2977 2978 return status; 2979 } 2980 2981 /** 2982 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2983 * @hw: pointer to the hw struct 2984 * @veb_seid: the SEID of the VEB to query 2985 * @switch_id: the uplink switch id 2986 * @floating: set to true if the VEB is floating 2987 * @statistic_index: index of the stats counter block for this VEB 2988 * @vebs_used: number of VEB's used by function 2989 * @vebs_free: total VEB's not reserved by any function 2990 * @cmd_details: pointer to command details structure or NULL 2991 * 2992 * This retrieves the parameters for a particular VEB, specified by 2993 * uplink_seid, and returns them to the caller. 2994 **/ 2995 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2996 u16 veb_seid, u16 *switch_id, 2997 bool *floating, u16 *statistic_index, 2998 u16 *vebs_used, u16 *vebs_free, 2999 struct i40e_asq_cmd_details *cmd_details) 3000 { 3001 struct i40e_aq_desc desc; 3002 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 3003 (struct i40e_aqc_get_veb_parameters_completion *) 3004 &desc.params.raw; 3005 enum i40e_status_code status; 3006 3007 if (veb_seid == 0) 3008 return I40E_ERR_PARAM; 3009 3010 i40e_fill_default_direct_cmd_desc(&desc, 3011 i40e_aqc_opc_get_veb_parameters); 3012 cmd_resp->seid = CPU_TO_LE16(veb_seid); 3013 3014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3015 if (status) 3016 goto get_veb_exit; 3017 3018 if (switch_id) 3019 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 3020 if (statistic_index) 3021 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 3022 if (vebs_used) 3023 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 3024 if (vebs_free) 3025 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 3026 if (floating) { 3027 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 3028 3029 if (flags & I40E_AQC_ADD_VEB_FLOATING) 3030 *floating = true; 3031 else 3032 *floating = false; 3033 } 3034 3035 get_veb_exit: 3036 return status; 3037 } 3038 3039 /** 3040 * i40e_aq_add_macvlan 3041 * @hw: pointer to the hw struct 3042 * @seid: VSI for the mac address 3043 * @mv_list: list of macvlans to be added 3044 * @count: length of the list 3045 * @cmd_details: pointer to command details structure or NULL 3046 * 3047 * Add MAC/VLAN addresses to the HW filtering 3048 **/ 3049 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 3050 struct i40e_aqc_add_macvlan_element_data *mv_list, 3051 u16 count, struct i40e_asq_cmd_details *cmd_details) 3052 { 3053 struct i40e_aq_desc desc; 3054 struct i40e_aqc_macvlan *cmd = 3055 (struct i40e_aqc_macvlan *)&desc.params.raw; 3056 enum i40e_status_code status; 3057 u16 buf_size; 3058 int i; 3059 3060 if (count == 0 || !mv_list || !hw) 3061 return I40E_ERR_PARAM; 3062 3063 buf_size = count * sizeof(*mv_list); 3064 3065 /* prep the rest of the request */ 3066 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 3067 cmd->num_addresses = CPU_TO_LE16(count); 3068 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3069 cmd->seid[1] = 0; 3070 cmd->seid[2] = 0; 3071 3072 for (i = 0; i < count; i++) 3073 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 3074 mv_list[i].flags |= 3075 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 3076 3077 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3078 if (buf_size > I40E_AQ_LARGE_BUF) 3079 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3080 3081 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3082 cmd_details); 3083 3084 return status; 3085 } 3086 3087 /** 3088 * i40e_aq_remove_macvlan 3089 * @hw: pointer to the hw struct 3090 * @seid: VSI for the mac address 3091 * @mv_list: list of macvlans to be removed 3092 * @count: length of the list 3093 * @cmd_details: pointer to command details structure or NULL 3094 * 3095 * Remove MAC/VLAN addresses from the HW filtering 3096 **/ 3097 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 3098 struct i40e_aqc_remove_macvlan_element_data *mv_list, 3099 u16 count, struct i40e_asq_cmd_details *cmd_details) 3100 { 3101 struct i40e_aq_desc desc; 3102 struct i40e_aqc_macvlan *cmd = 3103 (struct i40e_aqc_macvlan *)&desc.params.raw; 3104 enum i40e_status_code status; 3105 u16 buf_size; 3106 3107 if (count == 0 || !mv_list || !hw) 3108 return I40E_ERR_PARAM; 3109 3110 buf_size = count * sizeof(*mv_list); 3111 3112 /* prep the rest of the request */ 3113 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 3114 cmd->num_addresses = CPU_TO_LE16(count); 3115 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3116 cmd->seid[1] = 0; 3117 cmd->seid[2] = 0; 3118 3119 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3120 if (buf_size > I40E_AQ_LARGE_BUF) 3121 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3122 3123 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3124 cmd_details); 3125 3126 return status; 3127 } 3128 3129 /** 3130 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 3131 * @hw: pointer to the hw struct 3132 * @opcode: AQ opcode for add or delete mirror rule 3133 * @sw_seid: Switch SEID (to which rule refers) 3134 * @rule_type: Rule Type (ingress/egress/VLAN) 3135 * @id: Destination VSI SEID or Rule ID 3136 * @count: length of the list 3137 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3138 * @cmd_details: pointer to command details structure or NULL 3139 * @rule_id: Rule ID returned from FW 3140 * @rules_used: Number of rules used in internal switch 3141 * @rules_free: Number of rules free in internal switch 3142 * 3143 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 3144 * VEBs/VEPA elements only 3145 **/ 3146 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 3147 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 3148 u16 count, __le16 *mr_list, 3149 struct i40e_asq_cmd_details *cmd_details, 3150 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3151 { 3152 struct i40e_aq_desc desc; 3153 struct i40e_aqc_add_delete_mirror_rule *cmd = 3154 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 3155 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 3156 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 3157 enum i40e_status_code status; 3158 u16 buf_size; 3159 3160 buf_size = count * sizeof(*mr_list); 3161 3162 /* prep the rest of the request */ 3163 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3164 cmd->seid = CPU_TO_LE16(sw_seid); 3165 cmd->rule_type = CPU_TO_LE16(rule_type & 3166 I40E_AQC_MIRROR_RULE_TYPE_MASK); 3167 cmd->num_entries = CPU_TO_LE16(count); 3168 /* Dest VSI for add, rule_id for delete */ 3169 cmd->destination = CPU_TO_LE16(id); 3170 if (mr_list) { 3171 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3172 I40E_AQ_FLAG_RD)); 3173 if (buf_size > I40E_AQ_LARGE_BUF) 3174 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3175 } 3176 3177 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3178 cmd_details); 3179 if (status == I40E_SUCCESS || 3180 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3181 if (rule_id) 3182 *rule_id = LE16_TO_CPU(resp->rule_id); 3183 if (rules_used) 3184 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3185 if (rules_free) 3186 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3187 } 3188 return status; 3189 } 3190 3191 /** 3192 * i40e_aq_add_mirrorrule - add a mirror rule 3193 * @hw: pointer to the hw struct 3194 * @sw_seid: Switch SEID (to which rule refers) 3195 * @rule_type: Rule Type (ingress/egress/VLAN) 3196 * @dest_vsi: SEID of VSI to which packets will be mirrored 3197 * @count: length of the list 3198 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3199 * @cmd_details: pointer to command details structure or NULL 3200 * @rule_id: Rule ID returned from FW 3201 * @rules_used: Number of rules used in internal switch 3202 * @rules_free: Number of rules free in internal switch 3203 * 3204 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3205 **/ 3206 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3207 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3208 struct i40e_asq_cmd_details *cmd_details, 3209 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3210 { 3211 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3212 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3213 if (count == 0 || !mr_list) 3214 return I40E_ERR_PARAM; 3215 } 3216 3217 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3218 rule_type, dest_vsi, count, mr_list, 3219 cmd_details, rule_id, rules_used, rules_free); 3220 } 3221 3222 /** 3223 * i40e_aq_delete_mirrorrule - delete a mirror rule 3224 * @hw: pointer to the hw struct 3225 * @sw_seid: Switch SEID (to which rule refers) 3226 * @rule_type: Rule Type (ingress/egress/VLAN) 3227 * @count: length of the list 3228 * @rule_id: Rule ID that is returned in the receive desc as part of 3229 * add_mirrorrule. 3230 * @mr_list: list of mirrored VLAN IDs to be removed 3231 * @cmd_details: pointer to command details structure or NULL 3232 * @rules_used: Number of rules used in internal switch 3233 * @rules_free: Number of rules free in internal switch 3234 * 3235 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3236 **/ 3237 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3238 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3239 struct i40e_asq_cmd_details *cmd_details, 3240 u16 *rules_used, u16 *rules_free) 3241 { 3242 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3243 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3244 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3245 * mirroring. For other rule_type, count and rule_type should 3246 * not matter. 3247 */ 3248 if (count == 0 || !mr_list) 3249 return I40E_ERR_PARAM; 3250 } 3251 3252 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3253 rule_type, rule_id, count, mr_list, 3254 cmd_details, NULL, rules_used, rules_free); 3255 } 3256 3257 /** 3258 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3259 * @hw: pointer to the hw struct 3260 * @seid: VSI for the vlan filters 3261 * @v_list: list of vlan filters to be added 3262 * @count: length of the list 3263 * @cmd_details: pointer to command details structure or NULL 3264 **/ 3265 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3266 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3267 u8 count, struct i40e_asq_cmd_details *cmd_details) 3268 { 3269 struct i40e_aq_desc desc; 3270 struct i40e_aqc_macvlan *cmd = 3271 (struct i40e_aqc_macvlan *)&desc.params.raw; 3272 enum i40e_status_code status; 3273 u16 buf_size; 3274 3275 if (count == 0 || !v_list || !hw) 3276 return I40E_ERR_PARAM; 3277 3278 buf_size = count * sizeof(*v_list); 3279 3280 /* prep the rest of the request */ 3281 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3282 cmd->num_addresses = CPU_TO_LE16(count); 3283 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3284 cmd->seid[1] = 0; 3285 cmd->seid[2] = 0; 3286 3287 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3288 if (buf_size > I40E_AQ_LARGE_BUF) 3289 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3290 3291 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3292 cmd_details); 3293 3294 return status; 3295 } 3296 3297 /** 3298 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3299 * @hw: pointer to the hw struct 3300 * @seid: VSI for the vlan filters 3301 * @v_list: list of macvlans to be removed 3302 * @count: length of the list 3303 * @cmd_details: pointer to command details structure or NULL 3304 **/ 3305 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3306 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3307 u8 count, struct i40e_asq_cmd_details *cmd_details) 3308 { 3309 struct i40e_aq_desc desc; 3310 struct i40e_aqc_macvlan *cmd = 3311 (struct i40e_aqc_macvlan *)&desc.params.raw; 3312 enum i40e_status_code status; 3313 u16 buf_size; 3314 3315 if (count == 0 || !v_list || !hw) 3316 return I40E_ERR_PARAM; 3317 3318 buf_size = count * sizeof(*v_list); 3319 3320 /* prep the rest of the request */ 3321 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3322 cmd->num_addresses = CPU_TO_LE16(count); 3323 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3324 cmd->seid[1] = 0; 3325 cmd->seid[2] = 0; 3326 3327 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3328 if (buf_size > I40E_AQ_LARGE_BUF) 3329 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3330 3331 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3332 cmd_details); 3333 3334 return status; 3335 } 3336 3337 /** 3338 * i40e_aq_send_msg_to_vf 3339 * @hw: pointer to the hardware structure 3340 * @vfid: vf id to send msg 3341 * @v_opcode: opcodes for VF-PF communication 3342 * @v_retval: return error code 3343 * @msg: pointer to the msg buffer 3344 * @msglen: msg length 3345 * @cmd_details: pointer to command details 3346 * 3347 * send msg to vf 3348 **/ 3349 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3350 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3351 struct i40e_asq_cmd_details *cmd_details) 3352 { 3353 struct i40e_aq_desc desc; 3354 struct i40e_aqc_pf_vf_message *cmd = 3355 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3356 enum i40e_status_code status; 3357 3358 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3359 cmd->id = CPU_TO_LE32(vfid); 3360 desc.cookie_high = CPU_TO_LE32(v_opcode); 3361 desc.cookie_low = CPU_TO_LE32(v_retval); 3362 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3363 if (msglen) { 3364 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3365 I40E_AQ_FLAG_RD)); 3366 if (msglen > I40E_AQ_LARGE_BUF) 3367 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3368 desc.datalen = CPU_TO_LE16(msglen); 3369 } 3370 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3371 3372 return status; 3373 } 3374 3375 /** 3376 * i40e_aq_debug_read_register 3377 * @hw: pointer to the hw struct 3378 * @reg_addr: register address 3379 * @reg_val: register value 3380 * @cmd_details: pointer to command details structure or NULL 3381 * 3382 * Read the register using the admin queue commands 3383 **/ 3384 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3385 u32 reg_addr, u64 *reg_val, 3386 struct i40e_asq_cmd_details *cmd_details) 3387 { 3388 struct i40e_aq_desc desc; 3389 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3390 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3391 enum i40e_status_code status; 3392 3393 if (reg_val == NULL) 3394 return I40E_ERR_PARAM; 3395 3396 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3397 3398 cmd_resp->address = CPU_TO_LE32(reg_addr); 3399 3400 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3401 3402 if (status == I40E_SUCCESS) { 3403 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3404 (u64)LE32_TO_CPU(cmd_resp->value_low); 3405 } 3406 3407 return status; 3408 } 3409 3410 /** 3411 * i40e_aq_debug_write_register 3412 * @hw: pointer to the hw struct 3413 * @reg_addr: register address 3414 * @reg_val: register value 3415 * @cmd_details: pointer to command details structure or NULL 3416 * 3417 * Write to a register using the admin queue commands 3418 **/ 3419 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3420 u32 reg_addr, u64 reg_val, 3421 struct i40e_asq_cmd_details *cmd_details) 3422 { 3423 struct i40e_aq_desc desc; 3424 struct i40e_aqc_debug_reg_read_write *cmd = 3425 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3426 enum i40e_status_code status; 3427 3428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3429 3430 cmd->address = CPU_TO_LE32(reg_addr); 3431 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3432 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3433 3434 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3435 3436 return status; 3437 } 3438 3439 /** 3440 * i40e_aq_request_resource 3441 * @hw: pointer to the hw struct 3442 * @resource: resource id 3443 * @access: access type 3444 * @sdp_number: resource number 3445 * @timeout: the maximum time in ms that the driver may hold the resource 3446 * @cmd_details: pointer to command details structure or NULL 3447 * 3448 * requests common resource using the admin queue commands 3449 **/ 3450 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3451 enum i40e_aq_resources_ids resource, 3452 enum i40e_aq_resource_access_type access, 3453 u8 sdp_number, u64 *timeout, 3454 struct i40e_asq_cmd_details *cmd_details) 3455 { 3456 struct i40e_aq_desc desc; 3457 struct i40e_aqc_request_resource *cmd_resp = 3458 (struct i40e_aqc_request_resource *)&desc.params.raw; 3459 enum i40e_status_code status; 3460 3461 DEBUGFUNC("i40e_aq_request_resource"); 3462 3463 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3464 3465 cmd_resp->resource_id = CPU_TO_LE16(resource); 3466 cmd_resp->access_type = CPU_TO_LE16(access); 3467 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3468 3469 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3470 /* The completion specifies the maximum time in ms that the driver 3471 * may hold the resource in the Timeout field. 3472 * If the resource is held by someone else, the command completes with 3473 * busy return value and the timeout field indicates the maximum time 3474 * the current owner of the resource has to free it. 3475 */ 3476 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3477 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3478 3479 return status; 3480 } 3481 3482 /** 3483 * i40e_aq_release_resource 3484 * @hw: pointer to the hw struct 3485 * @resource: resource id 3486 * @sdp_number: resource number 3487 * @cmd_details: pointer to command details structure or NULL 3488 * 3489 * release common resource using the admin queue commands 3490 **/ 3491 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3492 enum i40e_aq_resources_ids resource, 3493 u8 sdp_number, 3494 struct i40e_asq_cmd_details *cmd_details) 3495 { 3496 struct i40e_aq_desc desc; 3497 struct i40e_aqc_request_resource *cmd = 3498 (struct i40e_aqc_request_resource *)&desc.params.raw; 3499 enum i40e_status_code status; 3500 3501 DEBUGFUNC("i40e_aq_release_resource"); 3502 3503 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3504 3505 cmd->resource_id = CPU_TO_LE16(resource); 3506 cmd->resource_number = CPU_TO_LE32(sdp_number); 3507 3508 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3509 3510 return status; 3511 } 3512 3513 /** 3514 * i40e_aq_read_nvm 3515 * @hw: pointer to the hw struct 3516 * @module_pointer: module pointer location in words from the NVM beginning 3517 * @offset: byte offset from the module beginning 3518 * @length: length of the section to be read (in bytes from the offset) 3519 * @data: command buffer (size [bytes] = length) 3520 * @last_command: tells if this is the last command in a series 3521 * @cmd_details: pointer to command details structure or NULL 3522 * 3523 * Read the NVM using the admin queue commands 3524 **/ 3525 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3526 u32 offset, u16 length, void *data, 3527 bool last_command, 3528 struct i40e_asq_cmd_details *cmd_details) 3529 { 3530 struct i40e_aq_desc desc; 3531 struct i40e_aqc_nvm_update *cmd = 3532 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3533 enum i40e_status_code status; 3534 3535 DEBUGFUNC("i40e_aq_read_nvm"); 3536 3537 /* In offset the highest byte must be zeroed. */ 3538 if (offset & 0xFF000000) { 3539 status = I40E_ERR_PARAM; 3540 goto i40e_aq_read_nvm_exit; 3541 } 3542 3543 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3544 3545 /* If this is the last command in a series, set the proper flag. */ 3546 if (last_command) 3547 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3548 cmd->module_pointer = module_pointer; 3549 cmd->offset = CPU_TO_LE32(offset); 3550 cmd->length = CPU_TO_LE16(length); 3551 3552 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3553 if (length > I40E_AQ_LARGE_BUF) 3554 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3555 3556 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3557 3558 i40e_aq_read_nvm_exit: 3559 return status; 3560 } 3561 3562 /** 3563 * i40e_aq_read_nvm_config - read an nvm config block 3564 * @hw: pointer to the hw struct 3565 * @cmd_flags: NVM access admin command bits 3566 * @field_id: field or feature id 3567 * @data: buffer for result 3568 * @buf_size: buffer size 3569 * @element_count: pointer to count of elements read by FW 3570 * @cmd_details: pointer to command details structure or NULL 3571 **/ 3572 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3573 u8 cmd_flags, u32 field_id, void *data, 3574 u16 buf_size, u16 *element_count, 3575 struct i40e_asq_cmd_details *cmd_details) 3576 { 3577 struct i40e_aq_desc desc; 3578 struct i40e_aqc_nvm_config_read *cmd = 3579 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3580 enum i40e_status_code status; 3581 3582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3583 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3584 if (buf_size > I40E_AQ_LARGE_BUF) 3585 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3586 3587 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3588 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3589 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3590 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3591 else 3592 cmd->element_id_msw = 0; 3593 3594 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3595 3596 if (!status && element_count) 3597 *element_count = LE16_TO_CPU(cmd->element_count); 3598 3599 return status; 3600 } 3601 3602 /** 3603 * i40e_aq_write_nvm_config - write an nvm config block 3604 * @hw: pointer to the hw struct 3605 * @cmd_flags: NVM access admin command bits 3606 * @data: buffer for result 3607 * @buf_size: buffer size 3608 * @element_count: count of elements to be written 3609 * @cmd_details: pointer to command details structure or NULL 3610 **/ 3611 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3612 u8 cmd_flags, void *data, u16 buf_size, 3613 u16 element_count, 3614 struct i40e_asq_cmd_details *cmd_details) 3615 { 3616 struct i40e_aq_desc desc; 3617 struct i40e_aqc_nvm_config_write *cmd = 3618 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3619 enum i40e_status_code status; 3620 3621 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3622 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3623 if (buf_size > I40E_AQ_LARGE_BUF) 3624 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3625 3626 cmd->element_count = CPU_TO_LE16(element_count); 3627 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3628 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3629 3630 return status; 3631 } 3632 3633 /** 3634 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3635 * @hw: pointer to the hw struct 3636 * @buff: buffer for result 3637 * @buff_size: buffer size 3638 * @cmd_details: pointer to command details structure or NULL 3639 **/ 3640 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3641 void *buff, u16 buff_size, 3642 struct i40e_asq_cmd_details *cmd_details) 3643 { 3644 struct i40e_aq_desc desc; 3645 enum i40e_status_code status; 3646 3647 UNREFERENCED_2PARAMETER(buff, buff_size); 3648 3649 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3650 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3651 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3652 status = I40E_ERR_NOT_IMPLEMENTED; 3653 3654 return status; 3655 } 3656 3657 /** 3658 * i40e_aq_erase_nvm 3659 * @hw: pointer to the hw struct 3660 * @module_pointer: module pointer location in words from the NVM beginning 3661 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3662 * @length: length of the section to be erased (expressed in 4 KB) 3663 * @last_command: tells if this is the last command in a series 3664 * @cmd_details: pointer to command details structure or NULL 3665 * 3666 * Erase the NVM sector using the admin queue commands 3667 **/ 3668 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3669 u32 offset, u16 length, bool last_command, 3670 struct i40e_asq_cmd_details *cmd_details) 3671 { 3672 struct i40e_aq_desc desc; 3673 struct i40e_aqc_nvm_update *cmd = 3674 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3675 enum i40e_status_code status; 3676 3677 DEBUGFUNC("i40e_aq_erase_nvm"); 3678 3679 /* In offset the highest byte must be zeroed. */ 3680 if (offset & 0xFF000000) { 3681 status = I40E_ERR_PARAM; 3682 goto i40e_aq_erase_nvm_exit; 3683 } 3684 3685 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3686 3687 /* If this is the last command in a series, set the proper flag. */ 3688 if (last_command) 3689 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3690 cmd->module_pointer = module_pointer; 3691 cmd->offset = CPU_TO_LE32(offset); 3692 cmd->length = CPU_TO_LE16(length); 3693 3694 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3695 3696 i40e_aq_erase_nvm_exit: 3697 return status; 3698 } 3699 3700 /** 3701 * i40e_parse_discover_capabilities 3702 * @hw: pointer to the hw struct 3703 * @buff: pointer to a buffer containing device/function capability records 3704 * @cap_count: number of capability records in the list 3705 * @list_type_opc: type of capabilities list to parse 3706 * 3707 * Parse the device/function capabilities list. 3708 **/ 3709 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3710 u32 cap_count, 3711 enum i40e_admin_queue_opc list_type_opc) 3712 { 3713 struct i40e_aqc_list_capabilities_element_resp *cap; 3714 u32 valid_functions, num_functions; 3715 u32 number, logical_id, phys_id; 3716 struct i40e_hw_capabilities *p; 3717 enum i40e_status_code status; 3718 u16 id, ocp_cfg_word0; 3719 u8 major_rev; 3720 u32 i = 0; 3721 3722 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3723 3724 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3725 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3726 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3727 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3728 else 3729 return; 3730 3731 for (i = 0; i < cap_count; i++, cap++) { 3732 id = LE16_TO_CPU(cap->id); 3733 number = LE32_TO_CPU(cap->number); 3734 logical_id = LE32_TO_CPU(cap->logical_id); 3735 phys_id = LE32_TO_CPU(cap->phys_id); 3736 major_rev = cap->major_rev; 3737 3738 switch (id) { 3739 case I40E_AQ_CAP_ID_SWITCH_MODE: 3740 p->switch_mode = number; 3741 i40e_debug(hw, I40E_DEBUG_INIT, 3742 "HW Capability: Switch mode = %d\n", 3743 p->switch_mode); 3744 break; 3745 case I40E_AQ_CAP_ID_MNG_MODE: 3746 p->management_mode = number; 3747 if (major_rev > 1) { 3748 p->mng_protocols_over_mctp = logical_id; 3749 i40e_debug(hw, I40E_DEBUG_INIT, 3750 "HW Capability: Protocols over MCTP = %d\n", 3751 p->mng_protocols_over_mctp); 3752 } else { 3753 p->mng_protocols_over_mctp = 0; 3754 } 3755 i40e_debug(hw, I40E_DEBUG_INIT, 3756 "HW Capability: Management Mode = %d\n", 3757 p->management_mode); 3758 break; 3759 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3760 p->npar_enable = number; 3761 i40e_debug(hw, I40E_DEBUG_INIT, 3762 "HW Capability: NPAR enable = %d\n", 3763 p->npar_enable); 3764 break; 3765 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3766 p->os2bmc = number; 3767 i40e_debug(hw, I40E_DEBUG_INIT, 3768 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3769 break; 3770 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3771 p->valid_functions = number; 3772 i40e_debug(hw, I40E_DEBUG_INIT, 3773 "HW Capability: Valid Functions = %d\n", 3774 p->valid_functions); 3775 break; 3776 case I40E_AQ_CAP_ID_SRIOV: 3777 if (number == 1) 3778 p->sr_iov_1_1 = true; 3779 i40e_debug(hw, I40E_DEBUG_INIT, 3780 "HW Capability: SR-IOV = %d\n", 3781 p->sr_iov_1_1); 3782 break; 3783 case I40E_AQ_CAP_ID_VF: 3784 p->num_vfs = number; 3785 p->vf_base_id = logical_id; 3786 i40e_debug(hw, I40E_DEBUG_INIT, 3787 "HW Capability: VF count = %d\n", 3788 p->num_vfs); 3789 i40e_debug(hw, I40E_DEBUG_INIT, 3790 "HW Capability: VF base_id = %d\n", 3791 p->vf_base_id); 3792 break; 3793 case I40E_AQ_CAP_ID_VMDQ: 3794 if (number == 1) 3795 p->vmdq = true; 3796 i40e_debug(hw, I40E_DEBUG_INIT, 3797 "HW Capability: VMDQ = %d\n", p->vmdq); 3798 break; 3799 case I40E_AQ_CAP_ID_8021QBG: 3800 if (number == 1) 3801 p->evb_802_1_qbg = true; 3802 i40e_debug(hw, I40E_DEBUG_INIT, 3803 "HW Capability: 802.1Qbg = %d\n", number); 3804 break; 3805 case I40E_AQ_CAP_ID_8021QBR: 3806 if (number == 1) 3807 p->evb_802_1_qbh = true; 3808 i40e_debug(hw, I40E_DEBUG_INIT, 3809 "HW Capability: 802.1Qbh = %d\n", number); 3810 break; 3811 case I40E_AQ_CAP_ID_VSI: 3812 p->num_vsis = number; 3813 i40e_debug(hw, I40E_DEBUG_INIT, 3814 "HW Capability: VSI count = %d\n", 3815 p->num_vsis); 3816 break; 3817 case I40E_AQ_CAP_ID_DCB: 3818 if (number == 1) { 3819 p->dcb = true; 3820 p->enabled_tcmap = logical_id; 3821 p->maxtc = phys_id; 3822 } 3823 i40e_debug(hw, I40E_DEBUG_INIT, 3824 "HW Capability: DCB = %d\n", p->dcb); 3825 i40e_debug(hw, I40E_DEBUG_INIT, 3826 "HW Capability: TC Mapping = %d\n", 3827 logical_id); 3828 i40e_debug(hw, I40E_DEBUG_INIT, 3829 "HW Capability: TC Max = %d\n", p->maxtc); 3830 break; 3831 case I40E_AQ_CAP_ID_FCOE: 3832 if (number == 1) 3833 p->fcoe = true; 3834 i40e_debug(hw, I40E_DEBUG_INIT, 3835 "HW Capability: FCOE = %d\n", p->fcoe); 3836 break; 3837 case I40E_AQ_CAP_ID_ISCSI: 3838 if (number == 1) 3839 p->iscsi = true; 3840 i40e_debug(hw, I40E_DEBUG_INIT, 3841 "HW Capability: iSCSI = %d\n", p->iscsi); 3842 break; 3843 case I40E_AQ_CAP_ID_RSS: 3844 p->rss = true; 3845 p->rss_table_size = number; 3846 p->rss_table_entry_width = logical_id; 3847 i40e_debug(hw, I40E_DEBUG_INIT, 3848 "HW Capability: RSS = %d\n", p->rss); 3849 i40e_debug(hw, I40E_DEBUG_INIT, 3850 "HW Capability: RSS table size = %d\n", 3851 p->rss_table_size); 3852 i40e_debug(hw, I40E_DEBUG_INIT, 3853 "HW Capability: RSS table width = %d\n", 3854 p->rss_table_entry_width); 3855 break; 3856 case I40E_AQ_CAP_ID_RXQ: 3857 p->num_rx_qp = number; 3858 p->base_queue = phys_id; 3859 i40e_debug(hw, I40E_DEBUG_INIT, 3860 "HW Capability: Rx QP = %d\n", number); 3861 i40e_debug(hw, I40E_DEBUG_INIT, 3862 "HW Capability: base_queue = %d\n", 3863 p->base_queue); 3864 break; 3865 case I40E_AQ_CAP_ID_TXQ: 3866 p->num_tx_qp = number; 3867 p->base_queue = phys_id; 3868 i40e_debug(hw, I40E_DEBUG_INIT, 3869 "HW Capability: Tx QP = %d\n", number); 3870 i40e_debug(hw, I40E_DEBUG_INIT, 3871 "HW Capability: base_queue = %d\n", 3872 p->base_queue); 3873 break; 3874 case I40E_AQ_CAP_ID_MSIX: 3875 p->num_msix_vectors = number; 3876 i40e_debug(hw, I40E_DEBUG_INIT, 3877 "HW Capability: MSIX vector count = %d\n", 3878 p->num_msix_vectors); 3879 break; 3880 case I40E_AQ_CAP_ID_VF_MSIX: 3881 p->num_msix_vectors_vf = number; 3882 i40e_debug(hw, I40E_DEBUG_INIT, 3883 "HW Capability: MSIX VF vector count = %d\n", 3884 p->num_msix_vectors_vf); 3885 break; 3886 case I40E_AQ_CAP_ID_FLEX10: 3887 if (major_rev == 1) { 3888 if (number == 1) { 3889 p->flex10_enable = true; 3890 p->flex10_capable = true; 3891 } 3892 } else { 3893 /* Capability revision >= 2 */ 3894 if (number & 1) 3895 p->flex10_enable = true; 3896 if (number & 2) 3897 p->flex10_capable = true; 3898 } 3899 p->flex10_mode = logical_id; 3900 p->flex10_status = phys_id; 3901 i40e_debug(hw, I40E_DEBUG_INIT, 3902 "HW Capability: Flex10 mode = %d\n", 3903 p->flex10_mode); 3904 i40e_debug(hw, I40E_DEBUG_INIT, 3905 "HW Capability: Flex10 status = %d\n", 3906 p->flex10_status); 3907 break; 3908 case I40E_AQ_CAP_ID_CEM: 3909 if (number == 1) 3910 p->mgmt_cem = true; 3911 i40e_debug(hw, I40E_DEBUG_INIT, 3912 "HW Capability: CEM = %d\n", p->mgmt_cem); 3913 break; 3914 case I40E_AQ_CAP_ID_IWARP: 3915 if (number == 1) 3916 p->iwarp = true; 3917 i40e_debug(hw, I40E_DEBUG_INIT, 3918 "HW Capability: iWARP = %d\n", p->iwarp); 3919 break; 3920 case I40E_AQ_CAP_ID_LED: 3921 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3922 p->led[phys_id] = true; 3923 i40e_debug(hw, I40E_DEBUG_INIT, 3924 "HW Capability: LED - PIN %d\n", phys_id); 3925 break; 3926 case I40E_AQ_CAP_ID_SDP: 3927 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3928 p->sdp[phys_id] = true; 3929 i40e_debug(hw, I40E_DEBUG_INIT, 3930 "HW Capability: SDP - PIN %d\n", phys_id); 3931 break; 3932 case I40E_AQ_CAP_ID_MDIO: 3933 if (number == 1) { 3934 p->mdio_port_num = phys_id; 3935 p->mdio_port_mode = logical_id; 3936 } 3937 i40e_debug(hw, I40E_DEBUG_INIT, 3938 "HW Capability: MDIO port number = %d\n", 3939 p->mdio_port_num); 3940 i40e_debug(hw, I40E_DEBUG_INIT, 3941 "HW Capability: MDIO port mode = %d\n", 3942 p->mdio_port_mode); 3943 break; 3944 case I40E_AQ_CAP_ID_1588: 3945 if (number == 1) 3946 p->ieee_1588 = true; 3947 i40e_debug(hw, I40E_DEBUG_INIT, 3948 "HW Capability: IEEE 1588 = %d\n", 3949 p->ieee_1588); 3950 break; 3951 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3952 p->fd = true; 3953 p->fd_filters_guaranteed = number; 3954 p->fd_filters_best_effort = logical_id; 3955 i40e_debug(hw, I40E_DEBUG_INIT, 3956 "HW Capability: Flow Director = 1\n"); 3957 i40e_debug(hw, I40E_DEBUG_INIT, 3958 "HW Capability: Guaranteed FD filters = %d\n", 3959 p->fd_filters_guaranteed); 3960 break; 3961 case I40E_AQ_CAP_ID_WSR_PROT: 3962 p->wr_csr_prot = (u64)number; 3963 p->wr_csr_prot |= (u64)logical_id << 32; 3964 i40e_debug(hw, I40E_DEBUG_INIT, 3965 "HW Capability: wr_csr_prot = 0x%llX\n\n", 3966 (p->wr_csr_prot & 0xffff)); 3967 break; 3968 case I40E_AQ_CAP_ID_NVM_MGMT: 3969 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3970 p->sec_rev_disabled = true; 3971 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3972 p->update_disabled = true; 3973 break; 3974 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 3975 hw->num_wol_proxy_filters = (u16)number; 3976 hw->wol_proxy_vsi_seid = (u16)logical_id; 3977 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 3978 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 3979 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 3980 else 3981 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 3982 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 3983 i40e_debug(hw, I40E_DEBUG_INIT, 3984 "HW Capability: WOL proxy filters = %d\n", 3985 hw->num_wol_proxy_filters); 3986 break; 3987 default: 3988 break; 3989 } 3990 } 3991 3992 if (p->fcoe) 3993 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3994 3995 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3996 p->fcoe = false; 3997 3998 /* count the enabled ports (aka the "not disabled" ports) */ 3999 hw->num_ports = 0; 4000 for (i = 0; i < 4; i++) { 4001 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 4002 u64 port_cfg = 0; 4003 4004 /* use AQ read to get the physical register offset instead 4005 * of the port relative offset 4006 */ 4007 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 4008 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 4009 hw->num_ports++; 4010 } 4011 4012 /* OCP cards case: if a mezz is removed the ethernet port is at 4013 * disabled state in PRTGEN_CNF register. Additional NVM read is 4014 * needed in order to check if we are dealing with OCP card. 4015 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 4016 * physical ports results in wrong partition id calculation and thus 4017 * not supporting WoL. 4018 */ 4019 if (hw->mac.type == I40E_MAC_X722) { 4020 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) { 4021 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 4022 2 * I40E_SR_OCP_CFG_WORD0, 4023 sizeof(ocp_cfg_word0), 4024 &ocp_cfg_word0, true, NULL); 4025 if (status == I40E_SUCCESS && 4026 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 4027 hw->num_ports = 4; 4028 i40e_release_nvm(hw); 4029 } 4030 } 4031 4032 valid_functions = p->valid_functions; 4033 num_functions = 0; 4034 while (valid_functions) { 4035 if (valid_functions & 1) 4036 num_functions++; 4037 valid_functions >>= 1; 4038 } 4039 4040 /* partition id is 1-based, and functions are evenly spread 4041 * across the ports as partitions 4042 */ 4043 if (hw->num_ports != 0) { 4044 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 4045 hw->num_partitions = num_functions / hw->num_ports; 4046 } 4047 4048 /* additional HW specific goodies that might 4049 * someday be HW version specific 4050 */ 4051 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 4052 } 4053 4054 /** 4055 * i40e_aq_discover_capabilities 4056 * @hw: pointer to the hw struct 4057 * @buff: a virtual buffer to hold the capabilities 4058 * @buff_size: Size of the virtual buffer 4059 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 4060 * @list_type_opc: capabilities type to discover - pass in the command opcode 4061 * @cmd_details: pointer to command details structure or NULL 4062 * 4063 * Get the device capabilities descriptions from the firmware 4064 **/ 4065 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 4066 void *buff, u16 buff_size, u16 *data_size, 4067 enum i40e_admin_queue_opc list_type_opc, 4068 struct i40e_asq_cmd_details *cmd_details) 4069 { 4070 struct i40e_aqc_list_capabilites *cmd; 4071 struct i40e_aq_desc desc; 4072 enum i40e_status_code status = I40E_SUCCESS; 4073 4074 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 4075 4076 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 4077 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 4078 status = I40E_ERR_PARAM; 4079 goto exit; 4080 } 4081 4082 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 4083 4084 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4085 if (buff_size > I40E_AQ_LARGE_BUF) 4086 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4087 4088 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4089 *data_size = LE16_TO_CPU(desc.datalen); 4090 4091 if (status) 4092 goto exit; 4093 4094 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 4095 list_type_opc); 4096 4097 exit: 4098 return status; 4099 } 4100 4101 /** 4102 * i40e_aq_update_nvm 4103 * @hw: pointer to the hw struct 4104 * @module_pointer: module pointer location in words from the NVM beginning 4105 * @offset: byte offset from the module beginning 4106 * @length: length of the section to be written (in bytes from the offset) 4107 * @data: command buffer (size [bytes] = length) 4108 * @last_command: tells if this is the last command in a series 4109 * @preservation_flags: Preservation mode flags 4110 * @cmd_details: pointer to command details structure or NULL 4111 * 4112 * Update the NVM using the admin queue commands 4113 **/ 4114 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 4115 u32 offset, u16 length, void *data, 4116 bool last_command, u8 preservation_flags, 4117 struct i40e_asq_cmd_details *cmd_details) 4118 { 4119 struct i40e_aq_desc desc; 4120 struct i40e_aqc_nvm_update *cmd = 4121 (struct i40e_aqc_nvm_update *)&desc.params.raw; 4122 enum i40e_status_code status; 4123 4124 DEBUGFUNC("i40e_aq_update_nvm"); 4125 4126 /* In offset the highest byte must be zeroed. */ 4127 if (offset & 0xFF000000) { 4128 status = I40E_ERR_PARAM; 4129 goto i40e_aq_update_nvm_exit; 4130 } 4131 4132 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4133 4134 /* If this is the last command in a series, set the proper flag. */ 4135 if (last_command) 4136 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 4137 if (hw->mac.type == I40E_MAC_X722) { 4138 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 4139 cmd->command_flags |= 4140 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 4141 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4142 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 4143 cmd->command_flags |= 4144 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 4145 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4146 } 4147 cmd->module_pointer = module_pointer; 4148 cmd->offset = CPU_TO_LE32(offset); 4149 cmd->length = CPU_TO_LE16(length); 4150 4151 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4152 if (length > I40E_AQ_LARGE_BUF) 4153 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4154 4155 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 4156 4157 i40e_aq_update_nvm_exit: 4158 return status; 4159 } 4160 4161 /** 4162 * i40e_aq_rearrange_nvm 4163 * @hw: pointer to the hw struct 4164 * @rearrange_nvm: defines direction of rearrangement 4165 * @cmd_details: pointer to command details structure or NULL 4166 * 4167 * Rearrange NVM structure, available only for transition FW 4168 **/ 4169 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw, 4170 u8 rearrange_nvm, 4171 struct i40e_asq_cmd_details *cmd_details) 4172 { 4173 struct i40e_aqc_nvm_update *cmd; 4174 enum i40e_status_code status; 4175 struct i40e_aq_desc desc; 4176 4177 DEBUGFUNC("i40e_aq_rearrange_nvm"); 4178 4179 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw; 4180 4181 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4182 4183 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT | 4184 I40E_AQ_NVM_REARRANGE_TO_STRUCT); 4185 4186 if (!rearrange_nvm) { 4187 status = I40E_ERR_PARAM; 4188 goto i40e_aq_rearrange_nvm_exit; 4189 } 4190 4191 cmd->command_flags |= rearrange_nvm; 4192 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4193 4194 i40e_aq_rearrange_nvm_exit: 4195 return status; 4196 } 4197 4198 /** 4199 * i40e_aq_nvm_progress 4200 * @hw: pointer to the hw struct 4201 * @progress: pointer to progress returned from AQ 4202 * @cmd_details: pointer to command details structure or NULL 4203 * 4204 * Gets progress of flash rearrangement process 4205 **/ 4206 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress, 4207 struct i40e_asq_cmd_details *cmd_details) 4208 { 4209 enum i40e_status_code status; 4210 struct i40e_aq_desc desc; 4211 4212 DEBUGFUNC("i40e_aq_nvm_progress"); 4213 4214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress); 4215 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4216 *progress = desc.params.raw[0]; 4217 return status; 4218 } 4219 4220 /** 4221 * i40e_aq_get_lldp_mib 4222 * @hw: pointer to the hw struct 4223 * @bridge_type: type of bridge requested 4224 * @mib_type: Local, Remote or both Local and Remote MIBs 4225 * @buff: pointer to a user supplied buffer to store the MIB block 4226 * @buff_size: size of the buffer (in bytes) 4227 * @local_len : length of the returned Local LLDP MIB 4228 * @remote_len: length of the returned Remote LLDP MIB 4229 * @cmd_details: pointer to command details structure or NULL 4230 * 4231 * Requests the complete LLDP MIB (entire packet). 4232 **/ 4233 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 4234 u8 mib_type, void *buff, u16 buff_size, 4235 u16 *local_len, u16 *remote_len, 4236 struct i40e_asq_cmd_details *cmd_details) 4237 { 4238 struct i40e_aq_desc desc; 4239 struct i40e_aqc_lldp_get_mib *cmd = 4240 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4241 struct i40e_aqc_lldp_get_mib *resp = 4242 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4243 enum i40e_status_code status; 4244 4245 if (buff_size == 0 || !buff) 4246 return I40E_ERR_PARAM; 4247 4248 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 4249 /* Indirect Command */ 4250 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4251 4252 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 4253 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4254 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4255 4256 desc.datalen = CPU_TO_LE16(buff_size); 4257 4258 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4259 if (buff_size > I40E_AQ_LARGE_BUF) 4260 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4261 4262 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4263 if (!status) { 4264 if (local_len != NULL) 4265 *local_len = LE16_TO_CPU(resp->local_len); 4266 if (remote_len != NULL) 4267 *remote_len = LE16_TO_CPU(resp->remote_len); 4268 } 4269 4270 return status; 4271 } 4272 4273 /** 4274 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4275 * @hw: pointer to the hw struct 4276 * @mib_type: Local, Remote or both Local and Remote MIBs 4277 * @buff: pointer to a user supplied buffer to store the MIB block 4278 * @buff_size: size of the buffer (in bytes) 4279 * @cmd_details: pointer to command details structure or NULL 4280 * 4281 * Set the LLDP MIB. 4282 **/ 4283 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4284 u8 mib_type, void *buff, u16 buff_size, 4285 struct i40e_asq_cmd_details *cmd_details) 4286 { 4287 struct i40e_aq_desc desc; 4288 struct i40e_aqc_lldp_set_local_mib *cmd = 4289 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4290 enum i40e_status_code status; 4291 4292 if (buff_size == 0 || !buff) 4293 return I40E_ERR_PARAM; 4294 4295 i40e_fill_default_direct_cmd_desc(&desc, 4296 i40e_aqc_opc_lldp_set_local_mib); 4297 /* Indirect Command */ 4298 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4299 if (buff_size > I40E_AQ_LARGE_BUF) 4300 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4301 desc.datalen = CPU_TO_LE16(buff_size); 4302 4303 cmd->type = mib_type; 4304 cmd->length = CPU_TO_LE16(buff_size); 4305 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff)); 4306 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff)); 4307 4308 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4309 return status; 4310 } 4311 4312 /** 4313 * i40e_aq_cfg_lldp_mib_change_event 4314 * @hw: pointer to the hw struct 4315 * @enable_update: Enable or Disable event posting 4316 * @cmd_details: pointer to command details structure or NULL 4317 * 4318 * Enable or Disable posting of an event on ARQ when LLDP MIB 4319 * associated with the interface changes 4320 **/ 4321 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4322 bool enable_update, 4323 struct i40e_asq_cmd_details *cmd_details) 4324 { 4325 struct i40e_aq_desc desc; 4326 struct i40e_aqc_lldp_update_mib *cmd = 4327 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4328 enum i40e_status_code status; 4329 4330 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4331 4332 if (!enable_update) 4333 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4334 4335 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4336 4337 return status; 4338 } 4339 4340 /** 4341 * i40e_aq_add_lldp_tlv 4342 * @hw: pointer to the hw struct 4343 * @bridge_type: type of bridge 4344 * @buff: buffer with TLV to add 4345 * @buff_size: length of the buffer 4346 * @tlv_len: length of the TLV to be added 4347 * @mib_len: length of the LLDP MIB returned in response 4348 * @cmd_details: pointer to command details structure or NULL 4349 * 4350 * Add the specified TLV to LLDP Local MIB for the given bridge type, 4351 * it is responsibility of the caller to make sure that the TLV is not 4352 * already present in the LLDPDU. 4353 * In return firmware will write the complete LLDP MIB with the newly 4354 * added TLV in the response buffer. 4355 **/ 4356 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 4357 void *buff, u16 buff_size, u16 tlv_len, 4358 u16 *mib_len, 4359 struct i40e_asq_cmd_details *cmd_details) 4360 { 4361 struct i40e_aq_desc desc; 4362 struct i40e_aqc_lldp_add_tlv *cmd = 4363 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4364 enum i40e_status_code status; 4365 4366 if (buff_size == 0 || !buff || tlv_len == 0) 4367 return I40E_ERR_PARAM; 4368 4369 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 4370 4371 /* Indirect Command */ 4372 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4373 if (buff_size > I40E_AQ_LARGE_BUF) 4374 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4375 desc.datalen = CPU_TO_LE16(buff_size); 4376 4377 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4378 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4379 cmd->len = CPU_TO_LE16(tlv_len); 4380 4381 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4382 if (!status) { 4383 if (mib_len != NULL) 4384 *mib_len = LE16_TO_CPU(desc.datalen); 4385 } 4386 4387 return status; 4388 } 4389 4390 /** 4391 * i40e_aq_update_lldp_tlv 4392 * @hw: pointer to the hw struct 4393 * @bridge_type: type of bridge 4394 * @buff: buffer with TLV to update 4395 * @buff_size: size of the buffer holding original and updated TLVs 4396 * @old_len: Length of the Original TLV 4397 * @new_len: Length of the Updated TLV 4398 * @offset: offset of the updated TLV in the buff 4399 * @mib_len: length of the returned LLDP MIB 4400 * @cmd_details: pointer to command details structure or NULL 4401 * 4402 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 4403 * Firmware will place the complete LLDP MIB in response buffer with the 4404 * updated TLV. 4405 **/ 4406 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 4407 u8 bridge_type, void *buff, u16 buff_size, 4408 u16 old_len, u16 new_len, u16 offset, 4409 u16 *mib_len, 4410 struct i40e_asq_cmd_details *cmd_details) 4411 { 4412 struct i40e_aq_desc desc; 4413 struct i40e_aqc_lldp_update_tlv *cmd = 4414 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 4415 enum i40e_status_code status; 4416 4417 if (buff_size == 0 || !buff || offset == 0 || 4418 old_len == 0 || new_len == 0) 4419 return I40E_ERR_PARAM; 4420 4421 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 4422 4423 /* Indirect Command */ 4424 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4425 if (buff_size > I40E_AQ_LARGE_BUF) 4426 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4427 desc.datalen = CPU_TO_LE16(buff_size); 4428 4429 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4430 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4431 cmd->old_len = CPU_TO_LE16(old_len); 4432 cmd->new_offset = CPU_TO_LE16(offset); 4433 cmd->new_len = CPU_TO_LE16(new_len); 4434 4435 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4436 if (!status) { 4437 if (mib_len != NULL) 4438 *mib_len = LE16_TO_CPU(desc.datalen); 4439 } 4440 4441 return status; 4442 } 4443 4444 /** 4445 * i40e_aq_delete_lldp_tlv 4446 * @hw: pointer to the hw struct 4447 * @bridge_type: type of bridge 4448 * @buff: pointer to a user supplied buffer that has the TLV 4449 * @buff_size: length of the buffer 4450 * @tlv_len: length of the TLV to be deleted 4451 * @mib_len: length of the returned LLDP MIB 4452 * @cmd_details: pointer to command details structure or NULL 4453 * 4454 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 4455 * The firmware places the entire LLDP MIB in the response buffer. 4456 **/ 4457 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 4458 u8 bridge_type, void *buff, u16 buff_size, 4459 u16 tlv_len, u16 *mib_len, 4460 struct i40e_asq_cmd_details *cmd_details) 4461 { 4462 struct i40e_aq_desc desc; 4463 struct i40e_aqc_lldp_add_tlv *cmd = 4464 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4465 enum i40e_status_code status; 4466 4467 if (buff_size == 0 || !buff) 4468 return I40E_ERR_PARAM; 4469 4470 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 4471 4472 /* Indirect Command */ 4473 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4474 if (buff_size > I40E_AQ_LARGE_BUF) 4475 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4476 desc.datalen = CPU_TO_LE16(buff_size); 4477 cmd->len = CPU_TO_LE16(tlv_len); 4478 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4479 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4480 4481 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4482 if (!status) { 4483 if (mib_len != NULL) 4484 *mib_len = LE16_TO_CPU(desc.datalen); 4485 } 4486 4487 return status; 4488 } 4489 4490 /** 4491 * i40e_aq_stop_lldp 4492 * @hw: pointer to the hw struct 4493 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4494 * @cmd_details: pointer to command details structure or NULL 4495 * 4496 * Stop or Shutdown the embedded LLDP Agent 4497 **/ 4498 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4499 struct i40e_asq_cmd_details *cmd_details) 4500 { 4501 struct i40e_aq_desc desc; 4502 struct i40e_aqc_lldp_stop *cmd = 4503 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4504 enum i40e_status_code status; 4505 4506 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4507 4508 if (shutdown_agent) 4509 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4510 4511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4512 4513 return status; 4514 } 4515 4516 /** 4517 * i40e_aq_start_lldp 4518 * @hw: pointer to the hw struct 4519 * @cmd_details: pointer to command details structure or NULL 4520 * 4521 * Start the embedded LLDP Agent on all ports. 4522 **/ 4523 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4524 struct i40e_asq_cmd_details *cmd_details) 4525 { 4526 struct i40e_aq_desc desc; 4527 struct i40e_aqc_lldp_start *cmd = 4528 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4529 enum i40e_status_code status; 4530 4531 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4532 4533 cmd->command = I40E_AQ_LLDP_AGENT_START; 4534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4535 4536 return status; 4537 } 4538 4539 /** 4540 * i40e_aq_set_dcb_parameters 4541 * @hw: pointer to the hw struct 4542 * @cmd_details: pointer to command details structure or NULL 4543 * @dcb_enable: True if DCB configuration needs to be applied 4544 * 4545 **/ 4546 enum i40e_status_code 4547 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 4548 struct i40e_asq_cmd_details *cmd_details) 4549 { 4550 struct i40e_aq_desc desc; 4551 struct i40e_aqc_set_dcb_parameters *cmd = 4552 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 4553 enum i40e_status_code status; 4554 4555 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) 4556 return I40E_ERR_DEVICE_NOT_SUPPORTED; 4557 4558 i40e_fill_default_direct_cmd_desc(&desc, 4559 i40e_aqc_opc_set_dcb_parameters); 4560 4561 if (dcb_enable) { 4562 cmd->valid_flags = I40E_DCB_VALID; 4563 cmd->command = I40E_AQ_DCB_SET_AGENT; 4564 } 4565 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4566 4567 return status; 4568 } 4569 4570 /** 4571 * i40e_aq_get_cee_dcb_config 4572 * @hw: pointer to the hw struct 4573 * @buff: response buffer that stores CEE operational configuration 4574 * @buff_size: size of the buffer passed 4575 * @cmd_details: pointer to command details structure or NULL 4576 * 4577 * Get CEE DCBX mode operational configuration from firmware 4578 **/ 4579 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4580 void *buff, u16 buff_size, 4581 struct i40e_asq_cmd_details *cmd_details) 4582 { 4583 struct i40e_aq_desc desc; 4584 enum i40e_status_code status; 4585 4586 if (buff_size == 0 || !buff) 4587 return I40E_ERR_PARAM; 4588 4589 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4590 4591 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4592 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4593 cmd_details); 4594 4595 return status; 4596 } 4597 4598 /** 4599 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4600 * @hw: pointer to the hw struct 4601 * @start_agent: True if DCBx Agent needs to be Started 4602 * False if DCBx Agent needs to be Stopped 4603 * @cmd_details: pointer to command details structure or NULL 4604 * 4605 * Start/Stop the embedded dcbx Agent 4606 **/ 4607 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4608 bool start_agent, 4609 struct i40e_asq_cmd_details *cmd_details) 4610 { 4611 struct i40e_aq_desc desc; 4612 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4613 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4614 &desc.params.raw; 4615 enum i40e_status_code status; 4616 4617 i40e_fill_default_direct_cmd_desc(&desc, 4618 i40e_aqc_opc_lldp_stop_start_spec_agent); 4619 4620 if (start_agent) 4621 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4622 4623 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4624 4625 return status; 4626 } 4627 4628 /** 4629 * i40e_aq_add_udp_tunnel 4630 * @hw: pointer to the hw struct 4631 * @udp_port: the UDP port to add in Host byte order 4632 * @protocol_index: protocol index type 4633 * @filter_index: pointer to filter index 4634 * @cmd_details: pointer to command details structure or NULL 4635 * 4636 * Note: Firmware expects the udp_port value to be in Little Endian format, 4637 * and this function will call CPU_TO_LE16 to convert from Host byte order to 4638 * Little Endian order. 4639 **/ 4640 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4641 u16 udp_port, u8 protocol_index, 4642 u8 *filter_index, 4643 struct i40e_asq_cmd_details *cmd_details) 4644 { 4645 struct i40e_aq_desc desc; 4646 struct i40e_aqc_add_udp_tunnel *cmd = 4647 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4648 struct i40e_aqc_del_udp_tunnel_completion *resp = 4649 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4650 enum i40e_status_code status; 4651 4652 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4653 4654 cmd->udp_port = CPU_TO_LE16(udp_port); 4655 cmd->protocol_type = protocol_index; 4656 4657 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4658 4659 if (!status && filter_index) 4660 *filter_index = resp->index; 4661 4662 return status; 4663 } 4664 4665 /** 4666 * i40e_aq_del_udp_tunnel 4667 * @hw: pointer to the hw struct 4668 * @index: filter index 4669 * @cmd_details: pointer to command details structure or NULL 4670 **/ 4671 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4672 struct i40e_asq_cmd_details *cmd_details) 4673 { 4674 struct i40e_aq_desc desc; 4675 struct i40e_aqc_remove_udp_tunnel *cmd = 4676 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4677 enum i40e_status_code status; 4678 4679 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4680 4681 cmd->index = index; 4682 4683 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4684 4685 return status; 4686 } 4687 4688 /** 4689 * i40e_aq_get_switch_resource_alloc (0x0204) 4690 * @hw: pointer to the hw struct 4691 * @num_entries: pointer to u8 to store the number of resource entries returned 4692 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4693 * to store the resource information for all resource types. Each 4694 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4695 * @count: size, in bytes, of the buffer provided 4696 * @cmd_details: pointer to command details structure or NULL 4697 * 4698 * Query the resources allocated to a function. 4699 **/ 4700 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4701 u8 *num_entries, 4702 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4703 u16 count, 4704 struct i40e_asq_cmd_details *cmd_details) 4705 { 4706 struct i40e_aq_desc desc; 4707 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4708 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4709 enum i40e_status_code status; 4710 u16 length = count * sizeof(*buf); 4711 4712 i40e_fill_default_direct_cmd_desc(&desc, 4713 i40e_aqc_opc_get_switch_resource_alloc); 4714 4715 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4716 if (length > I40E_AQ_LARGE_BUF) 4717 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4718 4719 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4720 4721 if (!status && num_entries) 4722 *num_entries = cmd_resp->num_entries; 4723 4724 return status; 4725 } 4726 4727 /** 4728 * i40e_aq_delete_element - Delete switch element 4729 * @hw: pointer to the hw struct 4730 * @seid: the SEID to delete from the switch 4731 * @cmd_details: pointer to command details structure or NULL 4732 * 4733 * This deletes a switch element from the switch. 4734 **/ 4735 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4736 struct i40e_asq_cmd_details *cmd_details) 4737 { 4738 struct i40e_aq_desc desc; 4739 struct i40e_aqc_switch_seid *cmd = 4740 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4741 enum i40e_status_code status; 4742 4743 if (seid == 0) 4744 return I40E_ERR_PARAM; 4745 4746 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4747 4748 cmd->seid = CPU_TO_LE16(seid); 4749 4750 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4751 4752 return status; 4753 } 4754 4755 /** 4756 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4757 * @hw: pointer to the hw struct 4758 * @flags: component flags 4759 * @mac_seid: uplink seid (MAC SEID) 4760 * @vsi_seid: connected vsi seid 4761 * @ret_seid: seid of create pv component 4762 * 4763 * This instantiates an i40e port virtualizer with specified flags. 4764 * Depending on specified flags the port virtualizer can act as a 4765 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4766 */ 4767 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4768 u16 mac_seid, u16 vsi_seid, 4769 u16 *ret_seid) 4770 { 4771 struct i40e_aq_desc desc; 4772 struct i40e_aqc_add_update_pv *cmd = 4773 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4774 struct i40e_aqc_add_update_pv_completion *resp = 4775 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4776 enum i40e_status_code status; 4777 4778 if (vsi_seid == 0) 4779 return I40E_ERR_PARAM; 4780 4781 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4782 cmd->command_flags = CPU_TO_LE16(flags); 4783 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4784 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4785 4786 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4787 if (!status && ret_seid) 4788 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4789 4790 return status; 4791 } 4792 4793 /** 4794 * i40e_aq_add_tag - Add an S/E-tag 4795 * @hw: pointer to the hw struct 4796 * @direct_to_queue: should s-tag direct flow to a specific queue 4797 * @vsi_seid: VSI SEID to use this tag 4798 * @tag: value of the tag 4799 * @queue_num: queue number, only valid is direct_to_queue is true 4800 * @tags_used: return value, number of tags in use by this PF 4801 * @tags_free: return value, number of unallocated tags 4802 * @cmd_details: pointer to command details structure or NULL 4803 * 4804 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4805 * the number of tags allocated by the PF, and the number of unallocated 4806 * tags available. 4807 **/ 4808 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4809 u16 vsi_seid, u16 tag, u16 queue_num, 4810 u16 *tags_used, u16 *tags_free, 4811 struct i40e_asq_cmd_details *cmd_details) 4812 { 4813 struct i40e_aq_desc desc; 4814 struct i40e_aqc_add_tag *cmd = 4815 (struct i40e_aqc_add_tag *)&desc.params.raw; 4816 struct i40e_aqc_add_remove_tag_completion *resp = 4817 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4818 enum i40e_status_code status; 4819 4820 if (vsi_seid == 0) 4821 return I40E_ERR_PARAM; 4822 4823 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4824 4825 cmd->seid = CPU_TO_LE16(vsi_seid); 4826 cmd->tag = CPU_TO_LE16(tag); 4827 if (direct_to_queue) { 4828 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4829 cmd->queue_number = CPU_TO_LE16(queue_num); 4830 } 4831 4832 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4833 4834 if (!status) { 4835 if (tags_used != NULL) 4836 *tags_used = LE16_TO_CPU(resp->tags_used); 4837 if (tags_free != NULL) 4838 *tags_free = LE16_TO_CPU(resp->tags_free); 4839 } 4840 4841 return status; 4842 } 4843 4844 /** 4845 * i40e_aq_remove_tag - Remove an S- or E-tag 4846 * @hw: pointer to the hw struct 4847 * @vsi_seid: VSI SEID this tag is associated with 4848 * @tag: value of the S-tag to delete 4849 * @tags_used: return value, number of tags in use by this PF 4850 * @tags_free: return value, number of unallocated tags 4851 * @cmd_details: pointer to command details structure or NULL 4852 * 4853 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4854 * the number of tags allocated by the PF, and the number of unallocated 4855 * tags available. 4856 **/ 4857 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4858 u16 tag, u16 *tags_used, u16 *tags_free, 4859 struct i40e_asq_cmd_details *cmd_details) 4860 { 4861 struct i40e_aq_desc desc; 4862 struct i40e_aqc_remove_tag *cmd = 4863 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4864 struct i40e_aqc_add_remove_tag_completion *resp = 4865 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4866 enum i40e_status_code status; 4867 4868 if (vsi_seid == 0) 4869 return I40E_ERR_PARAM; 4870 4871 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4872 4873 cmd->seid = CPU_TO_LE16(vsi_seid); 4874 cmd->tag = CPU_TO_LE16(tag); 4875 4876 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4877 4878 if (!status) { 4879 if (tags_used != NULL) 4880 *tags_used = LE16_TO_CPU(resp->tags_used); 4881 if (tags_free != NULL) 4882 *tags_free = LE16_TO_CPU(resp->tags_free); 4883 } 4884 4885 return status; 4886 } 4887 4888 /** 4889 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4890 * @hw: pointer to the hw struct 4891 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4892 * @etag: value of E-tag to add 4893 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4894 * @buf: address of indirect buffer 4895 * @tags_used: return value, number of E-tags in use by this port 4896 * @tags_free: return value, number of unallocated M-tags 4897 * @cmd_details: pointer to command details structure or NULL 4898 * 4899 * This associates a multicast E-tag to a port virtualizer. It will return 4900 * the number of tags allocated by the PF, and the number of unallocated 4901 * tags available. 4902 * 4903 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4904 * num_tags_in_buf long. 4905 **/ 4906 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4907 u16 etag, u8 num_tags_in_buf, void *buf, 4908 u16 *tags_used, u16 *tags_free, 4909 struct i40e_asq_cmd_details *cmd_details) 4910 { 4911 struct i40e_aq_desc desc; 4912 struct i40e_aqc_add_remove_mcast_etag *cmd = 4913 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4914 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4915 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4916 enum i40e_status_code status; 4917 u16 length = sizeof(u16) * num_tags_in_buf; 4918 4919 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4920 return I40E_ERR_PARAM; 4921 4922 i40e_fill_default_direct_cmd_desc(&desc, 4923 i40e_aqc_opc_add_multicast_etag); 4924 4925 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4926 cmd->etag = CPU_TO_LE16(etag); 4927 cmd->num_unicast_etags = num_tags_in_buf; 4928 4929 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4930 if (length > I40E_AQ_LARGE_BUF) 4931 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4932 4933 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4934 4935 if (!status) { 4936 if (tags_used != NULL) 4937 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4938 if (tags_free != NULL) 4939 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4940 } 4941 4942 return status; 4943 } 4944 4945 /** 4946 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4947 * @hw: pointer to the hw struct 4948 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4949 * @etag: value of the E-tag to remove 4950 * @tags_used: return value, number of tags in use by this port 4951 * @tags_free: return value, number of unallocated tags 4952 * @cmd_details: pointer to command details structure or NULL 4953 * 4954 * This deletes an E-tag from the port virtualizer. It will return 4955 * the number of tags allocated by the port, and the number of unallocated 4956 * tags available. 4957 **/ 4958 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4959 u16 etag, u16 *tags_used, u16 *tags_free, 4960 struct i40e_asq_cmd_details *cmd_details) 4961 { 4962 struct i40e_aq_desc desc; 4963 struct i40e_aqc_add_remove_mcast_etag *cmd = 4964 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4965 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4966 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4967 enum i40e_status_code status; 4968 4969 4970 if (pv_seid == 0) 4971 return I40E_ERR_PARAM; 4972 4973 i40e_fill_default_direct_cmd_desc(&desc, 4974 i40e_aqc_opc_remove_multicast_etag); 4975 4976 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4977 cmd->etag = CPU_TO_LE16(etag); 4978 4979 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4980 4981 if (!status) { 4982 if (tags_used != NULL) 4983 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4984 if (tags_free != NULL) 4985 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4986 } 4987 4988 return status; 4989 } 4990 4991 /** 4992 * i40e_aq_update_tag - Update an S/E-tag 4993 * @hw: pointer to the hw struct 4994 * @vsi_seid: VSI SEID using this S-tag 4995 * @old_tag: old tag value 4996 * @new_tag: new tag value 4997 * @tags_used: return value, number of tags in use by this PF 4998 * @tags_free: return value, number of unallocated tags 4999 * @cmd_details: pointer to command details structure or NULL 5000 * 5001 * This updates the value of the tag currently attached to this VSI 5002 * in the switch complex. It will return the number of tags allocated 5003 * by the PF, and the number of unallocated tags available. 5004 **/ 5005 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 5006 u16 old_tag, u16 new_tag, u16 *tags_used, 5007 u16 *tags_free, 5008 struct i40e_asq_cmd_details *cmd_details) 5009 { 5010 struct i40e_aq_desc desc; 5011 struct i40e_aqc_update_tag *cmd = 5012 (struct i40e_aqc_update_tag *)&desc.params.raw; 5013 struct i40e_aqc_update_tag_completion *resp = 5014 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 5015 enum i40e_status_code status; 5016 5017 if (vsi_seid == 0) 5018 return I40E_ERR_PARAM; 5019 5020 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 5021 5022 cmd->seid = CPU_TO_LE16(vsi_seid); 5023 cmd->old_tag = CPU_TO_LE16(old_tag); 5024 cmd->new_tag = CPU_TO_LE16(new_tag); 5025 5026 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5027 5028 if (!status) { 5029 if (tags_used != NULL) 5030 *tags_used = LE16_TO_CPU(resp->tags_used); 5031 if (tags_free != NULL) 5032 *tags_free = LE16_TO_CPU(resp->tags_free); 5033 } 5034 5035 return status; 5036 } 5037 5038 /** 5039 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 5040 * @hw: pointer to the hw struct 5041 * @tcmap: TC map for request/release any ignore PFC condition 5042 * @request: request or release ignore PFC condition 5043 * @tcmap_ret: return TCs for which PFC is currently ignored 5044 * @cmd_details: pointer to command details structure or NULL 5045 * 5046 * This sends out request/release to ignore PFC condition for a TC. 5047 * It will return the TCs for which PFC is currently ignored. 5048 **/ 5049 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 5050 bool request, u8 *tcmap_ret, 5051 struct i40e_asq_cmd_details *cmd_details) 5052 { 5053 struct i40e_aq_desc desc; 5054 struct i40e_aqc_pfc_ignore *cmd_resp = 5055 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 5056 enum i40e_status_code status; 5057 5058 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 5059 5060 if (request) 5061 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 5062 5063 cmd_resp->tc_bitmap = tcmap; 5064 5065 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5066 5067 if (!status) { 5068 if (tcmap_ret != NULL) 5069 *tcmap_ret = cmd_resp->tc_bitmap; 5070 } 5071 5072 return status; 5073 } 5074 5075 /** 5076 * i40e_aq_dcb_updated - DCB Updated Command 5077 * @hw: pointer to the hw struct 5078 * @cmd_details: pointer to command details structure or NULL 5079 * 5080 * When LLDP is handled in PF this command is used by the PF 5081 * to notify EMP that a DCB setting is modified. 5082 * When LLDP is handled in EMP this command is used by the PF 5083 * to notify EMP whenever one of the following parameters get 5084 * modified: 5085 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 5086 * - PCIRTT in PRTDCB_GENC.PCIRTT 5087 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 5088 * EMP will return when the shared RPB settings have been 5089 * recomputed and modified. The retval field in the descriptor 5090 * will be set to 0 when RPB is modified. 5091 **/ 5092 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 5093 struct i40e_asq_cmd_details *cmd_details) 5094 { 5095 struct i40e_aq_desc desc; 5096 enum i40e_status_code status; 5097 5098 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 5099 5100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5101 5102 return status; 5103 } 5104 5105 /** 5106 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 5107 * @hw: pointer to the hw struct 5108 * @seid: defines the SEID of the switch for which the stats are requested 5109 * @vlan_id: the VLAN ID for which the statistics are requested 5110 * @stat_index: index of the statistics counters block assigned to this VLAN 5111 * @cmd_details: pointer to command details structure or NULL 5112 * 5113 * XL710 supports 128 smonVlanStats counters.This command is used to 5114 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 5115 * switch. 5116 **/ 5117 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 5118 u16 vlan_id, u16 *stat_index, 5119 struct i40e_asq_cmd_details *cmd_details) 5120 { 5121 struct i40e_aq_desc desc; 5122 struct i40e_aqc_add_remove_statistics *cmd_resp = 5123 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5124 enum i40e_status_code status; 5125 5126 if ((seid == 0) || (stat_index == NULL)) 5127 return I40E_ERR_PARAM; 5128 5129 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 5130 5131 cmd_resp->seid = CPU_TO_LE16(seid); 5132 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 5133 5134 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5135 5136 if (!status && stat_index) 5137 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 5138 5139 return status; 5140 } 5141 5142 /** 5143 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 5144 * @hw: pointer to the hw struct 5145 * @seid: defines the SEID of the switch for which the stats are requested 5146 * @vlan_id: the VLAN ID for which the statistics are requested 5147 * @stat_index: index of the statistics counters block assigned to this VLAN 5148 * @cmd_details: pointer to command details structure or NULL 5149 * 5150 * XL710 supports 128 smonVlanStats counters.This command is used to 5151 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 5152 * switch. 5153 **/ 5154 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 5155 u16 vlan_id, u16 stat_index, 5156 struct i40e_asq_cmd_details *cmd_details) 5157 { 5158 struct i40e_aq_desc desc; 5159 struct i40e_aqc_add_remove_statistics *cmd = 5160 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5161 enum i40e_status_code status; 5162 5163 if (seid == 0) 5164 return I40E_ERR_PARAM; 5165 5166 i40e_fill_default_direct_cmd_desc(&desc, 5167 i40e_aqc_opc_remove_statistics); 5168 5169 cmd->seid = CPU_TO_LE16(seid); 5170 cmd->vlan = CPU_TO_LE16(vlan_id); 5171 cmd->stat_index = CPU_TO_LE16(stat_index); 5172 5173 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5174 5175 return status; 5176 } 5177 5178 /** 5179 * i40e_aq_set_port_parameters - set physical port parameters. 5180 * @hw: pointer to the hw struct 5181 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 5182 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 5183 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 5184 * @double_vlan: if set double VLAN is enabled 5185 * @cmd_details: pointer to command details structure or NULL 5186 **/ 5187 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 5188 u16 bad_frame_vsi, bool save_bad_pac, 5189 bool pad_short_pac, bool double_vlan, 5190 struct i40e_asq_cmd_details *cmd_details) 5191 { 5192 struct i40e_aqc_set_port_parameters *cmd; 5193 enum i40e_status_code status; 5194 struct i40e_aq_desc desc; 5195 u16 command_flags = 0; 5196 5197 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 5198 5199 i40e_fill_default_direct_cmd_desc(&desc, 5200 i40e_aqc_opc_set_port_parameters); 5201 5202 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 5203 if (save_bad_pac) 5204 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 5205 if (pad_short_pac) 5206 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 5207 if (double_vlan) 5208 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 5209 cmd->command_flags = CPU_TO_LE16(command_flags); 5210 5211 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5212 5213 return status; 5214 } 5215 5216 /** 5217 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 5218 * @hw: pointer to the hw struct 5219 * @seid: seid for the physical port/switching component/vsi 5220 * @buff: Indirect buffer to hold data parameters and response 5221 * @buff_size: Indirect buffer size 5222 * @opcode: Tx scheduler AQ command opcode 5223 * @cmd_details: pointer to command details structure or NULL 5224 * 5225 * Generic command handler for Tx scheduler AQ commands 5226 **/ 5227 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 5228 void *buff, u16 buff_size, 5229 enum i40e_admin_queue_opc opcode, 5230 struct i40e_asq_cmd_details *cmd_details) 5231 { 5232 struct i40e_aq_desc desc; 5233 struct i40e_aqc_tx_sched_ind *cmd = 5234 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 5235 enum i40e_status_code status; 5236 bool cmd_param_flag = false; 5237 5238 switch (opcode) { 5239 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 5240 case i40e_aqc_opc_configure_vsi_tc_bw: 5241 case i40e_aqc_opc_enable_switching_comp_ets: 5242 case i40e_aqc_opc_modify_switching_comp_ets: 5243 case i40e_aqc_opc_disable_switching_comp_ets: 5244 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 5245 case i40e_aqc_opc_configure_switching_comp_bw_config: 5246 cmd_param_flag = true; 5247 break; 5248 case i40e_aqc_opc_query_vsi_bw_config: 5249 case i40e_aqc_opc_query_vsi_ets_sla_config: 5250 case i40e_aqc_opc_query_switching_comp_ets_config: 5251 case i40e_aqc_opc_query_port_ets_config: 5252 case i40e_aqc_opc_query_switching_comp_bw_config: 5253 cmd_param_flag = false; 5254 break; 5255 default: 5256 return I40E_ERR_PARAM; 5257 } 5258 5259 i40e_fill_default_direct_cmd_desc(&desc, opcode); 5260 5261 /* Indirect command */ 5262 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5263 if (cmd_param_flag) 5264 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5265 if (buff_size > I40E_AQ_LARGE_BUF) 5266 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5267 5268 desc.datalen = CPU_TO_LE16(buff_size); 5269 5270 cmd->vsi_seid = CPU_TO_LE16(seid); 5271 5272 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5273 5274 return status; 5275 } 5276 5277 /** 5278 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 5279 * @hw: pointer to the hw struct 5280 * @seid: VSI seid 5281 * @credit: BW limit credits (0 = disabled) 5282 * @max_credit: Max BW limit credits 5283 * @cmd_details: pointer to command details structure or NULL 5284 **/ 5285 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 5286 u16 seid, u16 credit, u8 max_credit, 5287 struct i40e_asq_cmd_details *cmd_details) 5288 { 5289 struct i40e_aq_desc desc; 5290 struct i40e_aqc_configure_vsi_bw_limit *cmd = 5291 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 5292 enum i40e_status_code status; 5293 5294 i40e_fill_default_direct_cmd_desc(&desc, 5295 i40e_aqc_opc_configure_vsi_bw_limit); 5296 5297 cmd->vsi_seid = CPU_TO_LE16(seid); 5298 cmd->credit = CPU_TO_LE16(credit); 5299 cmd->max_credit = max_credit; 5300 5301 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5302 5303 return status; 5304 } 5305 5306 /** 5307 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5308 * @hw: pointer to the hw struct 5309 * @seid: switching component seid 5310 * @credit: BW limit credits (0 = disabled) 5311 * @max_bw: Max BW limit credits 5312 * @cmd_details: pointer to command details structure or NULL 5313 **/ 5314 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5315 u16 seid, u16 credit, u8 max_bw, 5316 struct i40e_asq_cmd_details *cmd_details) 5317 { 5318 struct i40e_aq_desc desc; 5319 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5320 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5321 enum i40e_status_code status; 5322 5323 i40e_fill_default_direct_cmd_desc(&desc, 5324 i40e_aqc_opc_configure_switching_comp_bw_limit); 5325 5326 cmd->seid = CPU_TO_LE16(seid); 5327 cmd->credit = CPU_TO_LE16(credit); 5328 cmd->max_bw = max_bw; 5329 5330 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5331 5332 return status; 5333 } 5334 5335 /** 5336 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5337 * @hw: pointer to the hw struct 5338 * @seid: VSI seid 5339 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5340 * @cmd_details: pointer to command details structure or NULL 5341 **/ 5342 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5343 u16 seid, 5344 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5345 struct i40e_asq_cmd_details *cmd_details) 5346 { 5347 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5348 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5349 cmd_details); 5350 } 5351 5352 /** 5353 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5354 * @hw: pointer to the hw struct 5355 * @seid: VSI seid 5356 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5357 * @cmd_details: pointer to command details structure or NULL 5358 **/ 5359 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5360 u16 seid, 5361 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5362 struct i40e_asq_cmd_details *cmd_details) 5363 { 5364 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5365 i40e_aqc_opc_configure_vsi_tc_bw, 5366 cmd_details); 5367 } 5368 5369 /** 5370 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 5371 * @hw: pointer to the hw struct 5372 * @seid: seid of the switching component connected to Physical Port 5373 * @ets_data: Buffer holding ETS parameters 5374 * @opcode: Tx scheduler AQ command opcode 5375 * @cmd_details: pointer to command details structure or NULL 5376 **/ 5377 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 5378 u16 seid, 5379 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 5380 enum i40e_admin_queue_opc opcode, 5381 struct i40e_asq_cmd_details *cmd_details) 5382 { 5383 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 5384 sizeof(*ets_data), opcode, cmd_details); 5385 } 5386 5387 /** 5388 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 5389 * @hw: pointer to the hw struct 5390 * @seid: seid of the switching component 5391 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 5392 * @cmd_details: pointer to command details structure or NULL 5393 **/ 5394 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 5395 u16 seid, 5396 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 5397 struct i40e_asq_cmd_details *cmd_details) 5398 { 5399 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5400 i40e_aqc_opc_configure_switching_comp_bw_config, 5401 cmd_details); 5402 } 5403 5404 /** 5405 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5406 * @hw: pointer to the hw struct 5407 * @seid: seid of the switching component 5408 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5409 * @cmd_details: pointer to command details structure or NULL 5410 **/ 5411 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5412 struct i40e_hw *hw, u16 seid, 5413 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5414 struct i40e_asq_cmd_details *cmd_details) 5415 { 5416 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5417 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5418 cmd_details); 5419 } 5420 5421 /** 5422 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5423 * @hw: pointer to the hw struct 5424 * @seid: seid of the VSI 5425 * @bw_data: Buffer to hold VSI BW configuration 5426 * @cmd_details: pointer to command details structure or NULL 5427 **/ 5428 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5429 u16 seid, 5430 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5431 struct i40e_asq_cmd_details *cmd_details) 5432 { 5433 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5434 i40e_aqc_opc_query_vsi_bw_config, 5435 cmd_details); 5436 } 5437 5438 /** 5439 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5440 * @hw: pointer to the hw struct 5441 * @seid: seid of the VSI 5442 * @bw_data: Buffer to hold VSI BW configuration per TC 5443 * @cmd_details: pointer to command details structure or NULL 5444 **/ 5445 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5446 u16 seid, 5447 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5448 struct i40e_asq_cmd_details *cmd_details) 5449 { 5450 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5451 i40e_aqc_opc_query_vsi_ets_sla_config, 5452 cmd_details); 5453 } 5454 5455 /** 5456 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5457 * @hw: pointer to the hw struct 5458 * @seid: seid of the switching component 5459 * @bw_data: Buffer to hold switching component's per TC BW config 5460 * @cmd_details: pointer to command details structure or NULL 5461 **/ 5462 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5463 u16 seid, 5464 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5465 struct i40e_asq_cmd_details *cmd_details) 5466 { 5467 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5468 i40e_aqc_opc_query_switching_comp_ets_config, 5469 cmd_details); 5470 } 5471 5472 /** 5473 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5474 * @hw: pointer to the hw struct 5475 * @seid: seid of the VSI or switching component connected to Physical Port 5476 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5477 * @cmd_details: pointer to command details structure or NULL 5478 **/ 5479 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5480 u16 seid, 5481 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5482 struct i40e_asq_cmd_details *cmd_details) 5483 { 5484 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5485 i40e_aqc_opc_query_port_ets_config, 5486 cmd_details); 5487 } 5488 5489 /** 5490 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5491 * @hw: pointer to the hw struct 5492 * @seid: seid of the switching component 5493 * @bw_data: Buffer to hold switching component's BW configuration 5494 * @cmd_details: pointer to command details structure or NULL 5495 **/ 5496 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5497 u16 seid, 5498 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5499 struct i40e_asq_cmd_details *cmd_details) 5500 { 5501 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5502 i40e_aqc_opc_query_switching_comp_bw_config, 5503 cmd_details); 5504 } 5505 5506 /** 5507 * i40e_validate_filter_settings 5508 * @hw: pointer to the hardware structure 5509 * @settings: Filter control settings 5510 * 5511 * Check and validate the filter control settings passed. 5512 * The function checks for the valid filter/context sizes being 5513 * passed for FCoE and PE. 5514 * 5515 * Returns I40E_SUCCESS if the values passed are valid and within 5516 * range else returns an error. 5517 **/ 5518 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5519 struct i40e_filter_control_settings *settings) 5520 { 5521 u32 fcoe_cntx_size, fcoe_filt_size; 5522 u32 pe_cntx_size, pe_filt_size; 5523 u32 fcoe_fmax; 5524 5525 u32 val; 5526 5527 /* Validate FCoE settings passed */ 5528 switch (settings->fcoe_filt_num) { 5529 case I40E_HASH_FILTER_SIZE_1K: 5530 case I40E_HASH_FILTER_SIZE_2K: 5531 case I40E_HASH_FILTER_SIZE_4K: 5532 case I40E_HASH_FILTER_SIZE_8K: 5533 case I40E_HASH_FILTER_SIZE_16K: 5534 case I40E_HASH_FILTER_SIZE_32K: 5535 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5536 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5537 break; 5538 default: 5539 return I40E_ERR_PARAM; 5540 } 5541 5542 switch (settings->fcoe_cntx_num) { 5543 case I40E_DMA_CNTX_SIZE_512: 5544 case I40E_DMA_CNTX_SIZE_1K: 5545 case I40E_DMA_CNTX_SIZE_2K: 5546 case I40E_DMA_CNTX_SIZE_4K: 5547 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5548 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5549 break; 5550 default: 5551 return I40E_ERR_PARAM; 5552 } 5553 5554 /* Validate PE settings passed */ 5555 switch (settings->pe_filt_num) { 5556 case I40E_HASH_FILTER_SIZE_1K: 5557 case I40E_HASH_FILTER_SIZE_2K: 5558 case I40E_HASH_FILTER_SIZE_4K: 5559 case I40E_HASH_FILTER_SIZE_8K: 5560 case I40E_HASH_FILTER_SIZE_16K: 5561 case I40E_HASH_FILTER_SIZE_32K: 5562 case I40E_HASH_FILTER_SIZE_64K: 5563 case I40E_HASH_FILTER_SIZE_128K: 5564 case I40E_HASH_FILTER_SIZE_256K: 5565 case I40E_HASH_FILTER_SIZE_512K: 5566 case I40E_HASH_FILTER_SIZE_1M: 5567 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5568 pe_filt_size <<= (u32)settings->pe_filt_num; 5569 break; 5570 default: 5571 return I40E_ERR_PARAM; 5572 } 5573 5574 switch (settings->pe_cntx_num) { 5575 case I40E_DMA_CNTX_SIZE_512: 5576 case I40E_DMA_CNTX_SIZE_1K: 5577 case I40E_DMA_CNTX_SIZE_2K: 5578 case I40E_DMA_CNTX_SIZE_4K: 5579 case I40E_DMA_CNTX_SIZE_8K: 5580 case I40E_DMA_CNTX_SIZE_16K: 5581 case I40E_DMA_CNTX_SIZE_32K: 5582 case I40E_DMA_CNTX_SIZE_64K: 5583 case I40E_DMA_CNTX_SIZE_128K: 5584 case I40E_DMA_CNTX_SIZE_256K: 5585 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5586 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5587 break; 5588 default: 5589 return I40E_ERR_PARAM; 5590 } 5591 5592 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5593 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5594 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5595 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5596 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5597 return I40E_ERR_INVALID_SIZE; 5598 5599 return I40E_SUCCESS; 5600 } 5601 5602 /** 5603 * i40e_set_filter_control 5604 * @hw: pointer to the hardware structure 5605 * @settings: Filter control settings 5606 * 5607 * Set the Queue Filters for PE/FCoE and enable filters required 5608 * for a single PF. It is expected that these settings are programmed 5609 * at the driver initialization time. 5610 **/ 5611 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5612 struct i40e_filter_control_settings *settings) 5613 { 5614 enum i40e_status_code ret = I40E_SUCCESS; 5615 u32 hash_lut_size = 0; 5616 u32 val; 5617 5618 if (!settings) 5619 return I40E_ERR_PARAM; 5620 5621 /* Validate the input settings */ 5622 ret = i40e_validate_filter_settings(hw, settings); 5623 if (ret) 5624 return ret; 5625 5626 /* Read the PF Queue Filter control register */ 5627 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5628 5629 /* Program required PE hash buckets for the PF */ 5630 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5631 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5632 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5633 /* Program required PE contexts for the PF */ 5634 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5635 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5636 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5637 5638 /* Program required FCoE hash buckets for the PF */ 5639 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5640 val |= ((u32)settings->fcoe_filt_num << 5641 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5642 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5643 /* Program required FCoE DDP contexts for the PF */ 5644 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5645 val |= ((u32)settings->fcoe_cntx_num << 5646 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5647 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5648 5649 /* Program Hash LUT size for the PF */ 5650 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5651 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5652 hash_lut_size = 1; 5653 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5654 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5655 5656 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5657 if (settings->enable_fdir) 5658 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5659 if (settings->enable_ethtype) 5660 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5661 if (settings->enable_macvlan) 5662 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5663 5664 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5665 5666 return I40E_SUCCESS; 5667 } 5668 5669 /** 5670 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5671 * @hw: pointer to the hw struct 5672 * @mac_addr: MAC address to use in the filter 5673 * @ethtype: Ethertype to use in the filter 5674 * @flags: Flags that needs to be applied to the filter 5675 * @vsi_seid: seid of the control VSI 5676 * @queue: VSI queue number to send the packet to 5677 * @is_add: Add control packet filter if True else remove 5678 * @stats: Structure to hold information on control filter counts 5679 * @cmd_details: pointer to command details structure or NULL 5680 * 5681 * This command will Add or Remove control packet filter for a control VSI. 5682 * In return it will update the total number of perfect filter count in 5683 * the stats member. 5684 **/ 5685 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5686 u8 *mac_addr, u16 ethtype, u16 flags, 5687 u16 vsi_seid, u16 queue, bool is_add, 5688 struct i40e_control_filter_stats *stats, 5689 struct i40e_asq_cmd_details *cmd_details) 5690 { 5691 struct i40e_aq_desc desc; 5692 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5693 (struct i40e_aqc_add_remove_control_packet_filter *) 5694 &desc.params.raw; 5695 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5696 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5697 &desc.params.raw; 5698 enum i40e_status_code status; 5699 5700 if (vsi_seid == 0) 5701 return I40E_ERR_PARAM; 5702 5703 if (is_add) { 5704 i40e_fill_default_direct_cmd_desc(&desc, 5705 i40e_aqc_opc_add_control_packet_filter); 5706 cmd->queue = CPU_TO_LE16(queue); 5707 } else { 5708 i40e_fill_default_direct_cmd_desc(&desc, 5709 i40e_aqc_opc_remove_control_packet_filter); 5710 } 5711 5712 if (mac_addr) 5713 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN, 5714 I40E_NONDMA_TO_NONDMA); 5715 5716 cmd->etype = CPU_TO_LE16(ethtype); 5717 cmd->flags = CPU_TO_LE16(flags); 5718 cmd->seid = CPU_TO_LE16(vsi_seid); 5719 5720 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5721 5722 if (!status && stats) { 5723 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5724 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5725 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5726 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5727 } 5728 5729 return status; 5730 } 5731 5732 /** 5733 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5734 * @hw: pointer to the hw struct 5735 * @seid: VSI seid to add ethertype filter from 5736 **/ 5737 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5738 u16 seid) 5739 { 5740 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5741 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5742 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5743 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5744 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5745 enum i40e_status_code status; 5746 5747 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5748 seid, 0, true, NULL, 5749 NULL); 5750 if (status) 5751 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5752 } 5753 5754 /** 5755 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5756 * @filters: list of cloud filters 5757 * @filter_count: length of list 5758 * 5759 * There's an issue in the device where the Geneve VNI layout needs 5760 * to be shifted 1 byte over from the VxLAN VNI 5761 **/ 5762 STATIC void i40e_fix_up_geneve_vni( 5763 struct i40e_aqc_cloud_filters_element_data *filters, 5764 u8 filter_count) 5765 { 5766 struct i40e_aqc_cloud_filters_element_data *f = filters; 5767 int i; 5768 5769 for (i = 0; i < filter_count; i++) { 5770 u16 tnl_type; 5771 u32 ti; 5772 5773 tnl_type = (LE16_TO_CPU(f[i].flags) & 5774 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5775 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5776 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5777 ti = LE32_TO_CPU(f[i].tenant_id); 5778 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5779 } 5780 } 5781 } 5782 5783 /** 5784 * i40e_aq_add_cloud_filters 5785 * @hw: pointer to the hardware structure 5786 * @seid: VSI seid to add cloud filters from 5787 * @filters: Buffer which contains the filters to be added 5788 * @filter_count: number of filters contained in the buffer 5789 * 5790 * Set the cloud filters for a given VSI. The contents of the 5791 * i40e_aqc_cloud_filters_element_data are filled 5792 * in by the caller of the function. 5793 * 5794 **/ 5795 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5796 u16 seid, 5797 struct i40e_aqc_cloud_filters_element_data *filters, 5798 u8 filter_count) 5799 { 5800 struct i40e_aq_desc desc; 5801 struct i40e_aqc_add_remove_cloud_filters *cmd = 5802 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5803 enum i40e_status_code status; 5804 u16 buff_len; 5805 5806 i40e_fill_default_direct_cmd_desc(&desc, 5807 i40e_aqc_opc_add_cloud_filters); 5808 5809 buff_len = filter_count * sizeof(*filters); 5810 desc.datalen = CPU_TO_LE16(buff_len); 5811 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5812 cmd->num_filters = filter_count; 5813 cmd->seid = CPU_TO_LE16(seid); 5814 5815 i40e_fix_up_geneve_vni(filters, filter_count); 5816 5817 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5818 5819 return status; 5820 } 5821 5822 /** 5823 * i40e_aq_add_cloud_filters_bb 5824 * @hw: pointer to the hardware structure 5825 * @seid: VSI seid to add cloud filters from 5826 * @filters: Buffer which contains the filters in big buffer to be added 5827 * @filter_count: number of filters contained in the buffer 5828 * 5829 * Set the cloud filters for a given VSI. The contents of the 5830 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5831 * the function. 5832 * 5833 **/ 5834 enum i40e_status_code 5835 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5836 struct i40e_aqc_cloud_filters_element_bb *filters, 5837 u8 filter_count) 5838 { 5839 struct i40e_aq_desc desc; 5840 struct i40e_aqc_add_remove_cloud_filters *cmd = 5841 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5842 enum i40e_status_code status; 5843 u16 buff_len; 5844 int i; 5845 5846 i40e_fill_default_direct_cmd_desc(&desc, 5847 i40e_aqc_opc_add_cloud_filters); 5848 5849 buff_len = filter_count * sizeof(*filters); 5850 desc.datalen = CPU_TO_LE16(buff_len); 5851 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5852 cmd->num_filters = filter_count; 5853 cmd->seid = CPU_TO_LE16(seid); 5854 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5855 5856 for (i = 0; i < filter_count; i++) { 5857 u16 tnl_type; 5858 u32 ti; 5859 5860 tnl_type = (LE16_TO_CPU(filters[i].element.flags) & 5861 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5862 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5863 5864 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5865 * one more byte further than normally used for Tenant ID in 5866 * other tunnel types. 5867 */ 5868 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5869 ti = LE32_TO_CPU(filters[i].element.tenant_id); 5870 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8); 5871 } 5872 } 5873 5874 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5875 5876 return status; 5877 } 5878 5879 /** 5880 * i40e_aq_rem_cloud_filters 5881 * @hw: pointer to the hardware structure 5882 * @seid: VSI seid to remove cloud filters from 5883 * @filters: Buffer which contains the filters to be removed 5884 * @filter_count: number of filters contained in the buffer 5885 * 5886 * Remove the cloud filters for a given VSI. The contents of the 5887 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5888 * of the function. 5889 * 5890 **/ 5891 enum i40e_status_code 5892 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5893 struct i40e_aqc_cloud_filters_element_data *filters, 5894 u8 filter_count) 5895 { 5896 struct i40e_aq_desc desc; 5897 struct i40e_aqc_add_remove_cloud_filters *cmd = 5898 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5899 enum i40e_status_code status; 5900 u16 buff_len; 5901 5902 i40e_fill_default_direct_cmd_desc(&desc, 5903 i40e_aqc_opc_remove_cloud_filters); 5904 5905 buff_len = filter_count * sizeof(*filters); 5906 desc.datalen = CPU_TO_LE16(buff_len); 5907 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5908 cmd->num_filters = filter_count; 5909 cmd->seid = CPU_TO_LE16(seid); 5910 5911 i40e_fix_up_geneve_vni(filters, filter_count); 5912 5913 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5914 5915 return status; 5916 } 5917 5918 /** 5919 * i40e_aq_rem_cloud_filters_bb 5920 * @hw: pointer to the hardware structure 5921 * @seid: VSI seid to remove cloud filters from 5922 * @filters: Buffer which contains the filters in big buffer to be removed 5923 * @filter_count: number of filters contained in the buffer 5924 * 5925 * Remove the big buffer cloud filters for a given VSI. The contents of the 5926 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5927 * function. 5928 * 5929 **/ 5930 enum i40e_status_code 5931 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5932 struct i40e_aqc_cloud_filters_element_bb *filters, 5933 u8 filter_count) 5934 { 5935 struct i40e_aq_desc desc; 5936 struct i40e_aqc_add_remove_cloud_filters *cmd = 5937 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5938 enum i40e_status_code status; 5939 u16 buff_len; 5940 int i; 5941 5942 i40e_fill_default_direct_cmd_desc(&desc, 5943 i40e_aqc_opc_remove_cloud_filters); 5944 5945 buff_len = filter_count * sizeof(*filters); 5946 desc.datalen = CPU_TO_LE16(buff_len); 5947 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5948 cmd->num_filters = filter_count; 5949 cmd->seid = CPU_TO_LE16(seid); 5950 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5951 5952 for (i = 0; i < filter_count; i++) { 5953 u16 tnl_type; 5954 u32 ti; 5955 5956 tnl_type = (LE16_TO_CPU(filters[i].element.flags) & 5957 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5958 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5959 5960 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5961 * one more byte further than normally used for Tenant ID in 5962 * other tunnel types. 5963 */ 5964 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5965 ti = LE32_TO_CPU(filters[i].element.tenant_id); 5966 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8); 5967 } 5968 } 5969 5970 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5971 5972 return status; 5973 } 5974 5975 /** 5976 * i40e_aq_replace_cloud_filters - Replace cloud filter command 5977 * @hw: pointer to the hw struct 5978 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct 5979 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct 5980 * 5981 **/ 5982 enum 5983 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw, 5984 struct i40e_aqc_replace_cloud_filters_cmd *filters, 5985 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf) 5986 { 5987 struct i40e_aq_desc desc; 5988 struct i40e_aqc_replace_cloud_filters_cmd *cmd = 5989 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw; 5990 enum i40e_status_code status = I40E_SUCCESS; 5991 int i = 0; 5992 5993 /* X722 doesn't support this command */ 5994 if (hw->mac.type == I40E_MAC_X722) 5995 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5996 5997 /* need FW version greater than 6.00 */ 5998 if (hw->aq.fw_maj_ver < 6) 5999 return I40E_NOT_SUPPORTED; 6000 6001 i40e_fill_default_direct_cmd_desc(&desc, 6002 i40e_aqc_opc_replace_cloud_filters); 6003 6004 desc.datalen = CPU_TO_LE16(32); 6005 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 6006 cmd->old_filter_type = filters->old_filter_type; 6007 cmd->new_filter_type = filters->new_filter_type; 6008 cmd->valid_flags = filters->valid_flags; 6009 cmd->tr_bit = filters->tr_bit; 6010 cmd->tr_bit2 = filters->tr_bit2; 6011 6012 status = i40e_asq_send_command(hw, &desc, cmd_buf, 6013 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL); 6014 6015 /* for get cloud filters command */ 6016 for (i = 0; i < 32; i += 4) { 6017 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i]; 6018 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1]; 6019 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2]; 6020 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3]; 6021 } 6022 6023 return status; 6024 } 6025 6026 6027 /** 6028 * i40e_aq_alternate_write 6029 * @hw: pointer to the hardware structure 6030 * @reg_addr0: address of first dword to be read 6031 * @reg_val0: value to be written under 'reg_addr0' 6032 * @reg_addr1: address of second dword to be read 6033 * @reg_val1: value to be written under 'reg_addr1' 6034 * 6035 * Write one or two dwords to alternate structure. Fields are indicated 6036 * by 'reg_addr0' and 'reg_addr1' register numbers. 6037 * 6038 **/ 6039 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 6040 u32 reg_addr0, u32 reg_val0, 6041 u32 reg_addr1, u32 reg_val1) 6042 { 6043 struct i40e_aq_desc desc; 6044 struct i40e_aqc_alternate_write *cmd_resp = 6045 (struct i40e_aqc_alternate_write *)&desc.params.raw; 6046 enum i40e_status_code status; 6047 6048 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 6049 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 6050 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 6051 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 6052 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 6053 6054 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6055 6056 return status; 6057 } 6058 6059 /** 6060 * i40e_aq_alternate_write_indirect 6061 * @hw: pointer to the hardware structure 6062 * @addr: address of a first register to be modified 6063 * @dw_count: number of alternate structure fields to write 6064 * @buffer: pointer to the command buffer 6065 * 6066 * Write 'dw_count' dwords from 'buffer' to alternate structure 6067 * starting at 'addr'. 6068 * 6069 **/ 6070 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 6071 u32 addr, u32 dw_count, void *buffer) 6072 { 6073 struct i40e_aq_desc desc; 6074 struct i40e_aqc_alternate_ind_write *cmd_resp = 6075 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 6076 enum i40e_status_code status; 6077 6078 if (buffer == NULL) 6079 return I40E_ERR_PARAM; 6080 6081 /* Indirect command */ 6082 i40e_fill_default_direct_cmd_desc(&desc, 6083 i40e_aqc_opc_alternate_write_indirect); 6084 6085 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 6086 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 6087 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 6088 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6089 6090 cmd_resp->address = CPU_TO_LE32(addr); 6091 cmd_resp->length = CPU_TO_LE32(dw_count); 6092 6093 status = i40e_asq_send_command(hw, &desc, buffer, 6094 I40E_LO_DWORD(4*dw_count), NULL); 6095 6096 return status; 6097 } 6098 6099 /** 6100 * i40e_aq_alternate_read 6101 * @hw: pointer to the hardware structure 6102 * @reg_addr0: address of first dword to be read 6103 * @reg_val0: pointer for data read from 'reg_addr0' 6104 * @reg_addr1: address of second dword to be read 6105 * @reg_val1: pointer for data read from 'reg_addr1' 6106 * 6107 * Read one or two dwords from alternate structure. Fields are indicated 6108 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 6109 * is not passed then only register at 'reg_addr0' is read. 6110 * 6111 **/ 6112 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 6113 u32 reg_addr0, u32 *reg_val0, 6114 u32 reg_addr1, u32 *reg_val1) 6115 { 6116 struct i40e_aq_desc desc; 6117 struct i40e_aqc_alternate_write *cmd_resp = 6118 (struct i40e_aqc_alternate_write *)&desc.params.raw; 6119 enum i40e_status_code status; 6120 6121 if (reg_val0 == NULL) 6122 return I40E_ERR_PARAM; 6123 6124 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 6125 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 6126 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 6127 6128 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6129 6130 if (status == I40E_SUCCESS) { 6131 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 6132 6133 if (reg_val1 != NULL) 6134 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 6135 } 6136 6137 return status; 6138 } 6139 6140 /** 6141 * i40e_aq_alternate_read_indirect 6142 * @hw: pointer to the hardware structure 6143 * @addr: address of the alternate structure field 6144 * @dw_count: number of alternate structure fields to read 6145 * @buffer: pointer to the command buffer 6146 * 6147 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 6148 * place them in 'buffer'. The buffer should be allocated by caller. 6149 * 6150 **/ 6151 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 6152 u32 addr, u32 dw_count, void *buffer) 6153 { 6154 struct i40e_aq_desc desc; 6155 struct i40e_aqc_alternate_ind_write *cmd_resp = 6156 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 6157 enum i40e_status_code status; 6158 6159 if (buffer == NULL) 6160 return I40E_ERR_PARAM; 6161 6162 /* Indirect command */ 6163 i40e_fill_default_direct_cmd_desc(&desc, 6164 i40e_aqc_opc_alternate_read_indirect); 6165 6166 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 6167 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 6168 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 6169 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6170 6171 cmd_resp->address = CPU_TO_LE32(addr); 6172 cmd_resp->length = CPU_TO_LE32(dw_count); 6173 6174 status = i40e_asq_send_command(hw, &desc, buffer, 6175 I40E_LO_DWORD(4*dw_count), NULL); 6176 6177 return status; 6178 } 6179 6180 /** 6181 * i40e_aq_alternate_clear 6182 * @hw: pointer to the HW structure. 6183 * 6184 * Clear the alternate structures of the port from which the function 6185 * is called. 6186 * 6187 **/ 6188 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 6189 { 6190 struct i40e_aq_desc desc; 6191 enum i40e_status_code status; 6192 6193 i40e_fill_default_direct_cmd_desc(&desc, 6194 i40e_aqc_opc_alternate_clear_port); 6195 6196 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6197 6198 return status; 6199 } 6200 6201 /** 6202 * i40e_aq_alternate_write_done 6203 * @hw: pointer to the HW structure. 6204 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 6205 * @reset_needed: indicates the SW should trigger GLOBAL reset 6206 * 6207 * Indicates to the FW that alternate structures have been changed. 6208 * 6209 **/ 6210 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 6211 u8 bios_mode, bool *reset_needed) 6212 { 6213 struct i40e_aq_desc desc; 6214 struct i40e_aqc_alternate_write_done *cmd = 6215 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 6216 enum i40e_status_code status; 6217 6218 if (reset_needed == NULL) 6219 return I40E_ERR_PARAM; 6220 6221 i40e_fill_default_direct_cmd_desc(&desc, 6222 i40e_aqc_opc_alternate_write_done); 6223 6224 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 6225 6226 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6227 if (!status && reset_needed) 6228 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 6229 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 6230 6231 return status; 6232 } 6233 6234 /** 6235 * i40e_aq_set_oem_mode 6236 * @hw: pointer to the HW structure. 6237 * @oem_mode: the OEM mode to be used 6238 * 6239 * Sets the device to a specific operating mode. Currently the only supported 6240 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 6241 * 6242 **/ 6243 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 6244 u8 oem_mode) 6245 { 6246 struct i40e_aq_desc desc; 6247 struct i40e_aqc_alternate_write_done *cmd = 6248 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 6249 enum i40e_status_code status; 6250 6251 i40e_fill_default_direct_cmd_desc(&desc, 6252 i40e_aqc_opc_alternate_set_mode); 6253 6254 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 6255 6256 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6257 6258 return status; 6259 } 6260 6261 /** 6262 * i40e_aq_resume_port_tx 6263 * @hw: pointer to the hardware structure 6264 * @cmd_details: pointer to command details structure or NULL 6265 * 6266 * Resume port's Tx traffic 6267 **/ 6268 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 6269 struct i40e_asq_cmd_details *cmd_details) 6270 { 6271 struct i40e_aq_desc desc; 6272 enum i40e_status_code status; 6273 6274 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 6275 6276 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6277 6278 return status; 6279 } 6280 6281 /** 6282 * i40e_set_pci_config_data - store PCI bus info 6283 * @hw: pointer to hardware structure 6284 * @link_status: the link status word from PCI config space 6285 * 6286 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 6287 **/ 6288 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 6289 { 6290 hw->bus.type = i40e_bus_type_pci_express; 6291 6292 switch (link_status & I40E_PCI_LINK_WIDTH) { 6293 case I40E_PCI_LINK_WIDTH_1: 6294 hw->bus.width = i40e_bus_width_pcie_x1; 6295 break; 6296 case I40E_PCI_LINK_WIDTH_2: 6297 hw->bus.width = i40e_bus_width_pcie_x2; 6298 break; 6299 case I40E_PCI_LINK_WIDTH_4: 6300 hw->bus.width = i40e_bus_width_pcie_x4; 6301 break; 6302 case I40E_PCI_LINK_WIDTH_8: 6303 hw->bus.width = i40e_bus_width_pcie_x8; 6304 break; 6305 default: 6306 hw->bus.width = i40e_bus_width_unknown; 6307 break; 6308 } 6309 6310 switch (link_status & I40E_PCI_LINK_SPEED) { 6311 case I40E_PCI_LINK_SPEED_2500: 6312 hw->bus.speed = i40e_bus_speed_2500; 6313 break; 6314 case I40E_PCI_LINK_SPEED_5000: 6315 hw->bus.speed = i40e_bus_speed_5000; 6316 break; 6317 case I40E_PCI_LINK_SPEED_8000: 6318 hw->bus.speed = i40e_bus_speed_8000; 6319 break; 6320 default: 6321 hw->bus.speed = i40e_bus_speed_unknown; 6322 break; 6323 } 6324 } 6325 6326 /** 6327 * i40e_aq_debug_dump 6328 * @hw: pointer to the hardware structure 6329 * @cluster_id: specific cluster to dump 6330 * @table_id: table id within cluster 6331 * @start_index: index of line in the block to read 6332 * @buff_size: dump buffer size 6333 * @buff: dump buffer 6334 * @ret_buff_size: actual buffer size returned 6335 * @ret_next_table: next block to read 6336 * @ret_next_index: next index to read 6337 * @cmd_details: pointer to command details structure or NULL 6338 * 6339 * Dump internal FW/HW data for debug purposes. 6340 * 6341 **/ 6342 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 6343 u8 table_id, u32 start_index, u16 buff_size, 6344 void *buff, u16 *ret_buff_size, 6345 u8 *ret_next_table, u32 *ret_next_index, 6346 struct i40e_asq_cmd_details *cmd_details) 6347 { 6348 struct i40e_aq_desc desc; 6349 struct i40e_aqc_debug_dump_internals *cmd = 6350 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6351 struct i40e_aqc_debug_dump_internals *resp = 6352 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6353 enum i40e_status_code status; 6354 6355 if (buff_size == 0 || !buff) 6356 return I40E_ERR_PARAM; 6357 6358 i40e_fill_default_direct_cmd_desc(&desc, 6359 i40e_aqc_opc_debug_dump_internals); 6360 /* Indirect Command */ 6361 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6362 if (buff_size > I40E_AQ_LARGE_BUF) 6363 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6364 6365 cmd->cluster_id = cluster_id; 6366 cmd->table_id = table_id; 6367 cmd->idx = CPU_TO_LE32(start_index); 6368 6369 desc.datalen = CPU_TO_LE16(buff_size); 6370 6371 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 6372 if (!status) { 6373 if (ret_buff_size != NULL) 6374 *ret_buff_size = LE16_TO_CPU(desc.datalen); 6375 if (ret_next_table != NULL) 6376 *ret_next_table = resp->table_id; 6377 if (ret_next_index != NULL) 6378 *ret_next_index = LE32_TO_CPU(resp->idx); 6379 } 6380 6381 return status; 6382 } 6383 6384 /** 6385 * i40e_read_bw_from_alt_ram 6386 * @hw: pointer to the hardware structure 6387 * @max_bw: pointer for max_bw read 6388 * @min_bw: pointer for min_bw read 6389 * @min_valid: pointer for bool that is true if min_bw is a valid value 6390 * @max_valid: pointer for bool that is true if max_bw is a valid value 6391 * 6392 * Read bw from the alternate ram for the given pf 6393 **/ 6394 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 6395 u32 *max_bw, u32 *min_bw, 6396 bool *min_valid, bool *max_valid) 6397 { 6398 enum i40e_status_code status; 6399 u32 max_bw_addr, min_bw_addr; 6400 6401 /* Calculate the address of the min/max bw registers */ 6402 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6403 I40E_ALT_STRUCT_MAX_BW_OFFSET + 6404 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6405 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6406 I40E_ALT_STRUCT_MIN_BW_OFFSET + 6407 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6408 6409 /* Read the bandwidths from alt ram */ 6410 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 6411 min_bw_addr, min_bw); 6412 6413 if (*min_bw & I40E_ALT_BW_VALID_MASK) 6414 *min_valid = true; 6415 else 6416 *min_valid = false; 6417 6418 if (*max_bw & I40E_ALT_BW_VALID_MASK) 6419 *max_valid = true; 6420 else 6421 *max_valid = false; 6422 6423 return status; 6424 } 6425 6426 /** 6427 * i40e_aq_configure_partition_bw 6428 * @hw: pointer to the hardware structure 6429 * @bw_data: Buffer holding valid pfs and bw limits 6430 * @cmd_details: pointer to command details 6431 * 6432 * Configure partitions guaranteed/max bw 6433 **/ 6434 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 6435 struct i40e_aqc_configure_partition_bw_data *bw_data, 6436 struct i40e_asq_cmd_details *cmd_details) 6437 { 6438 enum i40e_status_code status; 6439 struct i40e_aq_desc desc; 6440 u16 bwd_size = sizeof(*bw_data); 6441 6442 i40e_fill_default_direct_cmd_desc(&desc, 6443 i40e_aqc_opc_configure_partition_bw); 6444 6445 /* Indirect command */ 6446 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6447 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6448 6449 desc.datalen = CPU_TO_LE16(bwd_size); 6450 6451 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 6452 6453 return status; 6454 } 6455 6456 /** 6457 * i40e_read_phy_register_clause22 6458 * @hw: pointer to the HW structure 6459 * @reg: register address in the page 6460 * @phy_addr: PHY address on MDIO interface 6461 * @value: PHY register value 6462 * 6463 * Reads specified PHY register value 6464 **/ 6465 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 6466 u16 reg, u8 phy_addr, u16 *value) 6467 { 6468 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6469 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6470 u32 command = 0; 6471 u16 retry = 1000; 6472 6473 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6474 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6475 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 6476 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6477 (I40E_GLGEN_MSCA_MDICMD_MASK); 6478 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6479 do { 6480 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6481 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6482 status = I40E_SUCCESS; 6483 break; 6484 } 6485 i40e_usec_delay(10); 6486 retry--; 6487 } while (retry); 6488 6489 if (status) { 6490 i40e_debug(hw, I40E_DEBUG_PHY, 6491 "PHY: Can't write command to external PHY.\n"); 6492 } else { 6493 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6494 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6495 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6496 } 6497 6498 return status; 6499 } 6500 6501 /** 6502 * i40e_write_phy_register_clause22 6503 * @hw: pointer to the HW structure 6504 * @reg: register address in the page 6505 * @phy_addr: PHY address on MDIO interface 6506 * @value: PHY register value 6507 * 6508 * Writes specified PHY register value 6509 **/ 6510 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6511 u16 reg, u8 phy_addr, u16 value) 6512 { 6513 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6514 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6515 u32 command = 0; 6516 u16 retry = 1000; 6517 6518 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6519 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6520 6521 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6522 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6523 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6524 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6525 (I40E_GLGEN_MSCA_MDICMD_MASK); 6526 6527 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6528 do { 6529 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6530 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6531 status = I40E_SUCCESS; 6532 break; 6533 } 6534 i40e_usec_delay(10); 6535 retry--; 6536 } while (retry); 6537 6538 return status; 6539 } 6540 6541 /** 6542 * i40e_read_phy_register_clause45 6543 * @hw: pointer to the HW structure 6544 * @page: registers page number 6545 * @reg: register address in the page 6546 * @phy_addr: PHY address on MDIO interface 6547 * @value: PHY register value 6548 * 6549 * Reads specified PHY register value 6550 **/ 6551 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6552 u8 page, u16 reg, u8 phy_addr, u16 *value) 6553 { 6554 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6555 u32 command = 0; 6556 u16 retry = 1000; 6557 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6558 6559 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6560 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6561 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6562 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6563 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6564 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6565 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6566 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6567 do { 6568 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6569 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6570 status = I40E_SUCCESS; 6571 break; 6572 } 6573 i40e_usec_delay(10); 6574 retry--; 6575 } while (retry); 6576 6577 if (status) { 6578 i40e_debug(hw, I40E_DEBUG_PHY, 6579 "PHY: Can't write command to external PHY.\n"); 6580 goto phy_read_end; 6581 } 6582 6583 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6584 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6585 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6586 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6587 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6588 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6589 status = I40E_ERR_TIMEOUT; 6590 retry = 1000; 6591 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6592 do { 6593 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6594 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6595 status = I40E_SUCCESS; 6596 break; 6597 } 6598 i40e_usec_delay(10); 6599 retry--; 6600 } while (retry); 6601 6602 if (!status) { 6603 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6604 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6605 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6606 } else { 6607 i40e_debug(hw, I40E_DEBUG_PHY, 6608 "PHY: Can't read register value from external PHY.\n"); 6609 } 6610 6611 phy_read_end: 6612 return status; 6613 } 6614 6615 /** 6616 * i40e_write_phy_register_clause45 6617 * @hw: pointer to the HW structure 6618 * @page: registers page number 6619 * @reg: register address in the page 6620 * @phy_addr: PHY address on MDIO interface 6621 * @value: PHY register value 6622 * 6623 * Writes value to specified PHY register 6624 **/ 6625 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6626 u8 page, u16 reg, u8 phy_addr, u16 value) 6627 { 6628 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6629 u32 command = 0; 6630 u16 retry = 1000; 6631 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6632 6633 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6634 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6635 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6636 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6637 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6638 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6639 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6640 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6641 do { 6642 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6643 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6644 status = I40E_SUCCESS; 6645 break; 6646 } 6647 i40e_usec_delay(10); 6648 retry--; 6649 } while (retry); 6650 if (status) { 6651 i40e_debug(hw, I40E_DEBUG_PHY, 6652 "PHY: Can't write command to external PHY.\n"); 6653 goto phy_write_end; 6654 } 6655 6656 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6657 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6658 6659 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6660 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6661 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6662 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6663 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6664 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6665 status = I40E_ERR_TIMEOUT; 6666 retry = 1000; 6667 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6668 do { 6669 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6670 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6671 status = I40E_SUCCESS; 6672 break; 6673 } 6674 i40e_usec_delay(10); 6675 retry--; 6676 } while (retry); 6677 6678 phy_write_end: 6679 return status; 6680 } 6681 6682 /** 6683 * i40e_write_phy_register 6684 * @hw: pointer to the HW structure 6685 * @page: registers page number 6686 * @reg: register address in the page 6687 * @phy_addr: PHY address on MDIO interface 6688 * @value: PHY register value 6689 * 6690 * Writes value to specified PHY register 6691 **/ 6692 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6693 u8 page, u16 reg, u8 phy_addr, u16 value) 6694 { 6695 enum i40e_status_code status; 6696 6697 switch (hw->device_id) { 6698 case I40E_DEV_ID_1G_BASE_T_X722: 6699 status = i40e_write_phy_register_clause22(hw, 6700 reg, phy_addr, value); 6701 break; 6702 case I40E_DEV_ID_10G_BASE_T: 6703 case I40E_DEV_ID_10G_BASE_T4: 6704 #ifdef CARLSVILLE_HW 6705 case I40E_DEV_ID_10G_BASE_T_BC: 6706 #endif 6707 case I40E_DEV_ID_10G_BASE_T_X722: 6708 case I40E_DEV_ID_25G_B: 6709 case I40E_DEV_ID_25G_SFP28: 6710 status = i40e_write_phy_register_clause45(hw, 6711 page, reg, phy_addr, value); 6712 break; 6713 default: 6714 status = I40E_ERR_UNKNOWN_PHY; 6715 break; 6716 } 6717 6718 return status; 6719 } 6720 6721 /** 6722 * i40e_read_phy_register 6723 * @hw: pointer to the HW structure 6724 * @page: registers page number 6725 * @reg: register address in the page 6726 * @phy_addr: PHY address on MDIO interface 6727 * @value: PHY register value 6728 * 6729 * Reads specified PHY register value 6730 **/ 6731 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6732 u8 page, u16 reg, u8 phy_addr, u16 *value) 6733 { 6734 enum i40e_status_code status; 6735 6736 switch (hw->device_id) { 6737 case I40E_DEV_ID_1G_BASE_T_X722: 6738 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6739 value); 6740 break; 6741 case I40E_DEV_ID_10G_BASE_T: 6742 case I40E_DEV_ID_10G_BASE_T4: 6743 case I40E_DEV_ID_10G_BASE_T_X722: 6744 case I40E_DEV_ID_25G_B: 6745 case I40E_DEV_ID_25G_SFP28: 6746 status = i40e_read_phy_register_clause45(hw, page, reg, 6747 phy_addr, value); 6748 break; 6749 default: 6750 status = I40E_ERR_UNKNOWN_PHY; 6751 break; 6752 } 6753 6754 return status; 6755 } 6756 6757 /** 6758 * i40e_get_phy_address 6759 * @hw: pointer to the HW structure 6760 * @dev_num: PHY port num that address we want 6761 * 6762 * Gets PHY address for current port 6763 **/ 6764 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6765 { 6766 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6767 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6768 6769 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6770 } 6771 6772 /** 6773 * i40e_blink_phy_led 6774 * @hw: pointer to the HW structure 6775 * @time: time how long led will blinks in secs 6776 * @interval: gap between LED on and off in msecs 6777 * 6778 * Blinks PHY link LED 6779 **/ 6780 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6781 u32 time, u32 interval) 6782 { 6783 enum i40e_status_code status = I40E_SUCCESS; 6784 u32 i; 6785 u16 led_ctl = 0; 6786 u16 gpio_led_port; 6787 u16 led_reg; 6788 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6789 u8 phy_addr = 0; 6790 u8 port_num; 6791 6792 i = rd32(hw, I40E_PFGEN_PORTNUM); 6793 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6794 phy_addr = i40e_get_phy_address(hw, port_num); 6795 6796 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6797 led_addr++) { 6798 status = i40e_read_phy_register_clause45(hw, 6799 I40E_PHY_COM_REG_PAGE, 6800 led_addr, phy_addr, 6801 &led_reg); 6802 if (status) 6803 goto phy_blinking_end; 6804 led_ctl = led_reg; 6805 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6806 led_reg = 0; 6807 status = i40e_write_phy_register_clause45(hw, 6808 I40E_PHY_COM_REG_PAGE, 6809 led_addr, phy_addr, 6810 led_reg); 6811 if (status) 6812 goto phy_blinking_end; 6813 break; 6814 } 6815 } 6816 6817 if (time > 0 && interval > 0) { 6818 for (i = 0; i < time * 1000; i += interval) { 6819 status = i40e_read_phy_register_clause45(hw, 6820 I40E_PHY_COM_REG_PAGE, 6821 led_addr, phy_addr, &led_reg); 6822 if (status) 6823 goto restore_config; 6824 if (led_reg & I40E_PHY_LED_MANUAL_ON) 6825 led_reg = 0; 6826 else 6827 led_reg = I40E_PHY_LED_MANUAL_ON; 6828 status = i40e_write_phy_register_clause45(hw, 6829 I40E_PHY_COM_REG_PAGE, 6830 led_addr, phy_addr, led_reg); 6831 if (status) 6832 goto restore_config; 6833 i40e_msec_delay(interval); 6834 } 6835 } 6836 6837 restore_config: 6838 status = i40e_write_phy_register_clause45(hw, 6839 I40E_PHY_COM_REG_PAGE, 6840 led_addr, phy_addr, led_ctl); 6841 6842 phy_blinking_end: 6843 return status; 6844 } 6845 6846 /** 6847 * i40e_led_get_reg - read LED register 6848 * @hw: pointer to the HW structure 6849 * @led_addr: LED register address 6850 * @reg_val: read register value 6851 **/ 6852 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 6853 u32 *reg_val) 6854 { 6855 enum i40e_status_code status; 6856 u8 phy_addr = 0; 6857 6858 *reg_val = 0; 6859 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6860 status = i40e_aq_get_phy_register(hw, 6861 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6862 I40E_PHY_COM_REG_PAGE, true, 6863 I40E_PHY_LED_PROV_REG_1, 6864 reg_val, NULL); 6865 } else { 6866 phy_addr = i40e_get_phy_address(hw, hw->port); 6867 status = i40e_read_phy_register_clause45(hw, 6868 I40E_PHY_COM_REG_PAGE, 6869 led_addr, phy_addr, 6870 (u16 *)reg_val); 6871 } 6872 return status; 6873 } 6874 6875 /** 6876 * i40e_led_set_reg - write LED register 6877 * @hw: pointer to the HW structure 6878 * @led_addr: LED register address 6879 * @reg_val: register value to write 6880 **/ 6881 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 6882 u32 reg_val) 6883 { 6884 enum i40e_status_code status; 6885 u8 phy_addr = 0; 6886 6887 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6888 status = i40e_aq_set_phy_register(hw, 6889 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6890 I40E_PHY_COM_REG_PAGE, true, 6891 I40E_PHY_LED_PROV_REG_1, 6892 reg_val, NULL); 6893 } else { 6894 phy_addr = i40e_get_phy_address(hw, hw->port); 6895 status = i40e_write_phy_register_clause45(hw, 6896 I40E_PHY_COM_REG_PAGE, 6897 led_addr, phy_addr, 6898 (u16)reg_val); 6899 } 6900 6901 return status; 6902 } 6903 6904 /** 6905 * i40e_led_get_phy - return current on/off mode 6906 * @hw: pointer to the hw struct 6907 * @led_addr: address of led register to use 6908 * @val: original value of register to use 6909 * 6910 **/ 6911 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 6912 u16 *val) 6913 { 6914 enum i40e_status_code status = I40E_SUCCESS; 6915 u16 gpio_led_port; 6916 u32 reg_val_aq; 6917 u16 temp_addr; 6918 u8 phy_addr = 0; 6919 u16 reg_val; 6920 6921 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6922 status = i40e_aq_get_phy_register(hw, 6923 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6924 I40E_PHY_COM_REG_PAGE, true, 6925 I40E_PHY_LED_PROV_REG_1, 6926 ®_val_aq, NULL); 6927 if (status == I40E_SUCCESS) 6928 *val = (u16)reg_val_aq; 6929 return status; 6930 } 6931 temp_addr = I40E_PHY_LED_PROV_REG_1; 6932 phy_addr = i40e_get_phy_address(hw, hw->port); 6933 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6934 temp_addr++) { 6935 status = i40e_read_phy_register_clause45(hw, 6936 I40E_PHY_COM_REG_PAGE, 6937 temp_addr, phy_addr, 6938 ®_val); 6939 if (status) 6940 return status; 6941 *val = reg_val; 6942 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 6943 *led_addr = temp_addr; 6944 break; 6945 } 6946 } 6947 return status; 6948 } 6949 6950 /** 6951 * i40e_led_set_phy 6952 * @hw: pointer to the HW structure 6953 * @on: true or false 6954 * @led_addr: address of led register to use 6955 * @mode: original val plus bit for set or ignore 6956 * 6957 * Set led's on or off when controlled by the PHY 6958 * 6959 **/ 6960 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 6961 u16 led_addr, u32 mode) 6962 { 6963 enum i40e_status_code status = I40E_SUCCESS; 6964 u32 led_ctl = 0; 6965 u32 led_reg = 0; 6966 6967 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6968 if (status) 6969 return status; 6970 led_ctl = led_reg; 6971 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6972 led_reg = 0; 6973 status = i40e_led_set_reg(hw, led_addr, led_reg); 6974 if (status) 6975 return status; 6976 } 6977 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6978 if (status) 6979 goto restore_config; 6980 if (on) 6981 led_reg = I40E_PHY_LED_MANUAL_ON; 6982 else 6983 led_reg = 0; 6984 status = i40e_led_set_reg(hw, led_addr, led_reg); 6985 if (status) 6986 goto restore_config; 6987 if (mode & I40E_PHY_LED_MODE_ORIG) { 6988 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 6989 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6990 } 6991 return status; 6992 6993 restore_config: 6994 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6995 return status; 6996 } 6997 #endif /* PF_DRIVER */ 6998 6999 /** 7000 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 7001 * @hw: pointer to the hw struct 7002 * @reg_addr: register address 7003 * @reg_val: ptr to register value 7004 * @cmd_details: pointer to command details structure or NULL 7005 * 7006 * Use the firmware to read the Rx control register, 7007 * especially useful if the Rx unit is under heavy pressure 7008 **/ 7009 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 7010 u32 reg_addr, u32 *reg_val, 7011 struct i40e_asq_cmd_details *cmd_details) 7012 { 7013 struct i40e_aq_desc desc; 7014 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 7015 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 7016 enum i40e_status_code status; 7017 7018 if (reg_val == NULL) 7019 return I40E_ERR_PARAM; 7020 7021 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 7022 7023 cmd_resp->address = CPU_TO_LE32(reg_addr); 7024 7025 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7026 7027 if (status == I40E_SUCCESS) 7028 *reg_val = LE32_TO_CPU(cmd_resp->value); 7029 7030 return status; 7031 } 7032 7033 /** 7034 * i40e_read_rx_ctl - read from an Rx control register 7035 * @hw: pointer to the hw struct 7036 * @reg_addr: register address 7037 **/ 7038 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 7039 { 7040 enum i40e_status_code status = I40E_SUCCESS; 7041 bool use_register; 7042 int retry = 5; 7043 u32 val = 0; 7044 7045 use_register = (((hw->aq.api_maj_ver == 1) && 7046 (hw->aq.api_min_ver < 5)) || 7047 (hw->mac.type == I40E_MAC_X722)); 7048 if (!use_register) { 7049 do_retry: 7050 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 7051 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 7052 i40e_msec_delay(1); 7053 retry--; 7054 goto do_retry; 7055 } 7056 } 7057 7058 /* if the AQ access failed, try the old-fashioned way */ 7059 if (status || use_register) 7060 val = rd32(hw, reg_addr); 7061 7062 return val; 7063 } 7064 7065 /** 7066 * i40e_aq_rx_ctl_write_register 7067 * @hw: pointer to the hw struct 7068 * @reg_addr: register address 7069 * @reg_val: register value 7070 * @cmd_details: pointer to command details structure or NULL 7071 * 7072 * Use the firmware to write to an Rx control register, 7073 * especially useful if the Rx unit is under heavy pressure 7074 **/ 7075 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 7076 u32 reg_addr, u32 reg_val, 7077 struct i40e_asq_cmd_details *cmd_details) 7078 { 7079 struct i40e_aq_desc desc; 7080 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 7081 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 7082 enum i40e_status_code status; 7083 7084 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 7085 7086 cmd->address = CPU_TO_LE32(reg_addr); 7087 cmd->value = CPU_TO_LE32(reg_val); 7088 7089 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7090 7091 return status; 7092 } 7093 7094 /** 7095 * i40e_write_rx_ctl - write to an Rx control register 7096 * @hw: pointer to the hw struct 7097 * @reg_addr: register address 7098 * @reg_val: register value 7099 **/ 7100 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 7101 { 7102 enum i40e_status_code status = I40E_SUCCESS; 7103 bool use_register; 7104 int retry = 5; 7105 7106 use_register = (((hw->aq.api_maj_ver == 1) && 7107 (hw->aq.api_min_ver < 5)) || 7108 (hw->mac.type == I40E_MAC_X722)); 7109 if (!use_register) { 7110 do_retry: 7111 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 7112 reg_val, NULL); 7113 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 7114 i40e_msec_delay(1); 7115 retry--; 7116 goto do_retry; 7117 } 7118 } 7119 7120 /* if the AQ access failed, try the old-fashioned way */ 7121 if (status || use_register) 7122 wr32(hw, reg_addr, reg_val); 7123 } 7124 7125 #ifdef PF_DRIVER 7126 /** 7127 * i40e_aq_set_phy_register 7128 * @hw: pointer to the hw struct 7129 * @phy_select: select which phy should be accessed 7130 * @dev_addr: PHY device address 7131 * @page_change: enable auto page change 7132 * @reg_addr: PHY register address 7133 * @reg_val: new register value 7134 * @cmd_details: pointer to command details structure or NULL 7135 * 7136 * Write the external PHY register. 7137 **/ 7138 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw, 7139 u8 phy_select, u8 dev_addr, bool page_change, 7140 u32 reg_addr, u32 reg_val, 7141 struct i40e_asq_cmd_details *cmd_details) 7142 { 7143 struct i40e_aq_desc desc; 7144 struct i40e_aqc_phy_register_access *cmd = 7145 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 7146 enum i40e_status_code status; 7147 7148 i40e_fill_default_direct_cmd_desc(&desc, 7149 i40e_aqc_opc_set_phy_register); 7150 7151 cmd->phy_interface = phy_select; 7152 cmd->dev_addres = dev_addr; 7153 cmd->reg_address = CPU_TO_LE32(reg_addr); 7154 cmd->reg_value = CPU_TO_LE32(reg_val); 7155 7156 if (!page_change) 7157 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 7158 7159 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7160 7161 return status; 7162 } 7163 7164 /** 7165 * i40e_aq_get_phy_register 7166 * @hw: pointer to the hw struct 7167 * @phy_select: select which phy should be accessed 7168 * @dev_addr: PHY device address 7169 * @page_change: enable auto page change 7170 * @reg_addr: PHY register address 7171 * @reg_val: read register value 7172 * @cmd_details: pointer to command details structure or NULL 7173 * 7174 * Read the external PHY register. 7175 **/ 7176 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw, 7177 u8 phy_select, u8 dev_addr, bool page_change, 7178 u32 reg_addr, u32 *reg_val, 7179 struct i40e_asq_cmd_details *cmd_details) 7180 { 7181 struct i40e_aq_desc desc; 7182 struct i40e_aqc_phy_register_access *cmd = 7183 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 7184 enum i40e_status_code status; 7185 7186 i40e_fill_default_direct_cmd_desc(&desc, 7187 i40e_aqc_opc_get_phy_register); 7188 7189 cmd->phy_interface = phy_select; 7190 cmd->dev_addres = dev_addr; 7191 cmd->reg_address = CPU_TO_LE32(reg_addr); 7192 7193 if (!page_change) 7194 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 7195 7196 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7197 if (!status) 7198 *reg_val = LE32_TO_CPU(cmd->reg_value); 7199 7200 return status; 7201 } 7202 7203 #endif /* PF_DRIVER */ 7204 #ifdef VF_DRIVER 7205 7206 /** 7207 * i40e_aq_send_msg_to_pf 7208 * @hw: pointer to the hardware structure 7209 * @v_opcode: opcodes for VF-PF communication 7210 * @v_retval: return error code 7211 * @msg: pointer to the msg buffer 7212 * @msglen: msg length 7213 * @cmd_details: pointer to command details 7214 * 7215 * Send message to PF driver using admin queue. By default, this message 7216 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 7217 * completion before returning. 7218 **/ 7219 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 7220 enum virtchnl_ops v_opcode, 7221 enum i40e_status_code v_retval, 7222 u8 *msg, u16 msglen, 7223 struct i40e_asq_cmd_details *cmd_details) 7224 { 7225 struct i40e_aq_desc desc; 7226 struct i40e_asq_cmd_details details; 7227 enum i40e_status_code status; 7228 7229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 7230 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 7231 desc.cookie_high = CPU_TO_LE32(v_opcode); 7232 desc.cookie_low = CPU_TO_LE32(v_retval); 7233 if (msglen) { 7234 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 7235 | I40E_AQ_FLAG_RD)); 7236 if (msglen > I40E_AQ_LARGE_BUF) 7237 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7238 desc.datalen = CPU_TO_LE16(msglen); 7239 } 7240 if (!cmd_details) { 7241 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 7242 details.async = true; 7243 cmd_details = &details; 7244 } 7245 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 7246 msglen, cmd_details); 7247 return status; 7248 } 7249 7250 /** 7251 * i40e_vf_parse_hw_config 7252 * @hw: pointer to the hardware structure 7253 * @msg: pointer to the virtual channel VF resource structure 7254 * 7255 * Given a VF resource message from the PF, populate the hw struct 7256 * with appropriate information. 7257 **/ 7258 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 7259 struct virtchnl_vf_resource *msg) 7260 { 7261 struct virtchnl_vsi_resource *vsi_res; 7262 int i; 7263 7264 vsi_res = &msg->vsi_res[0]; 7265 7266 hw->dev_caps.num_vsis = msg->num_vsis; 7267 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 7268 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 7269 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 7270 hw->dev_caps.dcb = msg->vf_cap_flags & 7271 VIRTCHNL_VF_OFFLOAD_L2; 7272 hw->dev_caps.iwarp = (msg->vf_cap_flags & 7273 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 7274 for (i = 0; i < msg->num_vsis; i++) { 7275 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) { 7276 i40e_memcpy(hw->mac.perm_addr, 7277 vsi_res->default_mac_addr, 7278 ETH_ALEN, 7279 I40E_NONDMA_TO_NONDMA); 7280 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 7281 ETH_ALEN, 7282 I40E_NONDMA_TO_NONDMA); 7283 } 7284 vsi_res++; 7285 } 7286 } 7287 7288 /** 7289 * i40e_vf_reset 7290 * @hw: pointer to the hardware structure 7291 * 7292 * Send a VF_RESET message to the PF. Does not wait for response from PF 7293 * as none will be forthcoming. Immediately after calling this function, 7294 * the admin queue should be shut down and (optionally) reinitialized. 7295 **/ 7296 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 7297 { 7298 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF, 7299 I40E_SUCCESS, NULL, 0, NULL); 7300 } 7301 #endif /* VF_DRIVER */ 7302 7303 /** 7304 * i40e_aq_set_arp_proxy_config 7305 * @hw: pointer to the HW structure 7306 * @proxy_config: pointer to proxy config command table struct 7307 * @cmd_details: pointer to command details 7308 * 7309 * Set ARP offload parameters from pre-populated 7310 * i40e_aqc_arp_proxy_data struct 7311 **/ 7312 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 7313 struct i40e_aqc_arp_proxy_data *proxy_config, 7314 struct i40e_asq_cmd_details *cmd_details) 7315 { 7316 struct i40e_aq_desc desc; 7317 enum i40e_status_code status; 7318 7319 if (!proxy_config) 7320 return I40E_ERR_PARAM; 7321 7322 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 7323 7324 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7325 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7326 desc.params.external.addr_high = 7327 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config)); 7328 desc.params.external.addr_low = 7329 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config)); 7330 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data)); 7331 7332 status = i40e_asq_send_command(hw, &desc, proxy_config, 7333 sizeof(struct i40e_aqc_arp_proxy_data), 7334 cmd_details); 7335 7336 return status; 7337 } 7338 7339 /** 7340 * i40e_aq_opc_set_ns_proxy_table_entry 7341 * @hw: pointer to the HW structure 7342 * @ns_proxy_table_entry: pointer to NS table entry command struct 7343 * @cmd_details: pointer to command details 7344 * 7345 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 7346 * from pre-populated i40e_aqc_ns_proxy_data struct 7347 **/ 7348 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 7349 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 7350 struct i40e_asq_cmd_details *cmd_details) 7351 { 7352 struct i40e_aq_desc desc; 7353 enum i40e_status_code status; 7354 7355 if (!ns_proxy_table_entry) 7356 return I40E_ERR_PARAM; 7357 7358 i40e_fill_default_direct_cmd_desc(&desc, 7359 i40e_aqc_opc_set_ns_proxy_table_entry); 7360 7361 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7362 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7363 desc.params.external.addr_high = 7364 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry)); 7365 desc.params.external.addr_low = 7366 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry)); 7367 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data)); 7368 7369 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 7370 sizeof(struct i40e_aqc_ns_proxy_data), 7371 cmd_details); 7372 7373 return status; 7374 } 7375 7376 /** 7377 * i40e_aq_set_clear_wol_filter 7378 * @hw: pointer to the hw struct 7379 * @filter_index: index of filter to modify (0-7) 7380 * @filter: buffer containing filter to be set 7381 * @set_filter: true to set filter, false to clear filter 7382 * @no_wol_tco: if true, pass through packets cannot cause wake-up 7383 * if false, pass through packets may cause wake-up 7384 * @filter_valid: true if filter action is valid 7385 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid 7386 * @cmd_details: pointer to command details structure or NULL 7387 * 7388 * Set or clear WoL filter for port attached to the PF 7389 **/ 7390 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 7391 u8 filter_index, 7392 struct i40e_aqc_set_wol_filter_data *filter, 7393 bool set_filter, bool no_wol_tco, 7394 bool filter_valid, bool no_wol_tco_valid, 7395 struct i40e_asq_cmd_details *cmd_details) 7396 { 7397 struct i40e_aq_desc desc; 7398 struct i40e_aqc_set_wol_filter *cmd = 7399 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 7400 enum i40e_status_code status; 7401 u16 cmd_flags = 0; 7402 u16 valid_flags = 0; 7403 u16 buff_len = 0; 7404 7405 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 7406 7407 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 7408 return I40E_ERR_PARAM; 7409 cmd->filter_index = CPU_TO_LE16(filter_index); 7410 7411 if (set_filter) { 7412 if (!filter) 7413 return I40E_ERR_PARAM; 7414 7415 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 7416 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR; 7417 } 7418 7419 if (no_wol_tco) 7420 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 7421 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 7422 7423 if (filter_valid) 7424 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 7425 if (no_wol_tco_valid) 7426 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 7427 cmd->valid_flags = CPU_TO_LE16(valid_flags); 7428 7429 buff_len = sizeof(*filter); 7430 desc.datalen = CPU_TO_LE16(buff_len); 7431 7432 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7433 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7434 7435 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter)); 7436 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter)); 7437 7438 status = i40e_asq_send_command(hw, &desc, filter, 7439 buff_len, cmd_details); 7440 7441 return status; 7442 } 7443 7444 /** 7445 * i40e_aq_get_wake_event_reason 7446 * @hw: pointer to the hw struct 7447 * @wake_reason: return value, index of matching filter 7448 * @cmd_details: pointer to command details structure or NULL 7449 * 7450 * Get information for the reason of a Wake Up event 7451 **/ 7452 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 7453 u16 *wake_reason, 7454 struct i40e_asq_cmd_details *cmd_details) 7455 { 7456 struct i40e_aq_desc desc; 7457 struct i40e_aqc_get_wake_reason_completion *resp = 7458 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 7459 enum i40e_status_code status; 7460 7461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 7462 7463 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7464 7465 if (status == I40E_SUCCESS) 7466 *wake_reason = LE16_TO_CPU(resp->wake_reason); 7467 7468 return status; 7469 } 7470 7471 /** 7472 * i40e_aq_clear_all_wol_filters 7473 * @hw: pointer to the hw struct 7474 * @cmd_details: pointer to command details structure or NULL 7475 * 7476 * Get information for the reason of a Wake Up event 7477 **/ 7478 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw, 7479 struct i40e_asq_cmd_details *cmd_details) 7480 { 7481 struct i40e_aq_desc desc; 7482 enum i40e_status_code status; 7483 7484 i40e_fill_default_direct_cmd_desc(&desc, 7485 i40e_aqc_opc_clear_all_wol_filters); 7486 7487 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7488 7489 return status; 7490 } 7491 7492 /** 7493 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 7494 * @hw: pointer to the hw struct 7495 * @buff: command buffer (size in bytes = buff_size) 7496 * @buff_size: buffer size in bytes 7497 * @track_id: package tracking id 7498 * @error_offset: returns error offset 7499 * @error_info: returns error information 7500 * @cmd_details: pointer to command details structure or NULL 7501 **/ 7502 enum 7503 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 7504 u16 buff_size, u32 track_id, 7505 u32 *error_offset, u32 *error_info, 7506 struct i40e_asq_cmd_details *cmd_details) 7507 { 7508 struct i40e_aq_desc desc; 7509 struct i40e_aqc_write_personalization_profile *cmd = 7510 (struct i40e_aqc_write_personalization_profile *) 7511 &desc.params.raw; 7512 struct i40e_aqc_write_ddp_resp *resp; 7513 enum i40e_status_code status; 7514 7515 i40e_fill_default_direct_cmd_desc(&desc, 7516 i40e_aqc_opc_write_personalization_profile); 7517 7518 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 7519 if (buff_size > I40E_AQ_LARGE_BUF) 7520 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7521 7522 desc.datalen = CPU_TO_LE16(buff_size); 7523 7524 cmd->profile_track_id = CPU_TO_LE32(track_id); 7525 7526 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 7527 if (!status) { 7528 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 7529 if (error_offset) 7530 *error_offset = LE32_TO_CPU(resp->error_offset); 7531 if (error_info) 7532 *error_info = LE32_TO_CPU(resp->error_info); 7533 } 7534 7535 return status; 7536 } 7537 7538 /** 7539 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 7540 * @hw: pointer to the hw struct 7541 * @buff: command buffer (size in bytes = buff_size) 7542 * @buff_size: buffer size in bytes 7543 * @flags: AdminQ command flags 7544 * @cmd_details: pointer to command details structure or NULL 7545 **/ 7546 enum 7547 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 7548 u16 buff_size, u8 flags, 7549 struct i40e_asq_cmd_details *cmd_details) 7550 { 7551 struct i40e_aq_desc desc; 7552 struct i40e_aqc_get_applied_profiles *cmd = 7553 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 7554 enum i40e_status_code status; 7555 7556 i40e_fill_default_direct_cmd_desc(&desc, 7557 i40e_aqc_opc_get_personalization_profile_list); 7558 7559 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7560 if (buff_size > I40E_AQ_LARGE_BUF) 7561 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7562 desc.datalen = CPU_TO_LE16(buff_size); 7563 7564 cmd->flags = flags; 7565 7566 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 7567 7568 return status; 7569 } 7570 7571 /** 7572 * i40e_find_segment_in_package 7573 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 7574 * @pkg_hdr: pointer to the package header to be searched 7575 * 7576 * This function searches a package file for a particular segment type. On 7577 * success it returns a pointer to the segment header, otherwise it will 7578 * return NULL. 7579 **/ 7580 struct i40e_generic_seg_header * 7581 i40e_find_segment_in_package(u32 segment_type, 7582 struct i40e_package_header *pkg_hdr) 7583 { 7584 struct i40e_generic_seg_header *segment; 7585 u32 i; 7586 7587 /* Search all package segments for the requested segment type */ 7588 for (i = 0; i < pkg_hdr->segment_count; i++) { 7589 segment = 7590 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 7591 pkg_hdr->segment_offset[i]); 7592 7593 if (segment->type == segment_type) 7594 return segment; 7595 } 7596 7597 return NULL; 7598 } 7599 7600 /* Get section table in profile */ 7601 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 7602 do { \ 7603 struct i40e_profile_segment *p = (profile); \ 7604 u32 count; \ 7605 u32 *nvm; \ 7606 count = p->device_table_count; \ 7607 nvm = (u32 *)&p->device_table[count]; \ 7608 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 7609 } while (0) 7610 7611 /* Get section header in profile */ 7612 #define I40E_SECTION_HEADER(profile, offset) \ 7613 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 7614 7615 /** 7616 * i40e_find_section_in_profile 7617 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE) 7618 * @profile: pointer to the i40e segment header to be searched 7619 * 7620 * This function searches i40e segment for a particular section type. On 7621 * success it returns a pointer to the section header, otherwise it will 7622 * return NULL. 7623 **/ 7624 struct i40e_profile_section_header * 7625 i40e_find_section_in_profile(u32 section_type, 7626 struct i40e_profile_segment *profile) 7627 { 7628 struct i40e_profile_section_header *sec; 7629 struct i40e_section_table *sec_tbl; 7630 u32 sec_off; 7631 u32 i; 7632 7633 if (profile->header.type != SEGMENT_TYPE_I40E) 7634 return NULL; 7635 7636 I40E_SECTION_TABLE(profile, sec_tbl); 7637 7638 for (i = 0; i < sec_tbl->section_count; i++) { 7639 sec_off = sec_tbl->section_offset[i]; 7640 sec = I40E_SECTION_HEADER(profile, sec_off); 7641 if (sec->section.type == section_type) 7642 return sec; 7643 } 7644 7645 return NULL; 7646 } 7647 7648 /** 7649 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 7650 * @hw: pointer to the hw struct 7651 * @aq: command buffer containing all data to execute AQ 7652 **/ 7653 STATIC enum 7654 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw, 7655 struct i40e_profile_aq_section *aq) 7656 { 7657 enum i40e_status_code status; 7658 struct i40e_aq_desc desc; 7659 u8 *msg = NULL; 7660 u16 msglen; 7661 7662 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 7663 desc.flags |= CPU_TO_LE16(aq->flags); 7664 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw), 7665 I40E_NONDMA_TO_NONDMA); 7666 7667 msglen = aq->datalen; 7668 if (msglen) { 7669 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 7670 I40E_AQ_FLAG_RD)); 7671 if (msglen > I40E_AQ_LARGE_BUF) 7672 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7673 desc.datalen = CPU_TO_LE16(msglen); 7674 msg = &aq->data[0]; 7675 } 7676 7677 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 7678 7679 if (status != I40E_SUCCESS) { 7680 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7681 "unable to exec DDP AQ opcode %u, error %d\n", 7682 aq->opcode, status); 7683 return status; 7684 } 7685 7686 /* copy returned desc to aq_buf */ 7687 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw), 7688 I40E_NONDMA_TO_NONDMA); 7689 7690 return I40E_SUCCESS; 7691 } 7692 7693 /** 7694 * i40e_validate_profile 7695 * @hw: pointer to the hardware structure 7696 * @profile: pointer to the profile segment of the package to be validated 7697 * @track_id: package tracking id 7698 * @rollback: flag if the profile is for rollback. 7699 * 7700 * Validates supported devices and profile's sections. 7701 */ 7702 STATIC enum i40e_status_code 7703 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 7704 u32 track_id, bool rollback) 7705 { 7706 struct i40e_profile_section_header *sec = NULL; 7707 enum i40e_status_code status = I40E_SUCCESS; 7708 struct i40e_section_table *sec_tbl; 7709 u32 vendor_dev_id; 7710 u32 dev_cnt; 7711 u32 sec_off; 7712 u32 i; 7713 7714 if (track_id == I40E_DDP_TRACKID_INVALID) { 7715 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 7716 return I40E_NOT_SUPPORTED; 7717 } 7718 7719 dev_cnt = profile->device_table_count; 7720 for (i = 0; i < dev_cnt; i++) { 7721 vendor_dev_id = profile->device_table[i].vendor_dev_id; 7722 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID && 7723 hw->device_id == (vendor_dev_id & 0xFFFF)) 7724 break; 7725 } 7726 if (dev_cnt && (i == dev_cnt)) { 7727 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7728 "Device doesn't support DDP\n"); 7729 return I40E_ERR_DEVICE_NOT_SUPPORTED; 7730 } 7731 7732 I40E_SECTION_TABLE(profile, sec_tbl); 7733 7734 /* Validate sections types */ 7735 for (i = 0; i < sec_tbl->section_count; i++) { 7736 sec_off = sec_tbl->section_offset[i]; 7737 sec = I40E_SECTION_HEADER(profile, sec_off); 7738 if (rollback) { 7739 if (sec->section.type == SECTION_TYPE_MMIO || 7740 sec->section.type == SECTION_TYPE_AQ || 7741 sec->section.type == SECTION_TYPE_RB_AQ) { 7742 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7743 "Not a roll-back package\n"); 7744 return I40E_NOT_SUPPORTED; 7745 } 7746 } else { 7747 if (sec->section.type == SECTION_TYPE_RB_AQ || 7748 sec->section.type == SECTION_TYPE_RB_MMIO) { 7749 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7750 "Not an original package\n"); 7751 return I40E_NOT_SUPPORTED; 7752 } 7753 } 7754 } 7755 7756 return status; 7757 } 7758 7759 /** 7760 * i40e_write_profile 7761 * @hw: pointer to the hardware structure 7762 * @profile: pointer to the profile segment of the package to be downloaded 7763 * @track_id: package tracking id 7764 * 7765 * Handles the download of a complete package. 7766 */ 7767 enum i40e_status_code 7768 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 7769 u32 track_id) 7770 { 7771 enum i40e_status_code status = I40E_SUCCESS; 7772 struct i40e_section_table *sec_tbl; 7773 struct i40e_profile_section_header *sec = NULL; 7774 struct i40e_profile_aq_section *ddp_aq; 7775 u32 section_size = 0; 7776 u32 offset = 0, info = 0; 7777 u32 sec_off; 7778 u32 i; 7779 7780 status = i40e_validate_profile(hw, profile, track_id, false); 7781 if (status) 7782 return status; 7783 7784 I40E_SECTION_TABLE(profile, sec_tbl); 7785 7786 for (i = 0; i < sec_tbl->section_count; i++) { 7787 sec_off = sec_tbl->section_offset[i]; 7788 sec = I40E_SECTION_HEADER(profile, sec_off); 7789 /* Process generic admin command */ 7790 if (sec->section.type == SECTION_TYPE_AQ) { 7791 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 7792 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 7793 if (status) { 7794 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7795 "Failed to execute aq: section %d, opcode %u\n", 7796 i, ddp_aq->opcode); 7797 break; 7798 } 7799 sec->section.type = SECTION_TYPE_RB_AQ; 7800 } 7801 7802 /* Skip any non-mmio sections */ 7803 if (sec->section.type != SECTION_TYPE_MMIO) 7804 continue; 7805 7806 section_size = sec->section.size + 7807 sizeof(struct i40e_profile_section_header); 7808 7809 /* Write MMIO section */ 7810 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 7811 track_id, &offset, &info, NULL); 7812 if (status) { 7813 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7814 "Failed to write profile: section %d, offset %d, info %d\n", 7815 i, offset, info); 7816 break; 7817 } 7818 } 7819 return status; 7820 } 7821 7822 /** 7823 * i40e_rollback_profile 7824 * @hw: pointer to the hardware structure 7825 * @profile: pointer to the profile segment of the package to be removed 7826 * @track_id: package tracking id 7827 * 7828 * Rolls back previously loaded package. 7829 */ 7830 enum i40e_status_code 7831 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 7832 u32 track_id) 7833 { 7834 struct i40e_profile_section_header *sec = NULL; 7835 enum i40e_status_code status = I40E_SUCCESS; 7836 struct i40e_section_table *sec_tbl; 7837 u32 offset = 0, info = 0; 7838 u32 section_size = 0; 7839 u32 sec_off; 7840 int i; 7841 7842 status = i40e_validate_profile(hw, profile, track_id, true); 7843 if (status) 7844 return status; 7845 7846 I40E_SECTION_TABLE(profile, sec_tbl); 7847 7848 /* For rollback write sections in reverse */ 7849 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 7850 sec_off = sec_tbl->section_offset[i]; 7851 sec = I40E_SECTION_HEADER(profile, sec_off); 7852 7853 /* Skip any non-rollback sections */ 7854 if (sec->section.type != SECTION_TYPE_RB_MMIO) 7855 continue; 7856 7857 section_size = sec->section.size + 7858 sizeof(struct i40e_profile_section_header); 7859 7860 /* Write roll-back MMIO section */ 7861 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 7862 track_id, &offset, &info, NULL); 7863 if (status) { 7864 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7865 "Failed to write profile: section %d, offset %d, info %d\n", 7866 i, offset, info); 7867 break; 7868 } 7869 } 7870 return status; 7871 } 7872 7873 /** 7874 * i40e_add_pinfo_to_list 7875 * @hw: pointer to the hardware structure 7876 * @profile: pointer to the profile segment of the package 7877 * @profile_info_sec: buffer for information section 7878 * @track_id: package tracking id 7879 * 7880 * Register a profile to the list of loaded profiles. 7881 */ 7882 enum i40e_status_code 7883 i40e_add_pinfo_to_list(struct i40e_hw *hw, 7884 struct i40e_profile_segment *profile, 7885 u8 *profile_info_sec, u32 track_id) 7886 { 7887 enum i40e_status_code status = I40E_SUCCESS; 7888 struct i40e_profile_section_header *sec = NULL; 7889 struct i40e_profile_info *pinfo; 7890 u32 offset = 0, info = 0; 7891 7892 sec = (struct i40e_profile_section_header *)profile_info_sec; 7893 sec->tbl_size = 1; 7894 sec->data_end = sizeof(struct i40e_profile_section_header) + 7895 sizeof(struct i40e_profile_info); 7896 sec->section.type = SECTION_TYPE_INFO; 7897 sec->section.offset = sizeof(struct i40e_profile_section_header); 7898 sec->section.size = sizeof(struct i40e_profile_info); 7899 pinfo = (struct i40e_profile_info *)(profile_info_sec + 7900 sec->section.offset); 7901 pinfo->track_id = track_id; 7902 pinfo->version = profile->version; 7903 pinfo->op = I40E_DDP_ADD_TRACKID; 7904 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE, 7905 I40E_NONDMA_TO_NONDMA); 7906 7907 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end, 7908 track_id, &offset, &info, NULL); 7909 return status; 7910 } 7911