1 /******************************************************************************* 2 3 Copyright (c) 2013 - 2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 #include "i40e_type.h" 35 #include "i40e_adminq.h" 36 #include "i40e_prototype.h" 37 #include "virtchnl.h" 38 39 40 /** 41 * i40e_set_mac_type - Sets MAC type 42 * @hw: pointer to the HW structure 43 * 44 * This function sets the mac type of the adapter based on the 45 * vendor ID and device ID stored in the hw structure. 46 **/ 47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 #else 50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 51 #endif 52 { 53 enum i40e_status_code status = I40E_SUCCESS; 54 55 DEBUGFUNC("i40e_set_mac_type\n"); 56 57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 58 switch (hw->device_id) { 59 case I40E_DEV_ID_SFP_XL710: 60 case I40E_DEV_ID_QEMU: 61 case I40E_DEV_ID_KX_B: 62 case I40E_DEV_ID_KX_C: 63 case I40E_DEV_ID_QSFP_A: 64 case I40E_DEV_ID_QSFP_B: 65 case I40E_DEV_ID_QSFP_C: 66 case I40E_DEV_ID_10G_BASE_T: 67 case I40E_DEV_ID_10G_BASE_T4: 68 case I40E_DEV_ID_20G_KR2: 69 case I40E_DEV_ID_20G_KR2_A: 70 case I40E_DEV_ID_25G_B: 71 case I40E_DEV_ID_25G_SFP28: 72 hw->mac.type = I40E_MAC_XL710; 73 break; 74 #ifdef X722_A0_SUPPORT 75 case I40E_DEV_ID_X722_A0: 76 #endif 77 case I40E_DEV_ID_KX_X722: 78 case I40E_DEV_ID_QSFP_X722: 79 case I40E_DEV_ID_SFP_X722: 80 case I40E_DEV_ID_1G_BASE_T_X722: 81 case I40E_DEV_ID_10G_BASE_T_X722: 82 case I40E_DEV_ID_SFP_I_X722: 83 hw->mac.type = I40E_MAC_X722; 84 break; 85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 86 case I40E_DEV_ID_X722_VF: 87 #ifdef X722_A0_SUPPORT 88 case I40E_DEV_ID_X722_A0_VF: 89 #endif 90 hw->mac.type = I40E_MAC_X722_VF; 91 break; 92 #endif /* INTEGRATED_VF || VF_DRIVER */ 93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER) 94 case I40E_DEV_ID_VF: 95 case I40E_DEV_ID_VF_HV: 96 case I40E_DEV_ID_ADAPTIVE_VF: 97 hw->mac.type = I40E_MAC_VF; 98 break; 99 #endif 100 default: 101 hw->mac.type = I40E_MAC_GENERIC; 102 break; 103 } 104 } else { 105 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 106 } 107 108 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 109 hw->mac.type, status); 110 return status; 111 } 112 113 /** 114 * i40e_aq_str - convert AQ err code to a string 115 * @hw: pointer to the HW structure 116 * @aq_err: the AQ error code to convert 117 **/ 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 119 { 120 switch (aq_err) { 121 case I40E_AQ_RC_OK: 122 return "OK"; 123 case I40E_AQ_RC_EPERM: 124 return "I40E_AQ_RC_EPERM"; 125 case I40E_AQ_RC_ENOENT: 126 return "I40E_AQ_RC_ENOENT"; 127 case I40E_AQ_RC_ESRCH: 128 return "I40E_AQ_RC_ESRCH"; 129 case I40E_AQ_RC_EINTR: 130 return "I40E_AQ_RC_EINTR"; 131 case I40E_AQ_RC_EIO: 132 return "I40E_AQ_RC_EIO"; 133 case I40E_AQ_RC_ENXIO: 134 return "I40E_AQ_RC_ENXIO"; 135 case I40E_AQ_RC_E2BIG: 136 return "I40E_AQ_RC_E2BIG"; 137 case I40E_AQ_RC_EAGAIN: 138 return "I40E_AQ_RC_EAGAIN"; 139 case I40E_AQ_RC_ENOMEM: 140 return "I40E_AQ_RC_ENOMEM"; 141 case I40E_AQ_RC_EACCES: 142 return "I40E_AQ_RC_EACCES"; 143 case I40E_AQ_RC_EFAULT: 144 return "I40E_AQ_RC_EFAULT"; 145 case I40E_AQ_RC_EBUSY: 146 return "I40E_AQ_RC_EBUSY"; 147 case I40E_AQ_RC_EEXIST: 148 return "I40E_AQ_RC_EEXIST"; 149 case I40E_AQ_RC_EINVAL: 150 return "I40E_AQ_RC_EINVAL"; 151 case I40E_AQ_RC_ENOTTY: 152 return "I40E_AQ_RC_ENOTTY"; 153 case I40E_AQ_RC_ENOSPC: 154 return "I40E_AQ_RC_ENOSPC"; 155 case I40E_AQ_RC_ENOSYS: 156 return "I40E_AQ_RC_ENOSYS"; 157 case I40E_AQ_RC_ERANGE: 158 return "I40E_AQ_RC_ERANGE"; 159 case I40E_AQ_RC_EFLUSHED: 160 return "I40E_AQ_RC_EFLUSHED"; 161 case I40E_AQ_RC_BAD_ADDR: 162 return "I40E_AQ_RC_BAD_ADDR"; 163 case I40E_AQ_RC_EMODE: 164 return "I40E_AQ_RC_EMODE"; 165 case I40E_AQ_RC_EFBIG: 166 return "I40E_AQ_RC_EFBIG"; 167 } 168 169 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 170 return hw->err_str; 171 } 172 173 /** 174 * i40e_stat_str - convert status err code to a string 175 * @hw: pointer to the HW structure 176 * @stat_err: the status error code to convert 177 **/ 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 179 { 180 switch (stat_err) { 181 case I40E_SUCCESS: 182 return "OK"; 183 case I40E_ERR_NVM: 184 return "I40E_ERR_NVM"; 185 case I40E_ERR_NVM_CHECKSUM: 186 return "I40E_ERR_NVM_CHECKSUM"; 187 case I40E_ERR_PHY: 188 return "I40E_ERR_PHY"; 189 case I40E_ERR_CONFIG: 190 return "I40E_ERR_CONFIG"; 191 case I40E_ERR_PARAM: 192 return "I40E_ERR_PARAM"; 193 case I40E_ERR_MAC_TYPE: 194 return "I40E_ERR_MAC_TYPE"; 195 case I40E_ERR_UNKNOWN_PHY: 196 return "I40E_ERR_UNKNOWN_PHY"; 197 case I40E_ERR_LINK_SETUP: 198 return "I40E_ERR_LINK_SETUP"; 199 case I40E_ERR_ADAPTER_STOPPED: 200 return "I40E_ERR_ADAPTER_STOPPED"; 201 case I40E_ERR_INVALID_MAC_ADDR: 202 return "I40E_ERR_INVALID_MAC_ADDR"; 203 case I40E_ERR_DEVICE_NOT_SUPPORTED: 204 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 205 case I40E_ERR_MASTER_REQUESTS_PENDING: 206 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 207 case I40E_ERR_INVALID_LINK_SETTINGS: 208 return "I40E_ERR_INVALID_LINK_SETTINGS"; 209 case I40E_ERR_AUTONEG_NOT_COMPLETE: 210 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 211 case I40E_ERR_RESET_FAILED: 212 return "I40E_ERR_RESET_FAILED"; 213 case I40E_ERR_SWFW_SYNC: 214 return "I40E_ERR_SWFW_SYNC"; 215 case I40E_ERR_NO_AVAILABLE_VSI: 216 return "I40E_ERR_NO_AVAILABLE_VSI"; 217 case I40E_ERR_NO_MEMORY: 218 return "I40E_ERR_NO_MEMORY"; 219 case I40E_ERR_BAD_PTR: 220 return "I40E_ERR_BAD_PTR"; 221 case I40E_ERR_RING_FULL: 222 return "I40E_ERR_RING_FULL"; 223 case I40E_ERR_INVALID_PD_ID: 224 return "I40E_ERR_INVALID_PD_ID"; 225 case I40E_ERR_INVALID_QP_ID: 226 return "I40E_ERR_INVALID_QP_ID"; 227 case I40E_ERR_INVALID_CQ_ID: 228 return "I40E_ERR_INVALID_CQ_ID"; 229 case I40E_ERR_INVALID_CEQ_ID: 230 return "I40E_ERR_INVALID_CEQ_ID"; 231 case I40E_ERR_INVALID_AEQ_ID: 232 return "I40E_ERR_INVALID_AEQ_ID"; 233 case I40E_ERR_INVALID_SIZE: 234 return "I40E_ERR_INVALID_SIZE"; 235 case I40E_ERR_INVALID_ARP_INDEX: 236 return "I40E_ERR_INVALID_ARP_INDEX"; 237 case I40E_ERR_INVALID_FPM_FUNC_ID: 238 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 239 case I40E_ERR_QP_INVALID_MSG_SIZE: 240 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 241 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 242 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 243 case I40E_ERR_INVALID_FRAG_COUNT: 244 return "I40E_ERR_INVALID_FRAG_COUNT"; 245 case I40E_ERR_QUEUE_EMPTY: 246 return "I40E_ERR_QUEUE_EMPTY"; 247 case I40E_ERR_INVALID_ALIGNMENT: 248 return "I40E_ERR_INVALID_ALIGNMENT"; 249 case I40E_ERR_FLUSHED_QUEUE: 250 return "I40E_ERR_FLUSHED_QUEUE"; 251 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 252 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 253 case I40E_ERR_INVALID_IMM_DATA_SIZE: 254 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 255 case I40E_ERR_TIMEOUT: 256 return "I40E_ERR_TIMEOUT"; 257 case I40E_ERR_OPCODE_MISMATCH: 258 return "I40E_ERR_OPCODE_MISMATCH"; 259 case I40E_ERR_CQP_COMPL_ERROR: 260 return "I40E_ERR_CQP_COMPL_ERROR"; 261 case I40E_ERR_INVALID_VF_ID: 262 return "I40E_ERR_INVALID_VF_ID"; 263 case I40E_ERR_INVALID_HMCFN_ID: 264 return "I40E_ERR_INVALID_HMCFN_ID"; 265 case I40E_ERR_BACKING_PAGE_ERROR: 266 return "I40E_ERR_BACKING_PAGE_ERROR"; 267 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 268 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 269 case I40E_ERR_INVALID_PBLE_INDEX: 270 return "I40E_ERR_INVALID_PBLE_INDEX"; 271 case I40E_ERR_INVALID_SD_INDEX: 272 return "I40E_ERR_INVALID_SD_INDEX"; 273 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 274 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 275 case I40E_ERR_INVALID_SD_TYPE: 276 return "I40E_ERR_INVALID_SD_TYPE"; 277 case I40E_ERR_MEMCPY_FAILED: 278 return "I40E_ERR_MEMCPY_FAILED"; 279 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 280 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 281 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 282 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 283 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 284 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 285 case I40E_ERR_SRQ_ENABLED: 286 return "I40E_ERR_SRQ_ENABLED"; 287 case I40E_ERR_ADMIN_QUEUE_ERROR: 288 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 289 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 290 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 291 case I40E_ERR_BUF_TOO_SHORT: 292 return "I40E_ERR_BUF_TOO_SHORT"; 293 case I40E_ERR_ADMIN_QUEUE_FULL: 294 return "I40E_ERR_ADMIN_QUEUE_FULL"; 295 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 296 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 297 case I40E_ERR_BAD_IWARP_CQE: 298 return "I40E_ERR_BAD_IWARP_CQE"; 299 case I40E_ERR_NVM_BLANK_MODE: 300 return "I40E_ERR_NVM_BLANK_MODE"; 301 case I40E_ERR_NOT_IMPLEMENTED: 302 return "I40E_ERR_NOT_IMPLEMENTED"; 303 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 304 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 305 case I40E_ERR_DIAG_TEST_FAILED: 306 return "I40E_ERR_DIAG_TEST_FAILED"; 307 case I40E_ERR_NOT_READY: 308 return "I40E_ERR_NOT_READY"; 309 case I40E_NOT_SUPPORTED: 310 return "I40E_NOT_SUPPORTED"; 311 case I40E_ERR_FIRMWARE_API_VERSION: 312 return "I40E_ERR_FIRMWARE_API_VERSION"; 313 } 314 315 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 316 return hw->err_str; 317 } 318 319 /** 320 * i40e_debug_aq 321 * @hw: debug mask related to admin queue 322 * @mask: debug mask 323 * @desc: pointer to admin queue descriptor 324 * @buffer: pointer to command buffer 325 * @buf_len: max length of buffer 326 * 327 * Dumps debug log about adminq command with descriptor contents. 328 **/ 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 330 void *buffer, u16 buf_len) 331 { 332 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 333 u8 *buf = (u8 *)buffer; 334 u16 len; 335 u16 i = 0; 336 337 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 338 return; 339 340 len = LE16_TO_CPU(aq_desc->datalen); 341 342 i40e_debug(hw, mask, 343 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 344 LE16_TO_CPU(aq_desc->opcode), 345 LE16_TO_CPU(aq_desc->flags), 346 LE16_TO_CPU(aq_desc->datalen), 347 LE16_TO_CPU(aq_desc->retval)); 348 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 349 LE32_TO_CPU(aq_desc->cookie_high), 350 LE32_TO_CPU(aq_desc->cookie_low)); 351 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 352 LE32_TO_CPU(aq_desc->params.internal.param0), 353 LE32_TO_CPU(aq_desc->params.internal.param1)); 354 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 355 LE32_TO_CPU(aq_desc->params.external.addr_high), 356 LE32_TO_CPU(aq_desc->params.external.addr_low)); 357 358 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 359 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 360 if (buf_len < len) 361 len = buf_len; 362 /* write the full 16-byte chunks */ 363 for (i = 0; i < (len - 16); i += 16) 364 i40e_debug(hw, mask, 365 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 366 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 367 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 368 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 369 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 370 /* the most we could have left is 16 bytes, pad with zeros */ 371 if (i < len) { 372 char d_buf[16]; 373 int j, i_sav; 374 375 i_sav = i; 376 memset(d_buf, 0, sizeof(d_buf)); 377 for (j = 0; i < len; j++, i++) 378 d_buf[j] = buf[i]; 379 i40e_debug(hw, mask, 380 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 381 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 382 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 383 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 384 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 385 } 386 } 387 } 388 389 /** 390 * i40e_check_asq_alive 391 * @hw: pointer to the hw struct 392 * 393 * Returns true if Queue is enabled else false. 394 **/ 395 bool i40e_check_asq_alive(struct i40e_hw *hw) 396 { 397 if (hw->aq.asq.len) 398 #ifdef PF_DRIVER 399 #ifdef INTEGRATED_VF 400 if (!i40e_is_vf(hw)) 401 return !!(rd32(hw, hw->aq.asq.len) & 402 I40E_PF_ATQLEN_ATQENABLE_MASK); 403 #else 404 return !!(rd32(hw, hw->aq.asq.len) & 405 I40E_PF_ATQLEN_ATQENABLE_MASK); 406 #endif /* INTEGRATED_VF */ 407 #endif /* PF_DRIVER */ 408 #ifdef VF_DRIVER 409 #ifdef INTEGRATED_VF 410 if (i40e_is_vf(hw)) 411 return !!(rd32(hw, hw->aq.asq.len) & 412 I40E_VF_ATQLEN1_ATQENABLE_MASK); 413 #else 414 return !!(rd32(hw, hw->aq.asq.len) & 415 I40E_VF_ATQLEN1_ATQENABLE_MASK); 416 #endif /* INTEGRATED_VF */ 417 #endif /* VF_DRIVER */ 418 return false; 419 } 420 421 /** 422 * i40e_aq_queue_shutdown 423 * @hw: pointer to the hw struct 424 * @unloading: is the driver unloading itself 425 * 426 * Tell the Firmware that we're shutting down the AdminQ and whether 427 * or not the driver is unloading as well. 428 **/ 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 430 bool unloading) 431 { 432 struct i40e_aq_desc desc; 433 struct i40e_aqc_queue_shutdown *cmd = 434 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 435 enum i40e_status_code status; 436 437 i40e_fill_default_direct_cmd_desc(&desc, 438 i40e_aqc_opc_queue_shutdown); 439 440 if (unloading) 441 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 442 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 443 444 return status; 445 } 446 447 /** 448 * i40e_aq_get_set_rss_lut 449 * @hw: pointer to the hardware structure 450 * @vsi_id: vsi fw index 451 * @pf_lut: for PF table set true, for VSI table set false 452 * @lut: pointer to the lut buffer provided by the caller 453 * @lut_size: size of the lut buffer 454 * @set: set true to set the table, false to get the table 455 * 456 * Internal function to get or set RSS look up table 457 **/ 458 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 459 u16 vsi_id, bool pf_lut, 460 u8 *lut, u16 lut_size, 461 bool set) 462 { 463 enum i40e_status_code status; 464 struct i40e_aq_desc desc; 465 struct i40e_aqc_get_set_rss_lut *cmd_resp = 466 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 467 468 if (set) 469 i40e_fill_default_direct_cmd_desc(&desc, 470 i40e_aqc_opc_set_rss_lut); 471 else 472 i40e_fill_default_direct_cmd_desc(&desc, 473 i40e_aqc_opc_get_rss_lut); 474 475 /* Indirect command */ 476 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 477 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 478 479 cmd_resp->vsi_id = 480 CPU_TO_LE16((u16)((vsi_id << 481 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 482 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 483 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 484 485 if (pf_lut) 486 cmd_resp->flags |= CPU_TO_LE16((u16) 487 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 488 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 489 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 490 else 491 cmd_resp->flags |= CPU_TO_LE16((u16) 492 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 493 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 494 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 495 496 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 497 498 return status; 499 } 500 501 /** 502 * i40e_aq_get_rss_lut 503 * @hw: pointer to the hardware structure 504 * @vsi_id: vsi fw index 505 * @pf_lut: for PF table set true, for VSI table set false 506 * @lut: pointer to the lut buffer provided by the caller 507 * @lut_size: size of the lut buffer 508 * 509 * get the RSS lookup table, PF or VSI type 510 **/ 511 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 512 bool pf_lut, u8 *lut, u16 lut_size) 513 { 514 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 515 false); 516 } 517 518 /** 519 * i40e_aq_set_rss_lut 520 * @hw: pointer to the hardware structure 521 * @vsi_id: vsi fw index 522 * @pf_lut: for PF table set true, for VSI table set false 523 * @lut: pointer to the lut buffer provided by the caller 524 * @lut_size: size of the lut buffer 525 * 526 * set the RSS lookup table, PF or VSI type 527 **/ 528 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 529 bool pf_lut, u8 *lut, u16 lut_size) 530 { 531 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 532 } 533 534 /** 535 * i40e_aq_get_set_rss_key 536 * @hw: pointer to the hw struct 537 * @vsi_id: vsi fw index 538 * @key: pointer to key info struct 539 * @set: set true to set the key, false to get the key 540 * 541 * get the RSS key per VSI 542 **/ 543 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 544 u16 vsi_id, 545 struct i40e_aqc_get_set_rss_key_data *key, 546 bool set) 547 { 548 enum i40e_status_code status; 549 struct i40e_aq_desc desc; 550 struct i40e_aqc_get_set_rss_key *cmd_resp = 551 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 552 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 553 554 if (set) 555 i40e_fill_default_direct_cmd_desc(&desc, 556 i40e_aqc_opc_set_rss_key); 557 else 558 i40e_fill_default_direct_cmd_desc(&desc, 559 i40e_aqc_opc_get_rss_key); 560 561 /* Indirect command */ 562 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 563 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 564 565 cmd_resp->vsi_id = 566 CPU_TO_LE16((u16)((vsi_id << 567 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 568 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 569 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 570 571 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 572 573 return status; 574 } 575 576 /** 577 * i40e_aq_get_rss_key 578 * @hw: pointer to the hw struct 579 * @vsi_id: vsi fw index 580 * @key: pointer to key info struct 581 * 582 **/ 583 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 584 u16 vsi_id, 585 struct i40e_aqc_get_set_rss_key_data *key) 586 { 587 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 588 } 589 590 /** 591 * i40e_aq_set_rss_key 592 * @hw: pointer to the hw struct 593 * @vsi_id: vsi fw index 594 * @key: pointer to key info struct 595 * 596 * set the RSS key per VSI 597 **/ 598 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 599 u16 vsi_id, 600 struct i40e_aqc_get_set_rss_key_data *key) 601 { 602 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 603 } 604 605 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 606 * hardware to a bit-field that can be used by SW to more easily determine the 607 * packet type. 608 * 609 * Macros are used to shorten the table lines and make this table human 610 * readable. 611 * 612 * We store the PTYPE in the top byte of the bit field - this is just so that 613 * we can check that the table doesn't have a row missing, as the index into 614 * the table should be the PTYPE. 615 * 616 * Typical work flow: 617 * 618 * IF NOT i40e_ptype_lookup[ptype].known 619 * THEN 620 * Packet is unknown 621 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 622 * Use the rest of the fields to look at the tunnels, inner protocols, etc 623 * ELSE 624 * Use the enum i40e_rx_l2_ptype to decode the packet type 625 * ENDIF 626 */ 627 628 /* macro to make the table lines short */ 629 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 630 { PTYPE, \ 631 1, \ 632 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 633 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 634 I40E_RX_PTYPE_##OUTER_FRAG, \ 635 I40E_RX_PTYPE_TUNNEL_##T, \ 636 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 637 I40E_RX_PTYPE_##TEF, \ 638 I40E_RX_PTYPE_INNER_PROT_##I, \ 639 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 640 641 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 642 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 643 644 /* shorter macros makes the table fit but are terse */ 645 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 646 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 647 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 648 649 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 650 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 651 /* L2 Packet types */ 652 I40E_PTT_UNUSED_ENTRY(0), 653 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 654 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 655 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 656 I40E_PTT_UNUSED_ENTRY(4), 657 I40E_PTT_UNUSED_ENTRY(5), 658 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 659 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 660 I40E_PTT_UNUSED_ENTRY(8), 661 I40E_PTT_UNUSED_ENTRY(9), 662 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 663 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 664 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 665 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 666 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 667 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 668 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 669 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 670 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 671 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 672 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 673 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 674 675 /* Non Tunneled IPv4 */ 676 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 677 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 678 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 679 I40E_PTT_UNUSED_ENTRY(25), 680 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 681 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 682 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 683 684 /* IPv4 --> IPv4 */ 685 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 686 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 687 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 688 I40E_PTT_UNUSED_ENTRY(32), 689 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 690 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 691 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 692 693 /* IPv4 --> IPv6 */ 694 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 695 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 696 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 697 I40E_PTT_UNUSED_ENTRY(39), 698 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 699 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 700 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 701 702 /* IPv4 --> GRE/NAT */ 703 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 704 705 /* IPv4 --> GRE/NAT --> IPv4 */ 706 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 707 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 708 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 709 I40E_PTT_UNUSED_ENTRY(47), 710 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 711 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 712 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 713 714 /* IPv4 --> GRE/NAT --> IPv6 */ 715 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 716 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 717 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 718 I40E_PTT_UNUSED_ENTRY(54), 719 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 720 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 721 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 722 723 /* IPv4 --> GRE/NAT --> MAC */ 724 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 725 726 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 727 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 728 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 729 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 730 I40E_PTT_UNUSED_ENTRY(62), 731 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 732 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 733 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 734 735 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 736 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 737 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 738 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 739 I40E_PTT_UNUSED_ENTRY(69), 740 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 741 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 742 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 743 744 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 745 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 746 747 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 748 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 749 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 750 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 751 I40E_PTT_UNUSED_ENTRY(77), 752 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 753 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 754 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 755 756 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 757 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 758 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 759 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 760 I40E_PTT_UNUSED_ENTRY(84), 761 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 762 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 763 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 764 765 /* Non Tunneled IPv6 */ 766 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 767 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 768 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 769 I40E_PTT_UNUSED_ENTRY(91), 770 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 771 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 772 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 773 774 /* IPv6 --> IPv4 */ 775 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 776 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 777 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 778 I40E_PTT_UNUSED_ENTRY(98), 779 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 780 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 781 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 782 783 /* IPv6 --> IPv6 */ 784 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 785 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 786 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 787 I40E_PTT_UNUSED_ENTRY(105), 788 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 789 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 790 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 791 792 /* IPv6 --> GRE/NAT */ 793 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 794 795 /* IPv6 --> GRE/NAT -> IPv4 */ 796 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 797 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 798 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 799 I40E_PTT_UNUSED_ENTRY(113), 800 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 801 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 802 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 803 804 /* IPv6 --> GRE/NAT -> IPv6 */ 805 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 806 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 807 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 808 I40E_PTT_UNUSED_ENTRY(120), 809 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 810 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 811 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 812 813 /* IPv6 --> GRE/NAT -> MAC */ 814 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 815 816 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 817 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 818 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 819 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 820 I40E_PTT_UNUSED_ENTRY(128), 821 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 822 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 823 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 824 825 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 826 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 827 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 828 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 829 I40E_PTT_UNUSED_ENTRY(135), 830 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 831 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 832 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 833 834 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 835 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 836 837 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 838 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 839 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 840 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 841 I40E_PTT_UNUSED_ENTRY(143), 842 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 843 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 844 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 845 846 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 847 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 848 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 849 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 850 I40E_PTT_UNUSED_ENTRY(150), 851 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 852 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 853 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 854 855 /* unused entries */ 856 I40E_PTT_UNUSED_ENTRY(154), 857 I40E_PTT_UNUSED_ENTRY(155), 858 I40E_PTT_UNUSED_ENTRY(156), 859 I40E_PTT_UNUSED_ENTRY(157), 860 I40E_PTT_UNUSED_ENTRY(158), 861 I40E_PTT_UNUSED_ENTRY(159), 862 863 I40E_PTT_UNUSED_ENTRY(160), 864 I40E_PTT_UNUSED_ENTRY(161), 865 I40E_PTT_UNUSED_ENTRY(162), 866 I40E_PTT_UNUSED_ENTRY(163), 867 I40E_PTT_UNUSED_ENTRY(164), 868 I40E_PTT_UNUSED_ENTRY(165), 869 I40E_PTT_UNUSED_ENTRY(166), 870 I40E_PTT_UNUSED_ENTRY(167), 871 I40E_PTT_UNUSED_ENTRY(168), 872 I40E_PTT_UNUSED_ENTRY(169), 873 874 I40E_PTT_UNUSED_ENTRY(170), 875 I40E_PTT_UNUSED_ENTRY(171), 876 I40E_PTT_UNUSED_ENTRY(172), 877 I40E_PTT_UNUSED_ENTRY(173), 878 I40E_PTT_UNUSED_ENTRY(174), 879 I40E_PTT_UNUSED_ENTRY(175), 880 I40E_PTT_UNUSED_ENTRY(176), 881 I40E_PTT_UNUSED_ENTRY(177), 882 I40E_PTT_UNUSED_ENTRY(178), 883 I40E_PTT_UNUSED_ENTRY(179), 884 885 I40E_PTT_UNUSED_ENTRY(180), 886 I40E_PTT_UNUSED_ENTRY(181), 887 I40E_PTT_UNUSED_ENTRY(182), 888 I40E_PTT_UNUSED_ENTRY(183), 889 I40E_PTT_UNUSED_ENTRY(184), 890 I40E_PTT_UNUSED_ENTRY(185), 891 I40E_PTT_UNUSED_ENTRY(186), 892 I40E_PTT_UNUSED_ENTRY(187), 893 I40E_PTT_UNUSED_ENTRY(188), 894 I40E_PTT_UNUSED_ENTRY(189), 895 896 I40E_PTT_UNUSED_ENTRY(190), 897 I40E_PTT_UNUSED_ENTRY(191), 898 I40E_PTT_UNUSED_ENTRY(192), 899 I40E_PTT_UNUSED_ENTRY(193), 900 I40E_PTT_UNUSED_ENTRY(194), 901 I40E_PTT_UNUSED_ENTRY(195), 902 I40E_PTT_UNUSED_ENTRY(196), 903 I40E_PTT_UNUSED_ENTRY(197), 904 I40E_PTT_UNUSED_ENTRY(198), 905 I40E_PTT_UNUSED_ENTRY(199), 906 907 I40E_PTT_UNUSED_ENTRY(200), 908 I40E_PTT_UNUSED_ENTRY(201), 909 I40E_PTT_UNUSED_ENTRY(202), 910 I40E_PTT_UNUSED_ENTRY(203), 911 I40E_PTT_UNUSED_ENTRY(204), 912 I40E_PTT_UNUSED_ENTRY(205), 913 I40E_PTT_UNUSED_ENTRY(206), 914 I40E_PTT_UNUSED_ENTRY(207), 915 I40E_PTT_UNUSED_ENTRY(208), 916 I40E_PTT_UNUSED_ENTRY(209), 917 918 I40E_PTT_UNUSED_ENTRY(210), 919 I40E_PTT_UNUSED_ENTRY(211), 920 I40E_PTT_UNUSED_ENTRY(212), 921 I40E_PTT_UNUSED_ENTRY(213), 922 I40E_PTT_UNUSED_ENTRY(214), 923 I40E_PTT_UNUSED_ENTRY(215), 924 I40E_PTT_UNUSED_ENTRY(216), 925 I40E_PTT_UNUSED_ENTRY(217), 926 I40E_PTT_UNUSED_ENTRY(218), 927 I40E_PTT_UNUSED_ENTRY(219), 928 929 I40E_PTT_UNUSED_ENTRY(220), 930 I40E_PTT_UNUSED_ENTRY(221), 931 I40E_PTT_UNUSED_ENTRY(222), 932 I40E_PTT_UNUSED_ENTRY(223), 933 I40E_PTT_UNUSED_ENTRY(224), 934 I40E_PTT_UNUSED_ENTRY(225), 935 I40E_PTT_UNUSED_ENTRY(226), 936 I40E_PTT_UNUSED_ENTRY(227), 937 I40E_PTT_UNUSED_ENTRY(228), 938 I40E_PTT_UNUSED_ENTRY(229), 939 940 I40E_PTT_UNUSED_ENTRY(230), 941 I40E_PTT_UNUSED_ENTRY(231), 942 I40E_PTT_UNUSED_ENTRY(232), 943 I40E_PTT_UNUSED_ENTRY(233), 944 I40E_PTT_UNUSED_ENTRY(234), 945 I40E_PTT_UNUSED_ENTRY(235), 946 I40E_PTT_UNUSED_ENTRY(236), 947 I40E_PTT_UNUSED_ENTRY(237), 948 I40E_PTT_UNUSED_ENTRY(238), 949 I40E_PTT_UNUSED_ENTRY(239), 950 951 I40E_PTT_UNUSED_ENTRY(240), 952 I40E_PTT_UNUSED_ENTRY(241), 953 I40E_PTT_UNUSED_ENTRY(242), 954 I40E_PTT_UNUSED_ENTRY(243), 955 I40E_PTT_UNUSED_ENTRY(244), 956 I40E_PTT_UNUSED_ENTRY(245), 957 I40E_PTT_UNUSED_ENTRY(246), 958 I40E_PTT_UNUSED_ENTRY(247), 959 I40E_PTT_UNUSED_ENTRY(248), 960 I40E_PTT_UNUSED_ENTRY(249), 961 962 I40E_PTT_UNUSED_ENTRY(250), 963 I40E_PTT_UNUSED_ENTRY(251), 964 I40E_PTT_UNUSED_ENTRY(252), 965 I40E_PTT_UNUSED_ENTRY(253), 966 I40E_PTT_UNUSED_ENTRY(254), 967 I40E_PTT_UNUSED_ENTRY(255) 968 }; 969 970 971 /** 972 * i40e_validate_mac_addr - Validate unicast MAC address 973 * @mac_addr: pointer to MAC address 974 * 975 * Tests a MAC address to ensure it is a valid Individual Address 976 **/ 977 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 978 { 979 enum i40e_status_code status = I40E_SUCCESS; 980 981 DEBUGFUNC("i40e_validate_mac_addr"); 982 983 /* Broadcast addresses ARE multicast addresses 984 * Make sure it is not a multicast address 985 * Reject the zero address 986 */ 987 if (I40E_IS_MULTICAST(mac_addr) || 988 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 989 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 990 status = I40E_ERR_INVALID_MAC_ADDR; 991 992 return status; 993 } 994 #ifdef PF_DRIVER 995 996 /** 997 * i40e_init_shared_code - Initialize the shared code 998 * @hw: pointer to hardware structure 999 * 1000 * This assigns the MAC type and PHY code and inits the NVM. 1001 * Does not touch the hardware. This function must be called prior to any 1002 * other function in the shared code. The i40e_hw structure should be 1003 * memset to 0 prior to calling this function. The following fields in 1004 * hw structure should be filled in prior to calling this function: 1005 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 1006 * subsystem_vendor_id, and revision_id 1007 **/ 1008 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 1009 { 1010 enum i40e_status_code status = I40E_SUCCESS; 1011 u32 port, ari, func_rid; 1012 1013 DEBUGFUNC("i40e_init_shared_code"); 1014 1015 i40e_set_mac_type(hw); 1016 1017 switch (hw->mac.type) { 1018 case I40E_MAC_XL710: 1019 case I40E_MAC_X722: 1020 break; 1021 default: 1022 return I40E_ERR_DEVICE_NOT_SUPPORTED; 1023 } 1024 1025 hw->phy.get_link_info = true; 1026 1027 /* Determine port number and PF number*/ 1028 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 1029 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1030 hw->port = (u8)port; 1031 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 1032 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1033 func_rid = rd32(hw, I40E_PF_FUNC_RID); 1034 if (ari) 1035 hw->pf_id = (u8)(func_rid & 0xff); 1036 else 1037 hw->pf_id = (u8)(func_rid & 0x7); 1038 1039 if (hw->mac.type == I40E_MAC_X722) 1040 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 1041 1042 status = i40e_init_nvm(hw); 1043 return status; 1044 } 1045 1046 /** 1047 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1048 * @hw: pointer to the hw struct 1049 * @flags: a return indicator of what addresses were added to the addr store 1050 * @addrs: the requestor's mac addr store 1051 * @cmd_details: pointer to command details structure or NULL 1052 **/ 1053 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1054 u16 *flags, 1055 struct i40e_aqc_mac_address_read_data *addrs, 1056 struct i40e_asq_cmd_details *cmd_details) 1057 { 1058 struct i40e_aq_desc desc; 1059 struct i40e_aqc_mac_address_read *cmd_data = 1060 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1061 enum i40e_status_code status; 1062 1063 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1064 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1065 1066 status = i40e_asq_send_command(hw, &desc, addrs, 1067 sizeof(*addrs), cmd_details); 1068 *flags = LE16_TO_CPU(cmd_data->command_flags); 1069 1070 return status; 1071 } 1072 1073 /** 1074 * i40e_aq_mac_address_write - Change the MAC addresses 1075 * @hw: pointer to the hw struct 1076 * @flags: indicates which MAC to be written 1077 * @mac_addr: address to write 1078 * @cmd_details: pointer to command details structure or NULL 1079 **/ 1080 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1081 u16 flags, u8 *mac_addr, 1082 struct i40e_asq_cmd_details *cmd_details) 1083 { 1084 struct i40e_aq_desc desc; 1085 struct i40e_aqc_mac_address_write *cmd_data = 1086 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1087 enum i40e_status_code status; 1088 1089 i40e_fill_default_direct_cmd_desc(&desc, 1090 i40e_aqc_opc_mac_address_write); 1091 cmd_data->command_flags = CPU_TO_LE16(flags); 1092 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1093 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1094 ((u32)mac_addr[3] << 16) | 1095 ((u32)mac_addr[4] << 8) | 1096 mac_addr[5]); 1097 1098 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1099 1100 return status; 1101 } 1102 1103 /** 1104 * i40e_get_mac_addr - get MAC address 1105 * @hw: pointer to the HW structure 1106 * @mac_addr: pointer to MAC address 1107 * 1108 * Reads the adapter's MAC address from register 1109 **/ 1110 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1111 { 1112 struct i40e_aqc_mac_address_read_data addrs; 1113 enum i40e_status_code status; 1114 u16 flags = 0; 1115 1116 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1117 1118 if (flags & I40E_AQC_LAN_ADDR_VALID) 1119 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1120 I40E_NONDMA_TO_NONDMA); 1121 1122 return status; 1123 } 1124 1125 /** 1126 * i40e_get_port_mac_addr - get Port MAC address 1127 * @hw: pointer to the HW structure 1128 * @mac_addr: pointer to Port MAC address 1129 * 1130 * Reads the adapter's Port MAC address 1131 **/ 1132 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1133 { 1134 struct i40e_aqc_mac_address_read_data addrs; 1135 enum i40e_status_code status; 1136 u16 flags = 0; 1137 1138 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1139 if (status) 1140 return status; 1141 1142 if (flags & I40E_AQC_PORT_ADDR_VALID) 1143 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1144 I40E_NONDMA_TO_NONDMA); 1145 else 1146 status = I40E_ERR_INVALID_MAC_ADDR; 1147 1148 return status; 1149 } 1150 1151 /** 1152 * i40e_pre_tx_queue_cfg - pre tx queue configure 1153 * @hw: pointer to the HW structure 1154 * @queue: target pf queue index 1155 * @enable: state change request 1156 * 1157 * Handles hw requirement to indicate intention to enable 1158 * or disable target queue. 1159 **/ 1160 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1161 { 1162 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1163 u32 reg_block = 0; 1164 u32 reg_val; 1165 1166 if (abs_queue_idx >= 128) { 1167 reg_block = abs_queue_idx / 128; 1168 abs_queue_idx %= 128; 1169 } 1170 1171 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1172 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1173 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1174 1175 if (enable) 1176 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1177 else 1178 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1179 1180 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1181 } 1182 1183 /** 1184 * i40e_get_san_mac_addr - get SAN MAC address 1185 * @hw: pointer to the HW structure 1186 * @mac_addr: pointer to SAN MAC address 1187 * 1188 * Reads the adapter's SAN MAC address from NVM 1189 **/ 1190 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw, 1191 u8 *mac_addr) 1192 { 1193 struct i40e_aqc_mac_address_read_data addrs; 1194 enum i40e_status_code status; 1195 u16 flags = 0; 1196 1197 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1198 if (status) 1199 return status; 1200 1201 if (flags & I40E_AQC_SAN_ADDR_VALID) 1202 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac), 1203 I40E_NONDMA_TO_NONDMA); 1204 else 1205 status = I40E_ERR_INVALID_MAC_ADDR; 1206 1207 return status; 1208 } 1209 1210 /** 1211 * i40e_read_pba_string - Reads part number string from EEPROM 1212 * @hw: pointer to hardware structure 1213 * @pba_num: stores the part number string from the EEPROM 1214 * @pba_num_size: part number string buffer length 1215 * 1216 * Reads the part number string from the EEPROM. 1217 **/ 1218 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1219 u32 pba_num_size) 1220 { 1221 enum i40e_status_code status = I40E_SUCCESS; 1222 u16 pba_word = 0; 1223 u16 pba_size = 0; 1224 u16 pba_ptr = 0; 1225 u16 i = 0; 1226 1227 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1228 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1229 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1230 return status; 1231 } 1232 1233 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1234 if (status != I40E_SUCCESS) { 1235 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1236 return status; 1237 } 1238 1239 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1240 if (status != I40E_SUCCESS) { 1241 DEBUGOUT("Failed to read PBA Block size.\n"); 1242 return status; 1243 } 1244 1245 /* Subtract one to get PBA word count (PBA Size word is included in 1246 * total size) 1247 */ 1248 pba_size--; 1249 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1250 DEBUGOUT("Buffer to small for PBA data.\n"); 1251 return I40E_ERR_PARAM; 1252 } 1253 1254 for (i = 0; i < pba_size; i++) { 1255 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1256 if (status != I40E_SUCCESS) { 1257 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1258 return status; 1259 } 1260 1261 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1262 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1263 } 1264 pba_num[(pba_size * 2)] = '\0'; 1265 1266 return status; 1267 } 1268 1269 /** 1270 * i40e_get_media_type - Gets media type 1271 * @hw: pointer to the hardware structure 1272 **/ 1273 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1274 { 1275 enum i40e_media_type media; 1276 1277 switch (hw->phy.link_info.phy_type) { 1278 case I40E_PHY_TYPE_10GBASE_SR: 1279 case I40E_PHY_TYPE_10GBASE_LR: 1280 case I40E_PHY_TYPE_1000BASE_SX: 1281 case I40E_PHY_TYPE_1000BASE_LX: 1282 case I40E_PHY_TYPE_40GBASE_SR4: 1283 case I40E_PHY_TYPE_40GBASE_LR4: 1284 case I40E_PHY_TYPE_25GBASE_LR: 1285 case I40E_PHY_TYPE_25GBASE_SR: 1286 media = I40E_MEDIA_TYPE_FIBER; 1287 break; 1288 case I40E_PHY_TYPE_100BASE_TX: 1289 case I40E_PHY_TYPE_1000BASE_T: 1290 case I40E_PHY_TYPE_10GBASE_T: 1291 media = I40E_MEDIA_TYPE_BASET; 1292 break; 1293 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1294 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1295 case I40E_PHY_TYPE_10GBASE_CR1: 1296 case I40E_PHY_TYPE_40GBASE_CR4: 1297 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1298 case I40E_PHY_TYPE_40GBASE_AOC: 1299 case I40E_PHY_TYPE_10GBASE_AOC: 1300 case I40E_PHY_TYPE_25GBASE_CR: 1301 case I40E_PHY_TYPE_25GBASE_AOC: 1302 case I40E_PHY_TYPE_25GBASE_ACC: 1303 media = I40E_MEDIA_TYPE_DA; 1304 break; 1305 case I40E_PHY_TYPE_1000BASE_KX: 1306 case I40E_PHY_TYPE_10GBASE_KX4: 1307 case I40E_PHY_TYPE_10GBASE_KR: 1308 case I40E_PHY_TYPE_40GBASE_KR4: 1309 case I40E_PHY_TYPE_20GBASE_KR2: 1310 case I40E_PHY_TYPE_25GBASE_KR: 1311 media = I40E_MEDIA_TYPE_BACKPLANE; 1312 break; 1313 case I40E_PHY_TYPE_SGMII: 1314 case I40E_PHY_TYPE_XAUI: 1315 case I40E_PHY_TYPE_XFI: 1316 case I40E_PHY_TYPE_XLAUI: 1317 case I40E_PHY_TYPE_XLPPI: 1318 default: 1319 media = I40E_MEDIA_TYPE_UNKNOWN; 1320 break; 1321 } 1322 1323 return media; 1324 } 1325 1326 #define I40E_PF_RESET_WAIT_COUNT 200 1327 /** 1328 * i40e_pf_reset - Reset the PF 1329 * @hw: pointer to the hardware structure 1330 * 1331 * Assuming someone else has triggered a global reset, 1332 * assure the global reset is complete and then reset the PF 1333 **/ 1334 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1335 { 1336 u32 cnt = 0; 1337 u32 cnt1 = 0; 1338 u32 reg = 0; 1339 u32 grst_del; 1340 1341 /* Poll for Global Reset steady state in case of recent GRST. 1342 * The grst delay value is in 100ms units, and we'll wait a 1343 * couple counts longer to be sure we don't just miss the end. 1344 */ 1345 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1346 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1347 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1348 1349 grst_del = grst_del * 20; 1350 1351 for (cnt = 0; cnt < grst_del; cnt++) { 1352 reg = rd32(hw, I40E_GLGEN_RSTAT); 1353 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1354 break; 1355 i40e_msec_delay(100); 1356 } 1357 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1358 DEBUGOUT("Global reset polling failed to complete.\n"); 1359 return I40E_ERR_RESET_FAILED; 1360 } 1361 1362 /* Now Wait for the FW to be ready */ 1363 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1364 reg = rd32(hw, I40E_GLNVM_ULD); 1365 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1366 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1367 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1368 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1369 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1370 break; 1371 } 1372 i40e_msec_delay(10); 1373 } 1374 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1375 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1376 DEBUGOUT("wait for FW Reset complete timedout\n"); 1377 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1378 return I40E_ERR_RESET_FAILED; 1379 } 1380 1381 /* If there was a Global Reset in progress when we got here, 1382 * we don't need to do the PF Reset 1383 */ 1384 if (!cnt) { 1385 u32 reg2 = 0; 1386 1387 reg = rd32(hw, I40E_PFGEN_CTRL); 1388 wr32(hw, I40E_PFGEN_CTRL, 1389 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1390 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1391 reg = rd32(hw, I40E_PFGEN_CTRL); 1392 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1393 break; 1394 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1395 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1396 DEBUGOUT("Core reset upcoming.\n"); 1397 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2); 1398 return I40E_ERR_NOT_READY; 1399 } 1400 i40e_msec_delay(1); 1401 } 1402 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1403 DEBUGOUT("PF reset polling failed to complete.\n"); 1404 return I40E_ERR_RESET_FAILED; 1405 } 1406 } 1407 1408 i40e_clear_pxe_mode(hw); 1409 1410 1411 return I40E_SUCCESS; 1412 } 1413 1414 /** 1415 * i40e_clear_hw - clear out any left over hw state 1416 * @hw: pointer to the hw struct 1417 * 1418 * Clear queues and interrupts, typically called at init time, 1419 * but after the capabilities have been found so we know how many 1420 * queues and msix vectors have been allocated. 1421 **/ 1422 void i40e_clear_hw(struct i40e_hw *hw) 1423 { 1424 u32 num_queues, base_queue; 1425 u32 num_pf_int; 1426 u32 num_vf_int; 1427 u32 num_vfs; 1428 u32 i, j; 1429 u32 val; 1430 u32 eol = 0x7ff; 1431 1432 /* get number of interrupts, queues, and vfs */ 1433 val = rd32(hw, I40E_GLPCI_CNF2); 1434 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1435 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1436 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1437 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1438 1439 val = rd32(hw, I40E_PFLAN_QALLOC); 1440 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1441 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1442 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1443 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1444 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1445 num_queues = (j - base_queue) + 1; 1446 else 1447 num_queues = 0; 1448 1449 val = rd32(hw, I40E_PF_VT_PFALLOC); 1450 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1451 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1452 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1453 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1454 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1455 num_vfs = (j - i) + 1; 1456 else 1457 num_vfs = 0; 1458 1459 /* stop all the interrupts */ 1460 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1461 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1462 for (i = 0; i < num_pf_int - 2; i++) 1463 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1464 1465 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1466 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1467 wr32(hw, I40E_PFINT_LNKLST0, val); 1468 for (i = 0; i < num_pf_int - 2; i++) 1469 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1470 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1471 for (i = 0; i < num_vfs; i++) 1472 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1473 for (i = 0; i < num_vf_int - 2; i++) 1474 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1475 1476 /* warn the HW of the coming Tx disables */ 1477 for (i = 0; i < num_queues; i++) { 1478 u32 abs_queue_idx = base_queue + i; 1479 u32 reg_block = 0; 1480 1481 if (abs_queue_idx >= 128) { 1482 reg_block = abs_queue_idx / 128; 1483 abs_queue_idx %= 128; 1484 } 1485 1486 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1487 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1488 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1489 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1490 1491 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1492 } 1493 i40e_usec_delay(400); 1494 1495 /* stop all the queues */ 1496 for (i = 0; i < num_queues; i++) { 1497 wr32(hw, I40E_QINT_TQCTL(i), 0); 1498 wr32(hw, I40E_QTX_ENA(i), 0); 1499 wr32(hw, I40E_QINT_RQCTL(i), 0); 1500 wr32(hw, I40E_QRX_ENA(i), 0); 1501 } 1502 1503 /* short wait for all queue disables to settle */ 1504 i40e_usec_delay(50); 1505 } 1506 1507 /** 1508 * i40e_clear_pxe_mode - clear pxe operations mode 1509 * @hw: pointer to the hw struct 1510 * 1511 * Make sure all PXE mode settings are cleared, including things 1512 * like descriptor fetch/write-back mode. 1513 **/ 1514 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1515 { 1516 if (i40e_check_asq_alive(hw)) 1517 i40e_aq_clear_pxe_mode(hw, NULL); 1518 } 1519 1520 /** 1521 * i40e_led_is_mine - helper to find matching led 1522 * @hw: pointer to the hw struct 1523 * @idx: index into GPIO registers 1524 * 1525 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1526 */ 1527 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1528 { 1529 u32 gpio_val = 0; 1530 u32 port; 1531 1532 if (!hw->func_caps.led[idx]) 1533 return 0; 1534 1535 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1536 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1537 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1538 1539 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1540 * if it is not our port then ignore 1541 */ 1542 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1543 (port != hw->port)) 1544 return 0; 1545 1546 return gpio_val; 1547 } 1548 1549 #define I40E_COMBINED_ACTIVITY 0xA 1550 #define I40E_FILTER_ACTIVITY 0xE 1551 #define I40E_LINK_ACTIVITY 0xC 1552 #define I40E_MAC_ACTIVITY 0xD 1553 #define I40E_LED0 22 1554 1555 /** 1556 * i40e_led_get - return current on/off mode 1557 * @hw: pointer to the hw struct 1558 * 1559 * The value returned is the 'mode' field as defined in the 1560 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1561 * values are variations of possible behaviors relating to 1562 * blink, link, and wire. 1563 **/ 1564 u32 i40e_led_get(struct i40e_hw *hw) 1565 { 1566 u32 current_mode = 0; 1567 u32 mode = 0; 1568 int i; 1569 1570 /* as per the documentation GPIO 22-29 are the LED 1571 * GPIO pins named LED0..LED7 1572 */ 1573 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1574 u32 gpio_val = i40e_led_is_mine(hw, i); 1575 1576 if (!gpio_val) 1577 continue; 1578 1579 /* ignore gpio LED src mode entries related to the activity 1580 * LEDs 1581 */ 1582 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1583 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1584 switch (current_mode) { 1585 case I40E_COMBINED_ACTIVITY: 1586 case I40E_FILTER_ACTIVITY: 1587 case I40E_MAC_ACTIVITY: 1588 continue; 1589 default: 1590 break; 1591 } 1592 1593 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1594 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1595 break; 1596 } 1597 1598 return mode; 1599 } 1600 1601 /** 1602 * i40e_led_set - set new on/off mode 1603 * @hw: pointer to the hw struct 1604 * @mode: 0=off, 0xf=on (else see manual for mode details) 1605 * @blink: true if the LED should blink when on, false if steady 1606 * 1607 * if this function is used to turn on the blink it should 1608 * be used to disable the blink when restoring the original state. 1609 **/ 1610 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1611 { 1612 u32 current_mode = 0; 1613 int i; 1614 1615 if (mode & 0xfffffff0) 1616 DEBUGOUT1("invalid mode passed in %X\n", mode); 1617 1618 /* as per the documentation GPIO 22-29 are the LED 1619 * GPIO pins named LED0..LED7 1620 */ 1621 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1622 u32 gpio_val = i40e_led_is_mine(hw, i); 1623 1624 if (!gpio_val) 1625 continue; 1626 1627 /* ignore gpio LED src mode entries related to the activity 1628 * LEDs 1629 */ 1630 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1631 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1632 switch (current_mode) { 1633 case I40E_COMBINED_ACTIVITY: 1634 case I40E_FILTER_ACTIVITY: 1635 case I40E_MAC_ACTIVITY: 1636 continue; 1637 default: 1638 break; 1639 } 1640 1641 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1642 /* this & is a bit of paranoia, but serves as a range check */ 1643 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1644 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1645 1646 if (mode == I40E_LINK_ACTIVITY) 1647 blink = false; 1648 1649 if (blink) 1650 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1651 else 1652 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1653 1654 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1655 break; 1656 } 1657 } 1658 1659 /* Admin command wrappers */ 1660 1661 /** 1662 * i40e_aq_get_phy_capabilities 1663 * @hw: pointer to the hw struct 1664 * @abilities: structure for PHY capabilities to be filled 1665 * @qualified_modules: report Qualified Modules 1666 * @report_init: report init capabilities (active are default) 1667 * @cmd_details: pointer to command details structure or NULL 1668 * 1669 * Returns the various PHY abilities supported on the Port. 1670 **/ 1671 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1672 bool qualified_modules, bool report_init, 1673 struct i40e_aq_get_phy_abilities_resp *abilities, 1674 struct i40e_asq_cmd_details *cmd_details) 1675 { 1676 struct i40e_aq_desc desc; 1677 enum i40e_status_code status; 1678 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1679 1680 if (!abilities) 1681 return I40E_ERR_PARAM; 1682 1683 i40e_fill_default_direct_cmd_desc(&desc, 1684 i40e_aqc_opc_get_phy_abilities); 1685 1686 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1687 if (abilities_size > I40E_AQ_LARGE_BUF) 1688 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1689 1690 if (qualified_modules) 1691 desc.params.external.param0 |= 1692 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1693 1694 if (report_init) 1695 desc.params.external.param0 |= 1696 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1697 1698 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1699 cmd_details); 1700 1701 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1702 status = I40E_ERR_UNKNOWN_PHY; 1703 1704 if (report_init) { 1705 if (hw->mac.type == I40E_MAC_XL710 && 1706 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1707 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1708 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1709 } else { 1710 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1711 hw->phy.phy_types |= 1712 ((u64)abilities->phy_type_ext << 32); 1713 } 1714 } 1715 1716 return status; 1717 } 1718 1719 /** 1720 * i40e_aq_set_phy_config 1721 * @hw: pointer to the hw struct 1722 * @config: structure with PHY configuration to be set 1723 * @cmd_details: pointer to command details structure or NULL 1724 * 1725 * Set the various PHY configuration parameters 1726 * supported on the Port.One or more of the Set PHY config parameters may be 1727 * ignored in an MFP mode as the PF may not have the privilege to set some 1728 * of the PHY Config parameters. This status will be indicated by the 1729 * command response. 1730 **/ 1731 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1732 struct i40e_aq_set_phy_config *config, 1733 struct i40e_asq_cmd_details *cmd_details) 1734 { 1735 struct i40e_aq_desc desc; 1736 struct i40e_aq_set_phy_config *cmd = 1737 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1738 enum i40e_status_code status; 1739 1740 if (!config) 1741 return I40E_ERR_PARAM; 1742 1743 i40e_fill_default_direct_cmd_desc(&desc, 1744 i40e_aqc_opc_set_phy_config); 1745 1746 *cmd = *config; 1747 1748 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1749 1750 return status; 1751 } 1752 1753 /** 1754 * i40e_set_fc 1755 * @hw: pointer to the hw struct 1756 * 1757 * Set the requested flow control mode using set_phy_config. 1758 **/ 1759 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1760 bool atomic_restart) 1761 { 1762 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1763 struct i40e_aq_get_phy_abilities_resp abilities; 1764 struct i40e_aq_set_phy_config config; 1765 enum i40e_status_code status; 1766 u8 pause_mask = 0x0; 1767 1768 *aq_failures = 0x0; 1769 1770 switch (fc_mode) { 1771 case I40E_FC_FULL: 1772 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1773 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1774 break; 1775 case I40E_FC_RX_PAUSE: 1776 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1777 break; 1778 case I40E_FC_TX_PAUSE: 1779 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1780 break; 1781 default: 1782 break; 1783 } 1784 1785 /* Get the current phy config */ 1786 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1787 NULL); 1788 if (status) { 1789 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1790 return status; 1791 } 1792 1793 memset(&config, 0, sizeof(config)); 1794 /* clear the old pause settings */ 1795 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1796 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1797 /* set the new abilities */ 1798 config.abilities |= pause_mask; 1799 /* If the abilities have changed, then set the new config */ 1800 if (config.abilities != abilities.abilities) { 1801 /* Auto restart link so settings take effect */ 1802 if (atomic_restart) 1803 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1804 /* Copy over all the old settings */ 1805 config.phy_type = abilities.phy_type; 1806 config.phy_type_ext = abilities.phy_type_ext; 1807 config.link_speed = abilities.link_speed; 1808 config.eee_capability = abilities.eee_capability; 1809 config.eeer = abilities.eeer_val; 1810 config.low_power_ctrl = abilities.d3_lpan; 1811 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1812 I40E_AQ_PHY_FEC_CONFIG_MASK; 1813 status = i40e_aq_set_phy_config(hw, &config, NULL); 1814 1815 if (status) 1816 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1817 } 1818 /* Update the link info */ 1819 status = i40e_update_link_info(hw); 1820 if (status) { 1821 /* Wait a little bit (on 40G cards it sometimes takes a really 1822 * long time for link to come back from the atomic reset) 1823 * and try once more 1824 */ 1825 i40e_msec_delay(1000); 1826 status = i40e_update_link_info(hw); 1827 } 1828 if (status) 1829 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1830 1831 return status; 1832 } 1833 1834 /** 1835 * i40e_aq_set_mac_config 1836 * @hw: pointer to the hw struct 1837 * @max_frame_size: Maximum Frame Size to be supported by the port 1838 * @crc_en: Tell HW to append a CRC to outgoing frames 1839 * @pacing: Pacing configurations 1840 * @cmd_details: pointer to command details structure or NULL 1841 * 1842 * Configure MAC settings for frame size, jumbo frame support and the 1843 * addition of a CRC by the hardware. 1844 **/ 1845 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1846 u16 max_frame_size, 1847 bool crc_en, u16 pacing, 1848 struct i40e_asq_cmd_details *cmd_details) 1849 { 1850 struct i40e_aq_desc desc; 1851 struct i40e_aq_set_mac_config *cmd = 1852 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1853 enum i40e_status_code status; 1854 1855 if (max_frame_size == 0) 1856 return I40E_ERR_PARAM; 1857 1858 i40e_fill_default_direct_cmd_desc(&desc, 1859 i40e_aqc_opc_set_mac_config); 1860 1861 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1862 cmd->params = ((u8)pacing & 0x0F) << 3; 1863 if (crc_en) 1864 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1865 1866 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1867 1868 return status; 1869 } 1870 1871 /** 1872 * i40e_aq_clear_pxe_mode 1873 * @hw: pointer to the hw struct 1874 * @cmd_details: pointer to command details structure or NULL 1875 * 1876 * Tell the firmware that the driver is taking over from PXE 1877 **/ 1878 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1879 struct i40e_asq_cmd_details *cmd_details) 1880 { 1881 enum i40e_status_code status; 1882 struct i40e_aq_desc desc; 1883 struct i40e_aqc_clear_pxe *cmd = 1884 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1885 1886 i40e_fill_default_direct_cmd_desc(&desc, 1887 i40e_aqc_opc_clear_pxe_mode); 1888 1889 cmd->rx_cnt = 0x2; 1890 1891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1892 1893 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1894 1895 return status; 1896 } 1897 1898 /** 1899 * i40e_aq_set_link_restart_an 1900 * @hw: pointer to the hw struct 1901 * @enable_link: if true: enable link, if false: disable link 1902 * @cmd_details: pointer to command details structure or NULL 1903 * 1904 * Sets up the link and restarts the Auto-Negotiation over the link. 1905 **/ 1906 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1907 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1908 { 1909 struct i40e_aq_desc desc; 1910 struct i40e_aqc_set_link_restart_an *cmd = 1911 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1912 enum i40e_status_code status; 1913 1914 i40e_fill_default_direct_cmd_desc(&desc, 1915 i40e_aqc_opc_set_link_restart_an); 1916 1917 cmd->command = I40E_AQ_PHY_RESTART_AN; 1918 if (enable_link) 1919 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1920 else 1921 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1922 1923 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1924 1925 return status; 1926 } 1927 1928 /** 1929 * i40e_aq_get_link_info 1930 * @hw: pointer to the hw struct 1931 * @enable_lse: enable/disable LinkStatusEvent reporting 1932 * @link: pointer to link status structure - optional 1933 * @cmd_details: pointer to command details structure or NULL 1934 * 1935 * Returns the link status of the adapter. 1936 **/ 1937 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1938 bool enable_lse, struct i40e_link_status *link, 1939 struct i40e_asq_cmd_details *cmd_details) 1940 { 1941 struct i40e_aq_desc desc; 1942 struct i40e_aqc_get_link_status *resp = 1943 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1944 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1945 enum i40e_status_code status; 1946 bool tx_pause, rx_pause; 1947 u16 command_flags; 1948 1949 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1950 1951 if (enable_lse) 1952 command_flags = I40E_AQ_LSE_ENABLE; 1953 else 1954 command_flags = I40E_AQ_LSE_DISABLE; 1955 resp->command_flags = CPU_TO_LE16(command_flags); 1956 1957 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1958 1959 if (status != I40E_SUCCESS) 1960 goto aq_get_link_info_exit; 1961 1962 /* save off old link status information */ 1963 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1964 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1965 1966 /* update link status */ 1967 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1968 hw->phy.media_type = i40e_get_media_type(hw); 1969 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1970 hw_link_info->link_info = resp->link_info; 1971 hw_link_info->an_info = resp->an_info; 1972 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1973 I40E_AQ_CONFIG_FEC_RS_ENA); 1974 hw_link_info->ext_info = resp->ext_info; 1975 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1976 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1977 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1978 1979 /* update fc info */ 1980 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1981 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1982 if (tx_pause & rx_pause) 1983 hw->fc.current_mode = I40E_FC_FULL; 1984 else if (tx_pause) 1985 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1986 else if (rx_pause) 1987 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1988 else 1989 hw->fc.current_mode = I40E_FC_NONE; 1990 1991 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1992 hw_link_info->crc_enable = true; 1993 else 1994 hw_link_info->crc_enable = false; 1995 1996 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 1997 hw_link_info->lse_enable = true; 1998 else 1999 hw_link_info->lse_enable = false; 2000 2001 if ((hw->mac.type == I40E_MAC_XL710) && 2002 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 2003 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 2004 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 2005 2006 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 2007 hw->aq.api_min_ver >= 7) { 2008 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type); 2009 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 2010 } 2011 2012 /* save link status information */ 2013 if (link) 2014 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 2015 I40E_NONDMA_TO_NONDMA); 2016 2017 /* flag cleared so helper functions don't call AQ again */ 2018 hw->phy.get_link_info = false; 2019 2020 aq_get_link_info_exit: 2021 return status; 2022 } 2023 2024 /** 2025 * i40e_aq_set_phy_int_mask 2026 * @hw: pointer to the hw struct 2027 * @mask: interrupt mask to be set 2028 * @cmd_details: pointer to command details structure or NULL 2029 * 2030 * Set link interrupt mask. 2031 **/ 2032 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 2033 u16 mask, 2034 struct i40e_asq_cmd_details *cmd_details) 2035 { 2036 struct i40e_aq_desc desc; 2037 struct i40e_aqc_set_phy_int_mask *cmd = 2038 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 2039 enum i40e_status_code status; 2040 2041 i40e_fill_default_direct_cmd_desc(&desc, 2042 i40e_aqc_opc_set_phy_int_mask); 2043 2044 cmd->event_mask = CPU_TO_LE16(mask); 2045 2046 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2047 2048 return status; 2049 } 2050 2051 /** 2052 * i40e_aq_get_local_advt_reg 2053 * @hw: pointer to the hw struct 2054 * @advt_reg: local AN advertisement register value 2055 * @cmd_details: pointer to command details structure or NULL 2056 * 2057 * Get the Local AN advertisement register value. 2058 **/ 2059 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 2060 u64 *advt_reg, 2061 struct i40e_asq_cmd_details *cmd_details) 2062 { 2063 struct i40e_aq_desc desc; 2064 struct i40e_aqc_an_advt_reg *resp = 2065 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2066 enum i40e_status_code status; 2067 2068 i40e_fill_default_direct_cmd_desc(&desc, 2069 i40e_aqc_opc_get_local_advt_reg); 2070 2071 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2072 2073 if (status != I40E_SUCCESS) 2074 goto aq_get_local_advt_reg_exit; 2075 2076 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2077 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2078 2079 aq_get_local_advt_reg_exit: 2080 return status; 2081 } 2082 2083 /** 2084 * i40e_aq_set_local_advt_reg 2085 * @hw: pointer to the hw struct 2086 * @advt_reg: local AN advertisement register value 2087 * @cmd_details: pointer to command details structure or NULL 2088 * 2089 * Get the Local AN advertisement register value. 2090 **/ 2091 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2092 u64 advt_reg, 2093 struct i40e_asq_cmd_details *cmd_details) 2094 { 2095 struct i40e_aq_desc desc; 2096 struct i40e_aqc_an_advt_reg *cmd = 2097 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2098 enum i40e_status_code status; 2099 2100 i40e_fill_default_direct_cmd_desc(&desc, 2101 i40e_aqc_opc_get_local_advt_reg); 2102 2103 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2104 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2105 2106 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2107 2108 return status; 2109 } 2110 2111 /** 2112 * i40e_aq_get_partner_advt 2113 * @hw: pointer to the hw struct 2114 * @advt_reg: AN partner advertisement register value 2115 * @cmd_details: pointer to command details structure or NULL 2116 * 2117 * Get the link partner AN advertisement register value. 2118 **/ 2119 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2120 u64 *advt_reg, 2121 struct i40e_asq_cmd_details *cmd_details) 2122 { 2123 struct i40e_aq_desc desc; 2124 struct i40e_aqc_an_advt_reg *resp = 2125 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2126 enum i40e_status_code status; 2127 2128 i40e_fill_default_direct_cmd_desc(&desc, 2129 i40e_aqc_opc_get_partner_advt); 2130 2131 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2132 2133 if (status != I40E_SUCCESS) 2134 goto aq_get_partner_advt_exit; 2135 2136 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2137 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2138 2139 aq_get_partner_advt_exit: 2140 return status; 2141 } 2142 2143 /** 2144 * i40e_aq_set_lb_modes 2145 * @hw: pointer to the hw struct 2146 * @lb_modes: loopback mode to be set 2147 * @cmd_details: pointer to command details structure or NULL 2148 * 2149 * Sets loopback modes. 2150 **/ 2151 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 2152 u16 lb_modes, 2153 struct i40e_asq_cmd_details *cmd_details) 2154 { 2155 struct i40e_aq_desc desc; 2156 struct i40e_aqc_set_lb_mode *cmd = 2157 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2158 enum i40e_status_code status; 2159 2160 i40e_fill_default_direct_cmd_desc(&desc, 2161 i40e_aqc_opc_set_lb_modes); 2162 2163 cmd->lb_mode = CPU_TO_LE16(lb_modes); 2164 2165 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2166 2167 return status; 2168 } 2169 2170 /** 2171 * i40e_aq_set_phy_debug 2172 * @hw: pointer to the hw struct 2173 * @cmd_flags: debug command flags 2174 * @cmd_details: pointer to command details structure or NULL 2175 * 2176 * Reset the external PHY. 2177 **/ 2178 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2179 struct i40e_asq_cmd_details *cmd_details) 2180 { 2181 struct i40e_aq_desc desc; 2182 struct i40e_aqc_set_phy_debug *cmd = 2183 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2184 enum i40e_status_code status; 2185 2186 i40e_fill_default_direct_cmd_desc(&desc, 2187 i40e_aqc_opc_set_phy_debug); 2188 2189 cmd->command_flags = cmd_flags; 2190 2191 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2192 2193 return status; 2194 } 2195 2196 /** 2197 * i40e_aq_add_vsi 2198 * @hw: pointer to the hw struct 2199 * @vsi_ctx: pointer to a vsi context struct 2200 * @cmd_details: pointer to command details structure or NULL 2201 * 2202 * Add a VSI context to the hardware. 2203 **/ 2204 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2205 struct i40e_vsi_context *vsi_ctx, 2206 struct i40e_asq_cmd_details *cmd_details) 2207 { 2208 struct i40e_aq_desc desc; 2209 struct i40e_aqc_add_get_update_vsi *cmd = 2210 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2211 struct i40e_aqc_add_get_update_vsi_completion *resp = 2212 (struct i40e_aqc_add_get_update_vsi_completion *) 2213 &desc.params.raw; 2214 enum i40e_status_code status; 2215 2216 i40e_fill_default_direct_cmd_desc(&desc, 2217 i40e_aqc_opc_add_vsi); 2218 2219 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2220 cmd->connection_type = vsi_ctx->connection_type; 2221 cmd->vf_id = vsi_ctx->vf_num; 2222 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2223 2224 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2225 2226 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2227 sizeof(vsi_ctx->info), cmd_details); 2228 2229 if (status != I40E_SUCCESS) 2230 goto aq_add_vsi_exit; 2231 2232 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2233 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2234 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2235 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2236 2237 aq_add_vsi_exit: 2238 return status; 2239 } 2240 2241 /** 2242 * i40e_aq_set_default_vsi 2243 * @hw: pointer to the hw struct 2244 * @seid: vsi number 2245 * @cmd_details: pointer to command details structure or NULL 2246 **/ 2247 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2248 u16 seid, 2249 struct i40e_asq_cmd_details *cmd_details) 2250 { 2251 struct i40e_aq_desc desc; 2252 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2253 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2254 &desc.params.raw; 2255 enum i40e_status_code status; 2256 2257 i40e_fill_default_direct_cmd_desc(&desc, 2258 i40e_aqc_opc_set_vsi_promiscuous_modes); 2259 2260 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2261 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2262 cmd->seid = CPU_TO_LE16(seid); 2263 2264 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2265 2266 return status; 2267 } 2268 2269 /** 2270 * i40e_aq_clear_default_vsi 2271 * @hw: pointer to the hw struct 2272 * @seid: vsi number 2273 * @cmd_details: pointer to command details structure or NULL 2274 **/ 2275 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2276 u16 seid, 2277 struct i40e_asq_cmd_details *cmd_details) 2278 { 2279 struct i40e_aq_desc desc; 2280 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2281 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2282 &desc.params.raw; 2283 enum i40e_status_code status; 2284 2285 i40e_fill_default_direct_cmd_desc(&desc, 2286 i40e_aqc_opc_set_vsi_promiscuous_modes); 2287 2288 cmd->promiscuous_flags = CPU_TO_LE16(0); 2289 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2290 cmd->seid = CPU_TO_LE16(seid); 2291 2292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2293 2294 return status; 2295 } 2296 2297 /** 2298 * i40e_aq_set_vsi_unicast_promiscuous 2299 * @hw: pointer to the hw struct 2300 * @seid: vsi number 2301 * @set: set unicast promiscuous enable/disable 2302 * @cmd_details: pointer to command details structure or NULL 2303 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2304 **/ 2305 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2306 u16 seid, bool set, 2307 struct i40e_asq_cmd_details *cmd_details, 2308 bool rx_only_promisc) 2309 { 2310 struct i40e_aq_desc desc; 2311 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2312 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2313 enum i40e_status_code status; 2314 u16 flags = 0; 2315 2316 i40e_fill_default_direct_cmd_desc(&desc, 2317 i40e_aqc_opc_set_vsi_promiscuous_modes); 2318 2319 if (set) { 2320 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2321 if (rx_only_promisc && 2322 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2323 (hw->aq.api_maj_ver > 1))) 2324 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2325 } 2326 2327 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2328 2329 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2330 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2331 (hw->aq.api_maj_ver > 1)) 2332 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2333 2334 cmd->seid = CPU_TO_LE16(seid); 2335 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2336 2337 return status; 2338 } 2339 2340 /** 2341 * i40e_aq_set_vsi_multicast_promiscuous 2342 * @hw: pointer to the hw struct 2343 * @seid: vsi number 2344 * @set: set multicast promiscuous enable/disable 2345 * @cmd_details: pointer to command details structure or NULL 2346 **/ 2347 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2348 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2349 { 2350 struct i40e_aq_desc desc; 2351 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2352 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2353 enum i40e_status_code status; 2354 u16 flags = 0; 2355 2356 i40e_fill_default_direct_cmd_desc(&desc, 2357 i40e_aqc_opc_set_vsi_promiscuous_modes); 2358 2359 if (set) 2360 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2361 2362 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2363 2364 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2365 2366 cmd->seid = CPU_TO_LE16(seid); 2367 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2368 2369 return status; 2370 } 2371 2372 /** 2373 * i40e_aq_set_vsi_full_promiscuous 2374 * @hw: pointer to the hw struct 2375 * @seid: VSI number 2376 * @set: set promiscuous enable/disable 2377 * @cmd_details: pointer to command details structure or NULL 2378 **/ 2379 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw, 2380 u16 seid, bool set, 2381 struct i40e_asq_cmd_details *cmd_details) 2382 { 2383 struct i40e_aq_desc desc; 2384 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2385 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2386 enum i40e_status_code status; 2387 u16 flags = 0; 2388 2389 i40e_fill_default_direct_cmd_desc(&desc, 2390 i40e_aqc_opc_set_vsi_promiscuous_modes); 2391 2392 if (set) 2393 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST | 2394 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2395 I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2396 2397 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2398 2399 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST | 2400 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2401 I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2402 2403 cmd->seid = CPU_TO_LE16(seid); 2404 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2405 2406 return status; 2407 } 2408 2409 /** 2410 * i40e_aq_set_vsi_mc_promisc_on_vlan 2411 * @hw: pointer to the hw struct 2412 * @seid: vsi number 2413 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2414 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2415 * @cmd_details: pointer to command details structure or NULL 2416 **/ 2417 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2418 u16 seid, bool enable, u16 vid, 2419 struct i40e_asq_cmd_details *cmd_details) 2420 { 2421 struct i40e_aq_desc desc; 2422 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2423 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2424 enum i40e_status_code status; 2425 u16 flags = 0; 2426 2427 i40e_fill_default_direct_cmd_desc(&desc, 2428 i40e_aqc_opc_set_vsi_promiscuous_modes); 2429 2430 if (enable) 2431 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2432 2433 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2434 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2435 cmd->seid = CPU_TO_LE16(seid); 2436 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2437 2438 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2439 2440 return status; 2441 } 2442 2443 /** 2444 * i40e_aq_set_vsi_uc_promisc_on_vlan 2445 * @hw: pointer to the hw struct 2446 * @seid: vsi number 2447 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2448 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2449 * @cmd_details: pointer to command details structure or NULL 2450 **/ 2451 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2452 u16 seid, bool enable, u16 vid, 2453 struct i40e_asq_cmd_details *cmd_details) 2454 { 2455 struct i40e_aq_desc desc; 2456 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2457 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2458 enum i40e_status_code status; 2459 u16 flags = 0; 2460 2461 i40e_fill_default_direct_cmd_desc(&desc, 2462 i40e_aqc_opc_set_vsi_promiscuous_modes); 2463 2464 if (enable) 2465 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2466 2467 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2468 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2469 cmd->seid = CPU_TO_LE16(seid); 2470 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2471 2472 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2473 2474 return status; 2475 } 2476 2477 /** 2478 * i40e_aq_set_vsi_bc_promisc_on_vlan 2479 * @hw: pointer to the hw struct 2480 * @seid: vsi number 2481 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2482 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2483 * @cmd_details: pointer to command details structure or NULL 2484 **/ 2485 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2486 u16 seid, bool enable, u16 vid, 2487 struct i40e_asq_cmd_details *cmd_details) 2488 { 2489 struct i40e_aq_desc desc; 2490 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2491 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2492 enum i40e_status_code status; 2493 u16 flags = 0; 2494 2495 i40e_fill_default_direct_cmd_desc(&desc, 2496 i40e_aqc_opc_set_vsi_promiscuous_modes); 2497 2498 if (enable) 2499 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2500 2501 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2502 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2503 cmd->seid = CPU_TO_LE16(seid); 2504 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2505 2506 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2507 2508 return status; 2509 } 2510 2511 /** 2512 * i40e_aq_set_vsi_broadcast 2513 * @hw: pointer to the hw struct 2514 * @seid: vsi number 2515 * @set_filter: true to set filter, false to clear filter 2516 * @cmd_details: pointer to command details structure or NULL 2517 * 2518 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2519 **/ 2520 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2521 u16 seid, bool set_filter, 2522 struct i40e_asq_cmd_details *cmd_details) 2523 { 2524 struct i40e_aq_desc desc; 2525 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2526 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2527 enum i40e_status_code status; 2528 2529 i40e_fill_default_direct_cmd_desc(&desc, 2530 i40e_aqc_opc_set_vsi_promiscuous_modes); 2531 2532 if (set_filter) 2533 cmd->promiscuous_flags 2534 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2535 else 2536 cmd->promiscuous_flags 2537 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2538 2539 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2540 cmd->seid = CPU_TO_LE16(seid); 2541 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2542 2543 return status; 2544 } 2545 2546 /** 2547 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2548 * @hw: pointer to the hw struct 2549 * @seid: vsi number 2550 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2551 * @cmd_details: pointer to command details structure or NULL 2552 **/ 2553 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2554 u16 seid, bool enable, 2555 struct i40e_asq_cmd_details *cmd_details) 2556 { 2557 struct i40e_aq_desc desc; 2558 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2559 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2560 enum i40e_status_code status; 2561 u16 flags = 0; 2562 2563 i40e_fill_default_direct_cmd_desc(&desc, 2564 i40e_aqc_opc_set_vsi_promiscuous_modes); 2565 if (enable) 2566 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2567 2568 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2569 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2570 cmd->seid = CPU_TO_LE16(seid); 2571 2572 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2573 2574 return status; 2575 } 2576 2577 /** 2578 * i40e_get_vsi_params - get VSI configuration info 2579 * @hw: pointer to the hw struct 2580 * @vsi_ctx: pointer to a vsi context struct 2581 * @cmd_details: pointer to command details structure or NULL 2582 **/ 2583 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2584 struct i40e_vsi_context *vsi_ctx, 2585 struct i40e_asq_cmd_details *cmd_details) 2586 { 2587 struct i40e_aq_desc desc; 2588 struct i40e_aqc_add_get_update_vsi *cmd = 2589 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2590 struct i40e_aqc_add_get_update_vsi_completion *resp = 2591 (struct i40e_aqc_add_get_update_vsi_completion *) 2592 &desc.params.raw; 2593 enum i40e_status_code status; 2594 2595 UNREFERENCED_1PARAMETER(cmd_details); 2596 i40e_fill_default_direct_cmd_desc(&desc, 2597 i40e_aqc_opc_get_vsi_parameters); 2598 2599 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2600 2601 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2602 2603 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2604 sizeof(vsi_ctx->info), NULL); 2605 2606 if (status != I40E_SUCCESS) 2607 goto aq_get_vsi_params_exit; 2608 2609 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2610 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2611 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2612 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2613 2614 aq_get_vsi_params_exit: 2615 return status; 2616 } 2617 2618 /** 2619 * i40e_aq_update_vsi_params 2620 * @hw: pointer to the hw struct 2621 * @vsi_ctx: pointer to a vsi context struct 2622 * @cmd_details: pointer to command details structure or NULL 2623 * 2624 * Update a VSI context. 2625 **/ 2626 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2627 struct i40e_vsi_context *vsi_ctx, 2628 struct i40e_asq_cmd_details *cmd_details) 2629 { 2630 struct i40e_aq_desc desc; 2631 struct i40e_aqc_add_get_update_vsi *cmd = 2632 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2633 struct i40e_aqc_add_get_update_vsi_completion *resp = 2634 (struct i40e_aqc_add_get_update_vsi_completion *) 2635 &desc.params.raw; 2636 enum i40e_status_code status; 2637 2638 i40e_fill_default_direct_cmd_desc(&desc, 2639 i40e_aqc_opc_update_vsi_parameters); 2640 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2641 2642 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2643 2644 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2645 sizeof(vsi_ctx->info), cmd_details); 2646 2647 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2648 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2649 2650 return status; 2651 } 2652 2653 /** 2654 * i40e_aq_get_switch_config 2655 * @hw: pointer to the hardware structure 2656 * @buf: pointer to the result buffer 2657 * @buf_size: length of input buffer 2658 * @start_seid: seid to start for the report, 0 == beginning 2659 * @cmd_details: pointer to command details structure or NULL 2660 * 2661 * Fill the buf with switch configuration returned from AdminQ command 2662 **/ 2663 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2664 struct i40e_aqc_get_switch_config_resp *buf, 2665 u16 buf_size, u16 *start_seid, 2666 struct i40e_asq_cmd_details *cmd_details) 2667 { 2668 struct i40e_aq_desc desc; 2669 struct i40e_aqc_switch_seid *scfg = 2670 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2671 enum i40e_status_code status; 2672 2673 i40e_fill_default_direct_cmd_desc(&desc, 2674 i40e_aqc_opc_get_switch_config); 2675 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2676 if (buf_size > I40E_AQ_LARGE_BUF) 2677 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2678 scfg->seid = CPU_TO_LE16(*start_seid); 2679 2680 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2681 *start_seid = LE16_TO_CPU(scfg->seid); 2682 2683 return status; 2684 } 2685 2686 /** 2687 * i40e_aq_set_switch_config 2688 * @hw: pointer to the hardware structure 2689 * @flags: bit flag values to set 2690 * @valid_flags: which bit flags to set 2691 * @cmd_details: pointer to command details structure or NULL 2692 * 2693 * Set switch configuration bits 2694 **/ 2695 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2696 u16 flags, u16 valid_flags, 2697 struct i40e_asq_cmd_details *cmd_details) 2698 { 2699 struct i40e_aq_desc desc; 2700 struct i40e_aqc_set_switch_config *scfg = 2701 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2702 enum i40e_status_code status; 2703 2704 i40e_fill_default_direct_cmd_desc(&desc, 2705 i40e_aqc_opc_set_switch_config); 2706 scfg->flags = CPU_TO_LE16(flags); 2707 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2708 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2709 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag); 2710 scfg->first_tag = CPU_TO_LE16(hw->first_tag); 2711 scfg->second_tag = CPU_TO_LE16(hw->second_tag); 2712 } 2713 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2714 2715 return status; 2716 } 2717 2718 /** 2719 * i40e_aq_get_firmware_version 2720 * @hw: pointer to the hw struct 2721 * @fw_major_version: firmware major version 2722 * @fw_minor_version: firmware minor version 2723 * @fw_build: firmware build number 2724 * @api_major_version: major queue version 2725 * @api_minor_version: minor queue version 2726 * @cmd_details: pointer to command details structure or NULL 2727 * 2728 * Get the firmware version from the admin queue commands 2729 **/ 2730 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2731 u16 *fw_major_version, u16 *fw_minor_version, 2732 u32 *fw_build, 2733 u16 *api_major_version, u16 *api_minor_version, 2734 struct i40e_asq_cmd_details *cmd_details) 2735 { 2736 struct i40e_aq_desc desc; 2737 struct i40e_aqc_get_version *resp = 2738 (struct i40e_aqc_get_version *)&desc.params.raw; 2739 enum i40e_status_code status; 2740 2741 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2742 2743 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2744 2745 if (status == I40E_SUCCESS) { 2746 if (fw_major_version != NULL) 2747 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2748 if (fw_minor_version != NULL) 2749 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2750 if (fw_build != NULL) 2751 *fw_build = LE32_TO_CPU(resp->fw_build); 2752 if (api_major_version != NULL) 2753 *api_major_version = LE16_TO_CPU(resp->api_major); 2754 if (api_minor_version != NULL) 2755 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2756 2757 /* A workaround to fix the API version in SW */ 2758 if (api_major_version && api_minor_version && 2759 fw_major_version && fw_minor_version && 2760 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2761 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2762 (*fw_major_version > 4))) 2763 *api_minor_version = 2; 2764 } 2765 2766 return status; 2767 } 2768 2769 /** 2770 * i40e_aq_send_driver_version 2771 * @hw: pointer to the hw struct 2772 * @dv: driver's major, minor version 2773 * @cmd_details: pointer to command details structure or NULL 2774 * 2775 * Send the driver version to the firmware 2776 **/ 2777 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2778 struct i40e_driver_version *dv, 2779 struct i40e_asq_cmd_details *cmd_details) 2780 { 2781 struct i40e_aq_desc desc; 2782 struct i40e_aqc_driver_version *cmd = 2783 (struct i40e_aqc_driver_version *)&desc.params.raw; 2784 enum i40e_status_code status; 2785 u16 len; 2786 2787 if (dv == NULL) 2788 return I40E_ERR_PARAM; 2789 2790 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2791 2792 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2793 cmd->driver_major_ver = dv->major_version; 2794 cmd->driver_minor_ver = dv->minor_version; 2795 cmd->driver_build_ver = dv->build_version; 2796 cmd->driver_subbuild_ver = dv->subbuild_version; 2797 2798 len = 0; 2799 while (len < sizeof(dv->driver_string) && 2800 (dv->driver_string[len] < 0x80) && 2801 dv->driver_string[len]) 2802 len++; 2803 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2804 len, cmd_details); 2805 2806 return status; 2807 } 2808 2809 /** 2810 * i40e_get_link_status - get status of the HW network link 2811 * @hw: pointer to the hw struct 2812 * @link_up: pointer to bool (true/false = linkup/linkdown) 2813 * 2814 * Variable link_up true if link is up, false if link is down. 2815 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2816 * 2817 * Side effect: LinkStatusEvent reporting becomes enabled 2818 **/ 2819 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2820 { 2821 enum i40e_status_code status = I40E_SUCCESS; 2822 2823 if (hw->phy.get_link_info) { 2824 status = i40e_update_link_info(hw); 2825 2826 if (status != I40E_SUCCESS) 2827 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2828 status); 2829 } 2830 2831 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2832 2833 return status; 2834 } 2835 2836 /** 2837 * i40e_updatelink_status - update status of the HW network link 2838 * @hw: pointer to the hw struct 2839 **/ 2840 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2841 { 2842 struct i40e_aq_get_phy_abilities_resp abilities; 2843 enum i40e_status_code status = I40E_SUCCESS; 2844 2845 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2846 if (status) 2847 return status; 2848 2849 /* extra checking needed to ensure link info to user is timely */ 2850 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2851 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2852 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2853 status = i40e_aq_get_phy_capabilities(hw, false, false, 2854 &abilities, NULL); 2855 if (status) 2856 return status; 2857 2858 hw->phy.link_info.req_fec_info = 2859 abilities.fec_cfg_curr_mod_ext_info & 2860 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2861 2862 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2863 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2864 } 2865 return status; 2866 } 2867 2868 2869 /** 2870 * i40e_get_link_speed 2871 * @hw: pointer to the hw struct 2872 * 2873 * Returns the link speed of the adapter. 2874 **/ 2875 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2876 { 2877 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2878 enum i40e_status_code status = I40E_SUCCESS; 2879 2880 if (hw->phy.get_link_info) { 2881 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2882 2883 if (status != I40E_SUCCESS) 2884 goto i40e_link_speed_exit; 2885 } 2886 2887 speed = hw->phy.link_info.link_speed; 2888 2889 i40e_link_speed_exit: 2890 return speed; 2891 } 2892 2893 /** 2894 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2895 * @hw: pointer to the hw struct 2896 * @uplink_seid: the MAC or other gizmo SEID 2897 * @downlink_seid: the VSI SEID 2898 * @enabled_tc: bitmap of TCs to be enabled 2899 * @default_port: true for default port VSI, false for control port 2900 * @veb_seid: pointer to where to put the resulting VEB SEID 2901 * @enable_stats: true to turn on VEB stats 2902 * @cmd_details: pointer to command details structure or NULL 2903 * 2904 * This asks the FW to add a VEB between the uplink and downlink 2905 * elements. If the uplink SEID is 0, this will be a floating VEB. 2906 **/ 2907 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2908 u16 downlink_seid, u8 enabled_tc, 2909 bool default_port, u16 *veb_seid, 2910 bool enable_stats, 2911 struct i40e_asq_cmd_details *cmd_details) 2912 { 2913 struct i40e_aq_desc desc; 2914 struct i40e_aqc_add_veb *cmd = 2915 (struct i40e_aqc_add_veb *)&desc.params.raw; 2916 struct i40e_aqc_add_veb_completion *resp = 2917 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2918 enum i40e_status_code status; 2919 u16 veb_flags = 0; 2920 2921 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2922 if (!!uplink_seid != !!downlink_seid) 2923 return I40E_ERR_PARAM; 2924 2925 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2926 2927 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2928 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2929 cmd->enable_tcs = enabled_tc; 2930 if (!uplink_seid) 2931 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2932 if (default_port) 2933 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2934 else 2935 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2936 2937 /* reverse logic here: set the bitflag to disable the stats */ 2938 if (!enable_stats) 2939 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2940 2941 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2942 2943 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2944 2945 if (!status && veb_seid) 2946 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2947 2948 return status; 2949 } 2950 2951 /** 2952 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2953 * @hw: pointer to the hw struct 2954 * @veb_seid: the SEID of the VEB to query 2955 * @switch_id: the uplink switch id 2956 * @floating: set to true if the VEB is floating 2957 * @statistic_index: index of the stats counter block for this VEB 2958 * @vebs_used: number of VEB's used by function 2959 * @vebs_free: total VEB's not reserved by any function 2960 * @cmd_details: pointer to command details structure or NULL 2961 * 2962 * This retrieves the parameters for a particular VEB, specified by 2963 * uplink_seid, and returns them to the caller. 2964 **/ 2965 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2966 u16 veb_seid, u16 *switch_id, 2967 bool *floating, u16 *statistic_index, 2968 u16 *vebs_used, u16 *vebs_free, 2969 struct i40e_asq_cmd_details *cmd_details) 2970 { 2971 struct i40e_aq_desc desc; 2972 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2973 (struct i40e_aqc_get_veb_parameters_completion *) 2974 &desc.params.raw; 2975 enum i40e_status_code status; 2976 2977 if (veb_seid == 0) 2978 return I40E_ERR_PARAM; 2979 2980 i40e_fill_default_direct_cmd_desc(&desc, 2981 i40e_aqc_opc_get_veb_parameters); 2982 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2983 2984 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2985 if (status) 2986 goto get_veb_exit; 2987 2988 if (switch_id) 2989 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2990 if (statistic_index) 2991 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2992 if (vebs_used) 2993 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2994 if (vebs_free) 2995 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2996 if (floating) { 2997 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2998 2999 if (flags & I40E_AQC_ADD_VEB_FLOATING) 3000 *floating = true; 3001 else 3002 *floating = false; 3003 } 3004 3005 get_veb_exit: 3006 return status; 3007 } 3008 3009 /** 3010 * i40e_aq_add_macvlan 3011 * @hw: pointer to the hw struct 3012 * @seid: VSI for the mac address 3013 * @mv_list: list of macvlans to be added 3014 * @count: length of the list 3015 * @cmd_details: pointer to command details structure or NULL 3016 * 3017 * Add MAC/VLAN addresses to the HW filtering 3018 **/ 3019 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 3020 struct i40e_aqc_add_macvlan_element_data *mv_list, 3021 u16 count, struct i40e_asq_cmd_details *cmd_details) 3022 { 3023 struct i40e_aq_desc desc; 3024 struct i40e_aqc_macvlan *cmd = 3025 (struct i40e_aqc_macvlan *)&desc.params.raw; 3026 enum i40e_status_code status; 3027 u16 buf_size; 3028 int i; 3029 3030 if (count == 0 || !mv_list || !hw) 3031 return I40E_ERR_PARAM; 3032 3033 buf_size = count * sizeof(*mv_list); 3034 3035 /* prep the rest of the request */ 3036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 3037 cmd->num_addresses = CPU_TO_LE16(count); 3038 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3039 cmd->seid[1] = 0; 3040 cmd->seid[2] = 0; 3041 3042 for (i = 0; i < count; i++) 3043 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 3044 mv_list[i].flags |= 3045 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 3046 3047 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3048 if (buf_size > I40E_AQ_LARGE_BUF) 3049 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3050 3051 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3052 cmd_details); 3053 3054 return status; 3055 } 3056 3057 /** 3058 * i40e_aq_remove_macvlan 3059 * @hw: pointer to the hw struct 3060 * @seid: VSI for the mac address 3061 * @mv_list: list of macvlans to be removed 3062 * @count: length of the list 3063 * @cmd_details: pointer to command details structure or NULL 3064 * 3065 * Remove MAC/VLAN addresses from the HW filtering 3066 **/ 3067 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 3068 struct i40e_aqc_remove_macvlan_element_data *mv_list, 3069 u16 count, struct i40e_asq_cmd_details *cmd_details) 3070 { 3071 struct i40e_aq_desc desc; 3072 struct i40e_aqc_macvlan *cmd = 3073 (struct i40e_aqc_macvlan *)&desc.params.raw; 3074 enum i40e_status_code status; 3075 u16 buf_size; 3076 3077 if (count == 0 || !mv_list || !hw) 3078 return I40E_ERR_PARAM; 3079 3080 buf_size = count * sizeof(*mv_list); 3081 3082 /* prep the rest of the request */ 3083 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 3084 cmd->num_addresses = CPU_TO_LE16(count); 3085 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3086 cmd->seid[1] = 0; 3087 cmd->seid[2] = 0; 3088 3089 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3090 if (buf_size > I40E_AQ_LARGE_BUF) 3091 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3092 3093 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3094 cmd_details); 3095 3096 return status; 3097 } 3098 3099 /** 3100 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 3101 * @hw: pointer to the hw struct 3102 * @opcode: AQ opcode for add or delete mirror rule 3103 * @sw_seid: Switch SEID (to which rule refers) 3104 * @rule_type: Rule Type (ingress/egress/VLAN) 3105 * @id: Destination VSI SEID or Rule ID 3106 * @count: length of the list 3107 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3108 * @cmd_details: pointer to command details structure or NULL 3109 * @rule_id: Rule ID returned from FW 3110 * @rule_used: Number of rules used in internal switch 3111 * @rule_free: Number of rules free in internal switch 3112 * 3113 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 3114 * VEBs/VEPA elements only 3115 **/ 3116 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 3117 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 3118 u16 count, __le16 *mr_list, 3119 struct i40e_asq_cmd_details *cmd_details, 3120 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3121 { 3122 struct i40e_aq_desc desc; 3123 struct i40e_aqc_add_delete_mirror_rule *cmd = 3124 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 3125 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 3126 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 3127 enum i40e_status_code status; 3128 u16 buf_size; 3129 3130 buf_size = count * sizeof(*mr_list); 3131 3132 /* prep the rest of the request */ 3133 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3134 cmd->seid = CPU_TO_LE16(sw_seid); 3135 cmd->rule_type = CPU_TO_LE16(rule_type & 3136 I40E_AQC_MIRROR_RULE_TYPE_MASK); 3137 cmd->num_entries = CPU_TO_LE16(count); 3138 /* Dest VSI for add, rule_id for delete */ 3139 cmd->destination = CPU_TO_LE16(id); 3140 if (mr_list) { 3141 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3142 I40E_AQ_FLAG_RD)); 3143 if (buf_size > I40E_AQ_LARGE_BUF) 3144 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3145 } 3146 3147 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3148 cmd_details); 3149 if (status == I40E_SUCCESS || 3150 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3151 if (rule_id) 3152 *rule_id = LE16_TO_CPU(resp->rule_id); 3153 if (rules_used) 3154 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3155 if (rules_free) 3156 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3157 } 3158 return status; 3159 } 3160 3161 /** 3162 * i40e_aq_add_mirrorrule - add a mirror rule 3163 * @hw: pointer to the hw struct 3164 * @sw_seid: Switch SEID (to which rule refers) 3165 * @rule_type: Rule Type (ingress/egress/VLAN) 3166 * @dest_vsi: SEID of VSI to which packets will be mirrored 3167 * @count: length of the list 3168 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3169 * @cmd_details: pointer to command details structure or NULL 3170 * @rule_id: Rule ID returned from FW 3171 * @rule_used: Number of rules used in internal switch 3172 * @rule_free: Number of rules free in internal switch 3173 * 3174 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3175 **/ 3176 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3177 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3178 struct i40e_asq_cmd_details *cmd_details, 3179 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3180 { 3181 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3182 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3183 if (count == 0 || !mr_list) 3184 return I40E_ERR_PARAM; 3185 } 3186 3187 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3188 rule_type, dest_vsi, count, mr_list, 3189 cmd_details, rule_id, rules_used, rules_free); 3190 } 3191 3192 /** 3193 * i40e_aq_delete_mirrorrule - delete a mirror rule 3194 * @hw: pointer to the hw struct 3195 * @sw_seid: Switch SEID (to which rule refers) 3196 * @rule_type: Rule Type (ingress/egress/VLAN) 3197 * @count: length of the list 3198 * @rule_id: Rule ID that is returned in the receive desc as part of 3199 * add_mirrorrule. 3200 * @mr_list: list of mirrored VLAN IDs to be removed 3201 * @cmd_details: pointer to command details structure or NULL 3202 * @rule_used: Number of rules used in internal switch 3203 * @rule_free: Number of rules free in internal switch 3204 * 3205 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3206 **/ 3207 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3208 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3209 struct i40e_asq_cmd_details *cmd_details, 3210 u16 *rules_used, u16 *rules_free) 3211 { 3212 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3213 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3214 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3215 * mirroring. For other rule_type, count and rule_type should 3216 * not matter. 3217 */ 3218 if (count == 0 || !mr_list) 3219 return I40E_ERR_PARAM; 3220 } 3221 3222 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3223 rule_type, rule_id, count, mr_list, 3224 cmd_details, NULL, rules_used, rules_free); 3225 } 3226 3227 /** 3228 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3229 * @hw: pointer to the hw struct 3230 * @seid: VSI for the vlan filters 3231 * @v_list: list of vlan filters to be added 3232 * @count: length of the list 3233 * @cmd_details: pointer to command details structure or NULL 3234 **/ 3235 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3236 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3237 u8 count, struct i40e_asq_cmd_details *cmd_details) 3238 { 3239 struct i40e_aq_desc desc; 3240 struct i40e_aqc_macvlan *cmd = 3241 (struct i40e_aqc_macvlan *)&desc.params.raw; 3242 enum i40e_status_code status; 3243 u16 buf_size; 3244 3245 if (count == 0 || !v_list || !hw) 3246 return I40E_ERR_PARAM; 3247 3248 buf_size = count * sizeof(*v_list); 3249 3250 /* prep the rest of the request */ 3251 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3252 cmd->num_addresses = CPU_TO_LE16(count); 3253 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3254 cmd->seid[1] = 0; 3255 cmd->seid[2] = 0; 3256 3257 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3258 if (buf_size > I40E_AQ_LARGE_BUF) 3259 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3260 3261 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3262 cmd_details); 3263 3264 return status; 3265 } 3266 3267 /** 3268 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3269 * @hw: pointer to the hw struct 3270 * @seid: VSI for the vlan filters 3271 * @v_list: list of macvlans to be removed 3272 * @count: length of the list 3273 * @cmd_details: pointer to command details structure or NULL 3274 **/ 3275 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3276 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3277 u8 count, struct i40e_asq_cmd_details *cmd_details) 3278 { 3279 struct i40e_aq_desc desc; 3280 struct i40e_aqc_macvlan *cmd = 3281 (struct i40e_aqc_macvlan *)&desc.params.raw; 3282 enum i40e_status_code status; 3283 u16 buf_size; 3284 3285 if (count == 0 || !v_list || !hw) 3286 return I40E_ERR_PARAM; 3287 3288 buf_size = count * sizeof(*v_list); 3289 3290 /* prep the rest of the request */ 3291 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3292 cmd->num_addresses = CPU_TO_LE16(count); 3293 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3294 cmd->seid[1] = 0; 3295 cmd->seid[2] = 0; 3296 3297 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3298 if (buf_size > I40E_AQ_LARGE_BUF) 3299 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3300 3301 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3302 cmd_details); 3303 3304 return status; 3305 } 3306 3307 /** 3308 * i40e_aq_send_msg_to_vf 3309 * @hw: pointer to the hardware structure 3310 * @vfid: vf id to send msg 3311 * @v_opcode: opcodes for VF-PF communication 3312 * @v_retval: return error code 3313 * @msg: pointer to the msg buffer 3314 * @msglen: msg length 3315 * @cmd_details: pointer to command details 3316 * 3317 * send msg to vf 3318 **/ 3319 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3320 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3321 struct i40e_asq_cmd_details *cmd_details) 3322 { 3323 struct i40e_aq_desc desc; 3324 struct i40e_aqc_pf_vf_message *cmd = 3325 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3326 enum i40e_status_code status; 3327 3328 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3329 cmd->id = CPU_TO_LE32(vfid); 3330 desc.cookie_high = CPU_TO_LE32(v_opcode); 3331 desc.cookie_low = CPU_TO_LE32(v_retval); 3332 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3333 if (msglen) { 3334 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3335 I40E_AQ_FLAG_RD)); 3336 if (msglen > I40E_AQ_LARGE_BUF) 3337 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3338 desc.datalen = CPU_TO_LE16(msglen); 3339 } 3340 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3341 3342 return status; 3343 } 3344 3345 /** 3346 * i40e_aq_debug_read_register 3347 * @hw: pointer to the hw struct 3348 * @reg_addr: register address 3349 * @reg_val: register value 3350 * @cmd_details: pointer to command details structure or NULL 3351 * 3352 * Read the register using the admin queue commands 3353 **/ 3354 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3355 u32 reg_addr, u64 *reg_val, 3356 struct i40e_asq_cmd_details *cmd_details) 3357 { 3358 struct i40e_aq_desc desc; 3359 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3360 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3361 enum i40e_status_code status; 3362 3363 if (reg_val == NULL) 3364 return I40E_ERR_PARAM; 3365 3366 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3367 3368 cmd_resp->address = CPU_TO_LE32(reg_addr); 3369 3370 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3371 3372 if (status == I40E_SUCCESS) { 3373 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3374 (u64)LE32_TO_CPU(cmd_resp->value_low); 3375 } 3376 3377 return status; 3378 } 3379 3380 /** 3381 * i40e_aq_debug_write_register 3382 * @hw: pointer to the hw struct 3383 * @reg_addr: register address 3384 * @reg_val: register value 3385 * @cmd_details: pointer to command details structure or NULL 3386 * 3387 * Write to a register using the admin queue commands 3388 **/ 3389 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3390 u32 reg_addr, u64 reg_val, 3391 struct i40e_asq_cmd_details *cmd_details) 3392 { 3393 struct i40e_aq_desc desc; 3394 struct i40e_aqc_debug_reg_read_write *cmd = 3395 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3396 enum i40e_status_code status; 3397 3398 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3399 3400 cmd->address = CPU_TO_LE32(reg_addr); 3401 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3402 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3403 3404 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3405 3406 return status; 3407 } 3408 3409 /** 3410 * i40e_aq_request_resource 3411 * @hw: pointer to the hw struct 3412 * @resource: resource id 3413 * @access: access type 3414 * @sdp_number: resource number 3415 * @timeout: the maximum time in ms that the driver may hold the resource 3416 * @cmd_details: pointer to command details structure or NULL 3417 * 3418 * requests common resource using the admin queue commands 3419 **/ 3420 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3421 enum i40e_aq_resources_ids resource, 3422 enum i40e_aq_resource_access_type access, 3423 u8 sdp_number, u64 *timeout, 3424 struct i40e_asq_cmd_details *cmd_details) 3425 { 3426 struct i40e_aq_desc desc; 3427 struct i40e_aqc_request_resource *cmd_resp = 3428 (struct i40e_aqc_request_resource *)&desc.params.raw; 3429 enum i40e_status_code status; 3430 3431 DEBUGFUNC("i40e_aq_request_resource"); 3432 3433 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3434 3435 cmd_resp->resource_id = CPU_TO_LE16(resource); 3436 cmd_resp->access_type = CPU_TO_LE16(access); 3437 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3438 3439 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3440 /* The completion specifies the maximum time in ms that the driver 3441 * may hold the resource in the Timeout field. 3442 * If the resource is held by someone else, the command completes with 3443 * busy return value and the timeout field indicates the maximum time 3444 * the current owner of the resource has to free it. 3445 */ 3446 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3447 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3448 3449 return status; 3450 } 3451 3452 /** 3453 * i40e_aq_release_resource 3454 * @hw: pointer to the hw struct 3455 * @resource: resource id 3456 * @sdp_number: resource number 3457 * @cmd_details: pointer to command details structure or NULL 3458 * 3459 * release common resource using the admin queue commands 3460 **/ 3461 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3462 enum i40e_aq_resources_ids resource, 3463 u8 sdp_number, 3464 struct i40e_asq_cmd_details *cmd_details) 3465 { 3466 struct i40e_aq_desc desc; 3467 struct i40e_aqc_request_resource *cmd = 3468 (struct i40e_aqc_request_resource *)&desc.params.raw; 3469 enum i40e_status_code status; 3470 3471 DEBUGFUNC("i40e_aq_release_resource"); 3472 3473 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3474 3475 cmd->resource_id = CPU_TO_LE16(resource); 3476 cmd->resource_number = CPU_TO_LE32(sdp_number); 3477 3478 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3479 3480 return status; 3481 } 3482 3483 /** 3484 * i40e_aq_read_nvm 3485 * @hw: pointer to the hw struct 3486 * @module_pointer: module pointer location in words from the NVM beginning 3487 * @offset: byte offset from the module beginning 3488 * @length: length of the section to be read (in bytes from the offset) 3489 * @data: command buffer (size [bytes] = length) 3490 * @last_command: tells if this is the last command in a series 3491 * @cmd_details: pointer to command details structure or NULL 3492 * 3493 * Read the NVM using the admin queue commands 3494 **/ 3495 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3496 u32 offset, u16 length, void *data, 3497 bool last_command, 3498 struct i40e_asq_cmd_details *cmd_details) 3499 { 3500 struct i40e_aq_desc desc; 3501 struct i40e_aqc_nvm_update *cmd = 3502 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3503 enum i40e_status_code status; 3504 3505 DEBUGFUNC("i40e_aq_read_nvm"); 3506 3507 /* In offset the highest byte must be zeroed. */ 3508 if (offset & 0xFF000000) { 3509 status = I40E_ERR_PARAM; 3510 goto i40e_aq_read_nvm_exit; 3511 } 3512 3513 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3514 3515 /* If this is the last command in a series, set the proper flag. */ 3516 if (last_command) 3517 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3518 cmd->module_pointer = module_pointer; 3519 cmd->offset = CPU_TO_LE32(offset); 3520 cmd->length = CPU_TO_LE16(length); 3521 3522 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3523 if (length > I40E_AQ_LARGE_BUF) 3524 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3525 3526 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3527 3528 i40e_aq_read_nvm_exit: 3529 return status; 3530 } 3531 3532 /** 3533 * i40e_aq_read_nvm_config - read an nvm config block 3534 * @hw: pointer to the hw struct 3535 * @cmd_flags: NVM access admin command bits 3536 * @field_id: field or feature id 3537 * @data: buffer for result 3538 * @buf_size: buffer size 3539 * @element_count: pointer to count of elements read by FW 3540 * @cmd_details: pointer to command details structure or NULL 3541 **/ 3542 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3543 u8 cmd_flags, u32 field_id, void *data, 3544 u16 buf_size, u16 *element_count, 3545 struct i40e_asq_cmd_details *cmd_details) 3546 { 3547 struct i40e_aq_desc desc; 3548 struct i40e_aqc_nvm_config_read *cmd = 3549 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3550 enum i40e_status_code status; 3551 3552 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3553 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3554 if (buf_size > I40E_AQ_LARGE_BUF) 3555 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3556 3557 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3558 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3559 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3560 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3561 else 3562 cmd->element_id_msw = 0; 3563 3564 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3565 3566 if (!status && element_count) 3567 *element_count = LE16_TO_CPU(cmd->element_count); 3568 3569 return status; 3570 } 3571 3572 /** 3573 * i40e_aq_write_nvm_config - write an nvm config block 3574 * @hw: pointer to the hw struct 3575 * @cmd_flags: NVM access admin command bits 3576 * @data: buffer for result 3577 * @buf_size: buffer size 3578 * @element_count: count of elements to be written 3579 * @cmd_details: pointer to command details structure or NULL 3580 **/ 3581 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3582 u8 cmd_flags, void *data, u16 buf_size, 3583 u16 element_count, 3584 struct i40e_asq_cmd_details *cmd_details) 3585 { 3586 struct i40e_aq_desc desc; 3587 struct i40e_aqc_nvm_config_write *cmd = 3588 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3589 enum i40e_status_code status; 3590 3591 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3592 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3593 if (buf_size > I40E_AQ_LARGE_BUF) 3594 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3595 3596 cmd->element_count = CPU_TO_LE16(element_count); 3597 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3598 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3599 3600 return status; 3601 } 3602 3603 /** 3604 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3605 * @hw: pointer to the hw struct 3606 * @cmd_details: pointer to command details structure or NULL 3607 **/ 3608 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3609 void *buff, u16 buff_size, 3610 struct i40e_asq_cmd_details *cmd_details) 3611 { 3612 struct i40e_aq_desc desc; 3613 enum i40e_status_code status; 3614 3615 UNREFERENCED_2PARAMETER(buff, buff_size); 3616 3617 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3618 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3619 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3620 status = I40E_ERR_NOT_IMPLEMENTED; 3621 3622 return status; 3623 } 3624 3625 /** 3626 * i40e_aq_erase_nvm 3627 * @hw: pointer to the hw struct 3628 * @module_pointer: module pointer location in words from the NVM beginning 3629 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3630 * @length: length of the section to be erased (expressed in 4 KB) 3631 * @last_command: tells if this is the last command in a series 3632 * @cmd_details: pointer to command details structure or NULL 3633 * 3634 * Erase the NVM sector using the admin queue commands 3635 **/ 3636 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3637 u32 offset, u16 length, bool last_command, 3638 struct i40e_asq_cmd_details *cmd_details) 3639 { 3640 struct i40e_aq_desc desc; 3641 struct i40e_aqc_nvm_update *cmd = 3642 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3643 enum i40e_status_code status; 3644 3645 DEBUGFUNC("i40e_aq_erase_nvm"); 3646 3647 /* In offset the highest byte must be zeroed. */ 3648 if (offset & 0xFF000000) { 3649 status = I40E_ERR_PARAM; 3650 goto i40e_aq_erase_nvm_exit; 3651 } 3652 3653 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3654 3655 /* If this is the last command in a series, set the proper flag. */ 3656 if (last_command) 3657 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3658 cmd->module_pointer = module_pointer; 3659 cmd->offset = CPU_TO_LE32(offset); 3660 cmd->length = CPU_TO_LE16(length); 3661 3662 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3663 3664 i40e_aq_erase_nvm_exit: 3665 return status; 3666 } 3667 3668 /** 3669 * i40e_parse_discover_capabilities 3670 * @hw: pointer to the hw struct 3671 * @buff: pointer to a buffer containing device/function capability records 3672 * @cap_count: number of capability records in the list 3673 * @list_type_opc: type of capabilities list to parse 3674 * 3675 * Parse the device/function capabilities list. 3676 **/ 3677 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3678 u32 cap_count, 3679 enum i40e_admin_queue_opc list_type_opc) 3680 { 3681 struct i40e_aqc_list_capabilities_element_resp *cap; 3682 u32 valid_functions, num_functions; 3683 u32 number, logical_id, phys_id; 3684 struct i40e_hw_capabilities *p; 3685 u8 major_rev; 3686 u32 i = 0; 3687 u16 id; 3688 3689 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3690 3691 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3692 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3693 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3694 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3695 else 3696 return; 3697 3698 for (i = 0; i < cap_count; i++, cap++) { 3699 id = LE16_TO_CPU(cap->id); 3700 number = LE32_TO_CPU(cap->number); 3701 logical_id = LE32_TO_CPU(cap->logical_id); 3702 phys_id = LE32_TO_CPU(cap->phys_id); 3703 major_rev = cap->major_rev; 3704 3705 switch (id) { 3706 case I40E_AQ_CAP_ID_SWITCH_MODE: 3707 p->switch_mode = number; 3708 i40e_debug(hw, I40E_DEBUG_INIT, 3709 "HW Capability: Switch mode = %d\n", 3710 p->switch_mode); 3711 break; 3712 case I40E_AQ_CAP_ID_MNG_MODE: 3713 p->management_mode = number; 3714 if (major_rev > 1) { 3715 p->mng_protocols_over_mctp = logical_id; 3716 i40e_debug(hw, I40E_DEBUG_INIT, 3717 "HW Capability: Protocols over MCTP = %d\n", 3718 p->mng_protocols_over_mctp); 3719 } else { 3720 p->mng_protocols_over_mctp = 0; 3721 } 3722 i40e_debug(hw, I40E_DEBUG_INIT, 3723 "HW Capability: Management Mode = %d\n", 3724 p->management_mode); 3725 break; 3726 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3727 p->npar_enable = number; 3728 i40e_debug(hw, I40E_DEBUG_INIT, 3729 "HW Capability: NPAR enable = %d\n", 3730 p->npar_enable); 3731 break; 3732 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3733 p->os2bmc = number; 3734 i40e_debug(hw, I40E_DEBUG_INIT, 3735 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3736 break; 3737 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3738 p->valid_functions = number; 3739 i40e_debug(hw, I40E_DEBUG_INIT, 3740 "HW Capability: Valid Functions = %d\n", 3741 p->valid_functions); 3742 break; 3743 case I40E_AQ_CAP_ID_SRIOV: 3744 if (number == 1) 3745 p->sr_iov_1_1 = true; 3746 i40e_debug(hw, I40E_DEBUG_INIT, 3747 "HW Capability: SR-IOV = %d\n", 3748 p->sr_iov_1_1); 3749 break; 3750 case I40E_AQ_CAP_ID_VF: 3751 p->num_vfs = number; 3752 p->vf_base_id = logical_id; 3753 i40e_debug(hw, I40E_DEBUG_INIT, 3754 "HW Capability: VF count = %d\n", 3755 p->num_vfs); 3756 i40e_debug(hw, I40E_DEBUG_INIT, 3757 "HW Capability: VF base_id = %d\n", 3758 p->vf_base_id); 3759 break; 3760 case I40E_AQ_CAP_ID_VMDQ: 3761 if (number == 1) 3762 p->vmdq = true; 3763 i40e_debug(hw, I40E_DEBUG_INIT, 3764 "HW Capability: VMDQ = %d\n", p->vmdq); 3765 break; 3766 case I40E_AQ_CAP_ID_8021QBG: 3767 if (number == 1) 3768 p->evb_802_1_qbg = true; 3769 i40e_debug(hw, I40E_DEBUG_INIT, 3770 "HW Capability: 802.1Qbg = %d\n", number); 3771 break; 3772 case I40E_AQ_CAP_ID_8021QBR: 3773 if (number == 1) 3774 p->evb_802_1_qbh = true; 3775 i40e_debug(hw, I40E_DEBUG_INIT, 3776 "HW Capability: 802.1Qbh = %d\n", number); 3777 break; 3778 case I40E_AQ_CAP_ID_VSI: 3779 p->num_vsis = number; 3780 i40e_debug(hw, I40E_DEBUG_INIT, 3781 "HW Capability: VSI count = %d\n", 3782 p->num_vsis); 3783 break; 3784 case I40E_AQ_CAP_ID_DCB: 3785 if (number == 1) { 3786 p->dcb = true; 3787 p->enabled_tcmap = logical_id; 3788 p->maxtc = phys_id; 3789 } 3790 i40e_debug(hw, I40E_DEBUG_INIT, 3791 "HW Capability: DCB = %d\n", p->dcb); 3792 i40e_debug(hw, I40E_DEBUG_INIT, 3793 "HW Capability: TC Mapping = %d\n", 3794 logical_id); 3795 i40e_debug(hw, I40E_DEBUG_INIT, 3796 "HW Capability: TC Max = %d\n", p->maxtc); 3797 break; 3798 case I40E_AQ_CAP_ID_FCOE: 3799 if (number == 1) 3800 p->fcoe = true; 3801 i40e_debug(hw, I40E_DEBUG_INIT, 3802 "HW Capability: FCOE = %d\n", p->fcoe); 3803 break; 3804 case I40E_AQ_CAP_ID_ISCSI: 3805 if (number == 1) 3806 p->iscsi = true; 3807 i40e_debug(hw, I40E_DEBUG_INIT, 3808 "HW Capability: iSCSI = %d\n", p->iscsi); 3809 break; 3810 case I40E_AQ_CAP_ID_RSS: 3811 p->rss = true; 3812 p->rss_table_size = number; 3813 p->rss_table_entry_width = logical_id; 3814 i40e_debug(hw, I40E_DEBUG_INIT, 3815 "HW Capability: RSS = %d\n", p->rss); 3816 i40e_debug(hw, I40E_DEBUG_INIT, 3817 "HW Capability: RSS table size = %d\n", 3818 p->rss_table_size); 3819 i40e_debug(hw, I40E_DEBUG_INIT, 3820 "HW Capability: RSS table width = %d\n", 3821 p->rss_table_entry_width); 3822 break; 3823 case I40E_AQ_CAP_ID_RXQ: 3824 p->num_rx_qp = number; 3825 p->base_queue = phys_id; 3826 i40e_debug(hw, I40E_DEBUG_INIT, 3827 "HW Capability: Rx QP = %d\n", number); 3828 i40e_debug(hw, I40E_DEBUG_INIT, 3829 "HW Capability: base_queue = %d\n", 3830 p->base_queue); 3831 break; 3832 case I40E_AQ_CAP_ID_TXQ: 3833 p->num_tx_qp = number; 3834 p->base_queue = phys_id; 3835 i40e_debug(hw, I40E_DEBUG_INIT, 3836 "HW Capability: Tx QP = %d\n", number); 3837 i40e_debug(hw, I40E_DEBUG_INIT, 3838 "HW Capability: base_queue = %d\n", 3839 p->base_queue); 3840 break; 3841 case I40E_AQ_CAP_ID_MSIX: 3842 p->num_msix_vectors = number; 3843 i40e_debug(hw, I40E_DEBUG_INIT, 3844 "HW Capability: MSIX vector count = %d\n", 3845 p->num_msix_vectors); 3846 break; 3847 case I40E_AQ_CAP_ID_VF_MSIX: 3848 p->num_msix_vectors_vf = number; 3849 i40e_debug(hw, I40E_DEBUG_INIT, 3850 "HW Capability: MSIX VF vector count = %d\n", 3851 p->num_msix_vectors_vf); 3852 break; 3853 case I40E_AQ_CAP_ID_FLEX10: 3854 if (major_rev == 1) { 3855 if (number == 1) { 3856 p->flex10_enable = true; 3857 p->flex10_capable = true; 3858 } 3859 } else { 3860 /* Capability revision >= 2 */ 3861 if (number & 1) 3862 p->flex10_enable = true; 3863 if (number & 2) 3864 p->flex10_capable = true; 3865 } 3866 p->flex10_mode = logical_id; 3867 p->flex10_status = phys_id; 3868 i40e_debug(hw, I40E_DEBUG_INIT, 3869 "HW Capability: Flex10 mode = %d\n", 3870 p->flex10_mode); 3871 i40e_debug(hw, I40E_DEBUG_INIT, 3872 "HW Capability: Flex10 status = %d\n", 3873 p->flex10_status); 3874 break; 3875 case I40E_AQ_CAP_ID_CEM: 3876 if (number == 1) 3877 p->mgmt_cem = true; 3878 i40e_debug(hw, I40E_DEBUG_INIT, 3879 "HW Capability: CEM = %d\n", p->mgmt_cem); 3880 break; 3881 case I40E_AQ_CAP_ID_IWARP: 3882 if (number == 1) 3883 p->iwarp = true; 3884 i40e_debug(hw, I40E_DEBUG_INIT, 3885 "HW Capability: iWARP = %d\n", p->iwarp); 3886 break; 3887 case I40E_AQ_CAP_ID_LED: 3888 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3889 p->led[phys_id] = true; 3890 i40e_debug(hw, I40E_DEBUG_INIT, 3891 "HW Capability: LED - PIN %d\n", phys_id); 3892 break; 3893 case I40E_AQ_CAP_ID_SDP: 3894 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3895 p->sdp[phys_id] = true; 3896 i40e_debug(hw, I40E_DEBUG_INIT, 3897 "HW Capability: SDP - PIN %d\n", phys_id); 3898 break; 3899 case I40E_AQ_CAP_ID_MDIO: 3900 if (number == 1) { 3901 p->mdio_port_num = phys_id; 3902 p->mdio_port_mode = logical_id; 3903 } 3904 i40e_debug(hw, I40E_DEBUG_INIT, 3905 "HW Capability: MDIO port number = %d\n", 3906 p->mdio_port_num); 3907 i40e_debug(hw, I40E_DEBUG_INIT, 3908 "HW Capability: MDIO port mode = %d\n", 3909 p->mdio_port_mode); 3910 break; 3911 case I40E_AQ_CAP_ID_1588: 3912 if (number == 1) 3913 p->ieee_1588 = true; 3914 i40e_debug(hw, I40E_DEBUG_INIT, 3915 "HW Capability: IEEE 1588 = %d\n", 3916 p->ieee_1588); 3917 break; 3918 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3919 p->fd = true; 3920 p->fd_filters_guaranteed = number; 3921 p->fd_filters_best_effort = logical_id; 3922 i40e_debug(hw, I40E_DEBUG_INIT, 3923 "HW Capability: Flow Director = 1\n"); 3924 i40e_debug(hw, I40E_DEBUG_INIT, 3925 "HW Capability: Guaranteed FD filters = %d\n", 3926 p->fd_filters_guaranteed); 3927 break; 3928 case I40E_AQ_CAP_ID_WSR_PROT: 3929 p->wr_csr_prot = (u64)number; 3930 p->wr_csr_prot |= (u64)logical_id << 32; 3931 i40e_debug(hw, I40E_DEBUG_INIT, 3932 "HW Capability: wr_csr_prot = 0x%llX\n\n", 3933 (p->wr_csr_prot & 0xffff)); 3934 break; 3935 case I40E_AQ_CAP_ID_NVM_MGMT: 3936 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3937 p->sec_rev_disabled = true; 3938 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3939 p->update_disabled = true; 3940 break; 3941 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 3942 hw->num_wol_proxy_filters = (u16)number; 3943 hw->wol_proxy_vsi_seid = (u16)logical_id; 3944 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 3945 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 3946 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 3947 else 3948 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 3949 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 3950 i40e_debug(hw, I40E_DEBUG_INIT, 3951 "HW Capability: WOL proxy filters = %d\n", 3952 hw->num_wol_proxy_filters); 3953 break; 3954 default: 3955 break; 3956 } 3957 } 3958 3959 if (p->fcoe) 3960 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3961 3962 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3963 p->fcoe = false; 3964 3965 /* count the enabled ports (aka the "not disabled" ports) */ 3966 hw->num_ports = 0; 3967 for (i = 0; i < 4; i++) { 3968 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3969 u64 port_cfg = 0; 3970 3971 /* use AQ read to get the physical register offset instead 3972 * of the port relative offset 3973 */ 3974 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3975 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3976 hw->num_ports++; 3977 } 3978 3979 valid_functions = p->valid_functions; 3980 num_functions = 0; 3981 while (valid_functions) { 3982 if (valid_functions & 1) 3983 num_functions++; 3984 valid_functions >>= 1; 3985 } 3986 3987 /* partition id is 1-based, and functions are evenly spread 3988 * across the ports as partitions 3989 */ 3990 if (hw->num_ports != 0) { 3991 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3992 hw->num_partitions = num_functions / hw->num_ports; 3993 } 3994 3995 /* additional HW specific goodies that might 3996 * someday be HW version specific 3997 */ 3998 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3999 } 4000 4001 /** 4002 * i40e_aq_discover_capabilities 4003 * @hw: pointer to the hw struct 4004 * @buff: a virtual buffer to hold the capabilities 4005 * @buff_size: Size of the virtual buffer 4006 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 4007 * @list_type_opc: capabilities type to discover - pass in the command opcode 4008 * @cmd_details: pointer to command details structure or NULL 4009 * 4010 * Get the device capabilities descriptions from the firmware 4011 **/ 4012 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 4013 void *buff, u16 buff_size, u16 *data_size, 4014 enum i40e_admin_queue_opc list_type_opc, 4015 struct i40e_asq_cmd_details *cmd_details) 4016 { 4017 struct i40e_aqc_list_capabilites *cmd; 4018 struct i40e_aq_desc desc; 4019 enum i40e_status_code status = I40E_SUCCESS; 4020 4021 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 4022 4023 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 4024 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 4025 status = I40E_ERR_PARAM; 4026 goto exit; 4027 } 4028 4029 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 4030 4031 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4032 if (buff_size > I40E_AQ_LARGE_BUF) 4033 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4034 4035 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4036 *data_size = LE16_TO_CPU(desc.datalen); 4037 4038 if (status) 4039 goto exit; 4040 4041 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 4042 list_type_opc); 4043 4044 exit: 4045 return status; 4046 } 4047 4048 /** 4049 * i40e_aq_update_nvm 4050 * @hw: pointer to the hw struct 4051 * @module_pointer: module pointer location in words from the NVM beginning 4052 * @offset: byte offset from the module beginning 4053 * @length: length of the section to be written (in bytes from the offset) 4054 * @data: command buffer (size [bytes] = length) 4055 * @last_command: tells if this is the last command in a series 4056 * @cmd_details: pointer to command details structure or NULL 4057 * 4058 * Update the NVM using the admin queue commands 4059 **/ 4060 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 4061 u32 offset, u16 length, void *data, 4062 bool last_command, 4063 struct i40e_asq_cmd_details *cmd_details) 4064 { 4065 struct i40e_aq_desc desc; 4066 struct i40e_aqc_nvm_update *cmd = 4067 (struct i40e_aqc_nvm_update *)&desc.params.raw; 4068 enum i40e_status_code status; 4069 4070 DEBUGFUNC("i40e_aq_update_nvm"); 4071 4072 /* In offset the highest byte must be zeroed. */ 4073 if (offset & 0xFF000000) { 4074 status = I40E_ERR_PARAM; 4075 goto i40e_aq_update_nvm_exit; 4076 } 4077 4078 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4079 4080 /* If this is the last command in a series, set the proper flag. */ 4081 if (last_command) 4082 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 4083 cmd->module_pointer = module_pointer; 4084 cmd->offset = CPU_TO_LE32(offset); 4085 cmd->length = CPU_TO_LE16(length); 4086 4087 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4088 if (length > I40E_AQ_LARGE_BUF) 4089 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4090 4091 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 4092 4093 i40e_aq_update_nvm_exit: 4094 return status; 4095 } 4096 4097 /** 4098 * i40e_aq_get_lldp_mib 4099 * @hw: pointer to the hw struct 4100 * @bridge_type: type of bridge requested 4101 * @mib_type: Local, Remote or both Local and Remote MIBs 4102 * @buff: pointer to a user supplied buffer to store the MIB block 4103 * @buff_size: size of the buffer (in bytes) 4104 * @local_len : length of the returned Local LLDP MIB 4105 * @remote_len: length of the returned Remote LLDP MIB 4106 * @cmd_details: pointer to command details structure or NULL 4107 * 4108 * Requests the complete LLDP MIB (entire packet). 4109 **/ 4110 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 4111 u8 mib_type, void *buff, u16 buff_size, 4112 u16 *local_len, u16 *remote_len, 4113 struct i40e_asq_cmd_details *cmd_details) 4114 { 4115 struct i40e_aq_desc desc; 4116 struct i40e_aqc_lldp_get_mib *cmd = 4117 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4118 struct i40e_aqc_lldp_get_mib *resp = 4119 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4120 enum i40e_status_code status; 4121 4122 if (buff_size == 0 || !buff) 4123 return I40E_ERR_PARAM; 4124 4125 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 4126 /* Indirect Command */ 4127 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4128 4129 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 4130 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4131 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4132 4133 desc.datalen = CPU_TO_LE16(buff_size); 4134 4135 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4136 if (buff_size > I40E_AQ_LARGE_BUF) 4137 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4138 4139 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4140 if (!status) { 4141 if (local_len != NULL) 4142 *local_len = LE16_TO_CPU(resp->local_len); 4143 if (remote_len != NULL) 4144 *remote_len = LE16_TO_CPU(resp->remote_len); 4145 } 4146 4147 return status; 4148 } 4149 4150 /** 4151 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4152 * @hw: pointer to the hw struct 4153 * @mib_type: Local, Remote or both Local and Remote MIBs 4154 * @buff: pointer to a user supplied buffer to store the MIB block 4155 * @buff_size: size of the buffer (in bytes) 4156 * @cmd_details: pointer to command details structure or NULL 4157 * 4158 * Set the LLDP MIB. 4159 **/ 4160 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4161 u8 mib_type, void *buff, u16 buff_size, 4162 struct i40e_asq_cmd_details *cmd_details) 4163 { 4164 struct i40e_aq_desc desc; 4165 struct i40e_aqc_lldp_set_local_mib *cmd = 4166 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4167 enum i40e_status_code status; 4168 4169 if (buff_size == 0 || !buff) 4170 return I40E_ERR_PARAM; 4171 4172 i40e_fill_default_direct_cmd_desc(&desc, 4173 i40e_aqc_opc_lldp_set_local_mib); 4174 /* Indirect Command */ 4175 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4176 if (buff_size > I40E_AQ_LARGE_BUF) 4177 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4178 desc.datalen = CPU_TO_LE16(buff_size); 4179 4180 cmd->type = mib_type; 4181 cmd->length = CPU_TO_LE16(buff_size); 4182 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff)); 4183 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff)); 4184 4185 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4186 return status; 4187 } 4188 4189 /** 4190 * i40e_aq_cfg_lldp_mib_change_event 4191 * @hw: pointer to the hw struct 4192 * @enable_update: Enable or Disable event posting 4193 * @cmd_details: pointer to command details structure or NULL 4194 * 4195 * Enable or Disable posting of an event on ARQ when LLDP MIB 4196 * associated with the interface changes 4197 **/ 4198 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4199 bool enable_update, 4200 struct i40e_asq_cmd_details *cmd_details) 4201 { 4202 struct i40e_aq_desc desc; 4203 struct i40e_aqc_lldp_update_mib *cmd = 4204 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4205 enum i40e_status_code status; 4206 4207 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4208 4209 if (!enable_update) 4210 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4211 4212 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4213 4214 return status; 4215 } 4216 4217 /** 4218 * i40e_aq_add_lldp_tlv 4219 * @hw: pointer to the hw struct 4220 * @bridge_type: type of bridge 4221 * @buff: buffer with TLV to add 4222 * @buff_size: length of the buffer 4223 * @tlv_len: length of the TLV to be added 4224 * @mib_len: length of the LLDP MIB returned in response 4225 * @cmd_details: pointer to command details structure or NULL 4226 * 4227 * Add the specified TLV to LLDP Local MIB for the given bridge type, 4228 * it is responsibility of the caller to make sure that the TLV is not 4229 * already present in the LLDPDU. 4230 * In return firmware will write the complete LLDP MIB with the newly 4231 * added TLV in the response buffer. 4232 **/ 4233 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 4234 void *buff, u16 buff_size, u16 tlv_len, 4235 u16 *mib_len, 4236 struct i40e_asq_cmd_details *cmd_details) 4237 { 4238 struct i40e_aq_desc desc; 4239 struct i40e_aqc_lldp_add_tlv *cmd = 4240 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4241 enum i40e_status_code status; 4242 4243 if (buff_size == 0 || !buff || tlv_len == 0) 4244 return I40E_ERR_PARAM; 4245 4246 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 4247 4248 /* Indirect Command */ 4249 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4250 if (buff_size > I40E_AQ_LARGE_BUF) 4251 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4252 desc.datalen = CPU_TO_LE16(buff_size); 4253 4254 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4255 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4256 cmd->len = CPU_TO_LE16(tlv_len); 4257 4258 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4259 if (!status) { 4260 if (mib_len != NULL) 4261 *mib_len = LE16_TO_CPU(desc.datalen); 4262 } 4263 4264 return status; 4265 } 4266 4267 /** 4268 * i40e_aq_update_lldp_tlv 4269 * @hw: pointer to the hw struct 4270 * @bridge_type: type of bridge 4271 * @buff: buffer with TLV to update 4272 * @buff_size: size of the buffer holding original and updated TLVs 4273 * @old_len: Length of the Original TLV 4274 * @new_len: Length of the Updated TLV 4275 * @offset: offset of the updated TLV in the buff 4276 * @mib_len: length of the returned LLDP MIB 4277 * @cmd_details: pointer to command details structure or NULL 4278 * 4279 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 4280 * Firmware will place the complete LLDP MIB in response buffer with the 4281 * updated TLV. 4282 **/ 4283 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 4284 u8 bridge_type, void *buff, u16 buff_size, 4285 u16 old_len, u16 new_len, u16 offset, 4286 u16 *mib_len, 4287 struct i40e_asq_cmd_details *cmd_details) 4288 { 4289 struct i40e_aq_desc desc; 4290 struct i40e_aqc_lldp_update_tlv *cmd = 4291 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 4292 enum i40e_status_code status; 4293 4294 if (buff_size == 0 || !buff || offset == 0 || 4295 old_len == 0 || new_len == 0) 4296 return I40E_ERR_PARAM; 4297 4298 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 4299 4300 /* Indirect Command */ 4301 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4302 if (buff_size > I40E_AQ_LARGE_BUF) 4303 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4304 desc.datalen = CPU_TO_LE16(buff_size); 4305 4306 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4307 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4308 cmd->old_len = CPU_TO_LE16(old_len); 4309 cmd->new_offset = CPU_TO_LE16(offset); 4310 cmd->new_len = CPU_TO_LE16(new_len); 4311 4312 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4313 if (!status) { 4314 if (mib_len != NULL) 4315 *mib_len = LE16_TO_CPU(desc.datalen); 4316 } 4317 4318 return status; 4319 } 4320 4321 /** 4322 * i40e_aq_delete_lldp_tlv 4323 * @hw: pointer to the hw struct 4324 * @bridge_type: type of bridge 4325 * @buff: pointer to a user supplied buffer that has the TLV 4326 * @buff_size: length of the buffer 4327 * @tlv_len: length of the TLV to be deleted 4328 * @mib_len: length of the returned LLDP MIB 4329 * @cmd_details: pointer to command details structure or NULL 4330 * 4331 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 4332 * The firmware places the entire LLDP MIB in the response buffer. 4333 **/ 4334 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 4335 u8 bridge_type, void *buff, u16 buff_size, 4336 u16 tlv_len, u16 *mib_len, 4337 struct i40e_asq_cmd_details *cmd_details) 4338 { 4339 struct i40e_aq_desc desc; 4340 struct i40e_aqc_lldp_add_tlv *cmd = 4341 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4342 enum i40e_status_code status; 4343 4344 if (buff_size == 0 || !buff) 4345 return I40E_ERR_PARAM; 4346 4347 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 4348 4349 /* Indirect Command */ 4350 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4351 if (buff_size > I40E_AQ_LARGE_BUF) 4352 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4353 desc.datalen = CPU_TO_LE16(buff_size); 4354 cmd->len = CPU_TO_LE16(tlv_len); 4355 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4356 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4357 4358 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4359 if (!status) { 4360 if (mib_len != NULL) 4361 *mib_len = LE16_TO_CPU(desc.datalen); 4362 } 4363 4364 return status; 4365 } 4366 4367 /** 4368 * i40e_aq_stop_lldp 4369 * @hw: pointer to the hw struct 4370 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4371 * @cmd_details: pointer to command details structure or NULL 4372 * 4373 * Stop or Shutdown the embedded LLDP Agent 4374 **/ 4375 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4376 struct i40e_asq_cmd_details *cmd_details) 4377 { 4378 struct i40e_aq_desc desc; 4379 struct i40e_aqc_lldp_stop *cmd = 4380 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4381 enum i40e_status_code status; 4382 4383 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4384 4385 if (shutdown_agent) 4386 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4387 4388 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4389 4390 return status; 4391 } 4392 4393 /** 4394 * i40e_aq_start_lldp 4395 * @hw: pointer to the hw struct 4396 * @cmd_details: pointer to command details structure or NULL 4397 * 4398 * Start the embedded LLDP Agent on all ports. 4399 **/ 4400 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4401 struct i40e_asq_cmd_details *cmd_details) 4402 { 4403 struct i40e_aq_desc desc; 4404 struct i40e_aqc_lldp_start *cmd = 4405 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4406 enum i40e_status_code status; 4407 4408 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4409 4410 cmd->command = I40E_AQ_LLDP_AGENT_START; 4411 4412 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4413 4414 return status; 4415 } 4416 4417 /** 4418 * i40e_aq_get_cee_dcb_config 4419 * @hw: pointer to the hw struct 4420 * @buff: response buffer that stores CEE operational configuration 4421 * @buff_size: size of the buffer passed 4422 * @cmd_details: pointer to command details structure or NULL 4423 * 4424 * Get CEE DCBX mode operational configuration from firmware 4425 **/ 4426 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4427 void *buff, u16 buff_size, 4428 struct i40e_asq_cmd_details *cmd_details) 4429 { 4430 struct i40e_aq_desc desc; 4431 enum i40e_status_code status; 4432 4433 if (buff_size == 0 || !buff) 4434 return I40E_ERR_PARAM; 4435 4436 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4437 4438 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4439 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4440 cmd_details); 4441 4442 return status; 4443 } 4444 4445 /** 4446 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4447 * @hw: pointer to the hw struct 4448 * @start_agent: True if DCBx Agent needs to be Started 4449 * False if DCBx Agent needs to be Stopped 4450 * @cmd_details: pointer to command details structure or NULL 4451 * 4452 * Start/Stop the embedded dcbx Agent 4453 **/ 4454 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4455 bool start_agent, 4456 struct i40e_asq_cmd_details *cmd_details) 4457 { 4458 struct i40e_aq_desc desc; 4459 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4460 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4461 &desc.params.raw; 4462 enum i40e_status_code status; 4463 4464 i40e_fill_default_direct_cmd_desc(&desc, 4465 i40e_aqc_opc_lldp_stop_start_spec_agent); 4466 4467 if (start_agent) 4468 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4469 4470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4471 4472 return status; 4473 } 4474 4475 /** 4476 * i40e_aq_add_udp_tunnel 4477 * @hw: pointer to the hw struct 4478 * @udp_port: the UDP port to add in Host byte order 4479 * @header_len: length of the tunneling header length in DWords 4480 * @protocol_index: protocol index type 4481 * @filter_index: pointer to filter index 4482 * @cmd_details: pointer to command details structure or NULL 4483 * 4484 * Note: Firmware expects the udp_port value to be in Little Endian format, 4485 * and this function will call CPU_TO_LE16 to convert from Host byte order to 4486 * Little Endian order. 4487 **/ 4488 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4489 u16 udp_port, u8 protocol_index, 4490 u8 *filter_index, 4491 struct i40e_asq_cmd_details *cmd_details) 4492 { 4493 struct i40e_aq_desc desc; 4494 struct i40e_aqc_add_udp_tunnel *cmd = 4495 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4496 struct i40e_aqc_del_udp_tunnel_completion *resp = 4497 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4498 enum i40e_status_code status; 4499 4500 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4501 4502 cmd->udp_port = CPU_TO_LE16(udp_port); 4503 cmd->protocol_type = protocol_index; 4504 4505 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4506 4507 if (!status && filter_index) 4508 *filter_index = resp->index; 4509 4510 return status; 4511 } 4512 4513 /** 4514 * i40e_aq_del_udp_tunnel 4515 * @hw: pointer to the hw struct 4516 * @index: filter index 4517 * @cmd_details: pointer to command details structure or NULL 4518 **/ 4519 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4520 struct i40e_asq_cmd_details *cmd_details) 4521 { 4522 struct i40e_aq_desc desc; 4523 struct i40e_aqc_remove_udp_tunnel *cmd = 4524 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4525 enum i40e_status_code status; 4526 4527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4528 4529 cmd->index = index; 4530 4531 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4532 4533 return status; 4534 } 4535 4536 /** 4537 * i40e_aq_get_switch_resource_alloc (0x0204) 4538 * @hw: pointer to the hw struct 4539 * @num_entries: pointer to u8 to store the number of resource entries returned 4540 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4541 * to store the resource information for all resource types. Each 4542 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4543 * @count: size, in bytes, of the buffer provided 4544 * @cmd_details: pointer to command details structure or NULL 4545 * 4546 * Query the resources allocated to a function. 4547 **/ 4548 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4549 u8 *num_entries, 4550 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4551 u16 count, 4552 struct i40e_asq_cmd_details *cmd_details) 4553 { 4554 struct i40e_aq_desc desc; 4555 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4556 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4557 enum i40e_status_code status; 4558 u16 length = count * sizeof(*buf); 4559 4560 i40e_fill_default_direct_cmd_desc(&desc, 4561 i40e_aqc_opc_get_switch_resource_alloc); 4562 4563 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4564 if (length > I40E_AQ_LARGE_BUF) 4565 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4566 4567 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4568 4569 if (!status && num_entries) 4570 *num_entries = cmd_resp->num_entries; 4571 4572 return status; 4573 } 4574 4575 /** 4576 * i40e_aq_delete_element - Delete switch element 4577 * @hw: pointer to the hw struct 4578 * @seid: the SEID to delete from the switch 4579 * @cmd_details: pointer to command details structure or NULL 4580 * 4581 * This deletes a switch element from the switch. 4582 **/ 4583 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4584 struct i40e_asq_cmd_details *cmd_details) 4585 { 4586 struct i40e_aq_desc desc; 4587 struct i40e_aqc_switch_seid *cmd = 4588 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4589 enum i40e_status_code status; 4590 4591 if (seid == 0) 4592 return I40E_ERR_PARAM; 4593 4594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4595 4596 cmd->seid = CPU_TO_LE16(seid); 4597 4598 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4599 4600 return status; 4601 } 4602 4603 /** 4604 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4605 * @hw: pointer to the hw struct 4606 * @flags: component flags 4607 * @mac_seid: uplink seid (MAC SEID) 4608 * @vsi_seid: connected vsi seid 4609 * @ret_seid: seid of create pv component 4610 * 4611 * This instantiates an i40e port virtualizer with specified flags. 4612 * Depending on specified flags the port virtualizer can act as a 4613 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4614 */ 4615 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4616 u16 mac_seid, u16 vsi_seid, 4617 u16 *ret_seid) 4618 { 4619 struct i40e_aq_desc desc; 4620 struct i40e_aqc_add_update_pv *cmd = 4621 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4622 struct i40e_aqc_add_update_pv_completion *resp = 4623 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4624 enum i40e_status_code status; 4625 4626 if (vsi_seid == 0) 4627 return I40E_ERR_PARAM; 4628 4629 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4630 cmd->command_flags = CPU_TO_LE16(flags); 4631 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4632 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4633 4634 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4635 if (!status && ret_seid) 4636 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4637 4638 return status; 4639 } 4640 4641 /** 4642 * i40e_aq_add_tag - Add an S/E-tag 4643 * @hw: pointer to the hw struct 4644 * @direct_to_queue: should s-tag direct flow to a specific queue 4645 * @vsi_seid: VSI SEID to use this tag 4646 * @tag: value of the tag 4647 * @queue_num: queue number, only valid is direct_to_queue is true 4648 * @tags_used: return value, number of tags in use by this PF 4649 * @tags_free: return value, number of unallocated tags 4650 * @cmd_details: pointer to command details structure or NULL 4651 * 4652 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4653 * the number of tags allocated by the PF, and the number of unallocated 4654 * tags available. 4655 **/ 4656 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4657 u16 vsi_seid, u16 tag, u16 queue_num, 4658 u16 *tags_used, u16 *tags_free, 4659 struct i40e_asq_cmd_details *cmd_details) 4660 { 4661 struct i40e_aq_desc desc; 4662 struct i40e_aqc_add_tag *cmd = 4663 (struct i40e_aqc_add_tag *)&desc.params.raw; 4664 struct i40e_aqc_add_remove_tag_completion *resp = 4665 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4666 enum i40e_status_code status; 4667 4668 if (vsi_seid == 0) 4669 return I40E_ERR_PARAM; 4670 4671 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4672 4673 cmd->seid = CPU_TO_LE16(vsi_seid); 4674 cmd->tag = CPU_TO_LE16(tag); 4675 if (direct_to_queue) { 4676 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4677 cmd->queue_number = CPU_TO_LE16(queue_num); 4678 } 4679 4680 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4681 4682 if (!status) { 4683 if (tags_used != NULL) 4684 *tags_used = LE16_TO_CPU(resp->tags_used); 4685 if (tags_free != NULL) 4686 *tags_free = LE16_TO_CPU(resp->tags_free); 4687 } 4688 4689 return status; 4690 } 4691 4692 /** 4693 * i40e_aq_remove_tag - Remove an S- or E-tag 4694 * @hw: pointer to the hw struct 4695 * @vsi_seid: VSI SEID this tag is associated with 4696 * @tag: value of the S-tag to delete 4697 * @tags_used: return value, number of tags in use by this PF 4698 * @tags_free: return value, number of unallocated tags 4699 * @cmd_details: pointer to command details structure or NULL 4700 * 4701 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4702 * the number of tags allocated by the PF, and the number of unallocated 4703 * tags available. 4704 **/ 4705 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4706 u16 tag, u16 *tags_used, u16 *tags_free, 4707 struct i40e_asq_cmd_details *cmd_details) 4708 { 4709 struct i40e_aq_desc desc; 4710 struct i40e_aqc_remove_tag *cmd = 4711 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4712 struct i40e_aqc_add_remove_tag_completion *resp = 4713 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4714 enum i40e_status_code status; 4715 4716 if (vsi_seid == 0) 4717 return I40E_ERR_PARAM; 4718 4719 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4720 4721 cmd->seid = CPU_TO_LE16(vsi_seid); 4722 cmd->tag = CPU_TO_LE16(tag); 4723 4724 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4725 4726 if (!status) { 4727 if (tags_used != NULL) 4728 *tags_used = LE16_TO_CPU(resp->tags_used); 4729 if (tags_free != NULL) 4730 *tags_free = LE16_TO_CPU(resp->tags_free); 4731 } 4732 4733 return status; 4734 } 4735 4736 /** 4737 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4738 * @hw: pointer to the hw struct 4739 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4740 * @etag: value of E-tag to add 4741 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4742 * @buf: address of indirect buffer 4743 * @tags_used: return value, number of E-tags in use by this port 4744 * @tags_free: return value, number of unallocated M-tags 4745 * @cmd_details: pointer to command details structure or NULL 4746 * 4747 * This associates a multicast E-tag to a port virtualizer. It will return 4748 * the number of tags allocated by the PF, and the number of unallocated 4749 * tags available. 4750 * 4751 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4752 * num_tags_in_buf long. 4753 **/ 4754 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4755 u16 etag, u8 num_tags_in_buf, void *buf, 4756 u16 *tags_used, u16 *tags_free, 4757 struct i40e_asq_cmd_details *cmd_details) 4758 { 4759 struct i40e_aq_desc desc; 4760 struct i40e_aqc_add_remove_mcast_etag *cmd = 4761 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4762 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4763 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4764 enum i40e_status_code status; 4765 u16 length = sizeof(u16) * num_tags_in_buf; 4766 4767 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4768 return I40E_ERR_PARAM; 4769 4770 i40e_fill_default_direct_cmd_desc(&desc, 4771 i40e_aqc_opc_add_multicast_etag); 4772 4773 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4774 cmd->etag = CPU_TO_LE16(etag); 4775 cmd->num_unicast_etags = num_tags_in_buf; 4776 4777 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4778 if (length > I40E_AQ_LARGE_BUF) 4779 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4780 4781 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4782 4783 if (!status) { 4784 if (tags_used != NULL) 4785 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4786 if (tags_free != NULL) 4787 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4788 } 4789 4790 return status; 4791 } 4792 4793 /** 4794 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4795 * @hw: pointer to the hw struct 4796 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4797 * @etag: value of the E-tag to remove 4798 * @tags_used: return value, number of tags in use by this port 4799 * @tags_free: return value, number of unallocated tags 4800 * @cmd_details: pointer to command details structure or NULL 4801 * 4802 * This deletes an E-tag from the port virtualizer. It will return 4803 * the number of tags allocated by the port, and the number of unallocated 4804 * tags available. 4805 **/ 4806 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4807 u16 etag, u16 *tags_used, u16 *tags_free, 4808 struct i40e_asq_cmd_details *cmd_details) 4809 { 4810 struct i40e_aq_desc desc; 4811 struct i40e_aqc_add_remove_mcast_etag *cmd = 4812 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4813 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4814 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4815 enum i40e_status_code status; 4816 4817 4818 if (pv_seid == 0) 4819 return I40E_ERR_PARAM; 4820 4821 i40e_fill_default_direct_cmd_desc(&desc, 4822 i40e_aqc_opc_remove_multicast_etag); 4823 4824 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4825 cmd->etag = CPU_TO_LE16(etag); 4826 4827 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4828 4829 if (!status) { 4830 if (tags_used != NULL) 4831 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4832 if (tags_free != NULL) 4833 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4834 } 4835 4836 return status; 4837 } 4838 4839 /** 4840 * i40e_aq_update_tag - Update an S/E-tag 4841 * @hw: pointer to the hw struct 4842 * @vsi_seid: VSI SEID using this S-tag 4843 * @old_tag: old tag value 4844 * @new_tag: new tag value 4845 * @tags_used: return value, number of tags in use by this PF 4846 * @tags_free: return value, number of unallocated tags 4847 * @cmd_details: pointer to command details structure or NULL 4848 * 4849 * This updates the value of the tag currently attached to this VSI 4850 * in the switch complex. It will return the number of tags allocated 4851 * by the PF, and the number of unallocated tags available. 4852 **/ 4853 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4854 u16 old_tag, u16 new_tag, u16 *tags_used, 4855 u16 *tags_free, 4856 struct i40e_asq_cmd_details *cmd_details) 4857 { 4858 struct i40e_aq_desc desc; 4859 struct i40e_aqc_update_tag *cmd = 4860 (struct i40e_aqc_update_tag *)&desc.params.raw; 4861 struct i40e_aqc_update_tag_completion *resp = 4862 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4863 enum i40e_status_code status; 4864 4865 if (vsi_seid == 0) 4866 return I40E_ERR_PARAM; 4867 4868 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4869 4870 cmd->seid = CPU_TO_LE16(vsi_seid); 4871 cmd->old_tag = CPU_TO_LE16(old_tag); 4872 cmd->new_tag = CPU_TO_LE16(new_tag); 4873 4874 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4875 4876 if (!status) { 4877 if (tags_used != NULL) 4878 *tags_used = LE16_TO_CPU(resp->tags_used); 4879 if (tags_free != NULL) 4880 *tags_free = LE16_TO_CPU(resp->tags_free); 4881 } 4882 4883 return status; 4884 } 4885 4886 /** 4887 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4888 * @hw: pointer to the hw struct 4889 * @tcmap: TC map for request/release any ignore PFC condition 4890 * @request: request or release ignore PFC condition 4891 * @tcmap_ret: return TCs for which PFC is currently ignored 4892 * @cmd_details: pointer to command details structure or NULL 4893 * 4894 * This sends out request/release to ignore PFC condition for a TC. 4895 * It will return the TCs for which PFC is currently ignored. 4896 **/ 4897 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4898 bool request, u8 *tcmap_ret, 4899 struct i40e_asq_cmd_details *cmd_details) 4900 { 4901 struct i40e_aq_desc desc; 4902 struct i40e_aqc_pfc_ignore *cmd_resp = 4903 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4904 enum i40e_status_code status; 4905 4906 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4907 4908 if (request) 4909 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4910 4911 cmd_resp->tc_bitmap = tcmap; 4912 4913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4914 4915 if (!status) { 4916 if (tcmap_ret != NULL) 4917 *tcmap_ret = cmd_resp->tc_bitmap; 4918 } 4919 4920 return status; 4921 } 4922 4923 /** 4924 * i40e_aq_dcb_updated - DCB Updated Command 4925 * @hw: pointer to the hw struct 4926 * @cmd_details: pointer to command details structure or NULL 4927 * 4928 * When LLDP is handled in PF this command is used by the PF 4929 * to notify EMP that a DCB setting is modified. 4930 * When LLDP is handled in EMP this command is used by the PF 4931 * to notify EMP whenever one of the following parameters get 4932 * modified: 4933 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4934 * - PCIRTT in PRTDCB_GENC.PCIRTT 4935 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4936 * EMP will return when the shared RPB settings have been 4937 * recomputed and modified. The retval field in the descriptor 4938 * will be set to 0 when RPB is modified. 4939 **/ 4940 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 4941 struct i40e_asq_cmd_details *cmd_details) 4942 { 4943 struct i40e_aq_desc desc; 4944 enum i40e_status_code status; 4945 4946 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 4947 4948 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4949 4950 return status; 4951 } 4952 4953 /** 4954 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 4955 * @hw: pointer to the hw struct 4956 * @seid: defines the SEID of the switch for which the stats are requested 4957 * @vlan_id: the VLAN ID for which the statistics are requested 4958 * @stat_index: index of the statistics counters block assigned to this VLAN 4959 * @cmd_details: pointer to command details structure or NULL 4960 * 4961 * XL710 supports 128 smonVlanStats counters.This command is used to 4962 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 4963 * switch. 4964 **/ 4965 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 4966 u16 vlan_id, u16 *stat_index, 4967 struct i40e_asq_cmd_details *cmd_details) 4968 { 4969 struct i40e_aq_desc desc; 4970 struct i40e_aqc_add_remove_statistics *cmd_resp = 4971 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4972 enum i40e_status_code status; 4973 4974 if ((seid == 0) || (stat_index == NULL)) 4975 return I40E_ERR_PARAM; 4976 4977 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 4978 4979 cmd_resp->seid = CPU_TO_LE16(seid); 4980 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 4981 4982 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4983 4984 if (!status && stat_index) 4985 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 4986 4987 return status; 4988 } 4989 4990 /** 4991 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 4992 * @hw: pointer to the hw struct 4993 * @seid: defines the SEID of the switch for which the stats are requested 4994 * @vlan_id: the VLAN ID for which the statistics are requested 4995 * @stat_index: index of the statistics counters block assigned to this VLAN 4996 * @cmd_details: pointer to command details structure or NULL 4997 * 4998 * XL710 supports 128 smonVlanStats counters.This command is used to 4999 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 5000 * switch. 5001 **/ 5002 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 5003 u16 vlan_id, u16 stat_index, 5004 struct i40e_asq_cmd_details *cmd_details) 5005 { 5006 struct i40e_aq_desc desc; 5007 struct i40e_aqc_add_remove_statistics *cmd = 5008 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5009 enum i40e_status_code status; 5010 5011 if (seid == 0) 5012 return I40E_ERR_PARAM; 5013 5014 i40e_fill_default_direct_cmd_desc(&desc, 5015 i40e_aqc_opc_remove_statistics); 5016 5017 cmd->seid = CPU_TO_LE16(seid); 5018 cmd->vlan = CPU_TO_LE16(vlan_id); 5019 cmd->stat_index = CPU_TO_LE16(stat_index); 5020 5021 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5022 5023 return status; 5024 } 5025 5026 /** 5027 * i40e_aq_set_port_parameters - set physical port parameters. 5028 * @hw: pointer to the hw struct 5029 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 5030 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 5031 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 5032 * @double_vlan: if set double VLAN is enabled 5033 * @cmd_details: pointer to command details structure or NULL 5034 **/ 5035 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 5036 u16 bad_frame_vsi, bool save_bad_pac, 5037 bool pad_short_pac, bool double_vlan, 5038 struct i40e_asq_cmd_details *cmd_details) 5039 { 5040 struct i40e_aqc_set_port_parameters *cmd; 5041 enum i40e_status_code status; 5042 struct i40e_aq_desc desc; 5043 u16 command_flags = 0; 5044 5045 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 5046 5047 i40e_fill_default_direct_cmd_desc(&desc, 5048 i40e_aqc_opc_set_port_parameters); 5049 5050 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 5051 if (save_bad_pac) 5052 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 5053 if (pad_short_pac) 5054 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 5055 if (double_vlan) 5056 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 5057 cmd->command_flags = CPU_TO_LE16(command_flags); 5058 5059 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5060 5061 return status; 5062 } 5063 5064 /** 5065 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 5066 * @hw: pointer to the hw struct 5067 * @seid: seid for the physical port/switching component/vsi 5068 * @buff: Indirect buffer to hold data parameters and response 5069 * @buff_size: Indirect buffer size 5070 * @opcode: Tx scheduler AQ command opcode 5071 * @cmd_details: pointer to command details structure or NULL 5072 * 5073 * Generic command handler for Tx scheduler AQ commands 5074 **/ 5075 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 5076 void *buff, u16 buff_size, 5077 enum i40e_admin_queue_opc opcode, 5078 struct i40e_asq_cmd_details *cmd_details) 5079 { 5080 struct i40e_aq_desc desc; 5081 struct i40e_aqc_tx_sched_ind *cmd = 5082 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 5083 enum i40e_status_code status; 5084 bool cmd_param_flag = false; 5085 5086 switch (opcode) { 5087 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 5088 case i40e_aqc_opc_configure_vsi_tc_bw: 5089 case i40e_aqc_opc_enable_switching_comp_ets: 5090 case i40e_aqc_opc_modify_switching_comp_ets: 5091 case i40e_aqc_opc_disable_switching_comp_ets: 5092 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 5093 case i40e_aqc_opc_configure_switching_comp_bw_config: 5094 cmd_param_flag = true; 5095 break; 5096 case i40e_aqc_opc_query_vsi_bw_config: 5097 case i40e_aqc_opc_query_vsi_ets_sla_config: 5098 case i40e_aqc_opc_query_switching_comp_ets_config: 5099 case i40e_aqc_opc_query_port_ets_config: 5100 case i40e_aqc_opc_query_switching_comp_bw_config: 5101 cmd_param_flag = false; 5102 break; 5103 default: 5104 return I40E_ERR_PARAM; 5105 } 5106 5107 i40e_fill_default_direct_cmd_desc(&desc, opcode); 5108 5109 /* Indirect command */ 5110 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5111 if (cmd_param_flag) 5112 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5113 if (buff_size > I40E_AQ_LARGE_BUF) 5114 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5115 5116 desc.datalen = CPU_TO_LE16(buff_size); 5117 5118 cmd->vsi_seid = CPU_TO_LE16(seid); 5119 5120 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5121 5122 return status; 5123 } 5124 5125 /** 5126 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 5127 * @hw: pointer to the hw struct 5128 * @seid: VSI seid 5129 * @credit: BW limit credits (0 = disabled) 5130 * @max_credit: Max BW limit credits 5131 * @cmd_details: pointer to command details structure or NULL 5132 **/ 5133 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 5134 u16 seid, u16 credit, u8 max_credit, 5135 struct i40e_asq_cmd_details *cmd_details) 5136 { 5137 struct i40e_aq_desc desc; 5138 struct i40e_aqc_configure_vsi_bw_limit *cmd = 5139 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 5140 enum i40e_status_code status; 5141 5142 i40e_fill_default_direct_cmd_desc(&desc, 5143 i40e_aqc_opc_configure_vsi_bw_limit); 5144 5145 cmd->vsi_seid = CPU_TO_LE16(seid); 5146 cmd->credit = CPU_TO_LE16(credit); 5147 cmd->max_credit = max_credit; 5148 5149 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5150 5151 return status; 5152 } 5153 5154 /** 5155 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5156 * @hw: pointer to the hw struct 5157 * @seid: switching component seid 5158 * @credit: BW limit credits (0 = disabled) 5159 * @max_bw: Max BW limit credits 5160 * @cmd_details: pointer to command details structure or NULL 5161 **/ 5162 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5163 u16 seid, u16 credit, u8 max_bw, 5164 struct i40e_asq_cmd_details *cmd_details) 5165 { 5166 struct i40e_aq_desc desc; 5167 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5168 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5169 enum i40e_status_code status; 5170 5171 i40e_fill_default_direct_cmd_desc(&desc, 5172 i40e_aqc_opc_configure_switching_comp_bw_limit); 5173 5174 cmd->seid = CPU_TO_LE16(seid); 5175 cmd->credit = CPU_TO_LE16(credit); 5176 cmd->max_bw = max_bw; 5177 5178 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5179 5180 return status; 5181 } 5182 5183 /** 5184 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5185 * @hw: pointer to the hw struct 5186 * @seid: VSI seid 5187 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5188 * @cmd_details: pointer to command details structure or NULL 5189 **/ 5190 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5191 u16 seid, 5192 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5193 struct i40e_asq_cmd_details *cmd_details) 5194 { 5195 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5196 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5197 cmd_details); 5198 } 5199 5200 /** 5201 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5202 * @hw: pointer to the hw struct 5203 * @seid: VSI seid 5204 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5205 * @cmd_details: pointer to command details structure or NULL 5206 **/ 5207 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5208 u16 seid, 5209 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5210 struct i40e_asq_cmd_details *cmd_details) 5211 { 5212 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5213 i40e_aqc_opc_configure_vsi_tc_bw, 5214 cmd_details); 5215 } 5216 5217 /** 5218 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 5219 * @hw: pointer to the hw struct 5220 * @seid: seid of the switching component connected to Physical Port 5221 * @ets_data: Buffer holding ETS parameters 5222 * @cmd_details: pointer to command details structure or NULL 5223 **/ 5224 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 5225 u16 seid, 5226 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 5227 enum i40e_admin_queue_opc opcode, 5228 struct i40e_asq_cmd_details *cmd_details) 5229 { 5230 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 5231 sizeof(*ets_data), opcode, cmd_details); 5232 } 5233 5234 /** 5235 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 5236 * @hw: pointer to the hw struct 5237 * @seid: seid of the switching component 5238 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 5239 * @cmd_details: pointer to command details structure or NULL 5240 **/ 5241 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 5242 u16 seid, 5243 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 5244 struct i40e_asq_cmd_details *cmd_details) 5245 { 5246 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5247 i40e_aqc_opc_configure_switching_comp_bw_config, 5248 cmd_details); 5249 } 5250 5251 /** 5252 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5253 * @hw: pointer to the hw struct 5254 * @seid: seid of the switching component 5255 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5256 * @cmd_details: pointer to command details structure or NULL 5257 **/ 5258 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5259 struct i40e_hw *hw, u16 seid, 5260 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5261 struct i40e_asq_cmd_details *cmd_details) 5262 { 5263 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5264 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5265 cmd_details); 5266 } 5267 5268 /** 5269 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5270 * @hw: pointer to the hw struct 5271 * @seid: seid of the VSI 5272 * @bw_data: Buffer to hold VSI BW configuration 5273 * @cmd_details: pointer to command details structure or NULL 5274 **/ 5275 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5276 u16 seid, 5277 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5278 struct i40e_asq_cmd_details *cmd_details) 5279 { 5280 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5281 i40e_aqc_opc_query_vsi_bw_config, 5282 cmd_details); 5283 } 5284 5285 /** 5286 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5287 * @hw: pointer to the hw struct 5288 * @seid: seid of the VSI 5289 * @bw_data: Buffer to hold VSI BW configuration per TC 5290 * @cmd_details: pointer to command details structure or NULL 5291 **/ 5292 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5293 u16 seid, 5294 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5295 struct i40e_asq_cmd_details *cmd_details) 5296 { 5297 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5298 i40e_aqc_opc_query_vsi_ets_sla_config, 5299 cmd_details); 5300 } 5301 5302 /** 5303 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5304 * @hw: pointer to the hw struct 5305 * @seid: seid of the switching component 5306 * @bw_data: Buffer to hold switching component's per TC BW config 5307 * @cmd_details: pointer to command details structure or NULL 5308 **/ 5309 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5310 u16 seid, 5311 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5312 struct i40e_asq_cmd_details *cmd_details) 5313 { 5314 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5315 i40e_aqc_opc_query_switching_comp_ets_config, 5316 cmd_details); 5317 } 5318 5319 /** 5320 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5321 * @hw: pointer to the hw struct 5322 * @seid: seid of the VSI or switching component connected to Physical Port 5323 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5324 * @cmd_details: pointer to command details structure or NULL 5325 **/ 5326 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5327 u16 seid, 5328 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5329 struct i40e_asq_cmd_details *cmd_details) 5330 { 5331 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5332 i40e_aqc_opc_query_port_ets_config, 5333 cmd_details); 5334 } 5335 5336 /** 5337 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5338 * @hw: pointer to the hw struct 5339 * @seid: seid of the switching component 5340 * @bw_data: Buffer to hold switching component's BW configuration 5341 * @cmd_details: pointer to command details structure or NULL 5342 **/ 5343 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5344 u16 seid, 5345 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5346 struct i40e_asq_cmd_details *cmd_details) 5347 { 5348 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5349 i40e_aqc_opc_query_switching_comp_bw_config, 5350 cmd_details); 5351 } 5352 5353 /** 5354 * i40e_validate_filter_settings 5355 * @hw: pointer to the hardware structure 5356 * @settings: Filter control settings 5357 * 5358 * Check and validate the filter control settings passed. 5359 * The function checks for the valid filter/context sizes being 5360 * passed for FCoE and PE. 5361 * 5362 * Returns I40E_SUCCESS if the values passed are valid and within 5363 * range else returns an error. 5364 **/ 5365 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5366 struct i40e_filter_control_settings *settings) 5367 { 5368 u32 fcoe_cntx_size, fcoe_filt_size; 5369 u32 pe_cntx_size, pe_filt_size; 5370 u32 fcoe_fmax; 5371 5372 u32 val; 5373 5374 /* Validate FCoE settings passed */ 5375 switch (settings->fcoe_filt_num) { 5376 case I40E_HASH_FILTER_SIZE_1K: 5377 case I40E_HASH_FILTER_SIZE_2K: 5378 case I40E_HASH_FILTER_SIZE_4K: 5379 case I40E_HASH_FILTER_SIZE_8K: 5380 case I40E_HASH_FILTER_SIZE_16K: 5381 case I40E_HASH_FILTER_SIZE_32K: 5382 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5383 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5384 break; 5385 default: 5386 return I40E_ERR_PARAM; 5387 } 5388 5389 switch (settings->fcoe_cntx_num) { 5390 case I40E_DMA_CNTX_SIZE_512: 5391 case I40E_DMA_CNTX_SIZE_1K: 5392 case I40E_DMA_CNTX_SIZE_2K: 5393 case I40E_DMA_CNTX_SIZE_4K: 5394 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5395 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5396 break; 5397 default: 5398 return I40E_ERR_PARAM; 5399 } 5400 5401 /* Validate PE settings passed */ 5402 switch (settings->pe_filt_num) { 5403 case I40E_HASH_FILTER_SIZE_1K: 5404 case I40E_HASH_FILTER_SIZE_2K: 5405 case I40E_HASH_FILTER_SIZE_4K: 5406 case I40E_HASH_FILTER_SIZE_8K: 5407 case I40E_HASH_FILTER_SIZE_16K: 5408 case I40E_HASH_FILTER_SIZE_32K: 5409 case I40E_HASH_FILTER_SIZE_64K: 5410 case I40E_HASH_FILTER_SIZE_128K: 5411 case I40E_HASH_FILTER_SIZE_256K: 5412 case I40E_HASH_FILTER_SIZE_512K: 5413 case I40E_HASH_FILTER_SIZE_1M: 5414 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5415 pe_filt_size <<= (u32)settings->pe_filt_num; 5416 break; 5417 default: 5418 return I40E_ERR_PARAM; 5419 } 5420 5421 switch (settings->pe_cntx_num) { 5422 case I40E_DMA_CNTX_SIZE_512: 5423 case I40E_DMA_CNTX_SIZE_1K: 5424 case I40E_DMA_CNTX_SIZE_2K: 5425 case I40E_DMA_CNTX_SIZE_4K: 5426 case I40E_DMA_CNTX_SIZE_8K: 5427 case I40E_DMA_CNTX_SIZE_16K: 5428 case I40E_DMA_CNTX_SIZE_32K: 5429 case I40E_DMA_CNTX_SIZE_64K: 5430 case I40E_DMA_CNTX_SIZE_128K: 5431 case I40E_DMA_CNTX_SIZE_256K: 5432 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5433 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5434 break; 5435 default: 5436 return I40E_ERR_PARAM; 5437 } 5438 5439 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5440 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5441 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5442 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5443 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5444 return I40E_ERR_INVALID_SIZE; 5445 5446 return I40E_SUCCESS; 5447 } 5448 5449 /** 5450 * i40e_set_filter_control 5451 * @hw: pointer to the hardware structure 5452 * @settings: Filter control settings 5453 * 5454 * Set the Queue Filters for PE/FCoE and enable filters required 5455 * for a single PF. It is expected that these settings are programmed 5456 * at the driver initialization time. 5457 **/ 5458 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5459 struct i40e_filter_control_settings *settings) 5460 { 5461 enum i40e_status_code ret = I40E_SUCCESS; 5462 u32 hash_lut_size = 0; 5463 u32 val; 5464 5465 if (!settings) 5466 return I40E_ERR_PARAM; 5467 5468 /* Validate the input settings */ 5469 ret = i40e_validate_filter_settings(hw, settings); 5470 if (ret) 5471 return ret; 5472 5473 /* Read the PF Queue Filter control register */ 5474 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5475 5476 /* Program required PE hash buckets for the PF */ 5477 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5478 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5479 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5480 /* Program required PE contexts for the PF */ 5481 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5482 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5483 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5484 5485 /* Program required FCoE hash buckets for the PF */ 5486 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5487 val |= ((u32)settings->fcoe_filt_num << 5488 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5489 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5490 /* Program required FCoE DDP contexts for the PF */ 5491 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5492 val |= ((u32)settings->fcoe_cntx_num << 5493 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5494 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5495 5496 /* Program Hash LUT size for the PF */ 5497 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5498 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5499 hash_lut_size = 1; 5500 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5501 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5502 5503 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5504 if (settings->enable_fdir) 5505 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5506 if (settings->enable_ethtype) 5507 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5508 if (settings->enable_macvlan) 5509 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5510 5511 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5512 5513 return I40E_SUCCESS; 5514 } 5515 5516 /** 5517 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5518 * @hw: pointer to the hw struct 5519 * @mac_addr: MAC address to use in the filter 5520 * @ethtype: Ethertype to use in the filter 5521 * @flags: Flags that needs to be applied to the filter 5522 * @vsi_seid: seid of the control VSI 5523 * @queue: VSI queue number to send the packet to 5524 * @is_add: Add control packet filter if True else remove 5525 * @stats: Structure to hold information on control filter counts 5526 * @cmd_details: pointer to command details structure or NULL 5527 * 5528 * This command will Add or Remove control packet filter for a control VSI. 5529 * In return it will update the total number of perfect filter count in 5530 * the stats member. 5531 **/ 5532 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5533 u8 *mac_addr, u16 ethtype, u16 flags, 5534 u16 vsi_seid, u16 queue, bool is_add, 5535 struct i40e_control_filter_stats *stats, 5536 struct i40e_asq_cmd_details *cmd_details) 5537 { 5538 struct i40e_aq_desc desc; 5539 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5540 (struct i40e_aqc_add_remove_control_packet_filter *) 5541 &desc.params.raw; 5542 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5543 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5544 &desc.params.raw; 5545 enum i40e_status_code status; 5546 5547 if (vsi_seid == 0) 5548 return I40E_ERR_PARAM; 5549 5550 if (is_add) { 5551 i40e_fill_default_direct_cmd_desc(&desc, 5552 i40e_aqc_opc_add_control_packet_filter); 5553 cmd->queue = CPU_TO_LE16(queue); 5554 } else { 5555 i40e_fill_default_direct_cmd_desc(&desc, 5556 i40e_aqc_opc_remove_control_packet_filter); 5557 } 5558 5559 if (mac_addr) 5560 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN, 5561 I40E_NONDMA_TO_NONDMA); 5562 5563 cmd->etype = CPU_TO_LE16(ethtype); 5564 cmd->flags = CPU_TO_LE16(flags); 5565 cmd->seid = CPU_TO_LE16(vsi_seid); 5566 5567 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5568 5569 if (!status && stats) { 5570 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5571 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5572 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5573 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5574 } 5575 5576 return status; 5577 } 5578 5579 /** 5580 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5581 * @hw: pointer to the hw struct 5582 * @seid: VSI seid to add ethertype filter from 5583 **/ 5584 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5585 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5586 u16 seid) 5587 { 5588 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5589 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5590 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5591 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5592 enum i40e_status_code status; 5593 5594 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5595 seid, 0, true, NULL, 5596 NULL); 5597 if (status) 5598 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5599 } 5600 5601 /** 5602 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5603 * @filters: list of cloud filters 5604 * @filter_count: length of list 5605 * 5606 * There's an issue in the device where the Geneve VNI layout needs 5607 * to be shifted 1 byte over from the VxLAN VNI 5608 **/ 5609 STATIC void i40e_fix_up_geneve_vni( 5610 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5611 u8 filter_count) 5612 { 5613 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters; 5614 int i; 5615 5616 for (i = 0; i < filter_count; i++) { 5617 u16 tnl_type; 5618 u32 ti; 5619 5620 tnl_type = (LE16_TO_CPU(f[i].flags) & 5621 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5622 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5623 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5624 ti = LE32_TO_CPU(f[i].tenant_id); 5625 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5626 } 5627 } 5628 } 5629 5630 /** 5631 * i40e_aq_add_cloud_filters 5632 * @hw: pointer to the hardware structure 5633 * @seid: VSI seid to add cloud filters from 5634 * @filters: Buffer which contains the filters to be added 5635 * @filter_count: number of filters contained in the buffer 5636 * 5637 * Set the cloud filters for a given VSI. The contents of the 5638 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5639 * in by the caller of the function. 5640 * 5641 **/ 5642 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5643 u16 seid, 5644 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5645 u8 filter_count) 5646 { 5647 struct i40e_aq_desc desc; 5648 struct i40e_aqc_add_remove_cloud_filters *cmd = 5649 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5650 enum i40e_status_code status; 5651 u16 buff_len; 5652 5653 i40e_fill_default_direct_cmd_desc(&desc, 5654 i40e_aqc_opc_add_cloud_filters); 5655 5656 buff_len = filter_count * sizeof(*filters); 5657 desc.datalen = CPU_TO_LE16(buff_len); 5658 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5659 cmd->num_filters = filter_count; 5660 cmd->seid = CPU_TO_LE16(seid); 5661 5662 i40e_fix_up_geneve_vni(filters, filter_count); 5663 5664 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5665 5666 return status; 5667 } 5668 5669 /** 5670 * i40e_aq_add_cloud_filters_big_buffer 5671 * @hw: pointer to the hardware structure 5672 * @seid: VSI seid to add cloud filters from 5673 * @filters: Buffer which contains the filters in big buffer to be added 5674 * @filter_count: number of filters contained in the buffer 5675 * 5676 * Set the cloud filters for a given VSI. The contents of the 5677 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of 5678 * the function. 5679 * 5680 **/ 5681 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw, 5682 u16 seid, 5683 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters, 5684 u8 filter_count) 5685 { 5686 struct i40e_aq_desc desc; 5687 struct i40e_aqc_add_remove_cloud_filters *cmd = 5688 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5689 enum i40e_status_code status; 5690 u16 buff_len; 5691 int i; 5692 5693 i40e_fill_default_direct_cmd_desc(&desc, 5694 i40e_aqc_opc_add_cloud_filters); 5695 5696 buff_len = filter_count * sizeof(*filters); 5697 desc.datalen = CPU_TO_LE16(buff_len); 5698 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5699 cmd->num_filters = filter_count; 5700 cmd->seid = CPU_TO_LE16(seid); 5701 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER; 5702 5703 /* adjust Geneve VNI for HW issue */ 5704 for (i = 0; i < filter_count; i++) { 5705 u16 tnl_type; 5706 u32 ti; 5707 5708 tnl_type = (LE16_TO_CPU(filters[i].element.flags) & 5709 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5710 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5711 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5712 ti = LE32_TO_CPU(filters[i].element.tenant_id); 5713 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8); 5714 } 5715 } 5716 5717 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5718 5719 return status; 5720 } 5721 5722 /** 5723 * i40e_aq_remove_cloud_filters 5724 * @hw: pointer to the hardware structure 5725 * @seid: VSI seid to remove cloud filters from 5726 * @filters: Buffer which contains the filters to be removed 5727 * @filter_count: number of filters contained in the buffer 5728 * 5729 * Remove the cloud filters for a given VSI. The contents of the 5730 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5731 * in by the caller of the function. 5732 * 5733 **/ 5734 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 5735 u16 seid, 5736 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5737 u8 filter_count) 5738 { 5739 struct i40e_aq_desc desc; 5740 struct i40e_aqc_add_remove_cloud_filters *cmd = 5741 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5742 enum i40e_status_code status; 5743 u16 buff_len; 5744 5745 i40e_fill_default_direct_cmd_desc(&desc, 5746 i40e_aqc_opc_remove_cloud_filters); 5747 5748 buff_len = filter_count * sizeof(*filters); 5749 desc.datalen = CPU_TO_LE16(buff_len); 5750 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5751 cmd->num_filters = filter_count; 5752 cmd->seid = CPU_TO_LE16(seid); 5753 5754 i40e_fix_up_geneve_vni(filters, filter_count); 5755 5756 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5757 5758 return status; 5759 } 5760 5761 /** 5762 * i40e_aq_remove_cloud_filters_big_buffer 5763 * @hw: pointer to the hardware structure 5764 * @seid: VSI seid to remove cloud filters from 5765 * @filters: Buffer which contains the filters in big buffer to be removed 5766 * @filter_count: number of filters contained in the buffer 5767 * 5768 * Remove the cloud filters for a given VSI. The contents of the 5769 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of 5770 * the function. 5771 * 5772 **/ 5773 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer( 5774 struct i40e_hw *hw, 5775 u16 seid, 5776 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters, 5777 u8 filter_count) 5778 { 5779 struct i40e_aq_desc desc; 5780 struct i40e_aqc_add_remove_cloud_filters *cmd = 5781 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5782 enum i40e_status_code status; 5783 u16 buff_len; 5784 int i; 5785 5786 i40e_fill_default_direct_cmd_desc(&desc, 5787 i40e_aqc_opc_remove_cloud_filters); 5788 5789 buff_len = filter_count * sizeof(*filters); 5790 desc.datalen = CPU_TO_LE16(buff_len); 5791 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5792 cmd->num_filters = filter_count; 5793 cmd->seid = CPU_TO_LE16(seid); 5794 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER; 5795 5796 /* adjust Geneve VNI for HW issue */ 5797 for (i = 0; i < filter_count; i++) { 5798 u16 tnl_type; 5799 u32 ti; 5800 5801 tnl_type = (LE16_TO_CPU(filters[i].element.flags) & 5802 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5803 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5804 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5805 ti = LE32_TO_CPU(filters[i].element.tenant_id); 5806 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8); 5807 } 5808 } 5809 5810 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5811 5812 return status; 5813 } 5814 5815 /** 5816 * i40e_aq_replace_cloud_filters - Replace cloud filter command 5817 * @hw: pointer to the hw struct 5818 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct 5819 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct 5820 * 5821 **/ 5822 enum 5823 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw, 5824 struct i40e_aqc_replace_cloud_filters_cmd *filters, 5825 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf) 5826 { 5827 struct i40e_aq_desc desc; 5828 struct i40e_aqc_replace_cloud_filters_cmd *cmd = 5829 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw; 5830 enum i40e_status_code status = I40E_SUCCESS; 5831 int i = 0; 5832 5833 i40e_fill_default_direct_cmd_desc(&desc, 5834 i40e_aqc_opc_replace_cloud_filters); 5835 5836 desc.datalen = CPU_TO_LE16(32); 5837 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5838 cmd->old_filter_type = filters->old_filter_type; 5839 cmd->new_filter_type = filters->new_filter_type; 5840 cmd->valid_flags = filters->valid_flags; 5841 cmd->tr_bit = filters->tr_bit; 5842 5843 status = i40e_asq_send_command(hw, &desc, cmd_buf, 5844 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL); 5845 5846 /* for get cloud filters command */ 5847 for (i = 0; i < 32; i += 4) { 5848 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i]; 5849 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1]; 5850 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2]; 5851 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3]; 5852 } 5853 5854 return status; 5855 } 5856 5857 5858 /** 5859 * i40e_aq_alternate_write 5860 * @hw: pointer to the hardware structure 5861 * @reg_addr0: address of first dword to be read 5862 * @reg_val0: value to be written under 'reg_addr0' 5863 * @reg_addr1: address of second dword to be read 5864 * @reg_val1: value to be written under 'reg_addr1' 5865 * 5866 * Write one or two dwords to alternate structure. Fields are indicated 5867 * by 'reg_addr0' and 'reg_addr1' register numbers. 5868 * 5869 **/ 5870 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 5871 u32 reg_addr0, u32 reg_val0, 5872 u32 reg_addr1, u32 reg_val1) 5873 { 5874 struct i40e_aq_desc desc; 5875 struct i40e_aqc_alternate_write *cmd_resp = 5876 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5877 enum i40e_status_code status; 5878 5879 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 5880 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5881 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5882 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5883 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5884 5885 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5886 5887 return status; 5888 } 5889 5890 /** 5891 * i40e_aq_alternate_write_indirect 5892 * @hw: pointer to the hardware structure 5893 * @addr: address of a first register to be modified 5894 * @dw_count: number of alternate structure fields to write 5895 * @buffer: pointer to the command buffer 5896 * 5897 * Write 'dw_count' dwords from 'buffer' to alternate structure 5898 * starting at 'addr'. 5899 * 5900 **/ 5901 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5902 u32 addr, u32 dw_count, void *buffer) 5903 { 5904 struct i40e_aq_desc desc; 5905 struct i40e_aqc_alternate_ind_write *cmd_resp = 5906 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5907 enum i40e_status_code status; 5908 5909 if (buffer == NULL) 5910 return I40E_ERR_PARAM; 5911 5912 /* Indirect command */ 5913 i40e_fill_default_direct_cmd_desc(&desc, 5914 i40e_aqc_opc_alternate_write_indirect); 5915 5916 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5917 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5918 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5919 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5920 5921 cmd_resp->address = CPU_TO_LE32(addr); 5922 cmd_resp->length = CPU_TO_LE32(dw_count); 5923 5924 status = i40e_asq_send_command(hw, &desc, buffer, 5925 I40E_LO_DWORD(4*dw_count), NULL); 5926 5927 return status; 5928 } 5929 5930 /** 5931 * i40e_aq_alternate_read 5932 * @hw: pointer to the hardware structure 5933 * @reg_addr0: address of first dword to be read 5934 * @reg_val0: pointer for data read from 'reg_addr0' 5935 * @reg_addr1: address of second dword to be read 5936 * @reg_val1: pointer for data read from 'reg_addr1' 5937 * 5938 * Read one or two dwords from alternate structure. Fields are indicated 5939 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5940 * is not passed then only register at 'reg_addr0' is read. 5941 * 5942 **/ 5943 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5944 u32 reg_addr0, u32 *reg_val0, 5945 u32 reg_addr1, u32 *reg_val1) 5946 { 5947 struct i40e_aq_desc desc; 5948 struct i40e_aqc_alternate_write *cmd_resp = 5949 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5950 enum i40e_status_code status; 5951 5952 if (reg_val0 == NULL) 5953 return I40E_ERR_PARAM; 5954 5955 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5956 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5957 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5958 5959 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5960 5961 if (status == I40E_SUCCESS) { 5962 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5963 5964 if (reg_val1 != NULL) 5965 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5966 } 5967 5968 return status; 5969 } 5970 5971 /** 5972 * i40e_aq_alternate_read_indirect 5973 * @hw: pointer to the hardware structure 5974 * @addr: address of the alternate structure field 5975 * @dw_count: number of alternate structure fields to read 5976 * @buffer: pointer to the command buffer 5977 * 5978 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5979 * place them in 'buffer'. The buffer should be allocated by caller. 5980 * 5981 **/ 5982 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5983 u32 addr, u32 dw_count, void *buffer) 5984 { 5985 struct i40e_aq_desc desc; 5986 struct i40e_aqc_alternate_ind_write *cmd_resp = 5987 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5988 enum i40e_status_code status; 5989 5990 if (buffer == NULL) 5991 return I40E_ERR_PARAM; 5992 5993 /* Indirect command */ 5994 i40e_fill_default_direct_cmd_desc(&desc, 5995 i40e_aqc_opc_alternate_read_indirect); 5996 5997 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5998 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5999 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 6000 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6001 6002 cmd_resp->address = CPU_TO_LE32(addr); 6003 cmd_resp->length = CPU_TO_LE32(dw_count); 6004 6005 status = i40e_asq_send_command(hw, &desc, buffer, 6006 I40E_LO_DWORD(4*dw_count), NULL); 6007 6008 return status; 6009 } 6010 6011 /** 6012 * i40e_aq_alternate_clear 6013 * @hw: pointer to the HW structure. 6014 * 6015 * Clear the alternate structures of the port from which the function 6016 * is called. 6017 * 6018 **/ 6019 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 6020 { 6021 struct i40e_aq_desc desc; 6022 enum i40e_status_code status; 6023 6024 i40e_fill_default_direct_cmd_desc(&desc, 6025 i40e_aqc_opc_alternate_clear_port); 6026 6027 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6028 6029 return status; 6030 } 6031 6032 /** 6033 * i40e_aq_alternate_write_done 6034 * @hw: pointer to the HW structure. 6035 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 6036 * @reset_needed: indicates the SW should trigger GLOBAL reset 6037 * 6038 * Indicates to the FW that alternate structures have been changed. 6039 * 6040 **/ 6041 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 6042 u8 bios_mode, bool *reset_needed) 6043 { 6044 struct i40e_aq_desc desc; 6045 struct i40e_aqc_alternate_write_done *cmd = 6046 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 6047 enum i40e_status_code status; 6048 6049 if (reset_needed == NULL) 6050 return I40E_ERR_PARAM; 6051 6052 i40e_fill_default_direct_cmd_desc(&desc, 6053 i40e_aqc_opc_alternate_write_done); 6054 6055 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 6056 6057 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6058 if (!status && reset_needed) 6059 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 6060 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 6061 6062 return status; 6063 } 6064 6065 /** 6066 * i40e_aq_set_oem_mode 6067 * @hw: pointer to the HW structure. 6068 * @oem_mode: the OEM mode to be used 6069 * 6070 * Sets the device to a specific operating mode. Currently the only supported 6071 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 6072 * 6073 **/ 6074 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 6075 u8 oem_mode) 6076 { 6077 struct i40e_aq_desc desc; 6078 struct i40e_aqc_alternate_write_done *cmd = 6079 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 6080 enum i40e_status_code status; 6081 6082 i40e_fill_default_direct_cmd_desc(&desc, 6083 i40e_aqc_opc_alternate_set_mode); 6084 6085 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 6086 6087 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 6088 6089 return status; 6090 } 6091 6092 /** 6093 * i40e_aq_resume_port_tx 6094 * @hw: pointer to the hardware structure 6095 * @cmd_details: pointer to command details structure or NULL 6096 * 6097 * Resume port's Tx traffic 6098 **/ 6099 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 6100 struct i40e_asq_cmd_details *cmd_details) 6101 { 6102 struct i40e_aq_desc desc; 6103 enum i40e_status_code status; 6104 6105 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 6106 6107 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6108 6109 return status; 6110 } 6111 6112 /** 6113 * i40e_set_pci_config_data - store PCI bus info 6114 * @hw: pointer to hardware structure 6115 * @link_status: the link status word from PCI config space 6116 * 6117 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 6118 **/ 6119 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 6120 { 6121 hw->bus.type = i40e_bus_type_pci_express; 6122 6123 switch (link_status & I40E_PCI_LINK_WIDTH) { 6124 case I40E_PCI_LINK_WIDTH_1: 6125 hw->bus.width = i40e_bus_width_pcie_x1; 6126 break; 6127 case I40E_PCI_LINK_WIDTH_2: 6128 hw->bus.width = i40e_bus_width_pcie_x2; 6129 break; 6130 case I40E_PCI_LINK_WIDTH_4: 6131 hw->bus.width = i40e_bus_width_pcie_x4; 6132 break; 6133 case I40E_PCI_LINK_WIDTH_8: 6134 hw->bus.width = i40e_bus_width_pcie_x8; 6135 break; 6136 default: 6137 hw->bus.width = i40e_bus_width_unknown; 6138 break; 6139 } 6140 6141 switch (link_status & I40E_PCI_LINK_SPEED) { 6142 case I40E_PCI_LINK_SPEED_2500: 6143 hw->bus.speed = i40e_bus_speed_2500; 6144 break; 6145 case I40E_PCI_LINK_SPEED_5000: 6146 hw->bus.speed = i40e_bus_speed_5000; 6147 break; 6148 case I40E_PCI_LINK_SPEED_8000: 6149 hw->bus.speed = i40e_bus_speed_8000; 6150 break; 6151 default: 6152 hw->bus.speed = i40e_bus_speed_unknown; 6153 break; 6154 } 6155 } 6156 6157 /** 6158 * i40e_aq_debug_dump 6159 * @hw: pointer to the hardware structure 6160 * @cluster_id: specific cluster to dump 6161 * @table_id: table id within cluster 6162 * @start_index: index of line in the block to read 6163 * @buff_size: dump buffer size 6164 * @buff: dump buffer 6165 * @ret_buff_size: actual buffer size returned 6166 * @ret_next_table: next block to read 6167 * @ret_next_index: next index to read 6168 * 6169 * Dump internal FW/HW data for debug purposes. 6170 * 6171 **/ 6172 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 6173 u8 table_id, u32 start_index, u16 buff_size, 6174 void *buff, u16 *ret_buff_size, 6175 u8 *ret_next_table, u32 *ret_next_index, 6176 struct i40e_asq_cmd_details *cmd_details) 6177 { 6178 struct i40e_aq_desc desc; 6179 struct i40e_aqc_debug_dump_internals *cmd = 6180 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6181 struct i40e_aqc_debug_dump_internals *resp = 6182 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6183 enum i40e_status_code status; 6184 6185 if (buff_size == 0 || !buff) 6186 return I40E_ERR_PARAM; 6187 6188 i40e_fill_default_direct_cmd_desc(&desc, 6189 i40e_aqc_opc_debug_dump_internals); 6190 /* Indirect Command */ 6191 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6192 if (buff_size > I40E_AQ_LARGE_BUF) 6193 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6194 6195 cmd->cluster_id = cluster_id; 6196 cmd->table_id = table_id; 6197 cmd->idx = CPU_TO_LE32(start_index); 6198 6199 desc.datalen = CPU_TO_LE16(buff_size); 6200 6201 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 6202 if (!status) { 6203 if (ret_buff_size != NULL) 6204 *ret_buff_size = LE16_TO_CPU(desc.datalen); 6205 if (ret_next_table != NULL) 6206 *ret_next_table = resp->table_id; 6207 if (ret_next_index != NULL) 6208 *ret_next_index = LE32_TO_CPU(resp->idx); 6209 } 6210 6211 return status; 6212 } 6213 6214 /** 6215 * i40e_read_bw_from_alt_ram 6216 * @hw: pointer to the hardware structure 6217 * @max_bw: pointer for max_bw read 6218 * @min_bw: pointer for min_bw read 6219 * @min_valid: pointer for bool that is true if min_bw is a valid value 6220 * @max_valid: pointer for bool that is true if max_bw is a valid value 6221 * 6222 * Read bw from the alternate ram for the given pf 6223 **/ 6224 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 6225 u32 *max_bw, u32 *min_bw, 6226 bool *min_valid, bool *max_valid) 6227 { 6228 enum i40e_status_code status; 6229 u32 max_bw_addr, min_bw_addr; 6230 6231 /* Calculate the address of the min/max bw registers */ 6232 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6233 I40E_ALT_STRUCT_MAX_BW_OFFSET + 6234 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6235 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6236 I40E_ALT_STRUCT_MIN_BW_OFFSET + 6237 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6238 6239 /* Read the bandwidths from alt ram */ 6240 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 6241 min_bw_addr, min_bw); 6242 6243 if (*min_bw & I40E_ALT_BW_VALID_MASK) 6244 *min_valid = true; 6245 else 6246 *min_valid = false; 6247 6248 if (*max_bw & I40E_ALT_BW_VALID_MASK) 6249 *max_valid = true; 6250 else 6251 *max_valid = false; 6252 6253 return status; 6254 } 6255 6256 /** 6257 * i40e_aq_configure_partition_bw 6258 * @hw: pointer to the hardware structure 6259 * @bw_data: Buffer holding valid pfs and bw limits 6260 * @cmd_details: pointer to command details 6261 * 6262 * Configure partitions guaranteed/max bw 6263 **/ 6264 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 6265 struct i40e_aqc_configure_partition_bw_data *bw_data, 6266 struct i40e_asq_cmd_details *cmd_details) 6267 { 6268 enum i40e_status_code status; 6269 struct i40e_aq_desc desc; 6270 u16 bwd_size = sizeof(*bw_data); 6271 6272 i40e_fill_default_direct_cmd_desc(&desc, 6273 i40e_aqc_opc_configure_partition_bw); 6274 6275 /* Indirect command */ 6276 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6277 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6278 6279 desc.datalen = CPU_TO_LE16(bwd_size); 6280 6281 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 6282 6283 return status; 6284 } 6285 6286 /** 6287 * i40e_read_phy_register_clause22 6288 * @hw: pointer to the HW structure 6289 * @reg: register address in the page 6290 * @phy_adr: PHY address on MDIO interface 6291 * @value: PHY register value 6292 * 6293 * Reads specified PHY register value 6294 **/ 6295 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 6296 u16 reg, u8 phy_addr, u16 *value) 6297 { 6298 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6299 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6300 u32 command = 0; 6301 u16 retry = 1000; 6302 6303 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6304 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6305 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 6306 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6307 (I40E_GLGEN_MSCA_MDICMD_MASK); 6308 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6309 do { 6310 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6311 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6312 status = I40E_SUCCESS; 6313 break; 6314 } 6315 i40e_usec_delay(10); 6316 retry--; 6317 } while (retry); 6318 6319 if (status) { 6320 i40e_debug(hw, I40E_DEBUG_PHY, 6321 "PHY: Can't write command to external PHY.\n"); 6322 } else { 6323 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6324 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6325 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6326 } 6327 6328 return status; 6329 } 6330 6331 /** 6332 * i40e_write_phy_register_clause22 6333 * @hw: pointer to the HW structure 6334 * @reg: register address in the page 6335 * @phy_adr: PHY address on MDIO interface 6336 * @value: PHY register value 6337 * 6338 * Writes specified PHY register value 6339 **/ 6340 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6341 u16 reg, u8 phy_addr, u16 value) 6342 { 6343 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6344 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6345 u32 command = 0; 6346 u16 retry = 1000; 6347 6348 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6349 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6350 6351 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6352 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6353 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6354 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6355 (I40E_GLGEN_MSCA_MDICMD_MASK); 6356 6357 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6358 do { 6359 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6360 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6361 status = I40E_SUCCESS; 6362 break; 6363 } 6364 i40e_usec_delay(10); 6365 retry--; 6366 } while (retry); 6367 6368 return status; 6369 } 6370 6371 /** 6372 * i40e_read_phy_register_clause45 6373 * @hw: pointer to the HW structure 6374 * @page: registers page number 6375 * @reg: register address in the page 6376 * @phy_adr: PHY address on MDIO interface 6377 * @value: PHY register value 6378 * 6379 * Reads specified PHY register value 6380 **/ 6381 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6382 u8 page, u16 reg, u8 phy_addr, u16 *value) 6383 { 6384 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6385 u32 command = 0; 6386 u16 retry = 1000; 6387 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6388 6389 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6390 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6391 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6392 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6393 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6394 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6395 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6396 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6397 do { 6398 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6399 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6400 status = I40E_SUCCESS; 6401 break; 6402 } 6403 i40e_usec_delay(10); 6404 retry--; 6405 } while (retry); 6406 6407 if (status) { 6408 i40e_debug(hw, I40E_DEBUG_PHY, 6409 "PHY: Can't write command to external PHY.\n"); 6410 goto phy_read_end; 6411 } 6412 6413 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6414 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6415 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6416 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6417 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6418 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6419 status = I40E_ERR_TIMEOUT; 6420 retry = 1000; 6421 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6422 do { 6423 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6424 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6425 status = I40E_SUCCESS; 6426 break; 6427 } 6428 i40e_usec_delay(10); 6429 retry--; 6430 } while (retry); 6431 6432 if (!status) { 6433 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6434 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6435 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6436 } else { 6437 i40e_debug(hw, I40E_DEBUG_PHY, 6438 "PHY: Can't read register value from external PHY.\n"); 6439 } 6440 6441 phy_read_end: 6442 return status; 6443 } 6444 6445 /** 6446 * i40e_write_phy_register_clause45 6447 * @hw: pointer to the HW structure 6448 * @page: registers page number 6449 * @reg: register address in the page 6450 * @phy_adr: PHY address on MDIO interface 6451 * @value: PHY register value 6452 * 6453 * Writes value to specified PHY register 6454 **/ 6455 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6456 u8 page, u16 reg, u8 phy_addr, u16 value) 6457 { 6458 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6459 u32 command = 0; 6460 u16 retry = 1000; 6461 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6462 6463 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6464 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6465 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6466 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6467 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6468 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6469 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6470 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6471 do { 6472 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6473 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6474 status = I40E_SUCCESS; 6475 break; 6476 } 6477 i40e_usec_delay(10); 6478 retry--; 6479 } while (retry); 6480 if (status) { 6481 i40e_debug(hw, I40E_DEBUG_PHY, 6482 "PHY: Can't write command to external PHY.\n"); 6483 goto phy_write_end; 6484 } 6485 6486 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6487 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6488 6489 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6490 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6491 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6492 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6493 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6494 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6495 status = I40E_ERR_TIMEOUT; 6496 retry = 1000; 6497 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6498 do { 6499 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6500 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6501 status = I40E_SUCCESS; 6502 break; 6503 } 6504 i40e_usec_delay(10); 6505 retry--; 6506 } while (retry); 6507 6508 phy_write_end: 6509 return status; 6510 } 6511 6512 /** 6513 * i40e_write_phy_register 6514 * @hw: pointer to the HW structure 6515 * @page: registers page number 6516 * @reg: register address in the page 6517 * @phy_adr: PHY address on MDIO interface 6518 * @value: PHY register value 6519 * 6520 * Writes value to specified PHY register 6521 **/ 6522 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6523 u8 page, u16 reg, u8 phy_addr, u16 value) 6524 { 6525 enum i40e_status_code status; 6526 6527 switch (hw->device_id) { 6528 case I40E_DEV_ID_1G_BASE_T_X722: 6529 status = i40e_write_phy_register_clause22(hw, 6530 reg, phy_addr, value); 6531 break; 6532 case I40E_DEV_ID_10G_BASE_T: 6533 case I40E_DEV_ID_10G_BASE_T4: 6534 case I40E_DEV_ID_10G_BASE_T_X722: 6535 case I40E_DEV_ID_25G_B: 6536 case I40E_DEV_ID_25G_SFP28: 6537 status = i40e_write_phy_register_clause45(hw, 6538 page, reg, phy_addr, value); 6539 break; 6540 default: 6541 status = I40E_ERR_UNKNOWN_PHY; 6542 break; 6543 } 6544 6545 return status; 6546 } 6547 6548 /** 6549 * i40e_read_phy_register 6550 * @hw: pointer to the HW structure 6551 * @page: registers page number 6552 * @reg: register address in the page 6553 * @phy_adr: PHY address on MDIO interface 6554 * @value: PHY register value 6555 * 6556 * Reads specified PHY register value 6557 **/ 6558 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6559 u8 page, u16 reg, u8 phy_addr, u16 *value) 6560 { 6561 enum i40e_status_code status; 6562 6563 switch (hw->device_id) { 6564 case I40E_DEV_ID_1G_BASE_T_X722: 6565 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6566 value); 6567 break; 6568 case I40E_DEV_ID_10G_BASE_T: 6569 case I40E_DEV_ID_10G_BASE_T4: 6570 case I40E_DEV_ID_10G_BASE_T_X722: 6571 case I40E_DEV_ID_25G_B: 6572 case I40E_DEV_ID_25G_SFP28: 6573 status = i40e_read_phy_register_clause45(hw, page, reg, 6574 phy_addr, value); 6575 break; 6576 default: 6577 status = I40E_ERR_UNKNOWN_PHY; 6578 break; 6579 } 6580 6581 return status; 6582 } 6583 6584 /** 6585 * i40e_get_phy_address 6586 * @hw: pointer to the HW structure 6587 * @dev_num: PHY port num that address we want 6588 * @phy_addr: Returned PHY address 6589 * 6590 * Gets PHY address for current port 6591 **/ 6592 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6593 { 6594 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6595 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6596 6597 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6598 } 6599 6600 /** 6601 * i40e_blink_phy_led 6602 * @hw: pointer to the HW structure 6603 * @time: time how long led will blinks in secs 6604 * @interval: gap between LED on and off in msecs 6605 * 6606 * Blinks PHY link LED 6607 **/ 6608 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6609 u32 time, u32 interval) 6610 { 6611 enum i40e_status_code status = I40E_SUCCESS; 6612 u32 i; 6613 u16 led_ctl = 0; 6614 u16 gpio_led_port; 6615 u16 led_reg; 6616 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6617 u8 phy_addr = 0; 6618 u8 port_num; 6619 6620 i = rd32(hw, I40E_PFGEN_PORTNUM); 6621 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6622 phy_addr = i40e_get_phy_address(hw, port_num); 6623 6624 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6625 led_addr++) { 6626 status = i40e_read_phy_register_clause45(hw, 6627 I40E_PHY_COM_REG_PAGE, 6628 led_addr, phy_addr, 6629 &led_reg); 6630 if (status) 6631 goto phy_blinking_end; 6632 led_ctl = led_reg; 6633 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6634 led_reg = 0; 6635 status = i40e_write_phy_register_clause45(hw, 6636 I40E_PHY_COM_REG_PAGE, 6637 led_addr, phy_addr, 6638 led_reg); 6639 if (status) 6640 goto phy_blinking_end; 6641 break; 6642 } 6643 } 6644 6645 if (time > 0 && interval > 0) { 6646 for (i = 0; i < time * 1000; i += interval) { 6647 status = i40e_read_phy_register_clause45(hw, 6648 I40E_PHY_COM_REG_PAGE, 6649 led_addr, phy_addr, &led_reg); 6650 if (status) 6651 goto restore_config; 6652 if (led_reg & I40E_PHY_LED_MANUAL_ON) 6653 led_reg = 0; 6654 else 6655 led_reg = I40E_PHY_LED_MANUAL_ON; 6656 status = i40e_write_phy_register_clause45(hw, 6657 I40E_PHY_COM_REG_PAGE, 6658 led_addr, phy_addr, led_reg); 6659 if (status) 6660 goto restore_config; 6661 i40e_msec_delay(interval); 6662 } 6663 } 6664 6665 restore_config: 6666 status = i40e_write_phy_register_clause45(hw, 6667 I40E_PHY_COM_REG_PAGE, 6668 led_addr, phy_addr, led_ctl); 6669 6670 phy_blinking_end: 6671 return status; 6672 } 6673 6674 /** 6675 * i40e_led_get_phy - return current on/off mode 6676 * @hw: pointer to the hw struct 6677 * @led_addr: address of led register to use 6678 * @val: original value of register to use 6679 * 6680 **/ 6681 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 6682 u16 *val) 6683 { 6684 enum i40e_status_code status = I40E_SUCCESS; 6685 u16 gpio_led_port; 6686 u8 phy_addr = 0; 6687 u16 reg_val; 6688 u16 temp_addr; 6689 u8 port_num; 6690 u32 i; 6691 u32 reg_val_aq; 6692 6693 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6694 status = 6695 i40e_aq_get_phy_register(hw, 6696 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6697 I40E_PHY_COM_REG_PAGE, 6698 I40E_PHY_LED_PROV_REG_1, 6699 ®_val_aq, NULL); 6700 if (status) 6701 return status; 6702 *val = (u16)reg_val_aq; 6703 } else { 6704 temp_addr = I40E_PHY_LED_PROV_REG_1; 6705 i = rd32(hw, I40E_PFGEN_PORTNUM); 6706 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6707 phy_addr = i40e_get_phy_address(hw, port_num); 6708 6709 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6710 temp_addr++) { 6711 status = 6712 i40e_read_phy_register_clause45(hw, 6713 I40E_PHY_COM_REG_PAGE, 6714 temp_addr, phy_addr, 6715 ®_val); 6716 if (status) 6717 return status; 6718 *val = reg_val; 6719 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 6720 *led_addr = temp_addr; 6721 break; 6722 } 6723 } 6724 } 6725 return status; 6726 } 6727 6728 /** 6729 * i40e_led_set_phy 6730 * @hw: pointer to the HW structure 6731 * @on: true or false 6732 * @mode: original val plus bit for set or ignore 6733 * Set led's on or off when controlled by the PHY 6734 * 6735 **/ 6736 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 6737 u16 led_addr, u32 mode) 6738 { 6739 enum i40e_status_code status = I40E_SUCCESS; 6740 u32 led_ctl = 0; 6741 u32 led_reg = 0; 6742 u8 phy_addr = 0; 6743 u8 port_num; 6744 u32 i; 6745 6746 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6747 status = 6748 i40e_aq_get_phy_register(hw, 6749 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6750 I40E_PHY_COM_REG_PAGE, 6751 I40E_PHY_LED_PROV_REG_1, 6752 &led_reg, NULL); 6753 } else { 6754 i = rd32(hw, I40E_PFGEN_PORTNUM); 6755 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6756 phy_addr = i40e_get_phy_address(hw, port_num); 6757 status = i40e_read_phy_register_clause45(hw, 6758 I40E_PHY_COM_REG_PAGE, 6759 led_addr, phy_addr, 6760 (u16 *)&led_reg); 6761 } 6762 if (status) 6763 return status; 6764 led_ctl = led_reg; 6765 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6766 led_reg = 0; 6767 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 6768 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 6769 status = i40e_aq_set_phy_register(hw, 6770 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6771 I40E_PHY_COM_REG_PAGE, 6772 I40E_PHY_LED_PROV_REG_1, 6773 led_reg, NULL); 6774 } else { 6775 status = i40e_write_phy_register_clause45(hw, 6776 I40E_PHY_COM_REG_PAGE, 6777 led_addr, phy_addr, 6778 (u16)led_reg); 6779 } 6780 if (status) 6781 return status; 6782 } 6783 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6784 status = 6785 i40e_aq_get_phy_register(hw, 6786 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6787 I40E_PHY_COM_REG_PAGE, 6788 I40E_PHY_LED_PROV_REG_1, 6789 &led_reg, NULL); 6790 } else { 6791 status = i40e_read_phy_register_clause45(hw, 6792 I40E_PHY_COM_REG_PAGE, 6793 led_addr, phy_addr, 6794 (u16 *)&led_reg); 6795 } 6796 if (status) 6797 goto restore_config; 6798 if (on) 6799 led_reg = I40E_PHY_LED_MANUAL_ON; 6800 else 6801 led_reg = 0; 6802 6803 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6804 status = 6805 i40e_aq_set_phy_register(hw, 6806 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6807 I40E_PHY_COM_REG_PAGE, 6808 I40E_PHY_LED_PROV_REG_1, 6809 led_reg, NULL); 6810 } else { 6811 status = 6812 i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 6813 led_addr, phy_addr, 6814 (u16)led_reg); 6815 } 6816 if (status) 6817 goto restore_config; 6818 if (mode & I40E_PHY_LED_MODE_ORIG) { 6819 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 6820 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6821 status = i40e_aq_set_phy_register(hw, 6822 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6823 I40E_PHY_COM_REG_PAGE, 6824 I40E_PHY_LED_PROV_REG_1, 6825 led_ctl, NULL); 6826 } else { 6827 status = i40e_write_phy_register_clause45(hw, 6828 I40E_PHY_COM_REG_PAGE, 6829 led_addr, phy_addr, 6830 (u16)led_ctl); 6831 } 6832 } 6833 return status; 6834 restore_config: 6835 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6836 status = 6837 i40e_aq_set_phy_register(hw, 6838 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6839 I40E_PHY_COM_REG_PAGE, 6840 I40E_PHY_LED_PROV_REG_1, 6841 led_ctl, NULL); 6842 } else { 6843 status = 6844 i40e_write_phy_register_clause45(hw, 6845 I40E_PHY_COM_REG_PAGE, 6846 led_addr, phy_addr, 6847 (u16)led_ctl); 6848 } 6849 return status; 6850 } 6851 #endif /* PF_DRIVER */ 6852 6853 /** 6854 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 6855 * @hw: pointer to the hw struct 6856 * @reg_addr: register address 6857 * @reg_val: ptr to register value 6858 * @cmd_details: pointer to command details structure or NULL 6859 * 6860 * Use the firmware to read the Rx control register, 6861 * especially useful if the Rx unit is under heavy pressure 6862 **/ 6863 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 6864 u32 reg_addr, u32 *reg_val, 6865 struct i40e_asq_cmd_details *cmd_details) 6866 { 6867 struct i40e_aq_desc desc; 6868 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 6869 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6870 enum i40e_status_code status; 6871 6872 if (reg_val == NULL) 6873 return I40E_ERR_PARAM; 6874 6875 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 6876 6877 cmd_resp->address = CPU_TO_LE32(reg_addr); 6878 6879 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6880 6881 if (status == I40E_SUCCESS) 6882 *reg_val = LE32_TO_CPU(cmd_resp->value); 6883 6884 return status; 6885 } 6886 6887 /** 6888 * i40e_read_rx_ctl - read from an Rx control register 6889 * @hw: pointer to the hw struct 6890 * @reg_addr: register address 6891 **/ 6892 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 6893 { 6894 enum i40e_status_code status = I40E_SUCCESS; 6895 bool use_register; 6896 int retry = 5; 6897 u32 val = 0; 6898 6899 use_register = (((hw->aq.api_maj_ver == 1) && 6900 (hw->aq.api_min_ver < 5)) || 6901 (hw->mac.type == I40E_MAC_X722)); 6902 if (!use_register) { 6903 do_retry: 6904 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 6905 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6906 i40e_msec_delay(1); 6907 retry--; 6908 goto do_retry; 6909 } 6910 } 6911 6912 /* if the AQ access failed, try the old-fashioned way */ 6913 if (status || use_register) 6914 val = rd32(hw, reg_addr); 6915 6916 return val; 6917 } 6918 6919 /** 6920 * i40e_aq_rx_ctl_write_register 6921 * @hw: pointer to the hw struct 6922 * @reg_addr: register address 6923 * @reg_val: register value 6924 * @cmd_details: pointer to command details structure or NULL 6925 * 6926 * Use the firmware to write to an Rx control register, 6927 * especially useful if the Rx unit is under heavy pressure 6928 **/ 6929 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 6930 u32 reg_addr, u32 reg_val, 6931 struct i40e_asq_cmd_details *cmd_details) 6932 { 6933 struct i40e_aq_desc desc; 6934 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 6935 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6936 enum i40e_status_code status; 6937 6938 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 6939 6940 cmd->address = CPU_TO_LE32(reg_addr); 6941 cmd->value = CPU_TO_LE32(reg_val); 6942 6943 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6944 6945 return status; 6946 } 6947 6948 /** 6949 * i40e_write_rx_ctl - write to an Rx control register 6950 * @hw: pointer to the hw struct 6951 * @reg_addr: register address 6952 * @reg_val: register value 6953 **/ 6954 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 6955 { 6956 enum i40e_status_code status = I40E_SUCCESS; 6957 bool use_register; 6958 int retry = 5; 6959 6960 use_register = (((hw->aq.api_maj_ver == 1) && 6961 (hw->aq.api_min_ver < 5)) || 6962 (hw->mac.type == I40E_MAC_X722)); 6963 if (!use_register) { 6964 do_retry: 6965 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 6966 reg_val, NULL); 6967 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6968 i40e_msec_delay(1); 6969 retry--; 6970 goto do_retry; 6971 } 6972 } 6973 6974 /* if the AQ access failed, try the old-fashioned way */ 6975 if (status || use_register) 6976 wr32(hw, reg_addr, reg_val); 6977 } 6978 6979 /** 6980 * i40e_aq_set_phy_register 6981 * @hw: pointer to the hw struct 6982 * @phy_select: select which phy should be accessed 6983 * @dev_addr: PHY device address 6984 * @reg_addr: PHY register address 6985 * @reg_val: new register value 6986 * @cmd_details: pointer to command details structure or NULL 6987 * 6988 * Write the external PHY register. 6989 **/ 6990 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw, 6991 u8 phy_select, u8 dev_addr, 6992 u32 reg_addr, u32 reg_val, 6993 struct i40e_asq_cmd_details *cmd_details) 6994 { 6995 struct i40e_aq_desc desc; 6996 struct i40e_aqc_phy_register_access *cmd = 6997 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6998 enum i40e_status_code status; 6999 7000 i40e_fill_default_direct_cmd_desc(&desc, 7001 i40e_aqc_opc_set_phy_register); 7002 7003 cmd->phy_interface = phy_select; 7004 cmd->dev_addres = dev_addr; 7005 cmd->reg_address = reg_addr; 7006 cmd->reg_value = reg_val; 7007 7008 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7009 7010 return status; 7011 } 7012 7013 /** 7014 * i40e_aq_get_phy_register 7015 * @hw: pointer to the hw struct 7016 * @phy_select: select which phy should be accessed 7017 * @dev_addr: PHY device address 7018 * @reg_addr: PHY register address 7019 * @reg_val: read register value 7020 * @cmd_details: pointer to command details structure or NULL 7021 * 7022 * Read the external PHY register. 7023 **/ 7024 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw, 7025 u8 phy_select, u8 dev_addr, 7026 u32 reg_addr, u32 *reg_val, 7027 struct i40e_asq_cmd_details *cmd_details) 7028 { 7029 struct i40e_aq_desc desc; 7030 struct i40e_aqc_phy_register_access *cmd = 7031 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 7032 enum i40e_status_code status; 7033 7034 i40e_fill_default_direct_cmd_desc(&desc, 7035 i40e_aqc_opc_get_phy_register); 7036 7037 cmd->phy_interface = phy_select; 7038 cmd->dev_addres = dev_addr; 7039 cmd->reg_address = reg_addr; 7040 7041 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7042 if (!status) 7043 *reg_val = cmd->reg_value; 7044 7045 return status; 7046 } 7047 7048 #ifdef VF_DRIVER 7049 7050 /** 7051 * i40e_aq_send_msg_to_pf 7052 * @hw: pointer to the hardware structure 7053 * @v_opcode: opcodes for VF-PF communication 7054 * @v_retval: return error code 7055 * @msg: pointer to the msg buffer 7056 * @msglen: msg length 7057 * @cmd_details: pointer to command details 7058 * 7059 * Send message to PF driver using admin queue. By default, this message 7060 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 7061 * completion before returning. 7062 **/ 7063 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 7064 enum virtchnl_ops v_opcode, 7065 enum i40e_status_code v_retval, 7066 u8 *msg, u16 msglen, 7067 struct i40e_asq_cmd_details *cmd_details) 7068 { 7069 struct i40e_aq_desc desc; 7070 struct i40e_asq_cmd_details details; 7071 enum i40e_status_code status; 7072 7073 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 7074 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 7075 desc.cookie_high = CPU_TO_LE32(v_opcode); 7076 desc.cookie_low = CPU_TO_LE32(v_retval); 7077 if (msglen) { 7078 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 7079 | I40E_AQ_FLAG_RD)); 7080 if (msglen > I40E_AQ_LARGE_BUF) 7081 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7082 desc.datalen = CPU_TO_LE16(msglen); 7083 } 7084 if (!cmd_details) { 7085 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 7086 details.async = true; 7087 cmd_details = &details; 7088 } 7089 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 7090 msglen, cmd_details); 7091 return status; 7092 } 7093 7094 /** 7095 * i40e_vf_parse_hw_config 7096 * @hw: pointer to the hardware structure 7097 * @msg: pointer to the virtual channel VF resource structure 7098 * 7099 * Given a VF resource message from the PF, populate the hw struct 7100 * with appropriate information. 7101 **/ 7102 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 7103 struct virtchnl_vf_resource *msg) 7104 { 7105 struct virtchnl_vsi_resource *vsi_res; 7106 int i; 7107 7108 vsi_res = &msg->vsi_res[0]; 7109 7110 hw->dev_caps.num_vsis = msg->num_vsis; 7111 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 7112 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 7113 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 7114 hw->dev_caps.dcb = msg->vf_offload_flags & 7115 VIRTCHNL_VF_OFFLOAD_L2; 7116 hw->dev_caps.iwarp = (msg->vf_offload_flags & 7117 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 7118 for (i = 0; i < msg->num_vsis; i++) { 7119 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) { 7120 i40e_memcpy(hw->mac.perm_addr, 7121 vsi_res->default_mac_addr, 7122 ETH_ALEN, 7123 I40E_NONDMA_TO_NONDMA); 7124 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 7125 ETH_ALEN, 7126 I40E_NONDMA_TO_NONDMA); 7127 } 7128 vsi_res++; 7129 } 7130 } 7131 7132 /** 7133 * i40e_vf_reset 7134 * @hw: pointer to the hardware structure 7135 * 7136 * Send a VF_RESET message to the PF. Does not wait for response from PF 7137 * as none will be forthcoming. Immediately after calling this function, 7138 * the admin queue should be shut down and (optionally) reinitialized. 7139 **/ 7140 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 7141 { 7142 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF, 7143 I40E_SUCCESS, NULL, 0, NULL); 7144 } 7145 #endif /* VF_DRIVER */ 7146 7147 /** 7148 * i40e_aq_set_arp_proxy_config 7149 * @hw: pointer to the HW structure 7150 * @proxy_config - pointer to proxy config command table struct 7151 * @cmd_details: pointer to command details 7152 * 7153 * Set ARP offload parameters from pre-populated 7154 * i40e_aqc_arp_proxy_data struct 7155 **/ 7156 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 7157 struct i40e_aqc_arp_proxy_data *proxy_config, 7158 struct i40e_asq_cmd_details *cmd_details) 7159 { 7160 struct i40e_aq_desc desc; 7161 enum i40e_status_code status; 7162 7163 if (!proxy_config) 7164 return I40E_ERR_PARAM; 7165 7166 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 7167 7168 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7169 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7170 desc.params.external.addr_high = 7171 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config)); 7172 desc.params.external.addr_low = 7173 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config)); 7174 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data)); 7175 7176 status = i40e_asq_send_command(hw, &desc, proxy_config, 7177 sizeof(struct i40e_aqc_arp_proxy_data), 7178 cmd_details); 7179 7180 return status; 7181 } 7182 7183 /** 7184 * i40e_aq_opc_set_ns_proxy_table_entry 7185 * @hw: pointer to the HW structure 7186 * @ns_proxy_table_entry: pointer to NS table entry command struct 7187 * @cmd_details: pointer to command details 7188 * 7189 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 7190 * from pre-populated i40e_aqc_ns_proxy_data struct 7191 **/ 7192 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 7193 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 7194 struct i40e_asq_cmd_details *cmd_details) 7195 { 7196 struct i40e_aq_desc desc; 7197 enum i40e_status_code status; 7198 7199 if (!ns_proxy_table_entry) 7200 return I40E_ERR_PARAM; 7201 7202 i40e_fill_default_direct_cmd_desc(&desc, 7203 i40e_aqc_opc_set_ns_proxy_table_entry); 7204 7205 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7206 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7207 desc.params.external.addr_high = 7208 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry)); 7209 desc.params.external.addr_low = 7210 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry)); 7211 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data)); 7212 7213 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 7214 sizeof(struct i40e_aqc_ns_proxy_data), 7215 cmd_details); 7216 7217 return status; 7218 } 7219 7220 /** 7221 * i40e_aq_set_clear_wol_filter 7222 * @hw: pointer to the hw struct 7223 * @filter_index: index of filter to modify (0-7) 7224 * @filter: buffer containing filter to be set 7225 * @set_filter: true to set filter, false to clear filter 7226 * @no_wol_tco: if true, pass through packets cannot cause wake-up 7227 * if false, pass through packets may cause wake-up 7228 * @filter_valid: true if filter action is valid 7229 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid 7230 * @cmd_details: pointer to command details structure or NULL 7231 * 7232 * Set or clear WoL filter for port attached to the PF 7233 **/ 7234 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 7235 u8 filter_index, 7236 struct i40e_aqc_set_wol_filter_data *filter, 7237 bool set_filter, bool no_wol_tco, 7238 bool filter_valid, bool no_wol_tco_valid, 7239 struct i40e_asq_cmd_details *cmd_details) 7240 { 7241 struct i40e_aq_desc desc; 7242 struct i40e_aqc_set_wol_filter *cmd = 7243 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 7244 enum i40e_status_code status; 7245 u16 cmd_flags = 0; 7246 u16 valid_flags = 0; 7247 u16 buff_len = 0; 7248 7249 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 7250 7251 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 7252 return I40E_ERR_PARAM; 7253 cmd->filter_index = CPU_TO_LE16(filter_index); 7254 7255 if (set_filter) { 7256 if (!filter) 7257 return I40E_ERR_PARAM; 7258 7259 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 7260 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR; 7261 } 7262 7263 if (no_wol_tco) 7264 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 7265 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 7266 7267 if (filter_valid) 7268 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 7269 if (no_wol_tco_valid) 7270 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 7271 cmd->valid_flags = CPU_TO_LE16(valid_flags); 7272 7273 buff_len = sizeof(*filter); 7274 desc.datalen = CPU_TO_LE16(buff_len); 7275 7276 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7277 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7278 7279 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter)); 7280 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter)); 7281 7282 status = i40e_asq_send_command(hw, &desc, filter, 7283 buff_len, cmd_details); 7284 7285 return status; 7286 } 7287 7288 /** 7289 * i40e_aq_get_wake_event_reason 7290 * @hw: pointer to the hw struct 7291 * @wake_reason: return value, index of matching filter 7292 * @cmd_details: pointer to command details structure or NULL 7293 * 7294 * Get information for the reason of a Wake Up event 7295 **/ 7296 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 7297 u16 *wake_reason, 7298 struct i40e_asq_cmd_details *cmd_details) 7299 { 7300 struct i40e_aq_desc desc; 7301 struct i40e_aqc_get_wake_reason_completion *resp = 7302 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 7303 enum i40e_status_code status; 7304 7305 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 7306 7307 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7308 7309 if (status == I40E_SUCCESS) 7310 *wake_reason = LE16_TO_CPU(resp->wake_reason); 7311 7312 return status; 7313 } 7314 7315 /** 7316 * i40e_aq_clear_all_wol_filters 7317 * @hw: pointer to the hw struct 7318 * @cmd_details: pointer to command details structure or NULL 7319 * 7320 * Get information for the reason of a Wake Up event 7321 **/ 7322 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw, 7323 struct i40e_asq_cmd_details *cmd_details) 7324 { 7325 struct i40e_aq_desc desc; 7326 enum i40e_status_code status; 7327 7328 i40e_fill_default_direct_cmd_desc(&desc, 7329 i40e_aqc_opc_clear_all_wol_filters); 7330 7331 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7332 7333 return status; 7334 } 7335 7336 7337 /** 7338 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 7339 * @hw: pointer to the hw struct 7340 * @buff: command buffer (size in bytes = buff_size) 7341 * @buff_size: buffer size in bytes 7342 * @track_id: package tracking id 7343 * @error_offset: returns error offset 7344 * @error_info: returns error information 7345 * @cmd_details: pointer to command details structure or NULL 7346 **/ 7347 enum 7348 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 7349 u16 buff_size, u32 track_id, 7350 u32 *error_offset, u32 *error_info, 7351 struct i40e_asq_cmd_details *cmd_details) 7352 { 7353 struct i40e_aq_desc desc; 7354 struct i40e_aqc_write_personalization_profile *cmd = 7355 (struct i40e_aqc_write_personalization_profile *) 7356 &desc.params.raw; 7357 struct i40e_aqc_write_ddp_resp *resp; 7358 enum i40e_status_code status; 7359 7360 i40e_fill_default_direct_cmd_desc(&desc, 7361 i40e_aqc_opc_write_personalization_profile); 7362 7363 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 7364 if (buff_size > I40E_AQ_LARGE_BUF) 7365 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7366 7367 desc.datalen = CPU_TO_LE16(buff_size); 7368 7369 cmd->profile_track_id = CPU_TO_LE32(track_id); 7370 7371 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 7372 if (!status) { 7373 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 7374 if (error_offset) 7375 *error_offset = LE32_TO_CPU(resp->error_offset); 7376 if (error_info) 7377 *error_info = LE32_TO_CPU(resp->error_info); 7378 } 7379 7380 return status; 7381 } 7382 7383 /** 7384 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 7385 * @hw: pointer to the hw struct 7386 * @buff: command buffer (size in bytes = buff_size) 7387 * @buff_size: buffer size in bytes 7388 * @cmd_details: pointer to command details structure or NULL 7389 **/ 7390 enum 7391 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 7392 u16 buff_size, u8 flags, 7393 struct i40e_asq_cmd_details *cmd_details) 7394 { 7395 struct i40e_aq_desc desc; 7396 struct i40e_aqc_get_applied_profiles *cmd = 7397 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 7398 enum i40e_status_code status; 7399 7400 i40e_fill_default_direct_cmd_desc(&desc, 7401 i40e_aqc_opc_get_personalization_profile_list); 7402 7403 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7404 if (buff_size > I40E_AQ_LARGE_BUF) 7405 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7406 desc.datalen = CPU_TO_LE16(buff_size); 7407 7408 cmd->flags = flags; 7409 7410 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 7411 7412 return status; 7413 } 7414 7415 /** 7416 * i40e_find_segment_in_package 7417 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 7418 * @pkg_hdr: pointer to the package header to be searched 7419 * 7420 * This function searches a package file for a particular segment type. On 7421 * success it returns a pointer to the segment header, otherwise it will 7422 * return NULL. 7423 **/ 7424 struct i40e_generic_seg_header * 7425 i40e_find_segment_in_package(u32 segment_type, 7426 struct i40e_package_header *pkg_hdr) 7427 { 7428 struct i40e_generic_seg_header *segment; 7429 u32 i; 7430 7431 /* Search all package segments for the requested segment type */ 7432 for (i = 0; i < pkg_hdr->segment_count; i++) { 7433 segment = 7434 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 7435 pkg_hdr->segment_offset[i]); 7436 7437 if (segment->type == segment_type) 7438 return segment; 7439 } 7440 7441 return NULL; 7442 } 7443 7444 /* Get section table in profile */ 7445 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 7446 do { \ 7447 struct i40e_profile_segment *p = (profile); \ 7448 u32 count; \ 7449 u32 *nvm; \ 7450 count = p->device_table_count; \ 7451 nvm = (u32 *)&p->device_table[count]; \ 7452 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 7453 } while (0) 7454 7455 /* Get section header in profile */ 7456 #define I40E_SECTION_HEADER(profile, offset) \ 7457 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 7458 7459 /** 7460 * i40e_find_section_in_profile 7461 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE) 7462 * @profile: pointer to the i40e segment header to be searched 7463 * 7464 * This function searches i40e segment for a particular section type. On 7465 * success it returns a pointer to the section header, otherwise it will 7466 * return NULL. 7467 **/ 7468 struct i40e_profile_section_header * 7469 i40e_find_section_in_profile(u32 section_type, 7470 struct i40e_profile_segment *profile) 7471 { 7472 struct i40e_profile_section_header *sec; 7473 struct i40e_section_table *sec_tbl; 7474 u32 sec_off; 7475 u32 i; 7476 7477 if (profile->header.type != SEGMENT_TYPE_I40E) 7478 return NULL; 7479 7480 I40E_SECTION_TABLE(profile, sec_tbl); 7481 7482 for (i = 0; i < sec_tbl->section_count; i++) { 7483 sec_off = sec_tbl->section_offset[i]; 7484 sec = I40E_SECTION_HEADER(profile, sec_off); 7485 if (sec->section.type == section_type) 7486 return sec; 7487 } 7488 7489 return NULL; 7490 } 7491 7492 /** 7493 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 7494 * @hw: pointer to the hw struct 7495 * @aq: command buffer containing all data to execute AQ 7496 **/ 7497 STATIC enum 7498 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw, 7499 struct i40e_profile_aq_section *aq) 7500 { 7501 enum i40e_status_code status; 7502 struct i40e_aq_desc desc; 7503 u8 *msg = NULL; 7504 u16 msglen; 7505 7506 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 7507 desc.flags |= CPU_TO_LE16(aq->flags); 7508 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw), 7509 I40E_NONDMA_TO_NONDMA); 7510 7511 msglen = aq->datalen; 7512 if (msglen) { 7513 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 7514 I40E_AQ_FLAG_RD)); 7515 if (msglen > I40E_AQ_LARGE_BUF) 7516 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 7517 desc.datalen = CPU_TO_LE16(msglen); 7518 msg = &aq->data[0]; 7519 } 7520 7521 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 7522 7523 if (status != I40E_SUCCESS) { 7524 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7525 "unable to exec DDP AQ opcode %u, error %d\n", 7526 aq->opcode, status); 7527 return status; 7528 } 7529 7530 /* copy returned desc to aq_buf */ 7531 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw), 7532 I40E_NONDMA_TO_NONDMA); 7533 7534 return I40E_SUCCESS; 7535 } 7536 7537 /** 7538 * i40e_validate_profile 7539 * @hw: pointer to the hardware structure 7540 * @profile: pointer to the profile segment of the package to be validated 7541 * @track_id: package tracking id 7542 * @rollback: flag if the profile is for rollback. 7543 * 7544 * Validates supported devices and profile's sections. 7545 */ 7546 STATIC enum i40e_status_code 7547 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 7548 u32 track_id, bool rollback) 7549 { 7550 struct i40e_profile_section_header *sec = NULL; 7551 enum i40e_status_code status = I40E_SUCCESS; 7552 struct i40e_section_table *sec_tbl; 7553 u32 vendor_dev_id; 7554 u32 dev_cnt; 7555 u32 sec_off; 7556 u32 i; 7557 7558 if (track_id == I40E_DDP_TRACKID_INVALID) { 7559 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 7560 return I40E_NOT_SUPPORTED; 7561 } 7562 7563 dev_cnt = profile->device_table_count; 7564 for (i = 0; i < dev_cnt; i++) { 7565 vendor_dev_id = profile->device_table[i].vendor_dev_id; 7566 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID && 7567 hw->device_id == (vendor_dev_id & 0xFFFF)) 7568 break; 7569 } 7570 if (dev_cnt && (i == dev_cnt)) { 7571 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7572 "Device doesn't support DDP\n"); 7573 return I40E_ERR_DEVICE_NOT_SUPPORTED; 7574 } 7575 7576 I40E_SECTION_TABLE(profile, sec_tbl); 7577 7578 /* Validate sections types */ 7579 for (i = 0; i < sec_tbl->section_count; i++) { 7580 sec_off = sec_tbl->section_offset[i]; 7581 sec = I40E_SECTION_HEADER(profile, sec_off); 7582 if (rollback) { 7583 if (sec->section.type == SECTION_TYPE_MMIO || 7584 sec->section.type == SECTION_TYPE_AQ || 7585 sec->section.type == SECTION_TYPE_RB_AQ) { 7586 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7587 "Not a roll-back package\n"); 7588 return I40E_NOT_SUPPORTED; 7589 } 7590 } else { 7591 if (sec->section.type == SECTION_TYPE_RB_AQ || 7592 sec->section.type == SECTION_TYPE_RB_MMIO) { 7593 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7594 "Not an original package\n"); 7595 return I40E_NOT_SUPPORTED; 7596 } 7597 } 7598 } 7599 7600 return status; 7601 } 7602 7603 /** 7604 * i40e_write_profile 7605 * @hw: pointer to the hardware structure 7606 * @profile: pointer to the profile segment of the package to be downloaded 7607 * @track_id: package tracking id 7608 * 7609 * Handles the download of a complete package. 7610 */ 7611 enum i40e_status_code 7612 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 7613 u32 track_id) 7614 { 7615 enum i40e_status_code status = I40E_SUCCESS; 7616 struct i40e_section_table *sec_tbl; 7617 struct i40e_profile_section_header *sec = NULL; 7618 struct i40e_profile_aq_section *ddp_aq; 7619 u32 section_size = 0; 7620 u32 offset = 0, info = 0; 7621 u32 sec_off; 7622 u32 i; 7623 7624 status = i40e_validate_profile(hw, profile, track_id, false); 7625 if (status) 7626 return status; 7627 7628 I40E_SECTION_TABLE(profile, sec_tbl); 7629 7630 for (i = 0; i < sec_tbl->section_count; i++) { 7631 sec_off = sec_tbl->section_offset[i]; 7632 sec = I40E_SECTION_HEADER(profile, sec_off); 7633 /* Process generic admin command */ 7634 if (sec->section.type == SECTION_TYPE_AQ) { 7635 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 7636 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 7637 if (status) { 7638 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7639 "Failed to execute aq: section %d, opcode %u\n", 7640 i, ddp_aq->opcode); 7641 break; 7642 } 7643 sec->section.type = SECTION_TYPE_RB_AQ; 7644 } 7645 7646 /* Skip any non-mmio sections */ 7647 if (sec->section.type != SECTION_TYPE_MMIO) 7648 continue; 7649 7650 section_size = sec->section.size + 7651 sizeof(struct i40e_profile_section_header); 7652 7653 /* Write MMIO section */ 7654 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 7655 track_id, &offset, &info, NULL); 7656 if (status) { 7657 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7658 "Failed to write profile: section %d, offset %d, info %d\n", 7659 i, offset, info); 7660 break; 7661 } 7662 } 7663 return status; 7664 } 7665 7666 /** 7667 * i40e_rollback_profile 7668 * @hw: pointer to the hardware structure 7669 * @profile: pointer to the profile segment of the package to be removed 7670 * @track_id: package tracking id 7671 * 7672 * Rolls back previously loaded package. 7673 */ 7674 enum i40e_status_code 7675 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 7676 u32 track_id) 7677 { 7678 struct i40e_profile_section_header *sec = NULL; 7679 enum i40e_status_code status = I40E_SUCCESS; 7680 struct i40e_section_table *sec_tbl; 7681 u32 offset = 0, info = 0; 7682 u32 section_size = 0; 7683 u32 sec_off; 7684 int i; 7685 7686 status = i40e_validate_profile(hw, profile, track_id, true); 7687 if (status) 7688 return status; 7689 7690 I40E_SECTION_TABLE(profile, sec_tbl); 7691 7692 /* For rollback write sections in reverse */ 7693 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 7694 sec_off = sec_tbl->section_offset[i]; 7695 sec = I40E_SECTION_HEADER(profile, sec_off); 7696 7697 /* Skip any non-rollback sections */ 7698 if (sec->section.type != SECTION_TYPE_RB_MMIO) 7699 continue; 7700 7701 section_size = sec->section.size + 7702 sizeof(struct i40e_profile_section_header); 7703 7704 /* Write roll-back MMIO section */ 7705 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 7706 track_id, &offset, &info, NULL); 7707 if (status) { 7708 i40e_debug(hw, I40E_DEBUG_PACKAGE, 7709 "Failed to write profile: section %d, offset %d, info %d\n", 7710 i, offset, info); 7711 break; 7712 } 7713 } 7714 return status; 7715 } 7716 7717 /** 7718 * i40e_add_pinfo_to_list 7719 * @hw: pointer to the hardware structure 7720 * @profile: pointer to the profile segment of the package 7721 * @profile_info_sec: buffer for information section 7722 * @track_id: package tracking id 7723 * 7724 * Register a profile to the list of loaded profiles. 7725 */ 7726 enum i40e_status_code 7727 i40e_add_pinfo_to_list(struct i40e_hw *hw, 7728 struct i40e_profile_segment *profile, 7729 u8 *profile_info_sec, u32 track_id) 7730 { 7731 enum i40e_status_code status = I40E_SUCCESS; 7732 struct i40e_profile_section_header *sec = NULL; 7733 struct i40e_profile_info *pinfo; 7734 u32 offset = 0, info = 0; 7735 7736 sec = (struct i40e_profile_section_header *)profile_info_sec; 7737 sec->tbl_size = 1; 7738 sec->data_end = sizeof(struct i40e_profile_section_header) + 7739 sizeof(struct i40e_profile_info); 7740 sec->section.type = SECTION_TYPE_INFO; 7741 sec->section.offset = sizeof(struct i40e_profile_section_header); 7742 sec->section.size = sizeof(struct i40e_profile_info); 7743 pinfo = (struct i40e_profile_info *)(profile_info_sec + 7744 sec->section.offset); 7745 pinfo->track_id = track_id; 7746 pinfo->version = profile->version; 7747 pinfo->op = I40E_DDP_ADD_TRACKID; 7748 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE, 7749 I40E_NONDMA_TO_NONDMA); 7750 7751 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end, 7752 track_id, &offset, &info, NULL); 7753 return status; 7754 } 7755