1 /******************************************************************************* 2 3 Copyright (c) 2013 - 2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 #ifndef _I40E_ADMINQ_CMD_H_ 35 #define _I40E_ADMINQ_CMD_H_ 36 37 /* This header file defines the i40e Admin Queue commands and is shared between 38 * i40e Firmware and Software. 39 * 40 * This file needs to comply with the Linux Kernel coding style. 41 */ 42 43 #define I40E_FW_API_VERSION_MAJOR 0x0001 44 #define I40E_FW_API_VERSION_MINOR_X722 0x0005 45 #define I40E_FW_API_VERSION_MINOR_X710 0x0007 46 47 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 48 I40E_FW_API_VERSION_MINOR_X710 : \ 49 I40E_FW_API_VERSION_MINOR_X722) 50 51 /* API version 1.7 implements additional link and PHY-specific APIs */ 52 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 53 54 struct i40e_aq_desc { 55 __le16 flags; 56 __le16 opcode; 57 __le16 datalen; 58 __le16 retval; 59 __le32 cookie_high; 60 __le32 cookie_low; 61 union { 62 struct { 63 __le32 param0; 64 __le32 param1; 65 __le32 param2; 66 __le32 param3; 67 } internal; 68 struct { 69 __le32 param0; 70 __le32 param1; 71 __le32 addr_high; 72 __le32 addr_low; 73 } external; 74 u8 raw[16]; 75 } params; 76 }; 77 78 /* Flags sub-structure 79 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 80 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 81 */ 82 83 /* command flags and offsets*/ 84 #define I40E_AQ_FLAG_DD_SHIFT 0 85 #define I40E_AQ_FLAG_CMP_SHIFT 1 86 #define I40E_AQ_FLAG_ERR_SHIFT 2 87 #define I40E_AQ_FLAG_VFE_SHIFT 3 88 #define I40E_AQ_FLAG_LB_SHIFT 9 89 #define I40E_AQ_FLAG_RD_SHIFT 10 90 #define I40E_AQ_FLAG_VFC_SHIFT 11 91 #define I40E_AQ_FLAG_BUF_SHIFT 12 92 #define I40E_AQ_FLAG_SI_SHIFT 13 93 #define I40E_AQ_FLAG_EI_SHIFT 14 94 #define I40E_AQ_FLAG_FE_SHIFT 15 95 96 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 97 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 98 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 99 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 100 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 101 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 102 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 103 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 104 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 105 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 106 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 107 108 /* error codes */ 109 enum i40e_admin_queue_err { 110 I40E_AQ_RC_OK = 0, /* success */ 111 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 112 I40E_AQ_RC_ENOENT = 2, /* No such element */ 113 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 114 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 115 I40E_AQ_RC_EIO = 5, /* I/O error */ 116 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 117 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 118 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 119 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 120 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 121 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 122 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 123 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 124 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 125 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 126 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 127 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 128 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 129 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 130 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 131 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 132 I40E_AQ_RC_EFBIG = 22, /* File too large */ 133 }; 134 135 /* Admin Queue command opcodes */ 136 enum i40e_admin_queue_opc { 137 /* aq commands */ 138 i40e_aqc_opc_get_version = 0x0001, 139 i40e_aqc_opc_driver_version = 0x0002, 140 i40e_aqc_opc_queue_shutdown = 0x0003, 141 i40e_aqc_opc_set_pf_context = 0x0004, 142 143 /* resource ownership */ 144 i40e_aqc_opc_request_resource = 0x0008, 145 i40e_aqc_opc_release_resource = 0x0009, 146 147 i40e_aqc_opc_list_func_capabilities = 0x000A, 148 i40e_aqc_opc_list_dev_capabilities = 0x000B, 149 150 /* Proxy commands */ 151 i40e_aqc_opc_set_proxy_config = 0x0104, 152 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 153 154 /* LAA */ 155 i40e_aqc_opc_mac_address_read = 0x0107, 156 i40e_aqc_opc_mac_address_write = 0x0108, 157 158 /* PXE */ 159 i40e_aqc_opc_clear_pxe_mode = 0x0110, 160 161 /* WoL commands */ 162 i40e_aqc_opc_set_wol_filter = 0x0120, 163 i40e_aqc_opc_get_wake_reason = 0x0121, 164 i40e_aqc_opc_clear_all_wol_filters = 0x025E, 165 166 /* internal switch commands */ 167 i40e_aqc_opc_get_switch_config = 0x0200, 168 i40e_aqc_opc_add_statistics = 0x0201, 169 i40e_aqc_opc_remove_statistics = 0x0202, 170 i40e_aqc_opc_set_port_parameters = 0x0203, 171 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 172 i40e_aqc_opc_set_switch_config = 0x0205, 173 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 174 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 175 176 i40e_aqc_opc_add_vsi = 0x0210, 177 i40e_aqc_opc_update_vsi_parameters = 0x0211, 178 i40e_aqc_opc_get_vsi_parameters = 0x0212, 179 180 i40e_aqc_opc_add_pv = 0x0220, 181 i40e_aqc_opc_update_pv_parameters = 0x0221, 182 i40e_aqc_opc_get_pv_parameters = 0x0222, 183 184 i40e_aqc_opc_add_veb = 0x0230, 185 i40e_aqc_opc_update_veb_parameters = 0x0231, 186 i40e_aqc_opc_get_veb_parameters = 0x0232, 187 188 i40e_aqc_opc_delete_element = 0x0243, 189 190 i40e_aqc_opc_add_macvlan = 0x0250, 191 i40e_aqc_opc_remove_macvlan = 0x0251, 192 i40e_aqc_opc_add_vlan = 0x0252, 193 i40e_aqc_opc_remove_vlan = 0x0253, 194 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 195 i40e_aqc_opc_add_tag = 0x0255, 196 i40e_aqc_opc_remove_tag = 0x0256, 197 i40e_aqc_opc_add_multicast_etag = 0x0257, 198 i40e_aqc_opc_remove_multicast_etag = 0x0258, 199 i40e_aqc_opc_update_tag = 0x0259, 200 i40e_aqc_opc_add_control_packet_filter = 0x025A, 201 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 202 i40e_aqc_opc_add_cloud_filters = 0x025C, 203 i40e_aqc_opc_remove_cloud_filters = 0x025D, 204 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 205 i40e_aqc_opc_replace_cloud_filters = 0x025F, 206 207 i40e_aqc_opc_add_mirror_rule = 0x0260, 208 i40e_aqc_opc_delete_mirror_rule = 0x0261, 209 210 /* Dynamic Device Personalization */ 211 i40e_aqc_opc_write_personalization_profile = 0x0270, 212 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 213 214 /* DCB commands */ 215 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 216 i40e_aqc_opc_dcb_updated = 0x0302, 217 218 /* TX scheduler */ 219 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 220 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 221 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 222 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 223 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 224 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 225 226 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 227 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 228 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 229 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 230 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 231 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 232 i40e_aqc_opc_query_port_ets_config = 0x0419, 233 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 234 i40e_aqc_opc_suspend_port_tx = 0x041B, 235 i40e_aqc_opc_resume_port_tx = 0x041C, 236 i40e_aqc_opc_configure_partition_bw = 0x041D, 237 /* hmc */ 238 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 239 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 240 241 /* phy commands*/ 242 i40e_aqc_opc_get_phy_abilities = 0x0600, 243 i40e_aqc_opc_set_phy_config = 0x0601, 244 i40e_aqc_opc_set_mac_config = 0x0603, 245 i40e_aqc_opc_set_link_restart_an = 0x0605, 246 i40e_aqc_opc_get_link_status = 0x0607, 247 i40e_aqc_opc_set_phy_int_mask = 0x0613, 248 i40e_aqc_opc_get_local_advt_reg = 0x0614, 249 i40e_aqc_opc_set_local_advt_reg = 0x0615, 250 i40e_aqc_opc_get_partner_advt = 0x0616, 251 i40e_aqc_opc_set_lb_modes = 0x0618, 252 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 253 i40e_aqc_opc_set_phy_debug = 0x0622, 254 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 255 i40e_aqc_opc_run_phy_activity = 0x0626, 256 i40e_aqc_opc_set_phy_register = 0x0628, 257 i40e_aqc_opc_get_phy_register = 0x0629, 258 259 /* NVM commands */ 260 i40e_aqc_opc_nvm_read = 0x0701, 261 i40e_aqc_opc_nvm_erase = 0x0702, 262 i40e_aqc_opc_nvm_update = 0x0703, 263 i40e_aqc_opc_nvm_config_read = 0x0704, 264 i40e_aqc_opc_nvm_config_write = 0x0705, 265 i40e_aqc_opc_oem_post_update = 0x0720, 266 i40e_aqc_opc_thermal_sensor = 0x0721, 267 268 /* virtualization commands */ 269 i40e_aqc_opc_send_msg_to_pf = 0x0801, 270 i40e_aqc_opc_send_msg_to_vf = 0x0802, 271 i40e_aqc_opc_send_msg_to_peer = 0x0803, 272 273 /* alternate structure */ 274 i40e_aqc_opc_alternate_write = 0x0900, 275 i40e_aqc_opc_alternate_write_indirect = 0x0901, 276 i40e_aqc_opc_alternate_read = 0x0902, 277 i40e_aqc_opc_alternate_read_indirect = 0x0903, 278 i40e_aqc_opc_alternate_write_done = 0x0904, 279 i40e_aqc_opc_alternate_set_mode = 0x0905, 280 i40e_aqc_opc_alternate_clear_port = 0x0906, 281 282 /* LLDP commands */ 283 i40e_aqc_opc_lldp_get_mib = 0x0A00, 284 i40e_aqc_opc_lldp_update_mib = 0x0A01, 285 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 286 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 287 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 288 i40e_aqc_opc_lldp_stop = 0x0A05, 289 i40e_aqc_opc_lldp_start = 0x0A06, 290 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 291 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 292 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 293 294 /* Tunnel commands */ 295 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 296 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 297 i40e_aqc_opc_set_rss_key = 0x0B02, 298 i40e_aqc_opc_set_rss_lut = 0x0B03, 299 i40e_aqc_opc_get_rss_key = 0x0B04, 300 i40e_aqc_opc_get_rss_lut = 0x0B05, 301 302 /* Async Events */ 303 i40e_aqc_opc_event_lan_overflow = 0x1001, 304 305 /* OEM commands */ 306 i40e_aqc_opc_oem_parameter_change = 0xFE00, 307 i40e_aqc_opc_oem_device_status_change = 0xFE01, 308 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 309 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 310 311 /* debug commands */ 312 i40e_aqc_opc_debug_read_reg = 0xFF03, 313 i40e_aqc_opc_debug_write_reg = 0xFF04, 314 i40e_aqc_opc_debug_modify_reg = 0xFF07, 315 i40e_aqc_opc_debug_dump_internals = 0xFF08, 316 }; 317 318 /* command structures and indirect data structures */ 319 320 /* Structure naming conventions: 321 * - no suffix for direct command descriptor structures 322 * - _data for indirect sent data 323 * - _resp for indirect return data (data which is both will use _data) 324 * - _completion for direct return data 325 * - _element_ for repeated elements (may also be _data or _resp) 326 * 327 * Command structures are expected to overlay the params.raw member of the basic 328 * descriptor, and as such cannot exceed 16 bytes in length. 329 */ 330 331 /* This macro is used to generate a compilation error if a structure 332 * is not exactly the correct length. It gives a divide by zero error if the 333 * structure is not of the correct size, otherwise it creates an enum that is 334 * never used. 335 */ 336 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 337 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 338 339 /* This macro is used extensively to ensure that command structures are 16 340 * bytes in length as they have to map to the raw array of that size. 341 */ 342 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 343 344 /* internal (0x00XX) commands */ 345 346 /* Get version (direct 0x0001) */ 347 struct i40e_aqc_get_version { 348 __le32 rom_ver; 349 __le32 fw_build; 350 __le16 fw_major; 351 __le16 fw_minor; 352 __le16 api_major; 353 __le16 api_minor; 354 }; 355 356 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 357 358 /* Send driver version (indirect 0x0002) */ 359 struct i40e_aqc_driver_version { 360 u8 driver_major_ver; 361 u8 driver_minor_ver; 362 u8 driver_build_ver; 363 u8 driver_subbuild_ver; 364 u8 reserved[4]; 365 __le32 address_high; 366 __le32 address_low; 367 }; 368 369 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 370 371 /* Queue Shutdown (direct 0x0003) */ 372 struct i40e_aqc_queue_shutdown { 373 __le32 driver_unloading; 374 #define I40E_AQ_DRIVER_UNLOADING 0x1 375 u8 reserved[12]; 376 }; 377 378 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 379 380 /* Set PF context (0x0004, direct) */ 381 struct i40e_aqc_set_pf_context { 382 u8 pf_id; 383 u8 reserved[15]; 384 }; 385 386 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 387 388 /* Request resource ownership (direct 0x0008) 389 * Release resource ownership (direct 0x0009) 390 */ 391 #define I40E_AQ_RESOURCE_NVM 1 392 #define I40E_AQ_RESOURCE_SDP 2 393 #define I40E_AQ_RESOURCE_ACCESS_READ 1 394 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 395 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 396 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 397 398 struct i40e_aqc_request_resource { 399 __le16 resource_id; 400 __le16 access_type; 401 __le32 timeout; 402 __le32 resource_number; 403 u8 reserved[4]; 404 }; 405 406 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 407 408 /* Get function capabilities (indirect 0x000A) 409 * Get device capabilities (indirect 0x000B) 410 */ 411 struct i40e_aqc_list_capabilites { 412 u8 command_flags; 413 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 414 u8 pf_index; 415 u8 reserved[2]; 416 __le32 count; 417 __le32 addr_high; 418 __le32 addr_low; 419 }; 420 421 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 422 423 struct i40e_aqc_list_capabilities_element_resp { 424 __le16 id; 425 u8 major_rev; 426 u8 minor_rev; 427 __le32 number; 428 __le32 logical_id; 429 __le32 phys_id; 430 u8 reserved[16]; 431 }; 432 433 /* list of caps */ 434 435 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 436 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 437 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 438 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 439 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 440 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 441 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 442 #define I40E_AQ_CAP_ID_SRIOV 0x0012 443 #define I40E_AQ_CAP_ID_VF 0x0013 444 #define I40E_AQ_CAP_ID_VMDQ 0x0014 445 #define I40E_AQ_CAP_ID_8021QBG 0x0015 446 #define I40E_AQ_CAP_ID_8021QBR 0x0016 447 #define I40E_AQ_CAP_ID_VSI 0x0017 448 #define I40E_AQ_CAP_ID_DCB 0x0018 449 #define I40E_AQ_CAP_ID_FCOE 0x0021 450 #define I40E_AQ_CAP_ID_ISCSI 0x0022 451 #define I40E_AQ_CAP_ID_RSS 0x0040 452 #define I40E_AQ_CAP_ID_RXQ 0x0041 453 #define I40E_AQ_CAP_ID_TXQ 0x0042 454 #define I40E_AQ_CAP_ID_MSIX 0x0043 455 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 456 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 457 #define I40E_AQ_CAP_ID_1588 0x0046 458 #define I40E_AQ_CAP_ID_IWARP 0x0051 459 #define I40E_AQ_CAP_ID_LED 0x0061 460 #define I40E_AQ_CAP_ID_SDP 0x0062 461 #define I40E_AQ_CAP_ID_MDIO 0x0063 462 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 463 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 464 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 465 #define I40E_AQ_CAP_ID_CEM 0x00F2 466 467 /* Set CPPM Configuration (direct 0x0103) */ 468 struct i40e_aqc_cppm_configuration { 469 __le16 command_flags; 470 #define I40E_AQ_CPPM_EN_LTRC 0x0800 471 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 472 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 473 #define I40E_AQ_CPPM_EN_HPTC 0x4000 474 #define I40E_AQ_CPPM_EN_DMARC 0x8000 475 __le16 ttlx; 476 __le32 dmacr; 477 __le16 dmcth; 478 u8 hptc; 479 u8 reserved; 480 __le32 pfltrc; 481 }; 482 483 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 484 485 /* Set ARP Proxy command / response (indirect 0x0104) */ 486 struct i40e_aqc_arp_proxy_data { 487 __le16 command_flags; 488 #define I40E_AQ_ARP_INIT_IPV4 0x0800 489 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 490 #define I40E_AQ_ARP_ENA 0x2000 491 #define I40E_AQ_ARP_ADD_IPV4 0x4000 492 #define I40E_AQ_ARP_DEL_IPV4 0x8000 493 __le16 table_id; 494 __le32 enabled_offloads; 495 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 496 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 497 __le32 ip_addr; 498 u8 mac_addr[6]; 499 u8 reserved[2]; 500 }; 501 502 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 503 504 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 505 struct i40e_aqc_ns_proxy_data { 506 __le16 table_idx_mac_addr_0; 507 __le16 table_idx_mac_addr_1; 508 __le16 table_idx_ipv6_0; 509 __le16 table_idx_ipv6_1; 510 __le16 control; 511 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 512 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 513 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 514 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 515 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 516 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 517 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 518 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 519 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 520 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 521 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 522 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 523 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 524 u8 mac_addr_0[6]; 525 u8 mac_addr_1[6]; 526 u8 local_mac_addr[6]; 527 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 528 u8 ipv6_addr_1[16]; 529 }; 530 531 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 532 533 /* Manage LAA Command (0x0106) - obsolete */ 534 struct i40e_aqc_mng_laa { 535 __le16 command_flags; 536 #define I40E_AQ_LAA_FLAG_WR 0x8000 537 u8 reserved[2]; 538 __le32 sal; 539 __le16 sah; 540 u8 reserved2[6]; 541 }; 542 543 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 544 545 /* Manage MAC Address Read Command (indirect 0x0107) */ 546 struct i40e_aqc_mac_address_read { 547 __le16 command_flags; 548 #define I40E_AQC_LAN_ADDR_VALID 0x10 549 #define I40E_AQC_SAN_ADDR_VALID 0x20 550 #define I40E_AQC_PORT_ADDR_VALID 0x40 551 #define I40E_AQC_WOL_ADDR_VALID 0x80 552 #define I40E_AQC_MC_MAG_EN_VALID 0x100 553 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 554 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 555 u8 reserved[6]; 556 __le32 addr_high; 557 __le32 addr_low; 558 }; 559 560 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 561 562 struct i40e_aqc_mac_address_read_data { 563 u8 pf_lan_mac[6]; 564 u8 pf_san_mac[6]; 565 u8 port_mac[6]; 566 u8 pf_wol_mac[6]; 567 }; 568 569 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 570 571 /* Manage MAC Address Write Command (0x0108) */ 572 struct i40e_aqc_mac_address_write { 573 __le16 command_flags; 574 #define I40E_AQC_MC_MAG_EN 0x0100 575 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 576 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 577 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 578 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 579 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 580 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 581 582 __le16 mac_sah; 583 __le32 mac_sal; 584 u8 reserved[8]; 585 }; 586 587 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 588 589 /* PXE commands (0x011x) */ 590 591 /* Clear PXE Command and response (direct 0x0110) */ 592 struct i40e_aqc_clear_pxe { 593 u8 rx_cnt; 594 u8 reserved[15]; 595 }; 596 597 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 598 599 /* Set WoL Filter (0x0120) */ 600 601 struct i40e_aqc_set_wol_filter { 602 __le16 filter_index; 603 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 604 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 605 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 606 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 607 608 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 609 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 610 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 611 __le16 cmd_flags; 612 #define I40E_AQC_SET_WOL_FILTER 0x8000 613 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 614 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 615 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 616 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 617 __le16 valid_flags; 618 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 619 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 620 u8 reserved[2]; 621 __le32 address_high; 622 __le32 address_low; 623 }; 624 625 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 626 627 struct i40e_aqc_set_wol_filter_data { 628 u8 filter[128]; 629 u8 mask[16]; 630 }; 631 632 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 633 634 /* Get Wake Reason (0x0121) */ 635 636 struct i40e_aqc_get_wake_reason_completion { 637 u8 reserved_1[2]; 638 __le16 wake_reason; 639 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 640 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 641 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 642 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 643 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 644 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 645 u8 reserved_2[12]; 646 }; 647 648 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 649 650 /* Switch configuration commands (0x02xx) */ 651 652 /* Used by many indirect commands that only pass an seid and a buffer in the 653 * command 654 */ 655 struct i40e_aqc_switch_seid { 656 __le16 seid; 657 u8 reserved[6]; 658 __le32 addr_high; 659 __le32 addr_low; 660 }; 661 662 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 663 664 /* Get Switch Configuration command (indirect 0x0200) 665 * uses i40e_aqc_switch_seid for the descriptor 666 */ 667 struct i40e_aqc_get_switch_config_header_resp { 668 __le16 num_reported; 669 __le16 num_total; 670 u8 reserved[12]; 671 }; 672 673 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 674 675 struct i40e_aqc_switch_config_element_resp { 676 u8 element_type; 677 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 678 #define I40E_AQ_SW_ELEM_TYPE_PF 2 679 #define I40E_AQ_SW_ELEM_TYPE_VF 3 680 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 681 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 682 #define I40E_AQ_SW_ELEM_TYPE_PV 16 683 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 684 #define I40E_AQ_SW_ELEM_TYPE_PA 18 685 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 686 u8 revision; 687 #define I40E_AQ_SW_ELEM_REV_1 1 688 __le16 seid; 689 __le16 uplink_seid; 690 __le16 downlink_seid; 691 u8 reserved[3]; 692 u8 connection_type; 693 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 694 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 695 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 696 __le16 scheduler_id; 697 __le16 element_info; 698 }; 699 700 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 701 702 /* Get Switch Configuration (indirect 0x0200) 703 * an array of elements are returned in the response buffer 704 * the first in the array is the header, remainder are elements 705 */ 706 struct i40e_aqc_get_switch_config_resp { 707 struct i40e_aqc_get_switch_config_header_resp header; 708 struct i40e_aqc_switch_config_element_resp element[1]; 709 }; 710 711 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 712 713 /* Add Statistics (direct 0x0201) 714 * Remove Statistics (direct 0x0202) 715 */ 716 struct i40e_aqc_add_remove_statistics { 717 __le16 seid; 718 __le16 vlan; 719 __le16 stat_index; 720 u8 reserved[10]; 721 }; 722 723 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 724 725 /* Set Port Parameters command (direct 0x0203) */ 726 struct i40e_aqc_set_port_parameters { 727 __le16 command_flags; 728 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 729 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 730 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 731 __le16 bad_frame_vsi; 732 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 733 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 734 __le16 default_seid; /* reserved for command */ 735 u8 reserved[10]; 736 }; 737 738 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 739 740 /* Get Switch Resource Allocation (indirect 0x0204) */ 741 struct i40e_aqc_get_switch_resource_alloc { 742 u8 num_entries; /* reserved for command */ 743 u8 reserved[7]; 744 __le32 addr_high; 745 __le32 addr_low; 746 }; 747 748 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 749 750 /* expect an array of these structs in the response buffer */ 751 struct i40e_aqc_switch_resource_alloc_element_resp { 752 u8 resource_type; 753 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 754 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 755 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 756 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 757 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 758 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 759 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 760 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 761 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 762 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 763 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 764 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 765 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 766 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 767 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 768 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 769 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 770 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 771 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 772 u8 reserved1; 773 __le16 guaranteed; 774 __le16 total; 775 __le16 used; 776 __le16 total_unalloced; 777 u8 reserved2[6]; 778 }; 779 780 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 781 782 /* Set Switch Configuration (direct 0x0205) */ 783 struct i40e_aqc_set_switch_config { 784 __le16 flags; 785 /* flags used for both fields below */ 786 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 787 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 788 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 789 __le16 valid_flags; 790 /* The ethertype in switch_tag is dropped on ingress and used 791 * internally by the switch. Set this to zero for the default 792 * of 0x88a8 (802.1ad). Should be zero for firmware API 793 * versions lower than 1.7. 794 */ 795 __le16 switch_tag; 796 /* The ethertypes in first_tag and second_tag are used to 797 * match the outer and inner VLAN tags (respectively) when HW 798 * double VLAN tagging is enabled via the set port parameters 799 * AQ command. Otherwise these are both ignored. Set them to 800 * zero for their defaults of 0x8100 (802.1Q). Should be zero 801 * for firmware API versions lower than 1.7. 802 */ 803 __le16 first_tag; 804 __le16 second_tag; 805 u8 reserved[6]; 806 }; 807 808 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 809 810 /* Read Receive control registers (direct 0x0206) 811 * Write Receive control registers (direct 0x0207) 812 * used for accessing Rx control registers that can be 813 * slow and need special handling when under high Rx load 814 */ 815 struct i40e_aqc_rx_ctl_reg_read_write { 816 __le32 reserved1; 817 __le32 address; 818 __le32 reserved2; 819 __le32 value; 820 }; 821 822 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 823 824 /* Add VSI (indirect 0x0210) 825 * this indirect command uses struct i40e_aqc_vsi_properties_data 826 * as the indirect buffer (128 bytes) 827 * 828 * Update VSI (indirect 0x211) 829 * uses the same data structure as Add VSI 830 * 831 * Get VSI (indirect 0x0212) 832 * uses the same completion and data structure as Add VSI 833 */ 834 struct i40e_aqc_add_get_update_vsi { 835 __le16 uplink_seid; 836 u8 connection_type; 837 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 838 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 839 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 840 u8 reserved1; 841 u8 vf_id; 842 u8 reserved2; 843 __le16 vsi_flags; 844 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 845 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 846 #define I40E_AQ_VSI_TYPE_VF 0x0 847 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 848 #define I40E_AQ_VSI_TYPE_PF 0x2 849 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 850 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 851 __le32 addr_high; 852 __le32 addr_low; 853 }; 854 855 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 856 857 struct i40e_aqc_add_get_update_vsi_completion { 858 __le16 seid; 859 __le16 vsi_number; 860 __le16 vsi_used; 861 __le16 vsi_free; 862 __le32 addr_high; 863 __le32 addr_low; 864 }; 865 866 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 867 868 struct i40e_aqc_vsi_properties_data { 869 /* first 96 byte are written by SW */ 870 __le16 valid_sections; 871 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 872 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 873 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 874 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 875 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 876 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 877 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 878 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 879 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 880 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 881 /* switch section */ 882 __le16 switch_id; /* 12bit id combined with flags below */ 883 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 884 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 885 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 886 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 887 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 888 u8 sw_reserved[2]; 889 /* security section */ 890 u8 sec_flags; 891 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 892 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 893 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 894 u8 sec_reserved; 895 /* VLAN section */ 896 __le16 pvid; /* VLANS include priority bits */ 897 __le16 fcoe_pvid; 898 u8 port_vlan_flags; 899 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 900 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 901 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 902 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 903 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 904 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 905 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 906 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 907 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 908 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 909 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 910 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 911 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 912 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 913 u8 pvlan_reserved[3]; 914 /* ingress egress up sections */ 915 __le32 ingress_table; /* bitmap, 3 bits per up */ 916 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 917 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 918 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 919 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 920 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 921 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 922 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 923 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 924 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 925 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 926 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 927 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 928 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 929 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 930 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 931 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 932 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 933 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 934 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 935 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 936 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 937 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 938 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 939 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 940 __le32 egress_table; /* same defines as for ingress table */ 941 /* cascaded PV section */ 942 __le16 cas_pv_tag; 943 u8 cas_pv_flags; 944 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 945 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 946 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 947 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 948 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 949 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 950 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 951 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 952 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 953 u8 cas_pv_reserved; 954 /* queue mapping section */ 955 __le16 mapping_flags; 956 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 957 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 958 __le16 queue_mapping[16]; 959 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 960 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 961 __le16 tc_mapping[8]; 962 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 963 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 964 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 965 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 966 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 967 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 968 /* queueing option section */ 969 u8 queueing_opt_flags; 970 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 971 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 972 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 973 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 974 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 975 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 976 u8 queueing_opt_reserved[3]; 977 /* scheduler section */ 978 u8 up_enable_bits; 979 u8 sched_reserved; 980 /* outer up section */ 981 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 982 u8 cmd_reserved[8]; 983 /* last 32 bytes are written by FW */ 984 __le16 qs_handle[8]; 985 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 986 __le16 stat_counter_idx; 987 __le16 sched_id; 988 u8 resp_reserved[12]; 989 }; 990 991 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 992 993 /* Add Port Virtualizer (direct 0x0220) 994 * also used for update PV (direct 0x0221) but only flags are used 995 * (IS_CTRL_PORT only works on add PV) 996 */ 997 struct i40e_aqc_add_update_pv { 998 __le16 command_flags; 999 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1000 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1001 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1002 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1003 __le16 uplink_seid; 1004 __le16 connected_seid; 1005 u8 reserved[10]; 1006 }; 1007 1008 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1009 1010 struct i40e_aqc_add_update_pv_completion { 1011 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1012 __le16 pv_seid; 1013 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1014 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1015 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1016 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1017 u8 reserved[14]; 1018 }; 1019 1020 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1021 1022 /* Get PV Params (direct 0x0222) 1023 * uses i40e_aqc_switch_seid for the descriptor 1024 */ 1025 1026 struct i40e_aqc_get_pv_params_completion { 1027 __le16 seid; 1028 __le16 default_stag; 1029 __le16 pv_flags; /* same flags as add_pv */ 1030 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1031 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1032 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1033 u8 reserved[8]; 1034 __le16 default_port_seid; 1035 }; 1036 1037 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1038 1039 /* Add VEB (direct 0x0230) */ 1040 struct i40e_aqc_add_veb { 1041 __le16 uplink_seid; 1042 __le16 downlink_seid; 1043 __le16 veb_flags; 1044 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1045 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1046 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1047 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1048 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1049 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1050 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1051 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1052 u8 enable_tcs; 1053 u8 reserved[9]; 1054 }; 1055 1056 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1057 1058 struct i40e_aqc_add_veb_completion { 1059 u8 reserved[6]; 1060 __le16 switch_seid; 1061 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1062 __le16 veb_seid; 1063 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1064 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1065 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1066 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1067 __le16 statistic_index; 1068 __le16 vebs_used; 1069 __le16 vebs_free; 1070 }; 1071 1072 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1073 1074 /* Get VEB Parameters (direct 0x0232) 1075 * uses i40e_aqc_switch_seid for the descriptor 1076 */ 1077 struct i40e_aqc_get_veb_parameters_completion { 1078 __le16 seid; 1079 __le16 switch_id; 1080 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1081 __le16 statistic_index; 1082 __le16 vebs_used; 1083 __le16 vebs_free; 1084 u8 reserved[4]; 1085 }; 1086 1087 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1088 1089 /* Delete Element (direct 0x0243) 1090 * uses the generic i40e_aqc_switch_seid 1091 */ 1092 1093 /* Add MAC-VLAN (indirect 0x0250) */ 1094 1095 /* used for the command for most vlan commands */ 1096 struct i40e_aqc_macvlan { 1097 __le16 num_addresses; 1098 __le16 seid[3]; 1099 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1100 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1101 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1102 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1103 __le32 addr_high; 1104 __le32 addr_low; 1105 }; 1106 1107 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1108 1109 /* indirect data for command and response */ 1110 struct i40e_aqc_add_macvlan_element_data { 1111 u8 mac_addr[6]; 1112 __le16 vlan_tag; 1113 __le16 flags; 1114 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1115 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1116 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1117 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1118 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1119 __le16 queue_number; 1120 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1121 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1122 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1123 /* response section */ 1124 u8 match_method; 1125 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1126 #define I40E_AQC_MM_HASH_MATCH 0x02 1127 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1128 u8 reserved1[3]; 1129 }; 1130 1131 struct i40e_aqc_add_remove_macvlan_completion { 1132 __le16 perfect_mac_used; 1133 __le16 perfect_mac_free; 1134 __le16 unicast_hash_free; 1135 __le16 multicast_hash_free; 1136 __le32 addr_high; 1137 __le32 addr_low; 1138 }; 1139 1140 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1141 1142 /* Remove MAC-VLAN (indirect 0x0251) 1143 * uses i40e_aqc_macvlan for the descriptor 1144 * data points to an array of num_addresses of elements 1145 */ 1146 1147 struct i40e_aqc_remove_macvlan_element_data { 1148 u8 mac_addr[6]; 1149 __le16 vlan_tag; 1150 u8 flags; 1151 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1152 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1153 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1154 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1155 u8 reserved[3]; 1156 /* reply section */ 1157 u8 error_code; 1158 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1159 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1160 u8 reply_reserved[3]; 1161 }; 1162 1163 /* Add VLAN (indirect 0x0252) 1164 * Remove VLAN (indirect 0x0253) 1165 * use the generic i40e_aqc_macvlan for the command 1166 */ 1167 struct i40e_aqc_add_remove_vlan_element_data { 1168 __le16 vlan_tag; 1169 u8 vlan_flags; 1170 /* flags for add VLAN */ 1171 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1172 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1173 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1174 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1175 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1176 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1177 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1178 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1179 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1180 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1181 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1182 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1183 /* flags for remove VLAN */ 1184 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1185 u8 reserved; 1186 u8 result; 1187 /* flags for add VLAN */ 1188 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1189 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1190 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1191 /* flags for remove VLAN */ 1192 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1193 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1194 u8 reserved1[3]; 1195 }; 1196 1197 struct i40e_aqc_add_remove_vlan_completion { 1198 u8 reserved[4]; 1199 __le16 vlans_used; 1200 __le16 vlans_free; 1201 __le32 addr_high; 1202 __le32 addr_low; 1203 }; 1204 1205 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1206 struct i40e_aqc_set_vsi_promiscuous_modes { 1207 __le16 promiscuous_flags; 1208 __le16 valid_flags; 1209 /* flags used for both fields above */ 1210 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1211 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1212 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1213 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1214 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1215 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1216 __le16 seid; 1217 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1218 __le16 vlan_tag; 1219 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1220 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1221 u8 reserved[8]; 1222 }; 1223 1224 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1225 1226 /* Add S/E-tag command (direct 0x0255) 1227 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1228 */ 1229 struct i40e_aqc_add_tag { 1230 __le16 flags; 1231 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1232 __le16 seid; 1233 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1234 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1235 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1236 __le16 tag; 1237 __le16 queue_number; 1238 u8 reserved[8]; 1239 }; 1240 1241 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1242 1243 struct i40e_aqc_add_remove_tag_completion { 1244 u8 reserved[12]; 1245 __le16 tags_used; 1246 __le16 tags_free; 1247 }; 1248 1249 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1250 1251 /* Remove S/E-tag command (direct 0x0256) 1252 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1253 */ 1254 struct i40e_aqc_remove_tag { 1255 __le16 seid; 1256 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1257 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1258 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1259 __le16 tag; 1260 u8 reserved[12]; 1261 }; 1262 1263 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1264 1265 /* Add multicast E-Tag (direct 0x0257) 1266 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1267 * and no external data 1268 */ 1269 struct i40e_aqc_add_remove_mcast_etag { 1270 __le16 pv_seid; 1271 __le16 etag; 1272 u8 num_unicast_etags; 1273 u8 reserved[3]; 1274 __le32 addr_high; /* address of array of 2-byte s-tags */ 1275 __le32 addr_low; 1276 }; 1277 1278 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1279 1280 struct i40e_aqc_add_remove_mcast_etag_completion { 1281 u8 reserved[4]; 1282 __le16 mcast_etags_used; 1283 __le16 mcast_etags_free; 1284 __le32 addr_high; 1285 __le32 addr_low; 1286 1287 }; 1288 1289 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1290 1291 /* Update S/E-Tag (direct 0x0259) */ 1292 struct i40e_aqc_update_tag { 1293 __le16 seid; 1294 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1295 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1296 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1297 __le16 old_tag; 1298 __le16 new_tag; 1299 u8 reserved[10]; 1300 }; 1301 1302 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1303 1304 struct i40e_aqc_update_tag_completion { 1305 u8 reserved[12]; 1306 __le16 tags_used; 1307 __le16 tags_free; 1308 }; 1309 1310 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1311 1312 /* Add Control Packet filter (direct 0x025A) 1313 * Remove Control Packet filter (direct 0x025B) 1314 * uses the i40e_aqc_add_oveb_cloud, 1315 * and the generic direct completion structure 1316 */ 1317 struct i40e_aqc_add_remove_control_packet_filter { 1318 u8 mac[6]; 1319 __le16 etype; 1320 __le16 flags; 1321 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1322 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1323 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1324 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1325 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1326 __le16 seid; 1327 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1328 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1329 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1330 __le16 queue; 1331 u8 reserved[2]; 1332 }; 1333 1334 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1335 1336 struct i40e_aqc_add_remove_control_packet_filter_completion { 1337 __le16 mac_etype_used; 1338 __le16 etype_used; 1339 __le16 mac_etype_free; 1340 __le16 etype_free; 1341 u8 reserved[8]; 1342 }; 1343 1344 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1345 1346 /* Add Cloud filters (indirect 0x025C) 1347 * Remove Cloud filters (indirect 0x025D) 1348 * uses the i40e_aqc_add_remove_cloud_filters, 1349 * and the generic indirect completion structure 1350 */ 1351 struct i40e_aqc_add_remove_cloud_filters { 1352 u8 num_filters; 1353 u8 reserved; 1354 __le16 seid; 1355 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1356 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1357 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1358 u8 big_buffer_flag; 1359 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1 1360 u8 reserved2[3]; 1361 __le32 addr_high; 1362 __le32 addr_low; 1363 }; 1364 1365 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1366 1367 struct i40e_aqc_add_remove_cloud_filters_element_data { 1368 u8 outer_mac[6]; 1369 u8 inner_mac[6]; 1370 __le16 inner_vlan; 1371 union { 1372 struct { 1373 u8 reserved[12]; 1374 u8 data[4]; 1375 } v4; 1376 struct { 1377 u8 data[16]; 1378 } v6; 1379 } ipaddr; 1380 __le16 flags; 1381 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1382 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1383 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1384 /* 0x0000 reserved */ 1385 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1386 /* 0x0002 reserved */ 1387 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1388 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1389 /* 0x0005 reserved */ 1390 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1391 /* 0x0007 reserved */ 1392 /* 0x0008 reserved */ 1393 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1394 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1395 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1396 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1397 /* 0x0010 to 0x0017 is for custom filters */ 1398 1399 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1400 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1401 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1402 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1403 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1404 1405 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1406 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1407 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1408 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1409 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1410 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1411 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1412 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1413 1414 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1415 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1416 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1417 1418 __le32 tenant_id; 1419 u8 reserved[4]; 1420 __le16 queue_number; 1421 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1422 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1423 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1424 u8 reserved2[14]; 1425 /* response section */ 1426 u8 allocation_result; 1427 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1428 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1429 u8 response_reserved[7]; 1430 }; 1431 1432 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when 1433 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. refer to 1434 * DCR288 1435 */ 1436 struct i40e_aqc_add_rm_cloud_filt_elem_ext { 1437 struct i40e_aqc_add_remove_cloud_filters_element_data element; 1438 u16 general_fields[32]; 1439 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1440 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1441 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1442 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1443 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1444 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1445 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1446 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1447 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1470 }; 1471 1472 struct i40e_aqc_remove_cloud_filters_completion { 1473 __le16 perfect_ovlan_used; 1474 __le16 perfect_ovlan_free; 1475 __le16 vlan_used; 1476 __le16 vlan_free; 1477 __le32 addr_high; 1478 __le32 addr_low; 1479 }; 1480 1481 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1482 1483 /* Replace filter Command 0x025F 1484 * uses the i40e_aqc_replace_cloud_filters, 1485 * and the generic indirect completion structure 1486 */ 1487 struct i40e_filter_data { 1488 u8 filter_type; 1489 u8 input[3]; 1490 }; 1491 1492 struct i40e_aqc_replace_cloud_filters_cmd { 1493 u8 valid_flags; 1494 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1495 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1496 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1497 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1498 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1499 u8 old_filter_type; 1500 u8 new_filter_type; 1501 u8 tr_bit; 1502 u8 reserved[4]; 1503 __le32 addr_high; 1504 __le32 addr_low; 1505 }; 1506 1507 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1508 u8 data[32]; 1509 /* Filter type INPUT codes*/ 1510 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1511 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL) 1512 1513 /* Field Vector offsets */ 1514 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1515 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1516 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1517 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1518 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1519 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1520 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1521 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1522 /* big FLU */ 1523 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1524 /* big FLU */ 1525 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1526 1527 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1528 struct i40e_filter_data filters[8]; 1529 }; 1530 1531 /* Add Mirror Rule (indirect or direct 0x0260) 1532 * Delete Mirror Rule (indirect or direct 0x0261) 1533 * note: some rule types (4,5) do not use an external buffer. 1534 * take care to set the flags correctly. 1535 */ 1536 struct i40e_aqc_add_delete_mirror_rule { 1537 __le16 seid; 1538 __le16 rule_type; 1539 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1540 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1541 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1542 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1543 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1544 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1545 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1546 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1547 __le16 num_entries; 1548 __le16 destination; /* VSI for add, rule id for delete */ 1549 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1550 __le32 addr_low; 1551 }; 1552 1553 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1554 1555 struct i40e_aqc_add_delete_mirror_rule_completion { 1556 u8 reserved[2]; 1557 __le16 rule_id; /* only used on add */ 1558 __le16 mirror_rules_used; 1559 __le16 mirror_rules_free; 1560 __le32 addr_high; 1561 __le32 addr_low; 1562 }; 1563 1564 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1565 1566 /* Dynamic Device Personalization */ 1567 struct i40e_aqc_write_personalization_profile { 1568 u8 flags; 1569 u8 reserved[3]; 1570 __le32 profile_track_id; 1571 __le32 addr_high; 1572 __le32 addr_low; 1573 }; 1574 1575 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1576 1577 struct i40e_aqc_write_ddp_resp { 1578 __le32 error_offset; 1579 __le32 error_info; 1580 __le32 addr_high; 1581 __le32 addr_low; 1582 }; 1583 1584 struct i40e_aqc_get_applied_profiles { 1585 u8 flags; 1586 #define I40E_AQC_GET_DDP_GET_CONF 0x1 1587 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 1588 u8 rsv[3]; 1589 __le32 reserved; 1590 __le32 addr_high; 1591 __le32 addr_low; 1592 }; 1593 1594 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1595 1596 /* DCB 0x03xx*/ 1597 1598 /* PFC Ignore (direct 0x0301) 1599 * the command and response use the same descriptor structure 1600 */ 1601 struct i40e_aqc_pfc_ignore { 1602 u8 tc_bitmap; 1603 u8 command_flags; /* unused on response */ 1604 #define I40E_AQC_PFC_IGNORE_SET 0x80 1605 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1606 u8 reserved[14]; 1607 }; 1608 1609 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1610 1611 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1612 * with no parameters 1613 */ 1614 1615 /* TX scheduler 0x04xx */ 1616 1617 /* Almost all the indirect commands use 1618 * this generic struct to pass the SEID in param0 1619 */ 1620 struct i40e_aqc_tx_sched_ind { 1621 __le16 vsi_seid; 1622 u8 reserved[6]; 1623 __le32 addr_high; 1624 __le32 addr_low; 1625 }; 1626 1627 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1628 1629 /* Several commands respond with a set of queue set handles */ 1630 struct i40e_aqc_qs_handles_resp { 1631 __le16 qs_handles[8]; 1632 }; 1633 1634 /* Configure VSI BW limits (direct 0x0400) */ 1635 struct i40e_aqc_configure_vsi_bw_limit { 1636 __le16 vsi_seid; 1637 u8 reserved[2]; 1638 __le16 credit; 1639 u8 reserved1[2]; 1640 u8 max_credit; /* 0-3, limit = 2^max */ 1641 u8 reserved2[7]; 1642 }; 1643 1644 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1645 1646 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1647 * responds with i40e_aqc_qs_handles_resp 1648 */ 1649 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1650 u8 tc_valid_bits; 1651 u8 reserved[15]; 1652 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1653 1654 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1655 __le16 tc_bw_max[2]; 1656 u8 reserved1[28]; 1657 }; 1658 1659 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1660 1661 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1662 * responds with i40e_aqc_qs_handles_resp 1663 */ 1664 struct i40e_aqc_configure_vsi_tc_bw_data { 1665 u8 tc_valid_bits; 1666 u8 reserved[3]; 1667 u8 tc_bw_credits[8]; 1668 u8 reserved1[4]; 1669 __le16 qs_handles[8]; 1670 }; 1671 1672 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1673 1674 /* Query vsi bw configuration (indirect 0x0408) */ 1675 struct i40e_aqc_query_vsi_bw_config_resp { 1676 u8 tc_valid_bits; 1677 u8 tc_suspended_bits; 1678 u8 reserved[14]; 1679 __le16 qs_handles[8]; 1680 u8 reserved1[4]; 1681 __le16 port_bw_limit; 1682 u8 reserved2[2]; 1683 u8 max_bw; /* 0-3, limit = 2^max */ 1684 u8 reserved3[23]; 1685 }; 1686 1687 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1688 1689 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1690 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1691 u8 tc_valid_bits; 1692 u8 reserved[3]; 1693 u8 share_credits[8]; 1694 __le16 credits[8]; 1695 1696 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1697 __le16 tc_bw_max[2]; 1698 }; 1699 1700 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1701 1702 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1703 struct i40e_aqc_configure_switching_comp_bw_limit { 1704 __le16 seid; 1705 u8 reserved[2]; 1706 __le16 credit; 1707 u8 reserved1[2]; 1708 u8 max_bw; /* 0-3, limit = 2^max */ 1709 u8 reserved2[7]; 1710 }; 1711 1712 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1713 1714 /* Enable Physical Port ETS (indirect 0x0413) 1715 * Modify Physical Port ETS (indirect 0x0414) 1716 * Disable Physical Port ETS (indirect 0x0415) 1717 */ 1718 struct i40e_aqc_configure_switching_comp_ets_data { 1719 u8 reserved[4]; 1720 u8 tc_valid_bits; 1721 u8 seepage; 1722 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1723 u8 tc_strict_priority_flags; 1724 u8 reserved1[17]; 1725 u8 tc_bw_share_credits[8]; 1726 u8 reserved2[96]; 1727 }; 1728 1729 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1730 1731 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1732 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1733 u8 tc_valid_bits; 1734 u8 reserved[15]; 1735 __le16 tc_bw_credit[8]; 1736 1737 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1738 __le16 tc_bw_max[2]; 1739 u8 reserved1[28]; 1740 }; 1741 1742 I40E_CHECK_STRUCT_LEN(0x40, 1743 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1744 1745 /* Configure Switching Component Bandwidth Allocation per Tc 1746 * (indirect 0x0417) 1747 */ 1748 struct i40e_aqc_configure_switching_comp_bw_config_data { 1749 u8 tc_valid_bits; 1750 u8 reserved[2]; 1751 u8 absolute_credits; /* bool */ 1752 u8 tc_bw_share_credits[8]; 1753 u8 reserved1[20]; 1754 }; 1755 1756 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1757 1758 /* Query Switching Component Configuration (indirect 0x0418) */ 1759 struct i40e_aqc_query_switching_comp_ets_config_resp { 1760 u8 tc_valid_bits; 1761 u8 reserved[35]; 1762 __le16 port_bw_limit; 1763 u8 reserved1[2]; 1764 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1765 u8 reserved2[23]; 1766 }; 1767 1768 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1769 1770 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1771 struct i40e_aqc_query_port_ets_config_resp { 1772 u8 reserved[4]; 1773 u8 tc_valid_bits; 1774 u8 reserved1; 1775 u8 tc_strict_priority_bits; 1776 u8 reserved2; 1777 u8 tc_bw_share_credits[8]; 1778 __le16 tc_bw_limits[8]; 1779 1780 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1781 __le16 tc_bw_max[2]; 1782 u8 reserved3[32]; 1783 }; 1784 1785 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1786 1787 /* Query Switching Component Bandwidth Allocation per Traffic Type 1788 * (indirect 0x041A) 1789 */ 1790 struct i40e_aqc_query_switching_comp_bw_config_resp { 1791 u8 tc_valid_bits; 1792 u8 reserved[2]; 1793 u8 absolute_credits_enable; /* bool */ 1794 u8 tc_bw_share_credits[8]; 1795 __le16 tc_bw_limits[8]; 1796 1797 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1798 __le16 tc_bw_max[2]; 1799 }; 1800 1801 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1802 1803 /* Suspend/resume port TX traffic 1804 * (direct 0x041B and 0x041C) uses the generic SEID struct 1805 */ 1806 1807 /* Configure partition BW 1808 * (indirect 0x041D) 1809 */ 1810 struct i40e_aqc_configure_partition_bw_data { 1811 __le16 pf_valid_bits; 1812 u8 min_bw[16]; /* guaranteed bandwidth */ 1813 u8 max_bw[16]; /* bandwidth limit */ 1814 }; 1815 1816 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1817 1818 /* Get and set the active HMC resource profile and status. 1819 * (direct 0x0500) and (direct 0x0501) 1820 */ 1821 struct i40e_aq_get_set_hmc_resource_profile { 1822 u8 pm_profile; 1823 u8 pe_vf_enabled; 1824 u8 reserved[14]; 1825 }; 1826 1827 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1828 1829 enum i40e_aq_hmc_profile { 1830 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1831 I40E_HMC_PROFILE_DEFAULT = 1, 1832 I40E_HMC_PROFILE_FAVOR_VF = 2, 1833 I40E_HMC_PROFILE_EQUAL = 3, 1834 }; 1835 1836 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1837 1838 /* set in param0 for get phy abilities to report qualified modules */ 1839 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1840 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1841 1842 enum i40e_aq_phy_type { 1843 I40E_PHY_TYPE_SGMII = 0x0, 1844 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1845 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1846 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1847 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1848 I40E_PHY_TYPE_XAUI = 0x5, 1849 I40E_PHY_TYPE_XFI = 0x6, 1850 I40E_PHY_TYPE_SFI = 0x7, 1851 I40E_PHY_TYPE_XLAUI = 0x8, 1852 I40E_PHY_TYPE_XLPPI = 0x9, 1853 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1854 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1855 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1856 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1857 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1858 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1859 I40E_PHY_TYPE_100BASE_TX = 0x11, 1860 I40E_PHY_TYPE_1000BASE_T = 0x12, 1861 I40E_PHY_TYPE_10GBASE_T = 0x13, 1862 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1863 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1864 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1865 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1866 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1867 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1868 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1869 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1870 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1871 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1872 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1873 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1874 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1875 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1876 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1877 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1878 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1879 I40E_PHY_TYPE_MAX, 1880 I40E_PHY_TYPE_EMPTY = 0xFE, 1881 I40E_PHY_TYPE_DEFAULT = 0xFF, 1882 }; 1883 1884 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1885 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1886 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1887 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1888 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1889 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1890 1891 enum i40e_aq_link_speed { 1892 I40E_LINK_SPEED_UNKNOWN = 0, 1893 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1894 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1895 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1896 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1897 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1898 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 1899 }; 1900 1901 struct i40e_aqc_module_desc { 1902 u8 oui[3]; 1903 u8 reserved1; 1904 u8 part_number[16]; 1905 u8 revision[4]; 1906 u8 reserved2[8]; 1907 }; 1908 1909 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1910 1911 struct i40e_aq_get_phy_abilities_resp { 1912 __le32 phy_type; /* bitmap using the above enum for offsets */ 1913 u8 link_speed; /* bitmap using the above enum bit patterns */ 1914 u8 abilities; 1915 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1916 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1917 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1918 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1919 #define I40E_AQ_PHY_AN_ENABLED 0x10 1920 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1921 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1922 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1923 __le16 eee_capability; 1924 #define I40E_AQ_EEE_100BASE_TX 0x0002 1925 #define I40E_AQ_EEE_1000BASE_T 0x0004 1926 #define I40E_AQ_EEE_10GBASE_T 0x0008 1927 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1928 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1929 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1930 __le32 eeer_val; 1931 u8 d3_lpan; 1932 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1933 u8 phy_type_ext; 1934 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 1935 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 1936 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1937 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1938 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1939 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1940 u8 fec_cfg_curr_mod_ext_info; 1941 #define I40E_AQ_ENABLE_FEC_KR 0x01 1942 #define I40E_AQ_ENABLE_FEC_RS 0x02 1943 #define I40E_AQ_REQUEST_FEC_KR 0x04 1944 #define I40E_AQ_REQUEST_FEC_RS 0x08 1945 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1946 #define I40E_AQ_FEC 1947 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1948 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1949 1950 u8 ext_comp_code; 1951 u8 phy_id[4]; 1952 u8 module_type[3]; 1953 u8 qualified_module_count; 1954 #define I40E_AQ_PHY_MAX_QMS 16 1955 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1956 }; 1957 1958 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1959 1960 /* Set PHY Config (direct 0x0601) */ 1961 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1962 __le32 phy_type; 1963 u8 link_speed; 1964 u8 abilities; 1965 /* bits 0-2 use the values from get_phy_abilities_resp */ 1966 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1967 #define I40E_AQ_PHY_ENABLE_AN 0x10 1968 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1969 __le16 eee_capability; 1970 __le32 eeer; 1971 u8 low_power_ctrl; 1972 u8 phy_type_ext; 1973 u8 fec_config; 1974 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 1975 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 1976 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 1977 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 1978 #define I40E_AQ_SET_FEC_AUTO BIT(4) 1979 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 1980 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 1981 u8 reserved; 1982 }; 1983 1984 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1985 1986 /* Set MAC Config command data structure (direct 0x0603) */ 1987 struct i40e_aq_set_mac_config { 1988 __le16 max_frame_size; 1989 u8 params; 1990 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1991 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1992 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1993 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1994 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1995 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1996 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1997 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1998 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1999 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2000 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2001 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2002 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2003 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2004 u8 tx_timer_priority; /* bitmap */ 2005 __le16 tx_timer_value; 2006 __le16 fc_refresh_threshold; 2007 u8 reserved[8]; 2008 }; 2009 2010 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2011 2012 /* Restart Auto-Negotiation (direct 0x605) */ 2013 struct i40e_aqc_set_link_restart_an { 2014 u8 command; 2015 #define I40E_AQ_PHY_RESTART_AN 0x02 2016 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2017 u8 reserved[15]; 2018 }; 2019 2020 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2021 2022 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2023 struct i40e_aqc_get_link_status { 2024 __le16 command_flags; /* only field set on command */ 2025 #define I40E_AQ_LSE_MASK 0x3 2026 #define I40E_AQ_LSE_NOP 0x0 2027 #define I40E_AQ_LSE_DISABLE 0x2 2028 #define I40E_AQ_LSE_ENABLE 0x3 2029 /* only response uses this flag */ 2030 #define I40E_AQ_LSE_IS_ENABLED 0x1 2031 u8 phy_type; /* i40e_aq_phy_type */ 2032 u8 link_speed; /* i40e_aq_link_speed */ 2033 u8 link_info; 2034 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2035 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2036 #define I40E_AQ_LINK_FAULT 0x02 2037 #define I40E_AQ_LINK_FAULT_TX 0x04 2038 #define I40E_AQ_LINK_FAULT_RX 0x08 2039 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2040 #define I40E_AQ_LINK_UP_PORT 0x20 2041 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2042 #define I40E_AQ_SIGNAL_DETECT 0x80 2043 u8 an_info; 2044 #define I40E_AQ_AN_COMPLETED 0x01 2045 #define I40E_AQ_LP_AN_ABILITY 0x02 2046 #define I40E_AQ_PD_FAULT 0x04 2047 #define I40E_AQ_FEC_EN 0x08 2048 #define I40E_AQ_PHY_LOW_POWER 0x10 2049 #define I40E_AQ_LINK_PAUSE_TX 0x20 2050 #define I40E_AQ_LINK_PAUSE_RX 0x40 2051 #define I40E_AQ_QUALIFIED_MODULE 0x80 2052 u8 ext_info; 2053 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2054 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2055 #define I40E_AQ_LINK_TX_SHIFT 0x02 2056 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2057 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2058 #define I40E_AQ_LINK_TX_DRAINED 0x01 2059 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2060 #define I40E_AQ_LINK_FORCED_40G 0x10 2061 /* 25G Error Codes */ 2062 #define I40E_AQ_25G_NO_ERR 0X00 2063 #define I40E_AQ_25G_NOT_PRESENT 0X01 2064 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2065 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2066 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2067 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2068 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2069 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2070 #define I40E_AQ_LOOPBACK_MASK 0x07 2071 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2072 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2073 __le16 max_frame_size; 2074 u8 config; 2075 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2076 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2077 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2078 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2079 union { 2080 struct { 2081 u8 power_desc; 2082 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2083 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2084 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2085 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2086 #define I40E_AQ_PWR_CLASS_MASK 0x03 2087 u8 reserved[4]; 2088 }; 2089 struct { 2090 u8 link_type[4]; 2091 u8 link_type_ext; 2092 }; 2093 }; 2094 }; 2095 2096 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2097 2098 /* Set event mask command (direct 0x613) */ 2099 struct i40e_aqc_set_phy_int_mask { 2100 u8 reserved[8]; 2101 __le16 event_mask; 2102 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2103 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2104 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2105 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2106 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2107 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2108 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2109 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2110 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2111 u8 reserved1[6]; 2112 }; 2113 2114 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2115 2116 /* Get Local AN advt register (direct 0x0614) 2117 * Set Local AN advt register (direct 0x0615) 2118 * Get Link Partner AN advt register (direct 0x0616) 2119 */ 2120 struct i40e_aqc_an_advt_reg { 2121 __le32 local_an_reg0; 2122 __le16 local_an_reg1; 2123 u8 reserved[10]; 2124 }; 2125 2126 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2127 2128 /* Set Loopback mode (0x0618) */ 2129 struct i40e_aqc_set_lb_mode { 2130 __le16 lb_mode; 2131 #define I40E_AQ_LB_PHY_LOCAL 0x01 2132 #define I40E_AQ_LB_PHY_REMOTE 0x02 2133 #define I40E_AQ_LB_MAC_LOCAL 0x04 2134 u8 reserved[14]; 2135 }; 2136 2137 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2138 2139 /* Set PHY Debug command (0x0622) */ 2140 struct i40e_aqc_set_phy_debug { 2141 u8 command_flags; 2142 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2143 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2144 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2145 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2146 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2147 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2148 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2149 /* Disable link manageability on a single port */ 2150 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2151 /* Disable link manageability on all ports needs both bits 4 and 5 */ 2152 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2153 u8 reserved[15]; 2154 }; 2155 2156 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2157 2158 enum i40e_aq_phy_reg_type { 2159 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2160 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2161 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2162 }; 2163 2164 /* Run PHY Activity (0x0626) */ 2165 struct i40e_aqc_run_phy_activity { 2166 __le16 activity_id; 2167 u8 flags; 2168 u8 reserved1; 2169 __le32 control; 2170 __le32 data; 2171 u8 reserved2[4]; 2172 }; 2173 2174 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2175 2176 /* Set PHY Register command (0x0628) */ 2177 /* Get PHY Register command (0x0629) */ 2178 struct i40e_aqc_phy_register_access { 2179 u8 phy_interface; 2180 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2181 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2182 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2183 u8 dev_addres; 2184 u8 reserved1[2]; 2185 u32 reg_address; 2186 u32 reg_value; 2187 u8 reserved2[4]; 2188 }; 2189 2190 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2191 2192 /* NVM Read command (indirect 0x0701) 2193 * NVM Erase commands (direct 0x0702) 2194 * NVM Update commands (indirect 0x0703) 2195 */ 2196 struct i40e_aqc_nvm_update { 2197 u8 command_flags; 2198 #define I40E_AQ_NVM_LAST_CMD 0x01 2199 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2200 u8 module_pointer; 2201 __le16 length; 2202 __le32 offset; 2203 __le32 addr_high; 2204 __le32 addr_low; 2205 }; 2206 2207 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2208 2209 /* NVM Config Read (indirect 0x0704) */ 2210 struct i40e_aqc_nvm_config_read { 2211 __le16 cmd_flags; 2212 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2213 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2214 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2215 __le16 element_count; 2216 __le16 element_id; /* Feature/field ID */ 2217 __le16 element_id_msw; /* MSWord of field ID */ 2218 __le32 address_high; 2219 __le32 address_low; 2220 }; 2221 2222 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2223 2224 /* NVM Config Write (indirect 0x0705) */ 2225 struct i40e_aqc_nvm_config_write { 2226 __le16 cmd_flags; 2227 __le16 element_count; 2228 u8 reserved[4]; 2229 __le32 address_high; 2230 __le32 address_low; 2231 }; 2232 2233 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2234 2235 /* Used for 0x0704 as well as for 0x0705 commands */ 2236 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2237 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2238 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2239 #define I40E_AQ_ANVM_FEATURE 0 2240 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2241 struct i40e_aqc_nvm_config_data_feature { 2242 __le16 feature_id; 2243 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2244 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2245 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2246 __le16 feature_options; 2247 __le16 feature_selection; 2248 }; 2249 2250 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2251 2252 struct i40e_aqc_nvm_config_data_immediate_field { 2253 __le32 field_id; 2254 __le32 field_value; 2255 __le16 field_options; 2256 __le16 reserved; 2257 }; 2258 2259 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2260 2261 /* OEM Post Update (indirect 0x0720) 2262 * no command data struct used 2263 */ 2264 struct i40e_aqc_nvm_oem_post_update { 2265 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2266 u8 sel_data; 2267 u8 reserved[7]; 2268 }; 2269 2270 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2271 2272 struct i40e_aqc_nvm_oem_post_update_buffer { 2273 u8 str_len; 2274 u8 dev_addr; 2275 __le16 eeprom_addr; 2276 u8 data[36]; 2277 }; 2278 2279 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2280 2281 /* Thermal Sensor (indirect 0x0721) 2282 * read or set thermal sensor configs and values 2283 * takes a sensor and command specific data buffer, not detailed here 2284 */ 2285 struct i40e_aqc_thermal_sensor { 2286 u8 sensor_action; 2287 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2288 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2289 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2290 u8 reserved[7]; 2291 __le32 addr_high; 2292 __le32 addr_low; 2293 }; 2294 2295 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2296 2297 /* Send to PF command (indirect 0x0801) id is only used by PF 2298 * Send to VF command (indirect 0x0802) id is only used by PF 2299 * Send to Peer PF command (indirect 0x0803) 2300 */ 2301 struct i40e_aqc_pf_vf_message { 2302 __le32 id; 2303 u8 reserved[4]; 2304 __le32 addr_high; 2305 __le32 addr_low; 2306 }; 2307 2308 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2309 2310 /* Alternate structure */ 2311 2312 /* Direct write (direct 0x0900) 2313 * Direct read (direct 0x0902) 2314 */ 2315 struct i40e_aqc_alternate_write { 2316 __le32 address0; 2317 __le32 data0; 2318 __le32 address1; 2319 __le32 data1; 2320 }; 2321 2322 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2323 2324 /* Indirect write (indirect 0x0901) 2325 * Indirect read (indirect 0x0903) 2326 */ 2327 2328 struct i40e_aqc_alternate_ind_write { 2329 __le32 address; 2330 __le32 length; 2331 __le32 addr_high; 2332 __le32 addr_low; 2333 }; 2334 2335 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2336 2337 /* Done alternate write (direct 0x0904) 2338 * uses i40e_aq_desc 2339 */ 2340 struct i40e_aqc_alternate_write_done { 2341 __le16 cmd_flags; 2342 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2343 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2344 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2345 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2346 u8 reserved[14]; 2347 }; 2348 2349 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2350 2351 /* Set OEM mode (direct 0x0905) */ 2352 struct i40e_aqc_alternate_set_mode { 2353 __le32 mode; 2354 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2355 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2356 u8 reserved[12]; 2357 }; 2358 2359 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2360 2361 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2362 2363 /* async events 0x10xx */ 2364 2365 /* Lan Queue Overflow Event (direct, 0x1001) */ 2366 struct i40e_aqc_lan_overflow { 2367 __le32 prtdcb_rupto; 2368 __le32 otx_ctl; 2369 u8 reserved[8]; 2370 }; 2371 2372 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2373 2374 /* Get LLDP MIB (indirect 0x0A00) */ 2375 struct i40e_aqc_lldp_get_mib { 2376 u8 type; 2377 u8 reserved1; 2378 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2379 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2380 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2381 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2382 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2383 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2384 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2385 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2386 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2387 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2388 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2389 __le16 local_len; 2390 __le16 remote_len; 2391 u8 reserved2[2]; 2392 __le32 addr_high; 2393 __le32 addr_low; 2394 }; 2395 2396 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2397 2398 /* Configure LLDP MIB Change Event (direct 0x0A01) 2399 * also used for the event (with type in the command field) 2400 */ 2401 struct i40e_aqc_lldp_update_mib { 2402 u8 command; 2403 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2404 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2405 u8 reserved[7]; 2406 __le32 addr_high; 2407 __le32 addr_low; 2408 }; 2409 2410 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2411 2412 /* Add LLDP TLV (indirect 0x0A02) 2413 * Delete LLDP TLV (indirect 0x0A04) 2414 */ 2415 struct i40e_aqc_lldp_add_tlv { 2416 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2417 u8 reserved1[1]; 2418 __le16 len; 2419 u8 reserved2[4]; 2420 __le32 addr_high; 2421 __le32 addr_low; 2422 }; 2423 2424 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2425 2426 /* Update LLDP TLV (indirect 0x0A03) */ 2427 struct i40e_aqc_lldp_update_tlv { 2428 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2429 u8 reserved; 2430 __le16 old_len; 2431 __le16 new_offset; 2432 __le16 new_len; 2433 __le32 addr_high; 2434 __le32 addr_low; 2435 }; 2436 2437 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2438 2439 /* Stop LLDP (direct 0x0A05) */ 2440 struct i40e_aqc_lldp_stop { 2441 u8 command; 2442 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2443 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2444 u8 reserved[15]; 2445 }; 2446 2447 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2448 2449 /* Start LLDP (direct 0x0A06) */ 2450 2451 struct i40e_aqc_lldp_start { 2452 u8 command; 2453 #define I40E_AQ_LLDP_AGENT_START 0x1 2454 u8 reserved[15]; 2455 }; 2456 2457 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2458 2459 /* Get CEE DCBX Oper Config (0x0A07) 2460 * uses the generic descriptor struct 2461 * returns below as indirect response 2462 */ 2463 2464 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2465 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2466 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2467 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2468 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2469 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2470 2471 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2472 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2473 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2474 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2475 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2476 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2477 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2478 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2479 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2480 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2481 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2482 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2483 2484 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2485 * word boundary layout issues, which the Linux compilers silently deal 2486 * with by adding padding, making the actual struct larger than designed. 2487 * However, the FW compiler for the NIC is less lenient and complains 2488 * about the struct. Hence, the struct defined here has an extra byte in 2489 * fields reserved3 and reserved4 to directly acknowledge that padding, 2490 * and the new length is used in the length check macro. 2491 */ 2492 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2493 u8 reserved1; 2494 u8 oper_num_tc; 2495 u8 oper_prio_tc[4]; 2496 u8 reserved2; 2497 u8 oper_tc_bw[8]; 2498 u8 oper_pfc_en; 2499 u8 reserved3[2]; 2500 __le16 oper_app_prio; 2501 u8 reserved4[2]; 2502 __le16 tlv_status; 2503 }; 2504 2505 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2506 2507 struct i40e_aqc_get_cee_dcb_cfg_resp { 2508 u8 oper_num_tc; 2509 u8 oper_prio_tc[4]; 2510 u8 oper_tc_bw[8]; 2511 u8 oper_pfc_en; 2512 __le16 oper_app_prio; 2513 __le32 tlv_status; 2514 u8 reserved[12]; 2515 }; 2516 2517 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2518 2519 /* Set Local LLDP MIB (indirect 0x0A08) 2520 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2521 */ 2522 struct i40e_aqc_lldp_set_local_mib { 2523 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2524 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2525 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2526 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2527 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2528 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2529 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2530 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2531 u8 type; 2532 u8 reserved0; 2533 __le16 length; 2534 u8 reserved1[4]; 2535 __le32 address_high; 2536 __le32 address_low; 2537 }; 2538 2539 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2540 2541 struct i40e_aqc_lldp_set_local_mib_resp { 2542 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2543 u8 status; 2544 u8 reserved[15]; 2545 }; 2546 2547 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2548 2549 /* Stop/Start LLDP Agent (direct 0x0A09) 2550 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2551 */ 2552 struct i40e_aqc_lldp_stop_start_specific_agent { 2553 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2554 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2555 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2556 u8 command; 2557 u8 reserved[15]; 2558 }; 2559 2560 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2561 2562 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2563 struct i40e_aqc_add_udp_tunnel { 2564 __le16 udp_port; 2565 u8 reserved0[3]; 2566 u8 protocol_type; 2567 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2568 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2569 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2570 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2571 u8 reserved1[10]; 2572 }; 2573 2574 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2575 2576 struct i40e_aqc_add_udp_tunnel_completion { 2577 __le16 udp_port; 2578 u8 filter_entry_index; 2579 u8 multiple_pfs; 2580 #define I40E_AQC_SINGLE_PF 0x0 2581 #define I40E_AQC_MULTIPLE_PFS 0x1 2582 u8 total_filters; 2583 u8 reserved[11]; 2584 }; 2585 2586 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2587 2588 /* remove UDP Tunnel command (0x0B01) */ 2589 struct i40e_aqc_remove_udp_tunnel { 2590 u8 reserved[2]; 2591 u8 index; /* 0 to 15 */ 2592 u8 reserved2[13]; 2593 }; 2594 2595 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2596 2597 struct i40e_aqc_del_udp_tunnel_completion { 2598 __le16 udp_port; 2599 u8 index; /* 0 to 15 */ 2600 u8 multiple_pfs; 2601 u8 total_filters_used; 2602 u8 reserved1[11]; 2603 }; 2604 2605 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2606 2607 struct i40e_aqc_get_set_rss_key { 2608 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2609 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2610 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2611 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2612 __le16 vsi_id; 2613 u8 reserved[6]; 2614 __le32 addr_high; 2615 __le32 addr_low; 2616 }; 2617 2618 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2619 2620 struct i40e_aqc_get_set_rss_key_data { 2621 u8 standard_rss_key[0x28]; 2622 u8 extended_hash_key[0xc]; 2623 }; 2624 2625 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2626 2627 struct i40e_aqc_get_set_rss_lut { 2628 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2629 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2630 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2631 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2632 __le16 vsi_id; 2633 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2634 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2635 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2636 2637 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2638 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2639 __le16 flags; 2640 u8 reserved[4]; 2641 __le32 addr_high; 2642 __le32 addr_low; 2643 }; 2644 2645 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2646 2647 /* tunnel key structure 0x0B10 */ 2648 2649 struct i40e_aqc_tunnel_key_structure { 2650 u8 key1_off; 2651 u8 key2_off; 2652 u8 key1_len; /* 0 to 15 */ 2653 u8 key2_len; /* 0 to 15 */ 2654 u8 flags; 2655 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2656 /* response flags */ 2657 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2658 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2659 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2660 u8 network_key_index; 2661 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2662 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2663 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2664 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2665 u8 reserved[10]; 2666 }; 2667 2668 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2669 2670 /* OEM mode commands (direct 0xFE0x) */ 2671 struct i40e_aqc_oem_param_change { 2672 __le32 param_type; 2673 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2674 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2675 #define I40E_AQ_OEM_PARAM_MAC 2 2676 __le32 param_value1; 2677 __le16 param_value2; 2678 u8 reserved[6]; 2679 }; 2680 2681 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2682 2683 struct i40e_aqc_oem_state_change { 2684 __le32 state; 2685 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2686 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2687 u8 reserved[12]; 2688 }; 2689 2690 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2691 2692 /* Initialize OCSD (0xFE02, direct) */ 2693 struct i40e_aqc_opc_oem_ocsd_initialize { 2694 u8 type_status; 2695 u8 reserved1[3]; 2696 __le32 ocsd_memory_block_addr_high; 2697 __le32 ocsd_memory_block_addr_low; 2698 __le32 requested_update_interval; 2699 }; 2700 2701 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2702 2703 /* Initialize OCBB (0xFE03, direct) */ 2704 struct i40e_aqc_opc_oem_ocbb_initialize { 2705 u8 type_status; 2706 u8 reserved1[3]; 2707 __le32 ocbb_memory_block_addr_high; 2708 __le32 ocbb_memory_block_addr_low; 2709 u8 reserved2[4]; 2710 }; 2711 2712 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2713 2714 /* debug commands */ 2715 2716 /* get device id (0xFF00) uses the generic structure */ 2717 2718 /* set test more (0xFF01, internal) */ 2719 2720 struct i40e_acq_set_test_mode { 2721 u8 mode; 2722 #define I40E_AQ_TEST_PARTIAL 0 2723 #define I40E_AQ_TEST_FULL 1 2724 #define I40E_AQ_TEST_NVM 2 2725 u8 reserved[3]; 2726 u8 command; 2727 #define I40E_AQ_TEST_OPEN 0 2728 #define I40E_AQ_TEST_CLOSE 1 2729 #define I40E_AQ_TEST_INC 2 2730 u8 reserved2[3]; 2731 __le32 address_high; 2732 __le32 address_low; 2733 }; 2734 2735 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2736 2737 /* Debug Read Register command (0xFF03) 2738 * Debug Write Register command (0xFF04) 2739 */ 2740 struct i40e_aqc_debug_reg_read_write { 2741 __le32 reserved; 2742 __le32 address; 2743 __le32 value_high; 2744 __le32 value_low; 2745 }; 2746 2747 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2748 2749 /* Scatter/gather Reg Read (indirect 0xFF05) 2750 * Scatter/gather Reg Write (indirect 0xFF06) 2751 */ 2752 2753 /* i40e_aq_desc is used for the command */ 2754 struct i40e_aqc_debug_reg_sg_element_data { 2755 __le32 address; 2756 __le32 value; 2757 }; 2758 2759 /* Debug Modify register (direct 0xFF07) */ 2760 struct i40e_aqc_debug_modify_reg { 2761 __le32 address; 2762 __le32 value; 2763 __le32 clear_mask; 2764 __le32 set_mask; 2765 }; 2766 2767 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2768 2769 /* dump internal data (0xFF08, indirect) */ 2770 2771 #define I40E_AQ_CLUSTER_ID_AUX 0 2772 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2773 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2774 #define I40E_AQ_CLUSTER_ID_HMC 3 2775 #define I40E_AQ_CLUSTER_ID_MAC0 4 2776 #define I40E_AQ_CLUSTER_ID_MAC1 5 2777 #define I40E_AQ_CLUSTER_ID_MAC2 6 2778 #define I40E_AQ_CLUSTER_ID_MAC3 7 2779 #define I40E_AQ_CLUSTER_ID_DCB 8 2780 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2781 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2782 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2783 2784 struct i40e_aqc_debug_dump_internals { 2785 u8 cluster_id; 2786 u8 table_id; 2787 __le16 data_size; 2788 __le32 idx; 2789 __le32 address_high; 2790 __le32 address_low; 2791 }; 2792 2793 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2794 2795 struct i40e_aqc_debug_modify_internals { 2796 u8 cluster_id; 2797 u8 cluster_specific_params[7]; 2798 __le32 address_high; 2799 __le32 address_low; 2800 }; 2801 2802 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2803 2804 #endif /* _I40E_ADMINQ_CMD_H_ */ 2805