1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #ifndef _ENA_ETHDEV_H_ 7 #define _ENA_ETHDEV_H_ 8 9 #include <rte_cycles.h> 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_timer.h> 13 14 #include "ena_com.h" 15 16 #define ENA_REGS_BAR 0 17 #define ENA_MEM_BAR 2 18 19 #define ENA_MAX_NUM_QUEUES 128 20 #define ENA_MIN_FRAME_LEN 64 21 #define ENA_NAME_MAX_LEN 20 22 #define ENA_PKT_MAX_BUFS 17 23 24 #define ENA_MIN_MTU 128 25 26 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 27 28 #define ENA_WD_TIMEOUT_SEC 3 29 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz()) 30 31 struct ena_adapter; 32 33 enum ena_ring_type { 34 ENA_RING_TYPE_RX = 1, 35 ENA_RING_TYPE_TX = 2, 36 }; 37 38 struct ena_tx_buffer { 39 struct rte_mbuf *mbuf; 40 unsigned int tx_descs; 41 unsigned int num_of_bufs; 42 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 43 }; 44 45 struct ena_calc_queue_size_ctx { 46 struct ena_com_dev_get_features_ctx *get_feat_ctx; 47 struct ena_com_dev *ena_dev; 48 u16 rx_queue_size; 49 u16 tx_queue_size; 50 u16 max_tx_sgl_size; 51 u16 max_rx_sgl_size; 52 }; 53 54 struct ena_stats_tx { 55 u64 cnt; 56 u64 bytes; 57 u64 prepare_ctx_err; 58 u64 linearize; 59 u64 linearize_failed; 60 u64 tx_poll; 61 u64 doorbells; 62 u64 bad_req_id; 63 u64 available_desc; 64 }; 65 66 struct ena_stats_rx { 67 u64 cnt; 68 u64 bytes; 69 u64 refill_partial; 70 u64 bad_csum; 71 u64 mbuf_alloc_fail; 72 u64 bad_desc_num; 73 u64 bad_req_id; 74 }; 75 76 struct ena_ring { 77 u16 next_to_use; 78 u16 next_to_clean; 79 80 enum ena_ring_type type; 81 enum ena_admin_placement_policy_type tx_mem_queue_type; 82 /* Holds the empty requests for TX/RX OOO completions */ 83 union { 84 uint16_t *empty_tx_reqs; 85 uint16_t *empty_rx_reqs; 86 }; 87 88 union { 89 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 90 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */ 91 }; 92 struct rte_mbuf **rx_refill_buffer; 93 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */ 94 95 struct ena_com_io_cq *ena_com_io_cq; 96 struct ena_com_io_sq *ena_com_io_sq; 97 98 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS] 99 __rte_cache_aligned; 100 101 struct rte_mempool *mb_pool; 102 unsigned int port_id; 103 unsigned int id; 104 /* Max length PMD can push to device for LLQ */ 105 uint8_t tx_max_header_size; 106 int configured; 107 108 uint8_t *push_buf_intermediate_buf; 109 110 struct ena_adapter *adapter; 111 uint64_t offloads; 112 u16 sgl_size; 113 114 union { 115 struct ena_stats_rx rx_stats; 116 struct ena_stats_tx tx_stats; 117 }; 118 119 unsigned int numa_socket_id; 120 } __rte_cache_aligned; 121 122 enum ena_adapter_state { 123 ENA_ADAPTER_STATE_FREE = 0, 124 ENA_ADAPTER_STATE_INIT = 1, 125 ENA_ADAPTER_STATE_RUNNING = 2, 126 ENA_ADAPTER_STATE_STOPPED = 3, 127 ENA_ADAPTER_STATE_CONFIG = 4, 128 ENA_ADAPTER_STATE_CLOSED = 5, 129 }; 130 131 struct ena_driver_stats { 132 rte_atomic64_t ierrors; 133 rte_atomic64_t oerrors; 134 rte_atomic64_t rx_nombuf; 135 rte_atomic64_t rx_drops; 136 }; 137 138 struct ena_stats_dev { 139 u64 wd_expired; 140 u64 dev_start; 141 u64 dev_stop; 142 }; 143 144 struct ena_offloads { 145 bool tso4_supported; 146 bool tx_csum_supported; 147 bool rx_csum_supported; 148 }; 149 150 /* board specific private data structure */ 151 struct ena_adapter { 152 /* OS defined structs */ 153 struct rte_pci_device *pdev; 154 struct rte_eth_dev_data *rte_eth_dev_data; 155 struct rte_eth_dev *rte_dev; 156 157 struct ena_com_dev ena_dev __rte_cache_aligned; 158 159 /* TX */ 160 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 161 int tx_ring_size; 162 u16 max_tx_sgl_size; 163 164 /* RX */ 165 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 166 int rx_ring_size; 167 u16 max_rx_sgl_size; 168 169 u16 num_queues; 170 u16 max_mtu; 171 struct ena_offloads offloads; 172 173 int id_number; 174 char name[ENA_NAME_MAX_LEN]; 175 u8 mac_addr[RTE_ETHER_ADDR_LEN]; 176 177 void *regs; 178 void *dev_mem_base; 179 180 struct ena_driver_stats *drv_stats; 181 enum ena_adapter_state state; 182 183 uint64_t tx_supported_offloads; 184 uint64_t tx_selected_offloads; 185 uint64_t rx_supported_offloads; 186 uint64_t rx_selected_offloads; 187 188 bool link_status; 189 190 enum ena_regs_reset_reason_types reset_reason; 191 192 struct rte_timer timer_wd; 193 uint64_t timestamp_wd; 194 uint64_t keep_alive_timeout; 195 196 struct ena_stats_dev dev_stats; 197 198 bool trigger_reset; 199 200 bool wd_state; 201 }; 202 203 #endif /* _ENA_ETHDEV_H_ */ 204