1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _ENA_ETHDEV_H_ 35 #define _ENA_ETHDEV_H_ 36 37 #include <rte_pci.h> 38 #include <rte_bus_pci.h> 39 40 #include "ena_com.h" 41 42 #define ENA_REGS_BAR 0 43 #define ENA_MEM_BAR 2 44 45 #define ENA_MAX_NUM_QUEUES 128 46 #define ENA_DEFAULT_RING_SIZE (1024) 47 #define ENA_MIN_FRAME_LEN 64 48 #define ENA_NAME_MAX_LEN 20 49 #define ENA_PKT_MAX_BUFS 17 50 51 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 52 53 struct ena_adapter; 54 55 enum ena_ring_type { 56 ENA_RING_TYPE_RX = 1, 57 ENA_RING_TYPE_TX = 2, 58 }; 59 60 struct ena_tx_buffer { 61 struct rte_mbuf *mbuf; 62 unsigned int tx_descs; 63 unsigned int num_of_bufs; 64 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 65 }; 66 67 struct ena_ring { 68 u16 next_to_use; 69 u16 next_to_clean; 70 71 enum ena_ring_type type; 72 enum ena_admin_placement_policy_type tx_mem_queue_type; 73 /* Holds the empty requests for TX OOO completions */ 74 uint16_t *empty_tx_reqs; 75 union { 76 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 77 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */ 78 }; 79 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */ 80 81 struct ena_com_io_cq *ena_com_io_cq; 82 struct ena_com_io_sq *ena_com_io_sq; 83 84 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS] 85 __rte_cache_aligned; 86 87 struct rte_mempool *mb_pool; 88 unsigned int port_id; 89 unsigned int id; 90 /* Max length PMD can push to device for LLQ */ 91 uint8_t tx_max_header_size; 92 int configured; 93 struct ena_adapter *adapter; 94 } __rte_cache_aligned; 95 96 enum ena_adapter_state { 97 ENA_ADAPTER_STATE_FREE = 0, 98 ENA_ADAPTER_STATE_INIT = 1, 99 ENA_ADAPTER_STATE_RUNNING = 2, 100 ENA_ADAPTER_STATE_STOPPED = 3, 101 ENA_ADAPTER_STATE_CONFIG = 4, 102 }; 103 104 struct ena_driver_stats { 105 rte_atomic64_t ierrors; 106 rte_atomic64_t oerrors; 107 rte_atomic64_t rx_nombuf; 108 }; 109 110 struct ena_stats_dev { 111 u64 tx_timeout; 112 u64 io_suspend; 113 u64 io_resume; 114 u64 wd_expired; 115 u64 interface_up; 116 u64 interface_down; 117 u64 admin_q_pause; 118 }; 119 120 struct ena_stats_tx { 121 u64 cnt; 122 u64 bytes; 123 u64 queue_stop; 124 u64 prepare_ctx_err; 125 u64 queue_wakeup; 126 u64 dma_mapping_err; 127 u64 linearize; 128 u64 linearize_failed; 129 u64 tx_poll; 130 u64 doorbells; 131 u64 missing_tx_comp; 132 u64 bad_req_id; 133 }; 134 135 struct ena_stats_rx { 136 u64 cnt; 137 u64 bytes; 138 u64 refil_partial; 139 u64 bad_csum; 140 u64 page_alloc_fail; 141 u64 skb_alloc_fail; 142 u64 dma_mapping_err; 143 u64 bad_desc_num; 144 u64 small_copy_len_pkt; 145 }; 146 147 /* board specific private data structure */ 148 struct ena_adapter { 149 /* OS defined structs */ 150 struct rte_pci_device *pdev; 151 struct rte_eth_dev_data *rte_eth_dev_data; 152 struct rte_eth_dev *rte_dev; 153 154 struct ena_com_dev ena_dev __rte_cache_aligned; 155 156 /* TX */ 157 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 158 int tx_ring_size; 159 160 /* RX */ 161 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 162 int rx_ring_size; 163 164 u16 num_queues; 165 u16 max_mtu; 166 u8 tso4_supported; 167 168 int id_number; 169 char name[ENA_NAME_MAX_LEN]; 170 u8 mac_addr[ETHER_ADDR_LEN]; 171 172 void *regs; 173 void *dev_mem_base; 174 175 struct ena_driver_stats *drv_stats; 176 enum ena_adapter_state state; 177 178 }; 179 180 #endif /* _ENA_ETHDEV_H_ */ 181