1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <rte_ether.h> 35 #include <rte_ethdev_driver.h> 36 #include <rte_ethdev_pci.h> 37 #include <rte_tcp.h> 38 #include <rte_atomic.h> 39 #include <rte_dev.h> 40 #include <rte_errno.h> 41 #include <rte_version.h> 42 #include <rte_eal_memconfig.h> 43 #include <rte_net.h> 44 45 #include "ena_ethdev.h" 46 #include "ena_logs.h" 47 #include "ena_platform.h" 48 #include "ena_com.h" 49 #include "ena_eth_com.h" 50 51 #include <ena_common_defs.h> 52 #include <ena_regs_defs.h> 53 #include <ena_admin_defs.h> 54 #include <ena_eth_io_defs.h> 55 56 #define DRV_MODULE_VER_MAJOR 1 57 #define DRV_MODULE_VER_MINOR 1 58 #define DRV_MODULE_VER_SUBMINOR 1 59 60 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 62 /*reverse version of ENA_IO_RXQ_IDX*/ 63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 64 65 /* While processing submitted and completed descriptors (rx and tx path 66 * respectively) in a loop it is desired to: 67 * - perform batch submissions while populating sumbissmion queue 68 * - avoid blocking transmission of other packets during cleanup phase 69 * Hence the utilization ratio of 1/8 of a queue size. 70 */ 71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) 72 73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 75 76 #define GET_L4_HDR_LEN(mbuf) \ 77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \ 78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 79 80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 82 #define ENA_HASH_KEY_SIZE 40 83 #define ENA_ETH_SS_STATS 0xFF 84 #define ETH_GSTRING_LEN 32 85 86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 87 88 #define ENA_MAX_RING_DESC ENA_DEFAULT_RING_SIZE 89 #define ENA_MIN_RING_DESC 128 90 91 enum ethtool_stringset { 92 ETH_SS_TEST = 0, 93 ETH_SS_STATS, 94 }; 95 96 struct ena_stats { 97 char name[ETH_GSTRING_LEN]; 98 int stat_offset; 99 }; 100 101 #define ENA_STAT_ENA_COM_ENTRY(stat) { \ 102 .name = #stat, \ 103 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \ 104 } 105 106 #define ENA_STAT_ENTRY(stat, stat_type) { \ 107 .name = #stat, \ 108 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 109 } 110 111 #define ENA_STAT_RX_ENTRY(stat) \ 112 ENA_STAT_ENTRY(stat, rx) 113 114 #define ENA_STAT_TX_ENTRY(stat) \ 115 ENA_STAT_ENTRY(stat, tx) 116 117 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 118 ENA_STAT_ENTRY(stat, dev) 119 120 /* 121 * Each rte_memzone should have unique name. 122 * To satisfy it, count number of allocation and add it to name. 123 */ 124 uint32_t ena_alloc_cnt; 125 126 static const struct ena_stats ena_stats_global_strings[] = { 127 ENA_STAT_GLOBAL_ENTRY(tx_timeout), 128 ENA_STAT_GLOBAL_ENTRY(io_suspend), 129 ENA_STAT_GLOBAL_ENTRY(io_resume), 130 ENA_STAT_GLOBAL_ENTRY(wd_expired), 131 ENA_STAT_GLOBAL_ENTRY(interface_up), 132 ENA_STAT_GLOBAL_ENTRY(interface_down), 133 ENA_STAT_GLOBAL_ENTRY(admin_q_pause), 134 }; 135 136 static const struct ena_stats ena_stats_tx_strings[] = { 137 ENA_STAT_TX_ENTRY(cnt), 138 ENA_STAT_TX_ENTRY(bytes), 139 ENA_STAT_TX_ENTRY(queue_stop), 140 ENA_STAT_TX_ENTRY(queue_wakeup), 141 ENA_STAT_TX_ENTRY(dma_mapping_err), 142 ENA_STAT_TX_ENTRY(linearize), 143 ENA_STAT_TX_ENTRY(linearize_failed), 144 ENA_STAT_TX_ENTRY(tx_poll), 145 ENA_STAT_TX_ENTRY(doorbells), 146 ENA_STAT_TX_ENTRY(prepare_ctx_err), 147 ENA_STAT_TX_ENTRY(missing_tx_comp), 148 ENA_STAT_TX_ENTRY(bad_req_id), 149 }; 150 151 static const struct ena_stats ena_stats_rx_strings[] = { 152 ENA_STAT_RX_ENTRY(cnt), 153 ENA_STAT_RX_ENTRY(bytes), 154 ENA_STAT_RX_ENTRY(refil_partial), 155 ENA_STAT_RX_ENTRY(bad_csum), 156 ENA_STAT_RX_ENTRY(page_alloc_fail), 157 ENA_STAT_RX_ENTRY(skb_alloc_fail), 158 ENA_STAT_RX_ENTRY(dma_mapping_err), 159 ENA_STAT_RX_ENTRY(bad_desc_num), 160 ENA_STAT_RX_ENTRY(small_copy_len_pkt), 161 }; 162 163 static const struct ena_stats ena_stats_ena_com_strings[] = { 164 ENA_STAT_ENA_COM_ENTRY(aborted_cmd), 165 ENA_STAT_ENA_COM_ENTRY(submitted_cmd), 166 ENA_STAT_ENA_COM_ENTRY(completed_cmd), 167 ENA_STAT_ENA_COM_ENTRY(out_of_space), 168 ENA_STAT_ENA_COM_ENTRY(no_completion), 169 }; 170 171 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 172 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 173 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 174 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings) 175 176 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 177 DEV_TX_OFFLOAD_UDP_CKSUM |\ 178 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 179 DEV_TX_OFFLOAD_TCP_TSO) 180 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 181 PKT_TX_IP_CKSUM |\ 182 PKT_TX_TCP_SEG) 183 184 /** Vendor ID used by Amazon devices */ 185 #define PCI_VENDOR_ID_AMAZON 0x1D0F 186 /** Amazon devices */ 187 #define PCI_DEVICE_ID_ENA_VF 0xEC20 188 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 189 190 #define ENA_TX_OFFLOAD_MASK (\ 191 PKT_TX_L4_MASK | \ 192 PKT_TX_IPV6 | \ 193 PKT_TX_IPV4 | \ 194 PKT_TX_IP_CKSUM | \ 195 PKT_TX_TCP_SEG) 196 197 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 198 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 199 200 int ena_logtype_init; 201 int ena_logtype_driver; 202 203 static const struct rte_pci_id pci_id_ena_map[] = { 204 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 205 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 206 { .device_id = 0 }, 207 }; 208 209 static struct ena_aenq_handlers aenq_handlers; 210 211 static int ena_device_init(struct ena_com_dev *ena_dev, 212 struct ena_com_dev_get_features_ctx *get_feat_ctx, 213 bool *wd_state); 214 static int ena_dev_configure(struct rte_eth_dev *dev); 215 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 216 uint16_t nb_pkts); 217 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 218 uint16_t nb_pkts); 219 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 220 uint16_t nb_desc, unsigned int socket_id, 221 const struct rte_eth_txconf *tx_conf); 222 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 223 uint16_t nb_desc, unsigned int socket_id, 224 const struct rte_eth_rxconf *rx_conf, 225 struct rte_mempool *mp); 226 static uint16_t eth_ena_recv_pkts(void *rx_queue, 227 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 228 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 229 static void ena_init_rings(struct ena_adapter *adapter); 230 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 231 static int ena_start(struct rte_eth_dev *dev); 232 static void ena_stop(struct rte_eth_dev *dev); 233 static void ena_close(struct rte_eth_dev *dev); 234 static int ena_dev_reset(struct rte_eth_dev *dev); 235 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 236 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 237 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 238 static void ena_rx_queue_release(void *queue); 239 static void ena_tx_queue_release(void *queue); 240 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 241 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 242 static int ena_link_update(struct rte_eth_dev *dev, 243 int wait_to_complete); 244 static int ena_create_io_queue(struct ena_ring *ring); 245 static void ena_queue_stop(struct ena_ring *ring); 246 static void ena_queue_stop_all(struct rte_eth_dev *dev, 247 enum ena_ring_type ring_type); 248 static int ena_queue_start(struct ena_ring *ring); 249 static int ena_queue_start_all(struct rte_eth_dev *dev, 250 enum ena_ring_type ring_type); 251 static void ena_stats_restart(struct rte_eth_dev *dev); 252 static void ena_infos_get(struct rte_eth_dev *dev, 253 struct rte_eth_dev_info *dev_info); 254 static int ena_rss_reta_update(struct rte_eth_dev *dev, 255 struct rte_eth_rss_reta_entry64 *reta_conf, 256 uint16_t reta_size); 257 static int ena_rss_reta_query(struct rte_eth_dev *dev, 258 struct rte_eth_rss_reta_entry64 *reta_conf, 259 uint16_t reta_size); 260 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset); 261 static void ena_interrupt_handler_rte(void *cb_arg); 262 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 263 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 264 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 265 266 static const struct eth_dev_ops ena_dev_ops = { 267 .dev_configure = ena_dev_configure, 268 .dev_infos_get = ena_infos_get, 269 .rx_queue_setup = ena_rx_queue_setup, 270 .tx_queue_setup = ena_tx_queue_setup, 271 .dev_start = ena_start, 272 .dev_stop = ena_stop, 273 .link_update = ena_link_update, 274 .stats_get = ena_stats_get, 275 .mtu_set = ena_mtu_set, 276 .rx_queue_release = ena_rx_queue_release, 277 .tx_queue_release = ena_tx_queue_release, 278 .dev_close = ena_close, 279 .dev_reset = ena_dev_reset, 280 .reta_update = ena_rss_reta_update, 281 .reta_query = ena_rss_reta_query, 282 }; 283 284 #define NUMA_NO_NODE SOCKET_ID_ANY 285 286 static inline int ena_cpu_to_node(int cpu) 287 { 288 struct rte_config *config = rte_eal_get_configuration(); 289 struct rte_fbarray *arr = &config->mem_config->memzones; 290 const struct rte_memzone *mz; 291 292 if (unlikely(cpu >= RTE_MAX_MEMZONE)) 293 return NUMA_NO_NODE; 294 295 mz = rte_fbarray_get(arr, cpu); 296 297 return mz->socket_id; 298 } 299 300 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 301 struct ena_com_rx_ctx *ena_rx_ctx) 302 { 303 uint64_t ol_flags = 0; 304 uint32_t packet_type = 0; 305 306 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 307 packet_type |= RTE_PTYPE_L4_TCP; 308 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 309 packet_type |= RTE_PTYPE_L4_UDP; 310 311 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 312 packet_type |= RTE_PTYPE_L3_IPV4; 313 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 314 packet_type |= RTE_PTYPE_L3_IPV6; 315 316 if (unlikely(ena_rx_ctx->l4_csum_err)) 317 ol_flags |= PKT_RX_L4_CKSUM_BAD; 318 if (unlikely(ena_rx_ctx->l3_csum_err)) 319 ol_flags |= PKT_RX_IP_CKSUM_BAD; 320 321 mbuf->ol_flags = ol_flags; 322 mbuf->packet_type = packet_type; 323 } 324 325 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 326 struct ena_com_tx_ctx *ena_tx_ctx, 327 uint64_t queue_offloads) 328 { 329 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 330 331 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 332 (queue_offloads & QUEUE_OFFLOADS)) { 333 /* check if TSO is required */ 334 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 335 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 336 ena_tx_ctx->tso_enable = true; 337 338 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 339 } 340 341 /* check if L3 checksum is needed */ 342 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 343 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 344 ena_tx_ctx->l3_csum_enable = true; 345 346 if (mbuf->ol_flags & PKT_TX_IPV6) { 347 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 348 } else { 349 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 350 351 /* set don't fragment (DF) flag */ 352 if (mbuf->packet_type & 353 (RTE_PTYPE_L4_NONFRAG 354 | RTE_PTYPE_INNER_L4_NONFRAG)) 355 ena_tx_ctx->df = true; 356 } 357 358 /* check if L4 checksum is needed */ 359 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) && 360 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 361 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 362 ena_tx_ctx->l4_csum_enable = true; 363 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) && 364 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 365 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 366 ena_tx_ctx->l4_csum_enable = true; 367 } else { 368 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 369 ena_tx_ctx->l4_csum_enable = false; 370 } 371 372 ena_meta->mss = mbuf->tso_segsz; 373 ena_meta->l3_hdr_len = mbuf->l3_len; 374 ena_meta->l3_hdr_offset = mbuf->l2_len; 375 376 ena_tx_ctx->meta_valid = true; 377 } else { 378 ena_tx_ctx->meta_valid = false; 379 } 380 } 381 382 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 383 { 384 if (likely(req_id < rx_ring->ring_size)) 385 return 0; 386 387 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id); 388 389 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 390 rx_ring->adapter->trigger_reset = true; 391 392 return -EFAULT; 393 } 394 395 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 396 { 397 struct ena_tx_buffer *tx_info = NULL; 398 399 if (likely(req_id < tx_ring->ring_size)) { 400 tx_info = &tx_ring->tx_buffer_info[req_id]; 401 if (likely(tx_info->mbuf)) 402 return 0; 403 } 404 405 if (tx_info) 406 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n"); 407 else 408 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id); 409 410 /* Trigger device reset */ 411 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 412 tx_ring->adapter->trigger_reset = true; 413 return -EFAULT; 414 } 415 416 static void ena_config_host_info(struct ena_com_dev *ena_dev) 417 { 418 struct ena_admin_host_info *host_info; 419 int rc; 420 421 /* Allocate only the host info */ 422 rc = ena_com_allocate_host_info(ena_dev); 423 if (rc) { 424 RTE_LOG(ERR, PMD, "Cannot allocate host info\n"); 425 return; 426 } 427 428 host_info = ena_dev->host_attr.host_info; 429 430 host_info->os_type = ENA_ADMIN_OS_DPDK; 431 host_info->kernel_ver = RTE_VERSION; 432 snprintf((char *)host_info->kernel_ver_str, 433 sizeof(host_info->kernel_ver_str), 434 "%s", rte_version()); 435 host_info->os_dist = RTE_VERSION; 436 snprintf((char *)host_info->os_dist_str, 437 sizeof(host_info->os_dist_str), 438 "%s", rte_version()); 439 host_info->driver_version = 440 (DRV_MODULE_VER_MAJOR) | 441 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 442 (DRV_MODULE_VER_SUBMINOR << 443 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 444 445 rc = ena_com_set_host_attributes(ena_dev); 446 if (rc) { 447 if (rc == -ENA_COM_UNSUPPORTED) 448 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 449 else 450 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 451 452 goto err; 453 } 454 455 return; 456 457 err: 458 ena_com_delete_host_info(ena_dev); 459 } 460 461 static int 462 ena_get_sset_count(struct rte_eth_dev *dev, int sset) 463 { 464 if (sset != ETH_SS_STATS) 465 return -EOPNOTSUPP; 466 467 /* Workaround for clang: 468 * touch internal structures to prevent 469 * compiler error 470 */ 471 ENA_TOUCH(ena_stats_global_strings); 472 ENA_TOUCH(ena_stats_tx_strings); 473 ENA_TOUCH(ena_stats_rx_strings); 474 ENA_TOUCH(ena_stats_ena_com_strings); 475 476 return dev->data->nb_tx_queues * 477 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) + 478 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM; 479 } 480 481 static void ena_config_debug_area(struct ena_adapter *adapter) 482 { 483 u32 debug_area_size; 484 int rc, ss_count; 485 486 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS); 487 if (ss_count <= 0) { 488 RTE_LOG(ERR, PMD, "SS count is negative\n"); 489 return; 490 } 491 492 /* allocate 32 bytes for each string and 64bit for the value */ 493 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 494 495 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 496 if (rc) { 497 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n"); 498 return; 499 } 500 501 rc = ena_com_set_host_attributes(&adapter->ena_dev); 502 if (rc) { 503 if (rc == -ENA_COM_UNSUPPORTED) 504 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 505 else 506 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 507 508 goto err; 509 } 510 511 return; 512 err: 513 ena_com_delete_debug_area(&adapter->ena_dev); 514 } 515 516 static void ena_close(struct rte_eth_dev *dev) 517 { 518 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 519 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 520 struct ena_adapter *adapter = 521 (struct ena_adapter *)(dev->data->dev_private); 522 523 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 524 ena_stop(dev); 525 adapter->state = ENA_ADAPTER_STATE_CLOSED; 526 527 ena_rx_queue_release_all(dev); 528 ena_tx_queue_release_all(dev); 529 530 rte_free(adapter->drv_stats); 531 adapter->drv_stats = NULL; 532 533 rte_intr_disable(intr_handle); 534 rte_intr_callback_unregister(intr_handle, 535 ena_interrupt_handler_rte, 536 adapter); 537 538 /* 539 * MAC is not allocated dynamically. Setting NULL should prevent from 540 * release of the resource in the rte_eth_dev_release_port(). 541 */ 542 dev->data->mac_addrs = NULL; 543 } 544 545 static int 546 ena_dev_reset(struct rte_eth_dev *dev) 547 { 548 int rc = 0; 549 550 ena_destroy_device(dev); 551 rc = eth_ena_dev_init(dev); 552 if (rc) 553 PMD_INIT_LOG(CRIT, "Cannot initialize device\n"); 554 555 return rc; 556 } 557 558 static int ena_rss_reta_update(struct rte_eth_dev *dev, 559 struct rte_eth_rss_reta_entry64 *reta_conf, 560 uint16_t reta_size) 561 { 562 struct ena_adapter *adapter = 563 (struct ena_adapter *)(dev->data->dev_private); 564 struct ena_com_dev *ena_dev = &adapter->ena_dev; 565 int rc, i; 566 u16 entry_value; 567 int conf_idx; 568 int idx; 569 570 if ((reta_size == 0) || (reta_conf == NULL)) 571 return -EINVAL; 572 573 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 574 RTE_LOG(WARNING, PMD, 575 "indirection table %d is bigger than supported (%d)\n", 576 reta_size, ENA_RX_RSS_TABLE_SIZE); 577 return -EINVAL; 578 } 579 580 for (i = 0 ; i < reta_size ; i++) { 581 /* each reta_conf is for 64 entries. 582 * to support 128 we use 2 conf of 64 583 */ 584 conf_idx = i / RTE_RETA_GROUP_SIZE; 585 idx = i % RTE_RETA_GROUP_SIZE; 586 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 587 entry_value = 588 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 589 590 rc = ena_com_indirect_table_fill_entry(ena_dev, 591 i, 592 entry_value); 593 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 594 RTE_LOG(ERR, PMD, 595 "Cannot fill indirect table\n"); 596 return rc; 597 } 598 } 599 } 600 601 rc = ena_com_indirect_table_set(ena_dev); 602 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 603 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 604 return rc; 605 } 606 607 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n", 608 __func__, reta_size, adapter->rte_dev->data->port_id); 609 610 return 0; 611 } 612 613 /* Query redirection table. */ 614 static int ena_rss_reta_query(struct rte_eth_dev *dev, 615 struct rte_eth_rss_reta_entry64 *reta_conf, 616 uint16_t reta_size) 617 { 618 struct ena_adapter *adapter = 619 (struct ena_adapter *)(dev->data->dev_private); 620 struct ena_com_dev *ena_dev = &adapter->ena_dev; 621 int rc; 622 int i; 623 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 624 int reta_conf_idx; 625 int reta_idx; 626 627 if (reta_size == 0 || reta_conf == NULL || 628 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 629 return -EINVAL; 630 631 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 632 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 633 RTE_LOG(ERR, PMD, "cannot get indirect table\n"); 634 return -ENOTSUP; 635 } 636 637 for (i = 0 ; i < reta_size ; i++) { 638 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 639 reta_idx = i % RTE_RETA_GROUP_SIZE; 640 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 641 reta_conf[reta_conf_idx].reta[reta_idx] = 642 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 643 } 644 645 return 0; 646 } 647 648 static int ena_rss_init_default(struct ena_adapter *adapter) 649 { 650 struct ena_com_dev *ena_dev = &adapter->ena_dev; 651 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 652 int rc, i; 653 u32 val; 654 655 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 656 if (unlikely(rc)) { 657 RTE_LOG(ERR, PMD, "Cannot init indirect table\n"); 658 goto err_rss_init; 659 } 660 661 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 662 val = i % nb_rx_queues; 663 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 664 ENA_IO_RXQ_IDX(val)); 665 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 666 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n"); 667 goto err_fill_indir; 668 } 669 } 670 671 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 672 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 673 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 674 RTE_LOG(INFO, PMD, "Cannot fill hash function\n"); 675 goto err_fill_indir; 676 } 677 678 rc = ena_com_set_default_hash_ctrl(ena_dev); 679 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 680 RTE_LOG(INFO, PMD, "Cannot fill hash control\n"); 681 goto err_fill_indir; 682 } 683 684 rc = ena_com_indirect_table_set(ena_dev); 685 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 686 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 687 goto err_fill_indir; 688 } 689 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n", 690 adapter->rte_dev->data->port_id); 691 692 return 0; 693 694 err_fill_indir: 695 ena_com_rss_destroy(ena_dev); 696 err_rss_init: 697 698 return rc; 699 } 700 701 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 702 { 703 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 704 int nb_queues = dev->data->nb_rx_queues; 705 int i; 706 707 for (i = 0; i < nb_queues; i++) 708 ena_rx_queue_release(queues[i]); 709 } 710 711 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 712 { 713 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 714 int nb_queues = dev->data->nb_tx_queues; 715 int i; 716 717 for (i = 0; i < nb_queues; i++) 718 ena_tx_queue_release(queues[i]); 719 } 720 721 static void ena_rx_queue_release(void *queue) 722 { 723 struct ena_ring *ring = (struct ena_ring *)queue; 724 725 /* Free ring resources */ 726 if (ring->rx_buffer_info) 727 rte_free(ring->rx_buffer_info); 728 ring->rx_buffer_info = NULL; 729 730 if (ring->rx_refill_buffer) 731 rte_free(ring->rx_refill_buffer); 732 ring->rx_refill_buffer = NULL; 733 734 if (ring->empty_rx_reqs) 735 rte_free(ring->empty_rx_reqs); 736 ring->empty_rx_reqs = NULL; 737 738 ring->configured = 0; 739 740 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n", 741 ring->port_id, ring->id); 742 } 743 744 static void ena_tx_queue_release(void *queue) 745 { 746 struct ena_ring *ring = (struct ena_ring *)queue; 747 748 /* Free ring resources */ 749 if (ring->tx_buffer_info) 750 rte_free(ring->tx_buffer_info); 751 752 if (ring->empty_tx_reqs) 753 rte_free(ring->empty_tx_reqs); 754 755 ring->empty_tx_reqs = NULL; 756 ring->tx_buffer_info = NULL; 757 758 ring->configured = 0; 759 760 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n", 761 ring->port_id, ring->id); 762 } 763 764 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 765 { 766 unsigned int i; 767 768 for (i = 0; i < ring->ring_size; ++i) 769 if (ring->rx_buffer_info[i]) { 770 rte_mbuf_raw_free(ring->rx_buffer_info[i]); 771 ring->rx_buffer_info[i] = NULL; 772 } 773 } 774 775 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 776 { 777 unsigned int i; 778 779 for (i = 0; i < ring->ring_size; ++i) { 780 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 781 782 if (tx_buf->mbuf) 783 rte_pktmbuf_free(tx_buf->mbuf); 784 } 785 } 786 787 static int ena_link_update(struct rte_eth_dev *dev, 788 __rte_unused int wait_to_complete) 789 { 790 struct rte_eth_link *link = &dev->data->dev_link; 791 struct ena_adapter *adapter; 792 793 adapter = (struct ena_adapter *)(dev->data->dev_private); 794 795 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 796 link->link_speed = ETH_SPEED_NUM_NONE; 797 link->link_duplex = ETH_LINK_FULL_DUPLEX; 798 799 return 0; 800 } 801 802 static int ena_queue_start_all(struct rte_eth_dev *dev, 803 enum ena_ring_type ring_type) 804 { 805 struct ena_adapter *adapter = 806 (struct ena_adapter *)(dev->data->dev_private); 807 struct ena_ring *queues = NULL; 808 int nb_queues; 809 int i = 0; 810 int rc = 0; 811 812 if (ring_type == ENA_RING_TYPE_RX) { 813 queues = adapter->rx_ring; 814 nb_queues = dev->data->nb_rx_queues; 815 } else { 816 queues = adapter->tx_ring; 817 nb_queues = dev->data->nb_tx_queues; 818 } 819 for (i = 0; i < nb_queues; i++) { 820 if (queues[i].configured) { 821 if (ring_type == ENA_RING_TYPE_RX) { 822 ena_assert_msg( 823 dev->data->rx_queues[i] == &queues[i], 824 "Inconsistent state of rx queues\n"); 825 } else { 826 ena_assert_msg( 827 dev->data->tx_queues[i] == &queues[i], 828 "Inconsistent state of tx queues\n"); 829 } 830 831 rc = ena_queue_start(&queues[i]); 832 833 if (rc) { 834 PMD_INIT_LOG(ERR, 835 "failed to start queue %d type(%d)", 836 i, ring_type); 837 goto err; 838 } 839 } 840 } 841 842 return 0; 843 844 err: 845 while (i--) 846 if (queues[i].configured) 847 ena_queue_stop(&queues[i]); 848 849 return rc; 850 } 851 852 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 853 { 854 uint32_t max_frame_len = adapter->max_mtu; 855 856 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 857 DEV_RX_OFFLOAD_JUMBO_FRAME) 858 max_frame_len = 859 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 860 861 return max_frame_len; 862 } 863 864 static int ena_check_valid_conf(struct ena_adapter *adapter) 865 { 866 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 867 868 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 869 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 870 "max mtu: %d, min mtu: %d\n", 871 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 872 return ENA_COM_UNSUPPORTED; 873 } 874 875 return 0; 876 } 877 878 static int 879 ena_calc_queue_size(struct ena_com_dev *ena_dev, 880 u16 *max_tx_sgl_size, 881 struct ena_com_dev_get_features_ctx *get_feat_ctx) 882 { 883 uint32_t queue_size = ENA_DEFAULT_RING_SIZE; 884 885 queue_size = RTE_MIN(queue_size, 886 get_feat_ctx->max_queues.max_cq_depth); 887 queue_size = RTE_MIN(queue_size, 888 get_feat_ctx->max_queues.max_sq_depth); 889 890 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 891 queue_size = RTE_MIN(queue_size, 892 get_feat_ctx->max_queues.max_llq_depth); 893 894 /* Round down to power of 2 */ 895 if (!rte_is_power_of_2(queue_size)) 896 queue_size = rte_align32pow2(queue_size >> 1); 897 898 if (unlikely(queue_size == 0)) { 899 PMD_INIT_LOG(ERR, "Invalid queue size"); 900 return -EFAULT; 901 } 902 903 *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 904 get_feat_ctx->max_queues.max_packet_tx_descs); 905 906 return queue_size; 907 } 908 909 static void ena_stats_restart(struct rte_eth_dev *dev) 910 { 911 struct ena_adapter *adapter = 912 (struct ena_adapter *)(dev->data->dev_private); 913 914 rte_atomic64_init(&adapter->drv_stats->ierrors); 915 rte_atomic64_init(&adapter->drv_stats->oerrors); 916 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 917 } 918 919 static int ena_stats_get(struct rte_eth_dev *dev, 920 struct rte_eth_stats *stats) 921 { 922 struct ena_admin_basic_stats ena_stats; 923 struct ena_adapter *adapter = 924 (struct ena_adapter *)(dev->data->dev_private); 925 struct ena_com_dev *ena_dev = &adapter->ena_dev; 926 int rc; 927 928 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 929 return -ENOTSUP; 930 931 memset(&ena_stats, 0, sizeof(ena_stats)); 932 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 933 if (unlikely(rc)) { 934 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA"); 935 return rc; 936 } 937 938 /* Set of basic statistics from ENA */ 939 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 940 ena_stats.rx_pkts_low); 941 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 942 ena_stats.tx_pkts_low); 943 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 944 ena_stats.rx_bytes_low); 945 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 946 ena_stats.tx_bytes_low); 947 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high, 948 ena_stats.rx_drops_low); 949 950 /* Driver related stats */ 951 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 952 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 953 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 954 return 0; 955 } 956 957 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 958 { 959 struct ena_adapter *adapter; 960 struct ena_com_dev *ena_dev; 961 int rc = 0; 962 963 ena_assert_msg(dev->data != NULL, "Uninitialized device"); 964 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device"); 965 adapter = (struct ena_adapter *)(dev->data->dev_private); 966 967 ena_dev = &adapter->ena_dev; 968 ena_assert_msg(ena_dev != NULL, "Uninitialized device"); 969 970 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 971 RTE_LOG(ERR, PMD, 972 "Invalid MTU setting. new_mtu: %d " 973 "max mtu: %d min mtu: %d\n", 974 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 975 return -EINVAL; 976 } 977 978 rc = ena_com_set_dev_mtu(ena_dev, mtu); 979 if (rc) 980 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu); 981 else 982 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu); 983 984 return rc; 985 } 986 987 static int ena_start(struct rte_eth_dev *dev) 988 { 989 struct ena_adapter *adapter = 990 (struct ena_adapter *)(dev->data->dev_private); 991 uint64_t ticks; 992 int rc = 0; 993 994 rc = ena_check_valid_conf(adapter); 995 if (rc) 996 return rc; 997 998 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 999 if (rc) 1000 return rc; 1001 1002 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1003 if (rc) 1004 goto err_start_tx; 1005 1006 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1007 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1008 rc = ena_rss_init_default(adapter); 1009 if (rc) 1010 goto err_rss_init; 1011 } 1012 1013 ena_stats_restart(dev); 1014 1015 adapter->timestamp_wd = rte_get_timer_cycles(); 1016 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1017 1018 ticks = rte_get_timer_hz(); 1019 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1020 ena_timer_wd_callback, adapter); 1021 1022 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1023 1024 return 0; 1025 1026 err_rss_init: 1027 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1028 err_start_tx: 1029 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1030 return rc; 1031 } 1032 1033 static void ena_stop(struct rte_eth_dev *dev) 1034 { 1035 struct ena_adapter *adapter = 1036 (struct ena_adapter *)(dev->data->dev_private); 1037 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1038 int rc; 1039 1040 rte_timer_stop_sync(&adapter->timer_wd); 1041 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1042 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1043 1044 if (adapter->trigger_reset) { 1045 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1046 if (rc) 1047 RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc); 1048 } 1049 1050 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1051 } 1052 1053 static int ena_create_io_queue(struct ena_ring *ring) 1054 { 1055 struct ena_adapter *adapter; 1056 struct ena_com_dev *ena_dev; 1057 struct ena_com_create_io_ctx ctx = 1058 /* policy set to _HOST just to satisfy icc compiler */ 1059 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1060 0, 0, 0, 0, 0 }; 1061 uint16_t ena_qid; 1062 unsigned int i; 1063 int rc; 1064 1065 adapter = ring->adapter; 1066 ena_dev = &adapter->ena_dev; 1067 1068 if (ring->type == ENA_RING_TYPE_TX) { 1069 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1070 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1071 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1072 ctx.queue_size = adapter->tx_ring_size; 1073 for (i = 0; i < ring->ring_size; i++) 1074 ring->empty_tx_reqs[i] = i; 1075 } else { 1076 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1077 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1078 ctx.queue_size = adapter->rx_ring_size; 1079 for (i = 0; i < ring->ring_size; i++) 1080 ring->empty_rx_reqs[i] = i; 1081 } 1082 ctx.qid = ena_qid; 1083 ctx.msix_vector = -1; /* interrupts not used */ 1084 ctx.numa_node = ena_cpu_to_node(ring->id); 1085 1086 rc = ena_com_create_io_queue(ena_dev, &ctx); 1087 if (rc) { 1088 RTE_LOG(ERR, PMD, 1089 "failed to create io queue #%d (qid:%d) rc: %d\n", 1090 ring->id, ena_qid, rc); 1091 return rc; 1092 } 1093 1094 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1095 &ring->ena_com_io_sq, 1096 &ring->ena_com_io_cq); 1097 if (rc) { 1098 RTE_LOG(ERR, PMD, 1099 "Failed to get io queue handlers. queue num %d rc: %d\n", 1100 ring->id, rc); 1101 ena_com_destroy_io_queue(ena_dev, ena_qid); 1102 return rc; 1103 } 1104 1105 if (ring->type == ENA_RING_TYPE_TX) 1106 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1107 1108 return 0; 1109 } 1110 1111 static void ena_queue_stop(struct ena_ring *ring) 1112 { 1113 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1114 1115 if (ring->type == ENA_RING_TYPE_RX) { 1116 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1117 ena_rx_queue_release_bufs(ring); 1118 } else { 1119 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1120 ena_tx_queue_release_bufs(ring); 1121 } 1122 } 1123 1124 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1125 enum ena_ring_type ring_type) 1126 { 1127 struct ena_adapter *adapter = 1128 (struct ena_adapter *)(dev->data->dev_private); 1129 struct ena_ring *queues = NULL; 1130 uint16_t nb_queues, i; 1131 1132 if (ring_type == ENA_RING_TYPE_RX) { 1133 queues = adapter->rx_ring; 1134 nb_queues = dev->data->nb_rx_queues; 1135 } else { 1136 queues = adapter->tx_ring; 1137 nb_queues = dev->data->nb_tx_queues; 1138 } 1139 1140 for (i = 0; i < nb_queues; ++i) 1141 if (queues[i].configured) 1142 ena_queue_stop(&queues[i]); 1143 } 1144 1145 static int ena_queue_start(struct ena_ring *ring) 1146 { 1147 int rc, bufs_num; 1148 1149 ena_assert_msg(ring->configured == 1, 1150 "Trying to start unconfigured queue\n"); 1151 1152 rc = ena_create_io_queue(ring); 1153 if (rc) { 1154 PMD_INIT_LOG(ERR, "Failed to create IO queue!\n"); 1155 return rc; 1156 } 1157 1158 ring->next_to_clean = 0; 1159 ring->next_to_use = 0; 1160 1161 if (ring->type == ENA_RING_TYPE_TX) 1162 return 0; 1163 1164 bufs_num = ring->ring_size - 1; 1165 rc = ena_populate_rx_queue(ring, bufs_num); 1166 if (rc != bufs_num) { 1167 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1168 ENA_IO_RXQ_IDX(ring->id)); 1169 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1170 return ENA_COM_FAULT; 1171 } 1172 1173 return 0; 1174 } 1175 1176 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1177 uint16_t queue_idx, 1178 uint16_t nb_desc, 1179 __rte_unused unsigned int socket_id, 1180 const struct rte_eth_txconf *tx_conf) 1181 { 1182 struct ena_ring *txq = NULL; 1183 struct ena_adapter *adapter = 1184 (struct ena_adapter *)(dev->data->dev_private); 1185 unsigned int i; 1186 1187 txq = &adapter->tx_ring[queue_idx]; 1188 1189 if (txq->configured) { 1190 RTE_LOG(CRIT, PMD, 1191 "API violation. Queue %d is already configured\n", 1192 queue_idx); 1193 return ENA_COM_FAULT; 1194 } 1195 1196 if (!rte_is_power_of_2(nb_desc)) { 1197 RTE_LOG(ERR, PMD, 1198 "Unsupported size of TX queue: %d is not a power of 2.", 1199 nb_desc); 1200 return -EINVAL; 1201 } 1202 1203 if (nb_desc > adapter->tx_ring_size) { 1204 RTE_LOG(ERR, PMD, 1205 "Unsupported size of TX queue (max size: %d)\n", 1206 adapter->tx_ring_size); 1207 return -EINVAL; 1208 } 1209 1210 txq->port_id = dev->data->port_id; 1211 txq->next_to_clean = 0; 1212 txq->next_to_use = 0; 1213 txq->ring_size = nb_desc; 1214 1215 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1216 sizeof(struct ena_tx_buffer) * 1217 txq->ring_size, 1218 RTE_CACHE_LINE_SIZE); 1219 if (!txq->tx_buffer_info) { 1220 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n"); 1221 return -ENOMEM; 1222 } 1223 1224 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1225 sizeof(u16) * txq->ring_size, 1226 RTE_CACHE_LINE_SIZE); 1227 if (!txq->empty_tx_reqs) { 1228 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n"); 1229 rte_free(txq->tx_buffer_info); 1230 return -ENOMEM; 1231 } 1232 1233 for (i = 0; i < txq->ring_size; i++) 1234 txq->empty_tx_reqs[i] = i; 1235 1236 if (tx_conf != NULL) { 1237 txq->offloads = 1238 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1239 } 1240 1241 /* Store pointer to this queue in upper layer */ 1242 txq->configured = 1; 1243 dev->data->tx_queues[queue_idx] = txq; 1244 1245 return 0; 1246 } 1247 1248 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1249 uint16_t queue_idx, 1250 uint16_t nb_desc, 1251 __rte_unused unsigned int socket_id, 1252 __rte_unused const struct rte_eth_rxconf *rx_conf, 1253 struct rte_mempool *mp) 1254 { 1255 struct ena_adapter *adapter = 1256 (struct ena_adapter *)(dev->data->dev_private); 1257 struct ena_ring *rxq = NULL; 1258 int i; 1259 1260 rxq = &adapter->rx_ring[queue_idx]; 1261 if (rxq->configured) { 1262 RTE_LOG(CRIT, PMD, 1263 "API violation. Queue %d is already configured\n", 1264 queue_idx); 1265 return ENA_COM_FAULT; 1266 } 1267 1268 if (!rte_is_power_of_2(nb_desc)) { 1269 RTE_LOG(ERR, PMD, 1270 "Unsupported size of RX queue: %d is not a power of 2.", 1271 nb_desc); 1272 return -EINVAL; 1273 } 1274 1275 if (nb_desc > adapter->rx_ring_size) { 1276 RTE_LOG(ERR, PMD, 1277 "Unsupported size of RX queue (max size: %d)\n", 1278 adapter->rx_ring_size); 1279 return -EINVAL; 1280 } 1281 1282 rxq->port_id = dev->data->port_id; 1283 rxq->next_to_clean = 0; 1284 rxq->next_to_use = 0; 1285 rxq->ring_size = nb_desc; 1286 rxq->mb_pool = mp; 1287 1288 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1289 sizeof(struct rte_mbuf *) * nb_desc, 1290 RTE_CACHE_LINE_SIZE); 1291 if (!rxq->rx_buffer_info) { 1292 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n"); 1293 return -ENOMEM; 1294 } 1295 1296 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1297 sizeof(struct rte_mbuf *) * nb_desc, 1298 RTE_CACHE_LINE_SIZE); 1299 1300 if (!rxq->rx_refill_buffer) { 1301 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n"); 1302 rte_free(rxq->rx_buffer_info); 1303 rxq->rx_buffer_info = NULL; 1304 return -ENOMEM; 1305 } 1306 1307 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1308 sizeof(uint16_t) * nb_desc, 1309 RTE_CACHE_LINE_SIZE); 1310 if (!rxq->empty_rx_reqs) { 1311 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n"); 1312 rte_free(rxq->rx_buffer_info); 1313 rxq->rx_buffer_info = NULL; 1314 rte_free(rxq->rx_refill_buffer); 1315 rxq->rx_refill_buffer = NULL; 1316 return -ENOMEM; 1317 } 1318 1319 for (i = 0; i < nb_desc; i++) 1320 rxq->empty_rx_reqs[i] = i; 1321 1322 /* Store pointer to this queue in upper layer */ 1323 rxq->configured = 1; 1324 dev->data->rx_queues[queue_idx] = rxq; 1325 1326 return 0; 1327 } 1328 1329 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1330 { 1331 unsigned int i; 1332 int rc; 1333 uint16_t ring_size = rxq->ring_size; 1334 uint16_t ring_mask = ring_size - 1; 1335 uint16_t next_to_use = rxq->next_to_use; 1336 uint16_t in_use, req_id; 1337 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1338 1339 if (unlikely(!count)) 1340 return 0; 1341 1342 in_use = rxq->next_to_use - rxq->next_to_clean; 1343 ena_assert_msg(((in_use + count) < ring_size), "bad ring state"); 1344 1345 /* get resources for incoming packets */ 1346 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1347 if (unlikely(rc < 0)) { 1348 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1349 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1350 return 0; 1351 } 1352 1353 for (i = 0; i < count; i++) { 1354 uint16_t next_to_use_masked = next_to_use & ring_mask; 1355 struct rte_mbuf *mbuf = mbufs[i]; 1356 struct ena_com_buf ebuf; 1357 1358 if (likely((i + 4) < count)) 1359 rte_prefetch0(mbufs[i + 4]); 1360 1361 req_id = rxq->empty_rx_reqs[next_to_use_masked]; 1362 rc = validate_rx_req_id(rxq, req_id); 1363 if (unlikely(rc < 0)) 1364 break; 1365 rxq->rx_buffer_info[req_id] = mbuf; 1366 1367 /* prepare physical address for DMA transaction */ 1368 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1369 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1370 /* pass resource to device */ 1371 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, 1372 &ebuf, req_id); 1373 if (unlikely(rc)) { 1374 RTE_LOG(WARNING, PMD, "failed adding rx desc\n"); 1375 rxq->rx_buffer_info[req_id] = NULL; 1376 break; 1377 } 1378 next_to_use++; 1379 } 1380 1381 if (unlikely(i < count)) { 1382 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d " 1383 "buffers (from %d)\n", rxq->id, i, count); 1384 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1385 count - i); 1386 } 1387 1388 /* When we submitted free recources to device... */ 1389 if (likely(i > 0)) { 1390 /* ...let HW know that it can fill buffers with data 1391 * 1392 * Add memory barrier to make sure the desc were written before 1393 * issue a doorbell 1394 */ 1395 rte_wmb(); 1396 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1397 1398 rxq->next_to_use = next_to_use; 1399 } 1400 1401 return i; 1402 } 1403 1404 static int ena_device_init(struct ena_com_dev *ena_dev, 1405 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1406 bool *wd_state) 1407 { 1408 uint32_t aenq_groups; 1409 int rc; 1410 bool readless_supported; 1411 1412 /* Initialize mmio registers */ 1413 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1414 if (rc) { 1415 RTE_LOG(ERR, PMD, "failed to init mmio read less\n"); 1416 return rc; 1417 } 1418 1419 /* The PCIe configuration space revision id indicate if mmio reg 1420 * read is disabled. 1421 */ 1422 readless_supported = 1423 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1424 & ENA_MMIO_DISABLE_REG_READ); 1425 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1426 1427 /* reset device */ 1428 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1429 if (rc) { 1430 RTE_LOG(ERR, PMD, "cannot reset device\n"); 1431 goto err_mmio_read_less; 1432 } 1433 1434 /* check FW version */ 1435 rc = ena_com_validate_version(ena_dev); 1436 if (rc) { 1437 RTE_LOG(ERR, PMD, "device version is too low\n"); 1438 goto err_mmio_read_less; 1439 } 1440 1441 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1442 1443 /* ENA device administration layer init */ 1444 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true); 1445 if (rc) { 1446 RTE_LOG(ERR, PMD, 1447 "cannot initialize ena admin queue with device\n"); 1448 goto err_mmio_read_less; 1449 } 1450 1451 /* To enable the msix interrupts the driver needs to know the number 1452 * of queues. So the driver uses polling mode to retrieve this 1453 * information. 1454 */ 1455 ena_com_set_admin_polling_mode(ena_dev, true); 1456 1457 ena_config_host_info(ena_dev); 1458 1459 /* Get Device Attributes and features */ 1460 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1461 if (rc) { 1462 RTE_LOG(ERR, PMD, 1463 "cannot get attribute for ena device rc= %d\n", rc); 1464 goto err_admin_init; 1465 } 1466 1467 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1468 BIT(ENA_ADMIN_NOTIFICATION) | 1469 BIT(ENA_ADMIN_KEEP_ALIVE) | 1470 BIT(ENA_ADMIN_FATAL_ERROR) | 1471 BIT(ENA_ADMIN_WARNING); 1472 1473 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1474 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1475 if (rc) { 1476 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc); 1477 goto err_admin_init; 1478 } 1479 1480 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1481 1482 return 0; 1483 1484 err_admin_init: 1485 ena_com_admin_destroy(ena_dev); 1486 1487 err_mmio_read_less: 1488 ena_com_mmio_reg_read_request_destroy(ena_dev); 1489 1490 return rc; 1491 } 1492 1493 static void ena_interrupt_handler_rte(void *cb_arg) 1494 { 1495 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg; 1496 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1497 1498 ena_com_admin_q_comp_intr_handler(ena_dev); 1499 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1500 ena_com_aenq_intr_handler(ena_dev, adapter); 1501 } 1502 1503 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1504 { 1505 if (!adapter->wd_state) 1506 return; 1507 1508 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1509 return; 1510 1511 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1512 adapter->keep_alive_timeout)) { 1513 RTE_LOG(ERR, PMD, "Keep alive timeout\n"); 1514 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1515 adapter->trigger_reset = true; 1516 } 1517 } 1518 1519 /* Check if admin queue is enabled */ 1520 static void check_for_admin_com_state(struct ena_adapter *adapter) 1521 { 1522 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1523 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n"); 1524 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1525 adapter->trigger_reset = true; 1526 } 1527 } 1528 1529 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1530 void *arg) 1531 { 1532 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1533 struct rte_eth_dev *dev = adapter->rte_dev; 1534 1535 check_for_missing_keep_alive(adapter); 1536 check_for_admin_com_state(adapter); 1537 1538 if (unlikely(adapter->trigger_reset)) { 1539 RTE_LOG(ERR, PMD, "Trigger reset is on\n"); 1540 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1541 NULL); 1542 } 1543 } 1544 1545 static int ena_calc_io_queue_num(__rte_unused struct ena_com_dev *ena_dev, 1546 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1547 { 1548 int io_sq_num, io_cq_num, io_queue_num; 1549 1550 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 1551 io_cq_num = get_feat_ctx->max_queues.max_cq_num; 1552 1553 io_queue_num = RTE_MIN(io_sq_num, io_cq_num); 1554 1555 if (unlikely(io_queue_num == 0)) { 1556 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n"); 1557 return -EFAULT; 1558 } 1559 1560 return io_queue_num; 1561 } 1562 1563 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1564 { 1565 struct rte_pci_device *pci_dev; 1566 struct rte_intr_handle *intr_handle; 1567 struct ena_adapter *adapter = 1568 (struct ena_adapter *)(eth_dev->data->dev_private); 1569 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1570 struct ena_com_dev_get_features_ctx get_feat_ctx; 1571 int queue_size, rc; 1572 u16 tx_sgl_size = 0; 1573 1574 static int adapters_found; 1575 bool wd_state; 1576 1577 eth_dev->dev_ops = &ena_dev_ops; 1578 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1579 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1580 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1581 1582 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1583 return 0; 1584 1585 memset(adapter, 0, sizeof(struct ena_adapter)); 1586 ena_dev = &adapter->ena_dev; 1587 1588 adapter->rte_eth_dev_data = eth_dev->data; 1589 adapter->rte_dev = eth_dev; 1590 1591 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1592 adapter->pdev = pci_dev; 1593 1594 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1595 pci_dev->addr.domain, 1596 pci_dev->addr.bus, 1597 pci_dev->addr.devid, 1598 pci_dev->addr.function); 1599 1600 intr_handle = &pci_dev->intr_handle; 1601 1602 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1603 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1604 1605 if (!adapter->regs) { 1606 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1607 ENA_REGS_BAR); 1608 return -ENXIO; 1609 } 1610 1611 ena_dev->reg_bar = adapter->regs; 1612 ena_dev->dmadev = adapter->pdev; 1613 1614 adapter->id_number = adapters_found; 1615 1616 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1617 adapter->id_number); 1618 1619 /* device specific initialization routine */ 1620 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1621 if (rc) { 1622 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1623 goto err; 1624 } 1625 adapter->wd_state = wd_state; 1626 1627 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1628 adapter->num_queues = ena_calc_io_queue_num(ena_dev, 1629 &get_feat_ctx); 1630 1631 queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx); 1632 if (queue_size <= 0 || adapter->num_queues <= 0) { 1633 rc = -EFAULT; 1634 goto err_device_destroy; 1635 } 1636 1637 adapter->tx_ring_size = queue_size; 1638 adapter->rx_ring_size = queue_size; 1639 1640 adapter->max_tx_sgl_size = tx_sgl_size; 1641 1642 /* prepare ring structures */ 1643 ena_init_rings(adapter); 1644 1645 ena_config_debug_area(adapter); 1646 1647 /* Set max MTU for this device */ 1648 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1649 1650 /* set device support for TSO */ 1651 adapter->tso4_supported = get_feat_ctx.offload.tx & 1652 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK; 1653 1654 /* Copy MAC address and point DPDK to it */ 1655 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr; 1656 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr, 1657 (struct ether_addr *)adapter->mac_addr); 1658 1659 /* 1660 * Pass the information to the rte_eth_dev_close() that it should also 1661 * release the private port resources. 1662 */ 1663 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1664 1665 adapter->drv_stats = rte_zmalloc("adapter stats", 1666 sizeof(*adapter->drv_stats), 1667 RTE_CACHE_LINE_SIZE); 1668 if (!adapter->drv_stats) { 1669 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n"); 1670 rc = -ENOMEM; 1671 goto err_delete_debug_area; 1672 } 1673 1674 rte_intr_callback_register(intr_handle, 1675 ena_interrupt_handler_rte, 1676 adapter); 1677 rte_intr_enable(intr_handle); 1678 ena_com_set_admin_polling_mode(ena_dev, false); 1679 ena_com_admin_aenq_enable(ena_dev); 1680 1681 if (adapters_found == 0) 1682 rte_timer_subsystem_init(); 1683 rte_timer_init(&adapter->timer_wd); 1684 1685 adapters_found++; 1686 adapter->state = ENA_ADAPTER_STATE_INIT; 1687 1688 return 0; 1689 1690 err_delete_debug_area: 1691 ena_com_delete_debug_area(ena_dev); 1692 1693 err_device_destroy: 1694 ena_com_delete_host_info(ena_dev); 1695 ena_com_admin_destroy(ena_dev); 1696 1697 err: 1698 return rc; 1699 } 1700 1701 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1702 { 1703 struct ena_adapter *adapter = 1704 (struct ena_adapter *)(eth_dev->data->dev_private); 1705 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1706 1707 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1708 return; 1709 1710 ena_com_set_admin_running_state(ena_dev, false); 1711 1712 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1713 ena_close(eth_dev); 1714 1715 ena_com_delete_debug_area(ena_dev); 1716 ena_com_delete_host_info(ena_dev); 1717 1718 ena_com_abort_admin_commands(ena_dev); 1719 ena_com_wait_for_abort_completion(ena_dev); 1720 ena_com_admin_destroy(ena_dev); 1721 ena_com_mmio_reg_read_request_destroy(ena_dev); 1722 1723 adapter->state = ENA_ADAPTER_STATE_FREE; 1724 } 1725 1726 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1727 { 1728 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1729 return 0; 1730 1731 ena_destroy_device(eth_dev); 1732 1733 eth_dev->dev_ops = NULL; 1734 eth_dev->rx_pkt_burst = NULL; 1735 eth_dev->tx_pkt_burst = NULL; 1736 eth_dev->tx_pkt_prepare = NULL; 1737 1738 return 0; 1739 } 1740 1741 static int ena_dev_configure(struct rte_eth_dev *dev) 1742 { 1743 struct ena_adapter *adapter = 1744 (struct ena_adapter *)(dev->data->dev_private); 1745 1746 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1747 1748 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1749 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1750 return 0; 1751 } 1752 1753 static void ena_init_rings(struct ena_adapter *adapter) 1754 { 1755 int i; 1756 1757 for (i = 0; i < adapter->num_queues; i++) { 1758 struct ena_ring *ring = &adapter->tx_ring[i]; 1759 1760 ring->configured = 0; 1761 ring->type = ENA_RING_TYPE_TX; 1762 ring->adapter = adapter; 1763 ring->id = i; 1764 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1765 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1766 ring->sgl_size = adapter->max_tx_sgl_size; 1767 } 1768 1769 for (i = 0; i < adapter->num_queues; i++) { 1770 struct ena_ring *ring = &adapter->rx_ring[i]; 1771 1772 ring->configured = 0; 1773 ring->type = ENA_RING_TYPE_RX; 1774 ring->adapter = adapter; 1775 ring->id = i; 1776 } 1777 } 1778 1779 static void ena_infos_get(struct rte_eth_dev *dev, 1780 struct rte_eth_dev_info *dev_info) 1781 { 1782 struct ena_adapter *adapter; 1783 struct ena_com_dev *ena_dev; 1784 struct ena_com_dev_get_features_ctx feat; 1785 uint64_t rx_feat = 0, tx_feat = 0; 1786 int rc = 0; 1787 1788 ena_assert_msg(dev->data != NULL, "Uninitialized device"); 1789 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device"); 1790 adapter = (struct ena_adapter *)(dev->data->dev_private); 1791 1792 ena_dev = &adapter->ena_dev; 1793 ena_assert_msg(ena_dev != NULL, "Uninitialized device"); 1794 1795 dev_info->speed_capa = 1796 ETH_LINK_SPEED_1G | 1797 ETH_LINK_SPEED_2_5G | 1798 ETH_LINK_SPEED_5G | 1799 ETH_LINK_SPEED_10G | 1800 ETH_LINK_SPEED_25G | 1801 ETH_LINK_SPEED_40G | 1802 ETH_LINK_SPEED_50G | 1803 ETH_LINK_SPEED_100G; 1804 1805 /* Get supported features from HW */ 1806 rc = ena_com_get_dev_attr_feat(ena_dev, &feat); 1807 if (unlikely(rc)) { 1808 RTE_LOG(ERR, PMD, 1809 "Cannot get attribute for ena device rc= %d\n", rc); 1810 return; 1811 } 1812 1813 /* Set Tx & Rx features available for device */ 1814 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) 1815 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1816 1817 if (feat.offload.tx & 1818 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) 1819 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1820 DEV_TX_OFFLOAD_UDP_CKSUM | 1821 DEV_TX_OFFLOAD_TCP_CKSUM; 1822 1823 if (feat.offload.rx_supported & 1824 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) 1825 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1826 DEV_RX_OFFLOAD_UDP_CKSUM | 1827 DEV_RX_OFFLOAD_TCP_CKSUM; 1828 1829 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 1830 1831 /* Inform framework about available features */ 1832 dev_info->rx_offload_capa = rx_feat; 1833 dev_info->rx_queue_offload_capa = rx_feat; 1834 dev_info->tx_offload_capa = tx_feat; 1835 dev_info->tx_queue_offload_capa = tx_feat; 1836 1837 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 1838 ETH_RSS_UDP; 1839 1840 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 1841 dev_info->max_rx_pktlen = adapter->max_mtu; 1842 dev_info->max_mac_addrs = 1; 1843 1844 dev_info->max_rx_queues = adapter->num_queues; 1845 dev_info->max_tx_queues = adapter->num_queues; 1846 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 1847 1848 adapter->tx_supported_offloads = tx_feat; 1849 adapter->rx_supported_offloads = rx_feat; 1850 1851 dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC; 1852 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1853 1854 dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC; 1855 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1856 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1857 feat.max_queues.max_packet_tx_descs); 1858 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1859 feat.max_queues.max_packet_tx_descs); 1860 } 1861 1862 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 1863 uint16_t nb_pkts) 1864 { 1865 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 1866 unsigned int ring_size = rx_ring->ring_size; 1867 unsigned int ring_mask = ring_size - 1; 1868 uint16_t next_to_clean = rx_ring->next_to_clean; 1869 uint16_t desc_in_use = 0; 1870 uint16_t req_id; 1871 unsigned int recv_idx = 0; 1872 struct rte_mbuf *mbuf = NULL; 1873 struct rte_mbuf *mbuf_head = NULL; 1874 struct rte_mbuf *mbuf_prev = NULL; 1875 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; 1876 unsigned int completed; 1877 1878 struct ena_com_rx_ctx ena_rx_ctx; 1879 int rc = 0; 1880 1881 /* Check adapter state */ 1882 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 1883 RTE_LOG(ALERT, PMD, 1884 "Trying to receive pkts while device is NOT running\n"); 1885 return 0; 1886 } 1887 1888 desc_in_use = rx_ring->next_to_use - next_to_clean; 1889 if (unlikely(nb_pkts > desc_in_use)) 1890 nb_pkts = desc_in_use; 1891 1892 for (completed = 0; completed < nb_pkts; completed++) { 1893 int segments = 0; 1894 1895 ena_rx_ctx.max_bufs = rx_ring->ring_size; 1896 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1897 ena_rx_ctx.descs = 0; 1898 /* receive packet context */ 1899 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 1900 rx_ring->ena_com_io_sq, 1901 &ena_rx_ctx); 1902 if (unlikely(rc)) { 1903 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc); 1904 rx_ring->adapter->reset_reason = 1905 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 1906 rx_ring->adapter->trigger_reset = true; 1907 return 0; 1908 } 1909 1910 if (unlikely(ena_rx_ctx.descs == 0)) 1911 break; 1912 1913 while (segments < ena_rx_ctx.descs) { 1914 req_id = ena_rx_ctx.ena_bufs[segments].req_id; 1915 rc = validate_rx_req_id(rx_ring, req_id); 1916 if (unlikely(rc)) { 1917 if (segments != 0) 1918 rte_mbuf_raw_free(mbuf_head); 1919 break; 1920 } 1921 1922 mbuf = rx_buff_info[req_id]; 1923 rx_buff_info[req_id] = NULL; 1924 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; 1925 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 1926 mbuf->refcnt = 1; 1927 mbuf->next = NULL; 1928 if (unlikely(segments == 0)) { 1929 mbuf->nb_segs = ena_rx_ctx.descs; 1930 mbuf->port = rx_ring->port_id; 1931 mbuf->pkt_len = 0; 1932 mbuf_head = mbuf; 1933 } else { 1934 /* for multi-segment pkts create mbuf chain */ 1935 mbuf_prev->next = mbuf; 1936 } 1937 mbuf_head->pkt_len += mbuf->data_len; 1938 1939 mbuf_prev = mbuf; 1940 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = 1941 req_id; 1942 segments++; 1943 next_to_clean++; 1944 } 1945 if (unlikely(rc)) 1946 break; 1947 1948 /* fill mbuf attributes if any */ 1949 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); 1950 mbuf_head->hash.rss = ena_rx_ctx.hash; 1951 1952 /* pass to DPDK application head mbuf */ 1953 rx_pkts[recv_idx] = mbuf_head; 1954 recv_idx++; 1955 } 1956 1957 rx_ring->next_to_clean = next_to_clean; 1958 1959 desc_in_use = desc_in_use - completed + 1; 1960 /* Burst refill to save doorbells, memory barriers, const interval */ 1961 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) { 1962 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1963 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); 1964 } 1965 1966 return recv_idx; 1967 } 1968 1969 static uint16_t 1970 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 1971 uint16_t nb_pkts) 1972 { 1973 int32_t ret; 1974 uint32_t i; 1975 struct rte_mbuf *m; 1976 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 1977 struct ipv4_hdr *ip_hdr; 1978 uint64_t ol_flags; 1979 uint16_t frag_field; 1980 1981 for (i = 0; i != nb_pkts; i++) { 1982 m = tx_pkts[i]; 1983 ol_flags = m->ol_flags; 1984 1985 if (!(ol_flags & PKT_TX_IPV4)) 1986 continue; 1987 1988 /* If there was not L2 header length specified, assume it is 1989 * length of the ethernet header. 1990 */ 1991 if (unlikely(m->l2_len == 0)) 1992 m->l2_len = sizeof(struct ether_hdr); 1993 1994 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, 1995 m->l2_len); 1996 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 1997 1998 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) { 1999 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2000 2001 /* If IPv4 header has DF flag enabled and TSO support is 2002 * disabled, partial chcecksum should not be calculated. 2003 */ 2004 if (!tx_ring->adapter->tso4_supported) 2005 continue; 2006 } 2007 2008 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2009 (ol_flags & PKT_TX_L4_MASK) == 2010 PKT_TX_SCTP_CKSUM) { 2011 rte_errno = ENOTSUP; 2012 return i; 2013 } 2014 2015 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2016 ret = rte_validate_tx_offload(m); 2017 if (ret != 0) { 2018 rte_errno = -ret; 2019 return i; 2020 } 2021 #endif 2022 2023 /* In case we are supposed to TSO and have DF not set (DF=0) 2024 * hardware must be provided with partial checksum, otherwise 2025 * it will take care of necessary calculations. 2026 */ 2027 2028 ret = rte_net_intel_cksum_flags_prepare(m, 2029 ol_flags & ~PKT_TX_TCP_SEG); 2030 if (ret != 0) { 2031 rte_errno = -ret; 2032 return i; 2033 } 2034 } 2035 2036 return i; 2037 } 2038 2039 static void ena_update_hints(struct ena_adapter *adapter, 2040 struct ena_admin_ena_hw_hints *hints) 2041 { 2042 if (hints->admin_completion_tx_timeout) 2043 adapter->ena_dev.admin_queue.completion_timeout = 2044 hints->admin_completion_tx_timeout * 1000; 2045 2046 if (hints->mmio_read_timeout) 2047 /* convert to usec */ 2048 adapter->ena_dev.mmio_read.reg_read_to = 2049 hints->mmio_read_timeout * 1000; 2050 2051 if (hints->driver_watchdog_timeout) { 2052 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2053 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2054 else 2055 // Convert msecs to ticks 2056 adapter->keep_alive_timeout = 2057 (hints->driver_watchdog_timeout * 2058 rte_get_timer_hz()) / 1000; 2059 } 2060 } 2061 2062 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2063 struct rte_mbuf *mbuf) 2064 { 2065 int num_segments, rc; 2066 2067 num_segments = mbuf->nb_segs; 2068 2069 if (likely(num_segments < tx_ring->sgl_size)) 2070 return 0; 2071 2072 rc = rte_pktmbuf_linearize(mbuf); 2073 if (unlikely(rc)) 2074 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n"); 2075 2076 return rc; 2077 } 2078 2079 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2080 uint16_t nb_pkts) 2081 { 2082 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2083 uint16_t next_to_use = tx_ring->next_to_use; 2084 uint16_t next_to_clean = tx_ring->next_to_clean; 2085 struct rte_mbuf *mbuf; 2086 unsigned int ring_size = tx_ring->ring_size; 2087 unsigned int ring_mask = ring_size - 1; 2088 struct ena_com_tx_ctx ena_tx_ctx; 2089 struct ena_tx_buffer *tx_info; 2090 struct ena_com_buf *ebuf; 2091 uint16_t rc, req_id, total_tx_descs = 0; 2092 uint16_t sent_idx = 0, empty_tx_reqs; 2093 int nb_hw_desc; 2094 2095 /* Check adapter state */ 2096 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2097 RTE_LOG(ALERT, PMD, 2098 "Trying to xmit pkts while device is NOT running\n"); 2099 return 0; 2100 } 2101 2102 empty_tx_reqs = ring_size - (next_to_use - next_to_clean); 2103 if (nb_pkts > empty_tx_reqs) 2104 nb_pkts = empty_tx_reqs; 2105 2106 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2107 mbuf = tx_pkts[sent_idx]; 2108 2109 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2110 if (unlikely(rc)) 2111 break; 2112 2113 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; 2114 tx_info = &tx_ring->tx_buffer_info[req_id]; 2115 tx_info->mbuf = mbuf; 2116 tx_info->num_of_bufs = 0; 2117 ebuf = tx_info->bufs; 2118 2119 /* Prepare TX context */ 2120 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2121 memset(&ena_tx_ctx.ena_meta, 0x0, 2122 sizeof(struct ena_com_tx_meta)); 2123 ena_tx_ctx.ena_bufs = ebuf; 2124 ena_tx_ctx.req_id = req_id; 2125 if (tx_ring->tx_mem_queue_type == 2126 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2127 /* prepare the push buffer with 2128 * virtual address of the data 2129 */ 2130 ena_tx_ctx.header_len = 2131 RTE_MIN(mbuf->data_len, 2132 tx_ring->tx_max_header_size); 2133 ena_tx_ctx.push_header = 2134 (void *)((char *)mbuf->buf_addr + 2135 mbuf->data_off); 2136 } /* there's no else as we take advantage of memset zeroing */ 2137 2138 /* Set TX offloads flags, if applicable */ 2139 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); 2140 2141 if (unlikely(mbuf->ol_flags & 2142 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD))) 2143 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2144 2145 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); 2146 2147 /* Process first segment taking into 2148 * consideration pushed header 2149 */ 2150 if (mbuf->data_len > ena_tx_ctx.header_len) { 2151 ebuf->paddr = mbuf->buf_iova + 2152 mbuf->data_off + 2153 ena_tx_ctx.header_len; 2154 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len; 2155 ebuf++; 2156 tx_info->num_of_bufs++; 2157 } 2158 2159 while ((mbuf = mbuf->next) != NULL) { 2160 ebuf->paddr = mbuf->buf_iova + mbuf->data_off; 2161 ebuf->len = mbuf->data_len; 2162 ebuf++; 2163 tx_info->num_of_bufs++; 2164 } 2165 2166 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2167 2168 /* Write data to device */ 2169 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, 2170 &ena_tx_ctx, &nb_hw_desc); 2171 if (unlikely(rc)) 2172 break; 2173 2174 tx_info->tx_descs = nb_hw_desc; 2175 2176 next_to_use++; 2177 } 2178 2179 /* If there are ready packets to be xmitted... */ 2180 if (sent_idx > 0) { 2181 /* ...let HW do its best :-) */ 2182 rte_wmb(); 2183 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2184 2185 tx_ring->next_to_use = next_to_use; 2186 } 2187 2188 /* Clear complete packets */ 2189 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { 2190 rc = validate_tx_req_id(tx_ring, req_id); 2191 if (rc) 2192 break; 2193 2194 /* Get Tx info & store how many descs were processed */ 2195 tx_info = &tx_ring->tx_buffer_info[req_id]; 2196 total_tx_descs += tx_info->tx_descs; 2197 2198 /* Free whole mbuf chain */ 2199 mbuf = tx_info->mbuf; 2200 rte_pktmbuf_free(mbuf); 2201 tx_info->mbuf = NULL; 2202 2203 /* Put back descriptor to the ring for reuse */ 2204 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; 2205 next_to_clean++; 2206 2207 /* If too many descs to clean, leave it for another run */ 2208 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) 2209 break; 2210 } 2211 2212 if (total_tx_descs > 0) { 2213 /* acknowledge completion of sent packets */ 2214 tx_ring->next_to_clean = next_to_clean; 2215 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2216 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2217 } 2218 2219 return sent_idx; 2220 } 2221 2222 /********************************************************************* 2223 * PMD configuration 2224 *********************************************************************/ 2225 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2226 struct rte_pci_device *pci_dev) 2227 { 2228 return rte_eth_dev_pci_generic_probe(pci_dev, 2229 sizeof(struct ena_adapter), eth_ena_dev_init); 2230 } 2231 2232 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2233 { 2234 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2235 } 2236 2237 static struct rte_pci_driver rte_ena_pmd = { 2238 .id_table = pci_id_ena_map, 2239 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2240 RTE_PCI_DRV_WC_ACTIVATE, 2241 .probe = eth_ena_pci_probe, 2242 .remove = eth_ena_pci_remove, 2243 }; 2244 2245 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2246 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2247 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2248 2249 RTE_INIT(ena_init_log) 2250 { 2251 ena_logtype_init = rte_log_register("pmd.net.ena.init"); 2252 if (ena_logtype_init >= 0) 2253 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE); 2254 ena_logtype_driver = rte_log_register("pmd.net.ena.driver"); 2255 if (ena_logtype_driver >= 0) 2256 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE); 2257 } 2258 2259 /****************************************************************************** 2260 ******************************** AENQ Handlers ******************************* 2261 *****************************************************************************/ 2262 static void ena_update_on_link_change(void *adapter_data, 2263 struct ena_admin_aenq_entry *aenq_e) 2264 { 2265 struct rte_eth_dev *eth_dev; 2266 struct ena_adapter *adapter; 2267 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2268 uint32_t status; 2269 2270 adapter = (struct ena_adapter *)adapter_data; 2271 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2272 eth_dev = adapter->rte_dev; 2273 2274 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2275 adapter->link_status = status; 2276 2277 ena_link_update(eth_dev, 0); 2278 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2279 } 2280 2281 static void ena_notification(void *data, 2282 struct ena_admin_aenq_entry *aenq_e) 2283 { 2284 struct ena_adapter *adapter = (struct ena_adapter *)data; 2285 struct ena_admin_ena_hw_hints *hints; 2286 2287 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2288 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n", 2289 aenq_e->aenq_common_desc.group, 2290 ENA_ADMIN_NOTIFICATION); 2291 2292 switch (aenq_e->aenq_common_desc.syndrom) { 2293 case ENA_ADMIN_UPDATE_HINTS: 2294 hints = (struct ena_admin_ena_hw_hints *) 2295 (&aenq_e->inline_data_w4); 2296 ena_update_hints(adapter, hints); 2297 break; 2298 default: 2299 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n", 2300 aenq_e->aenq_common_desc.syndrom); 2301 } 2302 } 2303 2304 static void ena_keep_alive(void *adapter_data, 2305 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2306 { 2307 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 2308 2309 adapter->timestamp_wd = rte_get_timer_cycles(); 2310 } 2311 2312 /** 2313 * This handler will called for unknown event group or unimplemented handlers 2314 **/ 2315 static void unimplemented_aenq_handler(__rte_unused void *data, 2316 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2317 { 2318 RTE_LOG(ERR, PMD, "Unknown event was received or event with " 2319 "unimplemented handler\n"); 2320 } 2321 2322 static struct ena_aenq_handlers aenq_handlers = { 2323 .handlers = { 2324 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 2325 [ENA_ADMIN_NOTIFICATION] = ena_notification, 2326 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 2327 }, 2328 .unimplemented_handler = unimplemented_aenq_handler 2329 }; 2330