1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "ena_com.h" 35 36 /*****************************************************************************/ 37 /*****************************************************************************/ 38 39 /* Timeout in micro-sec */ 40 #define ADMIN_CMD_TIMEOUT_US (3000000) 41 42 #define ENA_ASYNC_QUEUE_DEPTH 16 43 #define ENA_ADMIN_QUEUE_DEPTH 32 44 45 #ifdef ENA_EXTENDED_STATS 46 47 #define ENA_HISTOGRAM_ACTIVE_MASK_OFFSET 0xF08 48 #define ENA_EXTENDED_STAT_GET_FUNCT(_funct_queue) (_funct_queue & 0xFFFF) 49 #define ENA_EXTENDED_STAT_GET_QUEUE(_funct_queue) (_funct_queue >> 16) 50 51 #endif /* ENA_EXTENDED_STATS */ 52 53 #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \ 54 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \ 55 | (ENA_COMMON_SPEC_VERSION_MINOR)) 56 57 #define ENA_CTRL_MAJOR 0 58 #define ENA_CTRL_MINOR 0 59 #define ENA_CTRL_SUB_MINOR 1 60 61 #define MIN_ENA_CTRL_VER \ 62 (((ENA_CTRL_MAJOR) << \ 63 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \ 64 ((ENA_CTRL_MINOR) << \ 65 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \ 66 (ENA_CTRL_SUB_MINOR)) 67 68 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x))) 69 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32)) 70 71 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF 72 73 #define ENA_REGS_ADMIN_INTR_MASK 1 74 75 #define ENA_POLL_MS 5 76 77 /*****************************************************************************/ 78 /*****************************************************************************/ 79 /*****************************************************************************/ 80 81 enum ena_cmd_status { 82 ENA_CMD_SUBMITTED, 83 ENA_CMD_COMPLETED, 84 /* Abort - canceled by the driver */ 85 ENA_CMD_ABORTED, 86 }; 87 88 struct ena_comp_ctx { 89 ena_wait_event_t wait_event; 90 struct ena_admin_acq_entry *user_cqe; 91 u32 comp_size; 92 enum ena_cmd_status status; 93 /* status from the device */ 94 u8 comp_status; 95 u8 cmd_opcode; 96 bool occupied; 97 }; 98 99 struct ena_com_stats_ctx { 100 struct ena_admin_aq_get_stats_cmd get_cmd; 101 struct ena_admin_acq_get_stats_resp get_resp; 102 }; 103 104 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, 105 struct ena_common_mem_addr *ena_addr, 106 dma_addr_t addr) 107 { 108 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { 109 ena_trc_err("dma address has more bits that the device supports\n"); 110 return ENA_COM_INVAL; 111 } 112 113 ena_addr->mem_addr_low = lower_32_bits(addr); 114 ena_addr->mem_addr_high = (u16)upper_32_bits(addr); 115 116 return 0; 117 } 118 119 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) 120 { 121 struct ena_com_admin_sq *sq = &queue->sq; 122 u16 size = ADMIN_SQ_SIZE(queue->q_depth); 123 124 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr, 125 sq->mem_handle); 126 127 if (!sq->entries) { 128 ena_trc_err("memory allocation failed"); 129 return ENA_COM_NO_MEM; 130 } 131 132 sq->head = 0; 133 sq->tail = 0; 134 sq->phase = 1; 135 136 sq->db_addr = NULL; 137 138 return 0; 139 } 140 141 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) 142 { 143 struct ena_com_admin_cq *cq = &queue->cq; 144 u16 size = ADMIN_CQ_SIZE(queue->q_depth); 145 146 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr, 147 cq->mem_handle); 148 149 if (!cq->entries) { 150 ena_trc_err("memory allocation failed"); 151 return ENA_COM_NO_MEM; 152 } 153 154 cq->head = 0; 155 cq->phase = 1; 156 157 return 0; 158 } 159 160 static int ena_com_admin_init_aenq(struct ena_com_dev *dev, 161 struct ena_aenq_handlers *aenq_handlers) 162 { 163 struct ena_com_aenq *aenq = &dev->aenq; 164 u32 addr_low, addr_high, aenq_caps; 165 u16 size; 166 167 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; 168 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); 169 ENA_MEM_ALLOC_COHERENT(dev->dmadev, size, 170 aenq->entries, 171 aenq->dma_addr, 172 aenq->mem_handle); 173 174 if (!aenq->entries) { 175 ena_trc_err("memory allocation failed"); 176 return ENA_COM_NO_MEM; 177 } 178 179 aenq->head = aenq->q_depth; 180 aenq->phase = 1; 181 182 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); 183 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); 184 185 ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); 186 ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); 187 188 aenq_caps = 0; 189 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; 190 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) << 191 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & 192 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; 193 ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); 194 195 if (unlikely(!aenq_handlers)) { 196 ena_trc_err("aenq handlers pointer is NULL\n"); 197 return ENA_COM_INVAL; 198 } 199 200 aenq->aenq_handlers = aenq_handlers; 201 202 return 0; 203 } 204 205 static inline void comp_ctxt_release(struct ena_com_admin_queue *queue, 206 struct ena_comp_ctx *comp_ctx) 207 { 208 comp_ctx->occupied = false; 209 ATOMIC32_DEC(&queue->outstanding_cmds); 210 } 211 212 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue, 213 u16 command_id, bool capture) 214 { 215 if (unlikely(command_id >= queue->q_depth)) { 216 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", 217 command_id, queue->q_depth); 218 return NULL; 219 } 220 221 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) { 222 ena_trc_err("Completion context is occupied\n"); 223 return NULL; 224 } 225 226 if (capture) { 227 ATOMIC32_INC(&queue->outstanding_cmds); 228 queue->comp_ctx[command_id].occupied = true; 229 } 230 231 return &queue->comp_ctx[command_id]; 232 } 233 234 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 235 struct ena_admin_aq_entry *cmd, 236 size_t cmd_size_in_bytes, 237 struct ena_admin_acq_entry *comp, 238 size_t comp_size_in_bytes) 239 { 240 struct ena_comp_ctx *comp_ctx; 241 u16 tail_masked, cmd_id; 242 u16 queue_size_mask; 243 u16 cnt; 244 245 queue_size_mask = admin_queue->q_depth - 1; 246 247 tail_masked = admin_queue->sq.tail & queue_size_mask; 248 249 /* In case of queue FULL */ 250 cnt = ATOMIC32_READ(&admin_queue->outstanding_cmds); 251 if (cnt >= admin_queue->q_depth) { 252 ena_trc_dbg("admin queue is full.\n"); 253 admin_queue->stats.out_of_space++; 254 return ERR_PTR(ENA_COM_NO_SPACE); 255 } 256 257 cmd_id = admin_queue->curr_cmd_id; 258 259 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase & 260 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 261 262 cmd->aq_common_descriptor.command_id |= cmd_id & 263 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 264 265 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true); 266 if (unlikely(!comp_ctx)) 267 return ERR_PTR(ENA_COM_INVAL); 268 269 comp_ctx->status = ENA_CMD_SUBMITTED; 270 comp_ctx->comp_size = (u32)comp_size_in_bytes; 271 comp_ctx->user_cqe = comp; 272 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 273 274 ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event); 275 276 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes); 277 278 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) & 279 queue_size_mask; 280 281 admin_queue->sq.tail++; 282 admin_queue->stats.submitted_cmd++; 283 284 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0)) 285 admin_queue->sq.phase = !admin_queue->sq.phase; 286 287 ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail, 288 admin_queue->sq.db_addr); 289 290 return comp_ctx; 291 } 292 293 static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue) 294 { 295 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx); 296 struct ena_comp_ctx *comp_ctx; 297 u16 i; 298 299 queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size); 300 if (unlikely(!queue->comp_ctx)) { 301 ena_trc_err("memory allocation failed"); 302 return ENA_COM_NO_MEM; 303 } 304 305 for (i = 0; i < queue->q_depth; i++) { 306 comp_ctx = get_comp_ctxt(queue, i, false); 307 if (comp_ctx) 308 ENA_WAIT_EVENT_INIT(comp_ctx->wait_event); 309 } 310 311 return 0; 312 } 313 314 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 315 struct ena_admin_aq_entry *cmd, 316 size_t cmd_size_in_bytes, 317 struct ena_admin_acq_entry *comp, 318 size_t comp_size_in_bytes) 319 { 320 unsigned long flags = 0; 321 struct ena_comp_ctx *comp_ctx; 322 323 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 324 if (unlikely(!admin_queue->running_state)) { 325 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 326 return ERR_PTR(ENA_COM_NO_DEVICE); 327 } 328 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd, 329 cmd_size_in_bytes, 330 comp, 331 comp_size_in_bytes); 332 if (IS_ERR(comp_ctx)) 333 admin_queue->running_state = false; 334 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 335 336 return comp_ctx; 337 } 338 339 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, 340 struct ena_com_create_io_ctx *ctx, 341 struct ena_com_io_sq *io_sq) 342 { 343 size_t size; 344 int dev_node = 0; 345 346 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr)); 347 348 io_sq->desc_entry_size = 349 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 350 sizeof(struct ena_eth_io_tx_desc) : 351 sizeof(struct ena_eth_io_rx_desc); 352 353 size = io_sq->desc_entry_size * io_sq->q_depth; 354 355 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 356 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev, 357 size, 358 io_sq->desc_addr.virt_addr, 359 io_sq->desc_addr.phys_addr, 360 io_sq->desc_addr.mem_handle, 361 ctx->numa_node, 362 dev_node); 363 if (!io_sq->desc_addr.virt_addr) { 364 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 365 size, 366 io_sq->desc_addr.virt_addr, 367 io_sq->desc_addr.phys_addr, 368 io_sq->desc_addr.mem_handle); 369 } 370 } else { 371 ENA_MEM_ALLOC_NODE(ena_dev->dmadev, 372 size, 373 io_sq->desc_addr.virt_addr, 374 ctx->numa_node, 375 dev_node); 376 if (!io_sq->desc_addr.virt_addr) { 377 io_sq->desc_addr.virt_addr = 378 ENA_MEM_ALLOC(ena_dev->dmadev, size); 379 } 380 } 381 382 if (!io_sq->desc_addr.virt_addr) { 383 ena_trc_err("memory allocation failed"); 384 return ENA_COM_NO_MEM; 385 } 386 387 io_sq->tail = 0; 388 io_sq->next_to_comp = 0; 389 io_sq->phase = 1; 390 391 return 0; 392 } 393 394 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, 395 struct ena_com_create_io_ctx *ctx, 396 struct ena_com_io_cq *io_cq) 397 { 398 size_t size; 399 int prev_node = 0; 400 401 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr)); 402 403 /* Use the basic completion descriptor for Rx */ 404 io_cq->cdesc_entry_size_in_bytes = 405 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 406 sizeof(struct ena_eth_io_tx_cdesc) : 407 sizeof(struct ena_eth_io_rx_cdesc_base); 408 409 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 410 411 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev, 412 size, 413 io_cq->cdesc_addr.virt_addr, 414 io_cq->cdesc_addr.phys_addr, 415 io_cq->cdesc_addr.mem_handle, 416 ctx->numa_node, 417 prev_node); 418 if (!io_cq->cdesc_addr.virt_addr) { 419 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 420 size, 421 io_cq->cdesc_addr.virt_addr, 422 io_cq->cdesc_addr.phys_addr, 423 io_cq->cdesc_addr.mem_handle); 424 } 425 426 if (!io_cq->cdesc_addr.virt_addr) { 427 ena_trc_err("memory allocation failed"); 428 return ENA_COM_NO_MEM; 429 } 430 431 io_cq->phase = 1; 432 io_cq->head = 0; 433 434 return 0; 435 } 436 437 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue, 438 struct ena_admin_acq_entry *cqe) 439 { 440 struct ena_comp_ctx *comp_ctx; 441 u16 cmd_id; 442 443 cmd_id = cqe->acq_common_descriptor.command & 444 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 445 446 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); 447 if (unlikely(!comp_ctx)) { 448 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n"); 449 admin_queue->running_state = false; 450 return; 451 } 452 453 comp_ctx->status = ENA_CMD_COMPLETED; 454 comp_ctx->comp_status = cqe->acq_common_descriptor.status; 455 456 if (comp_ctx->user_cqe) 457 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size); 458 459 if (!admin_queue->polling) 460 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event); 461 } 462 463 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue) 464 { 465 struct ena_admin_acq_entry *cqe = NULL; 466 u16 comp_num = 0; 467 u16 head_masked; 468 u8 phase; 469 470 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1); 471 phase = admin_queue->cq.phase; 472 473 cqe = &admin_queue->cq.entries[head_masked]; 474 475 /* Go over all the completions */ 476 while ((cqe->acq_common_descriptor.flags & 477 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 478 /* Do not read the rest of the completion entry before the 479 * phase bit was validated 480 */ 481 rmb(); 482 ena_com_handle_single_admin_completion(admin_queue, cqe); 483 484 head_masked++; 485 comp_num++; 486 if (unlikely(head_masked == admin_queue->q_depth)) { 487 head_masked = 0; 488 phase = !phase; 489 } 490 491 cqe = &admin_queue->cq.entries[head_masked]; 492 } 493 494 admin_queue->cq.head += comp_num; 495 admin_queue->cq.phase = phase; 496 admin_queue->sq.head += comp_num; 497 admin_queue->stats.completed_cmd += comp_num; 498 } 499 500 static int ena_com_comp_status_to_errno(u8 comp_status) 501 { 502 if (unlikely(comp_status != 0)) 503 ena_trc_err("admin command failed[%u]\n", comp_status); 504 505 if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR)) 506 return ENA_COM_INVAL; 507 508 switch (comp_status) { 509 case ENA_ADMIN_SUCCESS: 510 return 0; 511 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 512 return ENA_COM_NO_MEM; 513 case ENA_ADMIN_UNSUPPORTED_OPCODE: 514 return ENA_COM_UNSUPPORTED; 515 case ENA_ADMIN_BAD_OPCODE: 516 case ENA_ADMIN_MALFORMED_REQUEST: 517 case ENA_ADMIN_ILLEGAL_PARAMETER: 518 case ENA_ADMIN_UNKNOWN_ERROR: 519 return ENA_COM_INVAL; 520 } 521 522 return 0; 523 } 524 525 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx, 526 struct ena_com_admin_queue *admin_queue) 527 { 528 unsigned long flags = 0; 529 uint64_t timeout; 530 int ret; 531 532 timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout); 533 534 while (1) { 535 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 536 ena_com_handle_admin_completion(admin_queue); 537 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 538 539 if (comp_ctx->status != ENA_CMD_SUBMITTED) 540 break; 541 542 if (ENA_TIME_EXPIRE(timeout)) { 543 ena_trc_err("Wait for completion (polling) timeout\n"); 544 /* ENA didn't have any completion */ 545 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 546 admin_queue->stats.no_completion++; 547 admin_queue->running_state = false; 548 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 549 550 ret = ENA_COM_TIMER_EXPIRED; 551 goto err; 552 } 553 554 ENA_MSLEEP(ENA_POLL_MS); 555 } 556 557 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { 558 ena_trc_err("Command was aborted\n"); 559 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 560 admin_queue->stats.aborted_cmd++; 561 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 562 ret = ENA_COM_NO_DEVICE; 563 goto err; 564 } 565 566 ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED, 567 "Invalid comp status %d\n", comp_ctx->status); 568 569 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 570 err: 571 comp_ctxt_release(admin_queue, comp_ctx); 572 return ret; 573 } 574 575 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx, 576 struct ena_com_admin_queue *admin_queue) 577 { 578 unsigned long flags = 0; 579 int ret; 580 581 ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event, 582 admin_queue->completion_timeout); 583 584 /* In case the command wasn't completed find out the root cause. 585 * There might be 2 kinds of errors 586 * 1) No completion (timeout reached) 587 * 2) There is completion but the device didn't get any msi-x interrupt. 588 */ 589 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) { 590 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 591 ena_com_handle_admin_completion(admin_queue); 592 admin_queue->stats.no_completion++; 593 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 594 595 if (comp_ctx->status == ENA_CMD_COMPLETED) 596 ena_trc_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n", 597 comp_ctx->cmd_opcode); 598 else 599 ena_trc_err("The ena device doesn't send any completion for the admin cmd %d status %d\n", 600 comp_ctx->cmd_opcode, comp_ctx->status); 601 602 admin_queue->running_state = false; 603 ret = ENA_COM_TIMER_EXPIRED; 604 goto err; 605 } 606 607 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 608 err: 609 comp_ctxt_release(admin_queue, comp_ctx); 610 return ret; 611 } 612 613 /* This method read the hardware device register through posting writes 614 * and waiting for response 615 * On timeout the function will return ENA_MMIO_READ_TIMEOUT 616 */ 617 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) 618 { 619 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 620 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp = 621 mmio_read->read_resp; 622 u32 mmio_read_reg, ret, i; 623 unsigned long flags = 0; 624 u32 timeout = mmio_read->reg_read_to; 625 626 ENA_MIGHT_SLEEP(); 627 628 if (timeout == 0) 629 timeout = ENA_REG_READ_TIMEOUT; 630 631 /* If readless is disabled, perform regular read */ 632 if (!mmio_read->readless_supported) 633 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset); 634 635 ENA_SPINLOCK_LOCK(mmio_read->lock, flags); 636 mmio_read->seq_num++; 637 638 read_resp->req_id = mmio_read->seq_num + 0xDEAD; 639 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) & 640 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK; 641 mmio_read_reg |= mmio_read->seq_num & 642 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK; 643 644 /* make sure read_resp->req_id get updated before the hw can write 645 * there 646 */ 647 wmb(); 648 649 ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); 650 651 for (i = 0; i < timeout; i++) { 652 if (read_resp->req_id == mmio_read->seq_num) 653 break; 654 655 ENA_UDELAY(1); 656 } 657 658 if (unlikely(i == timeout)) { 659 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", 660 mmio_read->seq_num, 661 offset, 662 read_resp->req_id, 663 read_resp->reg_off); 664 ret = ENA_MMIO_READ_TIMEOUT; 665 goto err; 666 } 667 668 if (read_resp->reg_off != offset) { 669 ena_trc_err("Read failure: wrong offset provided"); 670 ret = ENA_MMIO_READ_TIMEOUT; 671 } else { 672 ret = read_resp->reg_val; 673 } 674 err: 675 ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags); 676 677 return ret; 678 } 679 680 /* There are two types to wait for completion. 681 * Polling mode - wait until the completion is available. 682 * Async mode - wait on wait queue until the completion is ready 683 * (or the timeout expired). 684 * It is expected that the IRQ called ena_com_handle_admin_completion 685 * to mark the completions. 686 */ 687 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx, 688 struct ena_com_admin_queue *admin_queue) 689 { 690 if (admin_queue->polling) 691 return ena_com_wait_and_process_admin_cq_polling(comp_ctx, 692 admin_queue); 693 694 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx, 695 admin_queue); 696 } 697 698 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, 699 struct ena_com_io_sq *io_sq) 700 { 701 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 702 struct ena_admin_aq_destroy_sq_cmd destroy_cmd; 703 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp; 704 u8 direction; 705 int ret; 706 707 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 708 709 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 710 direction = ENA_ADMIN_SQ_DIRECTION_TX; 711 else 712 direction = ENA_ADMIN_SQ_DIRECTION_RX; 713 714 destroy_cmd.sq.sq_identity |= (direction << 715 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & 716 ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 717 718 destroy_cmd.sq.sq_idx = io_sq->idx; 719 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ; 720 721 ret = ena_com_execute_admin_command(admin_queue, 722 (struct ena_admin_aq_entry *)&destroy_cmd, 723 sizeof(destroy_cmd), 724 (struct ena_admin_acq_entry *)&destroy_resp, 725 sizeof(destroy_resp)); 726 727 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE))) 728 ena_trc_err("failed to destroy io sq error: %d\n", ret); 729 730 return ret; 731 } 732 733 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, 734 struct ena_com_io_sq *io_sq, 735 struct ena_com_io_cq *io_cq) 736 { 737 size_t size; 738 739 if (io_cq->cdesc_addr.virt_addr) { 740 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 741 742 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 743 size, 744 io_cq->cdesc_addr.virt_addr, 745 io_cq->cdesc_addr.phys_addr, 746 io_cq->cdesc_addr.mem_handle); 747 748 io_cq->cdesc_addr.virt_addr = NULL; 749 } 750 751 if (io_sq->desc_addr.virt_addr) { 752 size = io_sq->desc_entry_size * io_sq->q_depth; 753 754 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 755 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 756 size, 757 io_sq->desc_addr.virt_addr, 758 io_sq->desc_addr.phys_addr, 759 io_sq->desc_addr.mem_handle); 760 else 761 ENA_MEM_FREE(ena_dev->dmadev, io_sq->desc_addr.virt_addr); 762 763 io_sq->desc_addr.virt_addr = NULL; 764 } 765 } 766 767 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, 768 u16 exp_state) 769 { 770 u32 val, i; 771 772 /* Convert timeout from resolution of 100ms to ENA_POLL_MS */ 773 timeout = (timeout * 100) / ENA_POLL_MS; 774 775 for (i = 0; i < timeout; i++) { 776 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 777 778 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { 779 ena_trc_err("Reg read timeout occurred\n"); 780 return ENA_COM_TIMER_EXPIRED; 781 } 782 783 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == 784 exp_state) 785 return 0; 786 787 ENA_MSLEEP(ENA_POLL_MS); 788 } 789 790 return ENA_COM_TIMER_EXPIRED; 791 } 792 793 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, 794 enum ena_admin_aq_feature_id feature_id) 795 { 796 u32 feature_mask = 1 << feature_id; 797 798 /* Device attributes is always supported */ 799 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) && 800 !(ena_dev->supported_features & feature_mask)) 801 return false; 802 803 return true; 804 } 805 806 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, 807 struct ena_admin_get_feat_resp *get_resp, 808 enum ena_admin_aq_feature_id feature_id, 809 dma_addr_t control_buf_dma_addr, 810 u32 control_buff_size) 811 { 812 struct ena_com_admin_queue *admin_queue; 813 struct ena_admin_get_feat_cmd get_cmd; 814 int ret; 815 816 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { 817 ena_trc_dbg("Feature %d isn't supported\n", feature_id); 818 return ENA_COM_UNSUPPORTED; 819 } 820 821 memset(&get_cmd, 0x0, sizeof(get_cmd)); 822 admin_queue = &ena_dev->admin_queue; 823 824 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE; 825 826 if (control_buff_size) 827 get_cmd.aq_common_descriptor.flags = 828 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 829 else 830 get_cmd.aq_common_descriptor.flags = 0; 831 832 ret = ena_com_mem_addr_set(ena_dev, 833 &get_cmd.control_buffer.address, 834 control_buf_dma_addr); 835 if (unlikely(ret)) { 836 ena_trc_err("memory address set failed\n"); 837 return ret; 838 } 839 840 get_cmd.control_buffer.length = control_buff_size; 841 842 get_cmd.feat_common.feature_id = feature_id; 843 844 ret = ena_com_execute_admin_command(admin_queue, 845 (struct ena_admin_aq_entry *) 846 &get_cmd, 847 sizeof(get_cmd), 848 (struct ena_admin_acq_entry *) 849 get_resp, 850 sizeof(*get_resp)); 851 852 if (unlikely(ret)) 853 ena_trc_err("Failed to submit get_feature command %d error: %d\n", 854 feature_id, ret); 855 856 return ret; 857 } 858 859 static int ena_com_get_feature(struct ena_com_dev *ena_dev, 860 struct ena_admin_get_feat_resp *get_resp, 861 enum ena_admin_aq_feature_id feature_id) 862 { 863 return ena_com_get_feature_ex(ena_dev, 864 get_resp, 865 feature_id, 866 0, 867 0); 868 } 869 870 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) 871 { 872 struct ena_rss *rss = &ena_dev->rss; 873 874 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 875 sizeof(*rss->hash_key), 876 rss->hash_key, 877 rss->hash_key_dma_addr, 878 rss->hash_key_mem_handle); 879 880 if (unlikely(!rss->hash_key)) 881 return ENA_COM_NO_MEM; 882 883 return 0; 884 } 885 886 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) 887 { 888 struct ena_rss *rss = &ena_dev->rss; 889 890 if (rss->hash_key) 891 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 892 sizeof(*rss->hash_key), 893 rss->hash_key, 894 rss->hash_key_dma_addr, 895 rss->hash_key_mem_handle); 896 rss->hash_key = NULL; 897 } 898 899 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) 900 { 901 struct ena_rss *rss = &ena_dev->rss; 902 903 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 904 sizeof(*rss->hash_ctrl), 905 rss->hash_ctrl, 906 rss->hash_ctrl_dma_addr, 907 rss->hash_ctrl_mem_handle); 908 909 if (unlikely(!rss->hash_ctrl)) 910 return ENA_COM_NO_MEM; 911 912 return 0; 913 } 914 915 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) 916 { 917 struct ena_rss *rss = &ena_dev->rss; 918 919 if (rss->hash_ctrl) 920 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 921 sizeof(*rss->hash_ctrl), 922 rss->hash_ctrl, 923 rss->hash_ctrl_dma_addr, 924 rss->hash_ctrl_mem_handle); 925 rss->hash_ctrl = NULL; 926 } 927 928 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, 929 u16 log_size) 930 { 931 struct ena_rss *rss = &ena_dev->rss; 932 struct ena_admin_get_feat_resp get_resp; 933 size_t tbl_size; 934 int ret; 935 936 ret = ena_com_get_feature(ena_dev, &get_resp, 937 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 938 if (unlikely(ret)) 939 return ret; 940 941 if ((get_resp.u.ind_table.min_size > log_size) || 942 (get_resp.u.ind_table.max_size < log_size)) { 943 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 944 1 << log_size, 945 1 << get_resp.u.ind_table.min_size, 946 1 << get_resp.u.ind_table.max_size); 947 return ENA_COM_INVAL; 948 } 949 950 tbl_size = (1ULL << log_size) * 951 sizeof(struct ena_admin_rss_ind_table_entry); 952 953 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 954 tbl_size, 955 rss->rss_ind_tbl, 956 rss->rss_ind_tbl_dma_addr, 957 rss->rss_ind_tbl_mem_handle); 958 if (unlikely(!rss->rss_ind_tbl)) 959 goto mem_err1; 960 961 tbl_size = (1ULL << log_size) * sizeof(u16); 962 rss->host_rss_ind_tbl = 963 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size); 964 if (unlikely(!rss->host_rss_ind_tbl)) 965 goto mem_err2; 966 967 rss->tbl_log_size = log_size; 968 969 return 0; 970 971 mem_err2: 972 tbl_size = (1ULL << log_size) * 973 sizeof(struct ena_admin_rss_ind_table_entry); 974 975 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 976 tbl_size, 977 rss->rss_ind_tbl, 978 rss->rss_ind_tbl_dma_addr, 979 rss->rss_ind_tbl_mem_handle); 980 rss->rss_ind_tbl = NULL; 981 mem_err1: 982 rss->tbl_log_size = 0; 983 return ENA_COM_NO_MEM; 984 } 985 986 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) 987 { 988 struct ena_rss *rss = &ena_dev->rss; 989 size_t tbl_size = (1ULL << rss->tbl_log_size) * 990 sizeof(struct ena_admin_rss_ind_table_entry); 991 992 if (rss->rss_ind_tbl) 993 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 994 tbl_size, 995 rss->rss_ind_tbl, 996 rss->rss_ind_tbl_dma_addr, 997 rss->rss_ind_tbl_mem_handle); 998 rss->rss_ind_tbl = NULL; 999 1000 if (rss->host_rss_ind_tbl) 1001 ENA_MEM_FREE(ena_dev->dmadev, rss->host_rss_ind_tbl); 1002 rss->host_rss_ind_tbl = NULL; 1003 } 1004 1005 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, 1006 struct ena_com_io_sq *io_sq, u16 cq_idx) 1007 { 1008 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1009 struct ena_admin_aq_create_sq_cmd create_cmd; 1010 struct ena_admin_acq_create_sq_resp_desc cmd_completion; 1011 u8 direction; 1012 int ret; 1013 1014 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1015 1016 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ; 1017 1018 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1019 direction = ENA_ADMIN_SQ_DIRECTION_TX; 1020 else 1021 direction = ENA_ADMIN_SQ_DIRECTION_RX; 1022 1023 create_cmd.sq_identity |= (direction << 1024 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & 1025 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 1026 1027 create_cmd.sq_caps_2 |= io_sq->mem_queue_type & 1028 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1029 1030 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC << 1031 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & 1032 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 1033 1034 create_cmd.sq_caps_3 |= 1035 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1036 1037 create_cmd.cq_idx = cq_idx; 1038 create_cmd.sq_depth = io_sq->q_depth; 1039 1040 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 1041 ret = ena_com_mem_addr_set(ena_dev, 1042 &create_cmd.sq_ba, 1043 io_sq->desc_addr.phys_addr); 1044 if (unlikely(ret)) { 1045 ena_trc_err("memory address set failed\n"); 1046 return ret; 1047 } 1048 } 1049 1050 ret = ena_com_execute_admin_command(admin_queue, 1051 (struct ena_admin_aq_entry *)&create_cmd, 1052 sizeof(create_cmd), 1053 (struct ena_admin_acq_entry *)&cmd_completion, 1054 sizeof(cmd_completion)); 1055 if (unlikely(ret)) { 1056 ena_trc_err("Failed to create IO SQ. error: %d\n", ret); 1057 return ret; 1058 } 1059 1060 io_sq->idx = cmd_completion.sq_idx; 1061 1062 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1063 (uintptr_t)cmd_completion.sq_doorbell_offset); 1064 1065 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1066 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar 1067 + cmd_completion.llq_headers_offset); 1068 1069 io_sq->desc_addr.pbuf_dev_addr = 1070 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + 1071 cmd_completion.llq_descriptors_offset); 1072 } 1073 1074 ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); 1075 1076 return ret; 1077 } 1078 1079 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) 1080 { 1081 struct ena_rss *rss = &ena_dev->rss; 1082 struct ena_com_io_sq *io_sq; 1083 u16 qid; 1084 int i; 1085 1086 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1087 qid = rss->host_rss_ind_tbl[i]; 1088 if (qid >= ENA_TOTAL_NUM_QUEUES) 1089 return ENA_COM_INVAL; 1090 1091 io_sq = &ena_dev->io_sq_queues[qid]; 1092 1093 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX) 1094 return ENA_COM_INVAL; 1095 1096 rss->rss_ind_tbl[i].cq_idx = io_sq->idx; 1097 } 1098 1099 return 0; 1100 } 1101 1102 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev) 1103 { 1104 u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 }; 1105 struct ena_rss *rss = &ena_dev->rss; 1106 u8 idx; 1107 u16 i; 1108 1109 for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++) 1110 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i; 1111 1112 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1113 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES) 1114 return ENA_COM_INVAL; 1115 idx = (u8)rss->rss_ind_tbl[i].cq_idx; 1116 1117 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES) 1118 return ENA_COM_INVAL; 1119 1120 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx]; 1121 } 1122 1123 return 0; 1124 } 1125 1126 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev) 1127 { 1128 size_t size; 1129 1130 size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS; 1131 1132 ena_dev->intr_moder_tbl = ENA_MEM_ALLOC(ena_dev->dmadev, size); 1133 if (!ena_dev->intr_moder_tbl) 1134 return ENA_COM_NO_MEM; 1135 1136 ena_com_config_default_interrupt_moderation_table(ena_dev); 1137 1138 return 0; 1139 } 1140 1141 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, 1142 u16 intr_delay_resolution) 1143 { 1144 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 1145 unsigned int i; 1146 1147 if (!intr_delay_resolution) { 1148 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); 1149 intr_delay_resolution = 1; 1150 } 1151 ena_dev->intr_delay_resolution = intr_delay_resolution; 1152 1153 /* update Rx */ 1154 for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++) 1155 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution; 1156 1157 /* update Tx */ 1158 ena_dev->intr_moder_tx_interval /= intr_delay_resolution; 1159 } 1160 1161 /*****************************************************************************/ 1162 /******************************* API ******************************/ 1163 /*****************************************************************************/ 1164 1165 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 1166 struct ena_admin_aq_entry *cmd, 1167 size_t cmd_size, 1168 struct ena_admin_acq_entry *comp, 1169 size_t comp_size) 1170 { 1171 struct ena_comp_ctx *comp_ctx; 1172 int ret; 1173 1174 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size, 1175 comp, comp_size); 1176 if (IS_ERR(comp_ctx)) { 1177 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE)) 1178 ena_trc_dbg("Failed to submit command [%ld]\n", 1179 PTR_ERR(comp_ctx)); 1180 else 1181 ena_trc_err("Failed to submit command [%ld]\n", 1182 PTR_ERR(comp_ctx)); 1183 1184 return PTR_ERR(comp_ctx); 1185 } 1186 1187 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); 1188 if (unlikely(ret)) { 1189 if (admin_queue->running_state) 1190 ena_trc_err("Failed to process command. ret = %d\n", 1191 ret); 1192 else 1193 ena_trc_dbg("Failed to process command. ret = %d\n", 1194 ret); 1195 } 1196 return ret; 1197 } 1198 1199 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 1200 struct ena_com_io_cq *io_cq) 1201 { 1202 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1203 struct ena_admin_aq_create_cq_cmd create_cmd; 1204 struct ena_admin_acq_create_cq_resp_desc cmd_completion; 1205 int ret; 1206 1207 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1208 1209 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ; 1210 1211 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) & 1212 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1213 create_cmd.cq_caps_1 |= 1214 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1215 1216 create_cmd.msix_vector = io_cq->msix_vector; 1217 create_cmd.cq_depth = io_cq->q_depth; 1218 1219 ret = ena_com_mem_addr_set(ena_dev, 1220 &create_cmd.cq_ba, 1221 io_cq->cdesc_addr.phys_addr); 1222 if (unlikely(ret)) { 1223 ena_trc_err("memory address set failed\n"); 1224 return ret; 1225 } 1226 1227 ret = ena_com_execute_admin_command(admin_queue, 1228 (struct ena_admin_aq_entry *)&create_cmd, 1229 sizeof(create_cmd), 1230 (struct ena_admin_acq_entry *)&cmd_completion, 1231 sizeof(cmd_completion)); 1232 if (unlikely(ret)) { 1233 ena_trc_err("Failed to create IO CQ. error: %d\n", ret); 1234 return ret; 1235 } 1236 1237 io_cq->idx = cmd_completion.cq_idx; 1238 1239 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1240 cmd_completion.cq_interrupt_unmask_register_offset); 1241 1242 if (cmd_completion.cq_head_db_register_offset) 1243 io_cq->cq_head_db_reg = 1244 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1245 cmd_completion.cq_head_db_register_offset); 1246 1247 if (cmd_completion.numa_node_register_offset) 1248 io_cq->numa_node_cfg_reg = 1249 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1250 cmd_completion.numa_node_register_offset); 1251 1252 ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); 1253 1254 return ret; 1255 } 1256 1257 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 1258 struct ena_com_io_sq **io_sq, 1259 struct ena_com_io_cq **io_cq) 1260 { 1261 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1262 ena_trc_err("Invalid queue number %d but the max is %d\n", 1263 qid, ENA_TOTAL_NUM_QUEUES); 1264 return ENA_COM_INVAL; 1265 } 1266 1267 *io_sq = &ena_dev->io_sq_queues[qid]; 1268 *io_cq = &ena_dev->io_cq_queues[qid]; 1269 1270 return 0; 1271 } 1272 1273 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) 1274 { 1275 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1276 struct ena_comp_ctx *comp_ctx; 1277 u16 i; 1278 1279 if (!admin_queue->comp_ctx) 1280 return; 1281 1282 for (i = 0; i < admin_queue->q_depth; i++) { 1283 comp_ctx = get_comp_ctxt(admin_queue, i, false); 1284 if (unlikely(!comp_ctx)) 1285 break; 1286 1287 comp_ctx->status = ENA_CMD_ABORTED; 1288 1289 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event); 1290 } 1291 } 1292 1293 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) 1294 { 1295 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1296 unsigned long flags = 0; 1297 1298 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 1299 while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) { 1300 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 1301 ENA_MSLEEP(ENA_POLL_MS); 1302 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 1303 } 1304 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 1305 } 1306 1307 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 1308 struct ena_com_io_cq *io_cq) 1309 { 1310 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1311 struct ena_admin_aq_destroy_cq_cmd destroy_cmd; 1312 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp; 1313 int ret; 1314 1315 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 1316 1317 destroy_cmd.cq_idx = io_cq->idx; 1318 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ; 1319 1320 ret = ena_com_execute_admin_command(admin_queue, 1321 (struct ena_admin_aq_entry *)&destroy_cmd, 1322 sizeof(destroy_cmd), 1323 (struct ena_admin_acq_entry *)&destroy_resp, 1324 sizeof(destroy_resp)); 1325 1326 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE))) 1327 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret); 1328 1329 return ret; 1330 } 1331 1332 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) 1333 { 1334 return ena_dev->admin_queue.running_state; 1335 } 1336 1337 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) 1338 { 1339 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1340 unsigned long flags = 0; 1341 1342 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 1343 ena_dev->admin_queue.running_state = state; 1344 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 1345 } 1346 1347 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) 1348 { 1349 u16 depth = ena_dev->aenq.q_depth; 1350 1351 ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); 1352 1353 /* Init head_db to mark that all entries in the queue 1354 * are initially available 1355 */ 1356 ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1357 } 1358 1359 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) 1360 { 1361 struct ena_com_admin_queue *admin_queue; 1362 struct ena_admin_set_feat_cmd cmd; 1363 struct ena_admin_set_feat_resp resp; 1364 struct ena_admin_get_feat_resp get_resp; 1365 int ret; 1366 1367 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG); 1368 if (ret) { 1369 ena_trc_info("Can't get aenq configuration\n"); 1370 return ret; 1371 } 1372 1373 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { 1374 ena_trc_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n", 1375 get_resp.u.aenq.supported_groups, 1376 groups_flag); 1377 return ENA_COM_UNSUPPORTED; 1378 } 1379 1380 memset(&cmd, 0x0, sizeof(cmd)); 1381 admin_queue = &ena_dev->admin_queue; 1382 1383 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1384 cmd.aq_common_descriptor.flags = 0; 1385 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG; 1386 cmd.u.aenq.enabled_groups = groups_flag; 1387 1388 ret = ena_com_execute_admin_command(admin_queue, 1389 (struct ena_admin_aq_entry *)&cmd, 1390 sizeof(cmd), 1391 (struct ena_admin_acq_entry *)&resp, 1392 sizeof(resp)); 1393 1394 if (unlikely(ret)) 1395 ena_trc_err("Failed to config AENQ ret: %d\n", ret); 1396 1397 return ret; 1398 } 1399 1400 int ena_com_get_dma_width(struct ena_com_dev *ena_dev) 1401 { 1402 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1403 int width; 1404 1405 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { 1406 ena_trc_err("Reg read timeout occurred\n"); 1407 return ENA_COM_TIMER_EXPIRED; 1408 } 1409 1410 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> 1411 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; 1412 1413 ena_trc_dbg("ENA dma width: %d\n", width); 1414 1415 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { 1416 ena_trc_err("DMA width illegal value: %d\n", width); 1417 return ENA_COM_INVAL; 1418 } 1419 1420 ena_dev->dma_addr_bits = width; 1421 1422 return width; 1423 } 1424 1425 int ena_com_validate_version(struct ena_com_dev *ena_dev) 1426 { 1427 u32 ver; 1428 u32 ctrl_ver; 1429 u32 ctrl_ver_masked; 1430 1431 /* Make sure the ENA version and the controller version are at least 1432 * as the driver expects 1433 */ 1434 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); 1435 ctrl_ver = ena_com_reg_bar_read32(ena_dev, 1436 ENA_REGS_CONTROLLER_VERSION_OFF); 1437 1438 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || 1439 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { 1440 ena_trc_err("Reg read timeout occurred\n"); 1441 return ENA_COM_TIMER_EXPIRED; 1442 } 1443 1444 ena_trc_info("ena device version: %d.%d\n", 1445 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> 1446 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, 1447 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); 1448 1449 if (ver < MIN_ENA_VER) { 1450 ena_trc_err("ENA version is lower than the minimal version the driver supports\n"); 1451 return -1; 1452 } 1453 1454 ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n", 1455 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) 1456 >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, 1457 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) 1458 >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT, 1459 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK), 1460 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >> 1461 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT); 1462 1463 ctrl_ver_masked = 1464 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) | 1465 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) | 1466 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK); 1467 1468 /* Validate the ctrl version without the implementation ID */ 1469 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { 1470 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1471 return -1; 1472 } 1473 1474 return 0; 1475 } 1476 1477 void ena_com_admin_destroy(struct ena_com_dev *ena_dev) 1478 { 1479 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1480 struct ena_com_admin_cq *cq = &admin_queue->cq; 1481 struct ena_com_admin_sq *sq = &admin_queue->sq; 1482 struct ena_com_aenq *aenq = &ena_dev->aenq; 1483 u16 size; 1484 1485 ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event); 1486 if (admin_queue->comp_ctx) 1487 ENA_MEM_FREE(ena_dev->dmadev, admin_queue->comp_ctx); 1488 admin_queue->comp_ctx = NULL; 1489 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 1490 if (sq->entries) 1491 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries, 1492 sq->dma_addr, sq->mem_handle); 1493 sq->entries = NULL; 1494 1495 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 1496 if (cq->entries) 1497 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries, 1498 cq->dma_addr, cq->mem_handle); 1499 cq->entries = NULL; 1500 1501 size = ADMIN_AENQ_SIZE(aenq->q_depth); 1502 if (ena_dev->aenq.entries) 1503 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries, 1504 aenq->dma_addr, aenq->mem_handle); 1505 aenq->entries = NULL; 1506 } 1507 1508 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) 1509 { 1510 u32 mask_value = 0; 1511 1512 if (polling) 1513 mask_value = ENA_REGS_ADMIN_INTR_MASK; 1514 1515 ENA_REG_WRITE32(ena_dev->bus, mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); 1516 ena_dev->admin_queue.polling = polling; 1517 } 1518 1519 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) 1520 { 1521 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1522 1523 ENA_SPINLOCK_INIT(mmio_read->lock); 1524 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 1525 sizeof(*mmio_read->read_resp), 1526 mmio_read->read_resp, 1527 mmio_read->read_resp_dma_addr, 1528 mmio_read->read_resp_mem_handle); 1529 if (unlikely(!mmio_read->read_resp)) 1530 return ENA_COM_NO_MEM; 1531 1532 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1533 1534 mmio_read->read_resp->req_id = 0x0; 1535 mmio_read->seq_num = 0x0; 1536 mmio_read->readless_supported = true; 1537 1538 return 0; 1539 } 1540 1541 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) 1542 { 1543 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1544 1545 mmio_read->readless_supported = readless_supported; 1546 } 1547 1548 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) 1549 { 1550 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1551 1552 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1553 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1554 1555 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 1556 sizeof(*mmio_read->read_resp), 1557 mmio_read->read_resp, 1558 mmio_read->read_resp_dma_addr, 1559 mmio_read->read_resp_mem_handle); 1560 1561 mmio_read->read_resp = NULL; 1562 } 1563 1564 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) 1565 { 1566 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1567 u32 addr_low, addr_high; 1568 1569 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr); 1570 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr); 1571 1572 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1573 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1574 } 1575 1576 int ena_com_admin_init(struct ena_com_dev *ena_dev, 1577 struct ena_aenq_handlers *aenq_handlers, 1578 bool init_spinlock) 1579 { 1580 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1581 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high; 1582 int ret; 1583 1584 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1585 1586 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { 1587 ena_trc_err("Reg read timeout occurred\n"); 1588 return ENA_COM_TIMER_EXPIRED; 1589 } 1590 1591 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { 1592 ena_trc_err("Device isn't ready, abort com init\n"); 1593 return ENA_COM_NO_DEVICE; 1594 } 1595 1596 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH; 1597 1598 admin_queue->q_dmadev = ena_dev->dmadev; 1599 admin_queue->polling = false; 1600 admin_queue->curr_cmd_id = 0; 1601 1602 ATOMIC32_SET(&admin_queue->outstanding_cmds, 0); 1603 1604 if (init_spinlock) 1605 ENA_SPINLOCK_INIT(admin_queue->q_lock); 1606 1607 ret = ena_com_init_comp_ctxt(admin_queue); 1608 if (ret) 1609 goto error; 1610 1611 ret = ena_com_admin_init_sq(admin_queue); 1612 if (ret) 1613 goto error; 1614 1615 ret = ena_com_admin_init_cq(admin_queue); 1616 if (ret) 1617 goto error; 1618 1619 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1620 ENA_REGS_AQ_DB_OFF); 1621 1622 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr); 1623 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr); 1624 1625 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); 1626 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); 1627 1628 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr); 1629 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr); 1630 1631 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); 1632 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); 1633 1634 aq_caps = 0; 1635 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK; 1636 aq_caps |= (sizeof(struct ena_admin_aq_entry) << 1637 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) & 1638 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK; 1639 1640 acq_caps = 0; 1641 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK; 1642 acq_caps |= (sizeof(struct ena_admin_acq_entry) << 1643 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) & 1644 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK; 1645 1646 ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); 1647 ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); 1648 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); 1649 if (ret) 1650 goto error; 1651 1652 admin_queue->running_state = true; 1653 1654 return 0; 1655 error: 1656 ena_com_admin_destroy(ena_dev); 1657 1658 return ret; 1659 } 1660 1661 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 1662 struct ena_com_create_io_ctx *ctx) 1663 { 1664 struct ena_com_io_sq *io_sq; 1665 struct ena_com_io_cq *io_cq; 1666 int ret; 1667 1668 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { 1669 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n", 1670 ctx->qid, ENA_TOTAL_NUM_QUEUES); 1671 return ENA_COM_INVAL; 1672 } 1673 1674 io_sq = &ena_dev->io_sq_queues[ctx->qid]; 1675 io_cq = &ena_dev->io_cq_queues[ctx->qid]; 1676 1677 memset(io_sq, 0x0, sizeof(*io_sq)); 1678 memset(io_cq, 0x0, sizeof(*io_cq)); 1679 1680 /* Init CQ */ 1681 io_cq->q_depth = ctx->queue_size; 1682 io_cq->direction = ctx->direction; 1683 io_cq->qid = ctx->qid; 1684 1685 io_cq->msix_vector = ctx->msix_vector; 1686 1687 io_sq->q_depth = ctx->queue_size; 1688 io_sq->direction = ctx->direction; 1689 io_sq->qid = ctx->qid; 1690 1691 io_sq->mem_queue_type = ctx->mem_queue_type; 1692 1693 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1694 /* header length is limited to 8 bits */ 1695 io_sq->tx_max_header_size = 1696 ENA_MIN32(ena_dev->tx_max_header_size, SZ_256); 1697 1698 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); 1699 if (ret) 1700 goto error; 1701 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); 1702 if (ret) 1703 goto error; 1704 1705 ret = ena_com_create_io_cq(ena_dev, io_cq); 1706 if (ret) 1707 goto error; 1708 1709 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); 1710 if (ret) 1711 goto destroy_io_cq; 1712 1713 return 0; 1714 1715 destroy_io_cq: 1716 ena_com_destroy_io_cq(ena_dev, io_cq); 1717 error: 1718 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1719 return ret; 1720 } 1721 1722 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) 1723 { 1724 struct ena_com_io_sq *io_sq; 1725 struct ena_com_io_cq *io_cq; 1726 1727 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1728 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n", 1729 qid, ENA_TOTAL_NUM_QUEUES); 1730 return; 1731 } 1732 1733 io_sq = &ena_dev->io_sq_queues[qid]; 1734 io_cq = &ena_dev->io_cq_queues[qid]; 1735 1736 ena_com_destroy_io_sq(ena_dev, io_sq); 1737 ena_com_destroy_io_cq(ena_dev, io_cq); 1738 1739 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1740 } 1741 1742 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 1743 struct ena_admin_get_feat_resp *resp) 1744 { 1745 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG); 1746 } 1747 1748 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 1749 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1750 { 1751 struct ena_admin_get_feat_resp get_resp; 1752 int rc; 1753 1754 rc = ena_com_get_feature(ena_dev, &get_resp, 1755 ENA_ADMIN_DEVICE_ATTRIBUTES); 1756 if (rc) 1757 return rc; 1758 1759 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, 1760 sizeof(get_resp.u.dev_attr)); 1761 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; 1762 1763 rc = ena_com_get_feature(ena_dev, &get_resp, 1764 ENA_ADMIN_MAX_QUEUES_NUM); 1765 if (rc) 1766 return rc; 1767 1768 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue, 1769 sizeof(get_resp.u.max_queue)); 1770 ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size; 1771 1772 rc = ena_com_get_feature(ena_dev, &get_resp, 1773 ENA_ADMIN_AENQ_CONFIG); 1774 if (rc) 1775 return rc; 1776 1777 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq, 1778 sizeof(get_resp.u.aenq)); 1779 1780 rc = ena_com_get_feature(ena_dev, &get_resp, 1781 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG); 1782 if (rc) 1783 return rc; 1784 1785 memcpy(&get_feat_ctx->offload, &get_resp.u.offload, 1786 sizeof(get_resp.u.offload)); 1787 1788 /* Driver hints isn't mandatory admin command. So in case the 1789 * command isn't supported set driver hints to 0 1790 */ 1791 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS); 1792 1793 if (!rc) 1794 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, 1795 sizeof(get_resp.u.hw_hints)); 1796 else if (rc == ENA_COM_UNSUPPORTED) 1797 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints)); 1798 else 1799 return rc; 1800 1801 return 0; 1802 } 1803 1804 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) 1805 { 1806 ena_com_handle_admin_completion(&ena_dev->admin_queue); 1807 } 1808 1809 /* ena_handle_specific_aenq_event: 1810 * return the handler that is relevant to the specific event group 1811 */ 1812 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, 1813 u16 group) 1814 { 1815 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers; 1816 1817 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) 1818 return aenq_handlers->handlers[group]; 1819 1820 return aenq_handlers->unimplemented_handler; 1821 } 1822 1823 /* ena_aenq_intr_handler: 1824 * handles the aenq incoming events. 1825 * pop events from the queue and apply the specific handler 1826 */ 1827 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) 1828 { 1829 struct ena_admin_aenq_entry *aenq_e; 1830 struct ena_admin_aenq_common_desc *aenq_common; 1831 struct ena_com_aenq *aenq = &dev->aenq; 1832 ena_aenq_handler handler_cb; 1833 unsigned long long timestamp; 1834 u16 masked_head, processed = 0; 1835 u8 phase; 1836 1837 masked_head = aenq->head & (aenq->q_depth - 1); 1838 phase = aenq->phase; 1839 aenq_e = &aenq->entries[masked_head]; /* Get first entry */ 1840 aenq_common = &aenq_e->aenq_common_desc; 1841 1842 /* Go over all the events */ 1843 while ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == 1844 phase) { 1845 timestamp = (unsigned long long)aenq_common->timestamp_low | 1846 ((unsigned long long)aenq_common->timestamp_high << 32); 1847 ENA_TOUCH(timestamp); /* In case debug is disabled */ 1848 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n", 1849 aenq_common->group, 1850 aenq_common->syndrom, 1851 timestamp); 1852 1853 /* Handle specific event*/ 1854 handler_cb = ena_com_get_specific_aenq_cb(dev, 1855 aenq_common->group); 1856 handler_cb(data, aenq_e); /* call the actual event handler*/ 1857 1858 /* Get next event entry */ 1859 masked_head++; 1860 processed++; 1861 1862 if (unlikely(masked_head == aenq->q_depth)) { 1863 masked_head = 0; 1864 phase = !phase; 1865 } 1866 aenq_e = &aenq->entries[masked_head]; 1867 aenq_common = &aenq_e->aenq_common_desc; 1868 } 1869 1870 aenq->head += processed; 1871 aenq->phase = phase; 1872 1873 /* Don't update aenq doorbell if there weren't any processed events */ 1874 if (!processed) 1875 return; 1876 1877 /* write the aenq doorbell after all AENQ descriptors were read */ 1878 mb(); 1879 ENA_REG_WRITE32(dev->bus, (u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1880 } 1881 1882 int ena_com_dev_reset(struct ena_com_dev *ena_dev, 1883 enum ena_regs_reset_reason_types reset_reason) 1884 { 1885 u32 stat, timeout, cap, reset_val; 1886 int rc; 1887 1888 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1889 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1890 1891 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || 1892 (cap == ENA_MMIO_READ_TIMEOUT))) { 1893 ena_trc_err("Reg read32 timeout occurred\n"); 1894 return ENA_COM_TIMER_EXPIRED; 1895 } 1896 1897 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { 1898 ena_trc_err("Device isn't ready, can't reset device\n"); 1899 return ENA_COM_INVAL; 1900 } 1901 1902 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> 1903 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; 1904 if (timeout == 0) { 1905 ena_trc_err("Invalid timeout value\n"); 1906 return ENA_COM_INVAL; 1907 } 1908 1909 /* start reset */ 1910 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; 1911 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & 1912 ENA_REGS_DEV_CTL_RESET_REASON_MASK; 1913 ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 1914 1915 /* Write again the MMIO read request address */ 1916 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1917 1918 rc = wait_for_reset_state(ena_dev, timeout, 1919 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); 1920 if (rc != 0) { 1921 ena_trc_err("Reset indication didn't turn on\n"); 1922 return rc; 1923 } 1924 1925 /* reset done */ 1926 ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 1927 rc = wait_for_reset_state(ena_dev, timeout, 0); 1928 if (rc != 0) { 1929 ena_trc_err("Reset indication didn't turn off\n"); 1930 return rc; 1931 } 1932 1933 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >> 1934 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT; 1935 if (timeout) 1936 /* the resolution of timeout reg is 100ms */ 1937 ena_dev->admin_queue.completion_timeout = timeout * 100000; 1938 else 1939 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US; 1940 1941 return 0; 1942 } 1943 1944 static int ena_get_dev_stats(struct ena_com_dev *ena_dev, 1945 struct ena_com_stats_ctx *ctx, 1946 enum ena_admin_get_stats_type type) 1947 { 1948 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd; 1949 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp; 1950 struct ena_com_admin_queue *admin_queue; 1951 int ret; 1952 1953 admin_queue = &ena_dev->admin_queue; 1954 1955 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS; 1956 get_cmd->aq_common_descriptor.flags = 0; 1957 get_cmd->type = type; 1958 1959 ret = ena_com_execute_admin_command(admin_queue, 1960 (struct ena_admin_aq_entry *)get_cmd, 1961 sizeof(*get_cmd), 1962 (struct ena_admin_acq_entry *)get_resp, 1963 sizeof(*get_resp)); 1964 1965 if (unlikely(ret)) 1966 ena_trc_err("Failed to get stats. error: %d\n", ret); 1967 1968 return ret; 1969 } 1970 1971 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 1972 struct ena_admin_basic_stats *stats) 1973 { 1974 struct ena_com_stats_ctx ctx; 1975 int ret; 1976 1977 memset(&ctx, 0x0, sizeof(ctx)); 1978 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC); 1979 if (likely(ret == 0)) 1980 memcpy(stats, &ctx.get_resp.basic_stats, 1981 sizeof(ctx.get_resp.basic_stats)); 1982 1983 return ret; 1984 } 1985 1986 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) 1987 { 1988 struct ena_com_admin_queue *admin_queue; 1989 struct ena_admin_set_feat_cmd cmd; 1990 struct ena_admin_set_feat_resp resp; 1991 int ret; 1992 1993 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { 1994 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU); 1995 return ENA_COM_UNSUPPORTED; 1996 } 1997 1998 memset(&cmd, 0x0, sizeof(cmd)); 1999 admin_queue = &ena_dev->admin_queue; 2000 2001 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2002 cmd.aq_common_descriptor.flags = 0; 2003 cmd.feat_common.feature_id = ENA_ADMIN_MTU; 2004 cmd.u.mtu.mtu = mtu; 2005 2006 ret = ena_com_execute_admin_command(admin_queue, 2007 (struct ena_admin_aq_entry *)&cmd, 2008 sizeof(cmd), 2009 (struct ena_admin_acq_entry *)&resp, 2010 sizeof(resp)); 2011 2012 if (unlikely(ret)) 2013 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret); 2014 2015 return ret; 2016 } 2017 2018 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 2019 struct ena_admin_feature_offload_desc *offload) 2020 { 2021 int ret; 2022 struct ena_admin_get_feat_resp resp; 2023 2024 ret = ena_com_get_feature(ena_dev, &resp, 2025 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG); 2026 if (unlikely(ret)) { 2027 ena_trc_err("Failed to get offload capabilities %d\n", ret); 2028 return ret; 2029 } 2030 2031 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload)); 2032 2033 return 0; 2034 } 2035 2036 int ena_com_set_hash_function(struct ena_com_dev *ena_dev) 2037 { 2038 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2039 struct ena_rss *rss = &ena_dev->rss; 2040 struct ena_admin_set_feat_cmd cmd; 2041 struct ena_admin_set_feat_resp resp; 2042 struct ena_admin_get_feat_resp get_resp; 2043 int ret; 2044 2045 if (!ena_com_check_supported_feature_id(ena_dev, 2046 ENA_ADMIN_RSS_HASH_FUNCTION)) { 2047 ena_trc_dbg("Feature %d isn't supported\n", 2048 ENA_ADMIN_RSS_HASH_FUNCTION); 2049 return ENA_COM_UNSUPPORTED; 2050 } 2051 2052 /* Validate hash function is supported */ 2053 ret = ena_com_get_feature(ena_dev, &get_resp, 2054 ENA_ADMIN_RSS_HASH_FUNCTION); 2055 if (unlikely(ret)) 2056 return ret; 2057 2058 if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) { 2059 ena_trc_err("Func hash %d isn't supported by device, abort\n", 2060 rss->hash_func); 2061 return ENA_COM_UNSUPPORTED; 2062 } 2063 2064 memset(&cmd, 0x0, sizeof(cmd)); 2065 2066 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2067 cmd.aq_common_descriptor.flags = 2068 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2069 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION; 2070 cmd.u.flow_hash_func.init_val = rss->hash_init_val; 2071 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func; 2072 2073 ret = ena_com_mem_addr_set(ena_dev, 2074 &cmd.control_buffer.address, 2075 rss->hash_key_dma_addr); 2076 if (unlikely(ret)) { 2077 ena_trc_err("memory address set failed\n"); 2078 return ret; 2079 } 2080 2081 cmd.control_buffer.length = sizeof(*rss->hash_key); 2082 2083 ret = ena_com_execute_admin_command(admin_queue, 2084 (struct ena_admin_aq_entry *)&cmd, 2085 sizeof(cmd), 2086 (struct ena_admin_acq_entry *)&resp, 2087 sizeof(resp)); 2088 if (unlikely(ret)) { 2089 ena_trc_err("Failed to set hash function %d. error: %d\n", 2090 rss->hash_func, ret); 2091 return ENA_COM_INVAL; 2092 } 2093 2094 return 0; 2095 } 2096 2097 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 2098 enum ena_admin_hash_functions func, 2099 const u8 *key, u16 key_len, u32 init_val) 2100 { 2101 struct ena_rss *rss = &ena_dev->rss; 2102 struct ena_admin_get_feat_resp get_resp; 2103 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2104 rss->hash_key; 2105 int rc; 2106 2107 /* Make sure size is a mult of DWs */ 2108 if (unlikely(key_len & 0x3)) 2109 return ENA_COM_INVAL; 2110 2111 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2112 ENA_ADMIN_RSS_HASH_FUNCTION, 2113 rss->hash_key_dma_addr, 2114 sizeof(*rss->hash_key)); 2115 if (unlikely(rc)) 2116 return rc; 2117 2118 if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) { 2119 ena_trc_err("Flow hash function %d isn't supported\n", func); 2120 return ENA_COM_UNSUPPORTED; 2121 } 2122 2123 switch (func) { 2124 case ENA_ADMIN_TOEPLITZ: 2125 if (key_len > sizeof(hash_key->key)) { 2126 ena_trc_err("key len (%hu) is bigger than the max supported (%zu)\n", 2127 key_len, sizeof(hash_key->key)); 2128 return ENA_COM_INVAL; 2129 } 2130 2131 memcpy(hash_key->key, key, key_len); 2132 rss->hash_init_val = init_val; 2133 hash_key->keys_num = key_len >> 2; 2134 break; 2135 case ENA_ADMIN_CRC32: 2136 rss->hash_init_val = init_val; 2137 break; 2138 default: 2139 ena_trc_err("Invalid hash function (%d)\n", func); 2140 return ENA_COM_INVAL; 2141 } 2142 2143 rc = ena_com_set_hash_function(ena_dev); 2144 2145 /* Restore the old function */ 2146 if (unlikely(rc)) 2147 ena_com_get_hash_function(ena_dev, NULL, NULL); 2148 2149 return rc; 2150 } 2151 2152 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 2153 enum ena_admin_hash_functions *func, 2154 u8 *key) 2155 { 2156 struct ena_rss *rss = &ena_dev->rss; 2157 struct ena_admin_get_feat_resp get_resp; 2158 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2159 rss->hash_key; 2160 int rc; 2161 2162 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2163 ENA_ADMIN_RSS_HASH_FUNCTION, 2164 rss->hash_key_dma_addr, 2165 sizeof(*rss->hash_key)); 2166 if (unlikely(rc)) 2167 return rc; 2168 2169 rss->hash_func = get_resp.u.flow_hash_func.selected_func; 2170 if (func) 2171 *func = rss->hash_func; 2172 2173 if (key) 2174 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2); 2175 2176 return 0; 2177 } 2178 2179 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 2180 enum ena_admin_flow_hash_proto proto, 2181 u16 *fields) 2182 { 2183 struct ena_rss *rss = &ena_dev->rss; 2184 struct ena_admin_get_feat_resp get_resp; 2185 int rc; 2186 2187 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2188 ENA_ADMIN_RSS_HASH_INPUT, 2189 rss->hash_ctrl_dma_addr, 2190 sizeof(*rss->hash_ctrl)); 2191 if (unlikely(rc)) 2192 return rc; 2193 2194 if (fields) 2195 *fields = rss->hash_ctrl->selected_fields[proto].fields; 2196 2197 return 0; 2198 } 2199 2200 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) 2201 { 2202 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2203 struct ena_rss *rss = &ena_dev->rss; 2204 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2205 struct ena_admin_set_feat_cmd cmd; 2206 struct ena_admin_set_feat_resp resp; 2207 int ret; 2208 2209 if (!ena_com_check_supported_feature_id(ena_dev, 2210 ENA_ADMIN_RSS_HASH_INPUT)) { 2211 ena_trc_dbg("Feature %d isn't supported\n", 2212 ENA_ADMIN_RSS_HASH_INPUT); 2213 return ENA_COM_UNSUPPORTED; 2214 } 2215 2216 memset(&cmd, 0x0, sizeof(cmd)); 2217 2218 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2219 cmd.aq_common_descriptor.flags = 2220 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2221 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT; 2222 cmd.u.flow_hash_input.enabled_input_sort = 2223 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK | 2224 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 2225 2226 ret = ena_com_mem_addr_set(ena_dev, 2227 &cmd.control_buffer.address, 2228 rss->hash_ctrl_dma_addr); 2229 if (unlikely(ret)) { 2230 ena_trc_err("memory address set failed\n"); 2231 return ret; 2232 } 2233 cmd.control_buffer.length = sizeof(*hash_ctrl); 2234 2235 ret = ena_com_execute_admin_command(admin_queue, 2236 (struct ena_admin_aq_entry *)&cmd, 2237 sizeof(cmd), 2238 (struct ena_admin_acq_entry *)&resp, 2239 sizeof(resp)); 2240 if (unlikely(ret)) 2241 ena_trc_err("Failed to set hash input. error: %d\n", ret); 2242 2243 return ret; 2244 } 2245 2246 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) 2247 { 2248 struct ena_rss *rss = &ena_dev->rss; 2249 struct ena_admin_feature_rss_hash_control *hash_ctrl = 2250 rss->hash_ctrl; 2251 u16 available_fields = 0; 2252 int rc, i; 2253 2254 /* Get the supported hash input */ 2255 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2256 if (unlikely(rc)) 2257 return rc; 2258 2259 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields = 2260 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2261 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2262 2263 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields = 2264 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2265 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2266 2267 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields = 2268 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2269 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2270 2271 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields = 2272 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2273 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2274 2275 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields = 2276 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2277 2278 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields = 2279 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2280 2281 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields = 2282 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2283 2284 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields = 2285 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA; 2286 2287 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) { 2288 available_fields = hash_ctrl->selected_fields[i].fields & 2289 hash_ctrl->supported_fields[i].fields; 2290 if (available_fields != hash_ctrl->selected_fields[i].fields) { 2291 ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", 2292 i, hash_ctrl->supported_fields[i].fields, 2293 hash_ctrl->selected_fields[i].fields); 2294 return ENA_COM_UNSUPPORTED; 2295 } 2296 } 2297 2298 rc = ena_com_set_hash_ctrl(ena_dev); 2299 2300 /* In case of failure, restore the old hash ctrl */ 2301 if (unlikely(rc)) 2302 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2303 2304 return rc; 2305 } 2306 2307 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 2308 enum ena_admin_flow_hash_proto proto, 2309 u16 hash_fields) 2310 { 2311 struct ena_rss *rss = &ena_dev->rss; 2312 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2313 u16 supported_fields; 2314 int rc; 2315 2316 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { 2317 ena_trc_err("Invalid proto num (%u)\n", proto); 2318 return ENA_COM_INVAL; 2319 } 2320 2321 /* Get the ctrl table */ 2322 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); 2323 if (unlikely(rc)) 2324 return rc; 2325 2326 /* Make sure all the fields are supported */ 2327 supported_fields = hash_ctrl->supported_fields[proto].fields; 2328 if ((hash_fields & supported_fields) != hash_fields) { 2329 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n", 2330 proto, hash_fields, supported_fields); 2331 } 2332 2333 hash_ctrl->selected_fields[proto].fields = hash_fields; 2334 2335 rc = ena_com_set_hash_ctrl(ena_dev); 2336 2337 /* In case of failure, restore the old hash ctrl */ 2338 if (unlikely(rc)) 2339 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2340 2341 return 0; 2342 } 2343 2344 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 2345 u16 entry_idx, u16 entry_value) 2346 { 2347 struct ena_rss *rss = &ena_dev->rss; 2348 2349 if (unlikely(entry_idx >= (1 << rss->tbl_log_size))) 2350 return ENA_COM_INVAL; 2351 2352 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES))) 2353 return ENA_COM_INVAL; 2354 2355 rss->host_rss_ind_tbl[entry_idx] = entry_value; 2356 2357 return 0; 2358 } 2359 2360 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) 2361 { 2362 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2363 struct ena_rss *rss = &ena_dev->rss; 2364 struct ena_admin_set_feat_cmd cmd; 2365 struct ena_admin_set_feat_resp resp; 2366 int ret; 2367 2368 if (!ena_com_check_supported_feature_id(ena_dev, 2369 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { 2370 ena_trc_dbg("Feature %d isn't supported\n", 2371 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 2372 return ENA_COM_UNSUPPORTED; 2373 } 2374 2375 ret = ena_com_ind_tbl_convert_to_device(ena_dev); 2376 if (ret) { 2377 ena_trc_err("Failed to convert host indirection table to device table\n"); 2378 return ret; 2379 } 2380 2381 memset(&cmd, 0x0, sizeof(cmd)); 2382 2383 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2384 cmd.aq_common_descriptor.flags = 2385 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2386 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG; 2387 cmd.u.ind_table.size = rss->tbl_log_size; 2388 cmd.u.ind_table.inline_index = 0xFFFFFFFF; 2389 2390 ret = ena_com_mem_addr_set(ena_dev, 2391 &cmd.control_buffer.address, 2392 rss->rss_ind_tbl_dma_addr); 2393 if (unlikely(ret)) { 2394 ena_trc_err("memory address set failed\n"); 2395 return ret; 2396 } 2397 2398 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * 2399 sizeof(struct ena_admin_rss_ind_table_entry); 2400 2401 ret = ena_com_execute_admin_command(admin_queue, 2402 (struct ena_admin_aq_entry *)&cmd, 2403 sizeof(cmd), 2404 (struct ena_admin_acq_entry *)&resp, 2405 sizeof(resp)); 2406 2407 if (unlikely(ret)) 2408 ena_trc_err("Failed to set indirect table. error: %d\n", ret); 2409 2410 return ret; 2411 } 2412 2413 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) 2414 { 2415 struct ena_rss *rss = &ena_dev->rss; 2416 struct ena_admin_get_feat_resp get_resp; 2417 u32 tbl_size; 2418 int i, rc; 2419 2420 tbl_size = (1ULL << rss->tbl_log_size) * 2421 sizeof(struct ena_admin_rss_ind_table_entry); 2422 2423 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2424 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 2425 rss->rss_ind_tbl_dma_addr, 2426 tbl_size); 2427 if (unlikely(rc)) 2428 return rc; 2429 2430 if (!ind_tbl) 2431 return 0; 2432 2433 rc = ena_com_ind_tbl_convert_from_device(ena_dev); 2434 if (unlikely(rc)) 2435 return rc; 2436 2437 for (i = 0; i < (1 << rss->tbl_log_size); i++) 2438 ind_tbl[i] = rss->host_rss_ind_tbl[i]; 2439 2440 return 0; 2441 } 2442 2443 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) 2444 { 2445 int rc; 2446 2447 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2448 2449 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); 2450 if (unlikely(rc)) 2451 goto err_indr_tbl; 2452 2453 rc = ena_com_hash_key_allocate(ena_dev); 2454 if (unlikely(rc)) 2455 goto err_hash_key; 2456 2457 rc = ena_com_hash_ctrl_init(ena_dev); 2458 if (unlikely(rc)) 2459 goto err_hash_ctrl; 2460 2461 return 0; 2462 2463 err_hash_ctrl: 2464 ena_com_hash_key_destroy(ena_dev); 2465 err_hash_key: 2466 ena_com_indirect_table_destroy(ena_dev); 2467 err_indr_tbl: 2468 2469 return rc; 2470 } 2471 2472 void ena_com_rss_destroy(struct ena_com_dev *ena_dev) 2473 { 2474 ena_com_indirect_table_destroy(ena_dev); 2475 ena_com_hash_key_destroy(ena_dev); 2476 ena_com_hash_ctrl_destroy(ena_dev); 2477 2478 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2479 } 2480 2481 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) 2482 { 2483 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2484 2485 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 2486 SZ_4K, 2487 host_attr->host_info, 2488 host_attr->host_info_dma_addr, 2489 host_attr->host_info_dma_handle); 2490 if (unlikely(!host_attr->host_info)) 2491 return ENA_COM_NO_MEM; 2492 2493 return 0; 2494 } 2495 2496 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 2497 u32 debug_area_size) 2498 { 2499 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2500 2501 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 2502 debug_area_size, 2503 host_attr->debug_area_virt_addr, 2504 host_attr->debug_area_dma_addr, 2505 host_attr->debug_area_dma_handle); 2506 if (unlikely(!host_attr->debug_area_virt_addr)) { 2507 host_attr->debug_area_size = 0; 2508 return ENA_COM_NO_MEM; 2509 } 2510 2511 host_attr->debug_area_size = debug_area_size; 2512 2513 return 0; 2514 } 2515 2516 void ena_com_delete_host_info(struct ena_com_dev *ena_dev) 2517 { 2518 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2519 2520 if (host_attr->host_info) { 2521 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 2522 SZ_4K, 2523 host_attr->host_info, 2524 host_attr->host_info_dma_addr, 2525 host_attr->host_info_dma_handle); 2526 host_attr->host_info = NULL; 2527 } 2528 } 2529 2530 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) 2531 { 2532 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2533 2534 if (host_attr->debug_area_virt_addr) { 2535 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 2536 host_attr->debug_area_size, 2537 host_attr->debug_area_virt_addr, 2538 host_attr->debug_area_dma_addr, 2539 host_attr->debug_area_dma_handle); 2540 host_attr->debug_area_virt_addr = NULL; 2541 } 2542 } 2543 2544 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) 2545 { 2546 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2547 struct ena_com_admin_queue *admin_queue; 2548 struct ena_admin_set_feat_cmd cmd; 2549 struct ena_admin_set_feat_resp resp; 2550 2551 int ret; 2552 2553 /* Host attribute config is called before ena_com_get_dev_attr_feat 2554 * so ena_com can't check if the feature is supported. 2555 */ 2556 2557 memset(&cmd, 0x0, sizeof(cmd)); 2558 admin_queue = &ena_dev->admin_queue; 2559 2560 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2561 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG; 2562 2563 ret = ena_com_mem_addr_set(ena_dev, 2564 &cmd.u.host_attr.debug_ba, 2565 host_attr->debug_area_dma_addr); 2566 if (unlikely(ret)) { 2567 ena_trc_err("memory address set failed\n"); 2568 return ret; 2569 } 2570 2571 ret = ena_com_mem_addr_set(ena_dev, 2572 &cmd.u.host_attr.os_info_ba, 2573 host_attr->host_info_dma_addr); 2574 if (unlikely(ret)) { 2575 ena_trc_err("memory address set failed\n"); 2576 return ret; 2577 } 2578 2579 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size; 2580 2581 ret = ena_com_execute_admin_command(admin_queue, 2582 (struct ena_admin_aq_entry *)&cmd, 2583 sizeof(cmd), 2584 (struct ena_admin_acq_entry *)&resp, 2585 sizeof(resp)); 2586 2587 if (unlikely(ret)) 2588 ena_trc_err("Failed to set host attributes: %d\n", ret); 2589 2590 return ret; 2591 } 2592 2593 /* Interrupt moderation */ 2594 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) 2595 { 2596 return ena_com_check_supported_feature_id(ena_dev, 2597 ENA_ADMIN_INTERRUPT_MODERATION); 2598 } 2599 2600 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 2601 u32 tx_coalesce_usecs) 2602 { 2603 if (!ena_dev->intr_delay_resolution) { 2604 ena_trc_err("Illegal interrupt delay granularity value\n"); 2605 return ENA_COM_FAULT; 2606 } 2607 2608 ena_dev->intr_moder_tx_interval = tx_coalesce_usecs / 2609 ena_dev->intr_delay_resolution; 2610 2611 return 0; 2612 } 2613 2614 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 2615 u32 rx_coalesce_usecs) 2616 { 2617 if (!ena_dev->intr_delay_resolution) { 2618 ena_trc_err("Illegal interrupt delay granularity value\n"); 2619 return ENA_COM_FAULT; 2620 } 2621 2622 /* We use LOWEST entry of moderation table for storing 2623 * nonadaptive interrupt coalescing values 2624 */ 2625 ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = 2626 rx_coalesce_usecs / ena_dev->intr_delay_resolution; 2627 2628 return 0; 2629 } 2630 2631 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev) 2632 { 2633 if (ena_dev->intr_moder_tbl) 2634 ENA_MEM_FREE(ena_dev->dmadev, ena_dev->intr_moder_tbl); 2635 ena_dev->intr_moder_tbl = NULL; 2636 } 2637 2638 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) 2639 { 2640 struct ena_admin_get_feat_resp get_resp; 2641 u16 delay_resolution; 2642 int rc; 2643 2644 rc = ena_com_get_feature(ena_dev, &get_resp, 2645 ENA_ADMIN_INTERRUPT_MODERATION); 2646 2647 if (rc) { 2648 if (rc == ENA_COM_UNSUPPORTED) { 2649 ena_trc_dbg("Feature %d isn't supported\n", 2650 ENA_ADMIN_INTERRUPT_MODERATION); 2651 rc = 0; 2652 } else { 2653 ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n", 2654 rc); 2655 } 2656 2657 /* no moderation supported, disable adaptive support */ 2658 ena_com_disable_adaptive_moderation(ena_dev); 2659 return rc; 2660 } 2661 2662 rc = ena_com_init_interrupt_moderation_table(ena_dev); 2663 if (rc) 2664 goto err; 2665 2666 /* if moderation is supported by device we set adaptive moderation */ 2667 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution; 2668 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); 2669 ena_com_enable_adaptive_moderation(ena_dev); 2670 2671 return 0; 2672 err: 2673 ena_com_destroy_interrupt_moderation(ena_dev); 2674 return rc; 2675 } 2676 2677 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev) 2678 { 2679 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2680 2681 if (!intr_moder_tbl) 2682 return; 2683 2684 intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = 2685 ENA_INTR_LOWEST_USECS; 2686 intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval = 2687 ENA_INTR_LOWEST_PKTS; 2688 intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval = 2689 ENA_INTR_LOWEST_BYTES; 2690 2691 intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval = 2692 ENA_INTR_LOW_USECS; 2693 intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval = 2694 ENA_INTR_LOW_PKTS; 2695 intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval = 2696 ENA_INTR_LOW_BYTES; 2697 2698 intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval = 2699 ENA_INTR_MID_USECS; 2700 intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval = 2701 ENA_INTR_MID_PKTS; 2702 intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval = 2703 ENA_INTR_MID_BYTES; 2704 2705 intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval = 2706 ENA_INTR_HIGH_USECS; 2707 intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval = 2708 ENA_INTR_HIGH_PKTS; 2709 intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval = 2710 ENA_INTR_HIGH_BYTES; 2711 2712 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval = 2713 ENA_INTR_HIGHEST_USECS; 2714 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval = 2715 ENA_INTR_HIGHEST_PKTS; 2716 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval = 2717 ENA_INTR_HIGHEST_BYTES; 2718 } 2719 2720 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) 2721 { 2722 return ena_dev->intr_moder_tx_interval; 2723 } 2724 2725 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) 2726 { 2727 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2728 2729 if (intr_moder_tbl) 2730 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval; 2731 2732 return 0; 2733 } 2734 2735 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, 2736 enum ena_intr_moder_level level, 2737 struct ena_intr_moder_entry *entry) 2738 { 2739 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2740 2741 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) 2742 return; 2743 2744 intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval; 2745 if (ena_dev->intr_delay_resolution) 2746 intr_moder_tbl[level].intr_moder_interval /= 2747 ena_dev->intr_delay_resolution; 2748 intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval; 2749 2750 /* use hardcoded value until ethtool supports bytecount parameter */ 2751 if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED) 2752 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval; 2753 } 2754 2755 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, 2756 enum ena_intr_moder_level level, 2757 struct ena_intr_moder_entry *entry) 2758 { 2759 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2760 2761 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) 2762 return; 2763 2764 entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval; 2765 if (ena_dev->intr_delay_resolution) 2766 entry->intr_moder_interval *= ena_dev->intr_delay_resolution; 2767 entry->pkts_per_interval = 2768 intr_moder_tbl[level].pkts_per_interval; 2769 entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval; 2770 } 2771