1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stdio.h> 35 #include <errno.h> 36 #include <stdint.h> 37 #include <stdlib.h> 38 #include <unistd.h> 39 #include <stdarg.h> 40 #include <inttypes.h> 41 42 #include <rte_bus_pci.h> 43 #include <rte_interrupts.h> 44 #include <rte_log.h> 45 #include <rte_debug.h> 46 #include <rte_eal.h> 47 #include <rte_ether.h> 48 #include <rte_ethdev.h> 49 #include <rte_memcpy.h> 50 #include <rte_malloc.h> 51 #include <rte_random.h> 52 53 #include "base/e1000_defines.h" 54 #include "base/e1000_regs.h" 55 #include "base/e1000_hw.h" 56 #include "e1000_ethdev.h" 57 58 static inline uint16_t 59 dev_num_vf(struct rte_eth_dev *eth_dev) 60 { 61 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 62 63 return pci_dev->max_vfs; 64 } 65 66 static inline 67 int igb_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num) 68 { 69 unsigned char vf_mac_addr[ETHER_ADDR_LEN]; 70 struct e1000_vf_info *vfinfo = 71 *E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 72 uint16_t vfn; 73 74 for (vfn = 0; vfn < vf_num; vfn++) { 75 eth_random_addr(vf_mac_addr); 76 /* keep the random address as default */ 77 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr, 78 ETHER_ADDR_LEN); 79 } 80 81 return 0; 82 } 83 84 static inline int 85 igb_mb_intr_setup(struct rte_eth_dev *dev) 86 { 87 struct e1000_interrupt *intr = 88 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 89 90 intr->mask |= E1000_ICR_VMMB; 91 92 return 0; 93 } 94 95 void igb_pf_host_init(struct rte_eth_dev *eth_dev) 96 { 97 struct e1000_vf_info **vfinfo = 98 E1000_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private); 99 struct e1000_hw *hw = 100 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 101 uint16_t vf_num; 102 uint8_t nb_queue; 103 104 RTE_ETH_DEV_SRIOV(eth_dev).active = 0; 105 if (0 == (vf_num = dev_num_vf(eth_dev))) 106 return; 107 108 if (hw->mac.type == e1000_i350) 109 nb_queue = 1; 110 else if(hw->mac.type == e1000_82576) 111 /* per datasheet, it should be 2, but 1 seems correct */ 112 nb_queue = 1; 113 else 114 return; 115 116 *vfinfo = rte_zmalloc("vf_info", sizeof(struct e1000_vf_info) * vf_num, 0); 117 if (*vfinfo == NULL) 118 rte_panic("Cannot allocate memory for private VF data\n"); 119 120 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_8_POOLS; 121 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue; 122 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num; 123 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue); 124 125 igb_vf_perm_addr_gen(eth_dev, vf_num); 126 127 /* set mb interrupt mask */ 128 igb_mb_intr_setup(eth_dev); 129 130 return; 131 } 132 133 void igb_pf_host_uninit(struct rte_eth_dev *dev) 134 { 135 struct e1000_vf_info **vfinfo; 136 uint16_t vf_num; 137 138 PMD_INIT_FUNC_TRACE(); 139 140 vfinfo = E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 141 142 RTE_ETH_DEV_SRIOV(dev).active = 0; 143 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 0; 144 RTE_ETH_DEV_SRIOV(dev).def_vmdq_idx = 0; 145 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 0; 146 147 vf_num = dev_num_vf(dev); 148 if (vf_num == 0) 149 return; 150 151 rte_free(*vfinfo); 152 *vfinfo = NULL; 153 } 154 155 #define E1000_RAH_POOLSEL_SHIFT (18) 156 int igb_pf_host_configure(struct rte_eth_dev *eth_dev) 157 { 158 uint32_t vtctl; 159 uint16_t vf_num; 160 struct e1000_hw *hw = 161 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 162 uint32_t vlanctrl; 163 int i; 164 uint32_t rah; 165 166 if (0 == (vf_num = dev_num_vf(eth_dev))) 167 return -1; 168 169 /* enable VMDq and set the default pool for PF */ 170 vtctl = E1000_READ_REG(hw, E1000_VT_CTL); 171 vtctl &= ~E1000_VT_CTL_DEFAULT_POOL_MASK; 172 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx 173 << E1000_VT_CTL_DEFAULT_POOL_SHIFT; 174 vtctl |= E1000_VT_CTL_VM_REPL_EN; 175 E1000_WRITE_REG(hw, E1000_VT_CTL, vtctl); 176 177 /* Enable pools reserved to PF only */ 178 E1000_WRITE_REG(hw, E1000_VFRE, (~0U) << vf_num); 179 E1000_WRITE_REG(hw, E1000_VFTE, (~0U) << vf_num); 180 181 /* PFDMA Tx General Switch Control Enables VMDQ loopback */ 182 if (hw->mac.type == e1000_i350) 183 E1000_WRITE_REG(hw, E1000_TXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN); 184 else 185 E1000_WRITE_REG(hw, E1000_DTXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN); 186 187 /* clear VMDq map to perment rar 0 */ 188 rah = E1000_READ_REG(hw, E1000_RAH(0)); 189 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT); 190 E1000_WRITE_REG(hw, E1000_RAH(0), rah); 191 192 /* clear VMDq map to scan rar 32 */ 193 rah = E1000_READ_REG(hw, E1000_RAH(hw->mac.rar_entry_count)); 194 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT); 195 E1000_WRITE_REG(hw, E1000_RAH(hw->mac.rar_entry_count), rah); 196 197 /* set VMDq map to default PF pool */ 198 rah = E1000_READ_REG(hw, E1000_RAH(0)); 199 rah |= (0x1 << (RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx + 200 E1000_RAH_POOLSEL_SHIFT)); 201 E1000_WRITE_REG(hw, E1000_RAH(0), rah); 202 203 /* 204 * enable vlan filtering and allow all vlan tags through 205 */ 206 vlanctrl = E1000_READ_REG(hw, E1000_RCTL); 207 vlanctrl |= E1000_RCTL_VFE ; /* enable vlan filters */ 208 E1000_WRITE_REG(hw, E1000_RCTL, vlanctrl); 209 210 /* VFTA - enable all vlan filters */ 211 for (i = 0; i < IGB_VFTA_SIZE; i++) { 212 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, 0xFFFFFFFF); 213 } 214 215 /* Enable/Disable MAC Anti-Spoofing */ 216 e1000_vmdq_set_anti_spoofing_pf(hw, FALSE, vf_num); 217 218 return 0; 219 } 220 221 static void 222 set_rx_mode(struct rte_eth_dev *dev) 223 { 224 struct rte_eth_dev_data *dev_data = dev->data; 225 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 226 uint32_t fctrl, vmolr = E1000_VMOLR_BAM | E1000_VMOLR_AUPE; 227 uint16_t vfn = dev_num_vf(dev); 228 229 /* Check for Promiscuous and All Multicast modes */ 230 fctrl = E1000_READ_REG(hw, E1000_RCTL); 231 232 /* set all bits that we expect to always be set */ 233 fctrl &= ~E1000_RCTL_SBP; /* disable store-bad-packets */ 234 fctrl |= E1000_RCTL_BAM; 235 236 /* clear the bits we are changing the status of */ 237 fctrl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 238 239 if (dev_data->promiscuous) { 240 fctrl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 241 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 242 } else { 243 if (dev_data->all_multicast) { 244 fctrl |= E1000_RCTL_MPE; 245 vmolr |= E1000_VMOLR_MPME; 246 } else { 247 vmolr |= E1000_VMOLR_ROMPE; 248 } 249 } 250 251 if ((hw->mac.type == e1000_82576) || 252 (hw->mac.type == e1000_i350)) { 253 vmolr |= E1000_READ_REG(hw, E1000_VMOLR(vfn)) & 254 ~(E1000_VMOLR_MPME | E1000_VMOLR_ROMPE | 255 E1000_VMOLR_ROPE); 256 E1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr); 257 } 258 259 E1000_WRITE_REG(hw, E1000_RCTL, fctrl); 260 } 261 262 static inline void 263 igb_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf) 264 { 265 struct e1000_hw *hw = 266 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 267 struct e1000_vf_info *vfinfo = 268 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 269 uint32_t vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf)); 270 271 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | 272 E1000_VMOLR_BAM | E1000_VMOLR_AUPE); 273 E1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr); 274 275 E1000_WRITE_REG(hw, E1000_VMVIR(vf), 0); 276 277 /* reset multicast table array for vf */ 278 vfinfo[vf].num_vf_mc_hashes = 0; 279 280 /* reset rx mode */ 281 set_rx_mode(dev); 282 } 283 284 static inline void 285 igb_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf) 286 { 287 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 288 uint32_t reg; 289 290 /* enable transmit and receive for vf */ 291 reg = E1000_READ_REG(hw, E1000_VFTE); 292 reg |= (reg | (1 << vf)); 293 E1000_WRITE_REG(hw, E1000_VFTE, reg); 294 295 reg = E1000_READ_REG(hw, E1000_VFRE); 296 reg |= (reg | (1 << vf)); 297 E1000_WRITE_REG(hw, E1000_VFRE, reg); 298 299 igb_vf_reset_event(dev, vf); 300 } 301 302 static int 303 igb_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf) 304 { 305 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 306 struct e1000_vf_info *vfinfo = 307 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 308 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses; 309 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 310 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]); 311 uint32_t rah; 312 313 igb_vf_reset_msg(dev, vf); 314 315 hw->mac.ops.rar_set(hw, vf_mac, rar_entry); 316 rah = E1000_READ_REG(hw, E1000_RAH(rar_entry)); 317 rah |= (0x1 << (vf + E1000_RAH_POOLSEL_SHIFT)); 318 E1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah); 319 320 /* reply to reset with ack and vf mac address */ 321 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 322 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN); 323 e1000_write_mbx(hw, msgbuf, 3, vf); 324 325 return 0; 326 } 327 328 static int 329 igb_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 330 { 331 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 332 struct e1000_vf_info *vfinfo = 333 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 334 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 335 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]); 336 int rah; 337 338 if (is_unicast_ether_addr((struct ether_addr *)new_mac)) { 339 if (!is_zero_ether_addr((struct ether_addr *)new_mac)) 340 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 341 sizeof(vfinfo[vf].vf_mac_addresses)); 342 hw->mac.ops.rar_set(hw, new_mac, rar_entry); 343 rah = E1000_READ_REG(hw, E1000_RAH(rar_entry)); 344 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + vf)); 345 E1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah); 346 return 0; 347 } 348 return -1; 349 } 350 351 static int 352 igb_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf) 353 { 354 int i; 355 uint32_t vector_bit; 356 uint32_t vector_reg; 357 uint32_t mta_reg; 358 int entries = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> 359 E1000_VT_MSGINFO_SHIFT; 360 uint16_t *hash_list = (uint16_t *)&msgbuf[1]; 361 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 362 struct e1000_vf_info *vfinfo = 363 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 364 365 /* only so many hash values supported */ 366 entries = RTE_MIN(entries, E1000_MAX_VF_MC_ENTRIES); 367 368 /* 369 * salt away the number of multi cast addresses assigned 370 * to this VF for later use to restore when the PF multi cast 371 * list changes 372 */ 373 vfinfo->num_vf_mc_hashes = (uint16_t)entries; 374 375 /* 376 * VFs are limited to using the MTA hash table for their multicast 377 * addresses 378 */ 379 for (i = 0; i < entries; i++) { 380 vfinfo->vf_mc_hashes[i] = hash_list[i]; 381 } 382 383 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) { 384 vector_reg = (vfinfo->vf_mc_hashes[i] >> 5) & 0x7F; 385 vector_bit = vfinfo->vf_mc_hashes[i] & 0x1F; 386 mta_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, vector_reg); 387 mta_reg |= (1 << vector_bit); 388 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, vector_reg, mta_reg); 389 } 390 391 return 0; 392 } 393 394 static int 395 igb_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 396 { 397 int add, vid; 398 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 399 struct e1000_vf_info *vfinfo = 400 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 401 uint32_t vid_idx, vid_bit, vfta; 402 403 add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) 404 >> E1000_VT_MSGINFO_SHIFT; 405 vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 406 407 if (add) 408 vfinfo[vf].vlan_count++; 409 else if (vfinfo[vf].vlan_count) 410 vfinfo[vf].vlan_count--; 411 412 vid_idx = (uint32_t)((vid >> E1000_VFTA_ENTRY_SHIFT) & 413 E1000_VFTA_ENTRY_MASK); 414 vid_bit = (uint32_t)(1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK)); 415 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx); 416 if (add) 417 vfta |= vid_bit; 418 else 419 vfta &= ~vid_bit; 420 421 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta); 422 E1000_WRITE_FLUSH(hw); 423 424 return 0; 425 } 426 427 static int 428 igb_vf_set_rlpml(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 429 { 430 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 431 uint16_t rlpml = msgbuf[1] & E1000_VMOLR_RLPML_MASK; 432 uint32_t max_frame = rlpml + ETHER_HDR_LEN + ETHER_CRC_LEN; 433 uint32_t vmolr; 434 435 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN)) 436 return -1; 437 438 vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf)); 439 440 vmolr &= ~E1000_VMOLR_RLPML_MASK; 441 vmolr |= rlpml; 442 443 /* Enable Long Packet support */ 444 vmolr |= E1000_VMOLR_LPE; 445 446 E1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr); 447 E1000_WRITE_FLUSH(hw); 448 449 return 0; 450 } 451 452 static int 453 igb_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf) 454 { 455 uint16_t mbx_size = E1000_VFMAILBOX_SIZE; 456 uint32_t msgbuf[E1000_VFMAILBOX_SIZE]; 457 int32_t retval; 458 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 459 460 retval = e1000_read_mbx(hw, msgbuf, mbx_size, vf); 461 if (retval) { 462 PMD_INIT_LOG(ERR, "Error mbx recv msg from VF %d", vf); 463 return retval; 464 } 465 466 /* do nothing with the message already processed */ 467 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 468 return retval; 469 470 /* flush the ack before we write any messages back */ 471 E1000_WRITE_FLUSH(hw); 472 473 /* perform VF reset */ 474 if (msgbuf[0] == E1000_VF_RESET) { 475 return igb_vf_reset(dev, vf, msgbuf); 476 } 477 478 /* check & process VF to PF mailbox message */ 479 switch ((msgbuf[0] & 0xFFFF)) { 480 case E1000_VF_SET_MAC_ADDR: 481 retval = igb_vf_set_mac_addr(dev, vf, msgbuf); 482 break; 483 case E1000_VF_SET_MULTICAST: 484 retval = igb_vf_set_multicast(dev, vf, msgbuf); 485 break; 486 case E1000_VF_SET_LPE: 487 retval = igb_vf_set_rlpml(dev, vf, msgbuf); 488 break; 489 case E1000_VF_SET_VLAN: 490 retval = igb_vf_set_vlan(dev, vf, msgbuf); 491 break; 492 default: 493 PMD_INIT_LOG(DEBUG, "Unhandled Msg %8.8x", 494 (unsigned) msgbuf[0]); 495 retval = E1000_ERR_MBX; 496 break; 497 } 498 499 /* response the VF according to the message process result */ 500 if (retval) 501 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 502 else 503 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 504 505 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 506 507 e1000_write_mbx(hw, msgbuf, 1, vf); 508 509 return retval; 510 } 511 512 static inline void 513 igb_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf) 514 { 515 uint32_t msg = E1000_VT_MSGTYPE_NACK; 516 struct e1000_hw *hw = 517 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 518 519 e1000_write_mbx(hw, &msg, 1, vf); 520 } 521 522 void igb_pf_mbx_process(struct rte_eth_dev *eth_dev) 523 { 524 uint16_t vf; 525 struct e1000_hw *hw = 526 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 527 528 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) { 529 /* check & process vf function level reset */ 530 if (!e1000_check_for_rst(hw, vf)) 531 igb_vf_reset_event(eth_dev, vf); 532 533 /* check & process vf mailbox messages */ 534 if (!e1000_check_for_msg(hw, vf)) 535 igb_rcv_msg_from_vf(eth_dev, vf); 536 537 /* check & process acks from vf */ 538 if (!e1000_check_for_ack(hw, vf)) 539 igb_rcv_ack_from_vf(eth_dev, vf); 540 } 541 } 542