1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/queue.h> 35 #include <stdio.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <stdarg.h> 39 40 #include <rte_common.h> 41 #include <rte_interrupts.h> 42 #include <rte_byteorder.h> 43 #include <rte_log.h> 44 #include <rte_debug.h> 45 #include <rte_pci.h> 46 #include <rte_bus_pci.h> 47 #include <rte_ether.h> 48 #include <rte_ethdev.h> 49 #include <rte_ethdev_pci.h> 50 #include <rte_memory.h> 51 #include <rte_eal.h> 52 #include <rte_atomic.h> 53 #include <rte_malloc.h> 54 #include <rte_dev.h> 55 56 #include "e1000_logs.h" 57 #include "base/e1000_api.h" 58 #include "e1000_ethdev.h" 59 #include "igb_regs.h" 60 61 /* 62 * Default values for port configuration 63 */ 64 #define IGB_DEFAULT_RX_FREE_THRESH 32 65 66 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) 67 #define IGB_DEFAULT_RX_HTHRESH 8 68 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4) 69 70 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 71 #define IGB_DEFAULT_TX_HTHRESH 1 72 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16) 73 74 #define IGB_HKEY_MAX_INDEX 10 75 76 /* Bit shift and mask */ 77 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2) 78 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t) 79 #define IGB_8_BIT_WIDTH CHAR_BIT 80 #define IGB_8_BIT_MASK UINT8_MAX 81 82 /* Additional timesync values. */ 83 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL 84 #define E1000_ETQF_FILTER_1588 3 85 #define IGB_82576_TSYNC_SHIFT 16 86 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) 87 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) 88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000 89 90 #define E1000_VTIVAR_MISC 0x01740 91 #define E1000_VTIVAR_MISC_MASK 0xFF 92 #define E1000_VTIVAR_VALID 0x80 93 #define E1000_VTIVAR_MISC_MAILBOX 0 94 #define E1000_VTIVAR_MISC_INTR_MASK 0x3 95 96 /* External VLAN Enable bit mask */ 97 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26) 98 99 /* External VLAN Ether Type bit mask and shift */ 100 #define E1000_VET_VET_EXT 0xFFFF0000 101 #define E1000_VET_VET_EXT_SHIFT 16 102 103 static int eth_igb_configure(struct rte_eth_dev *dev); 104 static int eth_igb_start(struct rte_eth_dev *dev); 105 static void eth_igb_stop(struct rte_eth_dev *dev); 106 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev); 107 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev); 108 static void eth_igb_close(struct rte_eth_dev *dev); 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev); 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev); 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev); 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev); 113 static int eth_igb_link_update(struct rte_eth_dev *dev, 114 int wait_to_complete); 115 static int eth_igb_stats_get(struct rte_eth_dev *dev, 116 struct rte_eth_stats *rte_stats); 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev, 118 struct rte_eth_xstat *xstats, unsigned n); 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, 120 const uint64_t *ids, 121 uint64_t *values, unsigned int n); 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev, 123 struct rte_eth_xstat_name *xstats_names, 124 unsigned int size); 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev, 126 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 127 unsigned int limit); 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev); 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev); 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev, 131 char *fw_version, size_t fw_size); 132 static void eth_igb_infos_get(struct rte_eth_dev *dev, 133 struct rte_eth_dev_info *dev_info); 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev); 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev, 136 struct rte_eth_dev_info *dev_info); 137 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, 138 struct rte_eth_fc_conf *fc_conf); 139 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, 140 struct rte_eth_fc_conf *fc_conf); 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev); 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev); 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev, 145 struct rte_intr_handle *handle); 146 static void eth_igb_interrupt_handler(void *param); 147 static int igb_hardware_init(struct e1000_hw *hw); 148 static void igb_hw_control_acquire(struct e1000_hw *hw); 149 static void igb_hw_control_release(struct e1000_hw *hw); 150 static void igb_init_manageability(struct e1000_hw *hw); 151 static void igb_release_manageability(struct e1000_hw *hw); 152 153 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 154 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev, 156 uint16_t vlan_id, int on); 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, 158 enum rte_vlan_type vlan_type, 159 uint16_t tpid_id); 160 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask); 161 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev); 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev); 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev); 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev); 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev); 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev); 168 169 static int eth_igb_led_on(struct rte_eth_dev *dev); 170 static int eth_igb_led_off(struct rte_eth_dev *dev); 171 172 static void igb_intr_disable(struct e1000_hw *hw); 173 static int igb_get_rx_buffer_size(struct e1000_hw *hw); 174 static int eth_igb_rar_set(struct rte_eth_dev *dev, 175 struct ether_addr *mac_addr, 176 uint32_t index, uint32_t pool); 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index); 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev, 179 struct ether_addr *addr); 180 181 static void igbvf_intr_disable(struct e1000_hw *hw); 182 static int igbvf_dev_configure(struct rte_eth_dev *dev); 183 static int igbvf_dev_start(struct rte_eth_dev *dev); 184 static void igbvf_dev_stop(struct rte_eth_dev *dev); 185 static void igbvf_dev_close(struct rte_eth_dev *dev); 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev); 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev); 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev); 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev); 190 static int eth_igbvf_link_update(struct e1000_hw *hw); 191 static int eth_igbvf_stats_get(struct rte_eth_dev *dev, 192 struct rte_eth_stats *rte_stats); 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev, 194 struct rte_eth_xstat *xstats, unsigned n); 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev, 196 struct rte_eth_xstat_name *xstats_names, 197 unsigned limit); 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev); 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev, 200 uint16_t vlan_id, int on); 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on); 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on); 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev, 204 struct ether_addr *addr); 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev); 206 static int igbvf_get_regs(struct rte_eth_dev *dev, 207 struct rte_dev_reg_info *regs); 208 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev, 210 struct rte_eth_rss_reta_entry64 *reta_conf, 211 uint16_t reta_size); 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev, 213 struct rte_eth_rss_reta_entry64 *reta_conf, 214 uint16_t reta_size); 215 216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev, 217 struct rte_eth_syn_filter *filter); 218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev, 219 enum rte_filter_op filter_op, 220 void *arg); 221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev, 222 struct rte_eth_ntuple_filter *ntuple_filter); 223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev, 224 struct rte_eth_ntuple_filter *ntuple_filter); 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev, 226 struct rte_eth_flex_filter *filter); 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev, 228 enum rte_filter_op filter_op, 229 void *arg); 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev, 231 struct rte_eth_ntuple_filter *ntuple_filter); 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev, 233 struct rte_eth_ntuple_filter *ntuple_filter); 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev, 235 struct rte_eth_ntuple_filter *filter); 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev, 237 enum rte_filter_op filter_op, 238 void *arg); 239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev, 240 enum rte_filter_op filter_op, 241 void *arg); 242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev, 243 struct rte_eth_ethertype_filter *filter); 244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev, 245 enum rte_filter_type filter_type, 246 enum rte_filter_op filter_op, 247 void *arg); 248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev); 249 static int eth_igb_get_regs(struct rte_eth_dev *dev, 250 struct rte_dev_reg_info *regs); 251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev); 252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev, 253 struct rte_dev_eeprom_info *eeprom); 254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev, 255 struct rte_dev_eeprom_info *eeprom); 256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev, 257 struct ether_addr *mc_addr_set, 258 uint32_t nb_mc_addr); 259 static int igb_timesync_enable(struct rte_eth_dev *dev); 260 static int igb_timesync_disable(struct rte_eth_dev *dev); 261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 262 struct timespec *timestamp, 263 uint32_t flags); 264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 265 struct timespec *timestamp); 266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 267 static int igb_timesync_read_time(struct rte_eth_dev *dev, 268 struct timespec *timestamp); 269 static int igb_timesync_write_time(struct rte_eth_dev *dev, 270 const struct timespec *timestamp); 271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, 272 uint16_t queue_id); 273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, 274 uint16_t queue_id); 275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction, 276 uint8_t queue, uint8_t msix_vector); 277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector, 278 uint8_t index, uint8_t offset); 279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev); 280 static void eth_igbvf_interrupt_handler(void *param); 281 static void igbvf_mbx_process(struct rte_eth_dev *dev); 282 static int igb_filter_restore(struct rte_eth_dev *dev); 283 284 /* 285 * Define VF Stats MACRO for Non "cleared on read" register 286 */ 287 #define UPDATE_VF_STAT(reg, last, cur) \ 288 { \ 289 u32 latest = E1000_READ_REG(hw, reg); \ 290 cur += (latest - last) & UINT_MAX; \ 291 last = latest; \ 292 } 293 294 #define IGB_FC_PAUSE_TIME 0x0680 295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */ 296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */ 297 298 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */ 299 300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full; 301 302 /* 303 * The set of PCI devices this driver supports 304 */ 305 static const struct rte_pci_id pci_id_igb_map[] = { 306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) }, 307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) }, 308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) }, 309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) }, 310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) }, 311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) }, 312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) }, 313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) }, 314 315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) }, 316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) }, 317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) }, 318 319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) }, 320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) }, 321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) }, 322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) }, 323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) }, 324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) }, 325 326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) }, 327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) }, 328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) }, 329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) }, 330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) }, 331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) }, 332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) }, 333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) }, 334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) }, 335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) }, 336 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) }, 337 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) }, 338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) }, 339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) }, 340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) }, 342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) }, 344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) }, 345 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) }, 346 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) }, 347 { .vendor_id = 0, /* sentinel */ }, 348 }; 349 350 /* 351 * The set of PCI devices this driver supports (for 82576&I350 VF) 352 */ 353 static const struct rte_pci_id pci_id_igbvf_map[] = { 354 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) }, 355 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) }, 356 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) }, 357 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) }, 358 { .vendor_id = 0, /* sentinel */ }, 359 }; 360 361 static const struct rte_eth_desc_lim rx_desc_lim = { 362 .nb_max = E1000_MAX_RING_DESC, 363 .nb_min = E1000_MIN_RING_DESC, 364 .nb_align = IGB_RXD_ALIGN, 365 }; 366 367 static const struct rte_eth_desc_lim tx_desc_lim = { 368 .nb_max = E1000_MAX_RING_DESC, 369 .nb_min = E1000_MIN_RING_DESC, 370 .nb_align = IGB_RXD_ALIGN, 371 .nb_seg_max = IGB_TX_MAX_SEG, 372 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG, 373 }; 374 375 static const struct eth_dev_ops eth_igb_ops = { 376 .dev_configure = eth_igb_configure, 377 .dev_start = eth_igb_start, 378 .dev_stop = eth_igb_stop, 379 .dev_set_link_up = eth_igb_dev_set_link_up, 380 .dev_set_link_down = eth_igb_dev_set_link_down, 381 .dev_close = eth_igb_close, 382 .promiscuous_enable = eth_igb_promiscuous_enable, 383 .promiscuous_disable = eth_igb_promiscuous_disable, 384 .allmulticast_enable = eth_igb_allmulticast_enable, 385 .allmulticast_disable = eth_igb_allmulticast_disable, 386 .link_update = eth_igb_link_update, 387 .stats_get = eth_igb_stats_get, 388 .xstats_get = eth_igb_xstats_get, 389 .xstats_get_by_id = eth_igb_xstats_get_by_id, 390 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id, 391 .xstats_get_names = eth_igb_xstats_get_names, 392 .stats_reset = eth_igb_stats_reset, 393 .xstats_reset = eth_igb_xstats_reset, 394 .fw_version_get = eth_igb_fw_version_get, 395 .dev_infos_get = eth_igb_infos_get, 396 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get, 397 .mtu_set = eth_igb_mtu_set, 398 .vlan_filter_set = eth_igb_vlan_filter_set, 399 .vlan_tpid_set = eth_igb_vlan_tpid_set, 400 .vlan_offload_set = eth_igb_vlan_offload_set, 401 .rx_queue_setup = eth_igb_rx_queue_setup, 402 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable, 403 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable, 404 .rx_queue_release = eth_igb_rx_queue_release, 405 .rx_queue_count = eth_igb_rx_queue_count, 406 .rx_descriptor_done = eth_igb_rx_descriptor_done, 407 .rx_descriptor_status = eth_igb_rx_descriptor_status, 408 .tx_descriptor_status = eth_igb_tx_descriptor_status, 409 .tx_queue_setup = eth_igb_tx_queue_setup, 410 .tx_queue_release = eth_igb_tx_queue_release, 411 .tx_done_cleanup = eth_igb_tx_done_cleanup, 412 .dev_led_on = eth_igb_led_on, 413 .dev_led_off = eth_igb_led_off, 414 .flow_ctrl_get = eth_igb_flow_ctrl_get, 415 .flow_ctrl_set = eth_igb_flow_ctrl_set, 416 .mac_addr_add = eth_igb_rar_set, 417 .mac_addr_remove = eth_igb_rar_clear, 418 .mac_addr_set = eth_igb_default_mac_addr_set, 419 .reta_update = eth_igb_rss_reta_update, 420 .reta_query = eth_igb_rss_reta_query, 421 .rss_hash_update = eth_igb_rss_hash_update, 422 .rss_hash_conf_get = eth_igb_rss_hash_conf_get, 423 .filter_ctrl = eth_igb_filter_ctrl, 424 .set_mc_addr_list = eth_igb_set_mc_addr_list, 425 .rxq_info_get = igb_rxq_info_get, 426 .txq_info_get = igb_txq_info_get, 427 .timesync_enable = igb_timesync_enable, 428 .timesync_disable = igb_timesync_disable, 429 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp, 430 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp, 431 .get_reg = eth_igb_get_regs, 432 .get_eeprom_length = eth_igb_get_eeprom_length, 433 .get_eeprom = eth_igb_get_eeprom, 434 .set_eeprom = eth_igb_set_eeprom, 435 .timesync_adjust_time = igb_timesync_adjust_time, 436 .timesync_read_time = igb_timesync_read_time, 437 .timesync_write_time = igb_timesync_write_time, 438 }; 439 440 /* 441 * dev_ops for virtual function, bare necessities for basic vf 442 * operation have been implemented 443 */ 444 static const struct eth_dev_ops igbvf_eth_dev_ops = { 445 .dev_configure = igbvf_dev_configure, 446 .dev_start = igbvf_dev_start, 447 .dev_stop = igbvf_dev_stop, 448 .dev_close = igbvf_dev_close, 449 .promiscuous_enable = igbvf_promiscuous_enable, 450 .promiscuous_disable = igbvf_promiscuous_disable, 451 .allmulticast_enable = igbvf_allmulticast_enable, 452 .allmulticast_disable = igbvf_allmulticast_disable, 453 .link_update = eth_igb_link_update, 454 .stats_get = eth_igbvf_stats_get, 455 .xstats_get = eth_igbvf_xstats_get, 456 .xstats_get_names = eth_igbvf_xstats_get_names, 457 .stats_reset = eth_igbvf_stats_reset, 458 .xstats_reset = eth_igbvf_stats_reset, 459 .vlan_filter_set = igbvf_vlan_filter_set, 460 .dev_infos_get = eth_igbvf_infos_get, 461 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get, 462 .rx_queue_setup = eth_igb_rx_queue_setup, 463 .rx_queue_release = eth_igb_rx_queue_release, 464 .tx_queue_setup = eth_igb_tx_queue_setup, 465 .tx_queue_release = eth_igb_tx_queue_release, 466 .set_mc_addr_list = eth_igb_set_mc_addr_list, 467 .rxq_info_get = igb_rxq_info_get, 468 .txq_info_get = igb_txq_info_get, 469 .mac_addr_set = igbvf_default_mac_addr_set, 470 .get_reg = igbvf_get_regs, 471 }; 472 473 /* store statistics names and its offset in stats structure */ 474 struct rte_igb_xstats_name_off { 475 char name[RTE_ETH_XSTATS_NAME_SIZE]; 476 unsigned offset; 477 }; 478 479 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = { 480 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)}, 481 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)}, 482 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)}, 483 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)}, 484 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)}, 485 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)}, 486 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats, 487 ecol)}, 488 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)}, 489 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)}, 490 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)}, 491 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)}, 492 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)}, 493 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)}, 494 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)}, 495 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)}, 496 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)}, 497 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)}, 498 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats, 499 fcruc)}, 500 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)}, 501 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)}, 502 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)}, 503 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)}, 504 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats, 505 prc1023)}, 506 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats, 507 prc1522)}, 508 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)}, 509 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)}, 510 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)}, 511 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)}, 512 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)}, 513 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)}, 514 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)}, 515 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)}, 516 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)}, 517 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)}, 518 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)}, 519 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)}, 520 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)}, 521 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)}, 522 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)}, 523 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)}, 524 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)}, 525 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats, 526 ptc1023)}, 527 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats, 528 ptc1522)}, 529 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)}, 530 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)}, 531 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)}, 532 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)}, 533 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)}, 534 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)}, 535 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)}, 536 537 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)}, 538 }; 539 540 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \ 541 sizeof(rte_igb_stats_strings[0])) 542 543 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = { 544 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)}, 545 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)}, 546 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)}, 547 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)}, 548 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)}, 549 }; 550 551 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \ 552 sizeof(rte_igbvf_stats_strings[0])) 553 554 /** 555 * Atomically reads the link status information from global 556 * structure rte_eth_dev. 557 * 558 * @param dev 559 * - Pointer to the structure rte_eth_dev to read from. 560 * - Pointer to the buffer to be saved with the link status. 561 * 562 * @return 563 * - On success, zero. 564 * - On failure, negative value. 565 */ 566 static inline int 567 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev, 568 struct rte_eth_link *link) 569 { 570 struct rte_eth_link *dst = link; 571 struct rte_eth_link *src = &(dev->data->dev_link); 572 573 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 574 *(uint64_t *)src) == 0) 575 return -1; 576 577 return 0; 578 } 579 580 /** 581 * Atomically writes the link status information into global 582 * structure rte_eth_dev. 583 * 584 * @param dev 585 * - Pointer to the structure rte_eth_dev to read from. 586 * - Pointer to the buffer to be saved with the link status. 587 * 588 * @return 589 * - On success, zero. 590 * - On failure, negative value. 591 */ 592 static inline int 593 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev, 594 struct rte_eth_link *link) 595 { 596 struct rte_eth_link *dst = &(dev->data->dev_link); 597 struct rte_eth_link *src = link; 598 599 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 600 *(uint64_t *)src) == 0) 601 return -1; 602 603 return 0; 604 } 605 606 static inline void 607 igb_intr_enable(struct rte_eth_dev *dev) 608 { 609 struct e1000_interrupt *intr = 610 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 611 struct e1000_hw *hw = 612 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 613 614 E1000_WRITE_REG(hw, E1000_IMS, intr->mask); 615 E1000_WRITE_FLUSH(hw); 616 } 617 618 static void 619 igb_intr_disable(struct e1000_hw *hw) 620 { 621 E1000_WRITE_REG(hw, E1000_IMC, ~0); 622 E1000_WRITE_FLUSH(hw); 623 } 624 625 static inline void 626 igbvf_intr_enable(struct rte_eth_dev *dev) 627 { 628 struct e1000_hw *hw = 629 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 630 631 /* only for mailbox */ 632 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX); 633 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX); 634 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX); 635 E1000_WRITE_FLUSH(hw); 636 } 637 638 /* only for mailbox now. If RX/TX needed, should extend this function. */ 639 static void 640 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector) 641 { 642 uint32_t tmp = 0; 643 644 /* mailbox */ 645 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK); 646 tmp |= E1000_VTIVAR_VALID; 647 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp); 648 } 649 650 static void 651 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev) 652 { 653 struct e1000_hw *hw = 654 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 655 656 /* Configure VF other cause ivar */ 657 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX); 658 } 659 660 static inline int32_t 661 igb_pf_reset_hw(struct e1000_hw *hw) 662 { 663 uint32_t ctrl_ext; 664 int32_t status; 665 666 status = e1000_reset_hw(hw); 667 668 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 669 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 670 ctrl_ext |= E1000_CTRL_EXT_PFRSTD; 671 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 672 E1000_WRITE_FLUSH(hw); 673 674 return status; 675 } 676 677 static void 678 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev) 679 { 680 struct e1000_hw *hw = 681 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 682 683 684 hw->vendor_id = pci_dev->id.vendor_id; 685 hw->device_id = pci_dev->id.device_id; 686 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 687 hw->subsystem_device_id = pci_dev->id.subsystem_device_id; 688 689 e1000_set_mac_type(hw); 690 691 /* need to check if it is a vf device below */ 692 } 693 694 static int 695 igb_reset_swfw_lock(struct e1000_hw *hw) 696 { 697 int ret_val; 698 699 /* 700 * Do mac ops initialization manually here, since we will need 701 * some function pointers set by this call. 702 */ 703 ret_val = e1000_init_mac_params(hw); 704 if (ret_val) 705 return ret_val; 706 707 /* 708 * SMBI lock should not fail in this early stage. If this is the case, 709 * it is due to an improper exit of the application. 710 * So force the release of the faulty lock. 711 */ 712 if (e1000_get_hw_semaphore_generic(hw) < 0) { 713 PMD_DRV_LOG(DEBUG, "SMBI lock released"); 714 } 715 e1000_put_hw_semaphore_generic(hw); 716 717 if (hw->mac.ops.acquire_swfw_sync != NULL) { 718 uint16_t mask; 719 720 /* 721 * Phy lock should not fail in this early stage. If this is the case, 722 * it is due to an improper exit of the application. 723 * So force the release of the faulty lock. 724 */ 725 mask = E1000_SWFW_PHY0_SM << hw->bus.func; 726 if (hw->bus.func > E1000_FUNC_1) 727 mask <<= 2; 728 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { 729 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", 730 hw->bus.func); 731 } 732 hw->mac.ops.release_swfw_sync(hw, mask); 733 734 /* 735 * This one is more tricky since it is common to all ports; but 736 * swfw_sync retries last long enough (1s) to be almost sure that if 737 * lock can not be taken it is due to an improper lock of the 738 * semaphore. 739 */ 740 mask = E1000_SWFW_EEP_SM; 741 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) { 742 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 743 } 744 hw->mac.ops.release_swfw_sync(hw, mask); 745 } 746 747 return E1000_SUCCESS; 748 } 749 750 /* Remove all ntuple filters of the device */ 751 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 752 { 753 struct e1000_filter_info *filter_info = 754 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 755 struct e1000_5tuple_filter *p_5tuple; 756 struct e1000_2tuple_filter *p_2tuple; 757 758 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 759 TAILQ_REMOVE(&filter_info->fivetuple_list, 760 p_5tuple, entries); 761 rte_free(p_5tuple); 762 } 763 filter_info->fivetuple_mask = 0; 764 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) { 765 TAILQ_REMOVE(&filter_info->twotuple_list, 766 p_2tuple, entries); 767 rte_free(p_2tuple); 768 } 769 filter_info->twotuple_mask = 0; 770 771 return 0; 772 } 773 774 /* Remove all flex filters of the device */ 775 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev) 776 { 777 struct e1000_filter_info *filter_info = 778 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 779 struct e1000_flex_filter *p_flex; 780 781 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) { 782 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries); 783 rte_free(p_flex); 784 } 785 filter_info->flex_mask = 0; 786 787 return 0; 788 } 789 790 static int 791 eth_igb_dev_init(struct rte_eth_dev *eth_dev) 792 { 793 int error = 0; 794 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 795 struct e1000_hw *hw = 796 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 797 struct e1000_vfta * shadow_vfta = 798 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 799 struct e1000_filter_info *filter_info = 800 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 801 struct e1000_adapter *adapter = 802 E1000_DEV_PRIVATE(eth_dev->data->dev_private); 803 804 uint32_t ctrl_ext; 805 806 eth_dev->dev_ops = ð_igb_ops; 807 eth_dev->rx_pkt_burst = ð_igb_recv_pkts; 808 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts; 809 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts; 810 811 /* for secondary processes, we don't initialise any further as primary 812 * has already done this work. Only check we don't need a different 813 * RX function */ 814 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 815 if (eth_dev->data->scattered_rx) 816 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts; 817 return 0; 818 } 819 820 rte_eth_copy_pci_info(eth_dev, pci_dev); 821 822 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr; 823 824 igb_identify_hardware(eth_dev, pci_dev); 825 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) { 826 error = -EIO; 827 goto err_late; 828 } 829 830 e1000_get_bus_info(hw); 831 832 /* Reset any pending lock */ 833 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) { 834 error = -EIO; 835 goto err_late; 836 } 837 838 /* Finish initialization */ 839 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) { 840 error = -EIO; 841 goto err_late; 842 } 843 844 hw->mac.autoneg = 1; 845 hw->phy.autoneg_wait_to_complete = 0; 846 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX; 847 848 /* Copper options */ 849 if (hw->phy.media_type == e1000_media_type_copper) { 850 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 851 hw->phy.disable_polarity_correction = 0; 852 hw->phy.ms_type = e1000_ms_hw_default; 853 } 854 855 /* 856 * Start from a known state, this is important in reading the nvm 857 * and mac from that. 858 */ 859 igb_pf_reset_hw(hw); 860 861 /* Make sure we have a good EEPROM before we read from it */ 862 if (e1000_validate_nvm_checksum(hw) < 0) { 863 /* 864 * Some PCI-E parts fail the first check due to 865 * the link being in sleep state, call it again, 866 * if it fails a second time its a real issue. 867 */ 868 if (e1000_validate_nvm_checksum(hw) < 0) { 869 PMD_INIT_LOG(ERR, "EEPROM checksum invalid"); 870 error = -EIO; 871 goto err_late; 872 } 873 } 874 875 /* Read the permanent MAC address out of the EEPROM */ 876 if (e1000_read_mac_addr(hw) != 0) { 877 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address"); 878 error = -EIO; 879 goto err_late; 880 } 881 882 /* Allocate memory for storing MAC addresses */ 883 eth_dev->data->mac_addrs = rte_zmalloc("e1000", 884 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0); 885 if (eth_dev->data->mac_addrs == NULL) { 886 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to " 887 "store MAC addresses", 888 ETHER_ADDR_LEN * hw->mac.rar_entry_count); 889 error = -ENOMEM; 890 goto err_late; 891 } 892 893 /* Copy the permanent MAC address */ 894 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]); 895 896 /* initialize the vfta */ 897 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 898 899 /* Now initialize the hardware */ 900 if (igb_hardware_init(hw) != 0) { 901 PMD_INIT_LOG(ERR, "Hardware initialization failed"); 902 rte_free(eth_dev->data->mac_addrs); 903 eth_dev->data->mac_addrs = NULL; 904 error = -ENODEV; 905 goto err_late; 906 } 907 hw->mac.get_link_status = 1; 908 adapter->stopped = 0; 909 910 /* Indicate SOL/IDER usage */ 911 if (e1000_check_reset_block(hw) < 0) { 912 PMD_INIT_LOG(ERR, "PHY reset is blocked due to" 913 "SOL/IDER session"); 914 } 915 916 /* initialize PF if max_vfs not zero */ 917 igb_pf_host_init(eth_dev); 918 919 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 920 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 921 ctrl_ext |= E1000_CTRL_EXT_PFRSTD; 922 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 923 E1000_WRITE_FLUSH(hw); 924 925 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x", 926 eth_dev->data->port_id, pci_dev->id.vendor_id, 927 pci_dev->id.device_id); 928 929 rte_intr_callback_register(&pci_dev->intr_handle, 930 eth_igb_interrupt_handler, 931 (void *)eth_dev); 932 933 /* enable uio/vfio intr/eventfd mapping */ 934 rte_intr_enable(&pci_dev->intr_handle); 935 936 /* enable support intr */ 937 igb_intr_enable(eth_dev); 938 939 /* initialize filter info */ 940 memset(filter_info, 0, 941 sizeof(struct e1000_filter_info)); 942 943 TAILQ_INIT(&filter_info->flex_list); 944 TAILQ_INIT(&filter_info->twotuple_list); 945 TAILQ_INIT(&filter_info->fivetuple_list); 946 947 TAILQ_INIT(&igb_filter_ntuple_list); 948 TAILQ_INIT(&igb_filter_ethertype_list); 949 TAILQ_INIT(&igb_filter_syn_list); 950 TAILQ_INIT(&igb_filter_flex_list); 951 TAILQ_INIT(&igb_flow_list); 952 953 return 0; 954 955 err_late: 956 igb_hw_control_release(hw); 957 958 return error; 959 } 960 961 static int 962 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev) 963 { 964 struct rte_pci_device *pci_dev; 965 struct rte_intr_handle *intr_handle; 966 struct e1000_hw *hw; 967 struct e1000_adapter *adapter = 968 E1000_DEV_PRIVATE(eth_dev->data->dev_private); 969 struct e1000_filter_info *filter_info = 970 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 971 972 PMD_INIT_FUNC_TRACE(); 973 974 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 975 return -EPERM; 976 977 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 978 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 979 intr_handle = &pci_dev->intr_handle; 980 981 if (adapter->stopped == 0) 982 eth_igb_close(eth_dev); 983 984 eth_dev->dev_ops = NULL; 985 eth_dev->rx_pkt_burst = NULL; 986 eth_dev->tx_pkt_burst = NULL; 987 988 /* Reset any pending lock */ 989 igb_reset_swfw_lock(hw); 990 991 rte_free(eth_dev->data->mac_addrs); 992 eth_dev->data->mac_addrs = NULL; 993 994 /* uninitialize PF if max_vfs not zero */ 995 igb_pf_host_uninit(eth_dev); 996 997 /* disable uio intr before callback unregister */ 998 rte_intr_disable(intr_handle); 999 rte_intr_callback_unregister(intr_handle, 1000 eth_igb_interrupt_handler, eth_dev); 1001 1002 /* clear the SYN filter info */ 1003 filter_info->syn_info = 0; 1004 1005 /* clear the ethertype filters info */ 1006 filter_info->ethertype_mask = 0; 1007 memset(filter_info->ethertype_filters, 0, 1008 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter)); 1009 1010 /* remove all ntuple filters of the device */ 1011 igb_ntuple_filter_uninit(eth_dev); 1012 1013 /* remove all flex filters of the device */ 1014 igb_flex_filter_uninit(eth_dev); 1015 1016 /* clear all the filters list */ 1017 igb_filterlist_flush(eth_dev); 1018 1019 return 0; 1020 } 1021 1022 /* 1023 * Virtual Function device init 1024 */ 1025 static int 1026 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev) 1027 { 1028 struct rte_pci_device *pci_dev; 1029 struct rte_intr_handle *intr_handle; 1030 struct e1000_adapter *adapter = 1031 E1000_DEV_PRIVATE(eth_dev->data->dev_private); 1032 struct e1000_hw *hw = 1033 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1034 int diag; 1035 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr; 1036 1037 PMD_INIT_FUNC_TRACE(); 1038 1039 eth_dev->dev_ops = &igbvf_eth_dev_ops; 1040 eth_dev->rx_pkt_burst = ð_igb_recv_pkts; 1041 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts; 1042 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts; 1043 1044 /* for secondary processes, we don't initialise any further as primary 1045 * has already done this work. Only check we don't need a different 1046 * RX function */ 1047 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 1048 if (eth_dev->data->scattered_rx) 1049 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts; 1050 return 0; 1051 } 1052 1053 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1054 rte_eth_copy_pci_info(eth_dev, pci_dev); 1055 1056 hw->device_id = pci_dev->id.device_id; 1057 hw->vendor_id = pci_dev->id.vendor_id; 1058 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1059 adapter->stopped = 0; 1060 1061 /* Initialize the shared code (base driver) */ 1062 diag = e1000_setup_init_funcs(hw, TRUE); 1063 if (diag != 0) { 1064 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d", 1065 diag); 1066 return -EIO; 1067 } 1068 1069 /* init_mailbox_params */ 1070 hw->mbx.ops.init_params(hw); 1071 1072 /* Disable the interrupts for VF */ 1073 igbvf_intr_disable(hw); 1074 1075 diag = hw->mac.ops.reset_hw(hw); 1076 1077 /* Allocate memory for storing MAC addresses */ 1078 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN * 1079 hw->mac.rar_entry_count, 0); 1080 if (eth_dev->data->mac_addrs == NULL) { 1081 PMD_INIT_LOG(ERR, 1082 "Failed to allocate %d bytes needed to store MAC " 1083 "addresses", 1084 ETHER_ADDR_LEN * hw->mac.rar_entry_count); 1085 return -ENOMEM; 1086 } 1087 1088 /* Generate a random MAC address, if none was assigned by PF. */ 1089 if (is_zero_ether_addr(perm_addr)) { 1090 eth_random_addr(perm_addr->addr_bytes); 1091 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1092 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1093 "%02x:%02x:%02x:%02x:%02x:%02x", 1094 perm_addr->addr_bytes[0], 1095 perm_addr->addr_bytes[1], 1096 perm_addr->addr_bytes[2], 1097 perm_addr->addr_bytes[3], 1098 perm_addr->addr_bytes[4], 1099 perm_addr->addr_bytes[5]); 1100 } 1101 1102 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0); 1103 if (diag) { 1104 rte_free(eth_dev->data->mac_addrs); 1105 eth_dev->data->mac_addrs = NULL; 1106 return diag; 1107 } 1108 /* Copy the permanent MAC address */ 1109 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr, 1110 ð_dev->data->mac_addrs[0]); 1111 1112 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x " 1113 "mac.type=%s", 1114 eth_dev->data->port_id, pci_dev->id.vendor_id, 1115 pci_dev->id.device_id, "igb_mac_82576_vf"); 1116 1117 intr_handle = &pci_dev->intr_handle; 1118 rte_intr_callback_register(intr_handle, 1119 eth_igbvf_interrupt_handler, eth_dev); 1120 1121 return 0; 1122 } 1123 1124 static int 1125 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev) 1126 { 1127 struct e1000_adapter *adapter = 1128 E1000_DEV_PRIVATE(eth_dev->data->dev_private); 1129 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1130 1131 PMD_INIT_FUNC_TRACE(); 1132 1133 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1134 return -EPERM; 1135 1136 if (adapter->stopped == 0) 1137 igbvf_dev_close(eth_dev); 1138 1139 eth_dev->dev_ops = NULL; 1140 eth_dev->rx_pkt_burst = NULL; 1141 eth_dev->tx_pkt_burst = NULL; 1142 1143 rte_free(eth_dev->data->mac_addrs); 1144 eth_dev->data->mac_addrs = NULL; 1145 1146 /* disable uio intr before callback unregister */ 1147 rte_intr_disable(&pci_dev->intr_handle); 1148 rte_intr_callback_unregister(&pci_dev->intr_handle, 1149 eth_igbvf_interrupt_handler, 1150 (void *)eth_dev); 1151 1152 return 0; 1153 } 1154 1155 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1156 struct rte_pci_device *pci_dev) 1157 { 1158 return rte_eth_dev_pci_generic_probe(pci_dev, 1159 sizeof(struct e1000_adapter), eth_igb_dev_init); 1160 } 1161 1162 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev) 1163 { 1164 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit); 1165 } 1166 1167 static struct rte_pci_driver rte_igb_pmd = { 1168 .id_table = pci_id_igb_map, 1169 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 1170 RTE_PCI_DRV_IOVA_AS_VA, 1171 .probe = eth_igb_pci_probe, 1172 .remove = eth_igb_pci_remove, 1173 }; 1174 1175 1176 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1177 struct rte_pci_device *pci_dev) 1178 { 1179 return rte_eth_dev_pci_generic_probe(pci_dev, 1180 sizeof(struct e1000_adapter), eth_igbvf_dev_init); 1181 } 1182 1183 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev) 1184 { 1185 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit); 1186 } 1187 1188 /* 1189 * virtual function driver struct 1190 */ 1191 static struct rte_pci_driver rte_igbvf_pmd = { 1192 .id_table = pci_id_igbvf_map, 1193 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, 1194 .probe = eth_igbvf_pci_probe, 1195 .remove = eth_igbvf_pci_remove, 1196 }; 1197 1198 static void 1199 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1200 { 1201 struct e1000_hw *hw = 1202 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1203 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */ 1204 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 1205 rctl |= E1000_RCTL_VFE; 1206 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1207 } 1208 1209 static int 1210 igb_check_mq_mode(struct rte_eth_dev *dev) 1211 { 1212 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 1213 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 1214 uint16_t nb_rx_q = dev->data->nb_rx_queues; 1215 uint16_t nb_tx_q = dev->data->nb_tx_queues; 1216 1217 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) || 1218 tx_mq_mode == ETH_MQ_TX_DCB || 1219 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) { 1220 PMD_INIT_LOG(ERR, "DCB mode is not supported."); 1221 return -EINVAL; 1222 } 1223 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 1224 /* Check multi-queue mode. 1225 * To no break software we accept ETH_MQ_RX_NONE as this might 1226 * be used to turn off VLAN filter. 1227 */ 1228 1229 if (rx_mq_mode == ETH_MQ_RX_NONE || 1230 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 1231 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 1232 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1; 1233 } else { 1234 /* Only support one queue on VFs. 1235 * RSS together with SRIOV is not supported. 1236 */ 1237 PMD_INIT_LOG(ERR, "SRIOV is active," 1238 " wrong mq_mode rx %d.", 1239 rx_mq_mode); 1240 return -EINVAL; 1241 } 1242 /* TX mode is not used here, so mode might be ignored.*/ 1243 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) { 1244 /* SRIOV only works in VMDq enable mode */ 1245 PMD_INIT_LOG(WARNING, "SRIOV is active," 1246 " TX mode %d is not supported. " 1247 " Driver will behave as %d mode.", 1248 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY); 1249 } 1250 1251 /* check valid queue number */ 1252 if ((nb_rx_q > 1) || (nb_tx_q > 1)) { 1253 PMD_INIT_LOG(ERR, "SRIOV is active," 1254 " only support one queue on VFs."); 1255 return -EINVAL; 1256 } 1257 } else { 1258 /* To no break software that set invalid mode, only display 1259 * warning if invalid mode is used. 1260 */ 1261 if (rx_mq_mode != ETH_MQ_RX_NONE && 1262 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY && 1263 rx_mq_mode != ETH_MQ_RX_RSS) { 1264 /* RSS together with VMDq not supported*/ 1265 PMD_INIT_LOG(ERR, "RX mode %d is not supported.", 1266 rx_mq_mode); 1267 return -EINVAL; 1268 } 1269 1270 if (tx_mq_mode != ETH_MQ_TX_NONE && 1271 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) { 1272 PMD_INIT_LOG(WARNING, "TX mode %d is not supported." 1273 " Due to txmode is meaningless in this" 1274 " driver, just ignore.", 1275 tx_mq_mode); 1276 } 1277 } 1278 return 0; 1279 } 1280 1281 static int 1282 eth_igb_configure(struct rte_eth_dev *dev) 1283 { 1284 struct e1000_interrupt *intr = 1285 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 1286 int ret; 1287 1288 PMD_INIT_FUNC_TRACE(); 1289 1290 /* multipe queue mode checking */ 1291 ret = igb_check_mq_mode(dev); 1292 if (ret != 0) { 1293 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.", 1294 ret); 1295 return ret; 1296 } 1297 1298 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE; 1299 PMD_INIT_FUNC_TRACE(); 1300 1301 return 0; 1302 } 1303 1304 static int 1305 eth_igb_start(struct rte_eth_dev *dev) 1306 { 1307 struct e1000_hw *hw = 1308 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1309 struct e1000_adapter *adapter = 1310 E1000_DEV_PRIVATE(dev->data->dev_private); 1311 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1312 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1313 int ret, mask; 1314 uint32_t intr_vector = 0; 1315 uint32_t ctrl_ext; 1316 uint32_t *speeds; 1317 int num_speeds; 1318 bool autoneg; 1319 1320 PMD_INIT_FUNC_TRACE(); 1321 1322 /* disable uio/vfio intr/eventfd mapping */ 1323 rte_intr_disable(intr_handle); 1324 1325 /* Power up the phy. Needed to make the link go Up */ 1326 eth_igb_dev_set_link_up(dev); 1327 1328 /* 1329 * Packet Buffer Allocation (PBA) 1330 * Writing PBA sets the receive portion of the buffer 1331 * the remainder is used for the transmit buffer. 1332 */ 1333 if (hw->mac.type == e1000_82575) { 1334 uint32_t pba; 1335 1336 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1337 E1000_WRITE_REG(hw, E1000_PBA, pba); 1338 } 1339 1340 /* Put the address into the Receive Address Array */ 1341 e1000_rar_set(hw, hw->mac.addr, 0); 1342 1343 /* Initialize the hardware */ 1344 if (igb_hardware_init(hw)) { 1345 PMD_INIT_LOG(ERR, "Unable to initialize the hardware"); 1346 return -EIO; 1347 } 1348 adapter->stopped = 0; 1349 1350 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN); 1351 1352 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1353 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1354 ctrl_ext |= E1000_CTRL_EXT_PFRSTD; 1355 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1356 E1000_WRITE_FLUSH(hw); 1357 1358 /* configure PF module if SRIOV enabled */ 1359 igb_pf_host_configure(dev); 1360 1361 /* check and configure queue intr-vector mapping */ 1362 if ((rte_intr_cap_multiple(intr_handle) || 1363 !RTE_ETH_DEV_SRIOV(dev).active) && 1364 dev->data->dev_conf.intr_conf.rxq != 0) { 1365 intr_vector = dev->data->nb_rx_queues; 1366 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1367 return -1; 1368 } 1369 1370 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1371 intr_handle->intr_vec = 1372 rte_zmalloc("intr_vec", 1373 dev->data->nb_rx_queues * sizeof(int), 0); 1374 if (intr_handle->intr_vec == NULL) { 1375 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 1376 " intr_vec", dev->data->nb_rx_queues); 1377 return -ENOMEM; 1378 } 1379 } 1380 1381 /* confiugre msix for rx interrupt */ 1382 eth_igb_configure_msix_intr(dev); 1383 1384 /* Configure for OS presence */ 1385 igb_init_manageability(hw); 1386 1387 eth_igb_tx_init(dev); 1388 1389 /* This can fail when allocating mbufs for descriptor rings */ 1390 ret = eth_igb_rx_init(dev); 1391 if (ret) { 1392 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 1393 igb_dev_clear_queues(dev); 1394 return ret; 1395 } 1396 1397 e1000_clear_hw_cntrs_base_generic(hw); 1398 1399 /* 1400 * VLAN Offload Settings 1401 */ 1402 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \ 1403 ETH_VLAN_EXTEND_MASK; 1404 ret = eth_igb_vlan_offload_set(dev, mask); 1405 if (ret) { 1406 PMD_INIT_LOG(ERR, "Unable to set vlan offload"); 1407 igb_dev_clear_queues(dev); 1408 return ret; 1409 } 1410 1411 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 1412 /* Enable VLAN filter since VMDq always use VLAN filter */ 1413 igb_vmdq_vlan_hw_filter_enable(dev); 1414 } 1415 1416 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) || 1417 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) || 1418 (hw->mac.type == e1000_i211)) { 1419 /* Configure EITR with the maximum possible value (0xFFFF) */ 1420 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF); 1421 } 1422 1423 /* Setup link speed and duplex */ 1424 speeds = &dev->data->dev_conf.link_speeds; 1425 if (*speeds == ETH_LINK_SPEED_AUTONEG) { 1426 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX; 1427 hw->mac.autoneg = 1; 1428 } else { 1429 num_speeds = 0; 1430 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0; 1431 1432 /* Reset */ 1433 hw->phy.autoneg_advertised = 0; 1434 1435 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M | 1436 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M | 1437 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) { 1438 num_speeds = -1; 1439 goto error_invalid_config; 1440 } 1441 if (*speeds & ETH_LINK_SPEED_10M_HD) { 1442 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF; 1443 num_speeds++; 1444 } 1445 if (*speeds & ETH_LINK_SPEED_10M) { 1446 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL; 1447 num_speeds++; 1448 } 1449 if (*speeds & ETH_LINK_SPEED_100M_HD) { 1450 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF; 1451 num_speeds++; 1452 } 1453 if (*speeds & ETH_LINK_SPEED_100M) { 1454 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL; 1455 num_speeds++; 1456 } 1457 if (*speeds & ETH_LINK_SPEED_1G) { 1458 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL; 1459 num_speeds++; 1460 } 1461 if (num_speeds == 0 || (!autoneg && (num_speeds > 1))) 1462 goto error_invalid_config; 1463 1464 /* Set/reset the mac.autoneg based on the link speed, 1465 * fixed or not 1466 */ 1467 if (!autoneg) { 1468 hw->mac.autoneg = 0; 1469 hw->mac.forced_speed_duplex = 1470 hw->phy.autoneg_advertised; 1471 } else { 1472 hw->mac.autoneg = 1; 1473 } 1474 } 1475 1476 e1000_setup_link(hw); 1477 1478 if (rte_intr_allow_others(intr_handle)) { 1479 /* check if lsc interrupt is enabled */ 1480 if (dev->data->dev_conf.intr_conf.lsc != 0) 1481 eth_igb_lsc_interrupt_setup(dev, TRUE); 1482 else 1483 eth_igb_lsc_interrupt_setup(dev, FALSE); 1484 } else { 1485 rte_intr_callback_unregister(intr_handle, 1486 eth_igb_interrupt_handler, 1487 (void *)dev); 1488 if (dev->data->dev_conf.intr_conf.lsc != 0) 1489 PMD_INIT_LOG(INFO, "lsc won't enable because of" 1490 " no intr multiplex"); 1491 } 1492 1493 /* check if rxq interrupt is enabled */ 1494 if (dev->data->dev_conf.intr_conf.rxq != 0 && 1495 rte_intr_dp_is_en(intr_handle)) 1496 eth_igb_rxq_interrupt_setup(dev); 1497 1498 /* enable uio/vfio intr/eventfd mapping */ 1499 rte_intr_enable(intr_handle); 1500 1501 /* resume enabled intr since hw reset */ 1502 igb_intr_enable(dev); 1503 1504 /* restore all types filter */ 1505 igb_filter_restore(dev); 1506 1507 PMD_INIT_LOG(DEBUG, "<<"); 1508 1509 return 0; 1510 1511 error_invalid_config: 1512 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u", 1513 dev->data->dev_conf.link_speeds, dev->data->port_id); 1514 igb_dev_clear_queues(dev); 1515 return -EINVAL; 1516 } 1517 1518 /********************************************************************* 1519 * 1520 * This routine disables all traffic on the adapter by issuing a 1521 * global reset on the MAC. 1522 * 1523 **********************************************************************/ 1524 static void 1525 eth_igb_stop(struct rte_eth_dev *dev) 1526 { 1527 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1528 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1529 struct rte_eth_link link; 1530 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1531 1532 igb_intr_disable(hw); 1533 1534 /* disable intr eventfd mapping */ 1535 rte_intr_disable(intr_handle); 1536 1537 igb_pf_reset_hw(hw); 1538 E1000_WRITE_REG(hw, E1000_WUC, 0); 1539 1540 /* Set bit for Go Link disconnect */ 1541 if (hw->mac.type >= e1000_82580) { 1542 uint32_t phpm_reg; 1543 1544 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1545 phpm_reg |= E1000_82580_PM_GO_LINKD; 1546 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1547 } 1548 1549 /* Power down the phy. Needed to make the link go Down */ 1550 eth_igb_dev_set_link_down(dev); 1551 1552 igb_dev_clear_queues(dev); 1553 1554 /* clear the recorded link status */ 1555 memset(&link, 0, sizeof(link)); 1556 rte_igb_dev_atomic_write_link_status(dev, &link); 1557 1558 if (!rte_intr_allow_others(intr_handle)) 1559 /* resume to the default handler */ 1560 rte_intr_callback_register(intr_handle, 1561 eth_igb_interrupt_handler, 1562 (void *)dev); 1563 1564 /* Clean datapath event and queue/vec mapping */ 1565 rte_intr_efd_disable(intr_handle); 1566 if (intr_handle->intr_vec != NULL) { 1567 rte_free(intr_handle->intr_vec); 1568 intr_handle->intr_vec = NULL; 1569 } 1570 } 1571 1572 static int 1573 eth_igb_dev_set_link_up(struct rte_eth_dev *dev) 1574 { 1575 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1576 1577 if (hw->phy.media_type == e1000_media_type_copper) 1578 e1000_power_up_phy(hw); 1579 else 1580 e1000_power_up_fiber_serdes_link(hw); 1581 1582 return 0; 1583 } 1584 1585 static int 1586 eth_igb_dev_set_link_down(struct rte_eth_dev *dev) 1587 { 1588 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1589 1590 if (hw->phy.media_type == e1000_media_type_copper) 1591 e1000_power_down_phy(hw); 1592 else 1593 e1000_shutdown_fiber_serdes_link(hw); 1594 1595 return 0; 1596 } 1597 1598 static void 1599 eth_igb_close(struct rte_eth_dev *dev) 1600 { 1601 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1602 struct e1000_adapter *adapter = 1603 E1000_DEV_PRIVATE(dev->data->dev_private); 1604 struct rte_eth_link link; 1605 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1606 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1607 1608 eth_igb_stop(dev); 1609 adapter->stopped = 1; 1610 1611 e1000_phy_hw_reset(hw); 1612 igb_release_manageability(hw); 1613 igb_hw_control_release(hw); 1614 1615 /* Clear bit for Go Link disconnect */ 1616 if (hw->mac.type >= e1000_82580) { 1617 uint32_t phpm_reg; 1618 1619 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1620 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1621 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1622 } 1623 1624 igb_dev_free_queues(dev); 1625 1626 if (intr_handle->intr_vec) { 1627 rte_free(intr_handle->intr_vec); 1628 intr_handle->intr_vec = NULL; 1629 } 1630 1631 memset(&link, 0, sizeof(link)); 1632 rte_igb_dev_atomic_write_link_status(dev, &link); 1633 } 1634 1635 static int 1636 igb_get_rx_buffer_size(struct e1000_hw *hw) 1637 { 1638 uint32_t rx_buf_size; 1639 if (hw->mac.type == e1000_82576) { 1640 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10; 1641 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) { 1642 /* PBS needs to be translated according to a lookup table */ 1643 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf); 1644 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size); 1645 rx_buf_size = (rx_buf_size << 10); 1646 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { 1647 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10; 1648 } else { 1649 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10; 1650 } 1651 1652 return rx_buf_size; 1653 } 1654 1655 /********************************************************************* 1656 * 1657 * Initialize the hardware 1658 * 1659 **********************************************************************/ 1660 static int 1661 igb_hardware_init(struct e1000_hw *hw) 1662 { 1663 uint32_t rx_buf_size; 1664 int diag; 1665 1666 /* Let the firmware know the OS is in control */ 1667 igb_hw_control_acquire(hw); 1668 1669 /* 1670 * These parameters control the automatic generation (Tx) and 1671 * response (Rx) to Ethernet PAUSE frames. 1672 * - High water mark should allow for at least two standard size (1518) 1673 * frames to be received after sending an XOFF. 1674 * - Low water mark works best when it is very near the high water mark. 1675 * This allows the receiver to restart by sending XON when it has 1676 * drained a bit. Here we use an arbitrary value of 1500 which will 1677 * restart after one full frame is pulled from the buffer. There 1678 * could be several smaller frames in the buffer and if so they will 1679 * not trigger the XON until their total number reduces the buffer 1680 * by 1500. 1681 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1682 */ 1683 rx_buf_size = igb_get_rx_buffer_size(hw); 1684 1685 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2); 1686 hw->fc.low_water = hw->fc.high_water - 1500; 1687 hw->fc.pause_time = IGB_FC_PAUSE_TIME; 1688 hw->fc.send_xon = 1; 1689 1690 /* Set Flow control, use the tunable location if sane */ 1691 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4)) 1692 hw->fc.requested_mode = igb_fc_setting; 1693 else 1694 hw->fc.requested_mode = e1000_fc_none; 1695 1696 /* Issue a global reset */ 1697 igb_pf_reset_hw(hw); 1698 E1000_WRITE_REG(hw, E1000_WUC, 0); 1699 1700 diag = e1000_init_hw(hw); 1701 if (diag < 0) 1702 return diag; 1703 1704 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN); 1705 e1000_get_phy_info(hw); 1706 e1000_check_for_link(hw); 1707 1708 return 0; 1709 } 1710 1711 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */ 1712 static void 1713 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats) 1714 { 1715 int pause_frames; 1716 1717 uint64_t old_gprc = stats->gprc; 1718 uint64_t old_gptc = stats->gptc; 1719 uint64_t old_tpr = stats->tpr; 1720 uint64_t old_tpt = stats->tpt; 1721 uint64_t old_rpthc = stats->rpthc; 1722 uint64_t old_hgptc = stats->hgptc; 1723 1724 if(hw->phy.media_type == e1000_media_type_copper || 1725 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 1726 stats->symerrs += 1727 E1000_READ_REG(hw,E1000_SYMERRS); 1728 stats->sec += E1000_READ_REG(hw, E1000_SEC); 1729 } 1730 1731 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS); 1732 stats->mpc += E1000_READ_REG(hw, E1000_MPC); 1733 stats->scc += E1000_READ_REG(hw, E1000_SCC); 1734 stats->ecol += E1000_READ_REG(hw, E1000_ECOL); 1735 1736 stats->mcc += E1000_READ_REG(hw, E1000_MCC); 1737 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL); 1738 stats->colc += E1000_READ_REG(hw, E1000_COLC); 1739 stats->dc += E1000_READ_REG(hw, E1000_DC); 1740 stats->rlec += E1000_READ_REG(hw, E1000_RLEC); 1741 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC); 1742 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC); 1743 /* 1744 ** For watchdog management we need to know if we have been 1745 ** paused during the last interval, so capture that here. 1746 */ 1747 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC); 1748 stats->xoffrxc += pause_frames; 1749 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC); 1750 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC); 1751 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64); 1752 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127); 1753 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255); 1754 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511); 1755 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023); 1756 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522); 1757 stats->gprc += E1000_READ_REG(hw, E1000_GPRC); 1758 stats->bprc += E1000_READ_REG(hw, E1000_BPRC); 1759 stats->mprc += E1000_READ_REG(hw, E1000_MPRC); 1760 stats->gptc += E1000_READ_REG(hw, E1000_GPTC); 1761 1762 /* For the 64-bit byte counters the low dword must be read first. */ 1763 /* Both registers clear on the read of the high dword */ 1764 1765 /* Workaround CRC bytes included in size, take away 4 bytes/packet */ 1766 stats->gorc += E1000_READ_REG(hw, E1000_GORCL); 1767 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32); 1768 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN; 1769 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL); 1770 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32); 1771 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN; 1772 1773 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC); 1774 stats->ruc += E1000_READ_REG(hw, E1000_RUC); 1775 stats->rfc += E1000_READ_REG(hw, E1000_RFC); 1776 stats->roc += E1000_READ_REG(hw, E1000_ROC); 1777 stats->rjc += E1000_READ_REG(hw, E1000_RJC); 1778 1779 stats->tpr += E1000_READ_REG(hw, E1000_TPR); 1780 stats->tpt += E1000_READ_REG(hw, E1000_TPT); 1781 1782 stats->tor += E1000_READ_REG(hw, E1000_TORL); 1783 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32); 1784 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN; 1785 stats->tot += E1000_READ_REG(hw, E1000_TOTL); 1786 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32); 1787 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN; 1788 1789 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64); 1790 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127); 1791 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255); 1792 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511); 1793 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023); 1794 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522); 1795 stats->mptc += E1000_READ_REG(hw, E1000_MPTC); 1796 stats->bptc += E1000_READ_REG(hw, E1000_BPTC); 1797 1798 /* Interrupt Counts */ 1799 1800 stats->iac += E1000_READ_REG(hw, E1000_IAC); 1801 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC); 1802 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC); 1803 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC); 1804 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC); 1805 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC); 1806 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC); 1807 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC); 1808 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC); 1809 1810 /* Host to Card Statistics */ 1811 1812 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC); 1813 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC); 1814 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC); 1815 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC); 1816 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC); 1817 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC); 1818 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC); 1819 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL); 1820 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32); 1821 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN; 1822 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL); 1823 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32); 1824 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN; 1825 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS); 1826 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC); 1827 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC); 1828 1829 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC); 1830 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC); 1831 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS); 1832 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR); 1833 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC); 1834 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC); 1835 } 1836 1837 static int 1838 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats) 1839 { 1840 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1841 struct e1000_hw_stats *stats = 1842 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1843 1844 igb_read_stats_registers(hw, stats); 1845 1846 if (rte_stats == NULL) 1847 return -EINVAL; 1848 1849 /* Rx Errors */ 1850 rte_stats->imissed = stats->mpc; 1851 rte_stats->ierrors = stats->crcerrs + 1852 stats->rlec + stats->ruc + stats->roc + 1853 stats->rxerrc + stats->algnerrc + stats->cexterr; 1854 1855 /* Tx Errors */ 1856 rte_stats->oerrors = stats->ecol + stats->latecol; 1857 1858 rte_stats->ipackets = stats->gprc; 1859 rte_stats->opackets = stats->gptc; 1860 rte_stats->ibytes = stats->gorc; 1861 rte_stats->obytes = stats->gotc; 1862 return 0; 1863 } 1864 1865 static void 1866 eth_igb_stats_reset(struct rte_eth_dev *dev) 1867 { 1868 struct e1000_hw_stats *hw_stats = 1869 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1870 1871 /* HW registers are cleared on read */ 1872 eth_igb_stats_get(dev, NULL); 1873 1874 /* Reset software totals */ 1875 memset(hw_stats, 0, sizeof(*hw_stats)); 1876 } 1877 1878 static void 1879 eth_igb_xstats_reset(struct rte_eth_dev *dev) 1880 { 1881 struct e1000_hw_stats *stats = 1882 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1883 1884 /* HW registers are cleared on read */ 1885 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS); 1886 1887 /* Reset software totals */ 1888 memset(stats, 0, sizeof(*stats)); 1889 } 1890 1891 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1892 struct rte_eth_xstat_name *xstats_names, 1893 __rte_unused unsigned int size) 1894 { 1895 unsigned i; 1896 1897 if (xstats_names == NULL) 1898 return IGB_NB_XSTATS; 1899 1900 /* Note: limit checked in rte_eth_xstats_names() */ 1901 1902 for (i = 0; i < IGB_NB_XSTATS; i++) { 1903 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name), 1904 "%s", rte_igb_stats_strings[i].name); 1905 } 1906 1907 return IGB_NB_XSTATS; 1908 } 1909 1910 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev, 1911 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 1912 unsigned int limit) 1913 { 1914 unsigned int i; 1915 1916 if (!ids) { 1917 if (xstats_names == NULL) 1918 return IGB_NB_XSTATS; 1919 1920 for (i = 0; i < IGB_NB_XSTATS; i++) 1921 snprintf(xstats_names[i].name, 1922 sizeof(xstats_names[i].name), 1923 "%s", rte_igb_stats_strings[i].name); 1924 1925 return IGB_NB_XSTATS; 1926 1927 } else { 1928 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS]; 1929 1930 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 1931 IGB_NB_XSTATS); 1932 1933 for (i = 0; i < limit; i++) { 1934 if (ids[i] >= IGB_NB_XSTATS) { 1935 PMD_INIT_LOG(ERR, "id value isn't valid"); 1936 return -1; 1937 } 1938 strcpy(xstats_names[i].name, 1939 xstats_names_copy[ids[i]].name); 1940 } 1941 return limit; 1942 } 1943 } 1944 1945 static int 1946 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1947 unsigned n) 1948 { 1949 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1950 struct e1000_hw_stats *hw_stats = 1951 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1952 unsigned i; 1953 1954 if (n < IGB_NB_XSTATS) 1955 return IGB_NB_XSTATS; 1956 1957 igb_read_stats_registers(hw, hw_stats); 1958 1959 /* If this is a reset xstats is NULL, and we have cleared the 1960 * registers by reading them. 1961 */ 1962 if (!xstats) 1963 return 0; 1964 1965 /* Extended stats */ 1966 for (i = 0; i < IGB_NB_XSTATS; i++) { 1967 xstats[i].id = i; 1968 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 1969 rte_igb_stats_strings[i].offset); 1970 } 1971 1972 return IGB_NB_XSTATS; 1973 } 1974 1975 static int 1976 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1977 uint64_t *values, unsigned int n) 1978 { 1979 unsigned int i; 1980 1981 if (!ids) { 1982 struct e1000_hw *hw = 1983 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1984 struct e1000_hw_stats *hw_stats = 1985 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 1986 1987 if (n < IGB_NB_XSTATS) 1988 return IGB_NB_XSTATS; 1989 1990 igb_read_stats_registers(hw, hw_stats); 1991 1992 /* If this is a reset xstats is NULL, and we have cleared the 1993 * registers by reading them. 1994 */ 1995 if (!values) 1996 return 0; 1997 1998 /* Extended stats */ 1999 for (i = 0; i < IGB_NB_XSTATS; i++) 2000 values[i] = *(uint64_t *)(((char *)hw_stats) + 2001 rte_igb_stats_strings[i].offset); 2002 2003 return IGB_NB_XSTATS; 2004 2005 } else { 2006 uint64_t values_copy[IGB_NB_XSTATS]; 2007 2008 eth_igb_xstats_get_by_id(dev, NULL, values_copy, 2009 IGB_NB_XSTATS); 2010 2011 for (i = 0; i < n; i++) { 2012 if (ids[i] >= IGB_NB_XSTATS) { 2013 PMD_INIT_LOG(ERR, "id value isn't valid"); 2014 return -1; 2015 } 2016 values[i] = values_copy[ids[i]]; 2017 } 2018 return n; 2019 } 2020 } 2021 2022 static void 2023 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats) 2024 { 2025 /* Good Rx packets, include VF loopback */ 2026 UPDATE_VF_STAT(E1000_VFGPRC, 2027 hw_stats->last_gprc, hw_stats->gprc); 2028 2029 /* Good Rx octets, include VF loopback */ 2030 UPDATE_VF_STAT(E1000_VFGORC, 2031 hw_stats->last_gorc, hw_stats->gorc); 2032 2033 /* Good Tx packets, include VF loopback */ 2034 UPDATE_VF_STAT(E1000_VFGPTC, 2035 hw_stats->last_gptc, hw_stats->gptc); 2036 2037 /* Good Tx octets, include VF loopback */ 2038 UPDATE_VF_STAT(E1000_VFGOTC, 2039 hw_stats->last_gotc, hw_stats->gotc); 2040 2041 /* Rx Multicst packets */ 2042 UPDATE_VF_STAT(E1000_VFMPRC, 2043 hw_stats->last_mprc, hw_stats->mprc); 2044 2045 /* Good Rx loopback packets */ 2046 UPDATE_VF_STAT(E1000_VFGPRLBC, 2047 hw_stats->last_gprlbc, hw_stats->gprlbc); 2048 2049 /* Good Rx loopback octets */ 2050 UPDATE_VF_STAT(E1000_VFGORLBC, 2051 hw_stats->last_gorlbc, hw_stats->gorlbc); 2052 2053 /* Good Tx loopback packets */ 2054 UPDATE_VF_STAT(E1000_VFGPTLBC, 2055 hw_stats->last_gptlbc, hw_stats->gptlbc); 2056 2057 /* Good Tx loopback octets */ 2058 UPDATE_VF_STAT(E1000_VFGOTLBC, 2059 hw_stats->last_gotlbc, hw_stats->gotlbc); 2060 } 2061 2062 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 2063 struct rte_eth_xstat_name *xstats_names, 2064 __rte_unused unsigned limit) 2065 { 2066 unsigned i; 2067 2068 if (xstats_names != NULL) 2069 for (i = 0; i < IGBVF_NB_XSTATS; i++) { 2070 snprintf(xstats_names[i].name, 2071 sizeof(xstats_names[i].name), "%s", 2072 rte_igbvf_stats_strings[i].name); 2073 } 2074 return IGBVF_NB_XSTATS; 2075 } 2076 2077 static int 2078 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 2079 unsigned n) 2080 { 2081 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2082 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *) 2083 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 2084 unsigned i; 2085 2086 if (n < IGBVF_NB_XSTATS) 2087 return IGBVF_NB_XSTATS; 2088 2089 igbvf_read_stats_registers(hw, hw_stats); 2090 2091 if (!xstats) 2092 return 0; 2093 2094 for (i = 0; i < IGBVF_NB_XSTATS; i++) { 2095 xstats[i].id = i; 2096 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 2097 rte_igbvf_stats_strings[i].offset); 2098 } 2099 2100 return IGBVF_NB_XSTATS; 2101 } 2102 2103 static int 2104 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats) 2105 { 2106 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2107 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *) 2108 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 2109 2110 igbvf_read_stats_registers(hw, hw_stats); 2111 2112 if (rte_stats == NULL) 2113 return -EINVAL; 2114 2115 rte_stats->ipackets = hw_stats->gprc; 2116 rte_stats->ibytes = hw_stats->gorc; 2117 rte_stats->opackets = hw_stats->gptc; 2118 rte_stats->obytes = hw_stats->gotc; 2119 return 0; 2120 } 2121 2122 static void 2123 eth_igbvf_stats_reset(struct rte_eth_dev *dev) 2124 { 2125 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*) 2126 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 2127 2128 /* Sync HW register to the last stats */ 2129 eth_igbvf_stats_get(dev, NULL); 2130 2131 /* reset HW current stats*/ 2132 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) - 2133 offsetof(struct e1000_vf_stats, gprc)); 2134 } 2135 2136 static int 2137 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 2138 size_t fw_size) 2139 { 2140 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2141 struct e1000_fw_version fw; 2142 int ret; 2143 2144 e1000_get_fw_version(hw, &fw); 2145 2146 switch (hw->mac.type) { 2147 case e1000_i210: 2148 case e1000_i211: 2149 if (!(e1000_get_flash_presence_i210(hw))) { 2150 ret = snprintf(fw_version, fw_size, 2151 "%2d.%2d-%d", 2152 fw.invm_major, fw.invm_minor, 2153 fw.invm_img_type); 2154 break; 2155 } 2156 /* fall through */ 2157 default: 2158 /* if option rom is valid, display its version too */ 2159 if (fw.or_valid) { 2160 ret = snprintf(fw_version, fw_size, 2161 "%d.%d, 0x%08x, %d.%d.%d", 2162 fw.eep_major, fw.eep_minor, fw.etrack_id, 2163 fw.or_major, fw.or_build, fw.or_patch); 2164 /* no option rom */ 2165 } else { 2166 if (fw.etrack_id != 0X0000) { 2167 ret = snprintf(fw_version, fw_size, 2168 "%d.%d, 0x%08x", 2169 fw.eep_major, fw.eep_minor, 2170 fw.etrack_id); 2171 } else { 2172 ret = snprintf(fw_version, fw_size, 2173 "%d.%d.%d", 2174 fw.eep_major, fw.eep_minor, 2175 fw.eep_build); 2176 } 2177 } 2178 break; 2179 } 2180 2181 ret += 1; /* add the size of '\0' */ 2182 if (fw_size < (u32)ret) 2183 return ret; 2184 else 2185 return 0; 2186 } 2187 2188 static void 2189 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2190 { 2191 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2192 2193 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2194 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */ 2195 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */ 2196 dev_info->max_mac_addrs = hw->mac.rar_entry_count; 2197 dev_info->rx_offload_capa = 2198 DEV_RX_OFFLOAD_VLAN_STRIP | 2199 DEV_RX_OFFLOAD_IPV4_CKSUM | 2200 DEV_RX_OFFLOAD_UDP_CKSUM | 2201 DEV_RX_OFFLOAD_TCP_CKSUM; 2202 dev_info->tx_offload_capa = 2203 DEV_TX_OFFLOAD_VLAN_INSERT | 2204 DEV_TX_OFFLOAD_IPV4_CKSUM | 2205 DEV_TX_OFFLOAD_UDP_CKSUM | 2206 DEV_TX_OFFLOAD_TCP_CKSUM | 2207 DEV_TX_OFFLOAD_SCTP_CKSUM | 2208 DEV_TX_OFFLOAD_TCP_TSO; 2209 2210 switch (hw->mac.type) { 2211 case e1000_82575: 2212 dev_info->max_rx_queues = 4; 2213 dev_info->max_tx_queues = 4; 2214 dev_info->max_vmdq_pools = 0; 2215 break; 2216 2217 case e1000_82576: 2218 dev_info->max_rx_queues = 16; 2219 dev_info->max_tx_queues = 16; 2220 dev_info->max_vmdq_pools = ETH_8_POOLS; 2221 dev_info->vmdq_queue_num = 16; 2222 break; 2223 2224 case e1000_82580: 2225 dev_info->max_rx_queues = 8; 2226 dev_info->max_tx_queues = 8; 2227 dev_info->max_vmdq_pools = ETH_8_POOLS; 2228 dev_info->vmdq_queue_num = 8; 2229 break; 2230 2231 case e1000_i350: 2232 dev_info->max_rx_queues = 8; 2233 dev_info->max_tx_queues = 8; 2234 dev_info->max_vmdq_pools = ETH_8_POOLS; 2235 dev_info->vmdq_queue_num = 8; 2236 break; 2237 2238 case e1000_i354: 2239 dev_info->max_rx_queues = 8; 2240 dev_info->max_tx_queues = 8; 2241 break; 2242 2243 case e1000_i210: 2244 dev_info->max_rx_queues = 4; 2245 dev_info->max_tx_queues = 4; 2246 dev_info->max_vmdq_pools = 0; 2247 break; 2248 2249 case e1000_i211: 2250 dev_info->max_rx_queues = 2; 2251 dev_info->max_tx_queues = 2; 2252 dev_info->max_vmdq_pools = 0; 2253 break; 2254 2255 default: 2256 /* Should not happen */ 2257 break; 2258 } 2259 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t); 2260 dev_info->reta_size = ETH_RSS_RETA_SIZE_128; 2261 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL; 2262 2263 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2264 .rx_thresh = { 2265 .pthresh = IGB_DEFAULT_RX_PTHRESH, 2266 .hthresh = IGB_DEFAULT_RX_HTHRESH, 2267 .wthresh = IGB_DEFAULT_RX_WTHRESH, 2268 }, 2269 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH, 2270 .rx_drop_en = 0, 2271 }; 2272 2273 dev_info->default_txconf = (struct rte_eth_txconf) { 2274 .tx_thresh = { 2275 .pthresh = IGB_DEFAULT_TX_PTHRESH, 2276 .hthresh = IGB_DEFAULT_TX_HTHRESH, 2277 .wthresh = IGB_DEFAULT_TX_WTHRESH, 2278 }, 2279 .txq_flags = 0, 2280 }; 2281 2282 dev_info->rx_desc_lim = rx_desc_lim; 2283 dev_info->tx_desc_lim = tx_desc_lim; 2284 2285 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M | 2286 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M | 2287 ETH_LINK_SPEED_1G; 2288 } 2289 2290 static const uint32_t * 2291 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev) 2292 { 2293 static const uint32_t ptypes[] = { 2294 /* refers to igb_rxd_pkt_info_to_pkt_type() */ 2295 RTE_PTYPE_L2_ETHER, 2296 RTE_PTYPE_L3_IPV4, 2297 RTE_PTYPE_L3_IPV4_EXT, 2298 RTE_PTYPE_L3_IPV6, 2299 RTE_PTYPE_L3_IPV6_EXT, 2300 RTE_PTYPE_L4_TCP, 2301 RTE_PTYPE_L4_UDP, 2302 RTE_PTYPE_L4_SCTP, 2303 RTE_PTYPE_TUNNEL_IP, 2304 RTE_PTYPE_INNER_L3_IPV6, 2305 RTE_PTYPE_INNER_L3_IPV6_EXT, 2306 RTE_PTYPE_INNER_L4_TCP, 2307 RTE_PTYPE_INNER_L4_UDP, 2308 RTE_PTYPE_UNKNOWN 2309 }; 2310 2311 if (dev->rx_pkt_burst == eth_igb_recv_pkts || 2312 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts) 2313 return ptypes; 2314 return NULL; 2315 } 2316 2317 static void 2318 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2319 { 2320 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2321 2322 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2323 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */ 2324 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */ 2325 dev_info->max_mac_addrs = hw->mac.rar_entry_count; 2326 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | 2327 DEV_RX_OFFLOAD_IPV4_CKSUM | 2328 DEV_RX_OFFLOAD_UDP_CKSUM | 2329 DEV_RX_OFFLOAD_TCP_CKSUM; 2330 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | 2331 DEV_TX_OFFLOAD_IPV4_CKSUM | 2332 DEV_TX_OFFLOAD_UDP_CKSUM | 2333 DEV_TX_OFFLOAD_TCP_CKSUM | 2334 DEV_TX_OFFLOAD_SCTP_CKSUM | 2335 DEV_TX_OFFLOAD_TCP_TSO; 2336 switch (hw->mac.type) { 2337 case e1000_vfadapt: 2338 dev_info->max_rx_queues = 2; 2339 dev_info->max_tx_queues = 2; 2340 break; 2341 case e1000_vfadapt_i350: 2342 dev_info->max_rx_queues = 1; 2343 dev_info->max_tx_queues = 1; 2344 break; 2345 default: 2346 /* Should not happen */ 2347 break; 2348 } 2349 2350 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2351 .rx_thresh = { 2352 .pthresh = IGB_DEFAULT_RX_PTHRESH, 2353 .hthresh = IGB_DEFAULT_RX_HTHRESH, 2354 .wthresh = IGB_DEFAULT_RX_WTHRESH, 2355 }, 2356 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH, 2357 .rx_drop_en = 0, 2358 }; 2359 2360 dev_info->default_txconf = (struct rte_eth_txconf) { 2361 .tx_thresh = { 2362 .pthresh = IGB_DEFAULT_TX_PTHRESH, 2363 .hthresh = IGB_DEFAULT_TX_HTHRESH, 2364 .wthresh = IGB_DEFAULT_TX_WTHRESH, 2365 }, 2366 .txq_flags = 0, 2367 }; 2368 2369 dev_info->rx_desc_lim = rx_desc_lim; 2370 dev_info->tx_desc_lim = tx_desc_lim; 2371 } 2372 2373 /* return 0 means link status changed, -1 means not changed */ 2374 static int 2375 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete) 2376 { 2377 struct e1000_hw *hw = 2378 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2379 struct rte_eth_link link, old; 2380 int link_check, count; 2381 2382 link_check = 0; 2383 hw->mac.get_link_status = 1; 2384 2385 /* possible wait-to-complete in up to 9 seconds */ 2386 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) { 2387 /* Read the real link status */ 2388 switch (hw->phy.media_type) { 2389 case e1000_media_type_copper: 2390 /* Do the work to read phy */ 2391 e1000_check_for_link(hw); 2392 link_check = !hw->mac.get_link_status; 2393 break; 2394 2395 case e1000_media_type_fiber: 2396 e1000_check_for_link(hw); 2397 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 2398 E1000_STATUS_LU); 2399 break; 2400 2401 case e1000_media_type_internal_serdes: 2402 e1000_check_for_link(hw); 2403 link_check = hw->mac.serdes_has_link; 2404 break; 2405 2406 /* VF device is type_unknown */ 2407 case e1000_media_type_unknown: 2408 eth_igbvf_link_update(hw); 2409 link_check = !hw->mac.get_link_status; 2410 break; 2411 2412 default: 2413 break; 2414 } 2415 if (link_check || wait_to_complete == 0) 2416 break; 2417 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL); 2418 } 2419 memset(&link, 0, sizeof(link)); 2420 rte_igb_dev_atomic_read_link_status(dev, &link); 2421 old = link; 2422 2423 /* Now we check if a transition has happened */ 2424 if (link_check) { 2425 uint16_t duplex, speed; 2426 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 2427 link.link_duplex = (duplex == FULL_DUPLEX) ? 2428 ETH_LINK_FULL_DUPLEX : 2429 ETH_LINK_HALF_DUPLEX; 2430 link.link_speed = speed; 2431 link.link_status = ETH_LINK_UP; 2432 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2433 ETH_LINK_SPEED_FIXED); 2434 } else if (!link_check) { 2435 link.link_speed = 0; 2436 link.link_duplex = ETH_LINK_HALF_DUPLEX; 2437 link.link_status = ETH_LINK_DOWN; 2438 link.link_autoneg = ETH_LINK_FIXED; 2439 } 2440 rte_igb_dev_atomic_write_link_status(dev, &link); 2441 2442 /* not changed */ 2443 if (old.link_status == link.link_status) 2444 return -1; 2445 2446 /* changed */ 2447 return 0; 2448 } 2449 2450 /* 2451 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit. 2452 * For ASF and Pass Through versions of f/w this means 2453 * that the driver is loaded. 2454 */ 2455 static void 2456 igb_hw_control_acquire(struct e1000_hw *hw) 2457 { 2458 uint32_t ctrl_ext; 2459 2460 /* Let firmware know the driver has taken over */ 2461 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2462 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2463 } 2464 2465 /* 2466 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit. 2467 * For ASF and Pass Through versions of f/w this means that the 2468 * driver is no longer loaded. 2469 */ 2470 static void 2471 igb_hw_control_release(struct e1000_hw *hw) 2472 { 2473 uint32_t ctrl_ext; 2474 2475 /* Let firmware taken over control of h/w */ 2476 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2477 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 2478 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2479 } 2480 2481 /* 2482 * Bit of a misnomer, what this really means is 2483 * to enable OS management of the system... aka 2484 * to disable special hardware management features. 2485 */ 2486 static void 2487 igb_init_manageability(struct e1000_hw *hw) 2488 { 2489 if (e1000_enable_mng_pass_thru(hw)) { 2490 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H); 2491 uint32_t manc = E1000_READ_REG(hw, E1000_MANC); 2492 2493 /* disable hardware interception of ARP */ 2494 manc &= ~(E1000_MANC_ARP_EN); 2495 2496 /* enable receiving management packets to the host */ 2497 manc |= E1000_MANC_EN_MNG2HOST; 2498 manc2h |= 1 << 5; /* Mng Port 623 */ 2499 manc2h |= 1 << 6; /* Mng Port 664 */ 2500 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h); 2501 E1000_WRITE_REG(hw, E1000_MANC, manc); 2502 } 2503 } 2504 2505 static void 2506 igb_release_manageability(struct e1000_hw *hw) 2507 { 2508 if (e1000_enable_mng_pass_thru(hw)) { 2509 uint32_t manc = E1000_READ_REG(hw, E1000_MANC); 2510 2511 manc |= E1000_MANC_ARP_EN; 2512 manc &= ~E1000_MANC_EN_MNG2HOST; 2513 2514 E1000_WRITE_REG(hw, E1000_MANC, manc); 2515 } 2516 } 2517 2518 static void 2519 eth_igb_promiscuous_enable(struct rte_eth_dev *dev) 2520 { 2521 struct e1000_hw *hw = 2522 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2523 uint32_t rctl; 2524 2525 rctl = E1000_READ_REG(hw, E1000_RCTL); 2526 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2527 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2528 } 2529 2530 static void 2531 eth_igb_promiscuous_disable(struct rte_eth_dev *dev) 2532 { 2533 struct e1000_hw *hw = 2534 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2535 uint32_t rctl; 2536 2537 rctl = E1000_READ_REG(hw, E1000_RCTL); 2538 rctl &= (~E1000_RCTL_UPE); 2539 if (dev->data->all_multicast == 1) 2540 rctl |= E1000_RCTL_MPE; 2541 else 2542 rctl &= (~E1000_RCTL_MPE); 2543 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2544 } 2545 2546 static void 2547 eth_igb_allmulticast_enable(struct rte_eth_dev *dev) 2548 { 2549 struct e1000_hw *hw = 2550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2551 uint32_t rctl; 2552 2553 rctl = E1000_READ_REG(hw, E1000_RCTL); 2554 rctl |= E1000_RCTL_MPE; 2555 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2556 } 2557 2558 static void 2559 eth_igb_allmulticast_disable(struct rte_eth_dev *dev) 2560 { 2561 struct e1000_hw *hw = 2562 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2563 uint32_t rctl; 2564 2565 if (dev->data->promiscuous == 1) 2566 return; /* must remain in all_multicast mode */ 2567 rctl = E1000_READ_REG(hw, E1000_RCTL); 2568 rctl &= (~E1000_RCTL_MPE); 2569 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2570 } 2571 2572 static int 2573 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 2574 { 2575 struct e1000_hw *hw = 2576 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2577 struct e1000_vfta * shadow_vfta = 2578 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 2579 uint32_t vfta; 2580 uint32_t vid_idx; 2581 uint32_t vid_bit; 2582 2583 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) & 2584 E1000_VFTA_ENTRY_MASK); 2585 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK)); 2586 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx); 2587 if (on) 2588 vfta |= vid_bit; 2589 else 2590 vfta &= ~vid_bit; 2591 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta); 2592 2593 /* update local VFTA copy */ 2594 shadow_vfta->vfta[vid_idx] = vfta; 2595 2596 return 0; 2597 } 2598 2599 static int 2600 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, 2601 enum rte_vlan_type vlan_type, 2602 uint16_t tpid) 2603 { 2604 struct e1000_hw *hw = 2605 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2606 uint32_t reg, qinq; 2607 2608 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT); 2609 qinq &= E1000_CTRL_EXT_EXT_VLAN; 2610 2611 /* only outer TPID of double VLAN can be configured*/ 2612 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) { 2613 reg = E1000_READ_REG(hw, E1000_VET); 2614 reg = (reg & (~E1000_VET_VET_EXT)) | 2615 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT); 2616 E1000_WRITE_REG(hw, E1000_VET, reg); 2617 2618 return 0; 2619 } 2620 2621 /* all other TPID values are read-only*/ 2622 PMD_DRV_LOG(ERR, "Not supported"); 2623 2624 return -ENOTSUP; 2625 } 2626 2627 static void 2628 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev) 2629 { 2630 struct e1000_hw *hw = 2631 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2632 uint32_t reg; 2633 2634 /* Filter Table Disable */ 2635 reg = E1000_READ_REG(hw, E1000_RCTL); 2636 reg &= ~E1000_RCTL_CFIEN; 2637 reg &= ~E1000_RCTL_VFE; 2638 E1000_WRITE_REG(hw, E1000_RCTL, reg); 2639 } 2640 2641 static void 2642 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2643 { 2644 struct e1000_hw *hw = 2645 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2646 struct e1000_vfta * shadow_vfta = 2647 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 2648 uint32_t reg; 2649 int i; 2650 2651 /* Filter Table Enable, CFI not used for packet acceptance */ 2652 reg = E1000_READ_REG(hw, E1000_RCTL); 2653 reg &= ~E1000_RCTL_CFIEN; 2654 reg |= E1000_RCTL_VFE; 2655 E1000_WRITE_REG(hw, E1000_RCTL, reg); 2656 2657 /* restore VFTA table */ 2658 for (i = 0; i < IGB_VFTA_SIZE; i++) 2659 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]); 2660 } 2661 2662 static void 2663 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev) 2664 { 2665 struct e1000_hw *hw = 2666 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2667 uint32_t reg; 2668 2669 /* VLAN Mode Disable */ 2670 reg = E1000_READ_REG(hw, E1000_CTRL); 2671 reg &= ~E1000_CTRL_VME; 2672 E1000_WRITE_REG(hw, E1000_CTRL, reg); 2673 } 2674 2675 static void 2676 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev) 2677 { 2678 struct e1000_hw *hw = 2679 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2680 uint32_t reg; 2681 2682 /* VLAN Mode Enable */ 2683 reg = E1000_READ_REG(hw, E1000_CTRL); 2684 reg |= E1000_CTRL_VME; 2685 E1000_WRITE_REG(hw, E1000_CTRL, reg); 2686 } 2687 2688 static void 2689 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2690 { 2691 struct e1000_hw *hw = 2692 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2693 uint32_t reg; 2694 2695 /* CTRL_EXT: Extended VLAN */ 2696 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2697 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN; 2698 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2699 2700 /* Update maximum packet length */ 2701 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) 2702 E1000_WRITE_REG(hw, E1000_RLPML, 2703 dev->data->dev_conf.rxmode.max_rx_pkt_len + 2704 VLAN_TAG_SIZE); 2705 } 2706 2707 static void 2708 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2709 { 2710 struct e1000_hw *hw = 2711 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2712 uint32_t reg; 2713 2714 /* CTRL_EXT: Extended VLAN */ 2715 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2716 reg |= E1000_CTRL_EXT_EXTEND_VLAN; 2717 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2718 2719 /* Update maximum packet length */ 2720 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) 2721 E1000_WRITE_REG(hw, E1000_RLPML, 2722 dev->data->dev_conf.rxmode.max_rx_pkt_len + 2723 2 * VLAN_TAG_SIZE); 2724 } 2725 2726 static int 2727 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2728 { 2729 if(mask & ETH_VLAN_STRIP_MASK){ 2730 if (dev->data->dev_conf.rxmode.hw_vlan_strip) 2731 igb_vlan_hw_strip_enable(dev); 2732 else 2733 igb_vlan_hw_strip_disable(dev); 2734 } 2735 2736 if(mask & ETH_VLAN_FILTER_MASK){ 2737 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 2738 igb_vlan_hw_filter_enable(dev); 2739 else 2740 igb_vlan_hw_filter_disable(dev); 2741 } 2742 2743 if(mask & ETH_VLAN_EXTEND_MASK){ 2744 if (dev->data->dev_conf.rxmode.hw_vlan_extend) 2745 igb_vlan_hw_extend_enable(dev); 2746 else 2747 igb_vlan_hw_extend_disable(dev); 2748 } 2749 2750 return 0; 2751 } 2752 2753 2754 /** 2755 * It enables the interrupt mask and then enable the interrupt. 2756 * 2757 * @param dev 2758 * Pointer to struct rte_eth_dev. 2759 * @param on 2760 * Enable or Disable 2761 * 2762 * @return 2763 * - On success, zero. 2764 * - On failure, a negative value. 2765 */ 2766 static int 2767 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 2768 { 2769 struct e1000_interrupt *intr = 2770 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2771 2772 if (on) 2773 intr->mask |= E1000_ICR_LSC; 2774 else 2775 intr->mask &= ~E1000_ICR_LSC; 2776 2777 return 0; 2778 } 2779 2780 /* It clears the interrupt causes and enables the interrupt. 2781 * It will be called once only during nic initialized. 2782 * 2783 * @param dev 2784 * Pointer to struct rte_eth_dev. 2785 * 2786 * @return 2787 * - On success, zero. 2788 * - On failure, a negative value. 2789 */ 2790 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev) 2791 { 2792 uint32_t mask, regval; 2793 struct e1000_hw *hw = 2794 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2795 struct rte_eth_dev_info dev_info; 2796 2797 memset(&dev_info, 0, sizeof(dev_info)); 2798 eth_igb_infos_get(dev, &dev_info); 2799 2800 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues); 2801 regval = E1000_READ_REG(hw, E1000_EIMS); 2802 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); 2803 2804 return 0; 2805 } 2806 2807 /* 2808 * It reads ICR and gets interrupt causes, check it and set a bit flag 2809 * to update link status. 2810 * 2811 * @param dev 2812 * Pointer to struct rte_eth_dev. 2813 * 2814 * @return 2815 * - On success, zero. 2816 * - On failure, a negative value. 2817 */ 2818 static int 2819 eth_igb_interrupt_get_status(struct rte_eth_dev *dev) 2820 { 2821 uint32_t icr; 2822 struct e1000_hw *hw = 2823 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2824 struct e1000_interrupt *intr = 2825 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2826 2827 igb_intr_disable(hw); 2828 2829 /* read-on-clear nic registers here */ 2830 icr = E1000_READ_REG(hw, E1000_ICR); 2831 2832 intr->flags = 0; 2833 if (icr & E1000_ICR_LSC) { 2834 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE; 2835 } 2836 2837 if (icr & E1000_ICR_VMMB) 2838 intr->flags |= E1000_FLAG_MAILBOX; 2839 2840 return 0; 2841 } 2842 2843 /* 2844 * It executes link_update after knowing an interrupt is prsent. 2845 * 2846 * @param dev 2847 * Pointer to struct rte_eth_dev. 2848 * 2849 * @return 2850 * - On success, zero. 2851 * - On failure, a negative value. 2852 */ 2853 static int 2854 eth_igb_interrupt_action(struct rte_eth_dev *dev, 2855 struct rte_intr_handle *intr_handle) 2856 { 2857 struct e1000_hw *hw = 2858 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2859 struct e1000_interrupt *intr = 2860 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2861 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2862 uint32_t tctl, rctl; 2863 struct rte_eth_link link; 2864 int ret; 2865 2866 if (intr->flags & E1000_FLAG_MAILBOX) { 2867 igb_pf_mbx_process(dev); 2868 intr->flags &= ~E1000_FLAG_MAILBOX; 2869 } 2870 2871 igb_intr_enable(dev); 2872 rte_intr_enable(intr_handle); 2873 2874 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) { 2875 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE; 2876 2877 /* set get_link_status to check register later */ 2878 hw->mac.get_link_status = 1; 2879 ret = eth_igb_link_update(dev, 0); 2880 2881 /* check if link has changed */ 2882 if (ret < 0) 2883 return 0; 2884 2885 memset(&link, 0, sizeof(link)); 2886 rte_igb_dev_atomic_read_link_status(dev, &link); 2887 if (link.link_status) { 2888 PMD_INIT_LOG(INFO, 2889 " Port %d: Link Up - speed %u Mbps - %s", 2890 dev->data->port_id, 2891 (unsigned)link.link_speed, 2892 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 2893 "full-duplex" : "half-duplex"); 2894 } else { 2895 PMD_INIT_LOG(INFO, " Port %d: Link Down", 2896 dev->data->port_id); 2897 } 2898 2899 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d", 2900 pci_dev->addr.domain, 2901 pci_dev->addr.bus, 2902 pci_dev->addr.devid, 2903 pci_dev->addr.function); 2904 tctl = E1000_READ_REG(hw, E1000_TCTL); 2905 rctl = E1000_READ_REG(hw, E1000_RCTL); 2906 if (link.link_status) { 2907 /* enable Tx/Rx */ 2908 tctl |= E1000_TCTL_EN; 2909 rctl |= E1000_RCTL_EN; 2910 } else { 2911 /* disable Tx/Rx */ 2912 tctl &= ~E1000_TCTL_EN; 2913 rctl &= ~E1000_RCTL_EN; 2914 } 2915 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 2916 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2917 E1000_WRITE_FLUSH(hw); 2918 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 2919 NULL, NULL); 2920 } 2921 2922 return 0; 2923 } 2924 2925 /** 2926 * Interrupt handler which shall be registered at first. 2927 * 2928 * @param handle 2929 * Pointer to interrupt handle. 2930 * @param param 2931 * The address of parameter (struct rte_eth_dev *) regsitered before. 2932 * 2933 * @return 2934 * void 2935 */ 2936 static void 2937 eth_igb_interrupt_handler(void *param) 2938 { 2939 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 2940 2941 eth_igb_interrupt_get_status(dev); 2942 eth_igb_interrupt_action(dev, dev->intr_handle); 2943 } 2944 2945 static int 2946 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev) 2947 { 2948 uint32_t eicr; 2949 struct e1000_hw *hw = 2950 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2951 struct e1000_interrupt *intr = 2952 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2953 2954 igbvf_intr_disable(hw); 2955 2956 /* read-on-clear nic registers here */ 2957 eicr = E1000_READ_REG(hw, E1000_EICR); 2958 intr->flags = 0; 2959 2960 if (eicr == E1000_VTIVAR_MISC_MAILBOX) 2961 intr->flags |= E1000_FLAG_MAILBOX; 2962 2963 return 0; 2964 } 2965 2966 void igbvf_mbx_process(struct rte_eth_dev *dev) 2967 { 2968 struct e1000_hw *hw = 2969 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2970 struct e1000_mbx_info *mbx = &hw->mbx; 2971 u32 in_msg = 0; 2972 2973 if (mbx->ops.read(hw, &in_msg, 1, 0)) 2974 return; 2975 2976 /* PF reset VF event */ 2977 if (in_msg == E1000_PF_CONTROL_MSG) 2978 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 2979 NULL, NULL); 2980 } 2981 2982 static int 2983 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle) 2984 { 2985 struct e1000_interrupt *intr = 2986 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2987 2988 if (intr->flags & E1000_FLAG_MAILBOX) { 2989 igbvf_mbx_process(dev); 2990 intr->flags &= ~E1000_FLAG_MAILBOX; 2991 } 2992 2993 igbvf_intr_enable(dev); 2994 rte_intr_enable(intr_handle); 2995 2996 return 0; 2997 } 2998 2999 static void 3000 eth_igbvf_interrupt_handler(void *param) 3001 { 3002 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3003 3004 eth_igbvf_interrupt_get_status(dev); 3005 eth_igbvf_interrupt_action(dev, dev->intr_handle); 3006 } 3007 3008 static int 3009 eth_igb_led_on(struct rte_eth_dev *dev) 3010 { 3011 struct e1000_hw *hw; 3012 3013 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3014 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP; 3015 } 3016 3017 static int 3018 eth_igb_led_off(struct rte_eth_dev *dev) 3019 { 3020 struct e1000_hw *hw; 3021 3022 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3023 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP; 3024 } 3025 3026 static int 3027 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3028 { 3029 struct e1000_hw *hw; 3030 uint32_t ctrl; 3031 int tx_pause; 3032 int rx_pause; 3033 3034 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3035 fc_conf->pause_time = hw->fc.pause_time; 3036 fc_conf->high_water = hw->fc.high_water; 3037 fc_conf->low_water = hw->fc.low_water; 3038 fc_conf->send_xon = hw->fc.send_xon; 3039 fc_conf->autoneg = hw->mac.autoneg; 3040 3041 /* 3042 * Return rx_pause and tx_pause status according to actual setting of 3043 * the TFCE and RFCE bits in the CTRL register. 3044 */ 3045 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3046 if (ctrl & E1000_CTRL_TFCE) 3047 tx_pause = 1; 3048 else 3049 tx_pause = 0; 3050 3051 if (ctrl & E1000_CTRL_RFCE) 3052 rx_pause = 1; 3053 else 3054 rx_pause = 0; 3055 3056 if (rx_pause && tx_pause) 3057 fc_conf->mode = RTE_FC_FULL; 3058 else if (rx_pause) 3059 fc_conf->mode = RTE_FC_RX_PAUSE; 3060 else if (tx_pause) 3061 fc_conf->mode = RTE_FC_TX_PAUSE; 3062 else 3063 fc_conf->mode = RTE_FC_NONE; 3064 3065 return 0; 3066 } 3067 3068 static int 3069 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3070 { 3071 struct e1000_hw *hw; 3072 int err; 3073 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = { 3074 e1000_fc_none, 3075 e1000_fc_rx_pause, 3076 e1000_fc_tx_pause, 3077 e1000_fc_full 3078 }; 3079 uint32_t rx_buf_size; 3080 uint32_t max_high_water; 3081 uint32_t rctl; 3082 3083 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3084 if (fc_conf->autoneg != hw->mac.autoneg) 3085 return -ENOTSUP; 3086 rx_buf_size = igb_get_rx_buffer_size(hw); 3087 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3088 3089 /* At least reserve one Ethernet frame for watermark */ 3090 max_high_water = rx_buf_size - ETHER_MAX_LEN; 3091 if ((fc_conf->high_water > max_high_water) || 3092 (fc_conf->high_water < fc_conf->low_water)) { 3093 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value"); 3094 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water); 3095 return -EINVAL; 3096 } 3097 3098 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode]; 3099 hw->fc.pause_time = fc_conf->pause_time; 3100 hw->fc.high_water = fc_conf->high_water; 3101 hw->fc.low_water = fc_conf->low_water; 3102 hw->fc.send_xon = fc_conf->send_xon; 3103 3104 err = e1000_setup_link_generic(hw); 3105 if (err == E1000_SUCCESS) { 3106 3107 /* check if we want to forward MAC frames - driver doesn't have native 3108 * capability to do that, so we'll write the registers ourselves */ 3109 3110 rctl = E1000_READ_REG(hw, E1000_RCTL); 3111 3112 /* set or clear MFLCN.PMCF bit depending on configuration */ 3113 if (fc_conf->mac_ctrl_frame_fwd != 0) 3114 rctl |= E1000_RCTL_PMCF; 3115 else 3116 rctl &= ~E1000_RCTL_PMCF; 3117 3118 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3119 E1000_WRITE_FLUSH(hw); 3120 3121 return 0; 3122 } 3123 3124 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err); 3125 return -EIO; 3126 } 3127 3128 #define E1000_RAH_POOLSEL_SHIFT (18) 3129 static int 3130 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 3131 uint32_t index, uint32_t pool) 3132 { 3133 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3134 uint32_t rah; 3135 3136 e1000_rar_set(hw, mac_addr->addr_bytes, index); 3137 rah = E1000_READ_REG(hw, E1000_RAH(index)); 3138 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool)); 3139 E1000_WRITE_REG(hw, E1000_RAH(index), rah); 3140 return 0; 3141 } 3142 3143 static void 3144 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index) 3145 { 3146 uint8_t addr[ETHER_ADDR_LEN]; 3147 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3148 3149 memset(addr, 0, sizeof(addr)); 3150 3151 e1000_rar_set(hw, addr, index); 3152 } 3153 3154 static void 3155 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev, 3156 struct ether_addr *addr) 3157 { 3158 eth_igb_rar_clear(dev, 0); 3159 3160 eth_igb_rar_set(dev, (void *)addr, 0, 0); 3161 } 3162 /* 3163 * Virtual Function operations 3164 */ 3165 static void 3166 igbvf_intr_disable(struct e1000_hw *hw) 3167 { 3168 PMD_INIT_FUNC_TRACE(); 3169 3170 /* Clear interrupt mask to stop from interrupts being generated */ 3171 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF); 3172 3173 E1000_WRITE_FLUSH(hw); 3174 } 3175 3176 static void 3177 igbvf_stop_adapter(struct rte_eth_dev *dev) 3178 { 3179 u32 reg_val; 3180 u16 i; 3181 struct rte_eth_dev_info dev_info; 3182 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3183 3184 memset(&dev_info, 0, sizeof(dev_info)); 3185 eth_igbvf_infos_get(dev, &dev_info); 3186 3187 /* Clear interrupt mask to stop from interrupts being generated */ 3188 igbvf_intr_disable(hw); 3189 3190 /* Clear any pending interrupts, flush previous writes */ 3191 E1000_READ_REG(hw, E1000_EICR); 3192 3193 /* Disable the transmit unit. Each queue must be disabled. */ 3194 for (i = 0; i < dev_info.max_tx_queues; i++) 3195 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH); 3196 3197 /* Disable the receive unit by stopping each queue */ 3198 for (i = 0; i < dev_info.max_rx_queues; i++) { 3199 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3200 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE; 3201 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val); 3202 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE) 3203 ; 3204 } 3205 3206 /* flush all queues disables */ 3207 E1000_WRITE_FLUSH(hw); 3208 msec_delay(2); 3209 } 3210 3211 static int eth_igbvf_link_update(struct e1000_hw *hw) 3212 { 3213 struct e1000_mbx_info *mbx = &hw->mbx; 3214 struct e1000_mac_info *mac = &hw->mac; 3215 int ret_val = E1000_SUCCESS; 3216 3217 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf"); 3218 3219 /* 3220 * We only want to run this if there has been a rst asserted. 3221 * in this case that could mean a link change, device reset, 3222 * or a virtual function reset 3223 */ 3224 3225 /* If we were hit with a reset or timeout drop the link */ 3226 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout) 3227 mac->get_link_status = TRUE; 3228 3229 if (!mac->get_link_status) 3230 goto out; 3231 3232 /* if link status is down no point in checking to see if pf is up */ 3233 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) 3234 goto out; 3235 3236 /* if we passed all the tests above then the link is up and we no 3237 * longer need to check for link */ 3238 mac->get_link_status = FALSE; 3239 3240 out: 3241 return ret_val; 3242 } 3243 3244 3245 static int 3246 igbvf_dev_configure(struct rte_eth_dev *dev) 3247 { 3248 struct rte_eth_conf* conf = &dev->data->dev_conf; 3249 3250 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 3251 dev->data->port_id); 3252 3253 /* 3254 * VF has no ability to enable/disable HW CRC 3255 * Keep the persistent behavior the same as Host PF 3256 */ 3257 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC 3258 if (!conf->rxmode.hw_strip_crc) { 3259 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 3260 conf->rxmode.hw_strip_crc = 1; 3261 } 3262 #else 3263 if (conf->rxmode.hw_strip_crc) { 3264 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 3265 conf->rxmode.hw_strip_crc = 0; 3266 } 3267 #endif 3268 3269 return 0; 3270 } 3271 3272 static int 3273 igbvf_dev_start(struct rte_eth_dev *dev) 3274 { 3275 struct e1000_hw *hw = 3276 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3277 struct e1000_adapter *adapter = 3278 E1000_DEV_PRIVATE(dev->data->dev_private); 3279 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3280 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3281 int ret; 3282 uint32_t intr_vector = 0; 3283 3284 PMD_INIT_FUNC_TRACE(); 3285 3286 hw->mac.ops.reset_hw(hw); 3287 adapter->stopped = 0; 3288 3289 /* Set all vfta */ 3290 igbvf_set_vfta_all(dev,1); 3291 3292 eth_igbvf_tx_init(dev); 3293 3294 /* This can fail when allocating mbufs for descriptor rings */ 3295 ret = eth_igbvf_rx_init(dev); 3296 if (ret) { 3297 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 3298 igb_dev_clear_queues(dev); 3299 return ret; 3300 } 3301 3302 /* check and configure queue intr-vector mapping */ 3303 if (rte_intr_cap_multiple(intr_handle) && 3304 dev->data->dev_conf.intr_conf.rxq) { 3305 intr_vector = dev->data->nb_rx_queues; 3306 ret = rte_intr_efd_enable(intr_handle, intr_vector); 3307 if (ret) 3308 return ret; 3309 } 3310 3311 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 3312 intr_handle->intr_vec = 3313 rte_zmalloc("intr_vec", 3314 dev->data->nb_rx_queues * sizeof(int), 0); 3315 if (!intr_handle->intr_vec) { 3316 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 3317 " intr_vec", dev->data->nb_rx_queues); 3318 return -ENOMEM; 3319 } 3320 } 3321 3322 eth_igbvf_configure_msix_intr(dev); 3323 3324 /* enable uio/vfio intr/eventfd mapping */ 3325 rte_intr_enable(intr_handle); 3326 3327 /* resume enabled intr since hw reset */ 3328 igbvf_intr_enable(dev); 3329 3330 return 0; 3331 } 3332 3333 static void 3334 igbvf_dev_stop(struct rte_eth_dev *dev) 3335 { 3336 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3337 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3338 3339 PMD_INIT_FUNC_TRACE(); 3340 3341 igbvf_stop_adapter(dev); 3342 3343 /* 3344 * Clear what we set, but we still keep shadow_vfta to 3345 * restore after device starts 3346 */ 3347 igbvf_set_vfta_all(dev,0); 3348 3349 igb_dev_clear_queues(dev); 3350 3351 /* disable intr eventfd mapping */ 3352 rte_intr_disable(intr_handle); 3353 3354 /* Clean datapath event and queue/vec mapping */ 3355 rte_intr_efd_disable(intr_handle); 3356 if (intr_handle->intr_vec) { 3357 rte_free(intr_handle->intr_vec); 3358 intr_handle->intr_vec = NULL; 3359 } 3360 } 3361 3362 static void 3363 igbvf_dev_close(struct rte_eth_dev *dev) 3364 { 3365 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3366 struct e1000_adapter *adapter = 3367 E1000_DEV_PRIVATE(dev->data->dev_private); 3368 struct ether_addr addr; 3369 3370 PMD_INIT_FUNC_TRACE(); 3371 3372 e1000_reset_hw(hw); 3373 3374 igbvf_dev_stop(dev); 3375 adapter->stopped = 1; 3376 igb_dev_free_queues(dev); 3377 3378 /** 3379 * reprogram the RAR with a zero mac address, 3380 * to ensure that the VF traffic goes to the PF 3381 * after stop, close and detach of the VF. 3382 **/ 3383 3384 memset(&addr, 0, sizeof(addr)); 3385 igbvf_default_mac_addr_set(dev, &addr); 3386 } 3387 3388 static void 3389 igbvf_promiscuous_enable(struct rte_eth_dev *dev) 3390 { 3391 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3392 3393 /* Set both unicast and multicast promisc */ 3394 e1000_promisc_set_vf(hw, e1000_promisc_enabled); 3395 } 3396 3397 static void 3398 igbvf_promiscuous_disable(struct rte_eth_dev *dev) 3399 { 3400 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3401 3402 /* If in allmulticast mode leave multicast promisc */ 3403 if (dev->data->all_multicast == 1) 3404 e1000_promisc_set_vf(hw, e1000_promisc_multicast); 3405 else 3406 e1000_promisc_set_vf(hw, e1000_promisc_disabled); 3407 } 3408 3409 static void 3410 igbvf_allmulticast_enable(struct rte_eth_dev *dev) 3411 { 3412 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3413 3414 /* In promiscuous mode multicast promisc already set */ 3415 if (dev->data->promiscuous == 0) 3416 e1000_promisc_set_vf(hw, e1000_promisc_multicast); 3417 } 3418 3419 static void 3420 igbvf_allmulticast_disable(struct rte_eth_dev *dev) 3421 { 3422 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3423 3424 /* In promiscuous mode leave multicast promisc enabled */ 3425 if (dev->data->promiscuous == 0) 3426 e1000_promisc_set_vf(hw, e1000_promisc_disabled); 3427 } 3428 3429 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on) 3430 { 3431 struct e1000_mbx_info *mbx = &hw->mbx; 3432 uint32_t msgbuf[2]; 3433 s32 err; 3434 3435 /* After set vlan, vlan strip will also be enabled in igb driver*/ 3436 msgbuf[0] = E1000_VF_SET_VLAN; 3437 msgbuf[1] = vid; 3438 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */ 3439 if (on) 3440 msgbuf[0] |= E1000_VF_SET_VLAN_ADD; 3441 3442 err = mbx->ops.write_posted(hw, msgbuf, 2, 0); 3443 if (err) 3444 goto mbx_err; 3445 3446 err = mbx->ops.read_posted(hw, msgbuf, 2, 0); 3447 if (err) 3448 goto mbx_err; 3449 3450 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS; 3451 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK)) 3452 err = -EINVAL; 3453 3454 mbx_err: 3455 return err; 3456 } 3457 3458 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on) 3459 { 3460 struct e1000_hw *hw = 3461 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3462 struct e1000_vfta * shadow_vfta = 3463 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 3464 int i = 0, j = 0, vfta = 0, mask = 1; 3465 3466 for (i = 0; i < IGB_VFTA_SIZE; i++){ 3467 vfta = shadow_vfta->vfta[i]; 3468 if(vfta){ 3469 mask = 1; 3470 for (j = 0; j < 32; j++){ 3471 if(vfta & mask) 3472 igbvf_set_vfta(hw, 3473 (uint16_t)((i<<5)+j), on); 3474 mask<<=1; 3475 } 3476 } 3477 } 3478 3479 } 3480 3481 static int 3482 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 3483 { 3484 struct e1000_hw *hw = 3485 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3486 struct e1000_vfta * shadow_vfta = 3487 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 3488 uint32_t vid_idx = 0; 3489 uint32_t vid_bit = 0; 3490 int ret = 0; 3491 3492 PMD_INIT_FUNC_TRACE(); 3493 3494 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/ 3495 ret = igbvf_set_vfta(hw, vlan_id, !!on); 3496 if(ret){ 3497 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 3498 return ret; 3499 } 3500 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 3501 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 3502 3503 /*Save what we set and retore it after device reset*/ 3504 if (on) 3505 shadow_vfta->vfta[vid_idx] |= vid_bit; 3506 else 3507 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 3508 3509 return 0; 3510 } 3511 3512 static void 3513 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr) 3514 { 3515 struct e1000_hw *hw = 3516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3517 3518 /* index is not used by rar_set() */ 3519 hw->mac.ops.rar_set(hw, (void *)addr, 0); 3520 } 3521 3522 3523 static int 3524 eth_igb_rss_reta_update(struct rte_eth_dev *dev, 3525 struct rte_eth_rss_reta_entry64 *reta_conf, 3526 uint16_t reta_size) 3527 { 3528 uint8_t i, j, mask; 3529 uint32_t reta, r; 3530 uint16_t idx, shift; 3531 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3532 3533 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3534 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3535 "(%d) doesn't match the number hardware can supported " 3536 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3537 return -EINVAL; 3538 } 3539 3540 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) { 3541 idx = i / RTE_RETA_GROUP_SIZE; 3542 shift = i % RTE_RETA_GROUP_SIZE; 3543 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 3544 IGB_4_BIT_MASK); 3545 if (!mask) 3546 continue; 3547 if (mask == IGB_4_BIT_MASK) 3548 r = 0; 3549 else 3550 r = E1000_READ_REG(hw, E1000_RETA(i >> 2)); 3551 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) { 3552 if (mask & (0x1 << j)) 3553 reta |= reta_conf[idx].reta[shift + j] << 3554 (CHAR_BIT * j); 3555 else 3556 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j)); 3557 } 3558 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3559 } 3560 3561 return 0; 3562 } 3563 3564 static int 3565 eth_igb_rss_reta_query(struct rte_eth_dev *dev, 3566 struct rte_eth_rss_reta_entry64 *reta_conf, 3567 uint16_t reta_size) 3568 { 3569 uint8_t i, j, mask; 3570 uint32_t reta; 3571 uint16_t idx, shift; 3572 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3573 3574 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3575 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3576 "(%d) doesn't match the number hardware can supported " 3577 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3578 return -EINVAL; 3579 } 3580 3581 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) { 3582 idx = i / RTE_RETA_GROUP_SIZE; 3583 shift = i % RTE_RETA_GROUP_SIZE; 3584 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 3585 IGB_4_BIT_MASK); 3586 if (!mask) 3587 continue; 3588 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2)); 3589 for (j = 0; j < IGB_4_BIT_WIDTH; j++) { 3590 if (mask & (0x1 << j)) 3591 reta_conf[idx].reta[shift + j] = 3592 ((reta >> (CHAR_BIT * j)) & 3593 IGB_8_BIT_MASK); 3594 } 3595 } 3596 3597 return 0; 3598 } 3599 3600 int 3601 eth_igb_syn_filter_set(struct rte_eth_dev *dev, 3602 struct rte_eth_syn_filter *filter, 3603 bool add) 3604 { 3605 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3606 struct e1000_filter_info *filter_info = 3607 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3608 uint32_t synqf, rfctl; 3609 3610 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM) 3611 return -EINVAL; 3612 3613 synqf = E1000_READ_REG(hw, E1000_SYNQF(0)); 3614 3615 if (add) { 3616 if (synqf & E1000_SYN_FILTER_ENABLE) 3617 return -EINVAL; 3618 3619 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) & 3620 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE); 3621 3622 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3623 if (filter->hig_pri) 3624 rfctl |= E1000_RFCTL_SYNQFP; 3625 else 3626 rfctl &= ~E1000_RFCTL_SYNQFP; 3627 3628 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3629 } else { 3630 if (!(synqf & E1000_SYN_FILTER_ENABLE)) 3631 return -ENOENT; 3632 synqf = 0; 3633 } 3634 3635 filter_info->syn_info = synqf; 3636 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf); 3637 E1000_WRITE_FLUSH(hw); 3638 return 0; 3639 } 3640 3641 static int 3642 eth_igb_syn_filter_get(struct rte_eth_dev *dev, 3643 struct rte_eth_syn_filter *filter) 3644 { 3645 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3646 uint32_t synqf, rfctl; 3647 3648 synqf = E1000_READ_REG(hw, E1000_SYNQF(0)); 3649 if (synqf & E1000_SYN_FILTER_ENABLE) { 3650 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3651 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0; 3652 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >> 3653 E1000_SYN_FILTER_QUEUE_SHIFT); 3654 return 0; 3655 } 3656 3657 return -ENOENT; 3658 } 3659 3660 static int 3661 eth_igb_syn_filter_handle(struct rte_eth_dev *dev, 3662 enum rte_filter_op filter_op, 3663 void *arg) 3664 { 3665 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3666 int ret; 3667 3668 MAC_TYPE_FILTER_SUP(hw->mac.type); 3669 3670 if (filter_op == RTE_ETH_FILTER_NOP) 3671 return 0; 3672 3673 if (arg == NULL) { 3674 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 3675 filter_op); 3676 return -EINVAL; 3677 } 3678 3679 switch (filter_op) { 3680 case RTE_ETH_FILTER_ADD: 3681 ret = eth_igb_syn_filter_set(dev, 3682 (struct rte_eth_syn_filter *)arg, 3683 TRUE); 3684 break; 3685 case RTE_ETH_FILTER_DELETE: 3686 ret = eth_igb_syn_filter_set(dev, 3687 (struct rte_eth_syn_filter *)arg, 3688 FALSE); 3689 break; 3690 case RTE_ETH_FILTER_GET: 3691 ret = eth_igb_syn_filter_get(dev, 3692 (struct rte_eth_syn_filter *)arg); 3693 break; 3694 default: 3695 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 3696 ret = -EINVAL; 3697 break; 3698 } 3699 3700 return ret; 3701 } 3702 3703 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/ 3704 static inline int 3705 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter, 3706 struct e1000_2tuple_filter_info *filter_info) 3707 { 3708 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM) 3709 return -EINVAL; 3710 if (filter->priority > E1000_2TUPLE_MAX_PRI) 3711 return -EINVAL; /* filter index is out of range. */ 3712 if (filter->tcp_flags > TCP_FLAG_ALL) 3713 return -EINVAL; /* flags is invalid. */ 3714 3715 switch (filter->dst_port_mask) { 3716 case UINT16_MAX: 3717 filter_info->dst_port_mask = 0; 3718 filter_info->dst_port = filter->dst_port; 3719 break; 3720 case 0: 3721 filter_info->dst_port_mask = 1; 3722 break; 3723 default: 3724 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 3725 return -EINVAL; 3726 } 3727 3728 switch (filter->proto_mask) { 3729 case UINT8_MAX: 3730 filter_info->proto_mask = 0; 3731 filter_info->proto = filter->proto; 3732 break; 3733 case 0: 3734 filter_info->proto_mask = 1; 3735 break; 3736 default: 3737 PMD_DRV_LOG(ERR, "invalid protocol mask."); 3738 return -EINVAL; 3739 } 3740 3741 filter_info->priority = (uint8_t)filter->priority; 3742 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) 3743 filter_info->tcp_flags = filter->tcp_flags; 3744 else 3745 filter_info->tcp_flags = 0; 3746 3747 return 0; 3748 } 3749 3750 static inline struct e1000_2tuple_filter * 3751 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list, 3752 struct e1000_2tuple_filter_info *key) 3753 { 3754 struct e1000_2tuple_filter *it; 3755 3756 TAILQ_FOREACH(it, filter_list, entries) { 3757 if (memcmp(key, &it->filter_info, 3758 sizeof(struct e1000_2tuple_filter_info)) == 0) { 3759 return it; 3760 } 3761 } 3762 return NULL; 3763 } 3764 3765 /* inject a igb 2tuple filter to HW */ 3766 static inline void 3767 igb_inject_2uple_filter(struct rte_eth_dev *dev, 3768 struct e1000_2tuple_filter *filter) 3769 { 3770 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3771 uint32_t ttqf = E1000_TTQF_DISABLE_MASK; 3772 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP; 3773 int i; 3774 3775 i = filter->index; 3776 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT); 3777 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */ 3778 imir |= E1000_IMIR_PORT_BP; 3779 else 3780 imir &= ~E1000_IMIR_PORT_BP; 3781 3782 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT; 3783 3784 ttqf |= E1000_TTQF_QUEUE_ENABLE; 3785 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT); 3786 ttqf |= (uint32_t)(filter->filter_info.proto & 3787 E1000_TTQF_PROTOCOL_MASK); 3788 if (filter->filter_info.proto_mask == 0) 3789 ttqf &= ~E1000_TTQF_MASK_ENABLE; 3790 3791 /* tcp flags bits setting. */ 3792 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) { 3793 if (filter->filter_info.tcp_flags & TCP_URG_FLAG) 3794 imir_ext |= E1000_IMIREXT_CTRL_URG; 3795 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG) 3796 imir_ext |= E1000_IMIREXT_CTRL_ACK; 3797 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG) 3798 imir_ext |= E1000_IMIREXT_CTRL_PSH; 3799 if (filter->filter_info.tcp_flags & TCP_RST_FLAG) 3800 imir_ext |= E1000_IMIREXT_CTRL_RST; 3801 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG) 3802 imir_ext |= E1000_IMIREXT_CTRL_SYN; 3803 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG) 3804 imir_ext |= E1000_IMIREXT_CTRL_FIN; 3805 } else { 3806 imir_ext |= E1000_IMIREXT_CTRL_BP; 3807 } 3808 E1000_WRITE_REG(hw, E1000_IMIR(i), imir); 3809 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf); 3810 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext); 3811 } 3812 3813 /* 3814 * igb_add_2tuple_filter - add a 2tuple filter 3815 * 3816 * @param 3817 * dev: Pointer to struct rte_eth_dev. 3818 * ntuple_filter: ponter to the filter that will be added. 3819 * 3820 * @return 3821 * - On success, zero. 3822 * - On failure, a negative value. 3823 */ 3824 static int 3825 igb_add_2tuple_filter(struct rte_eth_dev *dev, 3826 struct rte_eth_ntuple_filter *ntuple_filter) 3827 { 3828 struct e1000_filter_info *filter_info = 3829 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3830 struct e1000_2tuple_filter *filter; 3831 int i, ret; 3832 3833 filter = rte_zmalloc("e1000_2tuple_filter", 3834 sizeof(struct e1000_2tuple_filter), 0); 3835 if (filter == NULL) 3836 return -ENOMEM; 3837 3838 ret = ntuple_filter_to_2tuple(ntuple_filter, 3839 &filter->filter_info); 3840 if (ret < 0) { 3841 rte_free(filter); 3842 return ret; 3843 } 3844 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list, 3845 &filter->filter_info) != NULL) { 3846 PMD_DRV_LOG(ERR, "filter exists."); 3847 rte_free(filter); 3848 return -EEXIST; 3849 } 3850 filter->queue = ntuple_filter->queue; 3851 3852 /* 3853 * look for an unused 2tuple filter index, 3854 * and insert the filter to list. 3855 */ 3856 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) { 3857 if (!(filter_info->twotuple_mask & (1 << i))) { 3858 filter_info->twotuple_mask |= 1 << i; 3859 filter->index = i; 3860 TAILQ_INSERT_TAIL(&filter_info->twotuple_list, 3861 filter, 3862 entries); 3863 break; 3864 } 3865 } 3866 if (i >= E1000_MAX_TTQF_FILTERS) { 3867 PMD_DRV_LOG(ERR, "2tuple filters are full."); 3868 rte_free(filter); 3869 return -ENOSYS; 3870 } 3871 3872 igb_inject_2uple_filter(dev, filter); 3873 return 0; 3874 } 3875 3876 int 3877 igb_delete_2tuple_filter(struct rte_eth_dev *dev, 3878 struct e1000_2tuple_filter *filter) 3879 { 3880 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3881 struct e1000_filter_info *filter_info = 3882 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3883 3884 filter_info->twotuple_mask &= ~(1 << filter->index); 3885 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries); 3886 rte_free(filter); 3887 3888 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK); 3889 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0); 3890 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0); 3891 return 0; 3892 } 3893 3894 /* 3895 * igb_remove_2tuple_filter - remove a 2tuple filter 3896 * 3897 * @param 3898 * dev: Pointer to struct rte_eth_dev. 3899 * ntuple_filter: ponter to the filter that will be removed. 3900 * 3901 * @return 3902 * - On success, zero. 3903 * - On failure, a negative value. 3904 */ 3905 static int 3906 igb_remove_2tuple_filter(struct rte_eth_dev *dev, 3907 struct rte_eth_ntuple_filter *ntuple_filter) 3908 { 3909 struct e1000_filter_info *filter_info = 3910 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3911 struct e1000_2tuple_filter_info filter_2tuple; 3912 struct e1000_2tuple_filter *filter; 3913 int ret; 3914 3915 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info)); 3916 ret = ntuple_filter_to_2tuple(ntuple_filter, 3917 &filter_2tuple); 3918 if (ret < 0) 3919 return ret; 3920 3921 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list, 3922 &filter_2tuple); 3923 if (filter == NULL) { 3924 PMD_DRV_LOG(ERR, "filter doesn't exist."); 3925 return -ENOENT; 3926 } 3927 3928 igb_delete_2tuple_filter(dev, filter); 3929 3930 return 0; 3931 } 3932 3933 /* inject a igb flex filter to HW */ 3934 static inline void 3935 igb_inject_flex_filter(struct rte_eth_dev *dev, 3936 struct e1000_flex_filter *filter) 3937 { 3938 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3939 uint32_t wufc, queueing; 3940 uint32_t reg_off; 3941 uint8_t i, j = 0; 3942 3943 wufc = E1000_READ_REG(hw, E1000_WUFC); 3944 if (filter->index < E1000_MAX_FHFT) 3945 reg_off = E1000_FHFT(filter->index); 3946 else 3947 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT); 3948 3949 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ | 3950 (E1000_WUFC_FLX0 << filter->index)); 3951 queueing = filter->filter_info.len | 3952 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) | 3953 (filter->filter_info.priority << 3954 E1000_FHFT_QUEUEING_PRIO_SHIFT); 3955 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, 3956 queueing); 3957 3958 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) { 3959 E1000_WRITE_REG(hw, reg_off, 3960 filter->filter_info.dwords[j]); 3961 reg_off += sizeof(uint32_t); 3962 E1000_WRITE_REG(hw, reg_off, 3963 filter->filter_info.dwords[++j]); 3964 reg_off += sizeof(uint32_t); 3965 E1000_WRITE_REG(hw, reg_off, 3966 (uint32_t)filter->filter_info.mask[i]); 3967 reg_off += sizeof(uint32_t) * 2; 3968 ++j; 3969 } 3970 } 3971 3972 static inline struct e1000_flex_filter * 3973 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list, 3974 struct e1000_flex_filter_info *key) 3975 { 3976 struct e1000_flex_filter *it; 3977 3978 TAILQ_FOREACH(it, filter_list, entries) { 3979 if (memcmp(key, &it->filter_info, 3980 sizeof(struct e1000_flex_filter_info)) == 0) 3981 return it; 3982 } 3983 3984 return NULL; 3985 } 3986 3987 /* remove a flex byte filter 3988 * @param 3989 * dev: Pointer to struct rte_eth_dev. 3990 * filter: the pointer of the filter will be removed. 3991 */ 3992 void 3993 igb_remove_flex_filter(struct rte_eth_dev *dev, 3994 struct e1000_flex_filter *filter) 3995 { 3996 struct e1000_filter_info *filter_info = 3997 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 3998 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3999 uint32_t wufc, i; 4000 uint32_t reg_off; 4001 4002 wufc = E1000_READ_REG(hw, E1000_WUFC); 4003 if (filter->index < E1000_MAX_FHFT) 4004 reg_off = E1000_FHFT(filter->index); 4005 else 4006 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT); 4007 4008 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++) 4009 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0); 4010 4011 E1000_WRITE_REG(hw, E1000_WUFC, wufc & 4012 (~(E1000_WUFC_FLX0 << filter->index))); 4013 4014 filter_info->flex_mask &= ~(1 << filter->index); 4015 TAILQ_REMOVE(&filter_info->flex_list, filter, entries); 4016 rte_free(filter); 4017 } 4018 4019 int 4020 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev, 4021 struct rte_eth_flex_filter *filter, 4022 bool add) 4023 { 4024 struct e1000_filter_info *filter_info = 4025 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4026 struct e1000_flex_filter *flex_filter, *it; 4027 uint32_t mask; 4028 uint8_t shift, i; 4029 4030 flex_filter = rte_zmalloc("e1000_flex_filter", 4031 sizeof(struct e1000_flex_filter), 0); 4032 if (flex_filter == NULL) 4033 return -ENOMEM; 4034 4035 flex_filter->filter_info.len = filter->len; 4036 flex_filter->filter_info.priority = filter->priority; 4037 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len); 4038 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) { 4039 mask = 0; 4040 /* reverse bits in flex filter's mask*/ 4041 for (shift = 0; shift < CHAR_BIT; shift++) { 4042 if (filter->mask[i] & (0x01 << shift)) 4043 mask |= (0x80 >> shift); 4044 } 4045 flex_filter->filter_info.mask[i] = mask; 4046 } 4047 4048 it = eth_igb_flex_filter_lookup(&filter_info->flex_list, 4049 &flex_filter->filter_info); 4050 if (it == NULL && !add) { 4051 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4052 rte_free(flex_filter); 4053 return -ENOENT; 4054 } 4055 if (it != NULL && add) { 4056 PMD_DRV_LOG(ERR, "filter exists."); 4057 rte_free(flex_filter); 4058 return -EEXIST; 4059 } 4060 4061 if (add) { 4062 flex_filter->queue = filter->queue; 4063 /* 4064 * look for an unused flex filter index 4065 * and insert the filter into the list. 4066 */ 4067 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) { 4068 if (!(filter_info->flex_mask & (1 << i))) { 4069 filter_info->flex_mask |= 1 << i; 4070 flex_filter->index = i; 4071 TAILQ_INSERT_TAIL(&filter_info->flex_list, 4072 flex_filter, 4073 entries); 4074 break; 4075 } 4076 } 4077 if (i >= E1000_MAX_FLEX_FILTERS) { 4078 PMD_DRV_LOG(ERR, "flex filters are full."); 4079 rte_free(flex_filter); 4080 return -ENOSYS; 4081 } 4082 4083 igb_inject_flex_filter(dev, flex_filter); 4084 4085 } else { 4086 igb_remove_flex_filter(dev, it); 4087 rte_free(flex_filter); 4088 } 4089 4090 return 0; 4091 } 4092 4093 static int 4094 eth_igb_get_flex_filter(struct rte_eth_dev *dev, 4095 struct rte_eth_flex_filter *filter) 4096 { 4097 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4098 struct e1000_filter_info *filter_info = 4099 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4100 struct e1000_flex_filter flex_filter, *it; 4101 uint32_t wufc, queueing, wufc_en = 0; 4102 4103 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter)); 4104 flex_filter.filter_info.len = filter->len; 4105 flex_filter.filter_info.priority = filter->priority; 4106 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len); 4107 memcpy(flex_filter.filter_info.mask, filter->mask, 4108 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT); 4109 4110 it = eth_igb_flex_filter_lookup(&filter_info->flex_list, 4111 &flex_filter.filter_info); 4112 if (it == NULL) { 4113 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4114 return -ENOENT; 4115 } 4116 4117 wufc = E1000_READ_REG(hw, E1000_WUFC); 4118 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index); 4119 4120 if ((wufc & wufc_en) == wufc_en) { 4121 uint32_t reg_off = 0; 4122 if (it->index < E1000_MAX_FHFT) 4123 reg_off = E1000_FHFT(it->index); 4124 else 4125 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT); 4126 4127 queueing = E1000_READ_REG(hw, 4128 reg_off + E1000_FHFT_QUEUEING_OFFSET); 4129 filter->len = queueing & E1000_FHFT_QUEUEING_LEN; 4130 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >> 4131 E1000_FHFT_QUEUEING_PRIO_SHIFT; 4132 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >> 4133 E1000_FHFT_QUEUEING_QUEUE_SHIFT; 4134 return 0; 4135 } 4136 return -ENOENT; 4137 } 4138 4139 static int 4140 eth_igb_flex_filter_handle(struct rte_eth_dev *dev, 4141 enum rte_filter_op filter_op, 4142 void *arg) 4143 { 4144 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4145 struct rte_eth_flex_filter *filter; 4146 int ret = 0; 4147 4148 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 4149 4150 if (filter_op == RTE_ETH_FILTER_NOP) 4151 return ret; 4152 4153 if (arg == NULL) { 4154 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 4155 filter_op); 4156 return -EINVAL; 4157 } 4158 4159 filter = (struct rte_eth_flex_filter *)arg; 4160 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN 4161 || filter->len % sizeof(uint64_t) != 0) { 4162 PMD_DRV_LOG(ERR, "filter's length is out of range"); 4163 return -EINVAL; 4164 } 4165 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) { 4166 PMD_DRV_LOG(ERR, "filter's priority is out of range"); 4167 return -EINVAL; 4168 } 4169 4170 switch (filter_op) { 4171 case RTE_ETH_FILTER_ADD: 4172 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE); 4173 break; 4174 case RTE_ETH_FILTER_DELETE: 4175 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE); 4176 break; 4177 case RTE_ETH_FILTER_GET: 4178 ret = eth_igb_get_flex_filter(dev, filter); 4179 break; 4180 default: 4181 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 4182 ret = -EINVAL; 4183 break; 4184 } 4185 4186 return ret; 4187 } 4188 4189 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/ 4190 static inline int 4191 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter, 4192 struct e1000_5tuple_filter_info *filter_info) 4193 { 4194 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576) 4195 return -EINVAL; 4196 if (filter->priority > E1000_2TUPLE_MAX_PRI) 4197 return -EINVAL; /* filter index is out of range. */ 4198 if (filter->tcp_flags > TCP_FLAG_ALL) 4199 return -EINVAL; /* flags is invalid. */ 4200 4201 switch (filter->dst_ip_mask) { 4202 case UINT32_MAX: 4203 filter_info->dst_ip_mask = 0; 4204 filter_info->dst_ip = filter->dst_ip; 4205 break; 4206 case 0: 4207 filter_info->dst_ip_mask = 1; 4208 break; 4209 default: 4210 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 4211 return -EINVAL; 4212 } 4213 4214 switch (filter->src_ip_mask) { 4215 case UINT32_MAX: 4216 filter_info->src_ip_mask = 0; 4217 filter_info->src_ip = filter->src_ip; 4218 break; 4219 case 0: 4220 filter_info->src_ip_mask = 1; 4221 break; 4222 default: 4223 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 4224 return -EINVAL; 4225 } 4226 4227 switch (filter->dst_port_mask) { 4228 case UINT16_MAX: 4229 filter_info->dst_port_mask = 0; 4230 filter_info->dst_port = filter->dst_port; 4231 break; 4232 case 0: 4233 filter_info->dst_port_mask = 1; 4234 break; 4235 default: 4236 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 4237 return -EINVAL; 4238 } 4239 4240 switch (filter->src_port_mask) { 4241 case UINT16_MAX: 4242 filter_info->src_port_mask = 0; 4243 filter_info->src_port = filter->src_port; 4244 break; 4245 case 0: 4246 filter_info->src_port_mask = 1; 4247 break; 4248 default: 4249 PMD_DRV_LOG(ERR, "invalid src_port mask."); 4250 return -EINVAL; 4251 } 4252 4253 switch (filter->proto_mask) { 4254 case UINT8_MAX: 4255 filter_info->proto_mask = 0; 4256 filter_info->proto = filter->proto; 4257 break; 4258 case 0: 4259 filter_info->proto_mask = 1; 4260 break; 4261 default: 4262 PMD_DRV_LOG(ERR, "invalid protocol mask."); 4263 return -EINVAL; 4264 } 4265 4266 filter_info->priority = (uint8_t)filter->priority; 4267 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) 4268 filter_info->tcp_flags = filter->tcp_flags; 4269 else 4270 filter_info->tcp_flags = 0; 4271 4272 return 0; 4273 } 4274 4275 static inline struct e1000_5tuple_filter * 4276 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list, 4277 struct e1000_5tuple_filter_info *key) 4278 { 4279 struct e1000_5tuple_filter *it; 4280 4281 TAILQ_FOREACH(it, filter_list, entries) { 4282 if (memcmp(key, &it->filter_info, 4283 sizeof(struct e1000_5tuple_filter_info)) == 0) { 4284 return it; 4285 } 4286 } 4287 return NULL; 4288 } 4289 4290 /* inject a igb 5-tuple filter to HW */ 4291 static inline void 4292 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev, 4293 struct e1000_5tuple_filter *filter) 4294 { 4295 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4296 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK; 4297 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP; 4298 uint8_t i; 4299 4300 i = filter->index; 4301 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK; 4302 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */ 4303 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP; 4304 if (filter->filter_info.dst_ip_mask == 0) 4305 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP; 4306 if (filter->filter_info.src_port_mask == 0) 4307 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 4308 if (filter->filter_info.proto_mask == 0) 4309 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; 4310 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) & 4311 E1000_FTQF_QUEUE_MASK; 4312 ftqf |= E1000_FTQF_QUEUE_ENABLE; 4313 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf); 4314 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip); 4315 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip); 4316 4317 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT; 4318 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf); 4319 4320 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT); 4321 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */ 4322 imir |= E1000_IMIR_PORT_BP; 4323 else 4324 imir &= ~E1000_IMIR_PORT_BP; 4325 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT; 4326 4327 /* tcp flags bits setting. */ 4328 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) { 4329 if (filter->filter_info.tcp_flags & TCP_URG_FLAG) 4330 imir_ext |= E1000_IMIREXT_CTRL_URG; 4331 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG) 4332 imir_ext |= E1000_IMIREXT_CTRL_ACK; 4333 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG) 4334 imir_ext |= E1000_IMIREXT_CTRL_PSH; 4335 if (filter->filter_info.tcp_flags & TCP_RST_FLAG) 4336 imir_ext |= E1000_IMIREXT_CTRL_RST; 4337 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG) 4338 imir_ext |= E1000_IMIREXT_CTRL_SYN; 4339 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG) 4340 imir_ext |= E1000_IMIREXT_CTRL_FIN; 4341 } else { 4342 imir_ext |= E1000_IMIREXT_CTRL_BP; 4343 } 4344 E1000_WRITE_REG(hw, E1000_IMIR(i), imir); 4345 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext); 4346 } 4347 4348 /* 4349 * igb_add_5tuple_filter_82576 - add a 5tuple filter 4350 * 4351 * @param 4352 * dev: Pointer to struct rte_eth_dev. 4353 * ntuple_filter: ponter to the filter that will be added. 4354 * 4355 * @return 4356 * - On success, zero. 4357 * - On failure, a negative value. 4358 */ 4359 static int 4360 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev, 4361 struct rte_eth_ntuple_filter *ntuple_filter) 4362 { 4363 struct e1000_filter_info *filter_info = 4364 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4365 struct e1000_5tuple_filter *filter; 4366 uint8_t i; 4367 int ret; 4368 4369 filter = rte_zmalloc("e1000_5tuple_filter", 4370 sizeof(struct e1000_5tuple_filter), 0); 4371 if (filter == NULL) 4372 return -ENOMEM; 4373 4374 ret = ntuple_filter_to_5tuple_82576(ntuple_filter, 4375 &filter->filter_info); 4376 if (ret < 0) { 4377 rte_free(filter); 4378 return ret; 4379 } 4380 4381 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list, 4382 &filter->filter_info) != NULL) { 4383 PMD_DRV_LOG(ERR, "filter exists."); 4384 rte_free(filter); 4385 return -EEXIST; 4386 } 4387 filter->queue = ntuple_filter->queue; 4388 4389 /* 4390 * look for an unused 5tuple filter index, 4391 * and insert the filter to list. 4392 */ 4393 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) { 4394 if (!(filter_info->fivetuple_mask & (1 << i))) { 4395 filter_info->fivetuple_mask |= 1 << i; 4396 filter->index = i; 4397 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 4398 filter, 4399 entries); 4400 break; 4401 } 4402 } 4403 if (i >= E1000_MAX_FTQF_FILTERS) { 4404 PMD_DRV_LOG(ERR, "5tuple filters are full."); 4405 rte_free(filter); 4406 return -ENOSYS; 4407 } 4408 4409 igb_inject_5tuple_filter_82576(dev, filter); 4410 return 0; 4411 } 4412 4413 int 4414 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev, 4415 struct e1000_5tuple_filter *filter) 4416 { 4417 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4418 struct e1000_filter_info *filter_info = 4419 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4420 4421 filter_info->fivetuple_mask &= ~(1 << filter->index); 4422 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 4423 rte_free(filter); 4424 4425 E1000_WRITE_REG(hw, E1000_FTQF(filter->index), 4426 E1000_FTQF_VF_BP | E1000_FTQF_MASK); 4427 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0); 4428 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0); 4429 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0); 4430 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0); 4431 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0); 4432 return 0; 4433 } 4434 4435 /* 4436 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter 4437 * 4438 * @param 4439 * dev: Pointer to struct rte_eth_dev. 4440 * ntuple_filter: ponter to the filter that will be removed. 4441 * 4442 * @return 4443 * - On success, zero. 4444 * - On failure, a negative value. 4445 */ 4446 static int 4447 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev, 4448 struct rte_eth_ntuple_filter *ntuple_filter) 4449 { 4450 struct e1000_filter_info *filter_info = 4451 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4452 struct e1000_5tuple_filter_info filter_5tuple; 4453 struct e1000_5tuple_filter *filter; 4454 int ret; 4455 4456 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info)); 4457 ret = ntuple_filter_to_5tuple_82576(ntuple_filter, 4458 &filter_5tuple); 4459 if (ret < 0) 4460 return ret; 4461 4462 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list, 4463 &filter_5tuple); 4464 if (filter == NULL) { 4465 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4466 return -ENOENT; 4467 } 4468 4469 igb_delete_5tuple_filter_82576(dev, filter); 4470 4471 return 0; 4472 } 4473 4474 static int 4475 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 4476 { 4477 uint32_t rctl; 4478 struct e1000_hw *hw; 4479 struct rte_eth_dev_info dev_info; 4480 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN + 4481 VLAN_TAG_SIZE); 4482 4483 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4484 4485 #ifdef RTE_LIBRTE_82571_SUPPORT 4486 /* XXX: not bigger than max_rx_pktlen */ 4487 if (hw->mac.type == e1000_82571) 4488 return -ENOTSUP; 4489 #endif 4490 eth_igb_infos_get(dev, &dev_info); 4491 4492 /* check that mtu is within the allowed range */ 4493 if ((mtu < ETHER_MIN_MTU) || 4494 (frame_size > dev_info.max_rx_pktlen)) 4495 return -EINVAL; 4496 4497 /* refuse mtu that requires the support of scattered packets when this 4498 * feature has not been enabled before. */ 4499 if (!dev->data->scattered_rx && 4500 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) 4501 return -EINVAL; 4502 4503 rctl = E1000_READ_REG(hw, E1000_RCTL); 4504 4505 /* switch to jumbo mode if needed */ 4506 if (frame_size > ETHER_MAX_LEN) { 4507 dev->data->dev_conf.rxmode.jumbo_frame = 1; 4508 rctl |= E1000_RCTL_LPE; 4509 } else { 4510 dev->data->dev_conf.rxmode.jumbo_frame = 0; 4511 rctl &= ~E1000_RCTL_LPE; 4512 } 4513 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4514 4515 /* update max frame size */ 4516 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 4517 4518 E1000_WRITE_REG(hw, E1000_RLPML, 4519 dev->data->dev_conf.rxmode.max_rx_pkt_len); 4520 4521 return 0; 4522 } 4523 4524 /* 4525 * igb_add_del_ntuple_filter - add or delete a ntuple filter 4526 * 4527 * @param 4528 * dev: Pointer to struct rte_eth_dev. 4529 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 4530 * add: if true, add filter, if false, remove filter 4531 * 4532 * @return 4533 * - On success, zero. 4534 * - On failure, a negative value. 4535 */ 4536 int 4537 igb_add_del_ntuple_filter(struct rte_eth_dev *dev, 4538 struct rte_eth_ntuple_filter *ntuple_filter, 4539 bool add) 4540 { 4541 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4542 int ret; 4543 4544 switch (ntuple_filter->flags) { 4545 case RTE_5TUPLE_FLAGS: 4546 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG): 4547 if (hw->mac.type != e1000_82576) 4548 return -ENOTSUP; 4549 if (add) 4550 ret = igb_add_5tuple_filter_82576(dev, 4551 ntuple_filter); 4552 else 4553 ret = igb_remove_5tuple_filter_82576(dev, 4554 ntuple_filter); 4555 break; 4556 case RTE_2TUPLE_FLAGS: 4557 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG): 4558 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 && 4559 hw->mac.type != e1000_i210 && 4560 hw->mac.type != e1000_i211) 4561 return -ENOTSUP; 4562 if (add) 4563 ret = igb_add_2tuple_filter(dev, ntuple_filter); 4564 else 4565 ret = igb_remove_2tuple_filter(dev, ntuple_filter); 4566 break; 4567 default: 4568 ret = -EINVAL; 4569 break; 4570 } 4571 4572 return ret; 4573 } 4574 4575 /* 4576 * igb_get_ntuple_filter - get a ntuple filter 4577 * 4578 * @param 4579 * dev: Pointer to struct rte_eth_dev. 4580 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 4581 * 4582 * @return 4583 * - On success, zero. 4584 * - On failure, a negative value. 4585 */ 4586 static int 4587 igb_get_ntuple_filter(struct rte_eth_dev *dev, 4588 struct rte_eth_ntuple_filter *ntuple_filter) 4589 { 4590 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4591 struct e1000_filter_info *filter_info = 4592 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4593 struct e1000_5tuple_filter_info filter_5tuple; 4594 struct e1000_2tuple_filter_info filter_2tuple; 4595 struct e1000_5tuple_filter *p_5tuple_filter; 4596 struct e1000_2tuple_filter *p_2tuple_filter; 4597 int ret; 4598 4599 switch (ntuple_filter->flags) { 4600 case RTE_5TUPLE_FLAGS: 4601 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG): 4602 if (hw->mac.type != e1000_82576) 4603 return -ENOTSUP; 4604 memset(&filter_5tuple, 4605 0, 4606 sizeof(struct e1000_5tuple_filter_info)); 4607 ret = ntuple_filter_to_5tuple_82576(ntuple_filter, 4608 &filter_5tuple); 4609 if (ret < 0) 4610 return ret; 4611 p_5tuple_filter = igb_5tuple_filter_lookup_82576( 4612 &filter_info->fivetuple_list, 4613 &filter_5tuple); 4614 if (p_5tuple_filter == NULL) { 4615 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4616 return -ENOENT; 4617 } 4618 ntuple_filter->queue = p_5tuple_filter->queue; 4619 break; 4620 case RTE_2TUPLE_FLAGS: 4621 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG): 4622 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350) 4623 return -ENOTSUP; 4624 memset(&filter_2tuple, 4625 0, 4626 sizeof(struct e1000_2tuple_filter_info)); 4627 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple); 4628 if (ret < 0) 4629 return ret; 4630 p_2tuple_filter = igb_2tuple_filter_lookup( 4631 &filter_info->twotuple_list, 4632 &filter_2tuple); 4633 if (p_2tuple_filter == NULL) { 4634 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4635 return -ENOENT; 4636 } 4637 ntuple_filter->queue = p_2tuple_filter->queue; 4638 break; 4639 default: 4640 ret = -EINVAL; 4641 break; 4642 } 4643 4644 return 0; 4645 } 4646 4647 /* 4648 * igb_ntuple_filter_handle - Handle operations for ntuple filter. 4649 * @dev: pointer to rte_eth_dev structure 4650 * @filter_op:operation will be taken. 4651 * @arg: a pointer to specific structure corresponding to the filter_op 4652 */ 4653 static int 4654 igb_ntuple_filter_handle(struct rte_eth_dev *dev, 4655 enum rte_filter_op filter_op, 4656 void *arg) 4657 { 4658 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4659 int ret; 4660 4661 MAC_TYPE_FILTER_SUP(hw->mac.type); 4662 4663 if (filter_op == RTE_ETH_FILTER_NOP) 4664 return 0; 4665 4666 if (arg == NULL) { 4667 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 4668 filter_op); 4669 return -EINVAL; 4670 } 4671 4672 switch (filter_op) { 4673 case RTE_ETH_FILTER_ADD: 4674 ret = igb_add_del_ntuple_filter(dev, 4675 (struct rte_eth_ntuple_filter *)arg, 4676 TRUE); 4677 break; 4678 case RTE_ETH_FILTER_DELETE: 4679 ret = igb_add_del_ntuple_filter(dev, 4680 (struct rte_eth_ntuple_filter *)arg, 4681 FALSE); 4682 break; 4683 case RTE_ETH_FILTER_GET: 4684 ret = igb_get_ntuple_filter(dev, 4685 (struct rte_eth_ntuple_filter *)arg); 4686 break; 4687 default: 4688 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 4689 ret = -EINVAL; 4690 break; 4691 } 4692 return ret; 4693 } 4694 4695 static inline int 4696 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info, 4697 uint16_t ethertype) 4698 { 4699 int i; 4700 4701 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) { 4702 if (filter_info->ethertype_filters[i].ethertype == ethertype && 4703 (filter_info->ethertype_mask & (1 << i))) 4704 return i; 4705 } 4706 return -1; 4707 } 4708 4709 static inline int 4710 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info, 4711 uint16_t ethertype, uint32_t etqf) 4712 { 4713 int i; 4714 4715 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) { 4716 if (!(filter_info->ethertype_mask & (1 << i))) { 4717 filter_info->ethertype_mask |= 1 << i; 4718 filter_info->ethertype_filters[i].ethertype = ethertype; 4719 filter_info->ethertype_filters[i].etqf = etqf; 4720 return i; 4721 } 4722 } 4723 return -1; 4724 } 4725 4726 int 4727 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info, 4728 uint8_t idx) 4729 { 4730 if (idx >= E1000_MAX_ETQF_FILTERS) 4731 return -1; 4732 filter_info->ethertype_mask &= ~(1 << idx); 4733 filter_info->ethertype_filters[idx].ethertype = 0; 4734 filter_info->ethertype_filters[idx].etqf = 0; 4735 return idx; 4736 } 4737 4738 4739 int 4740 igb_add_del_ethertype_filter(struct rte_eth_dev *dev, 4741 struct rte_eth_ethertype_filter *filter, 4742 bool add) 4743 { 4744 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4745 struct e1000_filter_info *filter_info = 4746 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4747 uint32_t etqf = 0; 4748 int ret; 4749 4750 if (filter->ether_type == ETHER_TYPE_IPv4 || 4751 filter->ether_type == ETHER_TYPE_IPv6) { 4752 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 4753 " ethertype filter.", filter->ether_type); 4754 return -EINVAL; 4755 } 4756 4757 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 4758 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 4759 return -EINVAL; 4760 } 4761 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 4762 PMD_DRV_LOG(ERR, "drop option is unsupported."); 4763 return -EINVAL; 4764 } 4765 4766 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type); 4767 if (ret >= 0 && add) { 4768 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 4769 filter->ether_type); 4770 return -EEXIST; 4771 } 4772 if (ret < 0 && !add) { 4773 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 4774 filter->ether_type); 4775 return -ENOENT; 4776 } 4777 4778 if (add) { 4779 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE; 4780 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE); 4781 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT; 4782 ret = igb_ethertype_filter_insert(filter_info, 4783 filter->ether_type, etqf); 4784 if (ret < 0) { 4785 PMD_DRV_LOG(ERR, "ethertype filters are full."); 4786 return -ENOSYS; 4787 } 4788 } else { 4789 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret); 4790 if (ret < 0) 4791 return -ENOSYS; 4792 } 4793 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf); 4794 E1000_WRITE_FLUSH(hw); 4795 4796 return 0; 4797 } 4798 4799 static int 4800 igb_get_ethertype_filter(struct rte_eth_dev *dev, 4801 struct rte_eth_ethertype_filter *filter) 4802 { 4803 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4804 struct e1000_filter_info *filter_info = 4805 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 4806 uint32_t etqf; 4807 int ret; 4808 4809 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type); 4810 if (ret < 0) { 4811 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 4812 filter->ether_type); 4813 return -ENOENT; 4814 } 4815 4816 etqf = E1000_READ_REG(hw, E1000_ETQF(ret)); 4817 if (etqf & E1000_ETQF_FILTER_ENABLE) { 4818 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE; 4819 filter->flags = 0; 4820 filter->queue = (etqf & E1000_ETQF_QUEUE) >> 4821 E1000_ETQF_QUEUE_SHIFT; 4822 return 0; 4823 } 4824 4825 return -ENOENT; 4826 } 4827 4828 /* 4829 * igb_ethertype_filter_handle - Handle operations for ethertype filter. 4830 * @dev: pointer to rte_eth_dev structure 4831 * @filter_op:operation will be taken. 4832 * @arg: a pointer to specific structure corresponding to the filter_op 4833 */ 4834 static int 4835 igb_ethertype_filter_handle(struct rte_eth_dev *dev, 4836 enum rte_filter_op filter_op, 4837 void *arg) 4838 { 4839 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4840 int ret; 4841 4842 MAC_TYPE_FILTER_SUP(hw->mac.type); 4843 4844 if (filter_op == RTE_ETH_FILTER_NOP) 4845 return 0; 4846 4847 if (arg == NULL) { 4848 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 4849 filter_op); 4850 return -EINVAL; 4851 } 4852 4853 switch (filter_op) { 4854 case RTE_ETH_FILTER_ADD: 4855 ret = igb_add_del_ethertype_filter(dev, 4856 (struct rte_eth_ethertype_filter *)arg, 4857 TRUE); 4858 break; 4859 case RTE_ETH_FILTER_DELETE: 4860 ret = igb_add_del_ethertype_filter(dev, 4861 (struct rte_eth_ethertype_filter *)arg, 4862 FALSE); 4863 break; 4864 case RTE_ETH_FILTER_GET: 4865 ret = igb_get_ethertype_filter(dev, 4866 (struct rte_eth_ethertype_filter *)arg); 4867 break; 4868 default: 4869 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 4870 ret = -EINVAL; 4871 break; 4872 } 4873 return ret; 4874 } 4875 4876 static int 4877 eth_igb_filter_ctrl(struct rte_eth_dev *dev, 4878 enum rte_filter_type filter_type, 4879 enum rte_filter_op filter_op, 4880 void *arg) 4881 { 4882 int ret = 0; 4883 4884 switch (filter_type) { 4885 case RTE_ETH_FILTER_NTUPLE: 4886 ret = igb_ntuple_filter_handle(dev, filter_op, arg); 4887 break; 4888 case RTE_ETH_FILTER_ETHERTYPE: 4889 ret = igb_ethertype_filter_handle(dev, filter_op, arg); 4890 break; 4891 case RTE_ETH_FILTER_SYN: 4892 ret = eth_igb_syn_filter_handle(dev, filter_op, arg); 4893 break; 4894 case RTE_ETH_FILTER_FLEXIBLE: 4895 ret = eth_igb_flex_filter_handle(dev, filter_op, arg); 4896 break; 4897 case RTE_ETH_FILTER_GENERIC: 4898 if (filter_op != RTE_ETH_FILTER_GET) 4899 return -EINVAL; 4900 *(const void **)arg = &igb_flow_ops; 4901 break; 4902 default: 4903 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 4904 filter_type); 4905 break; 4906 } 4907 4908 return ret; 4909 } 4910 4911 static int 4912 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev, 4913 struct ether_addr *mc_addr_set, 4914 uint32_t nb_mc_addr) 4915 { 4916 struct e1000_hw *hw; 4917 4918 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4919 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr); 4920 return 0; 4921 } 4922 4923 static uint64_t 4924 igb_read_systime_cyclecounter(struct rte_eth_dev *dev) 4925 { 4926 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4927 uint64_t systime_cycles; 4928 4929 switch (hw->mac.type) { 4930 case e1000_i210: 4931 case e1000_i211: 4932 /* 4933 * Need to read System Time Residue Register to be able 4934 * to read the other two registers. 4935 */ 4936 E1000_READ_REG(hw, E1000_SYSTIMR); 4937 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 4938 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML); 4939 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH) 4940 * NSEC_PER_SEC; 4941 break; 4942 case e1000_82580: 4943 case e1000_i350: 4944 case e1000_i354: 4945 /* 4946 * Need to read System Time Residue Register to be able 4947 * to read the other two registers. 4948 */ 4949 E1000_READ_REG(hw, E1000_SYSTIMR); 4950 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML); 4951 /* Only the 8 LSB are valid. */ 4952 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH) 4953 & 0xff) << 32; 4954 break; 4955 default: 4956 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML); 4957 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH) 4958 << 32; 4959 break; 4960 } 4961 4962 return systime_cycles; 4963 } 4964 4965 static uint64_t 4966 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4967 { 4968 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4969 uint64_t rx_tstamp_cycles; 4970 4971 switch (hw->mac.type) { 4972 case e1000_i210: 4973 case e1000_i211: 4974 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 4975 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL); 4976 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH) 4977 * NSEC_PER_SEC; 4978 break; 4979 case e1000_82580: 4980 case e1000_i350: 4981 case e1000_i354: 4982 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL); 4983 /* Only the 8 LSB are valid. */ 4984 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH) 4985 & 0xff) << 32; 4986 break; 4987 default: 4988 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL); 4989 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH) 4990 << 32; 4991 break; 4992 } 4993 4994 return rx_tstamp_cycles; 4995 } 4996 4997 static uint64_t 4998 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4999 { 5000 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5001 uint64_t tx_tstamp_cycles; 5002 5003 switch (hw->mac.type) { 5004 case e1000_i210: 5005 case e1000_i211: 5006 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 5007 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL); 5008 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH) 5009 * NSEC_PER_SEC; 5010 break; 5011 case e1000_82580: 5012 case e1000_i350: 5013 case e1000_i354: 5014 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL); 5015 /* Only the 8 LSB are valid. */ 5016 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH) 5017 & 0xff) << 32; 5018 break; 5019 default: 5020 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL); 5021 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH) 5022 << 32; 5023 break; 5024 } 5025 5026 return tx_tstamp_cycles; 5027 } 5028 5029 static void 5030 igb_start_timecounters(struct rte_eth_dev *dev) 5031 { 5032 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5033 struct e1000_adapter *adapter = 5034 (struct e1000_adapter *)dev->data->dev_private; 5035 uint32_t incval = 1; 5036 uint32_t shift = 0; 5037 uint64_t mask = E1000_CYCLECOUNTER_MASK; 5038 5039 switch (hw->mac.type) { 5040 case e1000_82580: 5041 case e1000_i350: 5042 case e1000_i354: 5043 /* 32 LSB bits + 8 MSB bits = 40 bits */ 5044 mask = (1ULL << 40) - 1; 5045 /* fall-through */ 5046 case e1000_i210: 5047 case e1000_i211: 5048 /* 5049 * Start incrementing the register 5050 * used to timestamp PTP packets. 5051 */ 5052 E1000_WRITE_REG(hw, E1000_TIMINCA, incval); 5053 break; 5054 case e1000_82576: 5055 incval = E1000_INCVALUE_82576; 5056 shift = IGB_82576_TSYNC_SHIFT; 5057 E1000_WRITE_REG(hw, E1000_TIMINCA, 5058 E1000_INCPERIOD_82576 | incval); 5059 break; 5060 default: 5061 /* Not supported */ 5062 return; 5063 } 5064 5065 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 5066 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 5067 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 5068 5069 adapter->systime_tc.cc_mask = mask; 5070 adapter->systime_tc.cc_shift = shift; 5071 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 5072 5073 adapter->rx_tstamp_tc.cc_mask = mask; 5074 adapter->rx_tstamp_tc.cc_shift = shift; 5075 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 5076 5077 adapter->tx_tstamp_tc.cc_mask = mask; 5078 adapter->tx_tstamp_tc.cc_shift = shift; 5079 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 5080 } 5081 5082 static int 5083 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 5084 { 5085 struct e1000_adapter *adapter = 5086 (struct e1000_adapter *)dev->data->dev_private; 5087 5088 adapter->systime_tc.nsec += delta; 5089 adapter->rx_tstamp_tc.nsec += delta; 5090 adapter->tx_tstamp_tc.nsec += delta; 5091 5092 return 0; 5093 } 5094 5095 static int 5096 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 5097 { 5098 uint64_t ns; 5099 struct e1000_adapter *adapter = 5100 (struct e1000_adapter *)dev->data->dev_private; 5101 5102 ns = rte_timespec_to_ns(ts); 5103 5104 /* Set the timecounters to a new value. */ 5105 adapter->systime_tc.nsec = ns; 5106 adapter->rx_tstamp_tc.nsec = ns; 5107 adapter->tx_tstamp_tc.nsec = ns; 5108 5109 return 0; 5110 } 5111 5112 static int 5113 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 5114 { 5115 uint64_t ns, systime_cycles; 5116 struct e1000_adapter *adapter = 5117 (struct e1000_adapter *)dev->data->dev_private; 5118 5119 systime_cycles = igb_read_systime_cyclecounter(dev); 5120 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 5121 *ts = rte_ns_to_timespec(ns); 5122 5123 return 0; 5124 } 5125 5126 static int 5127 igb_timesync_enable(struct rte_eth_dev *dev) 5128 { 5129 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5130 uint32_t tsync_ctl; 5131 uint32_t tsauxc; 5132 5133 /* Stop the timesync system time. */ 5134 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0); 5135 /* Reset the timesync system time value. */ 5136 switch (hw->mac.type) { 5137 case e1000_82580: 5138 case e1000_i350: 5139 case e1000_i354: 5140 case e1000_i210: 5141 case e1000_i211: 5142 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0); 5143 /* fall-through */ 5144 case e1000_82576: 5145 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0); 5146 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0); 5147 break; 5148 default: 5149 /* Not supported. */ 5150 return -ENOTSUP; 5151 } 5152 5153 /* Enable system time for it isn't on by default. */ 5154 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC); 5155 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME; 5156 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc); 5157 5158 igb_start_timecounters(dev); 5159 5160 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 5161 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 5162 (ETHER_TYPE_1588 | 5163 E1000_ETQF_FILTER_ENABLE | 5164 E1000_ETQF_1588)); 5165 5166 /* Enable timestamping of received PTP packets. */ 5167 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL); 5168 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED; 5169 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl); 5170 5171 /* Enable Timestamping of transmitted PTP packets. */ 5172 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL); 5173 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED; 5174 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl); 5175 5176 return 0; 5177 } 5178 5179 static int 5180 igb_timesync_disable(struct rte_eth_dev *dev) 5181 { 5182 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5183 uint32_t tsync_ctl; 5184 5185 /* Disable timestamping of transmitted PTP packets. */ 5186 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL); 5187 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED; 5188 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl); 5189 5190 /* Disable timestamping of received PTP packets. */ 5191 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL); 5192 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED; 5193 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl); 5194 5195 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 5196 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0); 5197 5198 /* Stop incrementating the System Time registers. */ 5199 E1000_WRITE_REG(hw, E1000_TIMINCA, 0); 5200 5201 return 0; 5202 } 5203 5204 static int 5205 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 5206 struct timespec *timestamp, 5207 uint32_t flags __rte_unused) 5208 { 5209 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5210 struct e1000_adapter *adapter = 5211 (struct e1000_adapter *)dev->data->dev_private; 5212 uint32_t tsync_rxctl; 5213 uint64_t rx_tstamp_cycles; 5214 uint64_t ns; 5215 5216 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL); 5217 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0) 5218 return -EINVAL; 5219 5220 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev); 5221 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 5222 *timestamp = rte_ns_to_timespec(ns); 5223 5224 return 0; 5225 } 5226 5227 static int 5228 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 5229 struct timespec *timestamp) 5230 { 5231 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5232 struct e1000_adapter *adapter = 5233 (struct e1000_adapter *)dev->data->dev_private; 5234 uint32_t tsync_txctl; 5235 uint64_t tx_tstamp_cycles; 5236 uint64_t ns; 5237 5238 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL); 5239 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0) 5240 return -EINVAL; 5241 5242 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev); 5243 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 5244 *timestamp = rte_ns_to_timespec(ns); 5245 5246 return 0; 5247 } 5248 5249 static int 5250 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused) 5251 { 5252 int count = 0; 5253 int g_ind = 0; 5254 const struct reg_info *reg_group; 5255 5256 while ((reg_group = igb_regs[g_ind++])) 5257 count += igb_reg_group_count(reg_group); 5258 5259 return count; 5260 } 5261 5262 static int 5263 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 5264 { 5265 int count = 0; 5266 int g_ind = 0; 5267 const struct reg_info *reg_group; 5268 5269 while ((reg_group = igbvf_regs[g_ind++])) 5270 count += igb_reg_group_count(reg_group); 5271 5272 return count; 5273 } 5274 5275 static int 5276 eth_igb_get_regs(struct rte_eth_dev *dev, 5277 struct rte_dev_reg_info *regs) 5278 { 5279 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5280 uint32_t *data = regs->data; 5281 int g_ind = 0; 5282 int count = 0; 5283 const struct reg_info *reg_group; 5284 5285 if (data == NULL) { 5286 regs->length = eth_igb_get_reg_length(dev); 5287 regs->width = sizeof(uint32_t); 5288 return 0; 5289 } 5290 5291 /* Support only full register dump */ 5292 if ((regs->length == 0) || 5293 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) { 5294 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 5295 hw->device_id; 5296 while ((reg_group = igb_regs[g_ind++])) 5297 count += igb_read_regs_group(dev, &data[count], 5298 reg_group); 5299 return 0; 5300 } 5301 5302 return -ENOTSUP; 5303 } 5304 5305 static int 5306 igbvf_get_regs(struct rte_eth_dev *dev, 5307 struct rte_dev_reg_info *regs) 5308 { 5309 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5310 uint32_t *data = regs->data; 5311 int g_ind = 0; 5312 int count = 0; 5313 const struct reg_info *reg_group; 5314 5315 if (data == NULL) { 5316 regs->length = igbvf_get_reg_length(dev); 5317 regs->width = sizeof(uint32_t); 5318 return 0; 5319 } 5320 5321 /* Support only full register dump */ 5322 if ((regs->length == 0) || 5323 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) { 5324 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 5325 hw->device_id; 5326 while ((reg_group = igbvf_regs[g_ind++])) 5327 count += igb_read_regs_group(dev, &data[count], 5328 reg_group); 5329 return 0; 5330 } 5331 5332 return -ENOTSUP; 5333 } 5334 5335 static int 5336 eth_igb_get_eeprom_length(struct rte_eth_dev *dev) 5337 { 5338 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5339 5340 /* Return unit is byte count */ 5341 return hw->nvm.word_size * 2; 5342 } 5343 5344 static int 5345 eth_igb_get_eeprom(struct rte_eth_dev *dev, 5346 struct rte_dev_eeprom_info *in_eeprom) 5347 { 5348 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5349 struct e1000_nvm_info *nvm = &hw->nvm; 5350 uint16_t *data = in_eeprom->data; 5351 int first, length; 5352 5353 first = in_eeprom->offset >> 1; 5354 length = in_eeprom->length >> 1; 5355 if ((first >= hw->nvm.word_size) || 5356 ((first + length) >= hw->nvm.word_size)) 5357 return -EINVAL; 5358 5359 in_eeprom->magic = hw->vendor_id | 5360 ((uint32_t)hw->device_id << 16); 5361 5362 if ((nvm->ops.read) == NULL) 5363 return -ENOTSUP; 5364 5365 return nvm->ops.read(hw, first, length, data); 5366 } 5367 5368 static int 5369 eth_igb_set_eeprom(struct rte_eth_dev *dev, 5370 struct rte_dev_eeprom_info *in_eeprom) 5371 { 5372 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5373 struct e1000_nvm_info *nvm = &hw->nvm; 5374 uint16_t *data = in_eeprom->data; 5375 int first, length; 5376 5377 first = in_eeprom->offset >> 1; 5378 length = in_eeprom->length >> 1; 5379 if ((first >= hw->nvm.word_size) || 5380 ((first + length) >= hw->nvm.word_size)) 5381 return -EINVAL; 5382 5383 in_eeprom->magic = (uint32_t)hw->vendor_id | 5384 ((uint32_t)hw->device_id << 16); 5385 5386 if ((nvm->ops.write) == NULL) 5387 return -ENOTSUP; 5388 return nvm->ops.write(hw, first, length, data); 5389 } 5390 5391 static int 5392 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5393 { 5394 struct e1000_hw *hw = 5395 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5396 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5397 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5398 uint32_t vec = E1000_MISC_VEC_ID; 5399 5400 if (rte_intr_allow_others(intr_handle)) 5401 vec = E1000_RX_VEC_START; 5402 5403 uint32_t mask = 1 << (queue_id + vec); 5404 5405 E1000_WRITE_REG(hw, E1000_EIMC, mask); 5406 E1000_WRITE_FLUSH(hw); 5407 5408 return 0; 5409 } 5410 5411 static int 5412 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5413 { 5414 struct e1000_hw *hw = 5415 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5416 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5417 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5418 uint32_t vec = E1000_MISC_VEC_ID; 5419 5420 if (rte_intr_allow_others(intr_handle)) 5421 vec = E1000_RX_VEC_START; 5422 5423 uint32_t mask = 1 << (queue_id + vec); 5424 uint32_t regval; 5425 5426 regval = E1000_READ_REG(hw, E1000_EIMS); 5427 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); 5428 E1000_WRITE_FLUSH(hw); 5429 5430 rte_intr_enable(intr_handle); 5431 5432 return 0; 5433 } 5434 5435 static void 5436 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector, 5437 uint8_t index, uint8_t offset) 5438 { 5439 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 5440 5441 /* clear bits */ 5442 val &= ~((uint32_t)0xFF << offset); 5443 5444 /* write vector and valid bit */ 5445 val |= (msix_vector | E1000_IVAR_VALID) << offset; 5446 5447 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val); 5448 } 5449 5450 static void 5451 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction, 5452 uint8_t queue, uint8_t msix_vector) 5453 { 5454 uint32_t tmp = 0; 5455 5456 if (hw->mac.type == e1000_82575) { 5457 if (direction == 0) 5458 tmp = E1000_EICR_RX_QUEUE0 << queue; 5459 else if (direction == 1) 5460 tmp = E1000_EICR_TX_QUEUE0 << queue; 5461 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp); 5462 } else if (hw->mac.type == e1000_82576) { 5463 if ((direction == 0) || (direction == 1)) 5464 eth_igb_write_ivar(hw, msix_vector, queue & 0x7, 5465 ((queue & 0x8) << 1) + 5466 8 * direction); 5467 } else if ((hw->mac.type == e1000_82580) || 5468 (hw->mac.type == e1000_i350) || 5469 (hw->mac.type == e1000_i354) || 5470 (hw->mac.type == e1000_i210) || 5471 (hw->mac.type == e1000_i211)) { 5472 if ((direction == 0) || (direction == 1)) 5473 eth_igb_write_ivar(hw, msix_vector, 5474 queue >> 1, 5475 ((queue & 0x1) << 4) + 5476 8 * direction); 5477 } 5478 } 5479 5480 /* Sets up the hardware to generate MSI-X interrupts properly 5481 * @hw 5482 * board private structure 5483 */ 5484 static void 5485 eth_igb_configure_msix_intr(struct rte_eth_dev *dev) 5486 { 5487 int queue_id; 5488 uint32_t tmpval, regval, intr_mask; 5489 struct e1000_hw *hw = 5490 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5491 uint32_t vec = E1000_MISC_VEC_ID; 5492 uint32_t base = E1000_MISC_VEC_ID; 5493 uint32_t misc_shift = 0; 5494 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5495 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5496 5497 /* won't configure msix register if no mapping is done 5498 * between intr vector and event fd 5499 */ 5500 if (!rte_intr_dp_is_en(intr_handle)) 5501 return; 5502 5503 if (rte_intr_allow_others(intr_handle)) { 5504 vec = base = E1000_RX_VEC_START; 5505 misc_shift = 1; 5506 } 5507 5508 /* set interrupt vector for other causes */ 5509 if (hw->mac.type == e1000_82575) { 5510 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT); 5511 /* enable MSI-X PBA support */ 5512 tmpval |= E1000_CTRL_EXT_PBA_CLR; 5513 5514 /* Auto-Mask interrupts upon ICR read */ 5515 tmpval |= E1000_CTRL_EXT_EIAME; 5516 tmpval |= E1000_CTRL_EXT_IRCA; 5517 5518 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval); 5519 5520 /* enable msix_other interrupt */ 5521 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER); 5522 regval = E1000_READ_REG(hw, E1000_EIAC); 5523 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER); 5524 regval = E1000_READ_REG(hw, E1000_EIAM); 5525 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER); 5526 } else if ((hw->mac.type == e1000_82576) || 5527 (hw->mac.type == e1000_82580) || 5528 (hw->mac.type == e1000_i350) || 5529 (hw->mac.type == e1000_i354) || 5530 (hw->mac.type == e1000_i210) || 5531 (hw->mac.type == e1000_i211)) { 5532 /* turn on MSI-X capability first */ 5533 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE | 5534 E1000_GPIE_PBA | E1000_GPIE_EIAME | 5535 E1000_GPIE_NSICR); 5536 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << 5537 misc_shift; 5538 regval = E1000_READ_REG(hw, E1000_EIAC); 5539 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask); 5540 5541 /* enable msix_other interrupt */ 5542 regval = E1000_READ_REG(hw, E1000_EIMS); 5543 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask); 5544 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8; 5545 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval); 5546 } 5547 5548 /* use EIAM to auto-mask when MSI-X interrupt 5549 * is asserted, this saves a register write for every interrupt 5550 */ 5551 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << 5552 misc_shift; 5553 regval = E1000_READ_REG(hw, E1000_EIAM); 5554 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask); 5555 5556 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) { 5557 eth_igb_assign_msix_vector(hw, 0, queue_id, vec); 5558 intr_handle->intr_vec[queue_id] = vec; 5559 if (vec < base + intr_handle->nb_efd - 1) 5560 vec++; 5561 } 5562 5563 E1000_WRITE_FLUSH(hw); 5564 } 5565 5566 /* restore n-tuple filter */ 5567 static inline void 5568 igb_ntuple_filter_restore(struct rte_eth_dev *dev) 5569 { 5570 struct e1000_filter_info *filter_info = 5571 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 5572 struct e1000_5tuple_filter *p_5tuple; 5573 struct e1000_2tuple_filter *p_2tuple; 5574 5575 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) { 5576 igb_inject_5tuple_filter_82576(dev, p_5tuple); 5577 } 5578 5579 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) { 5580 igb_inject_2uple_filter(dev, p_2tuple); 5581 } 5582 } 5583 5584 /* restore SYN filter */ 5585 static inline void 5586 igb_syn_filter_restore(struct rte_eth_dev *dev) 5587 { 5588 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5589 struct e1000_filter_info *filter_info = 5590 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 5591 uint32_t synqf; 5592 5593 synqf = filter_info->syn_info; 5594 5595 if (synqf & E1000_SYN_FILTER_ENABLE) { 5596 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf); 5597 E1000_WRITE_FLUSH(hw); 5598 } 5599 } 5600 5601 /* restore ethernet type filter */ 5602 static inline void 5603 igb_ethertype_filter_restore(struct rte_eth_dev *dev) 5604 { 5605 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5606 struct e1000_filter_info *filter_info = 5607 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 5608 int i; 5609 5610 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) { 5611 if (filter_info->ethertype_mask & (1 << i)) { 5612 E1000_WRITE_REG(hw, E1000_ETQF(i), 5613 filter_info->ethertype_filters[i].etqf); 5614 E1000_WRITE_FLUSH(hw); 5615 } 5616 } 5617 } 5618 5619 /* restore flex byte filter */ 5620 static inline void 5621 igb_flex_filter_restore(struct rte_eth_dev *dev) 5622 { 5623 struct e1000_filter_info *filter_info = 5624 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 5625 struct e1000_flex_filter *flex_filter; 5626 5627 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) { 5628 igb_inject_flex_filter(dev, flex_filter); 5629 } 5630 } 5631 5632 /* restore all types filter */ 5633 static int 5634 igb_filter_restore(struct rte_eth_dev *dev) 5635 { 5636 igb_ntuple_filter_restore(dev); 5637 igb_ethertype_filter_restore(dev); 5638 igb_syn_filter_restore(dev); 5639 igb_flex_filter_restore(dev); 5640 5641 return 0; 5642 } 5643 5644 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd); 5645 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map); 5646 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci"); 5647 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd); 5648 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map); 5649 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci"); 5650