1d30ea906Sjfb8856606 /* SPDX-License-Identifier: BSD-3-Clause 22bfe3f2eSlogwang * 32bfe3f2eSlogwang * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. 44418919fSjohnjiang * Copyright 2017-2019 NXP 52bfe3f2eSlogwang * 62bfe3f2eSlogwang */ 72bfe3f2eSlogwang #ifndef __DPAA_ETHDEV_H__ 82bfe3f2eSlogwang #define __DPAA_ETHDEV_H__ 92bfe3f2eSlogwang 102bfe3f2eSlogwang /* System headers */ 112bfe3f2eSlogwang #include <stdbool.h> 12d30ea906Sjfb8856606 #include <rte_ethdev_driver.h> 13d30ea906Sjfb8856606 #include <rte_event_eth_rx_adapter.h> 142bfe3f2eSlogwang 152bfe3f2eSlogwang #include <fsl_usd.h> 162bfe3f2eSlogwang #include <fsl_qman.h> 172bfe3f2eSlogwang #include <fsl_bman.h> 184418919fSjohnjiang #include <dpaa_of.h> 192bfe3f2eSlogwang #include <netcfg.h> 202bfe3f2eSlogwang 214418919fSjohnjiang #define MAX_DPAA_CORES 4 222bfe3f2eSlogwang #define DPAA_MBUF_HW_ANNOTATION 64 232bfe3f2eSlogwang #define DPAA_FD_PTA_SIZE 64 242bfe3f2eSlogwang 252bfe3f2eSlogwang /* we will re-use the HEADROOM for annotation in RX */ 262bfe3f2eSlogwang #define DPAA_HW_BUF_RESERVE 0 272bfe3f2eSlogwang #define DPAA_PACKET_LAYOUT_ALIGN 64 282bfe3f2eSlogwang 292bfe3f2eSlogwang /* Alignment to use for cpu-local structs to avoid coherency problems. */ 302bfe3f2eSlogwang #define MAX_CACHELINE 64 312bfe3f2eSlogwang 322bfe3f2eSlogwang #define DPAA_MAX_RX_PKT_LEN 10240 332bfe3f2eSlogwang 34d30ea906Sjfb8856606 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */ 35d30ea906Sjfb8856606 36d30ea906Sjfb8856606 /* RX queue tail drop threshold (CGR Based) in frame count */ 37d30ea906Sjfb8856606 #define CGR_RX_PERFQ_THRESH 256 38*2d9fd380Sjfb8856606 #define CGR_TX_CGR_THRESH 512 392bfe3f2eSlogwang 402bfe3f2eSlogwang /*max mac filter for memac(8) including primary mac addr*/ 412bfe3f2eSlogwang #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) 422bfe3f2eSlogwang 432bfe3f2eSlogwang /*Maximum number of slots available in TX ring*/ 44d30ea906Sjfb8856606 #define DPAA_TX_BURST_SIZE 7 45d30ea906Sjfb8856606 46d30ea906Sjfb8856606 /* Optimal burst size for RX and TX as default */ 47d30ea906Sjfb8856606 #define DPAA_DEF_RX_BURST_SIZE 7 48d30ea906Sjfb8856606 #define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE 49d30ea906Sjfb8856606 50d30ea906Sjfb8856606 #ifndef VLAN_TAG_SIZE 51d30ea906Sjfb8856606 #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */ 52d30ea906Sjfb8856606 #endif 532bfe3f2eSlogwang 542bfe3f2eSlogwang /* PCD frame queues */ 552bfe3f2eSlogwang #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 56*2d9fd380Sjfb8856606 #define DPAA_VSP_PROFILE_MAX_NUM 8 57*2d9fd380Sjfb8856606 #define DPAA_MAX_NUM_PCD_QUEUES DPAA_VSP_PROFILE_MAX_NUM 58*2d9fd380Sjfb8856606 /*Same as VSP profile number*/ 592bfe3f2eSlogwang 602bfe3f2eSlogwang #define DPAA_IF_TX_PRIORITY 3 61d30ea906Sjfb8856606 #define DPAA_IF_RX_PRIORITY 0 622bfe3f2eSlogwang #define DPAA_IF_DEBUG_PRIORITY 7 632bfe3f2eSlogwang 642bfe3f2eSlogwang #define DPAA_IF_RX_ANNOTATION_STASH 1 652bfe3f2eSlogwang #define DPAA_IF_RX_DATA_STASH 1 662bfe3f2eSlogwang #define DPAA_IF_RX_CONTEXT_STASH 0 672bfe3f2eSlogwang 682bfe3f2eSlogwang /* Each "debug" FQ is represented by one of these */ 692bfe3f2eSlogwang #define DPAA_DEBUG_FQ_RX_ERROR 0 702bfe3f2eSlogwang #define DPAA_DEBUG_FQ_TX_ERROR 1 712bfe3f2eSlogwang 722bfe3f2eSlogwang #define DPAA_RSS_OFFLOAD_ALL ( \ 734418919fSjohnjiang ETH_RSS_L2_PAYLOAD | \ 74d30ea906Sjfb8856606 ETH_RSS_IP | \ 75d30ea906Sjfb8856606 ETH_RSS_UDP | \ 76d30ea906Sjfb8856606 ETH_RSS_TCP | \ 77d30ea906Sjfb8856606 ETH_RSS_SCTP) 782bfe3f2eSlogwang 792bfe3f2eSlogwang #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ 802bfe3f2eSlogwang PKT_TX_IP_CKSUM | \ 812bfe3f2eSlogwang PKT_TX_TCP_CKSUM | \ 822bfe3f2eSlogwang PKT_TX_UDP_CKSUM) 832bfe3f2eSlogwang 842bfe3f2eSlogwang /* DPAA Frame descriptor macros */ 852bfe3f2eSlogwang 862bfe3f2eSlogwang #define DPAA_FD_CMD_FCO 0x80000000 872bfe3f2eSlogwang /**< Frame queue Context Override */ 882bfe3f2eSlogwang #define DPAA_FD_CMD_RPD 0x40000000 892bfe3f2eSlogwang /**< Read Prepended Data */ 902bfe3f2eSlogwang #define DPAA_FD_CMD_UPD 0x20000000 912bfe3f2eSlogwang /**< Update Prepended Data */ 922bfe3f2eSlogwang #define DPAA_FD_CMD_DTC 0x10000000 932bfe3f2eSlogwang /**< Do IP/TCP/UDP Checksum */ 942bfe3f2eSlogwang #define DPAA_FD_CMD_DCL4C 0x10000000 952bfe3f2eSlogwang /**< Didn't calculate L4 Checksum */ 962bfe3f2eSlogwang #define DPAA_FD_CMD_CFQ 0x00ffffff 972bfe3f2eSlogwang /**< Confirmation Frame Queue */ 982bfe3f2eSlogwang 99*2d9fd380Sjfb8856606 #define DPAA_DEFAULT_RXQ_VSP_ID 1 100*2d9fd380Sjfb8856606 101*2d9fd380Sjfb8856606 #define FMC_FILE "/tmp/fmc.bin" 102*2d9fd380Sjfb8856606 1032bfe3f2eSlogwang /* Each network interface is represented by one of these */ 1042bfe3f2eSlogwang struct dpaa_if { 1052bfe3f2eSlogwang int valid; 1062bfe3f2eSlogwang char *name; 1072bfe3f2eSlogwang const struct fm_eth_port_cfg *cfg; 1082bfe3f2eSlogwang struct qman_fq *rx_queues; 109d30ea906Sjfb8856606 struct qman_cgr *cgr_rx; 1102bfe3f2eSlogwang struct qman_fq *tx_queues; 111*2d9fd380Sjfb8856606 struct qman_cgr *cgr_tx; 1122bfe3f2eSlogwang struct qman_fq debug_queues[2]; 1132bfe3f2eSlogwang uint16_t nb_rx_queues; 1142bfe3f2eSlogwang uint16_t nb_tx_queues; 1152bfe3f2eSlogwang uint32_t ifid; 1162bfe3f2eSlogwang struct dpaa_bp_info *bp_info; 1172bfe3f2eSlogwang struct rte_eth_fc_conf *fc_conf; 118*2d9fd380Sjfb8856606 void *port_handle; 119*2d9fd380Sjfb8856606 void *netenv_handle; 120*2d9fd380Sjfb8856606 void *scheme_handle[2]; 121*2d9fd380Sjfb8856606 uint32_t scheme_count; 122*2d9fd380Sjfb8856606 123*2d9fd380Sjfb8856606 void *vsp_handle[DPAA_VSP_PROFILE_MAX_NUM]; 124*2d9fd380Sjfb8856606 uint32_t vsp_bpid[DPAA_VSP_PROFILE_MAX_NUM]; 1252bfe3f2eSlogwang }; 1262bfe3f2eSlogwang 1272bfe3f2eSlogwang struct dpaa_if_stats { 1282bfe3f2eSlogwang /* Rx Statistics Counter */ 1292bfe3f2eSlogwang uint64_t reoct; /**<Rx Eth Octets Counter */ 1302bfe3f2eSlogwang uint64_t roct; /**<Rx Octet Counters */ 1312bfe3f2eSlogwang uint64_t raln; /**<Rx Alignment Error Counter */ 1322bfe3f2eSlogwang uint64_t rxpf; /**<Rx valid Pause Frame */ 1332bfe3f2eSlogwang uint64_t rfrm; /**<Rx Frame counter */ 1342bfe3f2eSlogwang uint64_t rfcs; /**<Rx frame check seq error */ 1352bfe3f2eSlogwang uint64_t rvlan; /**<Rx Vlan Frame Counter */ 1362bfe3f2eSlogwang uint64_t rerr; /**<Rx Frame error */ 1372bfe3f2eSlogwang uint64_t ruca; /**<Rx Unicast */ 1382bfe3f2eSlogwang uint64_t rmca; /**<Rx Multicast */ 1392bfe3f2eSlogwang uint64_t rbca; /**<Rx Broadcast */ 1402bfe3f2eSlogwang uint64_t rdrp; /**<Rx Dropped Packet */ 1412bfe3f2eSlogwang uint64_t rpkt; /**<Rx packet */ 1422bfe3f2eSlogwang uint64_t rund; /**<Rx undersized packets */ 1432bfe3f2eSlogwang uint32_t res_x[14]; 1442bfe3f2eSlogwang uint64_t rovr; /**<Rx oversized but good */ 1452bfe3f2eSlogwang uint64_t rjbr; /**<Rx oversized with bad csum */ 1462bfe3f2eSlogwang uint64_t rfrg; /**<Rx fragment Packet */ 1472bfe3f2eSlogwang uint64_t rcnp; /**<Rx control packets (0x8808 */ 1482bfe3f2eSlogwang uint64_t rdrntp; /**<Rx dropped due to FIFO overflow */ 1492bfe3f2eSlogwang uint32_t res01d0[12]; 1502bfe3f2eSlogwang /* Tx Statistics Counter */ 1512bfe3f2eSlogwang uint64_t teoct; /**<Tx eth octets */ 1522bfe3f2eSlogwang uint64_t toct; /**<Tx Octets */ 1532bfe3f2eSlogwang uint32_t res0210[2]; 1542bfe3f2eSlogwang uint64_t txpf; /**<Tx valid pause frame */ 1552bfe3f2eSlogwang uint64_t tfrm; /**<Tx frame counter */ 1562bfe3f2eSlogwang uint64_t tfcs; /**<Tx FCS error */ 1572bfe3f2eSlogwang uint64_t tvlan; /**<Tx Vlan Frame */ 1582bfe3f2eSlogwang uint64_t terr; /**<Tx frame error */ 1592bfe3f2eSlogwang uint64_t tuca; /**<Tx Unicast */ 1602bfe3f2eSlogwang uint64_t tmca; /**<Tx Multicast */ 1612bfe3f2eSlogwang uint64_t tbca; /**<Tx Broadcast */ 1622bfe3f2eSlogwang uint32_t res0258[2]; 1632bfe3f2eSlogwang uint64_t tpkt; /**<Tx Packet */ 1642bfe3f2eSlogwang uint64_t tund; /**<Tx Undersized */ 1652bfe3f2eSlogwang }; 1662bfe3f2eSlogwang 167*2d9fd380Sjfb8856606 __rte_internal 168d30ea906Sjfb8856606 int 169d30ea906Sjfb8856606 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 170d30ea906Sjfb8856606 int eth_rx_queue_id, 171d30ea906Sjfb8856606 u16 ch_id, 172d30ea906Sjfb8856606 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf); 173d30ea906Sjfb8856606 174*2d9fd380Sjfb8856606 __rte_internal 175d30ea906Sjfb8856606 int 176d30ea906Sjfb8856606 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 177d30ea906Sjfb8856606 int eth_rx_queue_id); 178d30ea906Sjfb8856606 179d30ea906Sjfb8856606 enum qman_cb_dqrr_result 180d30ea906Sjfb8856606 dpaa_rx_cb_parallel(void *event, 181d30ea906Sjfb8856606 struct qman_portal *qm __always_unused, 182d30ea906Sjfb8856606 struct qman_fq *fq, 183d30ea906Sjfb8856606 const struct qm_dqrr_entry *dqrr, 184d30ea906Sjfb8856606 void **bufs); 185d30ea906Sjfb8856606 enum qman_cb_dqrr_result 186d30ea906Sjfb8856606 dpaa_rx_cb_atomic(void *event, 187d30ea906Sjfb8856606 struct qman_portal *qm __always_unused, 188d30ea906Sjfb8856606 struct qman_fq *fq, 189d30ea906Sjfb8856606 const struct qm_dqrr_entry *dqrr, 190d30ea906Sjfb8856606 void **bufs); 191d30ea906Sjfb8856606 192*2d9fd380Sjfb8856606 /* PMD related logs */ 193*2d9fd380Sjfb8856606 extern int dpaa_logtype_pmd; 194*2d9fd380Sjfb8856606 195*2d9fd380Sjfb8856606 #define DPAA_PMD_LOG(level, fmt, args...) \ 196*2d9fd380Sjfb8856606 rte_log(RTE_LOG_ ## level, dpaa_logtype_pmd, "%s(): " fmt "\n", \ 197*2d9fd380Sjfb8856606 __func__, ##args) 198*2d9fd380Sjfb8856606 199*2d9fd380Sjfb8856606 #define PMD_INIT_FUNC_TRACE() DPAA_PMD_LOG(DEBUG, " >>") 200*2d9fd380Sjfb8856606 201*2d9fd380Sjfb8856606 #define DPAA_PMD_DEBUG(fmt, args...) \ 202*2d9fd380Sjfb8856606 DPAA_PMD_LOG(DEBUG, fmt, ## args) 203*2d9fd380Sjfb8856606 #define DPAA_PMD_ERR(fmt, args...) \ 204*2d9fd380Sjfb8856606 DPAA_PMD_LOG(ERR, fmt, ## args) 205*2d9fd380Sjfb8856606 #define DPAA_PMD_INFO(fmt, args...) \ 206*2d9fd380Sjfb8856606 DPAA_PMD_LOG(INFO, fmt, ## args) 207*2d9fd380Sjfb8856606 #define DPAA_PMD_WARN(fmt, args...) \ 208*2d9fd380Sjfb8856606 DPAA_PMD_LOG(WARNING, fmt, ## args) 209*2d9fd380Sjfb8856606 210*2d9fd380Sjfb8856606 /* DP Logs, toggled out at compile time if level lower than current level */ 211*2d9fd380Sjfb8856606 #define DPAA_DP_LOG(level, fmt, args...) \ 212*2d9fd380Sjfb8856606 RTE_LOG_DP(level, PMD, fmt, ## args) 213*2d9fd380Sjfb8856606 2142bfe3f2eSlogwang #endif 215