1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014-2017 Chelsio Communications. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Chelsio Communications nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _CXGBE_COMPAT_H_ 35 #define _CXGBE_COMPAT_H_ 36 37 #include <string.h> 38 #include <stdint.h> 39 #include <stdio.h> 40 #include <stdarg.h> 41 42 #include <rte_common.h> 43 #include <rte_memcpy.h> 44 #include <rte_byteorder.h> 45 #include <rte_cycles.h> 46 #include <rte_spinlock.h> 47 #include <rte_log.h> 48 #include <rte_io.h> 49 50 #define dev_printf(level, fmt, args...) \ 51 RTE_LOG(level, PMD, "rte_cxgbe_pmd: " fmt, ## args) 52 53 #define dev_err(x, args...) dev_printf(ERR, args) 54 #define dev_info(x, args...) dev_printf(INFO, args) 55 #define dev_warn(x, args...) dev_printf(WARNING, args) 56 57 #ifdef RTE_LIBRTE_CXGBE_DEBUG 58 #define dev_debug(x, args...) dev_printf(DEBUG, args) 59 #else 60 #define dev_debug(x, args...) do { } while (0) 61 #endif 62 63 #ifdef RTE_LIBRTE_CXGBE_DEBUG_REG 64 #define CXGBE_DEBUG_REG(x, args...) dev_printf(DEBUG, "REG:" args) 65 #else 66 #define CXGBE_DEBUG_REG(x, args...) do { } while (0) 67 #endif 68 69 #ifdef RTE_LIBRTE_CXGBE_DEBUG_MBOX 70 #define CXGBE_DEBUG_MBOX(x, args...) dev_printf(DEBUG, "MBOX:" args) 71 #else 72 #define CXGBE_DEBUG_MBOX(x, args...) do { } while (0) 73 #endif 74 75 #ifdef RTE_LIBRTE_CXGBE_DEBUG_TX 76 #define CXGBE_DEBUG_TX(x, args...) dev_printf(DEBUG, "TX:" args) 77 #else 78 #define CXGBE_DEBUG_TX(x, args...) do { } while (0) 79 #endif 80 81 #ifdef RTE_LIBRTE_CXGBE_DEBUG_RX 82 #define CXGBE_DEBUG_RX(x, args...) dev_printf(DEBUG, "RX:" args) 83 #else 84 #define CXGBE_DEBUG_RX(x, args...) do { } while (0) 85 #endif 86 87 #ifdef RTE_LIBRTE_CXGBE_DEBUG 88 #define CXGBE_FUNC_TRACE() \ 89 RTE_LOG(DEBUG, PMD, "CXGBE trace: %s\n", __func__) 90 #else 91 #define CXGBE_FUNC_TRACE() do { } while (0) 92 #endif 93 94 #define pr_err(y, args...) dev_err(0, y, ##args) 95 #define pr_warn(y, args...) dev_warn(0, y, ##args) 96 #define pr_info(y, args...) dev_info(0, y, ##args) 97 #define BUG() pr_err("BUG at %s:%d", __func__, __LINE__) 98 99 #define ASSERT(x) do {\ 100 if (!(x)) \ 101 rte_panic("CXGBE: x"); \ 102 } while (0) 103 #define BUG_ON(x) ASSERT(!(x)) 104 105 #ifndef WARN_ON 106 #define WARN_ON(x) do { \ 107 int ret = !!(x); \ 108 if (unlikely(ret)) \ 109 pr_warn("WARN_ON: \"" #x "\" at %s:%d\n", __func__, __LINE__); \ 110 } while (0) 111 #endif 112 113 #define __iomem 114 115 #ifndef BIT 116 #define BIT(n) (1 << (n)) 117 #endif 118 119 #define L1_CACHE_SHIFT 6 120 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 121 122 #define PAGE_SHIFT 12 123 #define CXGBE_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) 124 #define PTR_ALIGN(p, a) ((typeof(p))CXGBE_ALIGN((unsigned long)(p), (a))) 125 126 #define VLAN_HLEN 4 127 128 #define rmb() rte_rmb() /* dpdk rte provided rmb */ 129 #define wmb() rte_wmb() /* dpdk rte provided wmb */ 130 131 typedef uint8_t u8; 132 typedef int8_t s8; 133 typedef uint16_t u16; 134 typedef uint32_t u32; 135 typedef int32_t s32; 136 typedef uint64_t u64; 137 typedef int bool; 138 typedef uint64_t dma_addr_t; 139 140 #ifndef __le16 141 #define __le16 uint16_t 142 #endif 143 #ifndef __le32 144 #define __le32 uint32_t 145 #endif 146 #ifndef __le64 147 #define __le64 uint64_t 148 #endif 149 #ifndef __be16 150 #define __be16 uint16_t 151 #endif 152 #ifndef __be32 153 #define __be32 uint32_t 154 #endif 155 #ifndef __be64 156 #define __be64 uint64_t 157 #endif 158 #ifndef __u8 159 #define __u8 uint8_t 160 #endif 161 #ifndef __u16 162 #define __u16 uint16_t 163 #endif 164 #ifndef __u32 165 #define __u32 uint32_t 166 #endif 167 #ifndef __u64 168 #define __u64 uint64_t 169 #endif 170 171 #define FALSE 0 172 #define TRUE 1 173 #define false 0 174 #define true 1 175 176 #define min(a, b) RTE_MIN(a, b) 177 #define max(a, b) RTE_MAX(a, b) 178 179 /* 180 * round up val _p to a power of 2 size _s 181 */ 182 #define cxgbe_roundup(_p, _s) (((unsigned long)(_p) + (_s - 1)) & ~(_s - 1)) 183 184 #undef container_of 185 #define container_of(ptr, type, member) ({ \ 186 typeof(((type *)0)->member)(*__mptr) = (ptr); \ 187 (type *)((char *)__mptr - offsetof(type, member)); }) 188 189 #define ARRAY_SIZE(arr) RTE_DIM(arr) 190 191 #define cpu_to_be16(o) rte_cpu_to_be_16(o) 192 #define cpu_to_be32(o) rte_cpu_to_be_32(o) 193 #define cpu_to_be64(o) rte_cpu_to_be_64(o) 194 #define cpu_to_le32(o) rte_cpu_to_le_32(o) 195 #define be16_to_cpu(o) rte_be_to_cpu_16(o) 196 #define be32_to_cpu(o) rte_be_to_cpu_32(o) 197 #define be64_to_cpu(o) rte_be_to_cpu_64(o) 198 #define le32_to_cpu(o) rte_le_to_cpu_32(o) 199 200 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 201 #define DELAY(x) rte_delay_us(x) 202 #define udelay(x) DELAY(x) 203 #define msleep(x) DELAY(1000 * (x)) 204 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000)) 205 206 static inline uint8_t hweight32(uint32_t word32) 207 { 208 uint32_t res = word32 - ((word32 >> 1) & 0x55555555); 209 210 res = (res & 0x33333333) + ((res >> 2) & 0x33333333); 211 res = (res + (res >> 4)) & 0x0F0F0F0F; 212 res = res + (res >> 8); 213 return (res + (res >> 16)) & 0x000000FF; 214 215 } /* weight32 */ 216 217 /** 218 * cxgbe_fls - find last (most-significant) bit set 219 * @x: the word to search 220 * 221 * This is defined the same way as ffs. 222 * Note cxgbe_fls(0) = 0, cxgbe_fls(1) = 1, cxgbe_fls(0x80000000) = 32. 223 */ 224 static inline int cxgbe_fls(int x) 225 { 226 return x ? sizeof(x) * 8 - __builtin_clz(x) : 0; 227 } 228 229 static inline unsigned long ilog2(unsigned long n) 230 { 231 unsigned int e = 0; 232 233 while (n) { 234 if (n & ~((1 << 8) - 1)) { 235 e += 8; 236 n >>= 8; 237 continue; 238 } 239 240 if (n & ~((1 << 4) - 1)) { 241 e += 4; 242 n >>= 4; 243 } 244 245 for (;;) { 246 n >>= 1; 247 if (n == 0) 248 break; 249 e++; 250 } 251 } 252 253 return e; 254 } 255 256 static inline void writel(unsigned int val, volatile void __iomem *addr) 257 { 258 rte_write32(val, addr); 259 } 260 261 static inline void writeq(u64 val, volatile void __iomem *addr) 262 { 263 writel(val, addr); 264 writel(val >> 32, (void *)((uintptr_t)addr + 4)); 265 } 266 267 static inline void writel_relaxed(unsigned int val, volatile void __iomem *addr) 268 { 269 rte_write32_relaxed(val, addr); 270 } 271 272 #endif /* _CXGBE_COMPAT_H_ */ 273