1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) Broadcom Limited. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Broadcom Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <inttypes.h> 35 #include <stdbool.h> 36 37 #include <rte_dev.h> 38 #include <rte_ethdev.h> 39 #include <rte_malloc.h> 40 #include <rte_cycles.h> 41 42 #include "bnxt.h" 43 #include "bnxt_cpr.h" 44 #include "bnxt_filter.h" 45 #include "bnxt_hwrm.h" 46 #include "bnxt_ring.h" 47 #include "bnxt_rxq.h" 48 #include "bnxt_rxr.h" 49 #include "bnxt_stats.h" 50 #include "bnxt_txq.h" 51 #include "bnxt_txr.h" 52 #include "bnxt_vnic.h" 53 #include "hsi_struct_def_dpdk.h" 54 55 #define DRV_MODULE_NAME "bnxt" 56 static const char bnxt_version[] = 57 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n"; 58 59 #define PCI_VENDOR_ID_BROADCOM 0x14E4 60 61 #define BROADCOM_DEV_ID_57301 0x16c8 62 #define BROADCOM_DEV_ID_57302 0x16c9 63 #define BROADCOM_DEV_ID_57304_PF 0x16ca 64 #define BROADCOM_DEV_ID_57304_VF 0x16cb 65 #define BROADCOM_DEV_ID_57402 0x16d0 66 #define BROADCOM_DEV_ID_57404 0x16d1 67 #define BROADCOM_DEV_ID_57406_PF 0x16d2 68 #define BROADCOM_DEV_ID_57406_VF 0x16d3 69 #define BROADCOM_DEV_ID_57406_MF 0x16d4 70 #define BROADCOM_DEV_ID_57314 0x16df 71 72 static struct rte_pci_id bnxt_pci_id_map[] = { 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 83 { .vendor_id = 0, /* sentinel */ }, 84 }; 85 86 #define BNXT_ETH_RSS_SUPPORT ( \ 87 ETH_RSS_IPV4 | \ 88 ETH_RSS_NONFRAG_IPV4_TCP | \ 89 ETH_RSS_NONFRAG_IPV4_UDP | \ 90 ETH_RSS_IPV6 | \ 91 ETH_RSS_NONFRAG_IPV6_TCP | \ 92 ETH_RSS_NONFRAG_IPV6_UDP) 93 94 /***********************/ 95 96 /* 97 * High level utility functions 98 */ 99 100 static void bnxt_free_mem(struct bnxt *bp) 101 { 102 bnxt_free_filter_mem(bp); 103 bnxt_free_vnic_attributes(bp); 104 bnxt_free_vnic_mem(bp); 105 106 bnxt_free_stats(bp); 107 bnxt_free_tx_rings(bp); 108 bnxt_free_rx_rings(bp); 109 bnxt_free_def_cp_ring(bp); 110 } 111 112 static int bnxt_alloc_mem(struct bnxt *bp) 113 { 114 int rc; 115 116 /* Default completion ring */ 117 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY); 118 if (rc) 119 goto alloc_mem_err; 120 121 rc = bnxt_alloc_rings(bp, 0, NULL, NULL, 122 bp->def_cp_ring, "def_cp"); 123 if (rc) 124 goto alloc_mem_err; 125 126 rc = bnxt_alloc_vnic_mem(bp); 127 if (rc) 128 goto alloc_mem_err; 129 130 rc = bnxt_alloc_vnic_attributes(bp); 131 if (rc) 132 goto alloc_mem_err; 133 134 rc = bnxt_alloc_filter_mem(bp); 135 if (rc) 136 goto alloc_mem_err; 137 138 return 0; 139 140 alloc_mem_err: 141 bnxt_free_mem(bp); 142 return rc; 143 } 144 145 static int bnxt_init_chip(struct bnxt *bp) 146 { 147 unsigned int i, rss_idx, fw_idx; 148 int rc; 149 150 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 151 if (rc) { 152 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc); 153 goto err_out; 154 } 155 156 rc = bnxt_alloc_hwrm_rings(bp); 157 if (rc) { 158 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc); 159 goto err_out; 160 } 161 162 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 163 if (rc) { 164 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc); 165 goto err_out; 166 } 167 168 rc = bnxt_mq_rx_configure(bp); 169 if (rc) { 170 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc); 171 goto err_out; 172 } 173 174 /* VNIC configuration */ 175 for (i = 0; i < bp->nr_vnics; i++) { 176 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 177 178 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 179 if (rc) { 180 RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n", 181 rc); 182 goto err_out; 183 } 184 185 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic); 186 if (rc) { 187 RTE_LOG(ERR, PMD, 188 "HWRM vnic ctx alloc failure rc: %x\n", rc); 189 goto err_out; 190 } 191 192 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 193 if (rc) { 194 RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc); 195 goto err_out; 196 } 197 198 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 199 if (rc) { 200 RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n", 201 rc); 202 goto err_out; 203 } 204 if (vnic->rss_table && vnic->hash_type) { 205 /* 206 * Fill the RSS hash & redirection table with 207 * ring group ids for all VNICs 208 */ 209 for (rss_idx = 0, fw_idx = 0; 210 rss_idx < HW_HASH_INDEX_SIZE; 211 rss_idx++, fw_idx++) { 212 if (vnic->fw_grp_ids[fw_idx] == 213 INVALID_HW_RING_ID) 214 fw_idx = 0; 215 vnic->rss_table[rss_idx] = 216 vnic->fw_grp_ids[fw_idx]; 217 } 218 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 219 if (rc) { 220 RTE_LOG(ERR, PMD, 221 "HWRM vnic set RSS failure rc: %x\n", 222 rc); 223 goto err_out; 224 } 225 } 226 } 227 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]); 228 if (rc) { 229 RTE_LOG(ERR, PMD, 230 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 231 goto err_out; 232 } 233 234 return 0; 235 236 err_out: 237 bnxt_free_all_hwrm_resources(bp); 238 239 return rc; 240 } 241 242 static int bnxt_shutdown_nic(struct bnxt *bp) 243 { 244 bnxt_free_all_hwrm_resources(bp); 245 bnxt_free_all_filters(bp); 246 bnxt_free_all_vnics(bp); 247 return 0; 248 } 249 250 static int bnxt_init_nic(struct bnxt *bp) 251 { 252 int rc; 253 254 bnxt_init_ring_grps(bp); 255 bnxt_init_vnics(bp); 256 bnxt_init_filters(bp); 257 258 rc = bnxt_init_chip(bp); 259 if (rc) 260 return rc; 261 262 return 0; 263 } 264 265 /* 266 * Device configuration and status function 267 */ 268 269 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 270 struct rte_eth_dev_info *dev_info) 271 { 272 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 273 uint16_t max_vnics, i, j, vpool, vrxq; 274 275 /* MAC Specifics */ 276 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR; 277 dev_info->max_hash_mac_addrs = 0; 278 279 /* PF/VF specifics */ 280 if (BNXT_PF(bp)) { 281 dev_info->max_rx_queues = bp->pf.max_rx_rings; 282 dev_info->max_tx_queues = bp->pf.max_tx_rings; 283 dev_info->max_vfs = bp->pf.active_vfs; 284 dev_info->reta_size = bp->pf.max_rsscos_ctx; 285 max_vnics = bp->pf.max_vnics; 286 } else { 287 dev_info->max_rx_queues = bp->vf.max_rx_rings; 288 dev_info->max_tx_queues = bp->vf.max_tx_rings; 289 dev_info->reta_size = bp->vf.max_rsscos_ctx; 290 max_vnics = bp->vf.max_vnics; 291 } 292 293 /* Fast path specifics */ 294 dev_info->min_rx_bufsize = 1; 295 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN 296 + VLAN_TAG_SIZE; 297 dev_info->rx_offload_capa = 0; 298 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM | 299 DEV_TX_OFFLOAD_TCP_CKSUM | 300 DEV_TX_OFFLOAD_UDP_CKSUM | 301 DEV_TX_OFFLOAD_TCP_TSO; 302 303 /* *INDENT-OFF* */ 304 dev_info->default_rxconf = (struct rte_eth_rxconf) { 305 .rx_thresh = { 306 .pthresh = 8, 307 .hthresh = 8, 308 .wthresh = 0, 309 }, 310 .rx_free_thresh = 32, 311 .rx_drop_en = 0, 312 }; 313 314 dev_info->default_txconf = (struct rte_eth_txconf) { 315 .tx_thresh = { 316 .pthresh = 32, 317 .hthresh = 0, 318 .wthresh = 0, 319 }, 320 .tx_free_thresh = 32, 321 .tx_rs_thresh = 32, 322 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | 323 ETH_TXQ_FLAGS_NOOFFLOADS, 324 }; 325 /* *INDENT-ON* */ 326 327 /* 328 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 329 * need further investigation. 330 */ 331 332 /* VMDq resources */ 333 vpool = 64; /* ETH_64_POOLS */ 334 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 335 for (i = 0; i < 4; vpool >>= 1, i++) { 336 if (max_vnics > vpool) { 337 for (j = 0; j < 5; vrxq >>= 1, j++) { 338 if (dev_info->max_rx_queues > vrxq) { 339 if (vpool > vrxq) 340 vpool = vrxq; 341 goto found; 342 } 343 } 344 /* Not enough resources to support VMDq */ 345 break; 346 } 347 } 348 /* Not enough resources to support VMDq */ 349 vpool = 0; 350 vrxq = 0; 351 found: 352 dev_info->max_vmdq_pools = vpool; 353 dev_info->vmdq_queue_num = vrxq; 354 355 dev_info->vmdq_pool_base = 0; 356 dev_info->vmdq_queue_base = 0; 357 } 358 359 /* Configure the device based on the configuration provided */ 360 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 361 { 362 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 363 int rc; 364 365 bp->rx_queues = (void *)eth_dev->data->rx_queues; 366 bp->tx_queues = (void *)eth_dev->data->tx_queues; 367 368 /* Inherit new configurations */ 369 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 370 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 371 bp->rx_cp_nr_rings = bp->rx_nr_rings; 372 bp->tx_cp_nr_rings = bp->tx_nr_rings; 373 374 if (eth_dev->data->dev_conf.rxmode.jumbo_frame) 375 eth_dev->data->mtu = 376 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 377 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE; 378 rc = bnxt_set_hwrm_link_config(bp, true); 379 return rc; 380 } 381 382 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 383 { 384 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 385 int rc; 386 387 bp->dev_stopped = 0; 388 rc = bnxt_hwrm_func_reset(bp); 389 if (rc) { 390 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc); 391 rc = -1; 392 goto error; 393 } 394 395 rc = bnxt_alloc_mem(bp); 396 if (rc) 397 goto error; 398 399 rc = bnxt_init_nic(bp); 400 if (rc) 401 goto error; 402 403 return 0; 404 405 error: 406 bnxt_shutdown_nic(bp); 407 bnxt_free_tx_mbufs(bp); 408 bnxt_free_rx_mbufs(bp); 409 bnxt_free_mem(bp); 410 return rc; 411 } 412 413 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 414 { 415 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 416 417 eth_dev->data->dev_link.link_status = 1; 418 bnxt_set_hwrm_link_config(bp, true); 419 return 0; 420 } 421 422 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 423 { 424 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 425 426 eth_dev->data->dev_link.link_status = 0; 427 bnxt_set_hwrm_link_config(bp, false); 428 return 0; 429 } 430 431 /* Unload the driver, release resources */ 432 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 433 { 434 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 435 436 if (bp->eth_dev->data->dev_started) { 437 /* TBD: STOP HW queues DMA */ 438 eth_dev->data->dev_link.link_status = 0; 439 } 440 bnxt_shutdown_nic(bp); 441 } 442 443 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 444 { 445 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 446 447 if (bp->dev_stopped == 0) 448 bnxt_dev_stop_op(eth_dev); 449 450 bnxt_free_tx_mbufs(bp); 451 bnxt_free_rx_mbufs(bp); 452 bnxt_free_mem(bp); 453 rte_free(eth_dev->data->mac_addrs); 454 } 455 456 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 457 uint32_t index) 458 { 459 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 460 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 461 struct bnxt_vnic_info *vnic; 462 struct bnxt_filter_info *filter, *temp_filter; 463 int i; 464 465 /* 466 * Loop through all VNICs from the specified filter flow pools to 467 * remove the corresponding MAC addr filter 468 */ 469 for (i = 0; i < MAX_FF_POOLS; i++) { 470 if (!(pool_mask & (1ULL << i))) 471 continue; 472 473 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 474 filter = STAILQ_FIRST(&vnic->filter); 475 while (filter) { 476 temp_filter = STAILQ_NEXT(filter, next); 477 if (filter->mac_index == index) { 478 STAILQ_REMOVE(&vnic->filter, filter, 479 bnxt_filter_info, next); 480 bnxt_hwrm_clear_filter(bp, filter); 481 filter->mac_index = INVALID_MAC_INDEX; 482 memset(&filter->l2_addr, 0, 483 ETHER_ADDR_LEN); 484 STAILQ_INSERT_TAIL( 485 &bp->free_filter_list, 486 filter, next); 487 } 488 filter = temp_filter; 489 } 490 } 491 } 492 } 493 494 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 495 struct ether_addr *mac_addr, 496 uint32_t index, uint32_t pool) 497 { 498 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 499 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]); 500 struct bnxt_filter_info *filter; 501 502 if (!vnic) { 503 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool); 504 return; 505 } 506 /* Attach requested MAC address to the new l2_filter */ 507 STAILQ_FOREACH(filter, &vnic->filter, next) { 508 if (filter->mac_index == index) { 509 RTE_LOG(ERR, PMD, 510 "MAC addr already existed for pool %d\n", pool); 511 return; 512 } 513 } 514 filter = bnxt_alloc_filter(bp); 515 if (!filter) { 516 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n"); 517 return; 518 } 519 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 520 filter->mac_index = index; 521 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN); 522 bnxt_hwrm_set_filter(bp, vnic, filter); 523 } 524 525 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 526 int wait_to_complete) 527 { 528 int rc = 0; 529 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 530 struct rte_eth_link new; 531 unsigned int cnt = BNXT_LINK_WAIT_CNT; 532 533 memset(&new, 0, sizeof(new)); 534 do { 535 /* Retrieve link info from hardware */ 536 rc = bnxt_get_hwrm_link_config(bp, &new); 537 if (rc) { 538 new.link_speed = ETH_LINK_SPEED_100M; 539 new.link_duplex = ETH_LINK_FULL_DUPLEX; 540 RTE_LOG(ERR, PMD, 541 "Failed to retrieve link rc = 0x%x!", rc); 542 goto out; 543 } 544 if (!wait_to_complete) 545 break; 546 547 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 548 549 } while (!new.link_status && cnt--); 550 551 /* Timed out or success */ 552 if (new.link_status) { 553 /* Update only if success */ 554 eth_dev->data->dev_link.link_duplex = new.link_duplex; 555 eth_dev->data->dev_link.link_speed = new.link_speed; 556 } 557 eth_dev->data->dev_link.link_status = new.link_status; 558 out: 559 return rc; 560 } 561 562 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 563 { 564 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 565 struct bnxt_vnic_info *vnic; 566 567 if (bp->vnic_info == NULL) 568 return; 569 570 vnic = &bp->vnic_info[0]; 571 572 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 573 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic); 574 } 575 576 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 577 { 578 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 579 struct bnxt_vnic_info *vnic; 580 581 if (bp->vnic_info == NULL) 582 return; 583 584 vnic = &bp->vnic_info[0]; 585 586 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 587 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic); 588 } 589 590 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 591 { 592 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 593 struct bnxt_vnic_info *vnic; 594 595 if (bp->vnic_info == NULL) 596 return; 597 598 vnic = &bp->vnic_info[0]; 599 600 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 601 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic); 602 } 603 604 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 605 { 606 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 607 struct bnxt_vnic_info *vnic; 608 609 if (bp->vnic_info == NULL) 610 return; 611 612 vnic = &bp->vnic_info[0]; 613 614 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 615 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic); 616 } 617 618 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 619 struct rte_eth_rss_reta_entry64 *reta_conf, 620 uint16_t reta_size) 621 { 622 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 623 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 624 struct bnxt_vnic_info *vnic; 625 int i; 626 627 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 628 return -EINVAL; 629 630 if (reta_size != HW_HASH_INDEX_SIZE) { 631 RTE_LOG(ERR, PMD, "The configured hash table lookup size " 632 "(%d) must equal the size supported by the hardware " 633 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 634 return -EINVAL; 635 } 636 /* Update the RSS VNIC(s) */ 637 for (i = 0; i < MAX_FF_POOLS; i++) { 638 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 639 memcpy(vnic->rss_table, reta_conf, reta_size); 640 641 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 642 } 643 } 644 return 0; 645 } 646 647 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 648 struct rte_eth_rss_reta_entry64 *reta_conf, 649 uint16_t reta_size) 650 { 651 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 652 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 653 654 /* Retrieve from the default VNIC */ 655 if (!vnic) 656 return -EINVAL; 657 if (!vnic->rss_table) 658 return -EINVAL; 659 660 if (reta_size != HW_HASH_INDEX_SIZE) { 661 RTE_LOG(ERR, PMD, "The configured hash table lookup size " 662 "(%d) must equal the size supported by the hardware " 663 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 664 return -EINVAL; 665 } 666 /* EW - need to revisit here copying from u64 to u16 */ 667 memcpy(reta_conf, vnic->rss_table, reta_size); 668 669 return 0; 670 } 671 672 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 673 struct rte_eth_rss_conf *rss_conf) 674 { 675 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 676 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 677 struct bnxt_vnic_info *vnic; 678 uint16_t hash_type = 0; 679 int i; 680 681 /* 682 * If RSS enablement were different than dev_configure, 683 * then return -EINVAL 684 */ 685 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 686 if (!rss_conf->rss_hf) 687 return -EINVAL; 688 } else { 689 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 690 return -EINVAL; 691 } 692 if (rss_conf->rss_hf & ETH_RSS_IPV4) 693 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 694 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 695 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 696 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 697 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 698 if (rss_conf->rss_hf & ETH_RSS_IPV6) 699 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 700 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 701 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 702 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 703 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 704 705 /* Update the RSS VNIC(s) */ 706 for (i = 0; i < MAX_FF_POOLS; i++) { 707 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 708 vnic->hash_type = hash_type; 709 710 /* 711 * Use the supplied key if the key length is 712 * acceptable and the rss_key is not NULL 713 */ 714 if (rss_conf->rss_key && 715 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE) 716 memcpy(vnic->rss_hash_key, rss_conf->rss_key, 717 rss_conf->rss_key_len); 718 719 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 720 } 721 } 722 return 0; 723 } 724 725 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 726 struct rte_eth_rss_conf *rss_conf) 727 { 728 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 729 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 730 int len; 731 uint32_t hash_types; 732 733 /* RSS configuration is the same for all VNICs */ 734 if (vnic && vnic->rss_hash_key) { 735 if (rss_conf->rss_key) { 736 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 737 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 738 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 739 } 740 741 hash_types = vnic->hash_type; 742 rss_conf->rss_hf = 0; 743 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 744 rss_conf->rss_hf |= ETH_RSS_IPV4; 745 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 746 } 747 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 748 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 749 hash_types &= 750 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 751 } 752 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 753 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 754 hash_types &= 755 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 756 } 757 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 758 rss_conf->rss_hf |= ETH_RSS_IPV6; 759 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 760 } 761 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 762 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 763 hash_types &= 764 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 765 } 766 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 767 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 768 hash_types &= 769 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 770 } 771 if (hash_types) { 772 RTE_LOG(ERR, PMD, 773 "Unknwon RSS config from firmware (%08x), RSS disabled", 774 vnic->hash_type); 775 return -ENOTSUP; 776 } 777 } else { 778 rss_conf->rss_hf = 0; 779 } 780 return 0; 781 } 782 783 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 784 struct rte_eth_fc_conf *fc_conf __rte_unused) 785 { 786 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 787 struct rte_eth_link link_info; 788 int rc; 789 790 rc = bnxt_get_hwrm_link_config(bp, &link_info); 791 if (rc) 792 return rc; 793 794 memset(fc_conf, 0, sizeof(*fc_conf)); 795 if (bp->link_info.auto_pause) 796 fc_conf->autoneg = 1; 797 switch (bp->link_info.pause) { 798 case 0: 799 fc_conf->mode = RTE_FC_NONE; 800 break; 801 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 802 fc_conf->mode = RTE_FC_TX_PAUSE; 803 break; 804 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 805 fc_conf->mode = RTE_FC_RX_PAUSE; 806 break; 807 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 808 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 809 fc_conf->mode = RTE_FC_FULL; 810 break; 811 } 812 return 0; 813 } 814 815 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 816 struct rte_eth_fc_conf *fc_conf) 817 { 818 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 819 820 switch (fc_conf->mode) { 821 case RTE_FC_NONE: 822 bp->link_info.auto_pause = 0; 823 bp->link_info.force_pause = 0; 824 break; 825 case RTE_FC_RX_PAUSE: 826 if (fc_conf->autoneg) { 827 bp->link_info.auto_pause = 828 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 829 bp->link_info.force_pause = 0; 830 } else { 831 bp->link_info.auto_pause = 0; 832 bp->link_info.force_pause = 833 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 834 } 835 break; 836 case RTE_FC_TX_PAUSE: 837 if (fc_conf->autoneg) { 838 bp->link_info.auto_pause = 839 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 840 bp->link_info.force_pause = 0; 841 } else { 842 bp->link_info.auto_pause = 0; 843 bp->link_info.force_pause = 844 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 845 } 846 break; 847 case RTE_FC_FULL: 848 if (fc_conf->autoneg) { 849 bp->link_info.auto_pause = 850 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 851 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 852 bp->link_info.force_pause = 0; 853 } else { 854 bp->link_info.auto_pause = 0; 855 bp->link_info.force_pause = 856 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 857 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 858 } 859 break; 860 } 861 return bnxt_set_hwrm_link_config(bp, true); 862 } 863 864 /* 865 * Initialization 866 */ 867 868 static struct eth_dev_ops bnxt_dev_ops = { 869 .dev_infos_get = bnxt_dev_info_get_op, 870 .dev_close = bnxt_dev_close_op, 871 .dev_configure = bnxt_dev_configure_op, 872 .dev_start = bnxt_dev_start_op, 873 .dev_stop = bnxt_dev_stop_op, 874 .dev_set_link_up = bnxt_dev_set_link_up_op, 875 .dev_set_link_down = bnxt_dev_set_link_down_op, 876 .stats_get = bnxt_stats_get_op, 877 .stats_reset = bnxt_stats_reset_op, 878 .rx_queue_setup = bnxt_rx_queue_setup_op, 879 .rx_queue_release = bnxt_rx_queue_release_op, 880 .tx_queue_setup = bnxt_tx_queue_setup_op, 881 .tx_queue_release = bnxt_tx_queue_release_op, 882 .reta_update = bnxt_reta_update_op, 883 .reta_query = bnxt_reta_query_op, 884 .rss_hash_update = bnxt_rss_hash_update_op, 885 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 886 .link_update = bnxt_link_update_op, 887 .promiscuous_enable = bnxt_promiscuous_enable_op, 888 .promiscuous_disable = bnxt_promiscuous_disable_op, 889 .allmulticast_enable = bnxt_allmulticast_enable_op, 890 .allmulticast_disable = bnxt_allmulticast_disable_op, 891 .mac_addr_add = bnxt_mac_addr_add_op, 892 .mac_addr_remove = bnxt_mac_addr_remove_op, 893 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 894 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 895 }; 896 897 static bool bnxt_vf_pciid(uint16_t id) 898 { 899 if (id == BROADCOM_DEV_ID_57304_VF || 900 id == BROADCOM_DEV_ID_57406_VF) 901 return true; 902 return false; 903 } 904 905 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 906 { 907 int rc; 908 struct bnxt *bp = eth_dev->data->dev_private; 909 910 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 911 if (!eth_dev->pci_dev->mem_resource[0].addr) { 912 RTE_LOG(ERR, PMD, 913 "Cannot find PCI device base address, aborting\n"); 914 rc = -ENODEV; 915 goto init_err_disable; 916 } 917 918 bp->eth_dev = eth_dev; 919 bp->pdev = eth_dev->pci_dev; 920 921 bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr; 922 if (!bp->bar0) { 923 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n"); 924 rc = -ENOMEM; 925 goto init_err_release; 926 } 927 return 0; 928 929 init_err_release: 930 if (bp->bar0) 931 bp->bar0 = NULL; 932 933 init_err_disable: 934 935 return rc; 936 } 937 938 static int 939 bnxt_dev_init(struct rte_eth_dev *eth_dev) 940 { 941 static int version_printed; 942 struct bnxt *bp; 943 int rc; 944 945 if (version_printed++ == 0) 946 RTE_LOG(INFO, PMD, "%s", bnxt_version); 947 948 if (eth_dev->pci_dev->addr.function >= 2 && 949 eth_dev->pci_dev->addr.function < 4) { 950 RTE_LOG(ERR, PMD, "Function not enabled %x:\n", 951 eth_dev->pci_dev->addr.function); 952 rc = -ENOMEM; 953 goto error; 954 } 955 956 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev); 957 bp = eth_dev->data->dev_private; 958 959 if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id)) 960 bp->flags |= BNXT_FLAG_VF; 961 962 rc = bnxt_init_board(eth_dev); 963 if (rc) { 964 RTE_LOG(ERR, PMD, 965 "Board initialization failed rc: %x\n", rc); 966 goto error; 967 } 968 eth_dev->dev_ops = &bnxt_dev_ops; 969 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 970 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 971 972 rc = bnxt_alloc_hwrm_resources(bp); 973 if (rc) { 974 RTE_LOG(ERR, PMD, 975 "hwrm resource allocation failure rc: %x\n", rc); 976 goto error_free; 977 } 978 rc = bnxt_hwrm_ver_get(bp); 979 if (rc) 980 goto error_free; 981 bnxt_hwrm_queue_qportcfg(bp); 982 983 /* Get the MAX capabilities for this function */ 984 rc = bnxt_hwrm_func_qcaps(bp); 985 if (rc) { 986 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc); 987 goto error_free; 988 } 989 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 990 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0); 991 if (eth_dev->data->mac_addrs == NULL) { 992 RTE_LOG(ERR, PMD, 993 "Failed to alloc %u bytes needed to store MAC addr tbl", 994 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR); 995 rc = -ENOMEM; 996 goto error_free; 997 } 998 /* Copy the permanent MAC from the qcap response address now. */ 999 if (BNXT_PF(bp)) 1000 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr)); 1001 else 1002 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr)); 1003 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN); 1004 bp->grp_info = rte_zmalloc("bnxt_grp_info", 1005 sizeof(*bp->grp_info) * bp->max_ring_grps, 0); 1006 if (!bp->grp_info) { 1007 RTE_LOG(ERR, PMD, 1008 "Failed to alloc %zu bytes needed to store group info table\n", 1009 sizeof(*bp->grp_info) * bp->max_ring_grps); 1010 rc = -ENOMEM; 1011 goto error_free; 1012 } 1013 1014 rc = bnxt_hwrm_func_driver_register(bp, 0, 1015 bp->pf.vf_req_fwd); 1016 if (rc) { 1017 RTE_LOG(ERR, PMD, 1018 "Failed to register driver"); 1019 rc = -EBUSY; 1020 goto error_free; 1021 } 1022 1023 RTE_LOG(INFO, PMD, 1024 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n", 1025 eth_dev->pci_dev->mem_resource[0].phys_addr, 1026 eth_dev->pci_dev->mem_resource[0].addr); 1027 1028 bp->dev_stopped = 0; 1029 1030 return 0; 1031 1032 error_free: 1033 eth_dev->driver->eth_dev_uninit(eth_dev); 1034 error: 1035 return rc; 1036 } 1037 1038 static int 1039 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) { 1040 struct bnxt *bp = eth_dev->data->dev_private; 1041 int rc; 1042 1043 if (eth_dev->data->mac_addrs) 1044 rte_free(eth_dev->data->mac_addrs); 1045 if (bp->grp_info) 1046 rte_free(bp->grp_info); 1047 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 1048 bnxt_free_hwrm_resources(bp); 1049 if (bp->dev_stopped == 0) 1050 bnxt_dev_close_op(eth_dev); 1051 return rc; 1052 } 1053 1054 static struct eth_driver bnxt_rte_pmd = { 1055 .pci_drv = { 1056 .name = "rte_" DRV_MODULE_NAME "_pmd", 1057 .id_table = bnxt_pci_id_map, 1058 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1059 }, 1060 .eth_dev_init = bnxt_dev_init, 1061 .eth_dev_uninit = bnxt_dev_uninit, 1062 .dev_private_size = sizeof(struct bnxt), 1063 }; 1064 1065 static int bnxt_rte_pmd_init(const char *name, const char *params __rte_unused) 1066 { 1067 RTE_LOG(INFO, PMD, "bnxt_rte_pmd_init() called for %s\n", name); 1068 rte_eth_driver_register(&bnxt_rte_pmd); 1069 return 0; 1070 } 1071 1072 static struct rte_driver bnxt_pmd_drv = { 1073 .type = PMD_PDEV, 1074 .init = bnxt_rte_pmd_init, 1075 }; 1076 1077 PMD_REGISTER_DRIVER(bnxt_pmd_drv, bnxt); 1078 DRIVER_REGISTER_PCI_TABLE(bnxt, bnxt_pci_id_map); 1079