xref: /f-stack/dpdk/drivers/net/bnxt/bnxt.h (revision 16d80a6d)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2014-2018 Broadcom
3  * All rights reserved.
4  */
5 
6 #ifndef _BNXT_H_
7 #define _BNXT_H_
8 
9 #include <inttypes.h>
10 #include <stdbool.h>
11 #include <sys/queue.h>
12 
13 #include <rte_pci.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
19 #include <rte_time.h>
20 
21 #include "bnxt_cpr.h"
22 
23 #define BNXT_MAX_MTU		9574
24 #define VLAN_TAG_SIZE		4
25 #define BNXT_VF_RSV_NUM_RSS_CTX	1
26 #define BNXT_VF_RSV_NUM_L2_CTX	4
27 /* TODO: For now, do not support VMDq/RFS on VFs. */
28 #define BNXT_VF_RSV_NUM_VNIC	1
29 #define BNXT_MAX_LED		4
30 #define BNXT_NUM_VLANS		2
31 #define BNXT_MIN_RING_DESC	16
32 #define BNXT_MAX_TX_RING_DESC	4096
33 #define BNXT_MAX_RX_RING_DESC	8192
34 #define BNXT_DB_SIZE		0x80
35 
36 /* Chimp Communication Channel */
37 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET		0x0
38 #define GRCPF_REG_CHIMP_COMM_TRIGGER		0x100
39 /* Kong Communication Channel */
40 #define GRCPF_REG_KONG_CHANNEL_OFFSET		0xA00
41 #define GRCPF_REG_KONG_COMM_TRIGGER		0xB00
42 
43 #define BNXT_INT_LAT_TMR_MIN			75
44 #define BNXT_INT_LAT_TMR_MAX			150
45 #define BNXT_NUM_CMPL_AGGR_INT			36
46 #define BNXT_CMPL_AGGR_DMA_TMR			37
47 #define BNXT_NUM_CMPL_DMA_AGGR			36
48 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT	50
49 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT	12
50 
51 struct bnxt_led_info {
52 	uint8_t      led_id;
53 	uint8_t      led_type;
54 	uint8_t      led_group_id;
55 	uint8_t      unused;
56 	uint16_t  led_state_caps;
57 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
58 	rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
59 
60 	uint16_t  led_color_caps;
61 };
62 
63 struct bnxt_led_cfg {
64 	uint8_t led_id;
65 	uint8_t led_state;
66 	uint8_t led_color;
67 	uint8_t unused;
68 	uint16_t led_blink_on;
69 	uint16_t led_blink_off;
70 	uint8_t led_group_id;
71 	uint8_t rsvd;
72 };
73 
74 #define BNXT_LED_DFLT_ENA                               \
75 	(HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
76 	 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
77 	 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
78 	 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
79 	 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
80 
81 #define BNXT_LED_DFLT_ENA_SHIFT		6
82 
83 #define BNXT_LED_DFLT_ENABLES(x)                        \
84 	rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
85 
86 enum bnxt_hw_context {
87 	HW_CONTEXT_NONE     = 0,
88 	HW_CONTEXT_IS_RSS   = 1,
89 	HW_CONTEXT_IS_COS   = 2,
90 	HW_CONTEXT_IS_LB    = 3,
91 };
92 
93 struct bnxt_vlan_table_entry {
94 	uint16_t		tpid;
95 	uint16_t		vid;
96 } __attribute__((packed));
97 
98 struct bnxt_vlan_antispoof_table_entry {
99 	uint16_t		tpid;
100 	uint16_t		vid;
101 	uint16_t		mask;
102 } __attribute__((packed));
103 
104 struct bnxt_child_vf_info {
105 	void			*req_buf;
106 	struct bnxt_vlan_table_entry	*vlan_table;
107 	struct bnxt_vlan_antispoof_table_entry	*vlan_as_table;
108 	STAILQ_HEAD(, bnxt_filter_info)	filter;
109 	uint32_t		func_cfg_flags;
110 	uint32_t		l2_rx_mask;
111 	uint16_t		fid;
112 	uint16_t		max_tx_rate;
113 	uint16_t		dflt_vlan;
114 	uint16_t		vlan_count;
115 	uint8_t			mac_spoof_en;
116 	uint8_t			vlan_spoof_en;
117 	bool			random_mac;
118 	bool			persist_stats;
119 };
120 
121 struct bnxt_pf_info {
122 #define BNXT_FIRST_PF_FID	1
123 #define BNXT_MAX_VFS(bp)	(bp->pf.max_vfs)
124 #define BNXT_TOTAL_VFS(bp)	((bp)->pf.total_vfs)
125 #define BNXT_FIRST_VF_FID	128
126 #define BNXT_PF_RINGS_USED(bp)	bnxt_get_num_queues(bp)
127 #define BNXT_PF_RINGS_AVAIL(bp)	(bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
128 	uint16_t		port_id;
129 	uint16_t		first_vf_id;
130 	uint16_t		active_vfs;
131 	uint16_t		max_vfs;
132 	uint16_t		total_vfs; /* Total VFs possible.
133 					    * Not necessarily enabled.
134 					    */
135 	uint32_t		func_cfg_flags;
136 	void			*vf_req_buf;
137 	rte_iova_t		vf_req_buf_dma_addr;
138 	uint32_t		vf_req_fwd[8];
139 	uint16_t		total_vnics;
140 	struct bnxt_child_vf_info	*vf_info;
141 #define BNXT_EVB_MODE_NONE	0
142 #define BNXT_EVB_MODE_VEB	1
143 #define BNXT_EVB_MODE_VEPA	2
144 	uint8_t			evb_mode;
145 };
146 
147 /* Max wait time is 10 * 100ms = 1s */
148 #define BNXT_LINK_WAIT_CNT	10
149 #define BNXT_LINK_WAIT_INTERVAL	100
150 struct bnxt_link_info {
151 	uint32_t		phy_flags;
152 	uint8_t			mac_type;
153 	uint8_t			phy_link_status;
154 	uint8_t			loop_back;
155 	uint8_t			link_up;
156 	uint8_t			duplex;
157 	uint8_t			pause;
158 	uint8_t			force_pause;
159 	uint8_t			auto_pause;
160 	uint8_t			auto_mode;
161 #define PHY_VER_LEN		3
162 	uint8_t			phy_ver[PHY_VER_LEN];
163 	uint16_t		link_speed;
164 	uint16_t		support_speeds;
165 	uint16_t		auto_link_speed;
166 	uint16_t		force_link_speed;
167 	uint16_t		auto_link_speed_mask;
168 	uint32_t		preemphasis;
169 	uint8_t			phy_type;
170 	uint8_t			media_type;
171 };
172 
173 #define BNXT_COS_QUEUE_COUNT	8
174 struct bnxt_cos_queue_info {
175 	uint8_t	id;
176 	uint8_t	profile;
177 };
178 
179 struct rte_flow {
180 	STAILQ_ENTRY(rte_flow) next;
181 	struct bnxt_filter_info *filter;
182 	struct bnxt_vnic_info	*vnic;
183 };
184 
185 struct bnxt_ptp_cfg {
186 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
187 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
188 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
189 	struct rte_timecounter      tc;
190 	struct rte_timecounter      tx_tstamp_tc;
191 	struct rte_timecounter      rx_tstamp_tc;
192 	struct bnxt		*bp;
193 #define BNXT_MAX_TX_TS	1
194 	uint16_t			rxctl;
195 #define BNXT_PTP_MSG_SYNC			(1 << 0)
196 #define BNXT_PTP_MSG_DELAY_REQ			(1 << 1)
197 #define BNXT_PTP_MSG_PDELAY_REQ			(1 << 2)
198 #define BNXT_PTP_MSG_PDELAY_RESP		(1 << 3)
199 #define BNXT_PTP_MSG_FOLLOW_UP			(1 << 8)
200 #define BNXT_PTP_MSG_DELAY_RESP			(1 << 9)
201 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP	(1 << 10)
202 #define BNXT_PTP_MSG_ANNOUNCE			(1 << 11)
203 #define BNXT_PTP_MSG_SIGNALING			(1 << 12)
204 #define BNXT_PTP_MSG_MANAGEMENT			(1 << 13)
205 #define BNXT_PTP_MSG_EVENTS		(BNXT_PTP_MSG_SYNC |		\
206 					 BNXT_PTP_MSG_DELAY_REQ |	\
207 					 BNXT_PTP_MSG_PDELAY_REQ |	\
208 					 BNXT_PTP_MSG_PDELAY_RESP)
209 	uint8_t			tx_tstamp_en:1;
210 	int			rx_filter;
211 
212 #define BNXT_PTP_RX_TS_L	0
213 #define BNXT_PTP_RX_TS_H	1
214 #define BNXT_PTP_RX_SEQ		2
215 #define BNXT_PTP_RX_FIFO	3
216 #define BNXT_PTP_RX_FIFO_PENDING 0x1
217 #define BNXT_PTP_RX_FIFO_ADV	4
218 #define BNXT_PTP_RX_REGS	5
219 
220 #define BNXT_PTP_TX_TS_L	0
221 #define BNXT_PTP_TX_TS_H	1
222 #define BNXT_PTP_TX_SEQ		2
223 #define BNXT_PTP_TX_FIFO	3
224 #define BNXT_PTP_TX_FIFO_EMPTY	 0x2
225 #define BNXT_PTP_TX_REGS	4
226 	uint32_t			rx_regs[BNXT_PTP_RX_REGS];
227 	uint32_t			rx_mapped_regs[BNXT_PTP_RX_REGS];
228 	uint32_t			tx_regs[BNXT_PTP_TX_REGS];
229 	uint32_t			tx_mapped_regs[BNXT_PTP_TX_REGS];
230 };
231 
232 struct bnxt_coal {
233 	uint16_t			num_cmpl_aggr_int;
234 	uint16_t			num_cmpl_dma_aggr;
235 	uint16_t			num_cmpl_dma_aggr_during_int;
236 	uint16_t			int_lat_tmr_max;
237 	uint16_t			int_lat_tmr_min;
238 	uint16_t			cmpl_aggr_dma_tmr;
239 	uint16_t			cmpl_aggr_dma_tmr_during_int;
240 };
241 
242 #define BNXT_HWRM_SHORT_REQ_LEN		sizeof(struct hwrm_short_input)
243 struct bnxt {
244 	void				*bar0;
245 
246 	struct rte_eth_dev		*eth_dev;
247 	struct rte_eth_rss_conf		rss_conf;
248 	struct rte_pci_device		*pdev;
249 	void				*doorbell_base;
250 
251 	uint32_t		flags;
252 #define BNXT_FLAG_REGISTERED	(1 << 0)
253 #define BNXT_FLAG_VF		(1 << 1)
254 #define BNXT_FLAG_PORT_STATS	(1 << 2)
255 #define BNXT_FLAG_JUMBO		(1 << 3)
256 #define BNXT_FLAG_SHORT_CMD	(1 << 4)
257 #define BNXT_FLAG_UPDATE_HASH	(1 << 5)
258 #define BNXT_FLAG_PTP_SUPPORTED	(1 << 6)
259 #define BNXT_FLAG_MULTI_HOST    (1 << 7)
260 #define BNXT_FLAG_EXT_RX_PORT_STATS	(1 << 8)
261 #define BNXT_FLAG_EXT_TX_PORT_STATS	(1 << 9)
262 #define BNXT_FLAG_KONG_MB_EN	(1 << 10)
263 #define BNXT_FLAG_TRUSTED_VF_EN	(1 << 11)
264 #define BNXT_FLAG_DFLT_VNIC_SET	(1 << 12)
265 #define BNXT_FLAG_NEW_RM	(1 << 30)
266 #define BNXT_FLAG_INIT_DONE	(1U << 31)
267 #define BNXT_PF(bp)		(!((bp)->flags & BNXT_FLAG_VF))
268 #define BNXT_VF(bp)		((bp)->flags & BNXT_FLAG_VF)
269 #define BNXT_NPAR(bp)		((bp)->port_partition_type)
270 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
271 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
272 #define BNXT_USE_CHIMP_MB	0 //For non-CFA commands, everything uses Chimp.
273 #define BNXT_USE_KONG(bp)	((bp)->flags & BNXT_FLAG_KONG_MB_EN)
274 #define BNXT_VF_IS_TRUSTED(bp)	((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
275 
276 	unsigned int		rx_nr_rings;
277 	unsigned int		rx_cp_nr_rings;
278 	struct bnxt_rx_queue **rx_queues;
279 	const void		*rx_mem_zone;
280 	struct rx_port_stats    *hw_rx_port_stats;
281 	rte_iova_t		hw_rx_port_stats_map;
282 	struct rx_port_stats_ext    *hw_rx_port_stats_ext;
283 	rte_iova_t		hw_rx_port_stats_ext_map;
284 	uint16_t		fw_rx_port_stats_ext_size;
285 
286 	unsigned int		tx_nr_rings;
287 	unsigned int		tx_cp_nr_rings;
288 	struct bnxt_tx_queue **tx_queues;
289 	const void		*tx_mem_zone;
290 	struct tx_port_stats    *hw_tx_port_stats;
291 	rte_iova_t		hw_tx_port_stats_map;
292 	struct tx_port_stats_ext    *hw_tx_port_stats_ext;
293 	rte_iova_t		hw_tx_port_stats_ext_map;
294 	uint16_t		fw_tx_port_stats_ext_size;
295 
296 	/* Default completion ring */
297 	struct bnxt_cp_ring_info	*def_cp_ring;
298 	uint32_t		max_ring_grps;
299 	struct bnxt_ring_grp_info	*grp_info;
300 
301 	unsigned int		nr_vnics;
302 
303 	struct bnxt_vnic_info	*vnic_info;
304 	STAILQ_HEAD(, bnxt_vnic_info)	free_vnic_list;
305 
306 	struct bnxt_filter_info	*filter_info;
307 	STAILQ_HEAD(, bnxt_filter_info)	free_filter_list;
308 
309 	struct bnxt_irq         *irq_tbl;
310 
311 #define MAX_NUM_MAC_ADDR	32
312 	uint8_t			mac_addr[ETHER_ADDR_LEN];
313 
314 	uint16_t			hwrm_cmd_seq;
315 	uint16_t			kong_cmd_seq;
316 	void				*hwrm_cmd_resp_addr;
317 	rte_iova_t			hwrm_cmd_resp_dma_addr;
318 	void				*hwrm_short_cmd_req_addr;
319 	rte_iova_t			hwrm_short_cmd_req_dma_addr;
320 	rte_spinlock_t			hwrm_lock;
321 	uint16_t			max_req_len;
322 	uint16_t			max_resp_len;
323 
324 	struct bnxt_link_info	link_info;
325 	struct bnxt_cos_queue_info	cos_queue[BNXT_COS_QUEUE_COUNT];
326 	uint8_t			tx_cosq_id;
327 
328 	uint16_t		fw_fid;
329 	uint8_t			dflt_mac_addr[ETHER_ADDR_LEN];
330 	uint16_t		max_rsscos_ctx;
331 	uint16_t		max_cp_rings;
332 	uint16_t		max_tx_rings;
333 	uint16_t		max_rx_rings;
334 	uint16_t		max_l2_ctx;
335 	uint16_t		max_vnics;
336 	uint16_t		max_stat_ctx;
337 	uint16_t		vlan;
338 	struct bnxt_pf_info		pf;
339 	uint8_t			port_partition_type;
340 	uint8_t			dev_stopped;
341 	uint8_t			vxlan_port_cnt;
342 	uint8_t			geneve_port_cnt;
343 	uint16_t		vxlan_port;
344 	uint16_t		geneve_port;
345 	uint16_t		vxlan_fw_dst_port_id;
346 	uint16_t		geneve_fw_dst_port_id;
347 	uint32_t		fw_ver;
348 	uint32_t		hwrm_spec_code;
349 
350 	struct bnxt_led_info	leds[BNXT_MAX_LED];
351 	uint8_t			num_leds;
352 	struct bnxt_ptp_cfg     *ptp_cfg;
353 	uint16_t		vf_resv_strategy;
354 };
355 
356 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
357 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
358 
359 bool is_bnxt_supported(struct rte_eth_dev *dev);
360 bool bnxt_stratus_device(struct bnxt *bp);
361 extern const struct rte_flow_ops bnxt_flow_ops;
362 
363 extern int bnxt_logtype_driver;
364 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
365 	rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
366 		__func__, ## args)
367 
368 #define PMD_DRV_LOG(level, fmt, args...) \
369 	PMD_DRV_LOG_RAW(level, fmt, ## args)
370 #endif
371