1 /*- 2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved. 3 * 4 * Eric Davis <[email protected]> 5 * David Christensen <[email protected]> 6 * Gary Zambrano <[email protected]> 7 * 8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. 9 * Copyright (c) 2015 QLogic Corporation. 10 * All rights reserved. 11 * www.qlogic.com 12 * 13 * See LICENSE.bnx2x_pmd for copyright and licensing details. 14 */ 15 16 #ifndef ECORE_SP_H 17 #define ECORE_SP_H 18 19 #include <rte_byteorder.h> 20 21 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 22 #ifndef __LITTLE_ENDIAN 23 #define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN 24 #endif 25 #undef __BIG_ENDIAN 26 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 27 #ifndef __BIG_ENDIAN 28 #define __BIG_ENDIAN RTE_BIG_ENDIAN 29 #endif 30 #undef __LITTLE_ENDIAN 31 #endif 32 33 #include "ecore_mfw_req.h" 34 #include "ecore_fw_defs.h" 35 #include "ecore_hsi.h" 36 #include "ecore_reg.h" 37 38 struct bnx2x_softc; 39 typedef rte_iova_t ecore_dma_addr_t; /* expected to be 64 bit wide */ 40 typedef volatile int ecore_atomic_t; 41 42 43 #define ETH_ALEN ETHER_ADDR_LEN /* 6 */ 44 45 #define ECORE_SWCID_SHIFT 17 46 #define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1) 47 48 #define ECORE_MC_HASH_SIZE 8 49 #define ECORE_MC_HASH_OFFSET(sc, i) \ 50 (BAR_TSTRORM_INTMEM + \ 51 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4) 52 53 #define ECORE_MAX_MULTICAST 64 54 #define ECORE_MAX_EMUL_MULTI 1 55 56 #define IRO sc->iro_array 57 58 typedef rte_spinlock_t ECORE_MUTEX; 59 #define ECORE_MUTEX_INIT(_mutex) rte_spinlock_init(_mutex) 60 #define ECORE_MUTEX_LOCK(_mutex) rte_spinlock_lock(_mutex) 61 #define ECORE_MUTEX_UNLOCK(_mutex) rte_spinlock_unlock(_mutex) 62 63 typedef rte_spinlock_t ECORE_MUTEX_SPIN; 64 #define ECORE_SPIN_LOCK_INIT(_spin, _sc) rte_spinlock_init(_spin) 65 #define ECORE_SPIN_LOCK_BH(_spin) rte_spinlock_lock(_spin) /* bh = bottom-half */ 66 #define ECORE_SPIN_UNLOCK_BH(_spin) rte_spinlock_unlock(_spin) /* bh = bottom-half */ 67 68 #define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb() 69 #define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb() 70 #define ECORE_SMP_MB() mb() 71 #define ECORE_SMP_RMB() rmb() 72 #define ECORE_SMP_WMB() wmb() 73 #define ECORE_MMIOWB() wmb() 74 75 #define ECORE_SET_BIT_NA(bit, var) (*var |= (1 << bit)) 76 #define ECORE_CLEAR_BIT_NA(bit, var) (*var &= ~(1 << bit)) 77 78 #define ECORE_TEST_BIT(bit, var) bnx2x_test_bit(bit, var) 79 #define ECORE_SET_BIT(bit, var) bnx2x_set_bit(bit, var) 80 #define ECORE_CLEAR_BIT(bit, var) bnx2x_clear_bit(bit, var) 81 #define ECORE_TEST_AND_CLEAR_BIT(bit, var) bnx2x_test_and_clear_bit(bit, var) 82 83 #define atomic_load_acq_int (int)* 84 #define atomic_store_rel_int(a, v) (*a = v) 85 #define atomic_cmpset_acq_int(a, o, n) ((*a = (o & (n)) | (n)) ^ o) 86 87 #define atomic_load_acq_long (long)* 88 #define atomic_store_rel_long(a, v) (*a = v) 89 #define atomic_set_acq_long(a, v) (*a |= v) 90 #define atomic_clear_acq_long(a, v) (*a &= ~v) 91 #define atomic_cmpset_acq_long(a, o, n) ((*a = (o & (n)) | (n)) ^ o) 92 #define atomic_subtract_acq_long(a, v) (*a -= v) 93 #define atomic_add_acq_long(a, v) (*a += v) 94 95 #define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a) 96 #define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v) 97 #define ECORE_ATOMIC_CMPXCHG(a, o, n) bnx2x_cmpxchg((volatile int *)a, o, n) 98 99 #define ECORE_RET_PENDING(pending_bit, pending) \ 100 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS) 101 102 #define ECORE_SET_FLAG(value, mask, flag) \ 103 do { \ 104 (value) &= ~(mask); \ 105 (value) |= ((flag) << (mask##_SHIFT)); \ 106 } while (0) 107 108 #define ECORE_GET_FLAG(value, mask) \ 109 (((value) &= (mask)) >> (mask##_SHIFT)) 110 111 #define ECORE_MIGHT_SLEEP() 112 113 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id) 114 115 #define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s) 116 #define ECORE_MEMCPY(_a, _b, _s) rte_memcpy(_a, _b, _s) 117 #define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s) 118 119 #define ECORE_CPU_TO_LE16(x) htole16(x) 120 #define ECORE_CPU_TO_LE32(x) htole32(x) 121 122 #define ECORE_WAIT(_s, _t) DELAY(1000) 123 #define ECORE_MSLEEP(_t) DELAY((_t) * 1000) 124 125 #define ECORE_LIKELY(x) likely(x) 126 #define ECORE_UNLIKELY(x) unlikely(x) 127 128 #define ECORE_ZALLOC(_size, _flags, _sc) \ 129 rte_zmalloc("", _size, RTE_CACHE_LINE_SIZE) 130 131 #define ECORE_CALLOC(_len, _size, _flags, _sc) \ 132 rte_calloc("", _len, _size, RTE_CACHE_LINE_SIZE) 133 134 #define ECORE_FREE(_s, _buf, _size) \ 135 rte_free(_buf) 136 137 #define SC_ILT(sc) ((sc)->ilt) 138 #define ILOG2(x) bnx2x_ilog2(x) 139 140 #define ECORE_ILT_ZALLOC(x, y, size, str) \ 141 do { \ 142 x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \ 143 if (x) { \ 144 if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \ 145 size, (struct bnx2x_dma *)x, \ 146 str, RTE_CACHE_LINE_SIZE) != 0) { \ 147 rte_free(x); \ 148 x = NULL; \ 149 *y = 0; \ 150 } else { \ 151 *y = ((struct bnx2x_dma *)x)->paddr; \ 152 } \ 153 } \ 154 } while (0) 155 156 #define ECORE_ILT_FREE(x, y, size) \ 157 do { \ 158 if (x) { \ 159 rte_free(x); \ 160 x = NULL; \ 161 y = 0; \ 162 } \ 163 } while (0) 164 165 #define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE 166 167 #define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE 168 #define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE 169 #define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE 170 171 #define ECORE_SET_CTX_VALIDATION bnx2x_set_ctx_validation 172 173 #define ECORE_UPDATE_COALESCE_SB_INDEX bnx2x_update_coalesce_sb_index 174 175 #define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a)) 176 177 #define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN 178 179 #define ECORE_PATH_ID SC_PATH 180 #define ECORE_PORT_ID SC_PORT 181 #define ECORE_FUNC_ID SC_FUNC 182 #define ECORE_ABS_FUNC_ID SC_ABS_FUNC 183 184 #define CRCPOLY_LE 0xedb88320 185 uint32_t ecore_calc_crc32(uint32_t crc, uint8_t const *p, 186 uint32_t len, uint32_t magic); 187 188 uint8_t ecore_calc_crc8(uint32_t data, uint8_t crc); 189 190 191 static inline uint32_t 192 ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len) 193 { 194 return ecore_calc_crc32(seed, mac, len, CRCPOLY_LE); 195 } 196 197 #define ecore_sp_post(_sc, _a, _b, _c, _d) \ 198 bnx2x_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d) 199 200 #define ECORE_DBG_BREAK_IF(exp) \ 201 do { \ 202 if (unlikely(exp)) { \ 203 rte_panic("ECORE"); \ 204 } \ 205 } while (0) 206 207 #define ECORE_BUG() \ 208 do { \ 209 rte_panic("BUG (%s:%d)", __FILE__, __LINE__); \ 210 } while(0); 211 212 #define ECORE_BUG_ON(exp) \ 213 do { \ 214 if (likely(exp)) { \ 215 rte_panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \ 216 } \ 217 } while (0) 218 219 220 #define ECORE_MSG(m, ...) \ 221 PMD_DRV_LOG(DEBUG, m, ##__VA_ARGS__) 222 223 typedef struct _ecore_list_entry_t 224 { 225 struct _ecore_list_entry_t *next, *prev; 226 } ecore_list_entry_t; 227 228 typedef struct ecore_list_t 229 { 230 ecore_list_entry_t *head, *tail; 231 unsigned long cnt; 232 } ecore_list_t; 233 234 /* initialize the list */ 235 #define ECORE_LIST_INIT(_list) \ 236 do { \ 237 (_list)->head = NULL; \ 238 (_list)->tail = NULL; \ 239 (_list)->cnt = 0; \ 240 } while (0) 241 242 /* return TRUE if the element is the last on the list */ 243 #define ECORE_LIST_IS_LAST(_elem, _list) \ 244 (_elem == (_list)->tail) 245 246 /* return TRUE if the list is empty */ 247 #define ECORE_LIST_IS_EMPTY(_list) \ 248 ((_list)->cnt == 0) 249 250 /* return the first element */ 251 #define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \ 252 (cast *)((_list)->head) 253 254 /* return the next element */ 255 #define ECORE_LIST_NEXT(_elem, _link, cast) \ 256 (cast *)((&((_elem)->_link))->next) 257 258 /* push an element on the head of the list */ 259 #define ECORE_LIST_PUSH_HEAD(_elem, _list) \ 260 do { \ 261 (_elem)->prev = (ecore_list_entry_t *)0; \ 262 (_elem)->next = (_list)->head; \ 263 if ((_list)->tail == (ecore_list_entry_t *)0) { \ 264 (_list)->tail = (_elem); \ 265 } else { \ 266 (_list)->head->prev = (_elem); \ 267 } \ 268 (_list)->head = (_elem); \ 269 (_list)->cnt++; \ 270 } while (0) 271 272 /* push an element on the tail of the list */ 273 #define ECORE_LIST_PUSH_TAIL(_elem, _list) \ 274 do { \ 275 (_elem)->next = (ecore_list_entry_t *)0; \ 276 (_elem)->prev = (_list)->tail; \ 277 if ((_list)->tail) { \ 278 (_list)->tail->next = (_elem); \ 279 } else { \ 280 (_list)->head = (_elem); \ 281 } \ 282 (_list)->tail = (_elem); \ 283 (_list)->cnt++; \ 284 } while (0) 285 286 /* push list1 on the head of list2 and return with list1 as empty */ 287 #define ECORE_LIST_SPLICE_INIT(_list1, _list2) \ 288 do { \ 289 (_list1)->tail->next = (_list2)->head; \ 290 if ((_list2)->head) { \ 291 (_list2)->head->prev = (_list1)->tail; \ 292 } else { \ 293 (_list2)->tail = (_list1)->tail; \ 294 } \ 295 (_list2)->head = (_list1)->head; \ 296 (_list2)->cnt += (_list1)->cnt; \ 297 (_list1)->head = NULL; \ 298 (_list1)->tail = NULL; \ 299 (_list1)->cnt = 0; \ 300 } while (0) 301 302 /* remove an element from the list */ 303 #define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \ 304 do { \ 305 if ((_list)->head == (_elem)) { \ 306 if ((_list)->head) { \ 307 (_list)->head = (_list)->head->next; \ 308 if ((_list)->head) { \ 309 (_list)->head->prev = (ecore_list_entry_t *)0; \ 310 } else { \ 311 (_list)->tail = (ecore_list_entry_t *)0; \ 312 } \ 313 (_list)->cnt--; \ 314 } \ 315 } else if ((_list)->tail == (_elem)) { \ 316 if ((_list)->tail) { \ 317 (_list)->tail = (_list)->tail->prev; \ 318 if ((_list)->tail) { \ 319 (_list)->tail->next = (ecore_list_entry_t *)0; \ 320 } else { \ 321 (_list)->head = (ecore_list_entry_t *)0; \ 322 } \ 323 (_list)->cnt--; \ 324 } \ 325 } else { \ 326 (_elem)->prev->next = (_elem)->next; \ 327 (_elem)->next->prev = (_elem)->prev; \ 328 (_list)->cnt--; \ 329 } \ 330 } while (0) 331 332 /* walk the list */ 333 #define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \ 334 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \ 335 pos; \ 336 pos = ECORE_LIST_NEXT(pos, _link, cast)) 337 338 /* walk the list (safely) */ 339 #define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \ 340 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \ 341 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \ 342 pos != NULL; \ 343 pos = (cast *)n, \ 344 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL) 345 346 347 /* Manipulate a bit vector defined as an array of uint64_t */ 348 349 /* Number of bits in one sge_mask array element */ 350 #define BIT_VEC64_ELEM_SZ 64 351 #define BIT_VEC64_ELEM_SHIFT 6 352 #define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1) 353 354 #define __BIT_VEC64_SET_BIT(el, bit) \ 355 do { \ 356 el = ((el) | ((uint64_t)0x1 << (bit))); \ 357 } while (0) 358 359 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 360 do { \ 361 el = ((el) & (~((uint64_t)0x1 << (bit)))); \ 362 } while (0) 363 364 #define BIT_VEC64_SET_BIT(vec64, idx) \ 365 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 366 (idx) & BIT_VEC64_ELEM_MASK) 367 368 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 369 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 370 (idx) & BIT_VEC64_ELEM_MASK) 371 372 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 373 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 374 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 375 376 /* 377 * Creates a bitmask of all ones in less significant bits. 378 * idx - index of the most significant bit in the created mask 379 */ 380 #define BIT_VEC64_ONES_MASK(idx) \ 381 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 382 #define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0)) 383 384 /* fill in a MAC address the way the FW likes it */ 385 static inline void 386 ecore_set_fw_mac_addr(uint16_t *fw_hi, 387 uint16_t *fw_mid, 388 uint16_t *fw_lo, 389 uint8_t *mac) 390 { 391 ((uint8_t *)fw_hi)[0] = mac[1]; 392 ((uint8_t *)fw_hi)[1] = mac[0]; 393 ((uint8_t *)fw_mid)[0] = mac[3]; 394 ((uint8_t *)fw_mid)[1] = mac[2]; 395 ((uint8_t *)fw_lo)[0] = mac[5]; 396 ((uint8_t *)fw_lo)[1] = mac[4]; 397 } 398 399 400 enum ecore_status_t { 401 ECORE_EXISTS = -6, 402 ECORE_IO = -5, 403 ECORE_TIMEOUT = -4, 404 ECORE_INVAL = -3, 405 ECORE_BUSY = -2, 406 ECORE_NOMEM = -1, 407 ECORE_SUCCESS = 0, 408 /* PENDING is not an error and should be positive */ 409 ECORE_PENDING = 1, 410 }; 411 412 enum { 413 SWITCH_UPDATE, 414 AFEX_UPDATE, 415 }; 416 417 418 419 420 struct bnx2x_softc; 421 struct eth_context; 422 423 /* Bits representing general command's configuration */ 424 enum { 425 RAMROD_TX, 426 RAMROD_RX, 427 /* Wait until all pending commands complete */ 428 RAMROD_COMP_WAIT, 429 /* Don't send a ramrod, only update a registry */ 430 RAMROD_DRV_CLR_ONLY, 431 /* Configure HW according to the current object state */ 432 RAMROD_RESTORE, 433 /* Execute the next command now */ 434 RAMROD_EXEC, 435 /* Don't add a new command and continue execution of posponed 436 * commands. If not set a new command will be added to the 437 * pending commands list. 438 */ 439 RAMROD_CONT, 440 /* If there is another pending ramrod, wait until it finishes and 441 * re-try to submit this one. This flag can be set only in sleepable 442 * context, and should not be set from the context that completes the 443 * ramrods as deadlock will occur. 444 */ 445 RAMROD_RETRY, 446 }; 447 448 typedef enum { 449 ECORE_OBJ_TYPE_RX, 450 ECORE_OBJ_TYPE_TX, 451 ECORE_OBJ_TYPE_RX_TX, 452 } ecore_obj_type; 453 454 /* Public slow path states */ 455 enum { 456 ECORE_FILTER_MAC_PENDING, 457 ECORE_FILTER_VLAN_PENDING, 458 ECORE_FILTER_VLAN_MAC_PENDING, 459 ECORE_FILTER_RX_MODE_PENDING, 460 ECORE_FILTER_RX_MODE_SCHED, 461 ECORE_FILTER_ISCSI_ETH_START_SCHED, 462 ECORE_FILTER_ISCSI_ETH_STOP_SCHED, 463 ECORE_FILTER_FCOE_ETH_START_SCHED, 464 ECORE_FILTER_FCOE_ETH_STOP_SCHED, 465 ECORE_FILTER_MCAST_PENDING, 466 ECORE_FILTER_MCAST_SCHED, 467 ECORE_FILTER_RSS_CONF_PENDING, 468 ECORE_AFEX_FCOE_Q_UPDATE_PENDING, 469 ECORE_AFEX_PENDING_VIFSET_MCP_ACK 470 }; 471 472 struct ecore_raw_obj { 473 uint8_t func_id; 474 475 /* Queue params */ 476 uint8_t cl_id; 477 uint32_t cid; 478 479 /* Ramrod data buffer params */ 480 void *rdata; 481 ecore_dma_addr_t rdata_mapping; 482 483 /* Ramrod state params */ 484 int state; /* "ramrod is pending" state bit */ 485 unsigned long *pstate; /* pointer to state buffer */ 486 487 ecore_obj_type obj_type; 488 489 int (*wait_comp)(struct bnx2x_softc *sc, 490 struct ecore_raw_obj *o); 491 492 int (*check_pending)(struct ecore_raw_obj *o); 493 void (*clear_pending)(struct ecore_raw_obj *o); 494 void (*set_pending)(struct ecore_raw_obj *o); 495 }; 496 497 /************************* VLAN-MAC commands related parameters ***************/ 498 struct ecore_mac_ramrod_data { 499 uint8_t mac[ETH_ALEN]; 500 uint8_t is_inner_mac; 501 }; 502 503 struct ecore_vlan_ramrod_data { 504 uint16_t vlan; 505 }; 506 507 struct ecore_vlan_mac_ramrod_data { 508 uint8_t mac[ETH_ALEN]; 509 uint8_t is_inner_mac; 510 uint16_t vlan; 511 }; 512 513 union ecore_classification_ramrod_data { 514 struct ecore_mac_ramrod_data mac; 515 struct ecore_vlan_ramrod_data vlan; 516 struct ecore_vlan_mac_ramrod_data vlan_mac; 517 }; 518 519 /* VLAN_MAC commands */ 520 enum ecore_vlan_mac_cmd { 521 ECORE_VLAN_MAC_ADD, 522 ECORE_VLAN_MAC_DEL, 523 ECORE_VLAN_MAC_MOVE, 524 }; 525 526 struct ecore_vlan_mac_data { 527 /* Requested command: ECORE_VLAN_MAC_XX */ 528 enum ecore_vlan_mac_cmd cmd; 529 /* used to contain the data related vlan_mac_flags bits from 530 * ramrod parameters. 531 */ 532 unsigned long vlan_mac_flags; 533 534 /* Needed for MOVE command */ 535 struct ecore_vlan_mac_obj *target_obj; 536 537 union ecore_classification_ramrod_data u; 538 }; 539 540 /*************************** Exe Queue obj ************************************/ 541 union ecore_exe_queue_cmd_data { 542 struct ecore_vlan_mac_data vlan_mac; 543 544 struct { 545 } mcast; 546 }; 547 548 struct ecore_exeq_elem { 549 ecore_list_entry_t link; 550 551 /* Length of this element in the exe_chunk. */ 552 int cmd_len; 553 554 union ecore_exe_queue_cmd_data cmd_data; 555 }; 556 557 union ecore_qable_obj; 558 559 union ecore_exeq_comp_elem { 560 union event_ring_elem *elem; 561 }; 562 563 struct ecore_exe_queue_obj; 564 565 typedef int (*exe_q_validate)(struct bnx2x_softc *sc, 566 union ecore_qable_obj *o, 567 struct ecore_exeq_elem *elem); 568 569 typedef int (*exe_q_remove)(struct bnx2x_softc *sc, 570 union ecore_qable_obj *o, 571 struct ecore_exeq_elem *elem); 572 573 /* Return positive if entry was optimized, 0 - if not, negative 574 * in case of an error. 575 */ 576 typedef int (*exe_q_optimize)(struct bnx2x_softc *sc, 577 union ecore_qable_obj *o, 578 struct ecore_exeq_elem *elem); 579 typedef int (*exe_q_execute)(struct bnx2x_softc *sc, 580 union ecore_qable_obj *o, 581 ecore_list_t *exe_chunk, 582 unsigned long *ramrod_flags); 583 typedef struct ecore_exeq_elem * 584 (*exe_q_get)(struct ecore_exe_queue_obj *o, 585 struct ecore_exeq_elem *elem); 586 587 struct ecore_exe_queue_obj { 588 /* Commands pending for an execution. */ 589 ecore_list_t exe_queue; 590 591 /* Commands pending for an completion. */ 592 ecore_list_t pending_comp; 593 594 ECORE_MUTEX_SPIN lock; 595 596 /* Maximum length of commands' list for one execution */ 597 int exe_chunk_len; 598 599 union ecore_qable_obj *owner; 600 601 /****** Virtual functions ******/ 602 /** 603 * Called before commands execution for commands that are really 604 * going to be executed (after 'optimize'). 605 * 606 * Must run under exe_queue->lock 607 */ 608 exe_q_validate validate; 609 610 /** 611 * Called before removing pending commands, cleaning allocated 612 * resources (e.g., credits from validate) 613 */ 614 exe_q_remove remove; 615 616 /** 617 * This will try to cancel the current pending commands list 618 * considering the new command. 619 * 620 * Returns the number of optimized commands or a negative error code 621 * 622 * Must run under exe_queue->lock 623 */ 624 exe_q_optimize optimize; 625 626 /** 627 * Run the next commands chunk (owner specific). 628 */ 629 exe_q_execute execute; 630 631 /** 632 * Return the exe_queue element containing the specific command 633 * if any. Otherwise return NULL. 634 */ 635 exe_q_get get; 636 }; 637 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 638 /* 639 * Element in the VLAN_MAC registry list having all current configured 640 * rules. 641 */ 642 struct ecore_vlan_mac_registry_elem { 643 ecore_list_entry_t link; 644 645 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 646 * Relevant for 57711 only. VLANs and MACs share the 647 * same CAM for these chips. 648 */ 649 int cam_offset; 650 651 /* Needed for DEL and RESTORE flows */ 652 unsigned long vlan_mac_flags; 653 654 union ecore_classification_ramrod_data u; 655 }; 656 657 /* Bits representing VLAN_MAC commands specific flags */ 658 enum { 659 ECORE_UC_LIST_MAC, 660 ECORE_ETH_MAC, 661 ECORE_ISCSI_ETH_MAC, 662 ECORE_NETQ_ETH_MAC, 663 ECORE_DONT_CONSUME_CAM_CREDIT, 664 ECORE_DONT_CONSUME_CAM_CREDIT_DEST, 665 }; 666 667 struct ecore_vlan_mac_ramrod_params { 668 /* Object to run the command from */ 669 struct ecore_vlan_mac_obj *vlan_mac_obj; 670 671 /* General command flags: COMP_WAIT, etc. */ 672 unsigned long ramrod_flags; 673 674 /* Command specific configuration request */ 675 struct ecore_vlan_mac_data user_req; 676 }; 677 678 struct ecore_vlan_mac_obj { 679 struct ecore_raw_obj raw; 680 681 /* Bookkeeping list: will prevent the addition of already existing 682 * entries. 683 */ 684 ecore_list_t head; 685 /* Implement a simple reader/writer lock on the head list. 686 * all these fields should only be accessed under the exe_queue lock 687 */ 688 uint8_t head_reader; /* Num. of readers accessing head list */ 689 int head_exe_request; /* Pending execution request. */ 690 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ 691 692 /* Execution queue interface instance */ 693 struct ecore_exe_queue_obj exe_queue; 694 695 /* MACs credit pool */ 696 struct ecore_credit_pool_obj *macs_pool; 697 698 /* VLANs credit pool */ 699 struct ecore_credit_pool_obj *vlans_pool; 700 701 /* RAMROD command to be used */ 702 int ramrod_cmd; 703 704 /* copy first n elements onto preallocated buffer 705 * 706 * @param n number of elements to get 707 * @param buf buffer preallocated by caller into which elements 708 * will be copied. Note elements are 4-byte aligned 709 * so buffer size must be able to accommodate the 710 * aligned elements. 711 * 712 * @return number of copied bytes 713 */ 714 715 int (*get_n_elements)(struct bnx2x_softc *sc, 716 struct ecore_vlan_mac_obj *o, int n, uint8_t *base, 717 uint8_t stride, uint8_t size); 718 719 /** 720 * Checks if ADD-ramrod with the given params may be performed. 721 * 722 * @return zero if the element may be added 723 */ 724 725 int (*check_add)(struct bnx2x_softc *sc, 726 struct ecore_vlan_mac_obj *o, 727 union ecore_classification_ramrod_data *data); 728 729 /** 730 * Checks if DEL-ramrod with the given params may be performed. 731 * 732 * @return TRUE if the element may be deleted 733 */ 734 struct ecore_vlan_mac_registry_elem * 735 (*check_del)(struct bnx2x_softc *sc, 736 struct ecore_vlan_mac_obj *o, 737 union ecore_classification_ramrod_data *data); 738 739 /** 740 * Checks if DEL-ramrod with the given params may be performed. 741 * 742 * @return TRUE if the element may be deleted 743 */ 744 int (*check_move)(struct bnx2x_softc *sc, 745 struct ecore_vlan_mac_obj *src_o, 746 struct ecore_vlan_mac_obj *dst_o, 747 union ecore_classification_ramrod_data *data); 748 749 /** 750 * Update the relevant credit object(s) (consume/return 751 * correspondingly). 752 */ 753 int (*get_credit)(struct ecore_vlan_mac_obj *o); 754 int (*put_credit)(struct ecore_vlan_mac_obj *o); 755 int (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset); 756 int (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset); 757 758 /** 759 * Configures one rule in the ramrod data buffer. 760 */ 761 void (*set_one_rule)(struct bnx2x_softc *sc, 762 struct ecore_vlan_mac_obj *o, 763 struct ecore_exeq_elem *elem, int rule_idx, 764 int cam_offset); 765 766 /** 767 * Delete all configured elements having the given 768 * vlan_mac_flags specification. Assumes no pending for 769 * execution commands. Will schedule all all currently 770 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 771 * specification for deletion and will use the given 772 * ramrod_flags for the last DEL operation. 773 * 774 * @param sc 775 * @param o 776 * @param ramrod_flags RAMROD_XX flags 777 * 778 * @return 0 if the last operation has completed successfully 779 * and there are no more elements left, positive value 780 * if there are pending for completion commands, 781 * negative value in case of failure. 782 */ 783 int (*delete_all)(struct bnx2x_softc *sc, 784 struct ecore_vlan_mac_obj *o, 785 unsigned long *vlan_mac_flags, 786 unsigned long *ramrod_flags); 787 788 /** 789 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 790 * configured elements list. 791 * 792 * @param sc 793 * @param p Command parameters (RAMROD_COMP_WAIT bit in 794 * ramrod_flags is only taken into an account) 795 * @param ppos a pointer to the cookie that should be given back in the 796 * next call to make function handle the next element. If 797 * *ppos is set to NULL it will restart the iterator. 798 * If returned *ppos == NULL this means that the last 799 * element has been handled. 800 * 801 * @return int 802 */ 803 int (*restore)(struct bnx2x_softc *sc, 804 struct ecore_vlan_mac_ramrod_params *p, 805 struct ecore_vlan_mac_registry_elem **ppos); 806 807 /** 808 * Should be called on a completion arrival. 809 * 810 * @param sc 811 * @param o 812 * @param cqe Completion element we are handling 813 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 814 * pending commands will be executed. 815 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 816 * may also be set if needed. 817 * 818 * @return 0 if there are neither pending nor waiting for 819 * completion commands. Positive value if there are 820 * pending for execution or for completion commands. 821 * Negative value in case of an error (including an 822 * error in the cqe). 823 */ 824 int (*complete)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o, 825 union event_ring_elem *cqe, 826 unsigned long *ramrod_flags); 827 828 /** 829 * Wait for completion of all commands. Don't schedule new ones, 830 * just wait. It assumes that the completion code will schedule 831 * for new commands. 832 */ 833 int (*wait)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o); 834 }; 835 836 enum { 837 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0, 838 ECORE_LLH_CAM_ETH_LINE, 839 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 840 }; 841 842 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 843 844 /* RX_MODE ramrod special flags: set in rx_mode_flags field in 845 * a ecore_rx_mode_ramrod_params. 846 */ 847 enum { 848 ECORE_RX_MODE_FCOE_ETH, 849 ECORE_RX_MODE_ISCSI_ETH, 850 }; 851 852 enum { 853 ECORE_ACCEPT_UNICAST, 854 ECORE_ACCEPT_MULTICAST, 855 ECORE_ACCEPT_ALL_UNICAST, 856 ECORE_ACCEPT_ALL_MULTICAST, 857 ECORE_ACCEPT_BROADCAST, 858 ECORE_ACCEPT_UNMATCHED, 859 ECORE_ACCEPT_ANY_VLAN 860 }; 861 862 struct ecore_rx_mode_ramrod_params { 863 struct ecore_rx_mode_obj *rx_mode_obj; 864 unsigned long *pstate; 865 int state; 866 uint8_t cl_id; 867 uint32_t cid; 868 uint8_t func_id; 869 unsigned long ramrod_flags; 870 unsigned long rx_mode_flags; 871 872 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 873 * a tstorm_eth_mac_filter_config (e1x). 874 */ 875 void *rdata; 876 ecore_dma_addr_t rdata_mapping; 877 878 /* Rx mode settings */ 879 unsigned long rx_accept_flags; 880 881 /* internal switching settings */ 882 unsigned long tx_accept_flags; 883 }; 884 885 struct ecore_rx_mode_obj { 886 int (*config_rx_mode)(struct bnx2x_softc *sc, 887 struct ecore_rx_mode_ramrod_params *p); 888 889 int (*wait_comp)(struct bnx2x_softc *sc, 890 struct ecore_rx_mode_ramrod_params *p); 891 }; 892 893 /********************** Set multicast group ***********************************/ 894 895 struct ecore_mcast_list_elem { 896 ecore_list_entry_t link; 897 uint8_t *mac; 898 }; 899 900 union ecore_mcast_config_data { 901 uint8_t *mac; 902 uint8_t bin; /* used in a RESTORE flow */ 903 }; 904 905 struct ecore_mcast_ramrod_params { 906 struct ecore_mcast_obj *mcast_obj; 907 908 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 909 unsigned long ramrod_flags; 910 911 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */ 912 int mcast_list_len; 913 }; 914 915 enum ecore_mcast_cmd { 916 ECORE_MCAST_CMD_ADD, 917 ECORE_MCAST_CMD_CONT, 918 ECORE_MCAST_CMD_DEL, 919 ECORE_MCAST_CMD_RESTORE, 920 }; 921 922 struct ecore_mcast_obj { 923 struct ecore_raw_obj raw; 924 925 union { 926 struct { 927 #define ECORE_MCAST_BINS_NUM 256 928 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64) 929 uint64_t vec[ECORE_MCAST_VEC_SZ]; 930 931 /** Number of BINs to clear. Should be updated 932 * immediately when a command arrives in order to 933 * properly create DEL commands. 934 */ 935 int num_bins_set; 936 } aprox_match; 937 938 struct { 939 ecore_list_t macs; 940 int num_macs_set; 941 } exact_match; 942 } registry; 943 944 /* Pending commands */ 945 ecore_list_t pending_cmds_head; 946 947 /* A state that is set in raw.pstate, when there are pending commands */ 948 int sched_state; 949 950 /* Maximal number of mcast MACs configured in one command */ 951 int max_cmd_len; 952 953 /* Total number of currently pending MACs to configure: both 954 * in the pending commands list and in the current command. 955 */ 956 int total_pending_num; 957 958 uint8_t engine_id; 959 960 /** 961 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above) 962 */ 963 int (*config_mcast)(struct bnx2x_softc *sc, 964 struct ecore_mcast_ramrod_params *p, 965 enum ecore_mcast_cmd cmd); 966 967 /** 968 * Fills the ramrod data during the RESTORE flow. 969 * 970 * @param sc 971 * @param o 972 * @param start_idx Registry index to start from 973 * @param rdata_idx Index in the ramrod data to start from 974 * 975 * @return -1 if we handled the whole registry or index of the last 976 * handled registry element. 977 */ 978 int (*hdl_restore)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o, 979 int start_bin, int *rdata_idx); 980 981 int (*enqueue_cmd)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o, 982 struct ecore_mcast_ramrod_params *p, 983 enum ecore_mcast_cmd cmd); 984 985 void (*set_one_rule)(struct bnx2x_softc *sc, 986 struct ecore_mcast_obj *o, int idx, 987 union ecore_mcast_config_data *cfg_data, 988 enum ecore_mcast_cmd cmd); 989 990 /** Checks if there are more mcast MACs to be set or a previous 991 * command is still pending. 992 */ 993 int (*check_pending)(struct ecore_mcast_obj *o); 994 995 /** 996 * Set/Clear/Check SCHEDULED state of the object 997 */ 998 void (*set_sched)(struct ecore_mcast_obj *o); 999 void (*clear_sched)(struct ecore_mcast_obj *o); 1000 int (*check_sched)(struct ecore_mcast_obj *o); 1001 1002 /* Wait until all pending commands complete */ 1003 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o); 1004 1005 /** 1006 * Handle the internal object counters needed for proper 1007 * commands handling. Checks that the provided parameters are 1008 * feasible. 1009 */ 1010 int (*validate)(struct bnx2x_softc *sc, 1011 struct ecore_mcast_ramrod_params *p, 1012 enum ecore_mcast_cmd cmd); 1013 1014 /** 1015 * Restore the values of internal counters in case of a failure. 1016 */ 1017 void (*revert)(struct bnx2x_softc *sc, 1018 struct ecore_mcast_ramrod_params *p, 1019 int old_num_bins); 1020 1021 int (*get_registry_size)(struct ecore_mcast_obj *o); 1022 void (*set_registry_size)(struct ecore_mcast_obj *o, int n); 1023 }; 1024 1025 /*************************** Credit handling **********************************/ 1026 struct ecore_credit_pool_obj { 1027 1028 /* Current amount of credit in the pool */ 1029 ecore_atomic_t credit; 1030 1031 /* Maximum allowed credit. put() will check against it. */ 1032 int pool_sz; 1033 1034 /* Allocate a pool table statically. 1035 * 1036 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 1037 * 1038 * The set bit in the table will mean that the entry is available. 1039 */ 1040 #define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 1041 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE]; 1042 1043 /* Base pool offset (initialized differently */ 1044 int base_pool_offset; 1045 1046 /** 1047 * Get the next free pool entry. 1048 * 1049 * @return TRUE if there was a free entry in the pool 1050 */ 1051 int (*get_entry)(struct ecore_credit_pool_obj *o, int *entry); 1052 1053 /** 1054 * Return the entry back to the pool. 1055 * 1056 * @return TRUE if entry is legal and has been successfully 1057 * returned to the pool. 1058 */ 1059 int (*put_entry)(struct ecore_credit_pool_obj *o, int entry); 1060 1061 /** 1062 * Get the requested amount of credit from the pool. 1063 * 1064 * @param cnt Amount of requested credit 1065 * @return TRUE if the operation is successful 1066 */ 1067 int (*get)(struct ecore_credit_pool_obj *o, int cnt); 1068 1069 /** 1070 * Returns the credit to the pool. 1071 * 1072 * @param cnt Amount of credit to return 1073 * @return TRUE if the operation is successful 1074 */ 1075 int (*put)(struct ecore_credit_pool_obj *o, int cnt); 1076 1077 /** 1078 * Reads the current amount of credit. 1079 */ 1080 int (*check)(struct ecore_credit_pool_obj *o); 1081 }; 1082 1083 /*************************** RSS configuration ********************************/ 1084 enum { 1085 /* RSS_MODE bits are mutually exclusive */ 1086 ECORE_RSS_MODE_DISABLED, 1087 ECORE_RSS_MODE_REGULAR, 1088 1089 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 1090 1091 ECORE_RSS_IPV4, 1092 ECORE_RSS_IPV4_TCP, 1093 ECORE_RSS_IPV4_UDP, 1094 ECORE_RSS_IPV6, 1095 ECORE_RSS_IPV6_TCP, 1096 ECORE_RSS_IPV6_UDP, 1097 1098 ECORE_RSS_TUNNELING, 1099 }; 1100 1101 struct ecore_config_rss_params { 1102 struct ecore_rss_config_obj *rss_obj; 1103 1104 /* may have RAMROD_COMP_WAIT set only */ 1105 unsigned long ramrod_flags; 1106 1107 /* ECORE_RSS_X bits */ 1108 unsigned long rss_flags; 1109 1110 /* Number hash bits to take into an account */ 1111 uint8_t rss_result_mask; 1112 1113 /* Indirection table */ 1114 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1115 1116 /* RSS hash values */ 1117 uint32_t rss_key[10]; 1118 1119 /* valid only if ECORE_RSS_UPDATE_TOE is set */ 1120 uint16_t toe_rss_bitmap; 1121 1122 /* valid if ECORE_RSS_TUNNELING is set */ 1123 uint16_t tunnel_value; 1124 uint16_t tunnel_mask; 1125 }; 1126 1127 struct ecore_rss_config_obj { 1128 struct ecore_raw_obj raw; 1129 1130 /* RSS engine to use */ 1131 uint8_t engine_id; 1132 1133 /* Last configured indirection table */ 1134 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1135 1136 /* flags for enabling 4-tupple hash on UDP */ 1137 uint8_t udp_rss_v4; 1138 uint8_t udp_rss_v6; 1139 1140 int (*config_rss)(struct bnx2x_softc *sc, 1141 struct ecore_config_rss_params *p); 1142 }; 1143 1144 /*********************** Queue state update ***********************************/ 1145 1146 /* UPDATE command options */ 1147 enum { 1148 ECORE_Q_UPDATE_IN_VLAN_REM, 1149 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG, 1150 ECORE_Q_UPDATE_OUT_VLAN_REM, 1151 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG, 1152 ECORE_Q_UPDATE_ANTI_SPOOF, 1153 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG, 1154 ECORE_Q_UPDATE_ACTIVATE, 1155 ECORE_Q_UPDATE_ACTIVATE_CHNG, 1156 ECORE_Q_UPDATE_DEF_VLAN_EN, 1157 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG, 1158 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG, 1159 ECORE_Q_UPDATE_SILENT_VLAN_REM, 1160 ECORE_Q_UPDATE_TX_SWITCHING_CHNG, 1161 ECORE_Q_UPDATE_TX_SWITCHING, 1162 }; 1163 1164 /* Allowed Queue states */ 1165 enum ecore_q_state { 1166 ECORE_Q_STATE_RESET, 1167 ECORE_Q_STATE_INITIALIZED, 1168 ECORE_Q_STATE_ACTIVE, 1169 ECORE_Q_STATE_MULTI_COS, 1170 ECORE_Q_STATE_MCOS_TERMINATED, 1171 ECORE_Q_STATE_INACTIVE, 1172 ECORE_Q_STATE_STOPPED, 1173 ECORE_Q_STATE_TERMINATED, 1174 ECORE_Q_STATE_FLRED, 1175 ECORE_Q_STATE_MAX, 1176 }; 1177 1178 /* Allowed Queue states */ 1179 enum ecore_q_logical_state { 1180 ECORE_Q_LOGICAL_STATE_ACTIVE, 1181 ECORE_Q_LOGICAL_STATE_STOPPED, 1182 }; 1183 1184 /* Allowed commands */ 1185 enum ecore_queue_cmd { 1186 ECORE_Q_CMD_INIT, 1187 ECORE_Q_CMD_SETUP, 1188 ECORE_Q_CMD_SETUP_TX_ONLY, 1189 ECORE_Q_CMD_DEACTIVATE, 1190 ECORE_Q_CMD_ACTIVATE, 1191 ECORE_Q_CMD_UPDATE, 1192 ECORE_Q_CMD_UPDATE_TPA, 1193 ECORE_Q_CMD_HALT, 1194 ECORE_Q_CMD_CFC_DEL, 1195 ECORE_Q_CMD_TERMINATE, 1196 ECORE_Q_CMD_EMPTY, 1197 ECORE_Q_CMD_MAX, 1198 }; 1199 1200 /* queue SETUP + INIT flags */ 1201 enum { 1202 ECORE_Q_FLG_TPA, 1203 ECORE_Q_FLG_TPA_IPV6, 1204 ECORE_Q_FLG_TPA_GRO, 1205 ECORE_Q_FLG_STATS, 1206 ECORE_Q_FLG_ZERO_STATS, 1207 ECORE_Q_FLG_ACTIVE, 1208 ECORE_Q_FLG_OV, 1209 ECORE_Q_FLG_VLAN, 1210 ECORE_Q_FLG_COS, 1211 ECORE_Q_FLG_HC, 1212 ECORE_Q_FLG_HC_EN, 1213 ECORE_Q_FLG_DHC, 1214 ECORE_Q_FLG_OOO, 1215 ECORE_Q_FLG_FCOE, 1216 ECORE_Q_FLG_LEADING_RSS, 1217 ECORE_Q_FLG_MCAST, 1218 ECORE_Q_FLG_DEF_VLAN, 1219 ECORE_Q_FLG_TX_SWITCH, 1220 ECORE_Q_FLG_TX_SEC, 1221 ECORE_Q_FLG_ANTI_SPOOF, 1222 ECORE_Q_FLG_SILENT_VLAN_REM, 1223 ECORE_Q_FLG_FORCE_DEFAULT_PRI, 1224 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, 1225 ECORE_Q_FLG_PCSUM_ON_PKT, 1226 ECORE_Q_FLG_TUN_INC_INNER_IP_ID 1227 }; 1228 1229 /* Queue type options: queue type may be a combination of below. */ 1230 enum ecore_q_type { 1231 ECORE_Q_TYPE_FWD, 1232 ECORE_Q_TYPE_HAS_RX, 1233 ECORE_Q_TYPE_HAS_TX, 1234 }; 1235 1236 #define ECORE_PRIMARY_CID_INDEX 0 1237 #define ECORE_MULTI_TX_COS_E1X 3 /* QM only */ 1238 #define ECORE_MULTI_TX_COS_E2_E3A0 2 1239 #define ECORE_MULTI_TX_COS_E3B0 3 1240 #define ECORE_MULTI_TX_COS 3 /* Maximum possible */ 1241 #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN) 1242 1243 struct ecore_queue_init_params { 1244 struct { 1245 unsigned long flags; 1246 uint16_t hc_rate; 1247 uint8_t fw_sb_id; 1248 uint8_t sb_cq_index; 1249 } tx; 1250 1251 struct { 1252 unsigned long flags; 1253 uint16_t hc_rate; 1254 uint8_t fw_sb_id; 1255 uint8_t sb_cq_index; 1256 } rx; 1257 1258 /* CID context in the host memory */ 1259 struct eth_context *cxts[ECORE_MULTI_TX_COS]; 1260 1261 /* maximum number of cos supported by hardware */ 1262 uint8_t max_cos; 1263 }; 1264 1265 struct ecore_queue_terminate_params { 1266 /* index within the tx_only cids of this queue object */ 1267 uint8_t cid_index; 1268 }; 1269 1270 struct ecore_queue_cfc_del_params { 1271 /* index within the tx_only cids of this queue object */ 1272 uint8_t cid_index; 1273 }; 1274 1275 struct ecore_queue_update_params { 1276 unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */ 1277 uint16_t def_vlan; 1278 uint16_t silent_removal_value; 1279 uint16_t silent_removal_mask; 1280 /* index within the tx_only cids of this queue object */ 1281 uint8_t cid_index; 1282 }; 1283 1284 struct rxq_pause_params { 1285 uint16_t bd_th_lo; 1286 uint16_t bd_th_hi; 1287 uint16_t rcq_th_lo; 1288 uint16_t rcq_th_hi; 1289 uint16_t sge_th_lo; /* valid if ECORE_Q_FLG_TPA */ 1290 uint16_t sge_th_hi; /* valid if ECORE_Q_FLG_TPA */ 1291 uint16_t pri_map; 1292 }; 1293 1294 /* general */ 1295 struct ecore_general_setup_params { 1296 /* valid if ECORE_Q_FLG_STATS */ 1297 uint8_t stat_id; 1298 1299 uint8_t spcl_id; 1300 uint16_t mtu; 1301 uint8_t cos; 1302 }; 1303 1304 struct ecore_rxq_setup_params { 1305 /* dma */ 1306 ecore_dma_addr_t dscr_map; 1307 ecore_dma_addr_t rcq_map; 1308 ecore_dma_addr_t rcq_np_map; 1309 1310 uint16_t drop_flags; 1311 uint16_t buf_sz; 1312 uint8_t fw_sb_id; 1313 uint8_t cl_qzone_id; 1314 1315 /* valid if ECORE_Q_FLG_TPA */ 1316 uint16_t tpa_agg_sz; 1317 uint8_t max_tpa_queues; 1318 uint8_t rss_engine_id; 1319 1320 /* valid if ECORE_Q_FLG_MCAST */ 1321 uint8_t mcast_engine_id; 1322 1323 uint8_t cache_line_log; 1324 1325 uint8_t sb_cq_index; 1326 1327 /* valid if BXN2X_Q_FLG_SILENT_VLAN_REM */ 1328 uint16_t silent_removal_value; 1329 uint16_t silent_removal_mask; 1330 }; 1331 1332 struct ecore_txq_setup_params { 1333 /* dma */ 1334 ecore_dma_addr_t dscr_map; 1335 1336 uint8_t fw_sb_id; 1337 uint8_t sb_cq_index; 1338 uint8_t cos; /* valid if ECORE_Q_FLG_COS */ 1339 uint16_t traffic_type; 1340 /* equals to the leading rss client id, used for TX classification*/ 1341 uint8_t tss_leading_cl_id; 1342 1343 /* valid if ECORE_Q_FLG_DEF_VLAN */ 1344 uint16_t default_vlan; 1345 }; 1346 1347 struct ecore_queue_setup_params { 1348 struct ecore_general_setup_params gen_params; 1349 struct ecore_txq_setup_params txq_params; 1350 struct ecore_rxq_setup_params rxq_params; 1351 struct rxq_pause_params pause_params; 1352 unsigned long flags; 1353 }; 1354 1355 struct ecore_queue_setup_tx_only_params { 1356 struct ecore_general_setup_params gen_params; 1357 struct ecore_txq_setup_params txq_params; 1358 unsigned long flags; 1359 /* index within the tx_only cids of this queue object */ 1360 uint8_t cid_index; 1361 }; 1362 1363 struct ecore_queue_state_params { 1364 struct ecore_queue_sp_obj *q_obj; 1365 1366 /* Current command */ 1367 enum ecore_queue_cmd cmd; 1368 1369 /* may have RAMROD_COMP_WAIT set only */ 1370 unsigned long ramrod_flags; 1371 1372 /* Params according to the current command */ 1373 union { 1374 struct ecore_queue_update_params update; 1375 struct ecore_queue_setup_params setup; 1376 struct ecore_queue_init_params init; 1377 struct ecore_queue_setup_tx_only_params tx_only; 1378 struct ecore_queue_terminate_params terminate; 1379 struct ecore_queue_cfc_del_params cfc_del; 1380 } params; 1381 }; 1382 1383 struct ecore_viflist_params { 1384 uint8_t echo_res; 1385 uint8_t func_bit_map_res; 1386 }; 1387 1388 struct ecore_queue_sp_obj { 1389 uint32_t cids[ECORE_MULTI_TX_COS]; 1390 uint8_t cl_id; 1391 uint8_t func_id; 1392 1393 /* number of traffic classes supported by queue. 1394 * The primary connection of the queue supports the first traffic 1395 * class. Any further traffic class is supported by a tx-only 1396 * connection. 1397 * 1398 * Therefore max_cos is also a number of valid entries in the cids 1399 * array. 1400 */ 1401 uint8_t max_cos; 1402 uint8_t num_tx_only, next_tx_only; 1403 1404 enum ecore_q_state state, next_state; 1405 1406 /* bits from enum ecore_q_type */ 1407 unsigned long type; 1408 1409 /* ECORE_Q_CMD_XX bits. This object implements "one 1410 * pending" paradigm but for debug and tracing purposes it's 1411 * more convenient to have different bits for different 1412 * commands. 1413 */ 1414 unsigned long pending; 1415 1416 /* Buffer to use as a ramrod data and its mapping */ 1417 void *rdata; 1418 ecore_dma_addr_t rdata_mapping; 1419 1420 /** 1421 * Performs one state change according to the given parameters. 1422 * 1423 * @return 0 in case of success and negative value otherwise. 1424 */ 1425 int (*send_cmd)(struct bnx2x_softc *sc, 1426 struct ecore_queue_state_params *params); 1427 1428 /** 1429 * Sets the pending bit according to the requested transition. 1430 */ 1431 int (*set_pending)(struct ecore_queue_sp_obj *o, 1432 struct ecore_queue_state_params *params); 1433 1434 /** 1435 * Checks that the requested state transition is legal. 1436 */ 1437 int (*check_transition)(struct bnx2x_softc *sc, 1438 struct ecore_queue_sp_obj *o, 1439 struct ecore_queue_state_params *params); 1440 1441 /** 1442 * Completes the pending command. 1443 */ 1444 int (*complete_cmd)(struct bnx2x_softc *sc, 1445 struct ecore_queue_sp_obj *o, 1446 enum ecore_queue_cmd); 1447 1448 int (*wait_comp)(struct bnx2x_softc *sc, 1449 struct ecore_queue_sp_obj *o, 1450 enum ecore_queue_cmd cmd); 1451 }; 1452 1453 /********************** Function state update *********************************/ 1454 /* Allowed Function states */ 1455 enum ecore_func_state { 1456 ECORE_F_STATE_RESET, 1457 ECORE_F_STATE_INITIALIZED, 1458 ECORE_F_STATE_STARTED, 1459 ECORE_F_STATE_TX_STOPPED, 1460 ECORE_F_STATE_MAX, 1461 }; 1462 1463 /* Allowed Function commands */ 1464 enum ecore_func_cmd { 1465 ECORE_F_CMD_HW_INIT, 1466 ECORE_F_CMD_START, 1467 ECORE_F_CMD_STOP, 1468 ECORE_F_CMD_HW_RESET, 1469 ECORE_F_CMD_AFEX_UPDATE, 1470 ECORE_F_CMD_AFEX_VIFLISTS, 1471 ECORE_F_CMD_TX_STOP, 1472 ECORE_F_CMD_TX_START, 1473 ECORE_F_CMD_SWITCH_UPDATE, 1474 ECORE_F_CMD_MAX, 1475 }; 1476 1477 struct ecore_func_hw_init_params { 1478 /* A load phase returned by MCP. 1479 * 1480 * May be: 1481 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1482 * FW_MSG_CODE_DRV_LOAD_COMMON 1483 * FW_MSG_CODE_DRV_LOAD_PORT 1484 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1485 */ 1486 uint32_t load_phase; 1487 }; 1488 1489 struct ecore_func_hw_reset_params { 1490 /* A load phase returned by MCP. 1491 * 1492 * May be: 1493 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1494 * FW_MSG_CODE_DRV_LOAD_COMMON 1495 * FW_MSG_CODE_DRV_LOAD_PORT 1496 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1497 */ 1498 uint32_t reset_phase; 1499 }; 1500 1501 struct ecore_func_start_params { 1502 /* Multi Function mode: 1503 * - Single Function 1504 * - Switch Dependent 1505 * - Switch Independent 1506 */ 1507 uint16_t mf_mode; 1508 1509 /* Switch Dependent mode outer VLAN tag */ 1510 uint16_t sd_vlan_tag; 1511 1512 /* Function cos mode */ 1513 uint8_t network_cos_mode; 1514 1515 /* NVGRE classification enablement */ 1516 uint8_t nvgre_clss_en; 1517 1518 /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ 1519 uint8_t gre_tunnel_mode; 1520 1521 /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ 1522 uint8_t gre_tunnel_rss; 1523 1524 }; 1525 1526 struct ecore_func_switch_update_params { 1527 uint8_t suspend; 1528 }; 1529 1530 struct ecore_func_afex_update_params { 1531 uint16_t vif_id; 1532 uint16_t afex_default_vlan; 1533 uint8_t allowed_priorities; 1534 }; 1535 1536 struct ecore_func_afex_viflists_params { 1537 uint16_t vif_list_index; 1538 uint8_t func_bit_map; 1539 uint8_t afex_vif_list_command; 1540 uint8_t func_to_clear; 1541 }; 1542 struct ecore_func_tx_start_params { 1543 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1544 uint8_t dcb_enabled; 1545 uint8_t dcb_version; 1546 uint8_t dont_add_pri_0; 1547 }; 1548 1549 struct ecore_func_state_params { 1550 struct ecore_func_sp_obj *f_obj; 1551 1552 /* Current command */ 1553 enum ecore_func_cmd cmd; 1554 1555 /* may have RAMROD_COMP_WAIT set only */ 1556 unsigned long ramrod_flags; 1557 1558 /* Params according to the current command */ 1559 union { 1560 struct ecore_func_hw_init_params hw_init; 1561 struct ecore_func_hw_reset_params hw_reset; 1562 struct ecore_func_start_params start; 1563 struct ecore_func_switch_update_params switch_update; 1564 struct ecore_func_afex_update_params afex_update; 1565 struct ecore_func_afex_viflists_params afex_viflists; 1566 struct ecore_func_tx_start_params tx_start; 1567 } params; 1568 }; 1569 1570 struct ecore_func_sp_drv_ops { 1571 /* Init tool + runtime initialization: 1572 * - Common Chip 1573 * - Common (per Path) 1574 * - Port 1575 * - Function phases 1576 */ 1577 int (*init_hw_cmn_chip)(struct bnx2x_softc *sc); 1578 int (*init_hw_cmn)(struct bnx2x_softc *sc); 1579 int (*init_hw_port)(struct bnx2x_softc *sc); 1580 int (*init_hw_func)(struct bnx2x_softc *sc); 1581 1582 /* Reset Function HW: Common, Port, Function phases. */ 1583 void (*reset_hw_cmn)(struct bnx2x_softc *sc); 1584 void (*reset_hw_port)(struct bnx2x_softc *sc); 1585 void (*reset_hw_func)(struct bnx2x_softc *sc); 1586 1587 /* Prepare/Release FW resources */ 1588 int (*init_fw)(struct bnx2x_softc *sc); 1589 void (*release_fw)(struct bnx2x_softc *sc); 1590 }; 1591 1592 struct ecore_func_sp_obj { 1593 enum ecore_func_state state, next_state; 1594 1595 /* ECORE_FUNC_CMD_XX bits. This object implements "one 1596 * pending" paradigm but for debug and tracing purposes it's 1597 * more convenient to have different bits for different 1598 * commands. 1599 */ 1600 unsigned long pending; 1601 1602 /* Buffer to use as a ramrod data and its mapping */ 1603 void *rdata; 1604 ecore_dma_addr_t rdata_mapping; 1605 1606 /* Buffer to use as a afex ramrod data and its mapping. 1607 * This can't be same rdata as above because afex ramrod requests 1608 * can arrive to the object in parallel to other ramrod requests. 1609 */ 1610 void *afex_rdata; 1611 ecore_dma_addr_t afex_rdata_mapping; 1612 1613 /* this mutex validates that when pending flag is taken, the next 1614 * ramrod to be sent will be the one set the pending bit 1615 */ 1616 ECORE_MUTEX one_pending_mutex; 1617 1618 /* Driver interface */ 1619 struct ecore_func_sp_drv_ops *drv; 1620 1621 /** 1622 * Performs one state change according to the given parameters. 1623 * 1624 * @return 0 in case of success and negative value otherwise. 1625 */ 1626 int (*send_cmd)(struct bnx2x_softc *sc, 1627 struct ecore_func_state_params *params); 1628 1629 /** 1630 * Checks that the requested state transition is legal. 1631 */ 1632 int (*check_transition)(struct bnx2x_softc *sc, 1633 struct ecore_func_sp_obj *o, 1634 struct ecore_func_state_params *params); 1635 1636 /** 1637 * Completes the pending command. 1638 */ 1639 int (*complete_cmd)(struct bnx2x_softc *sc, 1640 struct ecore_func_sp_obj *o, 1641 enum ecore_func_cmd cmd); 1642 1643 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_func_sp_obj *o, 1644 enum ecore_func_cmd cmd); 1645 }; 1646 1647 /********************** Interfaces ********************************************/ 1648 /* Queueable objects set */ 1649 union ecore_qable_obj { 1650 struct ecore_vlan_mac_obj vlan_mac; 1651 }; 1652 /************** Function state update *********/ 1653 void ecore_init_func_obj(struct bnx2x_softc *sc, 1654 struct ecore_func_sp_obj *obj, 1655 void *rdata, ecore_dma_addr_t rdata_mapping, 1656 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping, 1657 struct ecore_func_sp_drv_ops *drv_iface); 1658 1659 int ecore_func_state_change(struct bnx2x_softc *sc, 1660 struct ecore_func_state_params *params); 1661 1662 enum ecore_func_state ecore_func_get_state(struct bnx2x_softc *sc, 1663 struct ecore_func_sp_obj *o); 1664 /******************* Queue State **************/ 1665 void ecore_init_queue_obj(struct bnx2x_softc *sc, 1666 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids, 1667 uint8_t cid_cnt, uint8_t func_id, void *rdata, 1668 ecore_dma_addr_t rdata_mapping, unsigned long type); 1669 1670 int ecore_queue_state_change(struct bnx2x_softc *sc, 1671 struct ecore_queue_state_params *params); 1672 1673 /********************* VLAN-MAC ****************/ 1674 void ecore_init_mac_obj(struct bnx2x_softc *sc, 1675 struct ecore_vlan_mac_obj *mac_obj, 1676 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1677 ecore_dma_addr_t rdata_mapping, int state, 1678 unsigned long *pstate, ecore_obj_type type, 1679 struct ecore_credit_pool_obj *macs_pool); 1680 1681 void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc, 1682 struct ecore_vlan_mac_obj *o); 1683 int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc, 1684 struct ecore_vlan_mac_obj *o); 1685 void ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc, 1686 struct ecore_vlan_mac_obj *o); 1687 int ecore_config_vlan_mac(struct bnx2x_softc *sc, 1688 struct ecore_vlan_mac_ramrod_params *p); 1689 1690 int ecore_vlan_mac_move(struct bnx2x_softc *sc, 1691 struct ecore_vlan_mac_ramrod_params *p, 1692 struct ecore_vlan_mac_obj *dest_o); 1693 1694 /********************* RX MODE ****************/ 1695 1696 void ecore_init_rx_mode_obj(struct bnx2x_softc *sc, 1697 struct ecore_rx_mode_obj *o); 1698 1699 /** 1700 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1701 * 1702 * @p: Command parameters 1703 * 1704 * Return: 0 - if operation was successful and there is no pending completions, 1705 * positive number - if there are pending completions, 1706 * negative - if there were errors 1707 */ 1708 int ecore_config_rx_mode(struct bnx2x_softc *sc, 1709 struct ecore_rx_mode_ramrod_params *p); 1710 1711 /****************** MULTICASTS ****************/ 1712 1713 void ecore_init_mcast_obj(struct bnx2x_softc *sc, 1714 struct ecore_mcast_obj *mcast_obj, 1715 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id, 1716 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping, 1717 int state, unsigned long *pstate, 1718 ecore_obj_type type); 1719 1720 /** 1721 * ecore_config_mcast - Configure multicast MACs list. 1722 * 1723 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1724 * 1725 * May configure a new list 1726 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up 1727 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current 1728 * configuration, continue to execute the pending commands 1729 * (ECORE_MCAST_CMD_CONT). 1730 * 1731 * If previous command is still pending or if number of MACs to 1732 * configure is more that maximum number of MACs in one command, 1733 * the current command will be enqueued to the tail of the 1734 * pending commands list. 1735 * 1736 * Return: 0 is operation was successful and there are no pending completions, 1737 * negative if there were errors, positive if there are pending 1738 * completions. 1739 */ 1740 int ecore_config_mcast(struct bnx2x_softc *sc, 1741 struct ecore_mcast_ramrod_params *p, 1742 enum ecore_mcast_cmd cmd); 1743 1744 /****************** CREDIT POOL ****************/ 1745 void ecore_init_mac_credit_pool(struct bnx2x_softc *sc, 1746 struct ecore_credit_pool_obj *p, uint8_t func_id, 1747 uint8_t func_num); 1748 void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc, 1749 struct ecore_credit_pool_obj *p, uint8_t func_id, 1750 uint8_t func_num); 1751 1752 /****************** RSS CONFIGURATION ****************/ 1753 void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj, 1754 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id, 1755 void *rdata, ecore_dma_addr_t rdata_mapping, 1756 int state, unsigned long *pstate, 1757 ecore_obj_type type); 1758 1759 /** 1760 * ecore_config_rss - Updates RSS configuration according to provided parameters 1761 * 1762 * Return: 0 in case of success 1763 */ 1764 int ecore_config_rss(struct bnx2x_softc *sc, 1765 struct ecore_config_rss_params *p); 1766 1767 1768 #endif /* ECORE_SP_H */ 1769