1d30ea906Sjfb8856606 /* SPDX-License-Identifier: BSD-3-Clause 2d30ea906Sjfb8856606 * Copyright(c) 2018 Aquantia Corporation 3d30ea906Sjfb8856606 */ 4d30ea906Sjfb8856606 5d30ea906Sjfb8856606 #ifndef _ATLANTIC_ETHDEV_H_ 6d30ea906Sjfb8856606 #define _ATLANTIC_ETHDEV_H_ 7d30ea906Sjfb8856606 #include <rte_errno.h> 8d30ea906Sjfb8856606 #include "rte_ethdev.h" 9d30ea906Sjfb8856606 10d30ea906Sjfb8856606 #include "atl_types.h" 11d30ea906Sjfb8856606 #include "hw_atl/hw_atl_utils.h" 12d30ea906Sjfb8856606 13d30ea906Sjfb8856606 #define ATL_RSS_OFFLOAD_ALL ( \ 14d30ea906Sjfb8856606 ETH_RSS_IPV4 | \ 15d30ea906Sjfb8856606 ETH_RSS_NONFRAG_IPV4_TCP | \ 16d30ea906Sjfb8856606 ETH_RSS_NONFRAG_IPV4_UDP | \ 17d30ea906Sjfb8856606 ETH_RSS_IPV6 | \ 18d30ea906Sjfb8856606 ETH_RSS_NONFRAG_IPV6_TCP | \ 19d30ea906Sjfb8856606 ETH_RSS_NONFRAG_IPV6_UDP | \ 20d30ea906Sjfb8856606 ETH_RSS_IPV6_EX | \ 21d30ea906Sjfb8856606 ETH_RSS_IPV6_TCP_EX | \ 22d30ea906Sjfb8856606 ETH_RSS_IPV6_UDP_EX) 23d30ea906Sjfb8856606 24d30ea906Sjfb8856606 #define ATL_DEV_PRIVATE_TO_HW(adapter) \ 25d30ea906Sjfb8856606 (&((struct atl_adapter *)adapter)->hw) 26d30ea906Sjfb8856606 27d30ea906Sjfb8856606 #define ATL_DEV_TO_ADAPTER(dev) \ 28d30ea906Sjfb8856606 ((struct atl_adapter *)(dev)->data->dev_private) 29d30ea906Sjfb8856606 30d30ea906Sjfb8856606 #define ATL_DEV_PRIVATE_TO_INTR(adapter) \ 31d30ea906Sjfb8856606 (&((struct atl_adapter *)adapter)->intr) 32d30ea906Sjfb8856606 33d30ea906Sjfb8856606 #define ATL_DEV_PRIVATE_TO_CFG(adapter) \ 34d30ea906Sjfb8856606 (&((struct atl_adapter *)adapter)->hw_cfg) 35d30ea906Sjfb8856606 36d30ea906Sjfb8856606 #define ATL_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) 37*4418919fSjohnjiang #define ATL_FLAG_MACSEC (uint32_t)(4 << 0) 38d30ea906Sjfb8856606 39d30ea906Sjfb8856606 struct atl_interrupt { 40d30ea906Sjfb8856606 uint32_t flags; 41d30ea906Sjfb8856606 uint32_t mask; 42d30ea906Sjfb8856606 }; 43d30ea906Sjfb8856606 44d30ea906Sjfb8856606 /* 45d30ea906Sjfb8856606 * Structure to store private data for each driver instance (for each port). 46d30ea906Sjfb8856606 */ 47d30ea906Sjfb8856606 struct atl_adapter { 48d30ea906Sjfb8856606 struct aq_hw_s hw; 49d30ea906Sjfb8856606 struct aq_hw_cfg_s hw_cfg; 50d30ea906Sjfb8856606 struct atl_sw_stats sw_stats; 51d30ea906Sjfb8856606 struct atl_interrupt intr; 52d30ea906Sjfb8856606 }; 53d30ea906Sjfb8856606 54d30ea906Sjfb8856606 /* 55d30ea906Sjfb8856606 * RX/TX function prototypes 56d30ea906Sjfb8856606 */ 57d30ea906Sjfb8856606 void atl_rx_queue_release(void *rxq); 58d30ea906Sjfb8856606 void atl_tx_queue_release(void *txq); 59d30ea906Sjfb8856606 60d30ea906Sjfb8856606 int atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 61d30ea906Sjfb8856606 uint16_t nb_rx_desc, unsigned int socket_id, 62d30ea906Sjfb8856606 const struct rte_eth_rxconf *rx_conf, 63d30ea906Sjfb8856606 struct rte_mempool *mb_pool); 64d30ea906Sjfb8856606 65d30ea906Sjfb8856606 int atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 66d30ea906Sjfb8856606 uint16_t nb_tx_desc, unsigned int socket_id, 67d30ea906Sjfb8856606 const struct rte_eth_txconf *tx_conf); 68d30ea906Sjfb8856606 69d30ea906Sjfb8856606 uint32_t atl_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id); 70d30ea906Sjfb8856606 71d30ea906Sjfb8856606 int atl_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); 72d30ea906Sjfb8856606 int atl_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); 73d30ea906Sjfb8856606 74d30ea906Sjfb8856606 int atl_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 75d30ea906Sjfb8856606 uint16_t queue_id); 76d30ea906Sjfb8856606 int atl_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 77d30ea906Sjfb8856606 uint16_t queue_id); 78d30ea906Sjfb8856606 79d30ea906Sjfb8856606 int atl_rx_init(struct rte_eth_dev *dev); 80d30ea906Sjfb8856606 int atl_tx_init(struct rte_eth_dev *dev); 81d30ea906Sjfb8856606 82d30ea906Sjfb8856606 int atl_start_queues(struct rte_eth_dev *dev); 83d30ea906Sjfb8856606 int atl_stop_queues(struct rte_eth_dev *dev); 84d30ea906Sjfb8856606 void atl_free_queues(struct rte_eth_dev *dev); 85d30ea906Sjfb8856606 86d30ea906Sjfb8856606 int atl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 87d30ea906Sjfb8856606 int atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 88d30ea906Sjfb8856606 89d30ea906Sjfb8856606 int atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 90d30ea906Sjfb8856606 int atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 91d30ea906Sjfb8856606 92d30ea906Sjfb8856606 void atl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 93d30ea906Sjfb8856606 struct rte_eth_rxq_info *qinfo); 94d30ea906Sjfb8856606 95d30ea906Sjfb8856606 void atl_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 96d30ea906Sjfb8856606 struct rte_eth_txq_info *qinfo); 97d30ea906Sjfb8856606 98d30ea906Sjfb8856606 uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 99d30ea906Sjfb8856606 uint16_t nb_pkts); 100d30ea906Sjfb8856606 101d30ea906Sjfb8856606 uint16_t atl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 102d30ea906Sjfb8856606 uint16_t nb_pkts); 103d30ea906Sjfb8856606 104d30ea906Sjfb8856606 uint16_t atl_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 105d30ea906Sjfb8856606 uint16_t nb_pkts); 106d30ea906Sjfb8856606 107*4418919fSjohnjiang int atl_macsec_enable(struct rte_eth_dev *dev, uint8_t encr, uint8_t repl_prot); 108*4418919fSjohnjiang int atl_macsec_disable(struct rte_eth_dev *dev); 109*4418919fSjohnjiang int atl_macsec_config_txsc(struct rte_eth_dev *dev, uint8_t *mac); 110*4418919fSjohnjiang int atl_macsec_config_rxsc(struct rte_eth_dev *dev, 111*4418919fSjohnjiang uint8_t *mac, uint16_t pi); 112*4418919fSjohnjiang int atl_macsec_select_txsa(struct rte_eth_dev *dev, uint8_t idx, 113*4418919fSjohnjiang uint8_t an, uint32_t pn, uint8_t *key); 114*4418919fSjohnjiang int atl_macsec_select_rxsa(struct rte_eth_dev *dev, uint8_t idx, 115*4418919fSjohnjiang uint8_t an, uint32_t pn, uint8_t *key); 116*4418919fSjohnjiang 117*4418919fSjohnjiang bool is_atlantic_supported(struct rte_eth_dev *dev); 118*4418919fSjohnjiang 119d30ea906Sjfb8856606 #endif /* _ATLANTIC_ETHDEV_H_ */ 120