1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Atomic Rules LLC 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _ARK_DDM_H_ 35 #define _ARK_DDM_H_ 36 37 #include <stdint.h> 38 39 #include <rte_memory.h> 40 41 42 /* The DDM or Downstream Data Mover is an internal Arkville hardware 43 * module for moving packet from host memory to the TX packet streams. 44 * This module is *not* intended for end-user manipulation, hence 45 * there is minimal documentation. 46 */ 47 48 /* struct defining Tx meta data -- fixed in FPGA -- 16 bytes */ 49 struct ark_tx_meta { 50 uint64_t physaddr; 51 uint32_t delta_ns; 52 uint16_t data_len; /* of this MBUF */ 53 #define ARK_DDM_EOP 0x01 54 #define ARK_DDM_SOP 0x02 55 uint8_t flags; /* bit 0 indicates last mbuf in chain. */ 56 uint8_t reserved[1]; 57 }; 58 59 60 /* 61 * DDM core hardware structures 62 * These are overlay structures to a memory mapped FPGA device. These 63 * structs will never be instantiated in ram memory 64 */ 65 #define ARK_DDM_CFG 0x0000 66 #define ARK_DDM_CONST 0xfacecafe 67 struct ark_ddm_cfg_t { 68 uint32_t r0; 69 volatile uint32_t tlp_stats_clear; 70 uint32_t const0; 71 volatile uint32_t tag_max; 72 volatile uint32_t command; 73 volatile uint32_t stop_flushed; 74 }; 75 76 #define ARK_DDM_STATS 0x0020 77 struct ark_ddm_stats_t { 78 volatile uint64_t tx_byte_count; 79 volatile uint64_t tx_pkt_count; 80 volatile uint64_t tx_mbuf_count; 81 }; 82 83 #define ARK_DDM_MRDQ 0x0040 84 struct ark_ddm_mrdq_t { 85 volatile uint32_t mrd_q1; 86 volatile uint32_t mrd_q2; 87 volatile uint32_t mrd_q3; 88 volatile uint32_t mrd_q4; 89 volatile uint32_t mrd_full; 90 }; 91 92 #define ARK_DDM_CPLDQ 0x0068 93 struct ark_ddm_cpldq_t { 94 volatile uint32_t cpld_q1; 95 volatile uint32_t cpld_q2; 96 volatile uint32_t cpld_q3; 97 volatile uint32_t cpld_q4; 98 volatile uint32_t cpld_full; 99 }; 100 101 #define ARK_DDM_MRD_PS 0x0090 102 struct ark_ddm_mrd_ps_t { 103 volatile uint32_t mrd_ps_min; 104 volatile uint32_t mrd_ps_max; 105 volatile uint32_t mrd_full_ps_min; 106 volatile uint32_t mrd_full_ps_max; 107 volatile uint32_t mrd_dw_ps_min; 108 volatile uint32_t mrd_dw_ps_max; 109 }; 110 111 #define ARK_DDM_QUEUE_STATS 0x00a8 112 struct ark_ddm_qstats_t { 113 volatile uint64_t byte_count; 114 volatile uint64_t pkt_count; 115 volatile uint64_t mbuf_count; 116 }; 117 118 #define ARK_DDM_CPLD_PS 0x00c0 119 struct ark_ddm_cpld_ps_t { 120 volatile uint32_t cpld_ps_min; 121 volatile uint32_t cpld_ps_max; 122 volatile uint32_t cpld_full_ps_min; 123 volatile uint32_t cpld_full_ps_max; 124 volatile uint32_t cpld_dw_ps_min; 125 volatile uint32_t cpld_dw_ps_max; 126 }; 127 128 #define ARK_DDM_SETUP 0x00e0 129 struct ark_ddm_setup_t { 130 rte_iova_t cons_write_index_addr; 131 uint32_t write_index_interval; /* 4ns each */ 132 volatile uint32_t cons_index; 133 }; 134 135 #define ARK_DDM_EXPECTED_SIZE 256 136 #define ARK_DDM_QOFFSET ARK_DDM_EXPECTED_SIZE 137 /* Consolidated structure */ 138 struct ark_ddm_t { 139 struct ark_ddm_cfg_t cfg; 140 uint8_t reserved0[(ARK_DDM_STATS - ARK_DDM_CFG) - 141 sizeof(struct ark_ddm_cfg_t)]; 142 struct ark_ddm_stats_t stats; 143 uint8_t reserved1[(ARK_DDM_MRDQ - ARK_DDM_STATS) - 144 sizeof(struct ark_ddm_stats_t)]; 145 struct ark_ddm_mrdq_t mrdq; 146 uint8_t reserved2[(ARK_DDM_CPLDQ - ARK_DDM_MRDQ) - 147 sizeof(struct ark_ddm_mrdq_t)]; 148 struct ark_ddm_cpldq_t cpldq; 149 uint8_t reserved3[(ARK_DDM_MRD_PS - ARK_DDM_CPLDQ) - 150 sizeof(struct ark_ddm_cpldq_t)]; 151 struct ark_ddm_mrd_ps_t mrd_ps; 152 struct ark_ddm_qstats_t queue_stats; 153 struct ark_ddm_cpld_ps_t cpld_ps; 154 uint8_t reserved5[(ARK_DDM_SETUP - ARK_DDM_CPLD_PS) - 155 sizeof(struct ark_ddm_cpld_ps_t)]; 156 struct ark_ddm_setup_t setup; 157 uint8_t reserved_p[(ARK_DDM_EXPECTED_SIZE - ARK_DDM_SETUP) - 158 sizeof(struct ark_ddm_setup_t)]; 159 }; 160 161 162 /* DDM function prototype */ 163 int ark_ddm_verify(struct ark_ddm_t *ddm); 164 void ark_ddm_start(struct ark_ddm_t *ddm); 165 int ark_ddm_stop(struct ark_ddm_t *ddm, const int wait); 166 void ark_ddm_reset(struct ark_ddm_t *ddm); 167 void ark_ddm_stats_reset(struct ark_ddm_t *ddm); 168 void ark_ddm_setup(struct ark_ddm_t *ddm, rte_iova_t cons_addr, 169 uint32_t interval); 170 void ark_ddm_dump_stats(struct ark_ddm_t *ddm, const char *msg); 171 void ark_ddm_dump(struct ark_ddm_t *ddm, const char *msg); 172 int ark_ddm_is_stopped(struct ark_ddm_t *ddm); 173 uint64_t ark_ddm_queue_byte_count(struct ark_ddm_t *ddm); 174 uint64_t ark_ddm_queue_pkt_count(struct ark_ddm_t *ddm); 175 void ark_ddm_queue_reset_stats(struct ark_ddm_t *ddm); 176 177 #endif 178