1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 NXP 3 */ 4 5 #ifndef __DPAA2_EVENTDEV_H__ 6 #define __DPAA2_EVENTDEV_H__ 7 8 #include <rte_eventdev_pmd.h> 9 #include <rte_eventdev_pmd_vdev.h> 10 #include <rte_atomic.h> 11 #include <mc/fsl_dpcon.h> 12 #include <mc/fsl_mc_sys.h> 13 14 #define EVENTDEV_NAME_DPAA2_PMD event_dpaa2 15 16 #define DPAA2_EVENT_DEFAULT_DPCI_PRIO 0 17 18 #define DPAA2_EVENT_MAX_QUEUES 16 19 #define DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT 1 20 #define DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT (UINT32_MAX - 1) 21 #define DPAA2_EVENT_PORT_DEQUEUE_TIMEOUT_NS 100UL 22 #define DPAA2_EVENT_MAX_QUEUE_FLOWS 2048 23 #define DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS 8 24 #define DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS 0 25 #define DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH 8 26 #define DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH 8 27 #define DPAA2_EVENT_MAX_NUM_EVENTS (INT32_MAX - 1) 28 29 #define DPAA2_EVENT_QUEUE_ATOMIC_FLOWS 2048 30 #define DPAA2_EVENT_QUEUE_ORDER_SEQUENCES 2048 31 32 enum { 33 DPAA2_EVENT_DPCI_PARALLEL_QUEUE, 34 DPAA2_EVENT_DPCI_ATOMIC_QUEUE, 35 DPAA2_EVENT_DPCI_MAX_QUEUES 36 }; 37 38 #define RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP \ 39 (RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | \ 40 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | \ 41 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID) 42 43 /**< Crypto Rx adapter cap to return If the packet transfers from 44 * the cryptodev to eventdev with DPAA2 devices. 45 */ 46 #define RTE_EVENT_CRYPTO_ADAPTER_DPAA2_CAP \ 47 (RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW | \ 48 RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND | \ 49 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA) 50 51 /**< Ethernet Rx adapter cap to return If the packet transfers from 52 * the ethdev to eventdev with DPAA2 devices. 53 */ 54 55 struct dpaa2_dpcon_dev { 56 TAILQ_ENTRY(dpaa2_dpcon_dev) next; 57 struct fsl_mc_io dpcon; 58 uint16_t token; 59 rte_atomic16_t in_use; 60 uint32_t dpcon_id; 61 uint16_t qbman_ch_id; 62 uint8_t num_priorities; 63 uint8_t channel_index; 64 }; 65 66 struct dpaa2_eventq { 67 /* DPcon device */ 68 struct dpaa2_dpcon_dev *dpcon; 69 /* Attached DPCI device */ 70 struct dpaa2_dpci_dev *dpci; 71 /* Mapped event port */ 72 struct dpaa2_io_portal_t *event_port; 73 /* Configuration provided by the user */ 74 uint32_t event_queue_cfg; 75 uint32_t event_queue_id; 76 }; 77 78 struct dpaa2_port { 79 struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES]; 80 uint8_t num_linked_evq; 81 uint8_t is_port_linked; 82 uint64_t timeout_us; 83 }; 84 85 struct dpaa2_eventdev { 86 struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES]; 87 uint32_t dequeue_timeout_ns; 88 uint8_t max_event_queues; 89 uint8_t nb_event_queues; 90 uint8_t nb_event_ports; 91 uint8_t resvd_1; 92 uint32_t nb_event_queue_flows; 93 uint32_t nb_event_port_dequeue_depth; 94 uint32_t nb_event_port_enqueue_depth; 95 uint32_t event_dev_cfg; 96 }; 97 98 struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void); 99 void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon); 100 101 #endif /* __DPAA2_EVENTDEV_H__ */ 102