1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 5 * Copyright 2016 NXP. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Freescale Semiconductor, Inc nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _RTE_DPAA2_SEC_PMD_PRIVATE_H_ 35 #define _RTE_DPAA2_SEC_PMD_PRIVATE_H_ 36 37 #define CRYPTODEV_NAME_DPAA2_SEC_PMD crypto_dpaa2_sec 38 /**< NXP DPAA2 - SEC PMD device name */ 39 40 #define MAX_QUEUES 64 41 #define MAX_DESC_SIZE 64 42 /** private data structure for each DPAA2_SEC device */ 43 struct dpaa2_sec_dev_private { 44 void *mc_portal; /**< MC Portal for configuring this device */ 45 void *hw; /**< Hardware handle for this device.Used by NADK framework */ 46 struct rte_mempool *fle_pool; /* per device memory pool for FLE */ 47 int32_t hw_id; /**< An unique ID of this device instance */ 48 int32_t vfio_fd; /**< File descriptor received via VFIO */ 49 uint16_t token; /**< Token required by DPxxx objects */ 50 unsigned int max_nb_queue_pairs; 51 /**< Max number of queue pairs supported by device */ 52 unsigned int max_nb_sessions; 53 /**< Max number of sessions supported by device */ 54 }; 55 56 struct dpaa2_sec_qp { 57 struct dpaa2_queue rx_vq; 58 struct dpaa2_queue tx_vq; 59 }; 60 61 enum shr_desc_type { 62 DESC_UPDATE, 63 DESC_FINAL, 64 DESC_INITFINAL, 65 }; 66 67 #define DIR_ENC 1 68 #define DIR_DEC 0 69 70 #define DPAA2_SET_FLC_EWS(flc) (flc->word1_bits23_16 |= 0x1) 71 #define DPAA2_SET_FLC_RSC(flc) (flc->word1_bits31_24 |= 0x1) 72 #define DPAA2_SET_FLC_REUSE_BS(flc) (flc->mode_bits |= 0x8000) 73 #define DPAA2_SET_FLC_REUSE_FF(flc) (flc->mode_bits |= 0x2000) 74 75 /* SEC Flow Context Descriptor */ 76 struct sec_flow_context { 77 /* word 0 */ 78 uint16_t word0_sdid; /* 11-0 SDID */ 79 uint16_t word0_res; /* 31-12 reserved */ 80 81 /* word 1 */ 82 uint8_t word1_sdl; /* 5-0 SDL */ 83 /* 7-6 reserved */ 84 85 uint8_t word1_bits_15_8; /* 11-8 CRID */ 86 /* 14-12 reserved */ 87 /* 15 CRJD */ 88 89 uint8_t word1_bits23_16; /* 16 EWS */ 90 /* 17 DAC */ 91 /* 18,19,20 ? */ 92 /* 23-21 reserved */ 93 94 uint8_t word1_bits31_24; /* 24 RSC */ 95 /* 25 RBMT */ 96 /* 31-26 reserved */ 97 98 /* word 2 RFLC[31-0] */ 99 uint32_t word2_rflc_31_0; 100 101 /* word 3 RFLC[63-32] */ 102 uint32_t word3_rflc_63_32; 103 104 /* word 4 */ 105 uint16_t word4_iicid; /* 15-0 IICID */ 106 uint16_t word4_oicid; /* 31-16 OICID */ 107 108 /* word 5 */ 109 uint32_t word5_ofqid:24; /* 23-0 OFQID */ 110 uint32_t word5_31_24:8; 111 /* 24 OSC */ 112 /* 25 OBMT */ 113 /* 29-26 reserved */ 114 /* 31-30 ICR */ 115 116 /* word 6 */ 117 uint32_t word6_oflc_31_0; 118 119 /* word 7 */ 120 uint32_t word7_oflc_63_32; 121 122 /* Word 8-15 storage profiles */ 123 uint16_t dl; /**< DataLength(correction) */ 124 uint16_t reserved; /**< reserved */ 125 uint16_t dhr; /**< DataHeadRoom(correction) */ 126 uint16_t mode_bits; /**< mode bits */ 127 uint16_t bpv0; /**< buffer pool0 valid */ 128 uint16_t bpid0; /**< Bypass Memory Translation */ 129 uint16_t bpv1; /**< buffer pool1 valid */ 130 uint16_t bpid1; /**< Bypass Memory Translation */ 131 uint64_t word_12_15[2]; /**< word 12-15 are reserved */ 132 }; 133 134 struct sec_flc_desc { 135 struct sec_flow_context flc; 136 uint32_t desc[MAX_DESC_SIZE]; 137 }; 138 139 struct ctxt_priv { 140 struct rte_mempool *fle_pool; /* per device memory pool for FLE */ 141 struct sec_flc_desc flc_desc[0]; 142 }; 143 144 enum dpaa2_sec_op_type { 145 DPAA2_SEC_NONE, /*!< No Cipher operations*/ 146 DPAA2_SEC_CIPHER,/*!< CIPHER operations */ 147 DPAA2_SEC_AUTH, /*!< Authentication Operations */ 148 DPAA2_SEC_AEAD, /*!< AEAD (AES-GCM/CCM) type operations */ 149 DPAA2_SEC_CIPHER_HASH, /*!< Authenticated Encryption with 150 * associated data 151 */ 152 DPAA2_SEC_HASH_CIPHER, /*!< Encryption with Authenticated 153 * associated data 154 */ 155 DPAA2_SEC_IPSEC, /*!< IPSEC protocol operations*/ 156 DPAA2_SEC_PDCP, /*!< PDCP protocol operations*/ 157 DPAA2_SEC_PKC, /*!< Public Key Cryptographic Operations */ 158 DPAA2_SEC_MAX 159 }; 160 161 struct dpaa2_sec_aead_ctxt { 162 uint16_t auth_only_len; /*!< Length of data for Auth only */ 163 uint8_t auth_cipher_text; /**< Authenticate/cipher ordering */ 164 }; 165 166 typedef struct dpaa2_sec_session_entry { 167 void *ctxt; 168 uint8_t ctxt_type; 169 uint8_t dir; /*!< Operation Direction */ 170 enum rte_crypto_cipher_algorithm cipher_alg; /*!< Cipher Algorithm*/ 171 enum rte_crypto_auth_algorithm auth_alg; /*!< Authentication Algorithm*/ 172 enum rte_crypto_aead_algorithm aead_alg; /*!< AEAD Algorithm*/ 173 union { 174 struct { 175 uint8_t *data; /**< pointer to key data */ 176 size_t length; /**< key length in bytes */ 177 } aead_key; 178 struct { 179 struct { 180 uint8_t *data; /**< pointer to key data */ 181 size_t length; /**< key length in bytes */ 182 } cipher_key; 183 struct { 184 uint8_t *data; /**< pointer to key data */ 185 size_t length; /**< key length in bytes */ 186 } auth_key; 187 }; 188 }; 189 struct { 190 uint16_t length; /**< IV length in bytes */ 191 uint16_t offset; /**< IV offset in bytes */ 192 } iv; 193 uint16_t digest_length; 194 uint8_t status; 195 union { 196 struct dpaa2_sec_aead_ctxt aead_ctxt; 197 } ext_params; 198 } dpaa2_sec_session; 199 200 static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = { 201 { /* MD5 HMAC */ 202 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 203 {.sym = { 204 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, 205 {.auth = { 206 .algo = RTE_CRYPTO_AUTH_MD5_HMAC, 207 .block_size = 64, 208 .key_size = { 209 .min = 1, 210 .max = 64, 211 .increment = 1 212 }, 213 .digest_size = { 214 .min = 1, 215 .max = 16, 216 .increment = 1 217 }, 218 .iv_size = { 0 } 219 }, } 220 }, } 221 }, 222 { /* SHA1 HMAC */ 223 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 224 {.sym = { 225 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, 226 {.auth = { 227 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC, 228 .block_size = 64, 229 .key_size = { 230 .min = 1, 231 .max = 64, 232 .increment = 1 233 }, 234 .digest_size = { 235 .min = 1, 236 .max = 20, 237 .increment = 1 238 }, 239 .iv_size = { 0 } 240 }, } 241 }, } 242 }, 243 { /* SHA224 HMAC */ 244 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 245 {.sym = { 246 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, 247 {.auth = { 248 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC, 249 .block_size = 64, 250 .key_size = { 251 .min = 1, 252 .max = 64, 253 .increment = 1 254 }, 255 .digest_size = { 256 .min = 1, 257 .max = 28, 258 .increment = 1 259 }, 260 .iv_size = { 0 } 261 }, } 262 }, } 263 }, 264 { /* SHA256 HMAC */ 265 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 266 {.sym = { 267 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, 268 {.auth = { 269 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC, 270 .block_size = 64, 271 .key_size = { 272 .min = 1, 273 .max = 64, 274 .increment = 1 275 }, 276 .digest_size = { 277 .min = 1, 278 .max = 32, 279 .increment = 1 280 }, 281 .iv_size = { 0 } 282 }, } 283 }, } 284 }, 285 { /* SHA384 HMAC */ 286 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 287 {.sym = { 288 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, 289 {.auth = { 290 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC, 291 .block_size = 128, 292 .key_size = { 293 .min = 1, 294 .max = 128, 295 .increment = 1 296 }, 297 .digest_size = { 298 .min = 1, 299 .max = 48, 300 .increment = 1 301 }, 302 .iv_size = { 0 } 303 }, } 304 }, } 305 }, 306 { /* SHA512 HMAC */ 307 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 308 {.sym = { 309 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, 310 {.auth = { 311 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC, 312 .block_size = 128, 313 .key_size = { 314 .min = 1, 315 .max = 128, 316 .increment = 1 317 }, 318 .digest_size = { 319 .min = 1, 320 .max = 64, 321 .increment = 1 322 }, 323 .iv_size = { 0 } 324 }, } 325 }, } 326 }, 327 { /* AES GCM */ 328 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 329 {.sym = { 330 .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD, 331 {.aead = { 332 .algo = RTE_CRYPTO_AEAD_AES_GCM, 333 .block_size = 16, 334 .key_size = { 335 .min = 16, 336 .max = 32, 337 .increment = 8 338 }, 339 .digest_size = { 340 .min = 8, 341 .max = 16, 342 .increment = 4 343 }, 344 .aad_size = { 345 .min = 0, 346 .max = 240, 347 .increment = 1 348 }, 349 .iv_size = { 350 .min = 12, 351 .max = 12, 352 .increment = 0 353 }, 354 }, } 355 }, } 356 }, 357 { /* AES CBC */ 358 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 359 {.sym = { 360 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, 361 {.cipher = { 362 .algo = RTE_CRYPTO_CIPHER_AES_CBC, 363 .block_size = 16, 364 .key_size = { 365 .min = 16, 366 .max = 32, 367 .increment = 8 368 }, 369 .iv_size = { 370 .min = 16, 371 .max = 16, 372 .increment = 0 373 } 374 }, } 375 }, } 376 }, 377 { /* AES CTR */ 378 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 379 {.sym = { 380 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, 381 {.cipher = { 382 .algo = RTE_CRYPTO_CIPHER_AES_CTR, 383 .block_size = 16, 384 .key_size = { 385 .min = 16, 386 .max = 32, 387 .increment = 8 388 }, 389 .iv_size = { 390 .min = 16, 391 .max = 16, 392 .increment = 0 393 }, 394 }, } 395 }, } 396 }, 397 { /* 3DES CBC */ 398 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, 399 {.sym = { 400 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, 401 {.cipher = { 402 .algo = RTE_CRYPTO_CIPHER_3DES_CBC, 403 .block_size = 8, 404 .key_size = { 405 .min = 16, 406 .max = 24, 407 .increment = 8 408 }, 409 .iv_size = { 410 .min = 8, 411 .max = 8, 412 .increment = 0 413 } 414 }, } 415 }, } 416 }, 417 418 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() 419 }; 420 421 static const struct rte_security_capability dpaa2_sec_security_cap[] = { 422 { /* IPsec Lookaside Protocol offload ESP Transport Egress */ 423 .action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL, 424 .protocol = RTE_SECURITY_PROTOCOL_IPSEC, 425 .ipsec = { 426 .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP, 427 .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL, 428 .direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS, 429 .options = { 0 } 430 }, 431 .crypto_capabilities = dpaa2_sec_capabilities 432 }, 433 { /* IPsec Lookaside Protocol offload ESP Tunnel Ingress */ 434 .action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL, 435 .protocol = RTE_SECURITY_PROTOCOL_IPSEC, 436 .ipsec = { 437 .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP, 438 .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL, 439 .direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS, 440 .options = { 0 } 441 }, 442 .crypto_capabilities = dpaa2_sec_capabilities 443 }, 444 { 445 .action = RTE_SECURITY_ACTION_TYPE_NONE 446 } 447 }; 448 449 /** 450 * Checksum 451 * 452 * @param buffer calculate chksum for buffer 453 * @param len buffer length 454 * 455 * @return checksum value in host cpu order 456 */ 457 static inline uint16_t 458 calc_chksum(void *buffer, int len) 459 { 460 uint16_t *buf = (uint16_t *)buffer; 461 uint32_t sum = 0; 462 uint16_t result; 463 464 for (sum = 0; len > 1; len -= 2) 465 sum += *buf++; 466 467 if (len == 1) 468 sum += *(unsigned char *)buf; 469 470 sum = (sum >> 16) + (sum & 0xFFFF); 471 sum += (sum >> 16); 472 result = ~sum; 473 474 return result; 475 } 476 477 #endif /* _RTE_DPAA2_SEC_PMD_PRIVATE_H_ */ 478