1d30ea906Sjfb8856606 /* SPDX-License-Identifier: BSD-3-Clause
2d30ea906Sjfb8856606  * Copyright(c) 2017 Cavium, Inc
32bfe3f2eSlogwang  */
42bfe3f2eSlogwang 
52bfe3f2eSlogwang #include <stdio.h>
62bfe3f2eSlogwang #include <unistd.h>
72bfe3f2eSlogwang 
82bfe3f2eSlogwang #include "test_order_common.h"
92bfe3f2eSlogwang 
10d30ea906Sjfb8856606 /* See http://doc.dpdk.org/guides/tools/testeventdev.html for test details */
112bfe3f2eSlogwang 
12*2d9fd380Sjfb8856606 static __rte_always_inline void
order_atq_process_stage_0(struct rte_event * const ev)132bfe3f2eSlogwang order_atq_process_stage_0(struct rte_event *const ev)
142bfe3f2eSlogwang {
152bfe3f2eSlogwang 	ev->sub_event_type = 1; /* move to stage 1 (atomic) on the same queue */
162bfe3f2eSlogwang 	ev->op = RTE_EVENT_OP_FORWARD;
172bfe3f2eSlogwang 	ev->sched_type = RTE_SCHED_TYPE_ATOMIC;
182bfe3f2eSlogwang 	ev->event_type = RTE_EVENT_TYPE_CPU;
192bfe3f2eSlogwang }
202bfe3f2eSlogwang 
212bfe3f2eSlogwang static int
order_atq_worker(void * arg,const bool flow_id_cap)22*2d9fd380Sjfb8856606 order_atq_worker(void *arg, const bool flow_id_cap)
232bfe3f2eSlogwang {
242bfe3f2eSlogwang 	ORDER_WORKER_INIT;
252bfe3f2eSlogwang 	struct rte_event ev;
262bfe3f2eSlogwang 
272bfe3f2eSlogwang 	while (t->err == false) {
282bfe3f2eSlogwang 		uint16_t event = rte_event_dequeue_burst(dev_id, port,
292bfe3f2eSlogwang 					&ev, 1, 0);
302bfe3f2eSlogwang 		if (!event) {
312bfe3f2eSlogwang 			if (rte_atomic64_read(outstand_pkts) <= 0)
322bfe3f2eSlogwang 				break;
332bfe3f2eSlogwang 			rte_pause();
342bfe3f2eSlogwang 			continue;
352bfe3f2eSlogwang 		}
362bfe3f2eSlogwang 
37*2d9fd380Sjfb8856606 		if (!flow_id_cap)
38*2d9fd380Sjfb8856606 			order_flow_id_copy_from_mbuf(t, &ev);
39*2d9fd380Sjfb8856606 
402bfe3f2eSlogwang 		if (ev.sub_event_type == 0) { /* stage 0 from producer */
412bfe3f2eSlogwang 			order_atq_process_stage_0(&ev);
422bfe3f2eSlogwang 			while (rte_event_enqueue_burst(dev_id, port, &ev, 1)
432bfe3f2eSlogwang 					!= 1)
442bfe3f2eSlogwang 				rte_pause();
452bfe3f2eSlogwang 		} else if (ev.sub_event_type == 1) { /* stage 1  */
462bfe3f2eSlogwang 			order_process_stage_1(t, &ev, nb_flows,
472bfe3f2eSlogwang 					expected_flow_seq, outstand_pkts);
482bfe3f2eSlogwang 		} else {
492bfe3f2eSlogwang 			order_process_stage_invalid(t, &ev);
502bfe3f2eSlogwang 		}
512bfe3f2eSlogwang 	}
522bfe3f2eSlogwang 	return 0;
532bfe3f2eSlogwang }
542bfe3f2eSlogwang 
552bfe3f2eSlogwang static int
order_atq_worker_burst(void * arg,const bool flow_id_cap)56*2d9fd380Sjfb8856606 order_atq_worker_burst(void *arg, const bool flow_id_cap)
572bfe3f2eSlogwang {
582bfe3f2eSlogwang 	ORDER_WORKER_INIT;
592bfe3f2eSlogwang 	struct rte_event ev[BURST_SIZE];
602bfe3f2eSlogwang 	uint16_t i;
612bfe3f2eSlogwang 
622bfe3f2eSlogwang 	while (t->err == false) {
632bfe3f2eSlogwang 		uint16_t const nb_rx = rte_event_dequeue_burst(dev_id, port, ev,
642bfe3f2eSlogwang 				BURST_SIZE, 0);
652bfe3f2eSlogwang 
662bfe3f2eSlogwang 		if (nb_rx == 0) {
672bfe3f2eSlogwang 			if (rte_atomic64_read(outstand_pkts) <= 0)
682bfe3f2eSlogwang 				break;
692bfe3f2eSlogwang 			rte_pause();
702bfe3f2eSlogwang 			continue;
712bfe3f2eSlogwang 		}
722bfe3f2eSlogwang 
732bfe3f2eSlogwang 		for (i = 0; i < nb_rx; i++) {
74*2d9fd380Sjfb8856606 			if (!flow_id_cap)
75*2d9fd380Sjfb8856606 				order_flow_id_copy_from_mbuf(t, &ev[i]);
76*2d9fd380Sjfb8856606 
772bfe3f2eSlogwang 			if (ev[i].sub_event_type == 0) { /*stage 0 */
782bfe3f2eSlogwang 				order_atq_process_stage_0(&ev[i]);
792bfe3f2eSlogwang 			} else if (ev[i].sub_event_type == 1) { /* stage 1 */
802bfe3f2eSlogwang 				order_process_stage_1(t, &ev[i], nb_flows,
812bfe3f2eSlogwang 					expected_flow_seq, outstand_pkts);
822bfe3f2eSlogwang 				ev[i].op = RTE_EVENT_OP_RELEASE;
832bfe3f2eSlogwang 			} else {
842bfe3f2eSlogwang 				order_process_stage_invalid(t, &ev[i]);
852bfe3f2eSlogwang 			}
862bfe3f2eSlogwang 		}
872bfe3f2eSlogwang 
882bfe3f2eSlogwang 		uint16_t enq;
892bfe3f2eSlogwang 
902bfe3f2eSlogwang 		enq = rte_event_enqueue_burst(dev_id, port, ev, nb_rx);
912bfe3f2eSlogwang 		while (enq < nb_rx) {
922bfe3f2eSlogwang 			enq += rte_event_enqueue_burst(dev_id, port,
932bfe3f2eSlogwang 							ev + enq, nb_rx - enq);
942bfe3f2eSlogwang 		}
952bfe3f2eSlogwang 	}
962bfe3f2eSlogwang 	return 0;
972bfe3f2eSlogwang }
982bfe3f2eSlogwang 
992bfe3f2eSlogwang static int
worker_wrapper(void * arg)1002bfe3f2eSlogwang worker_wrapper(void *arg)
1012bfe3f2eSlogwang {
1022bfe3f2eSlogwang 	struct worker_data *w  = arg;
1032bfe3f2eSlogwang 	const bool burst = evt_has_burst_mode(w->dev_id);
104*2d9fd380Sjfb8856606 	const bool flow_id_cap = evt_has_flow_id(w->dev_id);
1052bfe3f2eSlogwang 
106*2d9fd380Sjfb8856606 	if (burst) {
107*2d9fd380Sjfb8856606 		if (flow_id_cap)
108*2d9fd380Sjfb8856606 			return order_atq_worker_burst(arg, true);
1092bfe3f2eSlogwang 		else
110*2d9fd380Sjfb8856606 			return order_atq_worker_burst(arg, false);
111*2d9fd380Sjfb8856606 	} else {
112*2d9fd380Sjfb8856606 		if (flow_id_cap)
113*2d9fd380Sjfb8856606 			return order_atq_worker(arg, true);
114*2d9fd380Sjfb8856606 		else
115*2d9fd380Sjfb8856606 			return order_atq_worker(arg, false);
116*2d9fd380Sjfb8856606 	}
1172bfe3f2eSlogwang }
1182bfe3f2eSlogwang 
1192bfe3f2eSlogwang static int
order_atq_launch_lcores(struct evt_test * test,struct evt_options * opt)1202bfe3f2eSlogwang order_atq_launch_lcores(struct evt_test *test, struct evt_options *opt)
1212bfe3f2eSlogwang {
1222bfe3f2eSlogwang 	return order_launch_lcores(test, opt, worker_wrapper);
1232bfe3f2eSlogwang }
1242bfe3f2eSlogwang 
1252bfe3f2eSlogwang #define NB_QUEUES 1
1262bfe3f2eSlogwang static int
order_atq_eventdev_setup(struct evt_test * test,struct evt_options * opt)1272bfe3f2eSlogwang order_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)
1282bfe3f2eSlogwang {
1292bfe3f2eSlogwang 	int ret;
1302bfe3f2eSlogwang 
1312bfe3f2eSlogwang 	const uint8_t nb_workers = evt_nr_active_lcores(opt->wlcores);
1322bfe3f2eSlogwang 	/* number of active worker cores + 1 producer */
1332bfe3f2eSlogwang 	const uint8_t nb_ports = nb_workers + 1;
1342bfe3f2eSlogwang 
1354418919fSjohnjiang 	ret = evt_configure_eventdev(opt, NB_QUEUES, nb_ports);
1362bfe3f2eSlogwang 	if (ret) {
1372bfe3f2eSlogwang 		evt_err("failed to configure eventdev %d", opt->dev_id);
1382bfe3f2eSlogwang 		return ret;
1392bfe3f2eSlogwang 	}
1402bfe3f2eSlogwang 
1412bfe3f2eSlogwang 	/* q0 all types queue configuration */
1422bfe3f2eSlogwang 	struct rte_event_queue_conf q0_conf = {
1432bfe3f2eSlogwang 			.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
1442bfe3f2eSlogwang 			.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES,
1452bfe3f2eSlogwang 			.nb_atomic_flows = opt->nb_flows,
1462bfe3f2eSlogwang 			.nb_atomic_order_sequences = opt->nb_flows,
1472bfe3f2eSlogwang 	};
1482bfe3f2eSlogwang 	ret = rte_event_queue_setup(opt->dev_id, 0, &q0_conf);
1492bfe3f2eSlogwang 	if (ret) {
1502bfe3f2eSlogwang 		evt_err("failed to setup queue0 eventdev %d", opt->dev_id);
1512bfe3f2eSlogwang 		return ret;
1522bfe3f2eSlogwang 	}
1532bfe3f2eSlogwang 
1542bfe3f2eSlogwang 	/* setup one port per worker, linking to all queues */
1552bfe3f2eSlogwang 	ret = order_event_dev_port_setup(test, opt, nb_workers, NB_QUEUES);
1562bfe3f2eSlogwang 	if (ret)
1572bfe3f2eSlogwang 		return ret;
1582bfe3f2eSlogwang 
159d30ea906Sjfb8856606 	if (!evt_has_distributed_sched(opt->dev_id)) {
160d30ea906Sjfb8856606 		uint32_t service_id;
161d30ea906Sjfb8856606 		rte_event_dev_service_id_get(opt->dev_id, &service_id);
162d30ea906Sjfb8856606 		ret = evt_service_setup(service_id);
1632bfe3f2eSlogwang 		if (ret) {
1642bfe3f2eSlogwang 			evt_err("No service lcore found to run event dev.");
1652bfe3f2eSlogwang 			return ret;
1662bfe3f2eSlogwang 		}
167d30ea906Sjfb8856606 	}
1682bfe3f2eSlogwang 
1692bfe3f2eSlogwang 	ret = rte_event_dev_start(opt->dev_id);
1702bfe3f2eSlogwang 	if (ret) {
1712bfe3f2eSlogwang 		evt_err("failed to start eventdev %d", opt->dev_id);
1722bfe3f2eSlogwang 		return ret;
1732bfe3f2eSlogwang 	}
1742bfe3f2eSlogwang 
1752bfe3f2eSlogwang 	return 0;
1762bfe3f2eSlogwang }
1772bfe3f2eSlogwang 
1782bfe3f2eSlogwang static void
order_atq_opt_dump(struct evt_options * opt)1792bfe3f2eSlogwang order_atq_opt_dump(struct evt_options *opt)
1802bfe3f2eSlogwang {
1812bfe3f2eSlogwang 	order_opt_dump(opt);
1822bfe3f2eSlogwang 	evt_dump("nb_evdev_queues", "%d", NB_QUEUES);
1832bfe3f2eSlogwang }
1842bfe3f2eSlogwang 
1852bfe3f2eSlogwang static bool
order_atq_capability_check(struct evt_options * opt)1862bfe3f2eSlogwang order_atq_capability_check(struct evt_options *opt)
1872bfe3f2eSlogwang {
1882bfe3f2eSlogwang 	struct rte_event_dev_info dev_info;
1892bfe3f2eSlogwang 
1902bfe3f2eSlogwang 	rte_event_dev_info_get(opt->dev_id, &dev_info);
1912bfe3f2eSlogwang 	if (dev_info.max_event_queues < NB_QUEUES || dev_info.max_event_ports <
1922bfe3f2eSlogwang 			order_nb_event_ports(opt)) {
1932bfe3f2eSlogwang 		evt_err("not enough eventdev queues=%d/%d or ports=%d/%d",
1942bfe3f2eSlogwang 			NB_QUEUES, dev_info.max_event_queues,
1952bfe3f2eSlogwang 			order_nb_event_ports(opt), dev_info.max_event_ports);
1962bfe3f2eSlogwang 		return false;
1972bfe3f2eSlogwang 	}
1982bfe3f2eSlogwang 
1992bfe3f2eSlogwang 	if (!evt_has_all_types_queue(opt->dev_id))
2002bfe3f2eSlogwang 		return false;
2012bfe3f2eSlogwang 
2022bfe3f2eSlogwang 	return true;
2032bfe3f2eSlogwang }
2042bfe3f2eSlogwang 
2052bfe3f2eSlogwang static const struct evt_test_ops order_atq =  {
2062bfe3f2eSlogwang 	.cap_check          = order_atq_capability_check,
2072bfe3f2eSlogwang 	.opt_check          = order_opt_check,
2082bfe3f2eSlogwang 	.opt_dump           = order_atq_opt_dump,
2092bfe3f2eSlogwang 	.test_setup         = order_test_setup,
2102bfe3f2eSlogwang 	.mempool_setup      = order_mempool_setup,
2112bfe3f2eSlogwang 	.eventdev_setup     = order_atq_eventdev_setup,
2122bfe3f2eSlogwang 	.launch_lcores      = order_atq_launch_lcores,
2132bfe3f2eSlogwang 	.eventdev_destroy   = order_eventdev_destroy,
2142bfe3f2eSlogwang 	.mempool_destroy    = order_mempool_destroy,
2152bfe3f2eSlogwang 	.test_result        = order_test_result,
2162bfe3f2eSlogwang 	.test_destroy       = order_test_destroy,
2172bfe3f2eSlogwang };
2182bfe3f2eSlogwang 
2192bfe3f2eSlogwang EVT_TEST_REGISTER(order_atq);
220