1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <ctype.h> 6 #include <errno.h> 7 #include <inttypes.h> 8 #include <stdbool.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <string.h> 12 #include <sys/queue.h> 13 14 #include <rte_byteorder.h> 15 #include <rte_log.h> 16 #include <rte_debug.h> 17 #include <rte_interrupts.h> 18 #include <rte_memory.h> 19 #include <rte_memcpy.h> 20 #include <rte_memzone.h> 21 #include <rte_launch.h> 22 #include <rte_eal.h> 23 #include <rte_per_lcore.h> 24 #include <rte_lcore.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_common.h> 27 #include <rte_mempool.h> 28 #include <rte_malloc.h> 29 #include <rte_mbuf.h> 30 #include <rte_errno.h> 31 #include <rte_spinlock.h> 32 #include <rte_string_fns.h> 33 #include <rte_kvargs.h> 34 #include <rte_class.h> 35 #include <rte_ether.h> 36 #include <rte_telemetry.h> 37 38 #include "rte_ethdev_trace.h" 39 #include "rte_ethdev.h" 40 #include "ethdev_driver.h" 41 #include "ethdev_profile.h" 42 #include "ethdev_private.h" 43 44 static const char *MZ_RTE_ETH_DEV_DATA = "rte_eth_dev_data"; 45 struct rte_eth_dev rte_eth_devices[RTE_MAX_ETHPORTS]; 46 47 /* spinlock for eth device callbacks */ 48 static rte_spinlock_t eth_dev_cb_lock = RTE_SPINLOCK_INITIALIZER; 49 50 /* spinlock for add/remove rx callbacks */ 51 static rte_spinlock_t eth_dev_rx_cb_lock = RTE_SPINLOCK_INITIALIZER; 52 53 /* spinlock for add/remove tx callbacks */ 54 static rte_spinlock_t eth_dev_tx_cb_lock = RTE_SPINLOCK_INITIALIZER; 55 56 /* spinlock for shared data allocation */ 57 static rte_spinlock_t eth_dev_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 58 59 /* store statistics names and its offset in stats structure */ 60 struct rte_eth_xstats_name_off { 61 char name[RTE_ETH_XSTATS_NAME_SIZE]; 62 unsigned offset; 63 }; 64 65 /* Shared memory between primary and secondary processes. */ 66 static struct { 67 uint64_t next_owner_id; 68 rte_spinlock_t ownership_lock; 69 struct rte_eth_dev_data data[RTE_MAX_ETHPORTS]; 70 } *eth_dev_shared_data; 71 72 static const struct rte_eth_xstats_name_off eth_dev_stats_strings[] = { 73 {"rx_good_packets", offsetof(struct rte_eth_stats, ipackets)}, 74 {"tx_good_packets", offsetof(struct rte_eth_stats, opackets)}, 75 {"rx_good_bytes", offsetof(struct rte_eth_stats, ibytes)}, 76 {"tx_good_bytes", offsetof(struct rte_eth_stats, obytes)}, 77 {"rx_missed_errors", offsetof(struct rte_eth_stats, imissed)}, 78 {"rx_errors", offsetof(struct rte_eth_stats, ierrors)}, 79 {"tx_errors", offsetof(struct rte_eth_stats, oerrors)}, 80 {"rx_mbuf_allocation_errors", offsetof(struct rte_eth_stats, 81 rx_nombuf)}, 82 }; 83 84 #define RTE_NB_STATS RTE_DIM(eth_dev_stats_strings) 85 86 static const struct rte_eth_xstats_name_off eth_dev_rxq_stats_strings[] = { 87 {"packets", offsetof(struct rte_eth_stats, q_ipackets)}, 88 {"bytes", offsetof(struct rte_eth_stats, q_ibytes)}, 89 {"errors", offsetof(struct rte_eth_stats, q_errors)}, 90 }; 91 92 #define RTE_NB_RXQ_STATS RTE_DIM(eth_dev_rxq_stats_strings) 93 94 static const struct rte_eth_xstats_name_off eth_dev_txq_stats_strings[] = { 95 {"packets", offsetof(struct rte_eth_stats, q_opackets)}, 96 {"bytes", offsetof(struct rte_eth_stats, q_obytes)}, 97 }; 98 #define RTE_NB_TXQ_STATS RTE_DIM(eth_dev_txq_stats_strings) 99 100 #define RTE_RX_OFFLOAD_BIT2STR(_name) \ 101 { DEV_RX_OFFLOAD_##_name, #_name } 102 103 #define RTE_ETH_RX_OFFLOAD_BIT2STR(_name) \ 104 { RTE_ETH_RX_OFFLOAD_##_name, #_name } 105 106 static const struct { 107 uint64_t offload; 108 const char *name; 109 } eth_dev_rx_offload_names[] = { 110 RTE_RX_OFFLOAD_BIT2STR(VLAN_STRIP), 111 RTE_RX_OFFLOAD_BIT2STR(IPV4_CKSUM), 112 RTE_RX_OFFLOAD_BIT2STR(UDP_CKSUM), 113 RTE_RX_OFFLOAD_BIT2STR(TCP_CKSUM), 114 RTE_RX_OFFLOAD_BIT2STR(TCP_LRO), 115 RTE_RX_OFFLOAD_BIT2STR(QINQ_STRIP), 116 RTE_RX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM), 117 RTE_RX_OFFLOAD_BIT2STR(MACSEC_STRIP), 118 RTE_RX_OFFLOAD_BIT2STR(HEADER_SPLIT), 119 RTE_RX_OFFLOAD_BIT2STR(VLAN_FILTER), 120 RTE_RX_OFFLOAD_BIT2STR(VLAN_EXTEND), 121 RTE_RX_OFFLOAD_BIT2STR(JUMBO_FRAME), 122 RTE_RX_OFFLOAD_BIT2STR(SCATTER), 123 RTE_RX_OFFLOAD_BIT2STR(TIMESTAMP), 124 RTE_RX_OFFLOAD_BIT2STR(SECURITY), 125 RTE_RX_OFFLOAD_BIT2STR(KEEP_CRC), 126 RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM), 127 RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM), 128 RTE_RX_OFFLOAD_BIT2STR(RSS_HASH), 129 RTE_ETH_RX_OFFLOAD_BIT2STR(BUFFER_SPLIT), 130 }; 131 132 #undef RTE_RX_OFFLOAD_BIT2STR 133 #undef RTE_ETH_RX_OFFLOAD_BIT2STR 134 135 #define RTE_TX_OFFLOAD_BIT2STR(_name) \ 136 { DEV_TX_OFFLOAD_##_name, #_name } 137 138 static const struct { 139 uint64_t offload; 140 const char *name; 141 } eth_dev_tx_offload_names[] = { 142 RTE_TX_OFFLOAD_BIT2STR(VLAN_INSERT), 143 RTE_TX_OFFLOAD_BIT2STR(IPV4_CKSUM), 144 RTE_TX_OFFLOAD_BIT2STR(UDP_CKSUM), 145 RTE_TX_OFFLOAD_BIT2STR(TCP_CKSUM), 146 RTE_TX_OFFLOAD_BIT2STR(SCTP_CKSUM), 147 RTE_TX_OFFLOAD_BIT2STR(TCP_TSO), 148 RTE_TX_OFFLOAD_BIT2STR(UDP_TSO), 149 RTE_TX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM), 150 RTE_TX_OFFLOAD_BIT2STR(QINQ_INSERT), 151 RTE_TX_OFFLOAD_BIT2STR(VXLAN_TNL_TSO), 152 RTE_TX_OFFLOAD_BIT2STR(GRE_TNL_TSO), 153 RTE_TX_OFFLOAD_BIT2STR(IPIP_TNL_TSO), 154 RTE_TX_OFFLOAD_BIT2STR(GENEVE_TNL_TSO), 155 RTE_TX_OFFLOAD_BIT2STR(MACSEC_INSERT), 156 RTE_TX_OFFLOAD_BIT2STR(MT_LOCKFREE), 157 RTE_TX_OFFLOAD_BIT2STR(MULTI_SEGS), 158 RTE_TX_OFFLOAD_BIT2STR(MBUF_FAST_FREE), 159 RTE_TX_OFFLOAD_BIT2STR(SECURITY), 160 RTE_TX_OFFLOAD_BIT2STR(UDP_TNL_TSO), 161 RTE_TX_OFFLOAD_BIT2STR(IP_TNL_TSO), 162 RTE_TX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM), 163 RTE_TX_OFFLOAD_BIT2STR(SEND_ON_TIMESTAMP), 164 }; 165 166 #undef RTE_TX_OFFLOAD_BIT2STR 167 168 /** 169 * The user application callback description. 170 * 171 * It contains callback address to be registered by user application, 172 * the pointer to the parameters for callback, and the event type. 173 */ 174 struct rte_eth_dev_callback { 175 TAILQ_ENTRY(rte_eth_dev_callback) next; /**< Callbacks list */ 176 rte_eth_dev_cb_fn cb_fn; /**< Callback address */ 177 void *cb_arg; /**< Parameter for callback */ 178 void *ret_param; /**< Return parameter */ 179 enum rte_eth_event_type event; /**< Interrupt event type */ 180 uint32_t active; /**< Callback is executing */ 181 }; 182 183 enum { 184 STAT_QMAP_TX = 0, 185 STAT_QMAP_RX 186 }; 187 188 int 189 rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs_str) 190 { 191 int ret; 192 struct rte_devargs devargs; 193 const char *bus_param_key; 194 char *bus_str = NULL; 195 char *cls_str = NULL; 196 int str_size; 197 198 if (iter == NULL) { 199 RTE_ETHDEV_LOG(ERR, "Cannot initialize NULL iterator\n"); 200 return -EINVAL; 201 } 202 203 if (devargs_str == NULL) { 204 RTE_ETHDEV_LOG(ERR, 205 "Cannot initialize iterator from NULL device description string\n"); 206 return -EINVAL; 207 } 208 209 memset(iter, 0, sizeof(*iter)); 210 memset(&devargs, 0, sizeof(devargs)); 211 212 /* 213 * The devargs string may use various syntaxes: 214 * - 0000:08:00.0,representor=[1-3] 215 * - pci:0000:06:00.0,representor=[0,5] 216 * - class=eth,mac=00:11:22:33:44:55 217 * - bus=X,paramX=x/class=Y,paramY=y/driver=Z,paramZ=z 218 */ 219 220 /* 221 * Handle pure class filter (i.e. without any bus-level argument), 222 * from future new syntax. 223 * rte_devargs_parse() is not yet supporting the new syntax, 224 * that's why this simple case is temporarily parsed here. 225 */ 226 #define iter_anybus_str "class=eth," 227 if (strncmp(devargs_str, iter_anybus_str, 228 strlen(iter_anybus_str)) == 0) { 229 iter->cls_str = devargs_str + strlen(iter_anybus_str); 230 goto end; 231 } 232 233 /* Split bus, device and parameters. */ 234 ret = rte_devargs_parse(&devargs, devargs_str); 235 if (ret != 0) 236 goto error; 237 238 /* 239 * Assume parameters of old syntax can match only at ethdev level. 240 * Extra parameters will be ignored, thanks to "+" prefix. 241 */ 242 str_size = strlen(devargs.args) + 2; 243 cls_str = malloc(str_size); 244 if (cls_str == NULL) { 245 ret = -ENOMEM; 246 goto error; 247 } 248 ret = snprintf(cls_str, str_size, "+%s", devargs.args); 249 if (ret != str_size - 1) { 250 ret = -EINVAL; 251 goto error; 252 } 253 iter->cls_str = cls_str; 254 255 iter->bus = devargs.bus; 256 if (iter->bus->dev_iterate == NULL) { 257 ret = -ENOTSUP; 258 goto error; 259 } 260 261 /* Convert bus args to new syntax for use with new API dev_iterate. */ 262 if ((strcmp(iter->bus->name, "vdev") == 0) || 263 (strcmp(iter->bus->name, "fslmc") == 0) || 264 (strcmp(iter->bus->name, "dpaa_bus") == 0)) { 265 bus_param_key = "name"; 266 } else if (strcmp(iter->bus->name, "pci") == 0) { 267 bus_param_key = "addr"; 268 } else { 269 ret = -ENOTSUP; 270 goto error; 271 } 272 str_size = strlen(bus_param_key) + strlen(devargs.name) + 2; 273 bus_str = malloc(str_size); 274 if (bus_str == NULL) { 275 ret = -ENOMEM; 276 goto error; 277 } 278 ret = snprintf(bus_str, str_size, "%s=%s", 279 bus_param_key, devargs.name); 280 if (ret != str_size - 1) { 281 ret = -EINVAL; 282 goto error; 283 } 284 iter->bus_str = bus_str; 285 286 end: 287 iter->cls = rte_class_find_by_name("eth"); 288 rte_devargs_reset(&devargs); 289 return 0; 290 291 error: 292 if (ret == -ENOTSUP) 293 RTE_ETHDEV_LOG(ERR, "Bus %s does not support iterating.\n", 294 iter->bus->name); 295 rte_devargs_reset(&devargs); 296 free(bus_str); 297 free(cls_str); 298 return ret; 299 } 300 301 uint16_t 302 rte_eth_iterator_next(struct rte_dev_iterator *iter) 303 { 304 if (iter == NULL) { 305 RTE_ETHDEV_LOG(ERR, 306 "Cannot get next device from NULL iterator\n"); 307 return RTE_MAX_ETHPORTS; 308 } 309 310 if (iter->cls == NULL) /* invalid ethdev iterator */ 311 return RTE_MAX_ETHPORTS; 312 313 do { /* loop to try all matching rte_device */ 314 /* If not pure ethdev filter and */ 315 if (iter->bus != NULL && 316 /* not in middle of rte_eth_dev iteration, */ 317 iter->class_device == NULL) { 318 /* get next rte_device to try. */ 319 iter->device = iter->bus->dev_iterate( 320 iter->device, iter->bus_str, iter); 321 if (iter->device == NULL) 322 break; /* no more rte_device candidate */ 323 } 324 /* A device is matching bus part, need to check ethdev part. */ 325 iter->class_device = iter->cls->dev_iterate( 326 iter->class_device, iter->cls_str, iter); 327 if (iter->class_device != NULL) 328 return eth_dev_to_id(iter->class_device); /* match */ 329 } while (iter->bus != NULL); /* need to try next rte_device */ 330 331 /* No more ethdev port to iterate. */ 332 rte_eth_iterator_cleanup(iter); 333 return RTE_MAX_ETHPORTS; 334 } 335 336 void 337 rte_eth_iterator_cleanup(struct rte_dev_iterator *iter) 338 { 339 if (iter == NULL) { 340 RTE_ETHDEV_LOG(ERR, "Cannot do clean up from NULL iterator\n"); 341 return; 342 } 343 344 if (iter->bus_str == NULL) 345 return; /* nothing to free in pure class filter */ 346 free(RTE_CAST_FIELD(iter, bus_str, char *)); /* workaround const */ 347 free(RTE_CAST_FIELD(iter, cls_str, char *)); /* workaround const */ 348 memset(iter, 0, sizeof(*iter)); 349 } 350 351 uint16_t 352 rte_eth_find_next(uint16_t port_id) 353 { 354 while (port_id < RTE_MAX_ETHPORTS && 355 rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED) 356 port_id++; 357 358 if (port_id >= RTE_MAX_ETHPORTS) 359 return RTE_MAX_ETHPORTS; 360 361 return port_id; 362 } 363 364 /* 365 * Macro to iterate over all valid ports for internal usage. 366 * Note: RTE_ETH_FOREACH_DEV is different because filtering owned ports. 367 */ 368 #define RTE_ETH_FOREACH_VALID_DEV(port_id) \ 369 for (port_id = rte_eth_find_next(0); \ 370 port_id < RTE_MAX_ETHPORTS; \ 371 port_id = rte_eth_find_next(port_id + 1)) 372 373 uint16_t 374 rte_eth_find_next_of(uint16_t port_id, const struct rte_device *parent) 375 { 376 port_id = rte_eth_find_next(port_id); 377 while (port_id < RTE_MAX_ETHPORTS && 378 rte_eth_devices[port_id].device != parent) 379 port_id = rte_eth_find_next(port_id + 1); 380 381 return port_id; 382 } 383 384 uint16_t 385 rte_eth_find_next_sibling(uint16_t port_id, uint16_t ref_port_id) 386 { 387 RTE_ETH_VALID_PORTID_OR_ERR_RET(ref_port_id, RTE_MAX_ETHPORTS); 388 return rte_eth_find_next_of(port_id, 389 rte_eth_devices[ref_port_id].device); 390 } 391 392 static void 393 eth_dev_shared_data_prepare(void) 394 { 395 const unsigned flags = 0; 396 const struct rte_memzone *mz; 397 398 rte_spinlock_lock(ð_dev_shared_data_lock); 399 400 if (eth_dev_shared_data == NULL) { 401 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 402 /* Allocate port data and ownership shared memory. */ 403 mz = rte_memzone_reserve(MZ_RTE_ETH_DEV_DATA, 404 sizeof(*eth_dev_shared_data), 405 rte_socket_id(), flags); 406 } else 407 mz = rte_memzone_lookup(MZ_RTE_ETH_DEV_DATA); 408 if (mz == NULL) 409 rte_panic("Cannot allocate ethdev shared data\n"); 410 411 eth_dev_shared_data = mz->addr; 412 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 413 eth_dev_shared_data->next_owner_id = 414 RTE_ETH_DEV_NO_OWNER + 1; 415 rte_spinlock_init(ð_dev_shared_data->ownership_lock); 416 memset(eth_dev_shared_data->data, 0, 417 sizeof(eth_dev_shared_data->data)); 418 } 419 } 420 421 rte_spinlock_unlock(ð_dev_shared_data_lock); 422 } 423 424 static bool 425 eth_dev_is_allocated(const struct rte_eth_dev *ethdev) 426 { 427 return ethdev->data->name[0] != '\0'; 428 } 429 430 static struct rte_eth_dev * 431 eth_dev_allocated(const char *name) 432 { 433 uint16_t i; 434 435 RTE_BUILD_BUG_ON(RTE_MAX_ETHPORTS >= UINT16_MAX); 436 437 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 438 if (rte_eth_devices[i].data != NULL && 439 strcmp(rte_eth_devices[i].data->name, name) == 0) 440 return &rte_eth_devices[i]; 441 } 442 return NULL; 443 } 444 445 struct rte_eth_dev * 446 rte_eth_dev_allocated(const char *name) 447 { 448 struct rte_eth_dev *ethdev; 449 450 eth_dev_shared_data_prepare(); 451 452 rte_spinlock_lock(ð_dev_shared_data->ownership_lock); 453 454 ethdev = eth_dev_allocated(name); 455 456 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock); 457 458 return ethdev; 459 } 460 461 static uint16_t 462 eth_dev_find_free_port(void) 463 { 464 uint16_t i; 465 466 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 467 /* Using shared name field to find a free port. */ 468 if (eth_dev_shared_data->data[i].name[0] == '\0') { 469 RTE_ASSERT(rte_eth_devices[i].state == 470 RTE_ETH_DEV_UNUSED); 471 return i; 472 } 473 } 474 return RTE_MAX_ETHPORTS; 475 } 476 477 static struct rte_eth_dev * 478 eth_dev_get(uint16_t port_id) 479 { 480 struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id]; 481 482 eth_dev->data = ð_dev_shared_data->data[port_id]; 483 484 return eth_dev; 485 } 486 487 struct rte_eth_dev * 488 rte_eth_dev_allocate(const char *name) 489 { 490 uint16_t port_id; 491 struct rte_eth_dev *eth_dev = NULL; 492 size_t name_len; 493 494 name_len = strnlen(name, RTE_ETH_NAME_MAX_LEN); 495 if (name_len == 0) { 496 RTE_ETHDEV_LOG(ERR, "Zero length Ethernet device name\n"); 497 return NULL; 498 } 499 500 if (name_len >= RTE_ETH_NAME_MAX_LEN) { 501 RTE_ETHDEV_LOG(ERR, "Ethernet device name is too long\n"); 502 return NULL; 503 } 504 505 eth_dev_shared_data_prepare(); 506 507 /* Synchronize port creation between primary and secondary threads. */ 508 rte_spinlock_lock(ð_dev_shared_data->ownership_lock); 509 510 if (eth_dev_allocated(name) != NULL) { 511 RTE_ETHDEV_LOG(ERR, 512 "Ethernet device with name %s already allocated\n", 513 name); 514 goto unlock; 515 } 516 517 port_id = eth_dev_find_free_port(); 518 if (port_id == RTE_MAX_ETHPORTS) { 519 RTE_ETHDEV_LOG(ERR, 520 "Reached maximum number of Ethernet ports\n"); 521 goto unlock; 522 } 523 524 eth_dev = eth_dev_get(port_id); 525 strlcpy(eth_dev->data->name, name, sizeof(eth_dev->data->name)); 526 eth_dev->data->port_id = port_id; 527 eth_dev->data->mtu = RTE_ETHER_MTU; 528 pthread_mutex_init(ð_dev->data->flow_ops_mutex, NULL); 529 530 unlock: 531 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock); 532 533 return eth_dev; 534 } 535 536 /* 537 * Attach to a port already registered by the primary process, which 538 * makes sure that the same device would have the same port id both 539 * in the primary and secondary process. 540 */ 541 struct rte_eth_dev * 542 rte_eth_dev_attach_secondary(const char *name) 543 { 544 uint16_t i; 545 struct rte_eth_dev *eth_dev = NULL; 546 547 eth_dev_shared_data_prepare(); 548 549 /* Synchronize port attachment to primary port creation and release. */ 550 rte_spinlock_lock(ð_dev_shared_data->ownership_lock); 551 552 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 553 if (strcmp(eth_dev_shared_data->data[i].name, name) == 0) 554 break; 555 } 556 if (i == RTE_MAX_ETHPORTS) { 557 RTE_ETHDEV_LOG(ERR, 558 "Device %s is not driven by the primary process\n", 559 name); 560 } else { 561 eth_dev = eth_dev_get(i); 562 RTE_ASSERT(eth_dev->data->port_id == i); 563 } 564 565 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock); 566 return eth_dev; 567 } 568 569 int 570 rte_eth_dev_release_port(struct rte_eth_dev *eth_dev) 571 { 572 if (eth_dev == NULL) 573 return -EINVAL; 574 575 eth_dev_shared_data_prepare(); 576 577 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 578 rte_eth_dev_callback_process(eth_dev, 579 RTE_ETH_EVENT_DESTROY, NULL); 580 581 rte_spinlock_lock(ð_dev_shared_data->ownership_lock); 582 583 eth_dev->state = RTE_ETH_DEV_UNUSED; 584 eth_dev->device = NULL; 585 eth_dev->process_private = NULL; 586 eth_dev->intr_handle = NULL; 587 eth_dev->rx_pkt_burst = NULL; 588 eth_dev->tx_pkt_burst = NULL; 589 eth_dev->tx_pkt_prepare = NULL; 590 eth_dev->rx_queue_count = NULL; 591 eth_dev->rx_descriptor_status = NULL; 592 eth_dev->tx_descriptor_status = NULL; 593 eth_dev->dev_ops = NULL; 594 595 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 596 rte_free(eth_dev->data->rx_queues); 597 rte_free(eth_dev->data->tx_queues); 598 rte_free(eth_dev->data->mac_addrs); 599 rte_free(eth_dev->data->hash_mac_addrs); 600 rte_free(eth_dev->data->dev_private); 601 pthread_mutex_destroy(ð_dev->data->flow_ops_mutex); 602 memset(eth_dev->data, 0, sizeof(struct rte_eth_dev_data)); 603 } 604 605 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock); 606 607 return 0; 608 } 609 610 int 611 rte_eth_dev_is_valid_port(uint16_t port_id) 612 { 613 if (port_id >= RTE_MAX_ETHPORTS || 614 (rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED)) 615 return 0; 616 else 617 return 1; 618 } 619 620 static int 621 eth_is_valid_owner_id(uint64_t owner_id) 622 { 623 if (owner_id == RTE_ETH_DEV_NO_OWNER || 624 eth_dev_shared_data->next_owner_id <= owner_id) 625 return 0; 626 return 1; 627 } 628 629 uint64_t 630 rte_eth_find_next_owned_by(uint16_t port_id, const uint64_t owner_id) 631 { 632 port_id = rte_eth_find_next(port_id); 633 while (port_id < RTE_MAX_ETHPORTS && 634 rte_eth_devices[port_id].data->owner.id != owner_id) 635 port_id = rte_eth_find_next(port_id + 1); 636 637 return port_id; 638 } 639 640 int 641 rte_eth_dev_owner_new(uint64_t *owner_id) 642 { 643 if (owner_id == NULL) { 644 RTE_ETHDEV_LOG(ERR, "Cannot get new owner ID to NULL\n"); 645 return -EINVAL; 646 } 647 648 eth_dev_shared_data_prepare(); 649 650 rte_spinlock_lock(ð_dev_shared_data->ownership_lock); 651 652 *owner_id = eth_dev_shared_data->next_owner_id++; 653 654 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock); 655 return 0; 656 } 657 658 static int 659 eth_dev_owner_set(const uint16_t port_id, const uint64_t old_owner_id, 660 const struct rte_eth_dev_owner *new_owner) 661 { 662 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id]; 663 struct rte_eth_dev_owner *port_owner; 664 665 if (port_id >= RTE_MAX_ETHPORTS || !eth_dev_is_allocated(ethdev)) { 666 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n", 667 port_id); 668 return -ENODEV; 669 } 670 671 if (new_owner == NULL) { 672 RTE_ETHDEV_LOG(ERR, 673 "Cannot set ethdev port %u owner from NULL owner\n", 674 port_id); 675 return -EINVAL; 676 } 677 678 if (!eth_is_valid_owner_id(new_owner->id) && 679 !eth_is_valid_owner_id(old_owner_id)) { 680 RTE_ETHDEV_LOG(ERR, 681 "Invalid owner old_id=%016"PRIx64" new_id=%016"PRIx64"\n", 682 old_owner_id, new_owner->id); 683 return -EINVAL; 684 } 685 686 port_owner = &rte_eth_devices[port_id].data->owner; 687 if (port_owner->id != old_owner_id) { 688 RTE_ETHDEV_LOG(ERR, 689 "Cannot set owner to port %u already owned by %s_%016"PRIX64"\n", 690 port_id, port_owner->name, port_owner->id); 691 return -EPERM; 692 } 693 694 /* can not truncate (same structure) */ 695 strlcpy(port_owner->name, new_owner->name, RTE_ETH_MAX_OWNER_NAME_LEN); 696 697 port_owner->id = new_owner->id; 698 699 RTE_ETHDEV_LOG(DEBUG, "Port %u owner is %s_%016"PRIx64"\n", 700 port_id, new_owner->name, new_owner->id); 701 702 return 0; 703 } 704 705 int 706 rte_eth_dev_owner_set(const uint16_t port_id, 707 const struct rte_eth_dev_owner *owner) 708 { 709 int ret; 710 711 eth_dev_shared_data_prepare(); 712 713 rte_spinlock_lock(ð_dev_shared_data->ownership_lock); 714 715 ret = eth_dev_owner_set(port_id, RTE_ETH_DEV_NO_OWNER, owner); 716 717 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock); 718 return ret; 719 } 720 721 int 722 rte_eth_dev_owner_unset(const uint16_t port_id, const uint64_t owner_id) 723 { 724 const struct rte_eth_dev_owner new_owner = (struct rte_eth_dev_owner) 725 {.id = RTE_ETH_DEV_NO_OWNER, .name = ""}; 726 int ret; 727 728 eth_dev_shared_data_prepare(); 729 730 rte_spinlock_lock(ð_dev_shared_data->ownership_lock); 731 732 ret = eth_dev_owner_set(port_id, owner_id, &new_owner); 733 734 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock); 735 return ret; 736 } 737 738 int 739 rte_eth_dev_owner_delete(const uint64_t owner_id) 740 { 741 uint16_t port_id; 742 int ret = 0; 743 744 eth_dev_shared_data_prepare(); 745 746 rte_spinlock_lock(ð_dev_shared_data->ownership_lock); 747 748 if (eth_is_valid_owner_id(owner_id)) { 749 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) 750 if (rte_eth_devices[port_id].data->owner.id == owner_id) 751 memset(&rte_eth_devices[port_id].data->owner, 0, 752 sizeof(struct rte_eth_dev_owner)); 753 RTE_ETHDEV_LOG(NOTICE, 754 "All port owners owned by %016"PRIx64" identifier have removed\n", 755 owner_id); 756 } else { 757 RTE_ETHDEV_LOG(ERR, 758 "Invalid owner id=%016"PRIx64"\n", 759 owner_id); 760 ret = -EINVAL; 761 } 762 763 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock); 764 765 return ret; 766 } 767 768 int 769 rte_eth_dev_owner_get(const uint16_t port_id, struct rte_eth_dev_owner *owner) 770 { 771 struct rte_eth_dev *ethdev; 772 773 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 774 ethdev = &rte_eth_devices[port_id]; 775 776 if (!eth_dev_is_allocated(ethdev)) { 777 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n", 778 port_id); 779 return -ENODEV; 780 } 781 782 if (owner == NULL) { 783 RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u owner to NULL\n", 784 port_id); 785 return -EINVAL; 786 } 787 788 eth_dev_shared_data_prepare(); 789 790 rte_spinlock_lock(ð_dev_shared_data->ownership_lock); 791 rte_memcpy(owner, ðdev->data->owner, sizeof(*owner)); 792 rte_spinlock_unlock(ð_dev_shared_data->ownership_lock); 793 794 return 0; 795 } 796 797 int 798 rte_eth_dev_socket_id(uint16_t port_id) 799 { 800 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1); 801 return rte_eth_devices[port_id].data->numa_node; 802 } 803 804 void * 805 rte_eth_dev_get_sec_ctx(uint16_t port_id) 806 { 807 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL); 808 return rte_eth_devices[port_id].security_ctx; 809 } 810 811 uint16_t 812 rte_eth_dev_count_avail(void) 813 { 814 uint16_t p; 815 uint16_t count; 816 817 count = 0; 818 819 RTE_ETH_FOREACH_DEV(p) 820 count++; 821 822 return count; 823 } 824 825 uint16_t 826 rte_eth_dev_count_total(void) 827 { 828 uint16_t port, count = 0; 829 830 RTE_ETH_FOREACH_VALID_DEV(port) 831 count++; 832 833 return count; 834 } 835 836 int 837 rte_eth_dev_get_name_by_port(uint16_t port_id, char *name) 838 { 839 char *tmp; 840 841 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 842 843 if (name == NULL) { 844 RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u name to NULL\n", 845 port_id); 846 return -EINVAL; 847 } 848 849 /* shouldn't check 'rte_eth_devices[i].data', 850 * because it might be overwritten by VDEV PMD */ 851 tmp = eth_dev_shared_data->data[port_id].name; 852 strcpy(name, tmp); 853 return 0; 854 } 855 856 int 857 rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id) 858 { 859 uint16_t pid; 860 861 if (name == NULL) { 862 RTE_ETHDEV_LOG(ERR, "Cannot get port ID from NULL name"); 863 return -EINVAL; 864 } 865 866 if (port_id == NULL) { 867 RTE_ETHDEV_LOG(ERR, 868 "Cannot get port ID to NULL for %s\n", name); 869 return -EINVAL; 870 } 871 872 RTE_ETH_FOREACH_VALID_DEV(pid) 873 if (!strcmp(name, eth_dev_shared_data->data[pid].name)) { 874 *port_id = pid; 875 return 0; 876 } 877 878 return -ENODEV; 879 } 880 881 static int 882 eth_err(uint16_t port_id, int ret) 883 { 884 if (ret == 0) 885 return 0; 886 if (rte_eth_dev_is_removed(port_id)) 887 return -EIO; 888 return ret; 889 } 890 891 static void 892 eth_dev_rxq_release(struct rte_eth_dev *dev, uint16_t qid) 893 { 894 void **rxq = dev->data->rx_queues; 895 896 if (rxq[qid] == NULL) 897 return; 898 899 if (dev->dev_ops->rx_queue_release != NULL) 900 (*dev->dev_ops->rx_queue_release)(dev, qid); 901 rxq[qid] = NULL; 902 } 903 904 static void 905 eth_dev_txq_release(struct rte_eth_dev *dev, uint16_t qid) 906 { 907 void **txq = dev->data->tx_queues; 908 909 if (txq[qid] == NULL) 910 return; 911 912 if (dev->dev_ops->tx_queue_release != NULL) 913 (*dev->dev_ops->tx_queue_release)(dev, qid); 914 txq[qid] = NULL; 915 } 916 917 static int 918 eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues) 919 { 920 uint16_t old_nb_queues = dev->data->nb_rx_queues; 921 void **rxq; 922 unsigned i; 923 924 if (dev->data->rx_queues == NULL && nb_queues != 0) { /* first time configuration */ 925 dev->data->rx_queues = rte_zmalloc("ethdev->rx_queues", 926 sizeof(dev->data->rx_queues[0]) * nb_queues, 927 RTE_CACHE_LINE_SIZE); 928 if (dev->data->rx_queues == NULL) { 929 dev->data->nb_rx_queues = 0; 930 return -(ENOMEM); 931 } 932 } else if (dev->data->rx_queues != NULL && nb_queues != 0) { /* re-configure */ 933 for (i = nb_queues; i < old_nb_queues; i++) 934 eth_dev_rxq_release(dev, i); 935 936 rxq = dev->data->rx_queues; 937 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues, 938 RTE_CACHE_LINE_SIZE); 939 if (rxq == NULL) 940 return -(ENOMEM); 941 if (nb_queues > old_nb_queues) { 942 uint16_t new_qs = nb_queues - old_nb_queues; 943 944 memset(rxq + old_nb_queues, 0, 945 sizeof(rxq[0]) * new_qs); 946 } 947 948 dev->data->rx_queues = rxq; 949 950 } else if (dev->data->rx_queues != NULL && nb_queues == 0) { 951 for (i = nb_queues; i < old_nb_queues; i++) 952 eth_dev_rxq_release(dev, i); 953 954 rte_free(dev->data->rx_queues); 955 dev->data->rx_queues = NULL; 956 } 957 dev->data->nb_rx_queues = nb_queues; 958 return 0; 959 } 960 961 static int 962 eth_dev_validate_rx_queue(const struct rte_eth_dev *dev, uint16_t rx_queue_id) 963 { 964 uint16_t port_id; 965 966 if (rx_queue_id >= dev->data->nb_rx_queues) { 967 port_id = dev->data->port_id; 968 RTE_ETHDEV_LOG(ERR, 969 "Invalid Rx queue_id=%u of device with port_id=%u\n", 970 rx_queue_id, port_id); 971 return -EINVAL; 972 } 973 974 if (dev->data->rx_queues[rx_queue_id] == NULL) { 975 port_id = dev->data->port_id; 976 RTE_ETHDEV_LOG(ERR, 977 "Queue %u of device with port_id=%u has not been setup\n", 978 rx_queue_id, port_id); 979 return -EINVAL; 980 } 981 982 return 0; 983 } 984 985 static int 986 eth_dev_validate_tx_queue(const struct rte_eth_dev *dev, uint16_t tx_queue_id) 987 { 988 uint16_t port_id; 989 990 if (tx_queue_id >= dev->data->nb_tx_queues) { 991 port_id = dev->data->port_id; 992 RTE_ETHDEV_LOG(ERR, 993 "Invalid Tx queue_id=%u of device with port_id=%u\n", 994 tx_queue_id, port_id); 995 return -EINVAL; 996 } 997 998 if (dev->data->tx_queues[tx_queue_id] == NULL) { 999 port_id = dev->data->port_id; 1000 RTE_ETHDEV_LOG(ERR, 1001 "Queue %u of device with port_id=%u has not been setup\n", 1002 tx_queue_id, port_id); 1003 return -EINVAL; 1004 } 1005 1006 return 0; 1007 } 1008 1009 int 1010 rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id) 1011 { 1012 struct rte_eth_dev *dev; 1013 int ret; 1014 1015 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1016 dev = &rte_eth_devices[port_id]; 1017 1018 if (!dev->data->dev_started) { 1019 RTE_ETHDEV_LOG(ERR, 1020 "Port %u must be started before start any queue\n", 1021 port_id); 1022 return -EINVAL; 1023 } 1024 1025 ret = eth_dev_validate_rx_queue(dev, rx_queue_id); 1026 if (ret != 0) 1027 return ret; 1028 1029 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_start, -ENOTSUP); 1030 1031 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) { 1032 RTE_ETHDEV_LOG(INFO, 1033 "Can't start Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n", 1034 rx_queue_id, port_id); 1035 return -EINVAL; 1036 } 1037 1038 if (dev->data->rx_queue_state[rx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) { 1039 RTE_ETHDEV_LOG(INFO, 1040 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n", 1041 rx_queue_id, port_id); 1042 return 0; 1043 } 1044 1045 return eth_err(port_id, dev->dev_ops->rx_queue_start(dev, rx_queue_id)); 1046 } 1047 1048 int 1049 rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id) 1050 { 1051 struct rte_eth_dev *dev; 1052 int ret; 1053 1054 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1055 dev = &rte_eth_devices[port_id]; 1056 1057 ret = eth_dev_validate_rx_queue(dev, rx_queue_id); 1058 if (ret != 0) 1059 return ret; 1060 1061 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_stop, -ENOTSUP); 1062 1063 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) { 1064 RTE_ETHDEV_LOG(INFO, 1065 "Can't stop Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n", 1066 rx_queue_id, port_id); 1067 return -EINVAL; 1068 } 1069 1070 if (dev->data->rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) { 1071 RTE_ETHDEV_LOG(INFO, 1072 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n", 1073 rx_queue_id, port_id); 1074 return 0; 1075 } 1076 1077 return eth_err(port_id, dev->dev_ops->rx_queue_stop(dev, rx_queue_id)); 1078 } 1079 1080 int 1081 rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id) 1082 { 1083 struct rte_eth_dev *dev; 1084 int ret; 1085 1086 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1087 dev = &rte_eth_devices[port_id]; 1088 1089 if (!dev->data->dev_started) { 1090 RTE_ETHDEV_LOG(ERR, 1091 "Port %u must be started before start any queue\n", 1092 port_id); 1093 return -EINVAL; 1094 } 1095 1096 ret = eth_dev_validate_tx_queue(dev, tx_queue_id); 1097 if (ret != 0) 1098 return ret; 1099 1100 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_start, -ENOTSUP); 1101 1102 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) { 1103 RTE_ETHDEV_LOG(INFO, 1104 "Can't start Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n", 1105 tx_queue_id, port_id); 1106 return -EINVAL; 1107 } 1108 1109 if (dev->data->tx_queue_state[tx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) { 1110 RTE_ETHDEV_LOG(INFO, 1111 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n", 1112 tx_queue_id, port_id); 1113 return 0; 1114 } 1115 1116 return eth_err(port_id, dev->dev_ops->tx_queue_start(dev, tx_queue_id)); 1117 } 1118 1119 int 1120 rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id) 1121 { 1122 struct rte_eth_dev *dev; 1123 int ret; 1124 1125 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1126 dev = &rte_eth_devices[port_id]; 1127 1128 ret = eth_dev_validate_tx_queue(dev, tx_queue_id); 1129 if (ret != 0) 1130 return ret; 1131 1132 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_stop, -ENOTSUP); 1133 1134 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) { 1135 RTE_ETHDEV_LOG(INFO, 1136 "Can't stop Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n", 1137 tx_queue_id, port_id); 1138 return -EINVAL; 1139 } 1140 1141 if (dev->data->tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) { 1142 RTE_ETHDEV_LOG(INFO, 1143 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n", 1144 tx_queue_id, port_id); 1145 return 0; 1146 } 1147 1148 return eth_err(port_id, dev->dev_ops->tx_queue_stop(dev, tx_queue_id)); 1149 } 1150 1151 static int 1152 eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues) 1153 { 1154 uint16_t old_nb_queues = dev->data->nb_tx_queues; 1155 void **txq; 1156 unsigned i; 1157 1158 if (dev->data->tx_queues == NULL && nb_queues != 0) { /* first time configuration */ 1159 dev->data->tx_queues = rte_zmalloc("ethdev->tx_queues", 1160 sizeof(dev->data->tx_queues[0]) * nb_queues, 1161 RTE_CACHE_LINE_SIZE); 1162 if (dev->data->tx_queues == NULL) { 1163 dev->data->nb_tx_queues = 0; 1164 return -(ENOMEM); 1165 } 1166 } else if (dev->data->tx_queues != NULL && nb_queues != 0) { /* re-configure */ 1167 for (i = nb_queues; i < old_nb_queues; i++) 1168 eth_dev_txq_release(dev, i); 1169 1170 txq = dev->data->tx_queues; 1171 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues, 1172 RTE_CACHE_LINE_SIZE); 1173 if (txq == NULL) 1174 return -ENOMEM; 1175 if (nb_queues > old_nb_queues) { 1176 uint16_t new_qs = nb_queues - old_nb_queues; 1177 1178 memset(txq + old_nb_queues, 0, 1179 sizeof(txq[0]) * new_qs); 1180 } 1181 1182 dev->data->tx_queues = txq; 1183 1184 } else if (dev->data->tx_queues != NULL && nb_queues == 0) { 1185 for (i = nb_queues; i < old_nb_queues; i++) 1186 eth_dev_txq_release(dev, i); 1187 1188 rte_free(dev->data->tx_queues); 1189 dev->data->tx_queues = NULL; 1190 } 1191 dev->data->nb_tx_queues = nb_queues; 1192 return 0; 1193 } 1194 1195 uint32_t 1196 rte_eth_speed_bitflag(uint32_t speed, int duplex) 1197 { 1198 switch (speed) { 1199 case ETH_SPEED_NUM_10M: 1200 return duplex ? ETH_LINK_SPEED_10M : ETH_LINK_SPEED_10M_HD; 1201 case ETH_SPEED_NUM_100M: 1202 return duplex ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_100M_HD; 1203 case ETH_SPEED_NUM_1G: 1204 return ETH_LINK_SPEED_1G; 1205 case ETH_SPEED_NUM_2_5G: 1206 return ETH_LINK_SPEED_2_5G; 1207 case ETH_SPEED_NUM_5G: 1208 return ETH_LINK_SPEED_5G; 1209 case ETH_SPEED_NUM_10G: 1210 return ETH_LINK_SPEED_10G; 1211 case ETH_SPEED_NUM_20G: 1212 return ETH_LINK_SPEED_20G; 1213 case ETH_SPEED_NUM_25G: 1214 return ETH_LINK_SPEED_25G; 1215 case ETH_SPEED_NUM_40G: 1216 return ETH_LINK_SPEED_40G; 1217 case ETH_SPEED_NUM_50G: 1218 return ETH_LINK_SPEED_50G; 1219 case ETH_SPEED_NUM_56G: 1220 return ETH_LINK_SPEED_56G; 1221 case ETH_SPEED_NUM_100G: 1222 return ETH_LINK_SPEED_100G; 1223 case ETH_SPEED_NUM_200G: 1224 return ETH_LINK_SPEED_200G; 1225 default: 1226 return 0; 1227 } 1228 } 1229 1230 const char * 1231 rte_eth_dev_rx_offload_name(uint64_t offload) 1232 { 1233 const char *name = "UNKNOWN"; 1234 unsigned int i; 1235 1236 for (i = 0; i < RTE_DIM(eth_dev_rx_offload_names); ++i) { 1237 if (offload == eth_dev_rx_offload_names[i].offload) { 1238 name = eth_dev_rx_offload_names[i].name; 1239 break; 1240 } 1241 } 1242 1243 return name; 1244 } 1245 1246 const char * 1247 rte_eth_dev_tx_offload_name(uint64_t offload) 1248 { 1249 const char *name = "UNKNOWN"; 1250 unsigned int i; 1251 1252 for (i = 0; i < RTE_DIM(eth_dev_tx_offload_names); ++i) { 1253 if (offload == eth_dev_tx_offload_names[i].offload) { 1254 name = eth_dev_tx_offload_names[i].name; 1255 break; 1256 } 1257 } 1258 1259 return name; 1260 } 1261 1262 static inline int 1263 eth_dev_check_lro_pkt_size(uint16_t port_id, uint32_t config_size, 1264 uint32_t max_rx_pkt_len, uint32_t dev_info_size) 1265 { 1266 int ret = 0; 1267 1268 if (dev_info_size == 0) { 1269 if (config_size != max_rx_pkt_len) { 1270 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size" 1271 " %u != %u is not allowed\n", 1272 port_id, config_size, max_rx_pkt_len); 1273 ret = -EINVAL; 1274 } 1275 } else if (config_size > dev_info_size) { 1276 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u " 1277 "> max allowed value %u\n", port_id, config_size, 1278 dev_info_size); 1279 ret = -EINVAL; 1280 } else if (config_size < RTE_ETHER_MIN_LEN) { 1281 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u " 1282 "< min allowed value %u\n", port_id, config_size, 1283 (unsigned int)RTE_ETHER_MIN_LEN); 1284 ret = -EINVAL; 1285 } 1286 return ret; 1287 } 1288 1289 /* 1290 * Validate offloads that are requested through rte_eth_dev_configure against 1291 * the offloads successfully set by the ethernet device. 1292 * 1293 * @param port_id 1294 * The port identifier of the Ethernet device. 1295 * @param req_offloads 1296 * The offloads that have been requested through `rte_eth_dev_configure`. 1297 * @param set_offloads 1298 * The offloads successfully set by the ethernet device. 1299 * @param offload_type 1300 * The offload type i.e. Rx/Tx string. 1301 * @param offload_name 1302 * The function that prints the offload name. 1303 * @return 1304 * - (0) if validation successful. 1305 * - (-EINVAL) if requested offload has been silently disabled. 1306 * 1307 */ 1308 static int 1309 eth_dev_validate_offloads(uint16_t port_id, uint64_t req_offloads, 1310 uint64_t set_offloads, const char *offload_type, 1311 const char *(*offload_name)(uint64_t)) 1312 { 1313 uint64_t offloads_diff = req_offloads ^ set_offloads; 1314 uint64_t offload; 1315 int ret = 0; 1316 1317 while (offloads_diff != 0) { 1318 /* Check if any offload is requested but not enabled. */ 1319 offload = 1ULL << __builtin_ctzll(offloads_diff); 1320 if (offload & req_offloads) { 1321 RTE_ETHDEV_LOG(ERR, 1322 "Port %u failed to enable %s offload %s\n", 1323 port_id, offload_type, offload_name(offload)); 1324 ret = -EINVAL; 1325 } 1326 1327 /* Check if offload couldn't be disabled. */ 1328 if (offload & set_offloads) { 1329 RTE_ETHDEV_LOG(DEBUG, 1330 "Port %u %s offload %s is not requested but enabled\n", 1331 port_id, offload_type, offload_name(offload)); 1332 } 1333 1334 offloads_diff &= ~offload; 1335 } 1336 1337 return ret; 1338 } 1339 1340 int 1341 rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, 1342 const struct rte_eth_conf *dev_conf) 1343 { 1344 struct rte_eth_dev *dev; 1345 struct rte_eth_dev_info dev_info; 1346 struct rte_eth_conf orig_conf; 1347 uint16_t overhead_len; 1348 int diag; 1349 int ret; 1350 uint16_t old_mtu; 1351 1352 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1353 dev = &rte_eth_devices[port_id]; 1354 1355 if (dev_conf == NULL) { 1356 RTE_ETHDEV_LOG(ERR, 1357 "Cannot configure ethdev port %u from NULL config\n", 1358 port_id); 1359 return -EINVAL; 1360 } 1361 1362 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_configure, -ENOTSUP); 1363 1364 if (dev->data->dev_started) { 1365 RTE_ETHDEV_LOG(ERR, 1366 "Port %u must be stopped to allow configuration\n", 1367 port_id); 1368 return -EBUSY; 1369 } 1370 1371 /* 1372 * Ensure that "dev_configured" is always 0 each time prepare to do 1373 * dev_configure() to avoid any non-anticipated behaviour. 1374 * And set to 1 when dev_configure() is executed successfully. 1375 */ 1376 dev->data->dev_configured = 0; 1377 1378 /* Store original config, as rollback required on failure */ 1379 memcpy(&orig_conf, &dev->data->dev_conf, sizeof(dev->data->dev_conf)); 1380 1381 /* 1382 * Copy the dev_conf parameter into the dev structure. 1383 * rte_eth_dev_info_get() requires dev_conf, copy it before dev_info get 1384 */ 1385 if (dev_conf != &dev->data->dev_conf) 1386 memcpy(&dev->data->dev_conf, dev_conf, 1387 sizeof(dev->data->dev_conf)); 1388 1389 /* Backup mtu for rollback */ 1390 old_mtu = dev->data->mtu; 1391 1392 ret = rte_eth_dev_info_get(port_id, &dev_info); 1393 if (ret != 0) 1394 goto rollback; 1395 1396 /* Get the real Ethernet overhead length */ 1397 if (dev_info.max_mtu != UINT16_MAX && 1398 dev_info.max_rx_pktlen > dev_info.max_mtu) 1399 overhead_len = dev_info.max_rx_pktlen - dev_info.max_mtu; 1400 else 1401 overhead_len = RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 1402 1403 /* If number of queues specified by application for both Rx and Tx is 1404 * zero, use driver preferred values. This cannot be done individually 1405 * as it is valid for either Tx or Rx (but not both) to be zero. 1406 * If driver does not provide any preferred valued, fall back on 1407 * EAL defaults. 1408 */ 1409 if (nb_rx_q == 0 && nb_tx_q == 0) { 1410 nb_rx_q = dev_info.default_rxportconf.nb_queues; 1411 if (nb_rx_q == 0) 1412 nb_rx_q = RTE_ETH_DEV_FALLBACK_RX_NBQUEUES; 1413 nb_tx_q = dev_info.default_txportconf.nb_queues; 1414 if (nb_tx_q == 0) 1415 nb_tx_q = RTE_ETH_DEV_FALLBACK_TX_NBQUEUES; 1416 } 1417 1418 if (nb_rx_q > RTE_MAX_QUEUES_PER_PORT) { 1419 RTE_ETHDEV_LOG(ERR, 1420 "Number of RX queues requested (%u) is greater than max supported(%d)\n", 1421 nb_rx_q, RTE_MAX_QUEUES_PER_PORT); 1422 ret = -EINVAL; 1423 goto rollback; 1424 } 1425 1426 if (nb_tx_q > RTE_MAX_QUEUES_PER_PORT) { 1427 RTE_ETHDEV_LOG(ERR, 1428 "Number of TX queues requested (%u) is greater than max supported(%d)\n", 1429 nb_tx_q, RTE_MAX_QUEUES_PER_PORT); 1430 ret = -EINVAL; 1431 goto rollback; 1432 } 1433 1434 /* 1435 * Check that the numbers of RX and TX queues are not greater 1436 * than the maximum number of RX and TX queues supported by the 1437 * configured device. 1438 */ 1439 if (nb_rx_q > dev_info.max_rx_queues) { 1440 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_rx_queues=%u > %u\n", 1441 port_id, nb_rx_q, dev_info.max_rx_queues); 1442 ret = -EINVAL; 1443 goto rollback; 1444 } 1445 1446 if (nb_tx_q > dev_info.max_tx_queues) { 1447 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_tx_queues=%u > %u\n", 1448 port_id, nb_tx_q, dev_info.max_tx_queues); 1449 ret = -EINVAL; 1450 goto rollback; 1451 } 1452 1453 /* Check that the device supports requested interrupts */ 1454 if ((dev_conf->intr_conf.lsc == 1) && 1455 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC))) { 1456 RTE_ETHDEV_LOG(ERR, "Driver %s does not support lsc\n", 1457 dev->device->driver->name); 1458 ret = -EINVAL; 1459 goto rollback; 1460 } 1461 if ((dev_conf->intr_conf.rmv == 1) && 1462 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_RMV))) { 1463 RTE_ETHDEV_LOG(ERR, "Driver %s does not support rmv\n", 1464 dev->device->driver->name); 1465 ret = -EINVAL; 1466 goto rollback; 1467 } 1468 1469 /* 1470 * If jumbo frames are enabled, check that the maximum RX packet 1471 * length is supported by the configured device. 1472 */ 1473 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1474 if (dev_conf->rxmode.max_rx_pkt_len > dev_info.max_rx_pktlen) { 1475 RTE_ETHDEV_LOG(ERR, 1476 "Ethdev port_id=%u max_rx_pkt_len %u > max valid value %u\n", 1477 port_id, dev_conf->rxmode.max_rx_pkt_len, 1478 dev_info.max_rx_pktlen); 1479 ret = -EINVAL; 1480 goto rollback; 1481 } else if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN) { 1482 RTE_ETHDEV_LOG(ERR, 1483 "Ethdev port_id=%u max_rx_pkt_len %u < min valid value %u\n", 1484 port_id, dev_conf->rxmode.max_rx_pkt_len, 1485 (unsigned int)RTE_ETHER_MIN_LEN); 1486 ret = -EINVAL; 1487 goto rollback; 1488 } 1489 1490 /* Scale the MTU size to adapt max_rx_pkt_len */ 1491 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - 1492 overhead_len; 1493 } else { 1494 uint16_t pktlen = dev_conf->rxmode.max_rx_pkt_len; 1495 if (pktlen < RTE_ETHER_MIN_MTU + overhead_len || 1496 pktlen > RTE_ETHER_MTU + overhead_len) 1497 /* Use default value */ 1498 dev->data->dev_conf.rxmode.max_rx_pkt_len = 1499 RTE_ETHER_MTU + overhead_len; 1500 } 1501 1502 /* 1503 * If LRO is enabled, check that the maximum aggregated packet 1504 * size is supported by the configured device. 1505 */ 1506 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) { 1507 if (dev_conf->rxmode.max_lro_pkt_size == 0) 1508 dev->data->dev_conf.rxmode.max_lro_pkt_size = 1509 dev->data->dev_conf.rxmode.max_rx_pkt_len; 1510 ret = eth_dev_check_lro_pkt_size(port_id, 1511 dev->data->dev_conf.rxmode.max_lro_pkt_size, 1512 dev->data->dev_conf.rxmode.max_rx_pkt_len, 1513 dev_info.max_lro_pkt_size); 1514 if (ret != 0) 1515 goto rollback; 1516 } 1517 1518 /* Any requested offloading must be within its device capabilities */ 1519 if ((dev_conf->rxmode.offloads & dev_info.rx_offload_capa) != 1520 dev_conf->rxmode.offloads) { 1521 RTE_ETHDEV_LOG(ERR, 1522 "Ethdev port_id=%u requested Rx offloads 0x%"PRIx64" doesn't match Rx offloads " 1523 "capabilities 0x%"PRIx64" in %s()\n", 1524 port_id, dev_conf->rxmode.offloads, 1525 dev_info.rx_offload_capa, 1526 __func__); 1527 ret = -EINVAL; 1528 goto rollback; 1529 } 1530 if ((dev_conf->txmode.offloads & dev_info.tx_offload_capa) != 1531 dev_conf->txmode.offloads) { 1532 RTE_ETHDEV_LOG(ERR, 1533 "Ethdev port_id=%u requested Tx offloads 0x%"PRIx64" doesn't match Tx offloads " 1534 "capabilities 0x%"PRIx64" in %s()\n", 1535 port_id, dev_conf->txmode.offloads, 1536 dev_info.tx_offload_capa, 1537 __func__); 1538 ret = -EINVAL; 1539 goto rollback; 1540 } 1541 1542 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf = 1543 rte_eth_rss_hf_refine(dev_conf->rx_adv_conf.rss_conf.rss_hf); 1544 1545 /* Check that device supports requested rss hash functions. */ 1546 if ((dev_info.flow_type_rss_offloads | 1547 dev_conf->rx_adv_conf.rss_conf.rss_hf) != 1548 dev_info.flow_type_rss_offloads) { 1549 RTE_ETHDEV_LOG(ERR, 1550 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n", 1551 port_id, dev_conf->rx_adv_conf.rss_conf.rss_hf, 1552 dev_info.flow_type_rss_offloads); 1553 ret = -EINVAL; 1554 goto rollback; 1555 } 1556 1557 /* Check if Rx RSS distribution is disabled but RSS hash is enabled. */ 1558 if (((dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) == 0) && 1559 (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_RSS_HASH)) { 1560 RTE_ETHDEV_LOG(ERR, 1561 "Ethdev port_id=%u config invalid Rx mq_mode without RSS but %s offload is requested\n", 1562 port_id, 1563 rte_eth_dev_rx_offload_name(DEV_RX_OFFLOAD_RSS_HASH)); 1564 ret = -EINVAL; 1565 goto rollback; 1566 } 1567 1568 /* 1569 * Setup new number of RX/TX queues and reconfigure device. 1570 */ 1571 diag = eth_dev_rx_queue_config(dev, nb_rx_q); 1572 if (diag != 0) { 1573 RTE_ETHDEV_LOG(ERR, 1574 "Port%u eth_dev_rx_queue_config = %d\n", 1575 port_id, diag); 1576 ret = diag; 1577 goto rollback; 1578 } 1579 1580 diag = eth_dev_tx_queue_config(dev, nb_tx_q); 1581 if (diag != 0) { 1582 RTE_ETHDEV_LOG(ERR, 1583 "Port%u eth_dev_tx_queue_config = %d\n", 1584 port_id, diag); 1585 eth_dev_rx_queue_config(dev, 0); 1586 ret = diag; 1587 goto rollback; 1588 } 1589 1590 diag = (*dev->dev_ops->dev_configure)(dev); 1591 if (diag != 0) { 1592 RTE_ETHDEV_LOG(ERR, "Port%u dev_configure = %d\n", 1593 port_id, diag); 1594 ret = eth_err(port_id, diag); 1595 goto reset_queues; 1596 } 1597 1598 /* Initialize Rx profiling if enabled at compilation time. */ 1599 diag = __rte_eth_dev_profile_init(port_id, dev); 1600 if (diag != 0) { 1601 RTE_ETHDEV_LOG(ERR, "Port%u __rte_eth_dev_profile_init = %d\n", 1602 port_id, diag); 1603 ret = eth_err(port_id, diag); 1604 goto reset_queues; 1605 } 1606 1607 /* Validate Rx offloads. */ 1608 diag = eth_dev_validate_offloads(port_id, 1609 dev_conf->rxmode.offloads, 1610 dev->data->dev_conf.rxmode.offloads, "Rx", 1611 rte_eth_dev_rx_offload_name); 1612 if (diag != 0) { 1613 ret = diag; 1614 goto reset_queues; 1615 } 1616 1617 /* Validate Tx offloads. */ 1618 diag = eth_dev_validate_offloads(port_id, 1619 dev_conf->txmode.offloads, 1620 dev->data->dev_conf.txmode.offloads, "Tx", 1621 rte_eth_dev_tx_offload_name); 1622 if (diag != 0) { 1623 ret = diag; 1624 goto reset_queues; 1625 } 1626 1627 dev->data->dev_configured = 1; 1628 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, 0); 1629 return 0; 1630 reset_queues: 1631 eth_dev_rx_queue_config(dev, 0); 1632 eth_dev_tx_queue_config(dev, 0); 1633 rollback: 1634 memcpy(&dev->data->dev_conf, &orig_conf, sizeof(dev->data->dev_conf)); 1635 if (old_mtu != dev->data->mtu) 1636 dev->data->mtu = old_mtu; 1637 1638 rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, ret); 1639 return ret; 1640 } 1641 1642 void 1643 rte_eth_dev_internal_reset(struct rte_eth_dev *dev) 1644 { 1645 if (dev->data->dev_started) { 1646 RTE_ETHDEV_LOG(ERR, "Port %u must be stopped to allow reset\n", 1647 dev->data->port_id); 1648 return; 1649 } 1650 1651 eth_dev_rx_queue_config(dev, 0); 1652 eth_dev_tx_queue_config(dev, 0); 1653 1654 memset(&dev->data->dev_conf, 0, sizeof(dev->data->dev_conf)); 1655 } 1656 1657 static void 1658 eth_dev_mac_restore(struct rte_eth_dev *dev, 1659 struct rte_eth_dev_info *dev_info) 1660 { 1661 struct rte_ether_addr *addr; 1662 uint16_t i; 1663 uint32_t pool = 0; 1664 uint64_t pool_mask; 1665 1666 /* replay MAC address configuration including default MAC */ 1667 addr = &dev->data->mac_addrs[0]; 1668 if (*dev->dev_ops->mac_addr_set != NULL) 1669 (*dev->dev_ops->mac_addr_set)(dev, addr); 1670 else if (*dev->dev_ops->mac_addr_add != NULL) 1671 (*dev->dev_ops->mac_addr_add)(dev, addr, 0, pool); 1672 1673 if (*dev->dev_ops->mac_addr_add != NULL) { 1674 for (i = 1; i < dev_info->max_mac_addrs; i++) { 1675 addr = &dev->data->mac_addrs[i]; 1676 1677 /* skip zero address */ 1678 if (rte_is_zero_ether_addr(addr)) 1679 continue; 1680 1681 pool = 0; 1682 pool_mask = dev->data->mac_pool_sel[i]; 1683 1684 do { 1685 if (pool_mask & 1ULL) 1686 (*dev->dev_ops->mac_addr_add)(dev, 1687 addr, i, pool); 1688 pool_mask >>= 1; 1689 pool++; 1690 } while (pool_mask); 1691 } 1692 } 1693 } 1694 1695 static int 1696 eth_dev_config_restore(struct rte_eth_dev *dev, 1697 struct rte_eth_dev_info *dev_info, uint16_t port_id) 1698 { 1699 int ret; 1700 1701 if (!(*dev_info->dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR)) 1702 eth_dev_mac_restore(dev, dev_info); 1703 1704 /* replay promiscuous configuration */ 1705 /* 1706 * use callbacks directly since we don't need port_id check and 1707 * would like to bypass the same value set 1708 */ 1709 if (rte_eth_promiscuous_get(port_id) == 1 && 1710 *dev->dev_ops->promiscuous_enable != NULL) { 1711 ret = eth_err(port_id, 1712 (*dev->dev_ops->promiscuous_enable)(dev)); 1713 if (ret != 0 && ret != -ENOTSUP) { 1714 RTE_ETHDEV_LOG(ERR, 1715 "Failed to enable promiscuous mode for device (port %u): %s\n", 1716 port_id, rte_strerror(-ret)); 1717 return ret; 1718 } 1719 } else if (rte_eth_promiscuous_get(port_id) == 0 && 1720 *dev->dev_ops->promiscuous_disable != NULL) { 1721 ret = eth_err(port_id, 1722 (*dev->dev_ops->promiscuous_disable)(dev)); 1723 if (ret != 0 && ret != -ENOTSUP) { 1724 RTE_ETHDEV_LOG(ERR, 1725 "Failed to disable promiscuous mode for device (port %u): %s\n", 1726 port_id, rte_strerror(-ret)); 1727 return ret; 1728 } 1729 } 1730 1731 /* replay all multicast configuration */ 1732 /* 1733 * use callbacks directly since we don't need port_id check and 1734 * would like to bypass the same value set 1735 */ 1736 if (rte_eth_allmulticast_get(port_id) == 1 && 1737 *dev->dev_ops->allmulticast_enable != NULL) { 1738 ret = eth_err(port_id, 1739 (*dev->dev_ops->allmulticast_enable)(dev)); 1740 if (ret != 0 && ret != -ENOTSUP) { 1741 RTE_ETHDEV_LOG(ERR, 1742 "Failed to enable allmulticast mode for device (port %u): %s\n", 1743 port_id, rte_strerror(-ret)); 1744 return ret; 1745 } 1746 } else if (rte_eth_allmulticast_get(port_id) == 0 && 1747 *dev->dev_ops->allmulticast_disable != NULL) { 1748 ret = eth_err(port_id, 1749 (*dev->dev_ops->allmulticast_disable)(dev)); 1750 if (ret != 0 && ret != -ENOTSUP) { 1751 RTE_ETHDEV_LOG(ERR, 1752 "Failed to disable allmulticast mode for device (port %u): %s\n", 1753 port_id, rte_strerror(-ret)); 1754 return ret; 1755 } 1756 } 1757 1758 return 0; 1759 } 1760 1761 int 1762 rte_eth_dev_start(uint16_t port_id) 1763 { 1764 struct rte_eth_dev *dev; 1765 struct rte_eth_dev_info dev_info; 1766 int diag; 1767 int ret, ret_stop; 1768 1769 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1770 dev = &rte_eth_devices[port_id]; 1771 1772 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_start, -ENOTSUP); 1773 1774 if (dev->data->dev_configured == 0) { 1775 RTE_ETHDEV_LOG(INFO, 1776 "Device with port_id=%"PRIu16" is not configured.\n", 1777 port_id); 1778 return -EINVAL; 1779 } 1780 1781 if (dev->data->dev_started != 0) { 1782 RTE_ETHDEV_LOG(INFO, 1783 "Device with port_id=%"PRIu16" already started\n", 1784 port_id); 1785 return 0; 1786 } 1787 1788 ret = rte_eth_dev_info_get(port_id, &dev_info); 1789 if (ret != 0) 1790 return ret; 1791 1792 /* Lets restore MAC now if device does not support live change */ 1793 if (*dev_info.dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR) 1794 eth_dev_mac_restore(dev, &dev_info); 1795 1796 diag = (*dev->dev_ops->dev_start)(dev); 1797 if (diag == 0) 1798 dev->data->dev_started = 1; 1799 else 1800 return eth_err(port_id, diag); 1801 1802 ret = eth_dev_config_restore(dev, &dev_info, port_id); 1803 if (ret != 0) { 1804 RTE_ETHDEV_LOG(ERR, 1805 "Error during restoring configuration for device (port %u): %s\n", 1806 port_id, rte_strerror(-ret)); 1807 ret_stop = rte_eth_dev_stop(port_id); 1808 if (ret_stop != 0) { 1809 RTE_ETHDEV_LOG(ERR, 1810 "Failed to stop device (port %u): %s\n", 1811 port_id, rte_strerror(-ret_stop)); 1812 } 1813 1814 return ret; 1815 } 1816 1817 if (dev->data->dev_conf.intr_conf.lsc == 0) { 1818 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP); 1819 (*dev->dev_ops->link_update)(dev, 0); 1820 } 1821 1822 rte_ethdev_trace_start(port_id); 1823 return 0; 1824 } 1825 1826 int 1827 rte_eth_dev_stop(uint16_t port_id) 1828 { 1829 struct rte_eth_dev *dev; 1830 int ret; 1831 1832 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1833 dev = &rte_eth_devices[port_id]; 1834 1835 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_stop, -ENOTSUP); 1836 1837 if (dev->data->dev_started == 0) { 1838 RTE_ETHDEV_LOG(INFO, 1839 "Device with port_id=%"PRIu16" already stopped\n", 1840 port_id); 1841 return 0; 1842 } 1843 1844 dev->data->dev_started = 0; 1845 ret = (*dev->dev_ops->dev_stop)(dev); 1846 rte_ethdev_trace_stop(port_id, ret); 1847 1848 return ret; 1849 } 1850 1851 int 1852 rte_eth_dev_set_link_up(uint16_t port_id) 1853 { 1854 struct rte_eth_dev *dev; 1855 1856 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1857 dev = &rte_eth_devices[port_id]; 1858 1859 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_up, -ENOTSUP); 1860 return eth_err(port_id, (*dev->dev_ops->dev_set_link_up)(dev)); 1861 } 1862 1863 int 1864 rte_eth_dev_set_link_down(uint16_t port_id) 1865 { 1866 struct rte_eth_dev *dev; 1867 1868 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1869 dev = &rte_eth_devices[port_id]; 1870 1871 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_down, -ENOTSUP); 1872 return eth_err(port_id, (*dev->dev_ops->dev_set_link_down)(dev)); 1873 } 1874 1875 int 1876 rte_eth_dev_close(uint16_t port_id) 1877 { 1878 struct rte_eth_dev *dev; 1879 int firsterr, binerr; 1880 int *lasterr = &firsterr; 1881 1882 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1883 dev = &rte_eth_devices[port_id]; 1884 1885 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_close, -ENOTSUP); 1886 *lasterr = (*dev->dev_ops->dev_close)(dev); 1887 if (*lasterr != 0) 1888 lasterr = &binerr; 1889 1890 rte_ethdev_trace_close(port_id); 1891 *lasterr = rte_eth_dev_release_port(dev); 1892 1893 return firsterr; 1894 } 1895 1896 int 1897 rte_eth_dev_reset(uint16_t port_id) 1898 { 1899 struct rte_eth_dev *dev; 1900 int ret; 1901 1902 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1903 dev = &rte_eth_devices[port_id]; 1904 1905 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_reset, -ENOTSUP); 1906 1907 ret = rte_eth_dev_stop(port_id); 1908 if (ret != 0) { 1909 RTE_ETHDEV_LOG(ERR, 1910 "Failed to stop device (port %u) before reset: %s - ignore\n", 1911 port_id, rte_strerror(-ret)); 1912 } 1913 ret = dev->dev_ops->dev_reset(dev); 1914 1915 return eth_err(port_id, ret); 1916 } 1917 1918 int 1919 rte_eth_dev_is_removed(uint16_t port_id) 1920 { 1921 struct rte_eth_dev *dev; 1922 int ret; 1923 1924 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0); 1925 dev = &rte_eth_devices[port_id]; 1926 1927 if (dev->state == RTE_ETH_DEV_REMOVED) 1928 return 1; 1929 1930 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->is_removed, 0); 1931 1932 ret = dev->dev_ops->is_removed(dev); 1933 if (ret != 0) 1934 /* Device is physically removed. */ 1935 dev->state = RTE_ETH_DEV_REMOVED; 1936 1937 return ret; 1938 } 1939 1940 static int 1941 rte_eth_rx_queue_check_split(const struct rte_eth_rxseg_split *rx_seg, 1942 uint16_t n_seg, uint32_t *mbp_buf_size, 1943 const struct rte_eth_dev_info *dev_info) 1944 { 1945 const struct rte_eth_rxseg_capa *seg_capa = &dev_info->rx_seg_capa; 1946 struct rte_mempool *mp_first; 1947 uint32_t offset_mask; 1948 uint16_t seg_idx; 1949 1950 if (n_seg > seg_capa->max_nseg) { 1951 RTE_ETHDEV_LOG(ERR, 1952 "Requested Rx segments %u exceed supported %u\n", 1953 n_seg, seg_capa->max_nseg); 1954 return -EINVAL; 1955 } 1956 /* 1957 * Check the sizes and offsets against buffer sizes 1958 * for each segment specified in extended configuration. 1959 */ 1960 mp_first = rx_seg[0].mp; 1961 offset_mask = (1u << seg_capa->offset_align_log2) - 1; 1962 for (seg_idx = 0; seg_idx < n_seg; seg_idx++) { 1963 struct rte_mempool *mpl = rx_seg[seg_idx].mp; 1964 uint32_t length = rx_seg[seg_idx].length; 1965 uint32_t offset = rx_seg[seg_idx].offset; 1966 1967 if (mpl == NULL) { 1968 RTE_ETHDEV_LOG(ERR, "null mempool pointer\n"); 1969 return -EINVAL; 1970 } 1971 if (seg_idx != 0 && mp_first != mpl && 1972 seg_capa->multi_pools == 0) { 1973 RTE_ETHDEV_LOG(ERR, "Receiving to multiple pools is not supported\n"); 1974 return -ENOTSUP; 1975 } 1976 if (offset != 0) { 1977 if (seg_capa->offset_allowed == 0) { 1978 RTE_ETHDEV_LOG(ERR, "Rx segmentation with offset is not supported\n"); 1979 return -ENOTSUP; 1980 } 1981 if (offset & offset_mask) { 1982 RTE_ETHDEV_LOG(ERR, "Rx segmentation invalid offset alignment %u, %u\n", 1983 offset, 1984 seg_capa->offset_align_log2); 1985 return -EINVAL; 1986 } 1987 } 1988 if (mpl->private_data_size < 1989 sizeof(struct rte_pktmbuf_pool_private)) { 1990 RTE_ETHDEV_LOG(ERR, 1991 "%s private_data_size %u < %u\n", 1992 mpl->name, mpl->private_data_size, 1993 (unsigned int)sizeof 1994 (struct rte_pktmbuf_pool_private)); 1995 return -ENOSPC; 1996 } 1997 offset += seg_idx != 0 ? 0 : RTE_PKTMBUF_HEADROOM; 1998 *mbp_buf_size = rte_pktmbuf_data_room_size(mpl); 1999 length = length != 0 ? length : *mbp_buf_size; 2000 if (*mbp_buf_size < length + offset) { 2001 RTE_ETHDEV_LOG(ERR, 2002 "%s mbuf_data_room_size %u < %u (segment length=%u + segment offset=%u)\n", 2003 mpl->name, *mbp_buf_size, 2004 length + offset, length, offset); 2005 return -EINVAL; 2006 } 2007 } 2008 return 0; 2009 } 2010 2011 int 2012 rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, 2013 uint16_t nb_rx_desc, unsigned int socket_id, 2014 const struct rte_eth_rxconf *rx_conf, 2015 struct rte_mempool *mp) 2016 { 2017 int ret; 2018 uint32_t mbp_buf_size; 2019 struct rte_eth_dev *dev; 2020 struct rte_eth_dev_info dev_info; 2021 struct rte_eth_rxconf local_conf; 2022 2023 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2024 dev = &rte_eth_devices[port_id]; 2025 2026 if (rx_queue_id >= dev->data->nb_rx_queues) { 2027 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id); 2028 return -EINVAL; 2029 } 2030 2031 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_setup, -ENOTSUP); 2032 2033 ret = rte_eth_dev_info_get(port_id, &dev_info); 2034 if (ret != 0) 2035 return ret; 2036 2037 if (mp != NULL) { 2038 /* Single pool configuration check. */ 2039 if (rx_conf != NULL && rx_conf->rx_nseg != 0) { 2040 RTE_ETHDEV_LOG(ERR, 2041 "Ambiguous segment configuration\n"); 2042 return -EINVAL; 2043 } 2044 /* 2045 * Check the size of the mbuf data buffer, this value 2046 * must be provided in the private data of the memory pool. 2047 * First check that the memory pool(s) has a valid private data. 2048 */ 2049 if (mp->private_data_size < 2050 sizeof(struct rte_pktmbuf_pool_private)) { 2051 RTE_ETHDEV_LOG(ERR, "%s private_data_size %u < %u\n", 2052 mp->name, mp->private_data_size, 2053 (unsigned int) 2054 sizeof(struct rte_pktmbuf_pool_private)); 2055 return -ENOSPC; 2056 } 2057 mbp_buf_size = rte_pktmbuf_data_room_size(mp); 2058 if (mbp_buf_size < dev_info.min_rx_bufsize + 2059 RTE_PKTMBUF_HEADROOM) { 2060 RTE_ETHDEV_LOG(ERR, 2061 "%s mbuf_data_room_size %u < %u (RTE_PKTMBUF_HEADROOM=%u + min_rx_bufsize(dev)=%u)\n", 2062 mp->name, mbp_buf_size, 2063 RTE_PKTMBUF_HEADROOM + 2064 dev_info.min_rx_bufsize, 2065 RTE_PKTMBUF_HEADROOM, 2066 dev_info.min_rx_bufsize); 2067 return -EINVAL; 2068 } 2069 } else { 2070 const struct rte_eth_rxseg_split *rx_seg; 2071 uint16_t n_seg; 2072 2073 /* Extended multi-segment configuration check. */ 2074 if (rx_conf == NULL || rx_conf->rx_seg == NULL || rx_conf->rx_nseg == 0) { 2075 RTE_ETHDEV_LOG(ERR, 2076 "Memory pool is null and no extended configuration provided\n"); 2077 return -EINVAL; 2078 } 2079 2080 rx_seg = (const struct rte_eth_rxseg_split *)rx_conf->rx_seg; 2081 n_seg = rx_conf->rx_nseg; 2082 2083 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) { 2084 ret = rte_eth_rx_queue_check_split(rx_seg, n_seg, 2085 &mbp_buf_size, 2086 &dev_info); 2087 if (ret != 0) 2088 return ret; 2089 } else { 2090 RTE_ETHDEV_LOG(ERR, "No Rx segmentation offload configured\n"); 2091 return -EINVAL; 2092 } 2093 } 2094 2095 /* Use default specified by driver, if nb_rx_desc is zero */ 2096 if (nb_rx_desc == 0) { 2097 nb_rx_desc = dev_info.default_rxportconf.ring_size; 2098 /* If driver default is also zero, fall back on EAL default */ 2099 if (nb_rx_desc == 0) 2100 nb_rx_desc = RTE_ETH_DEV_FALLBACK_RX_RINGSIZE; 2101 } 2102 2103 if (nb_rx_desc > dev_info.rx_desc_lim.nb_max || 2104 nb_rx_desc < dev_info.rx_desc_lim.nb_min || 2105 nb_rx_desc % dev_info.rx_desc_lim.nb_align != 0) { 2106 2107 RTE_ETHDEV_LOG(ERR, 2108 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n", 2109 nb_rx_desc, dev_info.rx_desc_lim.nb_max, 2110 dev_info.rx_desc_lim.nb_min, 2111 dev_info.rx_desc_lim.nb_align); 2112 return -EINVAL; 2113 } 2114 2115 if (dev->data->dev_started && 2116 !(dev_info.dev_capa & 2117 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP)) 2118 return -EBUSY; 2119 2120 if (dev->data->dev_started && 2121 (dev->data->rx_queue_state[rx_queue_id] != 2122 RTE_ETH_QUEUE_STATE_STOPPED)) 2123 return -EBUSY; 2124 2125 eth_dev_rxq_release(dev, rx_queue_id); 2126 2127 if (rx_conf == NULL) 2128 rx_conf = &dev_info.default_rxconf; 2129 2130 local_conf = *rx_conf; 2131 2132 /* 2133 * If an offloading has already been enabled in 2134 * rte_eth_dev_configure(), it has been enabled on all queues, 2135 * so there is no need to enable it in this queue again. 2136 * The local_conf.offloads input to underlying PMD only carries 2137 * those offloadings which are only enabled on this queue and 2138 * not enabled on all queues. 2139 */ 2140 local_conf.offloads &= ~dev->data->dev_conf.rxmode.offloads; 2141 2142 /* 2143 * New added offloadings for this queue are those not enabled in 2144 * rte_eth_dev_configure() and they must be per-queue type. 2145 * A pure per-port offloading can't be enabled on a queue while 2146 * disabled on another queue. A pure per-port offloading can't 2147 * be enabled for any queue as new added one if it hasn't been 2148 * enabled in rte_eth_dev_configure(). 2149 */ 2150 if ((local_conf.offloads & dev_info.rx_queue_offload_capa) != 2151 local_conf.offloads) { 2152 RTE_ETHDEV_LOG(ERR, 2153 "Ethdev port_id=%d rx_queue_id=%d, new added offloads 0x%"PRIx64" must be " 2154 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n", 2155 port_id, rx_queue_id, local_conf.offloads, 2156 dev_info.rx_queue_offload_capa, 2157 __func__); 2158 return -EINVAL; 2159 } 2160 2161 /* 2162 * If LRO is enabled, check that the maximum aggregated packet 2163 * size is supported by the configured device. 2164 */ 2165 if (local_conf.offloads & DEV_RX_OFFLOAD_TCP_LRO) { 2166 if (dev->data->dev_conf.rxmode.max_lro_pkt_size == 0) 2167 dev->data->dev_conf.rxmode.max_lro_pkt_size = 2168 dev->data->dev_conf.rxmode.max_rx_pkt_len; 2169 int ret = eth_dev_check_lro_pkt_size(port_id, 2170 dev->data->dev_conf.rxmode.max_lro_pkt_size, 2171 dev->data->dev_conf.rxmode.max_rx_pkt_len, 2172 dev_info.max_lro_pkt_size); 2173 if (ret != 0) 2174 return ret; 2175 } 2176 2177 ret = (*dev->dev_ops->rx_queue_setup)(dev, rx_queue_id, nb_rx_desc, 2178 socket_id, &local_conf, mp); 2179 if (!ret) { 2180 if (!dev->data->min_rx_buf_size || 2181 dev->data->min_rx_buf_size > mbp_buf_size) 2182 dev->data->min_rx_buf_size = mbp_buf_size; 2183 } 2184 2185 rte_ethdev_trace_rxq_setup(port_id, rx_queue_id, nb_rx_desc, mp, 2186 rx_conf, ret); 2187 return eth_err(port_id, ret); 2188 } 2189 2190 int 2191 rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id, 2192 uint16_t nb_rx_desc, 2193 const struct rte_eth_hairpin_conf *conf) 2194 { 2195 int ret; 2196 struct rte_eth_dev *dev; 2197 struct rte_eth_hairpin_cap cap; 2198 int i; 2199 int count; 2200 2201 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2202 dev = &rte_eth_devices[port_id]; 2203 2204 if (rx_queue_id >= dev->data->nb_rx_queues) { 2205 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id); 2206 return -EINVAL; 2207 } 2208 2209 if (conf == NULL) { 2210 RTE_ETHDEV_LOG(ERR, 2211 "Cannot setup ethdev port %u Rx hairpin queue from NULL config\n", 2212 port_id); 2213 return -EINVAL; 2214 } 2215 2216 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap); 2217 if (ret != 0) 2218 return ret; 2219 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_hairpin_queue_setup, 2220 -ENOTSUP); 2221 /* if nb_rx_desc is zero use max number of desc from the driver. */ 2222 if (nb_rx_desc == 0) 2223 nb_rx_desc = cap.max_nb_desc; 2224 if (nb_rx_desc > cap.max_nb_desc) { 2225 RTE_ETHDEV_LOG(ERR, 2226 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu", 2227 nb_rx_desc, cap.max_nb_desc); 2228 return -EINVAL; 2229 } 2230 if (conf->peer_count > cap.max_rx_2_tx) { 2231 RTE_ETHDEV_LOG(ERR, 2232 "Invalid value for number of peers for Rx queue(=%u), should be: <= %hu", 2233 conf->peer_count, cap.max_rx_2_tx); 2234 return -EINVAL; 2235 } 2236 if (conf->peer_count == 0) { 2237 RTE_ETHDEV_LOG(ERR, 2238 "Invalid value for number of peers for Rx queue(=%u), should be: > 0", 2239 conf->peer_count); 2240 return -EINVAL; 2241 } 2242 for (i = 0, count = 0; i < dev->data->nb_rx_queues && 2243 cap.max_nb_queues != UINT16_MAX; i++) { 2244 if (i == rx_queue_id || rte_eth_dev_is_rx_hairpin_queue(dev, i)) 2245 count++; 2246 } 2247 if (count > cap.max_nb_queues) { 2248 RTE_ETHDEV_LOG(ERR, "To many Rx hairpin queues max is %d", 2249 cap.max_nb_queues); 2250 return -EINVAL; 2251 } 2252 if (dev->data->dev_started) 2253 return -EBUSY; 2254 eth_dev_rxq_release(dev, rx_queue_id); 2255 ret = (*dev->dev_ops->rx_hairpin_queue_setup)(dev, rx_queue_id, 2256 nb_rx_desc, conf); 2257 if (ret == 0) 2258 dev->data->rx_queue_state[rx_queue_id] = 2259 RTE_ETH_QUEUE_STATE_HAIRPIN; 2260 return eth_err(port_id, ret); 2261 } 2262 2263 int 2264 rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id, 2265 uint16_t nb_tx_desc, unsigned int socket_id, 2266 const struct rte_eth_txconf *tx_conf) 2267 { 2268 struct rte_eth_dev *dev; 2269 struct rte_eth_dev_info dev_info; 2270 struct rte_eth_txconf local_conf; 2271 int ret; 2272 2273 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2274 dev = &rte_eth_devices[port_id]; 2275 2276 if (tx_queue_id >= dev->data->nb_tx_queues) { 2277 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id); 2278 return -EINVAL; 2279 } 2280 2281 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_setup, -ENOTSUP); 2282 2283 ret = rte_eth_dev_info_get(port_id, &dev_info); 2284 if (ret != 0) 2285 return ret; 2286 2287 /* Use default specified by driver, if nb_tx_desc is zero */ 2288 if (nb_tx_desc == 0) { 2289 nb_tx_desc = dev_info.default_txportconf.ring_size; 2290 /* If driver default is zero, fall back on EAL default */ 2291 if (nb_tx_desc == 0) 2292 nb_tx_desc = RTE_ETH_DEV_FALLBACK_TX_RINGSIZE; 2293 } 2294 if (nb_tx_desc > dev_info.tx_desc_lim.nb_max || 2295 nb_tx_desc < dev_info.tx_desc_lim.nb_min || 2296 nb_tx_desc % dev_info.tx_desc_lim.nb_align != 0) { 2297 RTE_ETHDEV_LOG(ERR, 2298 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n", 2299 nb_tx_desc, dev_info.tx_desc_lim.nb_max, 2300 dev_info.tx_desc_lim.nb_min, 2301 dev_info.tx_desc_lim.nb_align); 2302 return -EINVAL; 2303 } 2304 2305 if (dev->data->dev_started && 2306 !(dev_info.dev_capa & 2307 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP)) 2308 return -EBUSY; 2309 2310 if (dev->data->dev_started && 2311 (dev->data->tx_queue_state[tx_queue_id] != 2312 RTE_ETH_QUEUE_STATE_STOPPED)) 2313 return -EBUSY; 2314 2315 eth_dev_txq_release(dev, tx_queue_id); 2316 2317 if (tx_conf == NULL) 2318 tx_conf = &dev_info.default_txconf; 2319 2320 local_conf = *tx_conf; 2321 2322 /* 2323 * If an offloading has already been enabled in 2324 * rte_eth_dev_configure(), it has been enabled on all queues, 2325 * so there is no need to enable it in this queue again. 2326 * The local_conf.offloads input to underlying PMD only carries 2327 * those offloadings which are only enabled on this queue and 2328 * not enabled on all queues. 2329 */ 2330 local_conf.offloads &= ~dev->data->dev_conf.txmode.offloads; 2331 2332 /* 2333 * New added offloadings for this queue are those not enabled in 2334 * rte_eth_dev_configure() and they must be per-queue type. 2335 * A pure per-port offloading can't be enabled on a queue while 2336 * disabled on another queue. A pure per-port offloading can't 2337 * be enabled for any queue as new added one if it hasn't been 2338 * enabled in rte_eth_dev_configure(). 2339 */ 2340 if ((local_conf.offloads & dev_info.tx_queue_offload_capa) != 2341 local_conf.offloads) { 2342 RTE_ETHDEV_LOG(ERR, 2343 "Ethdev port_id=%d tx_queue_id=%d, new added offloads 0x%"PRIx64" must be " 2344 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n", 2345 port_id, tx_queue_id, local_conf.offloads, 2346 dev_info.tx_queue_offload_capa, 2347 __func__); 2348 return -EINVAL; 2349 } 2350 2351 rte_ethdev_trace_txq_setup(port_id, tx_queue_id, nb_tx_desc, tx_conf); 2352 return eth_err(port_id, (*dev->dev_ops->tx_queue_setup)(dev, 2353 tx_queue_id, nb_tx_desc, socket_id, &local_conf)); 2354 } 2355 2356 int 2357 rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id, 2358 uint16_t nb_tx_desc, 2359 const struct rte_eth_hairpin_conf *conf) 2360 { 2361 struct rte_eth_dev *dev; 2362 struct rte_eth_hairpin_cap cap; 2363 int i; 2364 int count; 2365 int ret; 2366 2367 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2368 dev = &rte_eth_devices[port_id]; 2369 2370 if (tx_queue_id >= dev->data->nb_tx_queues) { 2371 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id); 2372 return -EINVAL; 2373 } 2374 2375 if (conf == NULL) { 2376 RTE_ETHDEV_LOG(ERR, 2377 "Cannot setup ethdev port %u Tx hairpin queue from NULL config\n", 2378 port_id); 2379 return -EINVAL; 2380 } 2381 2382 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap); 2383 if (ret != 0) 2384 return ret; 2385 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_hairpin_queue_setup, 2386 -ENOTSUP); 2387 /* if nb_rx_desc is zero use max number of desc from the driver. */ 2388 if (nb_tx_desc == 0) 2389 nb_tx_desc = cap.max_nb_desc; 2390 if (nb_tx_desc > cap.max_nb_desc) { 2391 RTE_ETHDEV_LOG(ERR, 2392 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu", 2393 nb_tx_desc, cap.max_nb_desc); 2394 return -EINVAL; 2395 } 2396 if (conf->peer_count > cap.max_tx_2_rx) { 2397 RTE_ETHDEV_LOG(ERR, 2398 "Invalid value for number of peers for Tx queue(=%u), should be: <= %hu", 2399 conf->peer_count, cap.max_tx_2_rx); 2400 return -EINVAL; 2401 } 2402 if (conf->peer_count == 0) { 2403 RTE_ETHDEV_LOG(ERR, 2404 "Invalid value for number of peers for Tx queue(=%u), should be: > 0", 2405 conf->peer_count); 2406 return -EINVAL; 2407 } 2408 for (i = 0, count = 0; i < dev->data->nb_tx_queues && 2409 cap.max_nb_queues != UINT16_MAX; i++) { 2410 if (i == tx_queue_id || rte_eth_dev_is_tx_hairpin_queue(dev, i)) 2411 count++; 2412 } 2413 if (count > cap.max_nb_queues) { 2414 RTE_ETHDEV_LOG(ERR, "To many Tx hairpin queues max is %d", 2415 cap.max_nb_queues); 2416 return -EINVAL; 2417 } 2418 if (dev->data->dev_started) 2419 return -EBUSY; 2420 eth_dev_txq_release(dev, tx_queue_id); 2421 ret = (*dev->dev_ops->tx_hairpin_queue_setup) 2422 (dev, tx_queue_id, nb_tx_desc, conf); 2423 if (ret == 0) 2424 dev->data->tx_queue_state[tx_queue_id] = 2425 RTE_ETH_QUEUE_STATE_HAIRPIN; 2426 return eth_err(port_id, ret); 2427 } 2428 2429 int 2430 rte_eth_hairpin_bind(uint16_t tx_port, uint16_t rx_port) 2431 { 2432 struct rte_eth_dev *dev; 2433 int ret; 2434 2435 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV); 2436 dev = &rte_eth_devices[tx_port]; 2437 2438 if (dev->data->dev_started == 0) { 2439 RTE_ETHDEV_LOG(ERR, "Tx port %d is not started\n", tx_port); 2440 return -EBUSY; 2441 } 2442 2443 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_bind, -ENOTSUP); 2444 ret = (*dev->dev_ops->hairpin_bind)(dev, rx_port); 2445 if (ret != 0) 2446 RTE_ETHDEV_LOG(ERR, "Failed to bind hairpin Tx %d" 2447 " to Rx %d (%d - all ports)\n", 2448 tx_port, rx_port, RTE_MAX_ETHPORTS); 2449 2450 return ret; 2451 } 2452 2453 int 2454 rte_eth_hairpin_unbind(uint16_t tx_port, uint16_t rx_port) 2455 { 2456 struct rte_eth_dev *dev; 2457 int ret; 2458 2459 RTE_ETH_VALID_PORTID_OR_ERR_RET(tx_port, -ENODEV); 2460 dev = &rte_eth_devices[tx_port]; 2461 2462 if (dev->data->dev_started == 0) { 2463 RTE_ETHDEV_LOG(ERR, "Tx port %d is already stopped\n", tx_port); 2464 return -EBUSY; 2465 } 2466 2467 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_unbind, -ENOTSUP); 2468 ret = (*dev->dev_ops->hairpin_unbind)(dev, rx_port); 2469 if (ret != 0) 2470 RTE_ETHDEV_LOG(ERR, "Failed to unbind hairpin Tx %d" 2471 " from Rx %d (%d - all ports)\n", 2472 tx_port, rx_port, RTE_MAX_ETHPORTS); 2473 2474 return ret; 2475 } 2476 2477 int 2478 rte_eth_hairpin_get_peer_ports(uint16_t port_id, uint16_t *peer_ports, 2479 size_t len, uint32_t direction) 2480 { 2481 struct rte_eth_dev *dev; 2482 int ret; 2483 2484 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2485 dev = &rte_eth_devices[port_id]; 2486 2487 if (peer_ports == NULL) { 2488 RTE_ETHDEV_LOG(ERR, 2489 "Cannot get ethdev port %u hairpin peer ports to NULL\n", 2490 port_id); 2491 return -EINVAL; 2492 } 2493 2494 if (len == 0) { 2495 RTE_ETHDEV_LOG(ERR, 2496 "Cannot get ethdev port %u hairpin peer ports to array with zero size\n", 2497 port_id); 2498 return -EINVAL; 2499 } 2500 2501 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_get_peer_ports, 2502 -ENOTSUP); 2503 2504 ret = (*dev->dev_ops->hairpin_get_peer_ports)(dev, peer_ports, 2505 len, direction); 2506 if (ret < 0) 2507 RTE_ETHDEV_LOG(ERR, "Failed to get %d hairpin peer %s ports\n", 2508 port_id, direction ? "Rx" : "Tx"); 2509 2510 return ret; 2511 } 2512 2513 void 2514 rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent, 2515 void *userdata __rte_unused) 2516 { 2517 rte_pktmbuf_free_bulk(pkts, unsent); 2518 } 2519 2520 void 2521 rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent, 2522 void *userdata) 2523 { 2524 uint64_t *count = userdata; 2525 2526 rte_pktmbuf_free_bulk(pkts, unsent); 2527 *count += unsent; 2528 } 2529 2530 int 2531 rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer, 2532 buffer_tx_error_fn cbfn, void *userdata) 2533 { 2534 if (buffer == NULL) { 2535 RTE_ETHDEV_LOG(ERR, 2536 "Cannot set Tx buffer error callback to NULL buffer\n"); 2537 return -EINVAL; 2538 } 2539 2540 buffer->error_callback = cbfn; 2541 buffer->error_userdata = userdata; 2542 return 0; 2543 } 2544 2545 int 2546 rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size) 2547 { 2548 int ret = 0; 2549 2550 if (buffer == NULL) { 2551 RTE_ETHDEV_LOG(ERR, "Cannot initialize NULL buffer\n"); 2552 return -EINVAL; 2553 } 2554 2555 buffer->size = size; 2556 if (buffer->error_callback == NULL) { 2557 ret = rte_eth_tx_buffer_set_err_callback( 2558 buffer, rte_eth_tx_buffer_drop_callback, NULL); 2559 } 2560 2561 return ret; 2562 } 2563 2564 int 2565 rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt) 2566 { 2567 struct rte_eth_dev *dev; 2568 int ret; 2569 2570 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2571 dev = &rte_eth_devices[port_id]; 2572 2573 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_done_cleanup, -ENOTSUP); 2574 2575 /* Call driver to free pending mbufs. */ 2576 ret = (*dev->dev_ops->tx_done_cleanup)(dev->data->tx_queues[queue_id], 2577 free_cnt); 2578 return eth_err(port_id, ret); 2579 } 2580 2581 int 2582 rte_eth_promiscuous_enable(uint16_t port_id) 2583 { 2584 struct rte_eth_dev *dev; 2585 int diag = 0; 2586 2587 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2588 dev = &rte_eth_devices[port_id]; 2589 2590 if (dev->data->promiscuous == 1) 2591 return 0; 2592 2593 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_enable, -ENOTSUP); 2594 2595 diag = (*dev->dev_ops->promiscuous_enable)(dev); 2596 dev->data->promiscuous = (diag == 0) ? 1 : 0; 2597 2598 return eth_err(port_id, diag); 2599 } 2600 2601 int 2602 rte_eth_promiscuous_disable(uint16_t port_id) 2603 { 2604 struct rte_eth_dev *dev; 2605 int diag = 0; 2606 2607 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2608 dev = &rte_eth_devices[port_id]; 2609 2610 if (dev->data->promiscuous == 0) 2611 return 0; 2612 2613 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_disable, -ENOTSUP); 2614 2615 dev->data->promiscuous = 0; 2616 diag = (*dev->dev_ops->promiscuous_disable)(dev); 2617 if (diag != 0) 2618 dev->data->promiscuous = 1; 2619 2620 return eth_err(port_id, diag); 2621 } 2622 2623 int 2624 rte_eth_promiscuous_get(uint16_t port_id) 2625 { 2626 struct rte_eth_dev *dev; 2627 2628 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2629 dev = &rte_eth_devices[port_id]; 2630 2631 return dev->data->promiscuous; 2632 } 2633 2634 int 2635 rte_eth_allmulticast_enable(uint16_t port_id) 2636 { 2637 struct rte_eth_dev *dev; 2638 int diag; 2639 2640 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2641 dev = &rte_eth_devices[port_id]; 2642 2643 if (dev->data->all_multicast == 1) 2644 return 0; 2645 2646 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_enable, -ENOTSUP); 2647 diag = (*dev->dev_ops->allmulticast_enable)(dev); 2648 dev->data->all_multicast = (diag == 0) ? 1 : 0; 2649 2650 return eth_err(port_id, diag); 2651 } 2652 2653 int 2654 rte_eth_allmulticast_disable(uint16_t port_id) 2655 { 2656 struct rte_eth_dev *dev; 2657 int diag; 2658 2659 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2660 dev = &rte_eth_devices[port_id]; 2661 2662 if (dev->data->all_multicast == 0) 2663 return 0; 2664 2665 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_disable, -ENOTSUP); 2666 dev->data->all_multicast = 0; 2667 diag = (*dev->dev_ops->allmulticast_disable)(dev); 2668 if (diag != 0) 2669 dev->data->all_multicast = 1; 2670 2671 return eth_err(port_id, diag); 2672 } 2673 2674 int 2675 rte_eth_allmulticast_get(uint16_t port_id) 2676 { 2677 struct rte_eth_dev *dev; 2678 2679 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2680 dev = &rte_eth_devices[port_id]; 2681 2682 return dev->data->all_multicast; 2683 } 2684 2685 int 2686 rte_eth_link_get(uint16_t port_id, struct rte_eth_link *eth_link) 2687 { 2688 struct rte_eth_dev *dev; 2689 2690 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2691 dev = &rte_eth_devices[port_id]; 2692 2693 if (eth_link == NULL) { 2694 RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u link to NULL\n", 2695 port_id); 2696 return -EINVAL; 2697 } 2698 2699 if (dev->data->dev_conf.intr_conf.lsc && dev->data->dev_started) 2700 rte_eth_linkstatus_get(dev, eth_link); 2701 else { 2702 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP); 2703 (*dev->dev_ops->link_update)(dev, 1); 2704 *eth_link = dev->data->dev_link; 2705 } 2706 2707 return 0; 2708 } 2709 2710 int 2711 rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *eth_link) 2712 { 2713 struct rte_eth_dev *dev; 2714 2715 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2716 dev = &rte_eth_devices[port_id]; 2717 2718 if (eth_link == NULL) { 2719 RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u link to NULL\n", 2720 port_id); 2721 return -EINVAL; 2722 } 2723 2724 if (dev->data->dev_conf.intr_conf.lsc && dev->data->dev_started) 2725 rte_eth_linkstatus_get(dev, eth_link); 2726 else { 2727 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP); 2728 (*dev->dev_ops->link_update)(dev, 0); 2729 *eth_link = dev->data->dev_link; 2730 } 2731 2732 return 0; 2733 } 2734 2735 const char * 2736 rte_eth_link_speed_to_str(uint32_t link_speed) 2737 { 2738 switch (link_speed) { 2739 case ETH_SPEED_NUM_NONE: return "None"; 2740 case ETH_SPEED_NUM_10M: return "10 Mbps"; 2741 case ETH_SPEED_NUM_100M: return "100 Mbps"; 2742 case ETH_SPEED_NUM_1G: return "1 Gbps"; 2743 case ETH_SPEED_NUM_2_5G: return "2.5 Gbps"; 2744 case ETH_SPEED_NUM_5G: return "5 Gbps"; 2745 case ETH_SPEED_NUM_10G: return "10 Gbps"; 2746 case ETH_SPEED_NUM_20G: return "20 Gbps"; 2747 case ETH_SPEED_NUM_25G: return "25 Gbps"; 2748 case ETH_SPEED_NUM_40G: return "40 Gbps"; 2749 case ETH_SPEED_NUM_50G: return "50 Gbps"; 2750 case ETH_SPEED_NUM_56G: return "56 Gbps"; 2751 case ETH_SPEED_NUM_100G: return "100 Gbps"; 2752 case ETH_SPEED_NUM_200G: return "200 Gbps"; 2753 case ETH_SPEED_NUM_UNKNOWN: return "Unknown"; 2754 default: return "Invalid"; 2755 } 2756 } 2757 2758 int 2759 rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link) 2760 { 2761 if (str == NULL) { 2762 RTE_ETHDEV_LOG(ERR, "Cannot convert link to NULL string\n"); 2763 return -EINVAL; 2764 } 2765 2766 if (len == 0) { 2767 RTE_ETHDEV_LOG(ERR, 2768 "Cannot convert link to string with zero size\n"); 2769 return -EINVAL; 2770 } 2771 2772 if (eth_link == NULL) { 2773 RTE_ETHDEV_LOG(ERR, "Cannot convert to string from NULL link\n"); 2774 return -EINVAL; 2775 } 2776 2777 if (eth_link->link_status == ETH_LINK_DOWN) 2778 return snprintf(str, len, "Link down"); 2779 else 2780 return snprintf(str, len, "Link up at %s %s %s", 2781 rte_eth_link_speed_to_str(eth_link->link_speed), 2782 (eth_link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 2783 "FDX" : "HDX", 2784 (eth_link->link_autoneg == ETH_LINK_AUTONEG) ? 2785 "Autoneg" : "Fixed"); 2786 } 2787 2788 int 2789 rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats) 2790 { 2791 struct rte_eth_dev *dev; 2792 2793 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2794 dev = &rte_eth_devices[port_id]; 2795 2796 if (stats == NULL) { 2797 RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u stats to NULL\n", 2798 port_id); 2799 return -EINVAL; 2800 } 2801 2802 memset(stats, 0, sizeof(*stats)); 2803 2804 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP); 2805 stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed; 2806 return eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats)); 2807 } 2808 2809 int 2810 rte_eth_stats_reset(uint16_t port_id) 2811 { 2812 struct rte_eth_dev *dev; 2813 int ret; 2814 2815 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2816 dev = &rte_eth_devices[port_id]; 2817 2818 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_reset, -ENOTSUP); 2819 ret = (*dev->dev_ops->stats_reset)(dev); 2820 if (ret != 0) 2821 return eth_err(port_id, ret); 2822 2823 dev->data->rx_mbuf_alloc_failed = 0; 2824 2825 return 0; 2826 } 2827 2828 static inline int 2829 eth_dev_get_xstats_basic_count(struct rte_eth_dev *dev) 2830 { 2831 uint16_t nb_rxqs, nb_txqs; 2832 int count; 2833 2834 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2835 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2836 2837 count = RTE_NB_STATS; 2838 if (dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) { 2839 count += nb_rxqs * RTE_NB_RXQ_STATS; 2840 count += nb_txqs * RTE_NB_TXQ_STATS; 2841 } 2842 2843 return count; 2844 } 2845 2846 static int 2847 eth_dev_get_xstats_count(uint16_t port_id) 2848 { 2849 struct rte_eth_dev *dev; 2850 int count; 2851 2852 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2853 dev = &rte_eth_devices[port_id]; 2854 if (dev->dev_ops->xstats_get_names != NULL) { 2855 count = (*dev->dev_ops->xstats_get_names)(dev, NULL, 0); 2856 if (count < 0) 2857 return eth_err(port_id, count); 2858 } else 2859 count = 0; 2860 2861 2862 count += eth_dev_get_xstats_basic_count(dev); 2863 2864 return count; 2865 } 2866 2867 int 2868 rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name, 2869 uint64_t *id) 2870 { 2871 int cnt_xstats, idx_xstat; 2872 2873 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2874 2875 if (xstat_name == NULL) { 2876 RTE_ETHDEV_LOG(ERR, 2877 "Cannot get ethdev port %u xstats ID from NULL xstat name\n", 2878 port_id); 2879 return -ENOMEM; 2880 } 2881 2882 if (id == NULL) { 2883 RTE_ETHDEV_LOG(ERR, 2884 "Cannot get ethdev port %u xstats ID to NULL\n", 2885 port_id); 2886 return -ENOMEM; 2887 } 2888 2889 /* Get count */ 2890 cnt_xstats = rte_eth_xstats_get_names_by_id(port_id, NULL, 0, NULL); 2891 if (cnt_xstats < 0) { 2892 RTE_ETHDEV_LOG(ERR, "Cannot get count of xstats\n"); 2893 return -ENODEV; 2894 } 2895 2896 /* Get id-name lookup table */ 2897 struct rte_eth_xstat_name xstats_names[cnt_xstats]; 2898 2899 if (cnt_xstats != rte_eth_xstats_get_names_by_id( 2900 port_id, xstats_names, cnt_xstats, NULL)) { 2901 RTE_ETHDEV_LOG(ERR, "Cannot get xstats lookup\n"); 2902 return -1; 2903 } 2904 2905 for (idx_xstat = 0; idx_xstat < cnt_xstats; idx_xstat++) { 2906 if (!strcmp(xstats_names[idx_xstat].name, xstat_name)) { 2907 *id = idx_xstat; 2908 return 0; 2909 }; 2910 } 2911 2912 return -EINVAL; 2913 } 2914 2915 /* retrieve basic stats names */ 2916 static int 2917 eth_basic_stats_get_names(struct rte_eth_dev *dev, 2918 struct rte_eth_xstat_name *xstats_names) 2919 { 2920 int cnt_used_entries = 0; 2921 uint32_t idx, id_queue; 2922 uint16_t num_q; 2923 2924 for (idx = 0; idx < RTE_NB_STATS; idx++) { 2925 strlcpy(xstats_names[cnt_used_entries].name, 2926 eth_dev_stats_strings[idx].name, 2927 sizeof(xstats_names[0].name)); 2928 cnt_used_entries++; 2929 } 2930 2931 if ((dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) == 0) 2932 return cnt_used_entries; 2933 2934 num_q = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2935 for (id_queue = 0; id_queue < num_q; id_queue++) { 2936 for (idx = 0; idx < RTE_NB_RXQ_STATS; idx++) { 2937 snprintf(xstats_names[cnt_used_entries].name, 2938 sizeof(xstats_names[0].name), 2939 "rx_q%u_%s", 2940 id_queue, eth_dev_rxq_stats_strings[idx].name); 2941 cnt_used_entries++; 2942 } 2943 2944 } 2945 num_q = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2946 for (id_queue = 0; id_queue < num_q; id_queue++) { 2947 for (idx = 0; idx < RTE_NB_TXQ_STATS; idx++) { 2948 snprintf(xstats_names[cnt_used_entries].name, 2949 sizeof(xstats_names[0].name), 2950 "tx_q%u_%s", 2951 id_queue, eth_dev_txq_stats_strings[idx].name); 2952 cnt_used_entries++; 2953 } 2954 } 2955 return cnt_used_entries; 2956 } 2957 2958 /* retrieve ethdev extended statistics names */ 2959 int 2960 rte_eth_xstats_get_names_by_id(uint16_t port_id, 2961 struct rte_eth_xstat_name *xstats_names, unsigned int size, 2962 uint64_t *ids) 2963 { 2964 struct rte_eth_xstat_name *xstats_names_copy; 2965 unsigned int no_basic_stat_requested = 1; 2966 unsigned int no_ext_stat_requested = 1; 2967 unsigned int expected_entries; 2968 unsigned int basic_count; 2969 struct rte_eth_dev *dev; 2970 unsigned int i; 2971 int ret; 2972 2973 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2974 dev = &rte_eth_devices[port_id]; 2975 2976 basic_count = eth_dev_get_xstats_basic_count(dev); 2977 ret = eth_dev_get_xstats_count(port_id); 2978 if (ret < 0) 2979 return ret; 2980 expected_entries = (unsigned int)ret; 2981 2982 /* Return max number of stats if no ids given */ 2983 if (!ids) { 2984 if (!xstats_names) 2985 return expected_entries; 2986 else if (xstats_names && size < expected_entries) 2987 return expected_entries; 2988 } 2989 2990 if (ids && !xstats_names) 2991 return -EINVAL; 2992 2993 if (ids && dev->dev_ops->xstats_get_names_by_id != NULL && size > 0) { 2994 uint64_t ids_copy[size]; 2995 2996 for (i = 0; i < size; i++) { 2997 if (ids[i] < basic_count) { 2998 no_basic_stat_requested = 0; 2999 break; 3000 } 3001 3002 /* 3003 * Convert ids to xstats ids that PMD knows. 3004 * ids known by user are basic + extended stats. 3005 */ 3006 ids_copy[i] = ids[i] - basic_count; 3007 } 3008 3009 if (no_basic_stat_requested) 3010 return (*dev->dev_ops->xstats_get_names_by_id)(dev, 3011 ids_copy, xstats_names, size); 3012 } 3013 3014 /* Retrieve all stats */ 3015 if (!ids) { 3016 int num_stats = rte_eth_xstats_get_names(port_id, xstats_names, 3017 expected_entries); 3018 if (num_stats < 0 || num_stats > (int)expected_entries) 3019 return num_stats; 3020 else 3021 return expected_entries; 3022 } 3023 3024 xstats_names_copy = calloc(expected_entries, 3025 sizeof(struct rte_eth_xstat_name)); 3026 3027 if (!xstats_names_copy) { 3028 RTE_ETHDEV_LOG(ERR, "Can't allocate memory\n"); 3029 return -ENOMEM; 3030 } 3031 3032 if (ids) { 3033 for (i = 0; i < size; i++) { 3034 if (ids[i] >= basic_count) { 3035 no_ext_stat_requested = 0; 3036 break; 3037 } 3038 } 3039 } 3040 3041 /* Fill xstats_names_copy structure */ 3042 if (ids && no_ext_stat_requested) { 3043 eth_basic_stats_get_names(dev, xstats_names_copy); 3044 } else { 3045 ret = rte_eth_xstats_get_names(port_id, xstats_names_copy, 3046 expected_entries); 3047 if (ret < 0) { 3048 free(xstats_names_copy); 3049 return ret; 3050 } 3051 } 3052 3053 /* Filter stats */ 3054 for (i = 0; i < size; i++) { 3055 if (ids[i] >= expected_entries) { 3056 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n"); 3057 free(xstats_names_copy); 3058 return -1; 3059 } 3060 xstats_names[i] = xstats_names_copy[ids[i]]; 3061 } 3062 3063 free(xstats_names_copy); 3064 return size; 3065 } 3066 3067 int 3068 rte_eth_xstats_get_names(uint16_t port_id, 3069 struct rte_eth_xstat_name *xstats_names, 3070 unsigned int size) 3071 { 3072 struct rte_eth_dev *dev; 3073 int cnt_used_entries; 3074 int cnt_expected_entries; 3075 int cnt_driver_entries; 3076 3077 cnt_expected_entries = eth_dev_get_xstats_count(port_id); 3078 if (xstats_names == NULL || cnt_expected_entries < 0 || 3079 (int)size < cnt_expected_entries) 3080 return cnt_expected_entries; 3081 3082 /* port_id checked in eth_dev_get_xstats_count() */ 3083 dev = &rte_eth_devices[port_id]; 3084 3085 cnt_used_entries = eth_basic_stats_get_names(dev, xstats_names); 3086 3087 if (dev->dev_ops->xstats_get_names != NULL) { 3088 /* If there are any driver-specific xstats, append them 3089 * to end of list. 3090 */ 3091 cnt_driver_entries = (*dev->dev_ops->xstats_get_names)( 3092 dev, 3093 xstats_names + cnt_used_entries, 3094 size - cnt_used_entries); 3095 if (cnt_driver_entries < 0) 3096 return eth_err(port_id, cnt_driver_entries); 3097 cnt_used_entries += cnt_driver_entries; 3098 } 3099 3100 return cnt_used_entries; 3101 } 3102 3103 3104 static int 3105 eth_basic_stats_get(uint16_t port_id, struct rte_eth_xstat *xstats) 3106 { 3107 struct rte_eth_dev *dev; 3108 struct rte_eth_stats eth_stats; 3109 unsigned int count = 0, i, q; 3110 uint64_t val, *stats_ptr; 3111 uint16_t nb_rxqs, nb_txqs; 3112 int ret; 3113 3114 ret = rte_eth_stats_get(port_id, ð_stats); 3115 if (ret < 0) 3116 return ret; 3117 3118 dev = &rte_eth_devices[port_id]; 3119 3120 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3121 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3122 3123 /* global stats */ 3124 for (i = 0; i < RTE_NB_STATS; i++) { 3125 stats_ptr = RTE_PTR_ADD(ð_stats, 3126 eth_dev_stats_strings[i].offset); 3127 val = *stats_ptr; 3128 xstats[count++].value = val; 3129 } 3130 3131 if ((dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) == 0) 3132 return count; 3133 3134 /* per-rxq stats */ 3135 for (q = 0; q < nb_rxqs; q++) { 3136 for (i = 0; i < RTE_NB_RXQ_STATS; i++) { 3137 stats_ptr = RTE_PTR_ADD(ð_stats, 3138 eth_dev_rxq_stats_strings[i].offset + 3139 q * sizeof(uint64_t)); 3140 val = *stats_ptr; 3141 xstats[count++].value = val; 3142 } 3143 } 3144 3145 /* per-txq stats */ 3146 for (q = 0; q < nb_txqs; q++) { 3147 for (i = 0; i < RTE_NB_TXQ_STATS; i++) { 3148 stats_ptr = RTE_PTR_ADD(ð_stats, 3149 eth_dev_txq_stats_strings[i].offset + 3150 q * sizeof(uint64_t)); 3151 val = *stats_ptr; 3152 xstats[count++].value = val; 3153 } 3154 } 3155 return count; 3156 } 3157 3158 /* retrieve ethdev extended statistics */ 3159 int 3160 rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids, 3161 uint64_t *values, unsigned int size) 3162 { 3163 unsigned int no_basic_stat_requested = 1; 3164 unsigned int no_ext_stat_requested = 1; 3165 unsigned int num_xstats_filled; 3166 unsigned int basic_count; 3167 uint16_t expected_entries; 3168 struct rte_eth_dev *dev; 3169 unsigned int i; 3170 int ret; 3171 3172 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3173 dev = &rte_eth_devices[port_id]; 3174 3175 ret = eth_dev_get_xstats_count(port_id); 3176 if (ret < 0) 3177 return ret; 3178 expected_entries = (uint16_t)ret; 3179 struct rte_eth_xstat xstats[expected_entries]; 3180 basic_count = eth_dev_get_xstats_basic_count(dev); 3181 3182 /* Return max number of stats if no ids given */ 3183 if (!ids) { 3184 if (!values) 3185 return expected_entries; 3186 else if (values && size < expected_entries) 3187 return expected_entries; 3188 } 3189 3190 if (ids && !values) 3191 return -EINVAL; 3192 3193 if (ids && dev->dev_ops->xstats_get_by_id != NULL && size) { 3194 unsigned int basic_count = eth_dev_get_xstats_basic_count(dev); 3195 uint64_t ids_copy[size]; 3196 3197 for (i = 0; i < size; i++) { 3198 if (ids[i] < basic_count) { 3199 no_basic_stat_requested = 0; 3200 break; 3201 } 3202 3203 /* 3204 * Convert ids to xstats ids that PMD knows. 3205 * ids known by user are basic + extended stats. 3206 */ 3207 ids_copy[i] = ids[i] - basic_count; 3208 } 3209 3210 if (no_basic_stat_requested) 3211 return (*dev->dev_ops->xstats_get_by_id)(dev, ids_copy, 3212 values, size); 3213 } 3214 3215 if (ids) { 3216 for (i = 0; i < size; i++) { 3217 if (ids[i] >= basic_count) { 3218 no_ext_stat_requested = 0; 3219 break; 3220 } 3221 } 3222 } 3223 3224 /* Fill the xstats structure */ 3225 if (ids && no_ext_stat_requested) 3226 ret = eth_basic_stats_get(port_id, xstats); 3227 else 3228 ret = rte_eth_xstats_get(port_id, xstats, expected_entries); 3229 3230 if (ret < 0) 3231 return ret; 3232 num_xstats_filled = (unsigned int)ret; 3233 3234 /* Return all stats */ 3235 if (!ids) { 3236 for (i = 0; i < num_xstats_filled; i++) 3237 values[i] = xstats[i].value; 3238 return expected_entries; 3239 } 3240 3241 /* Filter stats */ 3242 for (i = 0; i < size; i++) { 3243 if (ids[i] >= expected_entries) { 3244 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n"); 3245 return -1; 3246 } 3247 values[i] = xstats[ids[i]].value; 3248 } 3249 return size; 3250 } 3251 3252 int 3253 rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats, 3254 unsigned int n) 3255 { 3256 struct rte_eth_dev *dev; 3257 unsigned int count = 0, i; 3258 signed int xcount = 0; 3259 uint16_t nb_rxqs, nb_txqs; 3260 int ret; 3261 3262 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3263 dev = &rte_eth_devices[port_id]; 3264 3265 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3266 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 3267 3268 /* Return generic statistics */ 3269 count = RTE_NB_STATS; 3270 if (dev->data->dev_flags & RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS) 3271 count += (nb_rxqs * RTE_NB_RXQ_STATS) + (nb_txqs * RTE_NB_TXQ_STATS); 3272 3273 /* implemented by the driver */ 3274 if (dev->dev_ops->xstats_get != NULL) { 3275 /* Retrieve the xstats from the driver at the end of the 3276 * xstats struct. 3277 */ 3278 xcount = (*dev->dev_ops->xstats_get)(dev, 3279 xstats ? xstats + count : NULL, 3280 (n > count) ? n - count : 0); 3281 3282 if (xcount < 0) 3283 return eth_err(port_id, xcount); 3284 } 3285 3286 if (n < count + xcount || xstats == NULL) 3287 return count + xcount; 3288 3289 /* now fill the xstats structure */ 3290 ret = eth_basic_stats_get(port_id, xstats); 3291 if (ret < 0) 3292 return ret; 3293 count = ret; 3294 3295 for (i = 0; i < count; i++) 3296 xstats[i].id = i; 3297 /* add an offset to driver-specific stats */ 3298 for ( ; i < count + xcount; i++) 3299 xstats[i].id += count; 3300 3301 return count + xcount; 3302 } 3303 3304 /* reset ethdev extended statistics */ 3305 int 3306 rte_eth_xstats_reset(uint16_t port_id) 3307 { 3308 struct rte_eth_dev *dev; 3309 3310 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3311 dev = &rte_eth_devices[port_id]; 3312 3313 /* implemented by the driver */ 3314 if (dev->dev_ops->xstats_reset != NULL) 3315 return eth_err(port_id, (*dev->dev_ops->xstats_reset)(dev)); 3316 3317 /* fallback to default */ 3318 return rte_eth_stats_reset(port_id); 3319 } 3320 3321 static int 3322 eth_dev_set_queue_stats_mapping(uint16_t port_id, uint16_t queue_id, 3323 uint8_t stat_idx, uint8_t is_rx) 3324 { 3325 struct rte_eth_dev *dev; 3326 3327 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3328 dev = &rte_eth_devices[port_id]; 3329 3330 if (is_rx && (queue_id >= dev->data->nb_rx_queues)) 3331 return -EINVAL; 3332 3333 if (!is_rx && (queue_id >= dev->data->nb_tx_queues)) 3334 return -EINVAL; 3335 3336 if (stat_idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 3337 return -EINVAL; 3338 3339 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->queue_stats_mapping_set, -ENOTSUP); 3340 return (*dev->dev_ops->queue_stats_mapping_set) (dev, queue_id, stat_idx, is_rx); 3341 } 3342 3343 int 3344 rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id, uint16_t tx_queue_id, 3345 uint8_t stat_idx) 3346 { 3347 return eth_err(port_id, eth_dev_set_queue_stats_mapping(port_id, 3348 tx_queue_id, 3349 stat_idx, STAT_QMAP_TX)); 3350 } 3351 3352 int 3353 rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id, uint16_t rx_queue_id, 3354 uint8_t stat_idx) 3355 { 3356 return eth_err(port_id, eth_dev_set_queue_stats_mapping(port_id, 3357 rx_queue_id, 3358 stat_idx, STAT_QMAP_RX)); 3359 } 3360 3361 int 3362 rte_eth_dev_fw_version_get(uint16_t port_id, char *fw_version, size_t fw_size) 3363 { 3364 struct rte_eth_dev *dev; 3365 3366 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3367 dev = &rte_eth_devices[port_id]; 3368 3369 if (fw_version == NULL && fw_size > 0) { 3370 RTE_ETHDEV_LOG(ERR, 3371 "Cannot get ethdev port %u FW version to NULL when string size is non zero\n", 3372 port_id); 3373 return -EINVAL; 3374 } 3375 3376 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fw_version_get, -ENOTSUP); 3377 return eth_err(port_id, (*dev->dev_ops->fw_version_get)(dev, 3378 fw_version, fw_size)); 3379 } 3380 3381 int 3382 rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info) 3383 { 3384 struct rte_eth_dev *dev; 3385 const struct rte_eth_desc_lim lim = { 3386 .nb_max = UINT16_MAX, 3387 .nb_min = 0, 3388 .nb_align = 1, 3389 .nb_seg_max = UINT16_MAX, 3390 .nb_mtu_seg_max = UINT16_MAX, 3391 }; 3392 int diag; 3393 3394 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3395 dev = &rte_eth_devices[port_id]; 3396 3397 if (dev_info == NULL) { 3398 RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u info to NULL\n", 3399 port_id); 3400 return -EINVAL; 3401 } 3402 3403 /* 3404 * Init dev_info before port_id check since caller does not have 3405 * return status and does not know if get is successful or not. 3406 */ 3407 memset(dev_info, 0, sizeof(struct rte_eth_dev_info)); 3408 dev_info->switch_info.domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 3409 3410 dev_info->rx_desc_lim = lim; 3411 dev_info->tx_desc_lim = lim; 3412 dev_info->device = dev->device; 3413 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 3414 dev_info->max_mtu = UINT16_MAX; 3415 3416 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP); 3417 diag = (*dev->dev_ops->dev_infos_get)(dev, dev_info); 3418 if (diag != 0) { 3419 /* Cleanup already filled in device information */ 3420 memset(dev_info, 0, sizeof(struct rte_eth_dev_info)); 3421 return eth_err(port_id, diag); 3422 } 3423 3424 /* Maximum number of queues should be <= RTE_MAX_QUEUES_PER_PORT */ 3425 dev_info->max_rx_queues = RTE_MIN(dev_info->max_rx_queues, 3426 RTE_MAX_QUEUES_PER_PORT); 3427 dev_info->max_tx_queues = RTE_MIN(dev_info->max_tx_queues, 3428 RTE_MAX_QUEUES_PER_PORT); 3429 3430 dev_info->driver_name = dev->device->driver->name; 3431 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 3432 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 3433 3434 dev_info->dev_flags = &dev->data->dev_flags; 3435 3436 return 0; 3437 } 3438 3439 int 3440 rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask, 3441 uint32_t *ptypes, int num) 3442 { 3443 int i, j; 3444 struct rte_eth_dev *dev; 3445 const uint32_t *all_ptypes; 3446 3447 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3448 dev = &rte_eth_devices[port_id]; 3449 3450 if (ptypes == NULL && num > 0) { 3451 RTE_ETHDEV_LOG(ERR, 3452 "Cannot get ethdev port %u supported packet types to NULL when array size is non zero\n", 3453 port_id); 3454 return -EINVAL; 3455 } 3456 3457 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_supported_ptypes_get, 0); 3458 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev); 3459 3460 if (!all_ptypes) 3461 return 0; 3462 3463 for (i = 0, j = 0; all_ptypes[i] != RTE_PTYPE_UNKNOWN; ++i) 3464 if (all_ptypes[i] & ptype_mask) { 3465 if (j < num) 3466 ptypes[j] = all_ptypes[i]; 3467 j++; 3468 } 3469 3470 return j; 3471 } 3472 3473 int 3474 rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask, 3475 uint32_t *set_ptypes, unsigned int num) 3476 { 3477 const uint32_t valid_ptype_masks[] = { 3478 RTE_PTYPE_L2_MASK, 3479 RTE_PTYPE_L3_MASK, 3480 RTE_PTYPE_L4_MASK, 3481 RTE_PTYPE_TUNNEL_MASK, 3482 RTE_PTYPE_INNER_L2_MASK, 3483 RTE_PTYPE_INNER_L3_MASK, 3484 RTE_PTYPE_INNER_L4_MASK, 3485 }; 3486 const uint32_t *all_ptypes; 3487 struct rte_eth_dev *dev; 3488 uint32_t unused_mask; 3489 unsigned int i, j; 3490 int ret; 3491 3492 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3493 dev = &rte_eth_devices[port_id]; 3494 3495 if (num > 0 && set_ptypes == NULL) { 3496 RTE_ETHDEV_LOG(ERR, 3497 "Cannot get ethdev port %u set packet types to NULL when array size is non zero\n", 3498 port_id); 3499 return -EINVAL; 3500 } 3501 3502 if (*dev->dev_ops->dev_supported_ptypes_get == NULL || 3503 *dev->dev_ops->dev_ptypes_set == NULL) { 3504 ret = 0; 3505 goto ptype_unknown; 3506 } 3507 3508 if (ptype_mask == 0) { 3509 ret = (*dev->dev_ops->dev_ptypes_set)(dev, 3510 ptype_mask); 3511 goto ptype_unknown; 3512 } 3513 3514 unused_mask = ptype_mask; 3515 for (i = 0; i < RTE_DIM(valid_ptype_masks); i++) { 3516 uint32_t mask = ptype_mask & valid_ptype_masks[i]; 3517 if (mask && mask != valid_ptype_masks[i]) { 3518 ret = -EINVAL; 3519 goto ptype_unknown; 3520 } 3521 unused_mask &= ~valid_ptype_masks[i]; 3522 } 3523 3524 if (unused_mask) { 3525 ret = -EINVAL; 3526 goto ptype_unknown; 3527 } 3528 3529 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev); 3530 if (all_ptypes == NULL) { 3531 ret = 0; 3532 goto ptype_unknown; 3533 } 3534 3535 /* 3536 * Accommodate as many set_ptypes as possible. If the supplied 3537 * set_ptypes array is insufficient fill it partially. 3538 */ 3539 for (i = 0, j = 0; set_ptypes != NULL && 3540 (all_ptypes[i] != RTE_PTYPE_UNKNOWN); ++i) { 3541 if (ptype_mask & all_ptypes[i]) { 3542 if (j < num - 1) { 3543 set_ptypes[j] = all_ptypes[i]; 3544 j++; 3545 continue; 3546 } 3547 break; 3548 } 3549 } 3550 3551 if (set_ptypes != NULL && j < num) 3552 set_ptypes[j] = RTE_PTYPE_UNKNOWN; 3553 3554 return (*dev->dev_ops->dev_ptypes_set)(dev, ptype_mask); 3555 3556 ptype_unknown: 3557 if (num > 0) 3558 set_ptypes[0] = RTE_PTYPE_UNKNOWN; 3559 3560 return ret; 3561 } 3562 3563 int 3564 rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr) 3565 { 3566 struct rte_eth_dev *dev; 3567 3568 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3569 dev = &rte_eth_devices[port_id]; 3570 3571 if (mac_addr == NULL) { 3572 RTE_ETHDEV_LOG(ERR, 3573 "Cannot get ethdev port %u MAC address to NULL\n", 3574 port_id); 3575 return -EINVAL; 3576 } 3577 3578 rte_ether_addr_copy(&dev->data->mac_addrs[0], mac_addr); 3579 3580 return 0; 3581 } 3582 3583 int 3584 rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu) 3585 { 3586 struct rte_eth_dev *dev; 3587 3588 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3589 dev = &rte_eth_devices[port_id]; 3590 3591 if (mtu == NULL) { 3592 RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u MTU to NULL\n", 3593 port_id); 3594 return -EINVAL; 3595 } 3596 3597 *mtu = dev->data->mtu; 3598 return 0; 3599 } 3600 3601 int 3602 rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu) 3603 { 3604 int ret; 3605 struct rte_eth_dev_info dev_info; 3606 struct rte_eth_dev *dev; 3607 3608 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3609 dev = &rte_eth_devices[port_id]; 3610 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mtu_set, -ENOTSUP); 3611 3612 /* 3613 * Check if the device supports dev_infos_get, if it does not 3614 * skip min_mtu/max_mtu validation here as this requires values 3615 * that are populated within the call to rte_eth_dev_info_get() 3616 * which relies on dev->dev_ops->dev_infos_get. 3617 */ 3618 if (*dev->dev_ops->dev_infos_get != NULL) { 3619 ret = rte_eth_dev_info_get(port_id, &dev_info); 3620 if (ret != 0) 3621 return ret; 3622 3623 if (mtu < dev_info.min_mtu || mtu > dev_info.max_mtu) 3624 return -EINVAL; 3625 } 3626 3627 ret = (*dev->dev_ops->mtu_set)(dev, mtu); 3628 if (!ret) 3629 dev->data->mtu = mtu; 3630 3631 return eth_err(port_id, ret); 3632 } 3633 3634 int 3635 rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on) 3636 { 3637 struct rte_eth_dev *dev; 3638 int ret; 3639 3640 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3641 dev = &rte_eth_devices[port_id]; 3642 3643 if (!(dev->data->dev_conf.rxmode.offloads & 3644 DEV_RX_OFFLOAD_VLAN_FILTER)) { 3645 RTE_ETHDEV_LOG(ERR, "Port %u: vlan-filtering disabled\n", 3646 port_id); 3647 return -ENOSYS; 3648 } 3649 3650 if (vlan_id > 4095) { 3651 RTE_ETHDEV_LOG(ERR, "Port_id=%u invalid vlan_id=%u > 4095\n", 3652 port_id, vlan_id); 3653 return -EINVAL; 3654 } 3655 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_filter_set, -ENOTSUP); 3656 3657 ret = (*dev->dev_ops->vlan_filter_set)(dev, vlan_id, on); 3658 if (ret == 0) { 3659 struct rte_vlan_filter_conf *vfc; 3660 int vidx; 3661 int vbit; 3662 3663 vfc = &dev->data->vlan_filter_conf; 3664 vidx = vlan_id / 64; 3665 vbit = vlan_id % 64; 3666 3667 if (on) 3668 vfc->ids[vidx] |= UINT64_C(1) << vbit; 3669 else 3670 vfc->ids[vidx] &= ~(UINT64_C(1) << vbit); 3671 } 3672 3673 return eth_err(port_id, ret); 3674 } 3675 3676 int 3677 rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id, 3678 int on) 3679 { 3680 struct rte_eth_dev *dev; 3681 3682 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3683 dev = &rte_eth_devices[port_id]; 3684 3685 if (rx_queue_id >= dev->data->nb_rx_queues) { 3686 RTE_ETHDEV_LOG(ERR, "Invalid rx_queue_id=%u\n", rx_queue_id); 3687 return -EINVAL; 3688 } 3689 3690 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP); 3691 (*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on); 3692 3693 return 0; 3694 } 3695 3696 int 3697 rte_eth_dev_set_vlan_ether_type(uint16_t port_id, 3698 enum rte_vlan_type vlan_type, 3699 uint16_t tpid) 3700 { 3701 struct rte_eth_dev *dev; 3702 3703 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3704 dev = &rte_eth_devices[port_id]; 3705 3706 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_tpid_set, -ENOTSUP); 3707 return eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type, 3708 tpid)); 3709 } 3710 3711 int 3712 rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask) 3713 { 3714 struct rte_eth_dev_info dev_info; 3715 struct rte_eth_dev *dev; 3716 int ret = 0; 3717 int mask = 0; 3718 int cur, org = 0; 3719 uint64_t orig_offloads; 3720 uint64_t dev_offloads; 3721 uint64_t new_offloads; 3722 3723 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3724 dev = &rte_eth_devices[port_id]; 3725 3726 /* save original values in case of failure */ 3727 orig_offloads = dev->data->dev_conf.rxmode.offloads; 3728 dev_offloads = orig_offloads; 3729 3730 /* check which option changed by application */ 3731 cur = !!(offload_mask & ETH_VLAN_STRIP_OFFLOAD); 3732 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 3733 if (cur != org) { 3734 if (cur) 3735 dev_offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 3736 else 3737 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 3738 mask |= ETH_VLAN_STRIP_MASK; 3739 } 3740 3741 cur = !!(offload_mask & ETH_VLAN_FILTER_OFFLOAD); 3742 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER); 3743 if (cur != org) { 3744 if (cur) 3745 dev_offloads |= DEV_RX_OFFLOAD_VLAN_FILTER; 3746 else 3747 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_FILTER; 3748 mask |= ETH_VLAN_FILTER_MASK; 3749 } 3750 3751 cur = !!(offload_mask & ETH_VLAN_EXTEND_OFFLOAD); 3752 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND); 3753 if (cur != org) { 3754 if (cur) 3755 dev_offloads |= DEV_RX_OFFLOAD_VLAN_EXTEND; 3756 else 3757 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_EXTEND; 3758 mask |= ETH_VLAN_EXTEND_MASK; 3759 } 3760 3761 cur = !!(offload_mask & ETH_QINQ_STRIP_OFFLOAD); 3762 org = !!(dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP); 3763 if (cur != org) { 3764 if (cur) 3765 dev_offloads |= DEV_RX_OFFLOAD_QINQ_STRIP; 3766 else 3767 dev_offloads &= ~DEV_RX_OFFLOAD_QINQ_STRIP; 3768 mask |= ETH_QINQ_STRIP_MASK; 3769 } 3770 3771 /*no change*/ 3772 if (mask == 0) 3773 return ret; 3774 3775 ret = rte_eth_dev_info_get(port_id, &dev_info); 3776 if (ret != 0) 3777 return ret; 3778 3779 /* Rx VLAN offloading must be within its device capabilities */ 3780 if ((dev_offloads & dev_info.rx_offload_capa) != dev_offloads) { 3781 new_offloads = dev_offloads & ~orig_offloads; 3782 RTE_ETHDEV_LOG(ERR, 3783 "Ethdev port_id=%u requested new added VLAN offloads " 3784 "0x%" PRIx64 " must be within Rx offloads capabilities " 3785 "0x%" PRIx64 " in %s()\n", 3786 port_id, new_offloads, dev_info.rx_offload_capa, 3787 __func__); 3788 return -EINVAL; 3789 } 3790 3791 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_offload_set, -ENOTSUP); 3792 dev->data->dev_conf.rxmode.offloads = dev_offloads; 3793 ret = (*dev->dev_ops->vlan_offload_set)(dev, mask); 3794 if (ret) { 3795 /* hit an error restore original values */ 3796 dev->data->dev_conf.rxmode.offloads = orig_offloads; 3797 } 3798 3799 return eth_err(port_id, ret); 3800 } 3801 3802 int 3803 rte_eth_dev_get_vlan_offload(uint16_t port_id) 3804 { 3805 struct rte_eth_dev *dev; 3806 uint64_t *dev_offloads; 3807 int ret = 0; 3808 3809 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3810 dev = &rte_eth_devices[port_id]; 3811 dev_offloads = &dev->data->dev_conf.rxmode.offloads; 3812 3813 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 3814 ret |= ETH_VLAN_STRIP_OFFLOAD; 3815 3816 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 3817 ret |= ETH_VLAN_FILTER_OFFLOAD; 3818 3819 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 3820 ret |= ETH_VLAN_EXTEND_OFFLOAD; 3821 3822 if (*dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP) 3823 ret |= ETH_QINQ_STRIP_OFFLOAD; 3824 3825 return ret; 3826 } 3827 3828 int 3829 rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on) 3830 { 3831 struct rte_eth_dev *dev; 3832 3833 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3834 dev = &rte_eth_devices[port_id]; 3835 3836 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_pvid_set, -ENOTSUP); 3837 return eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on)); 3838 } 3839 3840 int 3841 rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf) 3842 { 3843 struct rte_eth_dev *dev; 3844 3845 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3846 dev = &rte_eth_devices[port_id]; 3847 3848 if (fc_conf == NULL) { 3849 RTE_ETHDEV_LOG(ERR, 3850 "Cannot get ethdev port %u flow control config to NULL\n", 3851 port_id); 3852 return -EINVAL; 3853 } 3854 3855 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_get, -ENOTSUP); 3856 memset(fc_conf, 0, sizeof(*fc_conf)); 3857 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf)); 3858 } 3859 3860 int 3861 rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf) 3862 { 3863 struct rte_eth_dev *dev; 3864 3865 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3866 dev = &rte_eth_devices[port_id]; 3867 3868 if (fc_conf == NULL) { 3869 RTE_ETHDEV_LOG(ERR, 3870 "Cannot set ethdev port %u flow control from NULL config\n", 3871 port_id); 3872 return -EINVAL; 3873 } 3874 3875 if ((fc_conf->send_xon != 0) && (fc_conf->send_xon != 1)) { 3876 RTE_ETHDEV_LOG(ERR, "Invalid send_xon, only 0/1 allowed\n"); 3877 return -EINVAL; 3878 } 3879 3880 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_set, -ENOTSUP); 3881 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf)); 3882 } 3883 3884 int 3885 rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id, 3886 struct rte_eth_pfc_conf *pfc_conf) 3887 { 3888 struct rte_eth_dev *dev; 3889 3890 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3891 dev = &rte_eth_devices[port_id]; 3892 3893 if (pfc_conf == NULL) { 3894 RTE_ETHDEV_LOG(ERR, 3895 "Cannot set ethdev port %u priority flow control from NULL config\n", 3896 port_id); 3897 return -EINVAL; 3898 } 3899 3900 if (pfc_conf->priority > (ETH_DCB_NUM_USER_PRIORITIES - 1)) { 3901 RTE_ETHDEV_LOG(ERR, "Invalid priority, only 0-7 allowed\n"); 3902 return -EINVAL; 3903 } 3904 3905 /* High water, low water validation are device specific */ 3906 if (*dev->dev_ops->priority_flow_ctrl_set) 3907 return eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set) 3908 (dev, pfc_conf)); 3909 return -ENOTSUP; 3910 } 3911 3912 static int 3913 eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf, 3914 uint16_t reta_size) 3915 { 3916 uint16_t i, num; 3917 3918 num = (reta_size + RTE_RETA_GROUP_SIZE - 1) / RTE_RETA_GROUP_SIZE; 3919 for (i = 0; i < num; i++) { 3920 if (reta_conf[i].mask) 3921 return 0; 3922 } 3923 3924 return -EINVAL; 3925 } 3926 3927 static int 3928 eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf, 3929 uint16_t reta_size, 3930 uint16_t max_rxq) 3931 { 3932 uint16_t i, idx, shift; 3933 3934 if (max_rxq == 0) { 3935 RTE_ETHDEV_LOG(ERR, "No receive queue is available\n"); 3936 return -EINVAL; 3937 } 3938 3939 for (i = 0; i < reta_size; i++) { 3940 idx = i / RTE_RETA_GROUP_SIZE; 3941 shift = i % RTE_RETA_GROUP_SIZE; 3942 if ((reta_conf[idx].mask & (1ULL << shift)) && 3943 (reta_conf[idx].reta[shift] >= max_rxq)) { 3944 RTE_ETHDEV_LOG(ERR, 3945 "reta_conf[%u]->reta[%u]: %u exceeds the maximum rxq index: %u\n", 3946 idx, shift, 3947 reta_conf[idx].reta[shift], max_rxq); 3948 return -EINVAL; 3949 } 3950 } 3951 3952 return 0; 3953 } 3954 3955 int 3956 rte_eth_dev_rss_reta_update(uint16_t port_id, 3957 struct rte_eth_rss_reta_entry64 *reta_conf, 3958 uint16_t reta_size) 3959 { 3960 struct rte_eth_dev *dev; 3961 int ret; 3962 3963 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3964 dev = &rte_eth_devices[port_id]; 3965 3966 if (reta_conf == NULL) { 3967 RTE_ETHDEV_LOG(ERR, 3968 "Cannot update ethdev port %u RSS RETA to NULL\n", 3969 port_id); 3970 return -EINVAL; 3971 } 3972 3973 if (reta_size == 0) { 3974 RTE_ETHDEV_LOG(ERR, 3975 "Cannot update ethdev port %u RSS RETA with zero size\n", 3976 port_id); 3977 return -EINVAL; 3978 } 3979 3980 /* Check mask bits */ 3981 ret = eth_check_reta_mask(reta_conf, reta_size); 3982 if (ret < 0) 3983 return ret; 3984 3985 /* Check entry value */ 3986 ret = eth_check_reta_entry(reta_conf, reta_size, 3987 dev->data->nb_rx_queues); 3988 if (ret < 0) 3989 return ret; 3990 3991 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_update, -ENOTSUP); 3992 return eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf, 3993 reta_size)); 3994 } 3995 3996 int 3997 rte_eth_dev_rss_reta_query(uint16_t port_id, 3998 struct rte_eth_rss_reta_entry64 *reta_conf, 3999 uint16_t reta_size) 4000 { 4001 struct rte_eth_dev *dev; 4002 int ret; 4003 4004 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4005 dev = &rte_eth_devices[port_id]; 4006 4007 if (reta_conf == NULL) { 4008 RTE_ETHDEV_LOG(ERR, 4009 "Cannot query ethdev port %u RSS RETA from NULL config\n", 4010 port_id); 4011 return -EINVAL; 4012 } 4013 4014 /* Check mask bits */ 4015 ret = eth_check_reta_mask(reta_conf, reta_size); 4016 if (ret < 0) 4017 return ret; 4018 4019 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_query, -ENOTSUP); 4020 return eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf, 4021 reta_size)); 4022 } 4023 4024 int 4025 rte_eth_dev_rss_hash_update(uint16_t port_id, 4026 struct rte_eth_rss_conf *rss_conf) 4027 { 4028 struct rte_eth_dev *dev; 4029 struct rte_eth_dev_info dev_info = { .flow_type_rss_offloads = 0, }; 4030 int ret; 4031 4032 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4033 dev = &rte_eth_devices[port_id]; 4034 4035 if (rss_conf == NULL) { 4036 RTE_ETHDEV_LOG(ERR, 4037 "Cannot update ethdev port %u RSS hash from NULL config\n", 4038 port_id); 4039 return -EINVAL; 4040 } 4041 4042 ret = rte_eth_dev_info_get(port_id, &dev_info); 4043 if (ret != 0) 4044 return ret; 4045 4046 rss_conf->rss_hf = rte_eth_rss_hf_refine(rss_conf->rss_hf); 4047 if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) != 4048 dev_info.flow_type_rss_offloads) { 4049 RTE_ETHDEV_LOG(ERR, 4050 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n", 4051 port_id, rss_conf->rss_hf, 4052 dev_info.flow_type_rss_offloads); 4053 return -EINVAL; 4054 } 4055 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_update, -ENOTSUP); 4056 return eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev, 4057 rss_conf)); 4058 } 4059 4060 int 4061 rte_eth_dev_rss_hash_conf_get(uint16_t port_id, 4062 struct rte_eth_rss_conf *rss_conf) 4063 { 4064 struct rte_eth_dev *dev; 4065 4066 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4067 dev = &rte_eth_devices[port_id]; 4068 4069 if (rss_conf == NULL) { 4070 RTE_ETHDEV_LOG(ERR, 4071 "Cannot get ethdev port %u RSS hash config to NULL\n", 4072 port_id); 4073 return -EINVAL; 4074 } 4075 4076 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_conf_get, -ENOTSUP); 4077 return eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev, 4078 rss_conf)); 4079 } 4080 4081 int 4082 rte_eth_dev_udp_tunnel_port_add(uint16_t port_id, 4083 struct rte_eth_udp_tunnel *udp_tunnel) 4084 { 4085 struct rte_eth_dev *dev; 4086 4087 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4088 dev = &rte_eth_devices[port_id]; 4089 4090 if (udp_tunnel == NULL) { 4091 RTE_ETHDEV_LOG(ERR, 4092 "Cannot add ethdev port %u UDP tunnel port from NULL UDP tunnel\n", 4093 port_id); 4094 return -EINVAL; 4095 } 4096 4097 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) { 4098 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 4099 return -EINVAL; 4100 } 4101 4102 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_add, -ENOTSUP); 4103 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev, 4104 udp_tunnel)); 4105 } 4106 4107 int 4108 rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id, 4109 struct rte_eth_udp_tunnel *udp_tunnel) 4110 { 4111 struct rte_eth_dev *dev; 4112 4113 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4114 dev = &rte_eth_devices[port_id]; 4115 4116 if (udp_tunnel == NULL) { 4117 RTE_ETHDEV_LOG(ERR, 4118 "Cannot delete ethdev port %u UDP tunnel port from NULL UDP tunnel\n", 4119 port_id); 4120 return -EINVAL; 4121 } 4122 4123 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) { 4124 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 4125 return -EINVAL; 4126 } 4127 4128 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_del, -ENOTSUP); 4129 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev, 4130 udp_tunnel)); 4131 } 4132 4133 int 4134 rte_eth_led_on(uint16_t port_id) 4135 { 4136 struct rte_eth_dev *dev; 4137 4138 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4139 dev = &rte_eth_devices[port_id]; 4140 4141 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_on, -ENOTSUP); 4142 return eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev)); 4143 } 4144 4145 int 4146 rte_eth_led_off(uint16_t port_id) 4147 { 4148 struct rte_eth_dev *dev; 4149 4150 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4151 dev = &rte_eth_devices[port_id]; 4152 4153 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_off, -ENOTSUP); 4154 return eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev)); 4155 } 4156 4157 int 4158 rte_eth_fec_get_capability(uint16_t port_id, 4159 struct rte_eth_fec_capa *speed_fec_capa, 4160 unsigned int num) 4161 { 4162 struct rte_eth_dev *dev; 4163 int ret; 4164 4165 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4166 dev = &rte_eth_devices[port_id]; 4167 4168 if (speed_fec_capa == NULL && num > 0) { 4169 RTE_ETHDEV_LOG(ERR, 4170 "Cannot get ethdev port %u FEC capability to NULL when array size is non zero\n", 4171 port_id); 4172 return -EINVAL; 4173 } 4174 4175 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_get_capability, -ENOTSUP); 4176 ret = (*dev->dev_ops->fec_get_capability)(dev, speed_fec_capa, num); 4177 4178 return ret; 4179 } 4180 4181 int 4182 rte_eth_fec_get(uint16_t port_id, uint32_t *fec_capa) 4183 { 4184 struct rte_eth_dev *dev; 4185 4186 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4187 dev = &rte_eth_devices[port_id]; 4188 4189 if (fec_capa == NULL) { 4190 RTE_ETHDEV_LOG(ERR, 4191 "Cannot get ethdev port %u current FEC mode to NULL\n", 4192 port_id); 4193 return -EINVAL; 4194 } 4195 4196 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_get, -ENOTSUP); 4197 return eth_err(port_id, (*dev->dev_ops->fec_get)(dev, fec_capa)); 4198 } 4199 4200 int 4201 rte_eth_fec_set(uint16_t port_id, uint32_t fec_capa) 4202 { 4203 struct rte_eth_dev *dev; 4204 4205 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4206 dev = &rte_eth_devices[port_id]; 4207 4208 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fec_set, -ENOTSUP); 4209 return eth_err(port_id, (*dev->dev_ops->fec_set)(dev, fec_capa)); 4210 } 4211 4212 /* 4213 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find 4214 * an empty spot. 4215 */ 4216 static int 4217 eth_dev_get_mac_addr_index(uint16_t port_id, const struct rte_ether_addr *addr) 4218 { 4219 struct rte_eth_dev_info dev_info; 4220 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 4221 unsigned i; 4222 int ret; 4223 4224 ret = rte_eth_dev_info_get(port_id, &dev_info); 4225 if (ret != 0) 4226 return -1; 4227 4228 for (i = 0; i < dev_info.max_mac_addrs; i++) 4229 if (memcmp(addr, &dev->data->mac_addrs[i], 4230 RTE_ETHER_ADDR_LEN) == 0) 4231 return i; 4232 4233 return -1; 4234 } 4235 4236 static const struct rte_ether_addr null_mac_addr; 4237 4238 int 4239 rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr, 4240 uint32_t pool) 4241 { 4242 struct rte_eth_dev *dev; 4243 int index; 4244 uint64_t pool_mask; 4245 int ret; 4246 4247 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4248 dev = &rte_eth_devices[port_id]; 4249 4250 if (addr == NULL) { 4251 RTE_ETHDEV_LOG(ERR, 4252 "Cannot add ethdev port %u MAC address from NULL address\n", 4253 port_id); 4254 return -EINVAL; 4255 } 4256 4257 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_add, -ENOTSUP); 4258 4259 if (rte_is_zero_ether_addr(addr)) { 4260 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n", 4261 port_id); 4262 return -EINVAL; 4263 } 4264 if (pool >= ETH_64_POOLS) { 4265 RTE_ETHDEV_LOG(ERR, "Pool id must be 0-%d\n", ETH_64_POOLS - 1); 4266 return -EINVAL; 4267 } 4268 4269 index = eth_dev_get_mac_addr_index(port_id, addr); 4270 if (index < 0) { 4271 index = eth_dev_get_mac_addr_index(port_id, &null_mac_addr); 4272 if (index < 0) { 4273 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n", 4274 port_id); 4275 return -ENOSPC; 4276 } 4277 } else { 4278 pool_mask = dev->data->mac_pool_sel[index]; 4279 4280 /* Check if both MAC address and pool is already there, and do nothing */ 4281 if (pool_mask & (1ULL << pool)) 4282 return 0; 4283 } 4284 4285 /* Update NIC */ 4286 ret = (*dev->dev_ops->mac_addr_add)(dev, addr, index, pool); 4287 4288 if (ret == 0) { 4289 /* Update address in NIC data structure */ 4290 rte_ether_addr_copy(addr, &dev->data->mac_addrs[index]); 4291 4292 /* Update pool bitmap in NIC data structure */ 4293 dev->data->mac_pool_sel[index] |= (1ULL << pool); 4294 } 4295 4296 return eth_err(port_id, ret); 4297 } 4298 4299 int 4300 rte_eth_dev_mac_addr_remove(uint16_t port_id, struct rte_ether_addr *addr) 4301 { 4302 struct rte_eth_dev *dev; 4303 int index; 4304 4305 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4306 dev = &rte_eth_devices[port_id]; 4307 4308 if (addr == NULL) { 4309 RTE_ETHDEV_LOG(ERR, 4310 "Cannot remove ethdev port %u MAC address from NULL address\n", 4311 port_id); 4312 return -EINVAL; 4313 } 4314 4315 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_remove, -ENOTSUP); 4316 4317 index = eth_dev_get_mac_addr_index(port_id, addr); 4318 if (index == 0) { 4319 RTE_ETHDEV_LOG(ERR, 4320 "Port %u: Cannot remove default MAC address\n", 4321 port_id); 4322 return -EADDRINUSE; 4323 } else if (index < 0) 4324 return 0; /* Do nothing if address wasn't found */ 4325 4326 /* Update NIC */ 4327 (*dev->dev_ops->mac_addr_remove)(dev, index); 4328 4329 /* Update address in NIC data structure */ 4330 rte_ether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]); 4331 4332 /* reset pool bitmap */ 4333 dev->data->mac_pool_sel[index] = 0; 4334 4335 return 0; 4336 } 4337 4338 int 4339 rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct rte_ether_addr *addr) 4340 { 4341 struct rte_eth_dev *dev; 4342 int ret; 4343 4344 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4345 dev = &rte_eth_devices[port_id]; 4346 4347 if (addr == NULL) { 4348 RTE_ETHDEV_LOG(ERR, 4349 "Cannot set ethdev port %u default MAC address from NULL address\n", 4350 port_id); 4351 return -EINVAL; 4352 } 4353 4354 if (!rte_is_valid_assigned_ether_addr(addr)) 4355 return -EINVAL; 4356 4357 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_set, -ENOTSUP); 4358 4359 ret = (*dev->dev_ops->mac_addr_set)(dev, addr); 4360 if (ret < 0) 4361 return ret; 4362 4363 /* Update default address in NIC data structure */ 4364 rte_ether_addr_copy(addr, &dev->data->mac_addrs[0]); 4365 4366 return 0; 4367 } 4368 4369 4370 /* 4371 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find 4372 * an empty spot. 4373 */ 4374 static int 4375 eth_dev_get_hash_mac_addr_index(uint16_t port_id, 4376 const struct rte_ether_addr *addr) 4377 { 4378 struct rte_eth_dev_info dev_info; 4379 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 4380 unsigned i; 4381 int ret; 4382 4383 ret = rte_eth_dev_info_get(port_id, &dev_info); 4384 if (ret != 0) 4385 return -1; 4386 4387 if (!dev->data->hash_mac_addrs) 4388 return -1; 4389 4390 for (i = 0; i < dev_info.max_hash_mac_addrs; i++) 4391 if (memcmp(addr, &dev->data->hash_mac_addrs[i], 4392 RTE_ETHER_ADDR_LEN) == 0) 4393 return i; 4394 4395 return -1; 4396 } 4397 4398 int 4399 rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct rte_ether_addr *addr, 4400 uint8_t on) 4401 { 4402 int index; 4403 int ret; 4404 struct rte_eth_dev *dev; 4405 4406 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4407 dev = &rte_eth_devices[port_id]; 4408 4409 if (addr == NULL) { 4410 RTE_ETHDEV_LOG(ERR, 4411 "Cannot set ethdev port %u unicast hash table from NULL address\n", 4412 port_id); 4413 return -EINVAL; 4414 } 4415 4416 if (rte_is_zero_ether_addr(addr)) { 4417 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n", 4418 port_id); 4419 return -EINVAL; 4420 } 4421 4422 index = eth_dev_get_hash_mac_addr_index(port_id, addr); 4423 /* Check if it's already there, and do nothing */ 4424 if ((index >= 0) && on) 4425 return 0; 4426 4427 if (index < 0) { 4428 if (!on) { 4429 RTE_ETHDEV_LOG(ERR, 4430 "Port %u: the MAC address was not set in UTA\n", 4431 port_id); 4432 return -EINVAL; 4433 } 4434 4435 index = eth_dev_get_hash_mac_addr_index(port_id, &null_mac_addr); 4436 if (index < 0) { 4437 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n", 4438 port_id); 4439 return -ENOSPC; 4440 } 4441 } 4442 4443 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_hash_table_set, -ENOTSUP); 4444 ret = (*dev->dev_ops->uc_hash_table_set)(dev, addr, on); 4445 if (ret == 0) { 4446 /* Update address in NIC data structure */ 4447 if (on) 4448 rte_ether_addr_copy(addr, 4449 &dev->data->hash_mac_addrs[index]); 4450 else 4451 rte_ether_addr_copy(&null_mac_addr, 4452 &dev->data->hash_mac_addrs[index]); 4453 } 4454 4455 return eth_err(port_id, ret); 4456 } 4457 4458 int 4459 rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on) 4460 { 4461 struct rte_eth_dev *dev; 4462 4463 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4464 dev = &rte_eth_devices[port_id]; 4465 4466 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_all_hash_table_set, -ENOTSUP); 4467 return eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev, 4468 on)); 4469 } 4470 4471 int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx, 4472 uint16_t tx_rate) 4473 { 4474 struct rte_eth_dev *dev; 4475 struct rte_eth_dev_info dev_info; 4476 struct rte_eth_link link; 4477 int ret; 4478 4479 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4480 dev = &rte_eth_devices[port_id]; 4481 4482 ret = rte_eth_dev_info_get(port_id, &dev_info); 4483 if (ret != 0) 4484 return ret; 4485 4486 link = dev->data->dev_link; 4487 4488 if (queue_idx > dev_info.max_tx_queues) { 4489 RTE_ETHDEV_LOG(ERR, 4490 "Set queue rate limit:port %u: invalid queue id=%u\n", 4491 port_id, queue_idx); 4492 return -EINVAL; 4493 } 4494 4495 if (tx_rate > link.link_speed) { 4496 RTE_ETHDEV_LOG(ERR, 4497 "Set queue rate limit:invalid tx_rate=%u, bigger than link speed= %d\n", 4498 tx_rate, link.link_speed); 4499 return -EINVAL; 4500 } 4501 4502 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_queue_rate_limit, -ENOTSUP); 4503 return eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev, 4504 queue_idx, tx_rate)); 4505 } 4506 4507 RTE_INIT(eth_dev_init_cb_lists) 4508 { 4509 uint16_t i; 4510 4511 for (i = 0; i < RTE_MAX_ETHPORTS; i++) 4512 TAILQ_INIT(&rte_eth_devices[i].link_intr_cbs); 4513 } 4514 4515 int 4516 rte_eth_dev_callback_register(uint16_t port_id, 4517 enum rte_eth_event_type event, 4518 rte_eth_dev_cb_fn cb_fn, void *cb_arg) 4519 { 4520 struct rte_eth_dev *dev; 4521 struct rte_eth_dev_callback *user_cb; 4522 uint16_t next_port; 4523 uint16_t last_port; 4524 4525 if (cb_fn == NULL) { 4526 RTE_ETHDEV_LOG(ERR, 4527 "Cannot register ethdev port %u callback from NULL\n", 4528 port_id); 4529 return -EINVAL; 4530 } 4531 4532 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) { 4533 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id); 4534 return -EINVAL; 4535 } 4536 4537 if (port_id == RTE_ETH_ALL) { 4538 next_port = 0; 4539 last_port = RTE_MAX_ETHPORTS - 1; 4540 } else { 4541 next_port = last_port = port_id; 4542 } 4543 4544 rte_spinlock_lock(ð_dev_cb_lock); 4545 4546 do { 4547 dev = &rte_eth_devices[next_port]; 4548 4549 TAILQ_FOREACH(user_cb, &(dev->link_intr_cbs), next) { 4550 if (user_cb->cb_fn == cb_fn && 4551 user_cb->cb_arg == cb_arg && 4552 user_cb->event == event) { 4553 break; 4554 } 4555 } 4556 4557 /* create a new callback. */ 4558 if (user_cb == NULL) { 4559 user_cb = rte_zmalloc("INTR_USER_CALLBACK", 4560 sizeof(struct rte_eth_dev_callback), 0); 4561 if (user_cb != NULL) { 4562 user_cb->cb_fn = cb_fn; 4563 user_cb->cb_arg = cb_arg; 4564 user_cb->event = event; 4565 TAILQ_INSERT_TAIL(&(dev->link_intr_cbs), 4566 user_cb, next); 4567 } else { 4568 rte_spinlock_unlock(ð_dev_cb_lock); 4569 rte_eth_dev_callback_unregister(port_id, event, 4570 cb_fn, cb_arg); 4571 return -ENOMEM; 4572 } 4573 4574 } 4575 } while (++next_port <= last_port); 4576 4577 rte_spinlock_unlock(ð_dev_cb_lock); 4578 return 0; 4579 } 4580 4581 int 4582 rte_eth_dev_callback_unregister(uint16_t port_id, 4583 enum rte_eth_event_type event, 4584 rte_eth_dev_cb_fn cb_fn, void *cb_arg) 4585 { 4586 int ret; 4587 struct rte_eth_dev *dev; 4588 struct rte_eth_dev_callback *cb, *next; 4589 uint16_t next_port; 4590 uint16_t last_port; 4591 4592 if (cb_fn == NULL) { 4593 RTE_ETHDEV_LOG(ERR, 4594 "Cannot unregister ethdev port %u callback from NULL\n", 4595 port_id); 4596 return -EINVAL; 4597 } 4598 4599 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) { 4600 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id); 4601 return -EINVAL; 4602 } 4603 4604 if (port_id == RTE_ETH_ALL) { 4605 next_port = 0; 4606 last_port = RTE_MAX_ETHPORTS - 1; 4607 } else { 4608 next_port = last_port = port_id; 4609 } 4610 4611 rte_spinlock_lock(ð_dev_cb_lock); 4612 4613 do { 4614 dev = &rte_eth_devices[next_port]; 4615 ret = 0; 4616 for (cb = TAILQ_FIRST(&dev->link_intr_cbs); cb != NULL; 4617 cb = next) { 4618 4619 next = TAILQ_NEXT(cb, next); 4620 4621 if (cb->cb_fn != cb_fn || cb->event != event || 4622 (cb_arg != (void *)-1 && cb->cb_arg != cb_arg)) 4623 continue; 4624 4625 /* 4626 * if this callback is not executing right now, 4627 * then remove it. 4628 */ 4629 if (cb->active == 0) { 4630 TAILQ_REMOVE(&(dev->link_intr_cbs), cb, next); 4631 rte_free(cb); 4632 } else { 4633 ret = -EAGAIN; 4634 } 4635 } 4636 } while (++next_port <= last_port); 4637 4638 rte_spinlock_unlock(ð_dev_cb_lock); 4639 return ret; 4640 } 4641 4642 int 4643 rte_eth_dev_callback_process(struct rte_eth_dev *dev, 4644 enum rte_eth_event_type event, void *ret_param) 4645 { 4646 struct rte_eth_dev_callback *cb_lst; 4647 struct rte_eth_dev_callback dev_cb; 4648 int rc = 0; 4649 4650 rte_spinlock_lock(ð_dev_cb_lock); 4651 TAILQ_FOREACH(cb_lst, &(dev->link_intr_cbs), next) { 4652 if (cb_lst->cb_fn == NULL || cb_lst->event != event) 4653 continue; 4654 dev_cb = *cb_lst; 4655 cb_lst->active = 1; 4656 if (ret_param != NULL) 4657 dev_cb.ret_param = ret_param; 4658 4659 rte_spinlock_unlock(ð_dev_cb_lock); 4660 rc = dev_cb.cb_fn(dev->data->port_id, dev_cb.event, 4661 dev_cb.cb_arg, dev_cb.ret_param); 4662 rte_spinlock_lock(ð_dev_cb_lock); 4663 cb_lst->active = 0; 4664 } 4665 rte_spinlock_unlock(ð_dev_cb_lock); 4666 return rc; 4667 } 4668 4669 void 4670 rte_eth_dev_probing_finish(struct rte_eth_dev *dev) 4671 { 4672 if (dev == NULL) 4673 return; 4674 4675 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_NEW, NULL); 4676 4677 dev->state = RTE_ETH_DEV_ATTACHED; 4678 } 4679 4680 int 4681 rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data) 4682 { 4683 uint32_t vec; 4684 struct rte_eth_dev *dev; 4685 struct rte_intr_handle *intr_handle; 4686 uint16_t qid; 4687 int rc; 4688 4689 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4690 dev = &rte_eth_devices[port_id]; 4691 4692 if (!dev->intr_handle) { 4693 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n"); 4694 return -ENOTSUP; 4695 } 4696 4697 intr_handle = dev->intr_handle; 4698 if (!intr_handle->intr_vec) { 4699 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n"); 4700 return -EPERM; 4701 } 4702 4703 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) { 4704 vec = intr_handle->intr_vec[qid]; 4705 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); 4706 if (rc && rc != -EEXIST) { 4707 RTE_ETHDEV_LOG(ERR, 4708 "p %u q %u rx ctl error op %d epfd %d vec %u\n", 4709 port_id, qid, op, epfd, vec); 4710 } 4711 } 4712 4713 return 0; 4714 } 4715 4716 int 4717 rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id) 4718 { 4719 struct rte_intr_handle *intr_handle; 4720 struct rte_eth_dev *dev; 4721 unsigned int efd_idx; 4722 uint32_t vec; 4723 int fd; 4724 4725 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1); 4726 dev = &rte_eth_devices[port_id]; 4727 4728 if (queue_id >= dev->data->nb_rx_queues) { 4729 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 4730 return -1; 4731 } 4732 4733 if (!dev->intr_handle) { 4734 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n"); 4735 return -1; 4736 } 4737 4738 intr_handle = dev->intr_handle; 4739 if (!intr_handle->intr_vec) { 4740 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n"); 4741 return -1; 4742 } 4743 4744 vec = intr_handle->intr_vec[queue_id]; 4745 efd_idx = (vec >= RTE_INTR_VEC_RXTX_OFFSET) ? 4746 (vec - RTE_INTR_VEC_RXTX_OFFSET) : vec; 4747 fd = intr_handle->efds[efd_idx]; 4748 4749 return fd; 4750 } 4751 4752 static inline int 4753 eth_dev_dma_mzone_name(char *name, size_t len, uint16_t port_id, uint16_t queue_id, 4754 const char *ring_name) 4755 { 4756 return snprintf(name, len, "eth_p%d_q%d_%s", 4757 port_id, queue_id, ring_name); 4758 } 4759 4760 const struct rte_memzone * 4761 rte_eth_dma_zone_reserve(const struct rte_eth_dev *dev, const char *ring_name, 4762 uint16_t queue_id, size_t size, unsigned align, 4763 int socket_id) 4764 { 4765 char z_name[RTE_MEMZONE_NAMESIZE]; 4766 const struct rte_memzone *mz; 4767 int rc; 4768 4769 rc = eth_dev_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id, 4770 queue_id, ring_name); 4771 if (rc >= RTE_MEMZONE_NAMESIZE) { 4772 RTE_ETHDEV_LOG(ERR, "ring name too long\n"); 4773 rte_errno = ENAMETOOLONG; 4774 return NULL; 4775 } 4776 4777 mz = rte_memzone_lookup(z_name); 4778 if (mz) { 4779 if ((socket_id != SOCKET_ID_ANY && socket_id != mz->socket_id) || 4780 size > mz->len || 4781 ((uintptr_t)mz->addr & (align - 1)) != 0) { 4782 RTE_ETHDEV_LOG(ERR, 4783 "memzone %s does not justify the requested attributes\n", 4784 mz->name); 4785 return NULL; 4786 } 4787 4788 return mz; 4789 } 4790 4791 return rte_memzone_reserve_aligned(z_name, size, socket_id, 4792 RTE_MEMZONE_IOVA_CONTIG, align); 4793 } 4794 4795 int 4796 rte_eth_dma_zone_free(const struct rte_eth_dev *dev, const char *ring_name, 4797 uint16_t queue_id) 4798 { 4799 char z_name[RTE_MEMZONE_NAMESIZE]; 4800 const struct rte_memzone *mz; 4801 int rc = 0; 4802 4803 rc = eth_dev_dma_mzone_name(z_name, sizeof(z_name), dev->data->port_id, 4804 queue_id, ring_name); 4805 if (rc >= RTE_MEMZONE_NAMESIZE) { 4806 RTE_ETHDEV_LOG(ERR, "ring name too long\n"); 4807 return -ENAMETOOLONG; 4808 } 4809 4810 mz = rte_memzone_lookup(z_name); 4811 if (mz) 4812 rc = rte_memzone_free(mz); 4813 else 4814 rc = -ENOENT; 4815 4816 return rc; 4817 } 4818 4819 int 4820 rte_eth_dev_create(struct rte_device *device, const char *name, 4821 size_t priv_data_size, 4822 ethdev_bus_specific_init ethdev_bus_specific_init, 4823 void *bus_init_params, 4824 ethdev_init_t ethdev_init, void *init_params) 4825 { 4826 struct rte_eth_dev *ethdev; 4827 int retval; 4828 4829 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_init, -EINVAL); 4830 4831 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 4832 ethdev = rte_eth_dev_allocate(name); 4833 if (!ethdev) 4834 return -ENODEV; 4835 4836 if (priv_data_size) { 4837 ethdev->data->dev_private = rte_zmalloc_socket( 4838 name, priv_data_size, RTE_CACHE_LINE_SIZE, 4839 device->numa_node); 4840 4841 if (!ethdev->data->dev_private) { 4842 RTE_ETHDEV_LOG(ERR, 4843 "failed to allocate private data\n"); 4844 retval = -ENOMEM; 4845 goto probe_failed; 4846 } 4847 } 4848 } else { 4849 ethdev = rte_eth_dev_attach_secondary(name); 4850 if (!ethdev) { 4851 RTE_ETHDEV_LOG(ERR, 4852 "secondary process attach failed, ethdev doesn't exist\n"); 4853 return -ENODEV; 4854 } 4855 } 4856 4857 ethdev->device = device; 4858 4859 if (ethdev_bus_specific_init) { 4860 retval = ethdev_bus_specific_init(ethdev, bus_init_params); 4861 if (retval) { 4862 RTE_ETHDEV_LOG(ERR, 4863 "ethdev bus specific initialisation failed\n"); 4864 goto probe_failed; 4865 } 4866 } 4867 4868 retval = ethdev_init(ethdev, init_params); 4869 if (retval) { 4870 RTE_ETHDEV_LOG(ERR, "ethdev initialisation failed\n"); 4871 goto probe_failed; 4872 } 4873 4874 rte_eth_dev_probing_finish(ethdev); 4875 4876 return retval; 4877 4878 probe_failed: 4879 rte_eth_dev_release_port(ethdev); 4880 return retval; 4881 } 4882 4883 int 4884 rte_eth_dev_destroy(struct rte_eth_dev *ethdev, 4885 ethdev_uninit_t ethdev_uninit) 4886 { 4887 int ret; 4888 4889 ethdev = rte_eth_dev_allocated(ethdev->data->name); 4890 if (!ethdev) 4891 return -ENODEV; 4892 4893 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_uninit, -EINVAL); 4894 4895 ret = ethdev_uninit(ethdev); 4896 if (ret) 4897 return ret; 4898 4899 return rte_eth_dev_release_port(ethdev); 4900 } 4901 4902 int 4903 rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id, 4904 int epfd, int op, void *data) 4905 { 4906 uint32_t vec; 4907 struct rte_eth_dev *dev; 4908 struct rte_intr_handle *intr_handle; 4909 int rc; 4910 4911 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4912 dev = &rte_eth_devices[port_id]; 4913 4914 if (queue_id >= dev->data->nb_rx_queues) { 4915 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 4916 return -EINVAL; 4917 } 4918 4919 if (!dev->intr_handle) { 4920 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n"); 4921 return -ENOTSUP; 4922 } 4923 4924 intr_handle = dev->intr_handle; 4925 if (!intr_handle->intr_vec) { 4926 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n"); 4927 return -EPERM; 4928 } 4929 4930 vec = intr_handle->intr_vec[queue_id]; 4931 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); 4932 if (rc && rc != -EEXIST) { 4933 RTE_ETHDEV_LOG(ERR, 4934 "p %u q %u rx ctl error op %d epfd %d vec %u\n", 4935 port_id, queue_id, op, epfd, vec); 4936 return rc; 4937 } 4938 4939 return 0; 4940 } 4941 4942 int 4943 rte_eth_dev_rx_intr_enable(uint16_t port_id, 4944 uint16_t queue_id) 4945 { 4946 struct rte_eth_dev *dev; 4947 int ret; 4948 4949 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4950 dev = &rte_eth_devices[port_id]; 4951 4952 ret = eth_dev_validate_rx_queue(dev, queue_id); 4953 if (ret != 0) 4954 return ret; 4955 4956 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_enable, -ENOTSUP); 4957 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev, queue_id)); 4958 } 4959 4960 int 4961 rte_eth_dev_rx_intr_disable(uint16_t port_id, 4962 uint16_t queue_id) 4963 { 4964 struct rte_eth_dev *dev; 4965 int ret; 4966 4967 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4968 dev = &rte_eth_devices[port_id]; 4969 4970 ret = eth_dev_validate_rx_queue(dev, queue_id); 4971 if (ret != 0) 4972 return ret; 4973 4974 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_disable, -ENOTSUP); 4975 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev, queue_id)); 4976 } 4977 4978 4979 const struct rte_eth_rxtx_callback * 4980 rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id, 4981 rte_rx_callback_fn fn, void *user_param) 4982 { 4983 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 4984 rte_errno = ENOTSUP; 4985 return NULL; 4986 #endif 4987 struct rte_eth_dev *dev; 4988 4989 /* check input parameters */ 4990 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 4991 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) { 4992 rte_errno = EINVAL; 4993 return NULL; 4994 } 4995 dev = &rte_eth_devices[port_id]; 4996 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) { 4997 rte_errno = EINVAL; 4998 return NULL; 4999 } 5000 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 5001 5002 if (cb == NULL) { 5003 rte_errno = ENOMEM; 5004 return NULL; 5005 } 5006 5007 cb->fn.rx = fn; 5008 cb->param = user_param; 5009 5010 rte_spinlock_lock(ð_dev_rx_cb_lock); 5011 /* Add the callbacks in fifo order. */ 5012 struct rte_eth_rxtx_callback *tail = 5013 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; 5014 5015 if (!tail) { 5016 /* Stores to cb->fn and cb->param should complete before 5017 * cb is visible to data plane. 5018 */ 5019 __atomic_store_n( 5020 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id], 5021 cb, __ATOMIC_RELEASE); 5022 5023 } else { 5024 while (tail->next) 5025 tail = tail->next; 5026 /* Stores to cb->fn and cb->param should complete before 5027 * cb is visible to data plane. 5028 */ 5029 __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE); 5030 } 5031 rte_spinlock_unlock(ð_dev_rx_cb_lock); 5032 5033 return cb; 5034 } 5035 5036 const struct rte_eth_rxtx_callback * 5037 rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id, 5038 rte_rx_callback_fn fn, void *user_param) 5039 { 5040 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 5041 rte_errno = ENOTSUP; 5042 return NULL; 5043 #endif 5044 /* check input parameters */ 5045 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 5046 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) { 5047 rte_errno = EINVAL; 5048 return NULL; 5049 } 5050 5051 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 5052 5053 if (cb == NULL) { 5054 rte_errno = ENOMEM; 5055 return NULL; 5056 } 5057 5058 cb->fn.rx = fn; 5059 cb->param = user_param; 5060 5061 rte_spinlock_lock(ð_dev_rx_cb_lock); 5062 /* Add the callbacks at first position */ 5063 cb->next = rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; 5064 /* Stores to cb->fn, cb->param and cb->next should complete before 5065 * cb is visible to data plane threads. 5066 */ 5067 __atomic_store_n( 5068 &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id], 5069 cb, __ATOMIC_RELEASE); 5070 rte_spinlock_unlock(ð_dev_rx_cb_lock); 5071 5072 return cb; 5073 } 5074 5075 const struct rte_eth_rxtx_callback * 5076 rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id, 5077 rte_tx_callback_fn fn, void *user_param) 5078 { 5079 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 5080 rte_errno = ENOTSUP; 5081 return NULL; 5082 #endif 5083 struct rte_eth_dev *dev; 5084 5085 /* check input parameters */ 5086 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 5087 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) { 5088 rte_errno = EINVAL; 5089 return NULL; 5090 } 5091 5092 dev = &rte_eth_devices[port_id]; 5093 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) { 5094 rte_errno = EINVAL; 5095 return NULL; 5096 } 5097 5098 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 5099 5100 if (cb == NULL) { 5101 rte_errno = ENOMEM; 5102 return NULL; 5103 } 5104 5105 cb->fn.tx = fn; 5106 cb->param = user_param; 5107 5108 rte_spinlock_lock(ð_dev_tx_cb_lock); 5109 /* Add the callbacks in fifo order. */ 5110 struct rte_eth_rxtx_callback *tail = 5111 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id]; 5112 5113 if (!tail) { 5114 /* Stores to cb->fn and cb->param should complete before 5115 * cb is visible to data plane. 5116 */ 5117 __atomic_store_n( 5118 &rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id], 5119 cb, __ATOMIC_RELEASE); 5120 5121 } else { 5122 while (tail->next) 5123 tail = tail->next; 5124 /* Stores to cb->fn and cb->param should complete before 5125 * cb is visible to data plane. 5126 */ 5127 __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE); 5128 } 5129 rte_spinlock_unlock(ð_dev_tx_cb_lock); 5130 5131 return cb; 5132 } 5133 5134 int 5135 rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id, 5136 const struct rte_eth_rxtx_callback *user_cb) 5137 { 5138 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 5139 return -ENOTSUP; 5140 #endif 5141 /* Check input parameters. */ 5142 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5143 if (user_cb == NULL || 5144 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) 5145 return -EINVAL; 5146 5147 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 5148 struct rte_eth_rxtx_callback *cb; 5149 struct rte_eth_rxtx_callback **prev_cb; 5150 int ret = -EINVAL; 5151 5152 rte_spinlock_lock(ð_dev_rx_cb_lock); 5153 prev_cb = &dev->post_rx_burst_cbs[queue_id]; 5154 for (; *prev_cb != NULL; prev_cb = &cb->next) { 5155 cb = *prev_cb; 5156 if (cb == user_cb) { 5157 /* Remove the user cb from the callback list. */ 5158 __atomic_store_n(prev_cb, cb->next, __ATOMIC_RELAXED); 5159 ret = 0; 5160 break; 5161 } 5162 } 5163 rte_spinlock_unlock(ð_dev_rx_cb_lock); 5164 5165 return ret; 5166 } 5167 5168 int 5169 rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id, 5170 const struct rte_eth_rxtx_callback *user_cb) 5171 { 5172 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 5173 return -ENOTSUP; 5174 #endif 5175 /* Check input parameters. */ 5176 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5177 if (user_cb == NULL || 5178 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) 5179 return -EINVAL; 5180 5181 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 5182 int ret = -EINVAL; 5183 struct rte_eth_rxtx_callback *cb; 5184 struct rte_eth_rxtx_callback **prev_cb; 5185 5186 rte_spinlock_lock(ð_dev_tx_cb_lock); 5187 prev_cb = &dev->pre_tx_burst_cbs[queue_id]; 5188 for (; *prev_cb != NULL; prev_cb = &cb->next) { 5189 cb = *prev_cb; 5190 if (cb == user_cb) { 5191 /* Remove the user cb from the callback list. */ 5192 __atomic_store_n(prev_cb, cb->next, __ATOMIC_RELAXED); 5193 ret = 0; 5194 break; 5195 } 5196 } 5197 rte_spinlock_unlock(ð_dev_tx_cb_lock); 5198 5199 return ret; 5200 } 5201 5202 int 5203 rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id, 5204 struct rte_eth_rxq_info *qinfo) 5205 { 5206 struct rte_eth_dev *dev; 5207 5208 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5209 dev = &rte_eth_devices[port_id]; 5210 5211 if (queue_id >= dev->data->nb_rx_queues) { 5212 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 5213 return -EINVAL; 5214 } 5215 5216 if (qinfo == NULL) { 5217 RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u Rx queue %u info to NULL\n", 5218 port_id, queue_id); 5219 return -EINVAL; 5220 } 5221 5222 if (dev->data->rx_queues == NULL || 5223 dev->data->rx_queues[queue_id] == NULL) { 5224 RTE_ETHDEV_LOG(ERR, 5225 "Rx queue %"PRIu16" of device with port_id=%" 5226 PRIu16" has not been setup\n", 5227 queue_id, port_id); 5228 return -EINVAL; 5229 } 5230 5231 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) { 5232 RTE_ETHDEV_LOG(INFO, 5233 "Can't get hairpin Rx queue %"PRIu16" info of device with port_id=%"PRIu16"\n", 5234 queue_id, port_id); 5235 return -EINVAL; 5236 } 5237 5238 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rxq_info_get, -ENOTSUP); 5239 5240 memset(qinfo, 0, sizeof(*qinfo)); 5241 dev->dev_ops->rxq_info_get(dev, queue_id, qinfo); 5242 qinfo->queue_state = dev->data->rx_queue_state[queue_id]; 5243 5244 return 0; 5245 } 5246 5247 int 5248 rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id, 5249 struct rte_eth_txq_info *qinfo) 5250 { 5251 struct rte_eth_dev *dev; 5252 5253 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5254 dev = &rte_eth_devices[port_id]; 5255 5256 if (queue_id >= dev->data->nb_tx_queues) { 5257 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id); 5258 return -EINVAL; 5259 } 5260 5261 if (qinfo == NULL) { 5262 RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u Tx queue %u info to NULL\n", 5263 port_id, queue_id); 5264 return -EINVAL; 5265 } 5266 5267 if (dev->data->tx_queues == NULL || 5268 dev->data->tx_queues[queue_id] == NULL) { 5269 RTE_ETHDEV_LOG(ERR, 5270 "Tx queue %"PRIu16" of device with port_id=%" 5271 PRIu16" has not been setup\n", 5272 queue_id, port_id); 5273 return -EINVAL; 5274 } 5275 5276 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) { 5277 RTE_ETHDEV_LOG(INFO, 5278 "Can't get hairpin Tx queue %"PRIu16" info of device with port_id=%"PRIu16"\n", 5279 queue_id, port_id); 5280 return -EINVAL; 5281 } 5282 5283 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->txq_info_get, -ENOTSUP); 5284 5285 memset(qinfo, 0, sizeof(*qinfo)); 5286 dev->dev_ops->txq_info_get(dev, queue_id, qinfo); 5287 qinfo->queue_state = dev->data->tx_queue_state[queue_id]; 5288 5289 return 0; 5290 } 5291 5292 int 5293 rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id, 5294 struct rte_eth_burst_mode *mode) 5295 { 5296 struct rte_eth_dev *dev; 5297 5298 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5299 dev = &rte_eth_devices[port_id]; 5300 5301 if (queue_id >= dev->data->nb_rx_queues) { 5302 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 5303 return -EINVAL; 5304 } 5305 5306 if (mode == NULL) { 5307 RTE_ETHDEV_LOG(ERR, 5308 "Cannot get ethdev port %u Rx queue %u burst mode to NULL\n", 5309 port_id, queue_id); 5310 return -EINVAL; 5311 } 5312 5313 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_burst_mode_get, -ENOTSUP); 5314 memset(mode, 0, sizeof(*mode)); 5315 return eth_err(port_id, 5316 dev->dev_ops->rx_burst_mode_get(dev, queue_id, mode)); 5317 } 5318 5319 int 5320 rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id, 5321 struct rte_eth_burst_mode *mode) 5322 { 5323 struct rte_eth_dev *dev; 5324 5325 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5326 dev = &rte_eth_devices[port_id]; 5327 5328 if (queue_id >= dev->data->nb_tx_queues) { 5329 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id); 5330 return -EINVAL; 5331 } 5332 5333 if (mode == NULL) { 5334 RTE_ETHDEV_LOG(ERR, 5335 "Cannot get ethdev port %u Tx queue %u burst mode to NULL\n", 5336 port_id, queue_id); 5337 return -EINVAL; 5338 } 5339 5340 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_burst_mode_get, -ENOTSUP); 5341 memset(mode, 0, sizeof(*mode)); 5342 return eth_err(port_id, 5343 dev->dev_ops->tx_burst_mode_get(dev, queue_id, mode)); 5344 } 5345 5346 int 5347 rte_eth_get_monitor_addr(uint16_t port_id, uint16_t queue_id, 5348 struct rte_power_monitor_cond *pmc) 5349 { 5350 struct rte_eth_dev *dev; 5351 5352 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5353 dev = &rte_eth_devices[port_id]; 5354 5355 if (queue_id >= dev->data->nb_rx_queues) { 5356 RTE_ETHDEV_LOG(ERR, "Invalid Rx queue_id=%u\n", queue_id); 5357 return -EINVAL; 5358 } 5359 5360 if (pmc == NULL) { 5361 RTE_ETHDEV_LOG(ERR, 5362 "Cannot get ethdev port %u Rx queue %u power monitor condition to NULL\n", 5363 port_id, queue_id); 5364 return -EINVAL; 5365 } 5366 5367 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_monitor_addr, -ENOTSUP); 5368 return eth_err(port_id, 5369 dev->dev_ops->get_monitor_addr(dev->data->rx_queues[queue_id], pmc)); 5370 } 5371 5372 int 5373 rte_eth_dev_set_mc_addr_list(uint16_t port_id, 5374 struct rte_ether_addr *mc_addr_set, 5375 uint32_t nb_mc_addr) 5376 { 5377 struct rte_eth_dev *dev; 5378 5379 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5380 dev = &rte_eth_devices[port_id]; 5381 5382 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_mc_addr_list, -ENOTSUP); 5383 return eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev, 5384 mc_addr_set, nb_mc_addr)); 5385 } 5386 5387 int 5388 rte_eth_timesync_enable(uint16_t port_id) 5389 { 5390 struct rte_eth_dev *dev; 5391 5392 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5393 dev = &rte_eth_devices[port_id]; 5394 5395 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_enable, -ENOTSUP); 5396 return eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev)); 5397 } 5398 5399 int 5400 rte_eth_timesync_disable(uint16_t port_id) 5401 { 5402 struct rte_eth_dev *dev; 5403 5404 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5405 dev = &rte_eth_devices[port_id]; 5406 5407 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_disable, -ENOTSUP); 5408 return eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev)); 5409 } 5410 5411 int 5412 rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp, 5413 uint32_t flags) 5414 { 5415 struct rte_eth_dev *dev; 5416 5417 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5418 dev = &rte_eth_devices[port_id]; 5419 5420 if (timestamp == NULL) { 5421 RTE_ETHDEV_LOG(ERR, 5422 "Cannot read ethdev port %u Rx timestamp to NULL\n", 5423 port_id); 5424 return -EINVAL; 5425 } 5426 5427 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_rx_timestamp, -ENOTSUP); 5428 return eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp) 5429 (dev, timestamp, flags)); 5430 } 5431 5432 int 5433 rte_eth_timesync_read_tx_timestamp(uint16_t port_id, 5434 struct timespec *timestamp) 5435 { 5436 struct rte_eth_dev *dev; 5437 5438 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5439 dev = &rte_eth_devices[port_id]; 5440 5441 if (timestamp == NULL) { 5442 RTE_ETHDEV_LOG(ERR, 5443 "Cannot read ethdev port %u Tx timestamp to NULL\n", 5444 port_id); 5445 return -EINVAL; 5446 } 5447 5448 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_tx_timestamp, -ENOTSUP); 5449 return eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp) 5450 (dev, timestamp)); 5451 } 5452 5453 int 5454 rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta) 5455 { 5456 struct rte_eth_dev *dev; 5457 5458 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5459 dev = &rte_eth_devices[port_id]; 5460 5461 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_adjust_time, -ENOTSUP); 5462 return eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev, delta)); 5463 } 5464 5465 int 5466 rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp) 5467 { 5468 struct rte_eth_dev *dev; 5469 5470 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5471 dev = &rte_eth_devices[port_id]; 5472 5473 if (timestamp == NULL) { 5474 RTE_ETHDEV_LOG(ERR, 5475 "Cannot read ethdev port %u timesync time to NULL\n", 5476 port_id); 5477 return -EINVAL; 5478 } 5479 5480 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_time, -ENOTSUP); 5481 return eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev, 5482 timestamp)); 5483 } 5484 5485 int 5486 rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp) 5487 { 5488 struct rte_eth_dev *dev; 5489 5490 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5491 dev = &rte_eth_devices[port_id]; 5492 5493 if (timestamp == NULL) { 5494 RTE_ETHDEV_LOG(ERR, 5495 "Cannot write ethdev port %u timesync from NULL time\n", 5496 port_id); 5497 return -EINVAL; 5498 } 5499 5500 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_write_time, -ENOTSUP); 5501 return eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev, 5502 timestamp)); 5503 } 5504 5505 int 5506 rte_eth_read_clock(uint16_t port_id, uint64_t *clock) 5507 { 5508 struct rte_eth_dev *dev; 5509 5510 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5511 dev = &rte_eth_devices[port_id]; 5512 5513 if (clock == NULL) { 5514 RTE_ETHDEV_LOG(ERR, "Cannot read ethdev port %u clock to NULL\n", 5515 port_id); 5516 return -EINVAL; 5517 } 5518 5519 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->read_clock, -ENOTSUP); 5520 return eth_err(port_id, (*dev->dev_ops->read_clock)(dev, clock)); 5521 } 5522 5523 int 5524 rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info) 5525 { 5526 struct rte_eth_dev *dev; 5527 5528 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5529 dev = &rte_eth_devices[port_id]; 5530 5531 if (info == NULL) { 5532 RTE_ETHDEV_LOG(ERR, 5533 "Cannot get ethdev port %u register info to NULL\n", 5534 port_id); 5535 return -EINVAL; 5536 } 5537 5538 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_reg, -ENOTSUP); 5539 return eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info)); 5540 } 5541 5542 int 5543 rte_eth_dev_get_eeprom_length(uint16_t port_id) 5544 { 5545 struct rte_eth_dev *dev; 5546 5547 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5548 dev = &rte_eth_devices[port_id]; 5549 5550 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom_length, -ENOTSUP); 5551 return eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev)); 5552 } 5553 5554 int 5555 rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info) 5556 { 5557 struct rte_eth_dev *dev; 5558 5559 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5560 dev = &rte_eth_devices[port_id]; 5561 5562 if (info == NULL) { 5563 RTE_ETHDEV_LOG(ERR, 5564 "Cannot get ethdev port %u EEPROM info to NULL\n", 5565 port_id); 5566 return -EINVAL; 5567 } 5568 5569 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom, -ENOTSUP); 5570 return eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info)); 5571 } 5572 5573 int 5574 rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info) 5575 { 5576 struct rte_eth_dev *dev; 5577 5578 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5579 dev = &rte_eth_devices[port_id]; 5580 5581 if (info == NULL) { 5582 RTE_ETHDEV_LOG(ERR, 5583 "Cannot set ethdev port %u EEPROM from NULL info\n", 5584 port_id); 5585 return -EINVAL; 5586 } 5587 5588 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_eeprom, -ENOTSUP); 5589 return eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info)); 5590 } 5591 5592 int 5593 rte_eth_dev_get_module_info(uint16_t port_id, 5594 struct rte_eth_dev_module_info *modinfo) 5595 { 5596 struct rte_eth_dev *dev; 5597 5598 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5599 dev = &rte_eth_devices[port_id]; 5600 5601 if (modinfo == NULL) { 5602 RTE_ETHDEV_LOG(ERR, 5603 "Cannot get ethdev port %u EEPROM module info to NULL\n", 5604 port_id); 5605 return -EINVAL; 5606 } 5607 5608 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_info, -ENOTSUP); 5609 return (*dev->dev_ops->get_module_info)(dev, modinfo); 5610 } 5611 5612 int 5613 rte_eth_dev_get_module_eeprom(uint16_t port_id, 5614 struct rte_dev_eeprom_info *info) 5615 { 5616 struct rte_eth_dev *dev; 5617 5618 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5619 dev = &rte_eth_devices[port_id]; 5620 5621 if (info == NULL) { 5622 RTE_ETHDEV_LOG(ERR, 5623 "Cannot get ethdev port %u module EEPROM info to NULL\n", 5624 port_id); 5625 return -EINVAL; 5626 } 5627 5628 if (info->data == NULL) { 5629 RTE_ETHDEV_LOG(ERR, 5630 "Cannot get ethdev port %u module EEPROM data to NULL\n", 5631 port_id); 5632 return -EINVAL; 5633 } 5634 5635 if (info->length == 0) { 5636 RTE_ETHDEV_LOG(ERR, 5637 "Cannot get ethdev port %u module EEPROM to data with zero size\n", 5638 port_id); 5639 return -EINVAL; 5640 } 5641 5642 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_eeprom, -ENOTSUP); 5643 return (*dev->dev_ops->get_module_eeprom)(dev, info); 5644 } 5645 5646 int 5647 rte_eth_dev_get_dcb_info(uint16_t port_id, 5648 struct rte_eth_dcb_info *dcb_info) 5649 { 5650 struct rte_eth_dev *dev; 5651 5652 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5653 dev = &rte_eth_devices[port_id]; 5654 5655 if (dcb_info == NULL) { 5656 RTE_ETHDEV_LOG(ERR, 5657 "Cannot get ethdev port %u DCB info to NULL\n", 5658 port_id); 5659 return -EINVAL; 5660 } 5661 5662 memset(dcb_info, 0, sizeof(struct rte_eth_dcb_info)); 5663 5664 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_dcb_info, -ENOTSUP); 5665 return eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info)); 5666 } 5667 5668 static void 5669 eth_dev_adjust_nb_desc(uint16_t *nb_desc, 5670 const struct rte_eth_desc_lim *desc_lim) 5671 { 5672 if (desc_lim->nb_align != 0) 5673 *nb_desc = RTE_ALIGN_CEIL(*nb_desc, desc_lim->nb_align); 5674 5675 if (desc_lim->nb_max != 0) 5676 *nb_desc = RTE_MIN(*nb_desc, desc_lim->nb_max); 5677 5678 *nb_desc = RTE_MAX(*nb_desc, desc_lim->nb_min); 5679 } 5680 5681 int 5682 rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id, 5683 uint16_t *nb_rx_desc, 5684 uint16_t *nb_tx_desc) 5685 { 5686 struct rte_eth_dev_info dev_info; 5687 int ret; 5688 5689 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5690 5691 ret = rte_eth_dev_info_get(port_id, &dev_info); 5692 if (ret != 0) 5693 return ret; 5694 5695 if (nb_rx_desc != NULL) 5696 eth_dev_adjust_nb_desc(nb_rx_desc, &dev_info.rx_desc_lim); 5697 5698 if (nb_tx_desc != NULL) 5699 eth_dev_adjust_nb_desc(nb_tx_desc, &dev_info.tx_desc_lim); 5700 5701 return 0; 5702 } 5703 5704 int 5705 rte_eth_dev_hairpin_capability_get(uint16_t port_id, 5706 struct rte_eth_hairpin_cap *cap) 5707 { 5708 struct rte_eth_dev *dev; 5709 5710 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5711 dev = &rte_eth_devices[port_id]; 5712 5713 if (cap == NULL) { 5714 RTE_ETHDEV_LOG(ERR, 5715 "Cannot get ethdev port %u hairpin capability to NULL\n", 5716 port_id); 5717 return -EINVAL; 5718 } 5719 5720 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_cap_get, -ENOTSUP); 5721 memset(cap, 0, sizeof(*cap)); 5722 return eth_err(port_id, (*dev->dev_ops->hairpin_cap_get)(dev, cap)); 5723 } 5724 5725 int 5726 rte_eth_dev_is_rx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id) 5727 { 5728 if (dev->data->rx_queue_state[queue_id] == RTE_ETH_QUEUE_STATE_HAIRPIN) 5729 return 1; 5730 return 0; 5731 } 5732 5733 int 5734 rte_eth_dev_is_tx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id) 5735 { 5736 if (dev->data->tx_queue_state[queue_id] == RTE_ETH_QUEUE_STATE_HAIRPIN) 5737 return 1; 5738 return 0; 5739 } 5740 5741 int 5742 rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool) 5743 { 5744 struct rte_eth_dev *dev; 5745 5746 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5747 dev = &rte_eth_devices[port_id]; 5748 5749 if (pool == NULL) { 5750 RTE_ETHDEV_LOG(ERR, 5751 "Cannot test ethdev port %u mempool operation from NULL pool\n", 5752 port_id); 5753 return -EINVAL; 5754 } 5755 5756 if (*dev->dev_ops->pool_ops_supported == NULL) 5757 return 1; /* all pools are supported */ 5758 5759 return (*dev->dev_ops->pool_ops_supported)(dev, pool); 5760 } 5761 5762 /** 5763 * A set of values to describe the possible states of a switch domain. 5764 */ 5765 enum rte_eth_switch_domain_state { 5766 RTE_ETH_SWITCH_DOMAIN_UNUSED = 0, 5767 RTE_ETH_SWITCH_DOMAIN_ALLOCATED 5768 }; 5769 5770 /** 5771 * Array of switch domains available for allocation. Array is sized to 5772 * RTE_MAX_ETHPORTS elements as there cannot be more active switch domains than 5773 * ethdev ports in a single process. 5774 */ 5775 static struct rte_eth_dev_switch { 5776 enum rte_eth_switch_domain_state state; 5777 } eth_dev_switch_domains[RTE_MAX_ETHPORTS]; 5778 5779 int 5780 rte_eth_switch_domain_alloc(uint16_t *domain_id) 5781 { 5782 uint16_t i; 5783 5784 *domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 5785 5786 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 5787 if (eth_dev_switch_domains[i].state == 5788 RTE_ETH_SWITCH_DOMAIN_UNUSED) { 5789 eth_dev_switch_domains[i].state = 5790 RTE_ETH_SWITCH_DOMAIN_ALLOCATED; 5791 *domain_id = i; 5792 return 0; 5793 } 5794 } 5795 5796 return -ENOSPC; 5797 } 5798 5799 int 5800 rte_eth_switch_domain_free(uint16_t domain_id) 5801 { 5802 if (domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID || 5803 domain_id >= RTE_MAX_ETHPORTS) 5804 return -EINVAL; 5805 5806 if (eth_dev_switch_domains[domain_id].state != 5807 RTE_ETH_SWITCH_DOMAIN_ALLOCATED) 5808 return -EINVAL; 5809 5810 eth_dev_switch_domains[domain_id].state = RTE_ETH_SWITCH_DOMAIN_UNUSED; 5811 5812 return 0; 5813 } 5814 5815 static int 5816 eth_dev_devargs_tokenise(struct rte_kvargs *arglist, const char *str_in) 5817 { 5818 int state; 5819 struct rte_kvargs_pair *pair; 5820 char *letter; 5821 5822 arglist->str = strdup(str_in); 5823 if (arglist->str == NULL) 5824 return -ENOMEM; 5825 5826 letter = arglist->str; 5827 state = 0; 5828 arglist->count = 0; 5829 pair = &arglist->pairs[0]; 5830 while (1) { 5831 switch (state) { 5832 case 0: /* Initial */ 5833 if (*letter == '=') 5834 return -EINVAL; 5835 else if (*letter == '\0') 5836 return 0; 5837 5838 state = 1; 5839 pair->key = letter; 5840 /* fall-thru */ 5841 5842 case 1: /* Parsing key */ 5843 if (*letter == '=') { 5844 *letter = '\0'; 5845 pair->value = letter + 1; 5846 state = 2; 5847 } else if (*letter == ',' || *letter == '\0') 5848 return -EINVAL; 5849 break; 5850 5851 5852 case 2: /* Parsing value */ 5853 if (*letter == '[') 5854 state = 3; 5855 else if (*letter == ',') { 5856 *letter = '\0'; 5857 arglist->count++; 5858 pair = &arglist->pairs[arglist->count]; 5859 state = 0; 5860 } else if (*letter == '\0') { 5861 letter--; 5862 arglist->count++; 5863 pair = &arglist->pairs[arglist->count]; 5864 state = 0; 5865 } 5866 break; 5867 5868 case 3: /* Parsing list */ 5869 if (*letter == ']') 5870 state = 2; 5871 else if (*letter == '\0') 5872 return -EINVAL; 5873 break; 5874 } 5875 letter++; 5876 } 5877 } 5878 5879 int 5880 rte_eth_devargs_parse(const char *dargs, struct rte_eth_devargs *eth_da) 5881 { 5882 struct rte_kvargs args; 5883 struct rte_kvargs_pair *pair; 5884 unsigned int i; 5885 int result = 0; 5886 5887 memset(eth_da, 0, sizeof(*eth_da)); 5888 5889 result = eth_dev_devargs_tokenise(&args, dargs); 5890 if (result < 0) 5891 goto parse_cleanup; 5892 5893 for (i = 0; i < args.count; i++) { 5894 pair = &args.pairs[i]; 5895 if (strcmp("representor", pair->key) == 0) { 5896 if (eth_da->type != RTE_ETH_REPRESENTOR_NONE) { 5897 RTE_LOG(ERR, EAL, "duplicated representor key: %s\n", 5898 dargs); 5899 result = -1; 5900 goto parse_cleanup; 5901 } 5902 result = rte_eth_devargs_parse_representor_ports( 5903 pair->value, eth_da); 5904 if (result < 0) 5905 goto parse_cleanup; 5906 } 5907 } 5908 5909 parse_cleanup: 5910 if (args.str) 5911 free(args.str); 5912 5913 return result; 5914 } 5915 5916 int 5917 rte_eth_representor_id_get(const struct rte_eth_dev *ethdev, 5918 enum rte_eth_representor_type type, 5919 int controller, int pf, int representor_port, 5920 uint16_t *repr_id) 5921 { 5922 int ret, n, count; 5923 uint32_t i; 5924 struct rte_eth_representor_info *info = NULL; 5925 size_t size; 5926 5927 if (type == RTE_ETH_REPRESENTOR_NONE) 5928 return 0; 5929 if (repr_id == NULL) 5930 return -EINVAL; 5931 5932 /* Get PMD representor range info. */ 5933 ret = rte_eth_representor_info_get(ethdev->data->port_id, NULL); 5934 if (ret == -ENOTSUP && type == RTE_ETH_REPRESENTOR_VF && 5935 controller == -1 && pf == -1) { 5936 /* Direct mapping for legacy VF representor. */ 5937 *repr_id = representor_port; 5938 return 0; 5939 } else if (ret < 0) { 5940 return ret; 5941 } 5942 n = ret; 5943 size = sizeof(*info) + n * sizeof(info->ranges[0]); 5944 info = calloc(1, size); 5945 if (info == NULL) 5946 return -ENOMEM; 5947 info->nb_ranges_alloc = n; 5948 ret = rte_eth_representor_info_get(ethdev->data->port_id, info); 5949 if (ret < 0) 5950 goto out; 5951 5952 /* Default controller and pf to caller. */ 5953 if (controller == -1) 5954 controller = info->controller; 5955 if (pf == -1) 5956 pf = info->pf; 5957 5958 /* Locate representor ID. */ 5959 ret = -ENOENT; 5960 for (i = 0; i < info->nb_ranges; ++i) { 5961 if (info->ranges[i].type != type) 5962 continue; 5963 if (info->ranges[i].controller != controller) 5964 continue; 5965 if (info->ranges[i].id_end < info->ranges[i].id_base) { 5966 RTE_LOG(WARNING, EAL, "Port %hu invalid representor ID Range %u - %u, entry %d\n", 5967 ethdev->data->port_id, info->ranges[i].id_base, 5968 info->ranges[i].id_end, i); 5969 continue; 5970 5971 } 5972 count = info->ranges[i].id_end - info->ranges[i].id_base + 1; 5973 switch (info->ranges[i].type) { 5974 case RTE_ETH_REPRESENTOR_PF: 5975 if (pf < info->ranges[i].pf || 5976 pf >= info->ranges[i].pf + count) 5977 continue; 5978 *repr_id = info->ranges[i].id_base + 5979 (pf - info->ranges[i].pf); 5980 ret = 0; 5981 goto out; 5982 case RTE_ETH_REPRESENTOR_VF: 5983 if (info->ranges[i].pf != pf) 5984 continue; 5985 if (representor_port < info->ranges[i].vf || 5986 representor_port >= info->ranges[i].vf + count) 5987 continue; 5988 *repr_id = info->ranges[i].id_base + 5989 (representor_port - info->ranges[i].vf); 5990 ret = 0; 5991 goto out; 5992 case RTE_ETH_REPRESENTOR_SF: 5993 if (info->ranges[i].pf != pf) 5994 continue; 5995 if (representor_port < info->ranges[i].sf || 5996 representor_port >= info->ranges[i].sf + count) 5997 continue; 5998 *repr_id = info->ranges[i].id_base + 5999 (representor_port - info->ranges[i].sf); 6000 ret = 0; 6001 goto out; 6002 default: 6003 break; 6004 } 6005 } 6006 out: 6007 free(info); 6008 return ret; 6009 } 6010 6011 static int 6012 eth_dev_handle_port_list(const char *cmd __rte_unused, 6013 const char *params __rte_unused, 6014 struct rte_tel_data *d) 6015 { 6016 int port_id; 6017 6018 rte_tel_data_start_array(d, RTE_TEL_INT_VAL); 6019 RTE_ETH_FOREACH_DEV(port_id) 6020 rte_tel_data_add_array_int(d, port_id); 6021 return 0; 6022 } 6023 6024 static void 6025 eth_dev_add_port_queue_stats(struct rte_tel_data *d, uint64_t *q_stats, 6026 const char *stat_name) 6027 { 6028 int q; 6029 struct rte_tel_data *q_data = rte_tel_data_alloc(); 6030 rte_tel_data_start_array(q_data, RTE_TEL_U64_VAL); 6031 for (q = 0; q < RTE_ETHDEV_QUEUE_STAT_CNTRS; q++) 6032 rte_tel_data_add_array_u64(q_data, q_stats[q]); 6033 rte_tel_data_add_dict_container(d, stat_name, q_data, 0); 6034 } 6035 6036 #define ADD_DICT_STAT(stats, s) rte_tel_data_add_dict_u64(d, #s, stats.s) 6037 6038 static int 6039 eth_dev_handle_port_stats(const char *cmd __rte_unused, 6040 const char *params, 6041 struct rte_tel_data *d) 6042 { 6043 struct rte_eth_stats stats; 6044 int port_id, ret; 6045 6046 if (params == NULL || strlen(params) == 0 || !isdigit(*params)) 6047 return -1; 6048 6049 port_id = atoi(params); 6050 if (!rte_eth_dev_is_valid_port(port_id)) 6051 return -1; 6052 6053 ret = rte_eth_stats_get(port_id, &stats); 6054 if (ret < 0) 6055 return -1; 6056 6057 rte_tel_data_start_dict(d); 6058 ADD_DICT_STAT(stats, ipackets); 6059 ADD_DICT_STAT(stats, opackets); 6060 ADD_DICT_STAT(stats, ibytes); 6061 ADD_DICT_STAT(stats, obytes); 6062 ADD_DICT_STAT(stats, imissed); 6063 ADD_DICT_STAT(stats, ierrors); 6064 ADD_DICT_STAT(stats, oerrors); 6065 ADD_DICT_STAT(stats, rx_nombuf); 6066 eth_dev_add_port_queue_stats(d, stats.q_ipackets, "q_ipackets"); 6067 eth_dev_add_port_queue_stats(d, stats.q_opackets, "q_opackets"); 6068 eth_dev_add_port_queue_stats(d, stats.q_ibytes, "q_ibytes"); 6069 eth_dev_add_port_queue_stats(d, stats.q_obytes, "q_obytes"); 6070 eth_dev_add_port_queue_stats(d, stats.q_errors, "q_errors"); 6071 6072 return 0; 6073 } 6074 6075 static int 6076 eth_dev_handle_port_xstats(const char *cmd __rte_unused, 6077 const char *params, 6078 struct rte_tel_data *d) 6079 { 6080 struct rte_eth_xstat *eth_xstats; 6081 struct rte_eth_xstat_name *xstat_names; 6082 int port_id, num_xstats; 6083 int i, ret; 6084 char *end_param; 6085 6086 if (params == NULL || strlen(params) == 0 || !isdigit(*params)) 6087 return -1; 6088 6089 port_id = strtoul(params, &end_param, 0); 6090 if (*end_param != '\0') 6091 RTE_ETHDEV_LOG(NOTICE, 6092 "Extra parameters passed to ethdev telemetry command, ignoring"); 6093 if (!rte_eth_dev_is_valid_port(port_id)) 6094 return -1; 6095 6096 num_xstats = rte_eth_xstats_get(port_id, NULL, 0); 6097 if (num_xstats < 0) 6098 return -1; 6099 6100 /* use one malloc for both names and stats */ 6101 eth_xstats = malloc((sizeof(struct rte_eth_xstat) + 6102 sizeof(struct rte_eth_xstat_name)) * num_xstats); 6103 if (eth_xstats == NULL) 6104 return -1; 6105 xstat_names = (void *)ð_xstats[num_xstats]; 6106 6107 ret = rte_eth_xstats_get_names(port_id, xstat_names, num_xstats); 6108 if (ret < 0 || ret > num_xstats) { 6109 free(eth_xstats); 6110 return -1; 6111 } 6112 6113 ret = rte_eth_xstats_get(port_id, eth_xstats, num_xstats); 6114 if (ret < 0 || ret > num_xstats) { 6115 free(eth_xstats); 6116 return -1; 6117 } 6118 6119 rte_tel_data_start_dict(d); 6120 for (i = 0; i < num_xstats; i++) 6121 rte_tel_data_add_dict_u64(d, xstat_names[i].name, 6122 eth_xstats[i].value); 6123 return 0; 6124 } 6125 6126 static int 6127 eth_dev_handle_port_link_status(const char *cmd __rte_unused, 6128 const char *params, 6129 struct rte_tel_data *d) 6130 { 6131 static const char *status_str = "status"; 6132 int ret, port_id; 6133 struct rte_eth_link link; 6134 char *end_param; 6135 6136 if (params == NULL || strlen(params) == 0 || !isdigit(*params)) 6137 return -1; 6138 6139 port_id = strtoul(params, &end_param, 0); 6140 if (*end_param != '\0') 6141 RTE_ETHDEV_LOG(NOTICE, 6142 "Extra parameters passed to ethdev telemetry command, ignoring"); 6143 if (!rte_eth_dev_is_valid_port(port_id)) 6144 return -1; 6145 6146 ret = rte_eth_link_get_nowait(port_id, &link); 6147 if (ret < 0) 6148 return -1; 6149 6150 rte_tel_data_start_dict(d); 6151 if (!link.link_status) { 6152 rte_tel_data_add_dict_string(d, status_str, "DOWN"); 6153 return 0; 6154 } 6155 rte_tel_data_add_dict_string(d, status_str, "UP"); 6156 rte_tel_data_add_dict_u64(d, "speed", link.link_speed); 6157 rte_tel_data_add_dict_string(d, "duplex", 6158 (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 6159 "full-duplex" : "half-duplex"); 6160 return 0; 6161 } 6162 6163 int 6164 rte_eth_hairpin_queue_peer_update(uint16_t peer_port, uint16_t peer_queue, 6165 struct rte_hairpin_peer_info *cur_info, 6166 struct rte_hairpin_peer_info *peer_info, 6167 uint32_t direction) 6168 { 6169 struct rte_eth_dev *dev; 6170 6171 /* Current queue information is not mandatory. */ 6172 if (peer_info == NULL) 6173 return -EINVAL; 6174 6175 /* No need to check the validity again. */ 6176 dev = &rte_eth_devices[peer_port]; 6177 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_update, 6178 -ENOTSUP); 6179 6180 return (*dev->dev_ops->hairpin_queue_peer_update)(dev, peer_queue, 6181 cur_info, peer_info, direction); 6182 } 6183 6184 int 6185 rte_eth_hairpin_queue_peer_bind(uint16_t cur_port, uint16_t cur_queue, 6186 struct rte_hairpin_peer_info *peer_info, 6187 uint32_t direction) 6188 { 6189 struct rte_eth_dev *dev; 6190 6191 if (peer_info == NULL) 6192 return -EINVAL; 6193 6194 /* No need to check the validity again. */ 6195 dev = &rte_eth_devices[cur_port]; 6196 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_bind, 6197 -ENOTSUP); 6198 6199 return (*dev->dev_ops->hairpin_queue_peer_bind)(dev, cur_queue, 6200 peer_info, direction); 6201 } 6202 6203 int 6204 rte_eth_hairpin_queue_peer_unbind(uint16_t cur_port, uint16_t cur_queue, 6205 uint32_t direction) 6206 { 6207 struct rte_eth_dev *dev; 6208 6209 /* No need to check the validity again. */ 6210 dev = &rte_eth_devices[cur_port]; 6211 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_queue_peer_unbind, 6212 -ENOTSUP); 6213 6214 return (*dev->dev_ops->hairpin_queue_peer_unbind)(dev, cur_queue, 6215 direction); 6216 } 6217 6218 int 6219 rte_eth_representor_info_get(uint16_t port_id, 6220 struct rte_eth_representor_info *info) 6221 { 6222 struct rte_eth_dev *dev; 6223 6224 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 6225 dev = &rte_eth_devices[port_id]; 6226 6227 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->representor_info_get, -ENOTSUP); 6228 return eth_err(port_id, (*dev->dev_ops->representor_info_get)(dev, info)); 6229 } 6230 6231 RTE_LOG_REGISTER_DEFAULT(rte_eth_dev_logtype, INFO); 6232 6233 RTE_INIT(ethdev_init_telemetry) 6234 { 6235 rte_telemetry_register_cmd("/ethdev/list", eth_dev_handle_port_list, 6236 "Returns list of available ethdev ports. Takes no parameters"); 6237 rte_telemetry_register_cmd("/ethdev/stats", eth_dev_handle_port_stats, 6238 "Returns the common stats for a port. Parameters: int port_id"); 6239 rte_telemetry_register_cmd("/ethdev/xstats", eth_dev_handle_port_xstats, 6240 "Returns the extended stats for a port. Parameters: int port_id"); 6241 rte_telemetry_register_cmd("/ethdev/link_status", 6242 eth_dev_handle_port_link_status, 6243 "Returns the link status for a port. Parameters: int port_id"); 6244 } 6245