1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2014 Intel Corporation 3 */ 4 5 #include <stdio.h> 6 #include <stdlib.h> 7 #include <stdint.h> 8 #include <inttypes.h> 9 #include <sys/un.h> 10 #include <fcntl.h> 11 #include <unistd.h> 12 #include <dirent.h> 13 #include <errno.h> 14 15 #include <sys/sysinfo.h> 16 #include <sys/types.h> 17 18 #include <rte_log.h> 19 #include <rte_power.h> 20 #include <rte_spinlock.h> 21 22 #include "power_manager.h" 23 24 #define RTE_LOGTYPE_POWER_MANAGER RTE_LOGTYPE_USER1 25 26 #define POWER_SCALE_CORE(DIRECTION, core_num , ret) do { \ 27 if (core_num >= POWER_MGR_MAX_CPUS) \ 28 return -1; \ 29 if (!(global_enabled_cpus & (1ULL << core_num))) \ 30 return -1; \ 31 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl); \ 32 ret = rte_power_freq_##DIRECTION(core_num); \ 33 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl); \ 34 } while (0) 35 36 #define POWER_SCALE_MASK(DIRECTION, core_mask, ret) do { \ 37 int i; \ 38 for (i = 0; core_mask; core_mask &= ~(1 << i++)) { \ 39 if ((core_mask >> i) & 1) { \ 40 if (!(global_enabled_cpus & (1ULL << i))) \ 41 continue; \ 42 rte_spinlock_lock(&global_core_freq_info[i].power_sl); \ 43 if (rte_power_freq_##DIRECTION(i) != 1) \ 44 ret = -1; \ 45 rte_spinlock_unlock(&global_core_freq_info[i].power_sl); \ 46 } \ 47 } \ 48 } while (0) 49 50 struct freq_info { 51 rte_spinlock_t power_sl; 52 uint32_t freqs[RTE_MAX_LCORE_FREQS]; 53 unsigned num_freqs; 54 } __rte_cache_aligned; 55 56 static struct freq_info global_core_freq_info[POWER_MGR_MAX_CPUS]; 57 58 struct core_info ci; 59 static uint64_t global_enabled_cpus; 60 61 #define SYSFS_CPU_PATH "/sys/devices/system/cpu/cpu%u/topology/core_id" 62 63 static unsigned 64 set_host_cpus_mask(void) 65 { 66 char path[PATH_MAX]; 67 unsigned i; 68 unsigned num_cpus = 0; 69 70 for (i = 0; i < POWER_MGR_MAX_CPUS; i++) { 71 snprintf(path, sizeof(path), SYSFS_CPU_PATH, i); 72 if (access(path, F_OK) == 0) { 73 global_enabled_cpus |= 1ULL << i; 74 num_cpus++; 75 } else 76 return num_cpus; 77 } 78 return num_cpus; 79 } 80 81 struct core_info * 82 get_core_info(void) 83 { 84 return &ci; 85 } 86 87 int 88 core_info_init(void) 89 { 90 struct core_info *ci; 91 int i; 92 93 ci = get_core_info(); 94 95 ci->core_count = get_nprocs_conf(); 96 ci->cd = malloc(ci->core_count * sizeof(struct core_details)); 97 if (!ci->cd) { 98 RTE_LOG(ERR, POWER_MANAGER, "Failed to allocate memory for core info."); 99 return -1; 100 } 101 for (i = 0; i < ci->core_count; i++) { 102 ci->cd[i].global_enabled_cpus = 1; 103 ci->cd[i].oob_enabled = 0; 104 ci->cd[i].msr_fd = 0; 105 } 106 printf("%d cores in system\n", ci->core_count); 107 return 0; 108 } 109 110 int 111 power_manager_init(void) 112 { 113 unsigned int i, num_cpus, num_freqs; 114 uint64_t cpu_mask; 115 int ret = 0; 116 117 num_cpus = set_host_cpus_mask(); 118 if (num_cpus == 0) { 119 RTE_LOG(ERR, POWER_MANAGER, "Unable to detected host CPUs, please " 120 "ensure that sufficient privileges exist to inspect sysfs\n"); 121 return -1; 122 } 123 rte_power_set_env(PM_ENV_ACPI_CPUFREQ); 124 cpu_mask = global_enabled_cpus; 125 for (i = 0; cpu_mask; cpu_mask &= ~(1 << i++)) { 126 if (rte_power_init(i) < 0) 127 RTE_LOG(ERR, POWER_MANAGER, 128 "Unable to initialize power manager " 129 "for core %u\n", i); 130 num_freqs = rte_power_freqs(i, global_core_freq_info[i].freqs, 131 RTE_MAX_LCORE_FREQS); 132 if (num_freqs == 0) { 133 RTE_LOG(ERR, POWER_MANAGER, 134 "Unable to get frequency list for core %u\n", 135 i); 136 global_enabled_cpus &= ~(1 << i); 137 num_cpus--; 138 ret = -1; 139 } 140 global_core_freq_info[i].num_freqs = num_freqs; 141 rte_spinlock_init(&global_core_freq_info[i].power_sl); 142 } 143 RTE_LOG(INFO, POWER_MANAGER, "Detected %u host CPUs , enabled core mask:" 144 " 0x%"PRIx64"\n", num_cpus, global_enabled_cpus); 145 return ret; 146 147 } 148 149 uint32_t 150 power_manager_get_current_frequency(unsigned core_num) 151 { 152 uint32_t freq, index; 153 154 if (core_num >= POWER_MGR_MAX_CPUS) { 155 RTE_LOG(ERR, POWER_MANAGER, "Core(%u) is out of range 0...%d\n", 156 core_num, POWER_MGR_MAX_CPUS-1); 157 return -1; 158 } 159 if (!(global_enabled_cpus & (1ULL << core_num))) 160 return 0; 161 162 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl); 163 index = rte_power_get_freq(core_num); 164 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl); 165 if (index >= POWER_MGR_MAX_CPUS) 166 freq = 0; 167 else 168 freq = global_core_freq_info[core_num].freqs[index]; 169 170 return freq; 171 } 172 173 int 174 power_manager_exit(void) 175 { 176 unsigned int i; 177 int ret = 0; 178 179 for (i = 0; global_enabled_cpus; global_enabled_cpus &= ~(1 << i++)) { 180 if (rte_power_exit(i) < 0) { 181 RTE_LOG(ERR, POWER_MANAGER, "Unable to shutdown power manager " 182 "for core %u\n", i); 183 ret = -1; 184 } 185 } 186 global_enabled_cpus = 0; 187 return ret; 188 } 189 190 int 191 power_manager_scale_mask_up(uint64_t core_mask) 192 { 193 int ret = 0; 194 195 POWER_SCALE_MASK(up, core_mask, ret); 196 return ret; 197 } 198 199 int 200 power_manager_scale_mask_down(uint64_t core_mask) 201 { 202 int ret = 0; 203 204 POWER_SCALE_MASK(down, core_mask, ret); 205 return ret; 206 } 207 208 int 209 power_manager_scale_mask_min(uint64_t core_mask) 210 { 211 int ret = 0; 212 213 POWER_SCALE_MASK(min, core_mask, ret); 214 return ret; 215 } 216 217 int 218 power_manager_scale_mask_max(uint64_t core_mask) 219 { 220 int ret = 0; 221 222 POWER_SCALE_MASK(max, core_mask, ret); 223 return ret; 224 } 225 226 int 227 power_manager_enable_turbo_mask(uint64_t core_mask) 228 { 229 int ret = 0; 230 231 POWER_SCALE_MASK(enable_turbo, core_mask, ret); 232 return ret; 233 } 234 235 int 236 power_manager_disable_turbo_mask(uint64_t core_mask) 237 { 238 int ret = 0; 239 240 POWER_SCALE_MASK(disable_turbo, core_mask, ret); 241 return ret; 242 } 243 244 int 245 power_manager_scale_core_up(unsigned core_num) 246 { 247 int ret = 0; 248 249 POWER_SCALE_CORE(up, core_num, ret); 250 return ret; 251 } 252 253 int 254 power_manager_scale_core_down(unsigned core_num) 255 { 256 int ret = 0; 257 258 POWER_SCALE_CORE(down, core_num, ret); 259 return ret; 260 } 261 262 int 263 power_manager_scale_core_min(unsigned core_num) 264 { 265 int ret = 0; 266 267 POWER_SCALE_CORE(min, core_num, ret); 268 return ret; 269 } 270 271 int 272 power_manager_scale_core_max(unsigned core_num) 273 { 274 int ret = 0; 275 276 POWER_SCALE_CORE(max, core_num, ret); 277 return ret; 278 } 279 280 int 281 power_manager_enable_turbo_core(unsigned int core_num) 282 { 283 int ret = 0; 284 285 POWER_SCALE_CORE(enable_turbo, core_num, ret); 286 return ret; 287 } 288 289 int 290 power_manager_disable_turbo_core(unsigned int core_num) 291 { 292 int ret = 0; 293 294 POWER_SCALE_CORE(disable_turbo, core_num, ret); 295 return ret; 296 } 297 298 int 299 power_manager_scale_core_med(unsigned int core_num) 300 { 301 int ret = 0; 302 303 if (core_num >= POWER_MGR_MAX_CPUS) 304 return -1; 305 if (!(global_enabled_cpus & (1ULL << core_num))) 306 return -1; 307 rte_spinlock_lock(&global_core_freq_info[core_num].power_sl); 308 ret = rte_power_set_freq(core_num, 309 global_core_freq_info[core_num].num_freqs / 2); 310 rte_spinlock_unlock(&global_core_freq_info[core_num].power_sl); 311 return ret; 312 } 313