1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _VMXNET3_ETHDEV_H_ 35 #define _VMXNET3_ETHDEV_H_ 36 37 #define VMXNET3_MAX_MAC_ADDRS 1 38 39 /* UPT feature to negotiate */ 40 #define VMXNET3_F_RXCSUM 0x0001 41 #define VMXNET3_F_RSS 0x0002 42 #define VMXNET3_F_RXVLAN 0x0004 43 #define VMXNET3_F_LRO 0x0008 44 45 /* Hash Types supported by device */ 46 #define VMXNET3_RSS_HASH_TYPE_NONE 0x0 47 #define VMXNET3_RSS_HASH_TYPE_IPV4 0x01 48 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV4 0x02 49 #define VMXNET3_RSS_HASH_TYPE_IPV6 0x04 50 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV6 0x08 51 52 #define VMXNET3_RSS_HASH_FUNC_NONE 0x0 53 #define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 0x01 54 55 #define VMXNET3_RSS_MAX_KEY_SIZE 40 56 #define VMXNET3_RSS_MAX_IND_TABLE_SIZE 128 57 58 #define VMXNET3_RSS_OFFLOAD_ALL ( \ 59 ETH_RSS_IPV4 | \ 60 ETH_RSS_NONFRAG_IPV4_TCP | \ 61 ETH_RSS_IPV6 | \ 62 ETH_RSS_NONFRAG_IPV6_TCP) 63 64 /* RSS configuration structure - shared with device through GPA */ 65 typedef struct VMXNET3_RSSConf { 66 uint16_t hashType; 67 uint16_t hashFunc; 68 uint16_t hashKeySize; 69 uint16_t indTableSize; 70 uint8_t hashKey[VMXNET3_RSS_MAX_KEY_SIZE]; 71 /* 72 * indTable is only element that can be changed without 73 * device quiesce-reset-update-activation cycle 74 */ 75 uint8_t indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE]; 76 } VMXNET3_RSSConf; 77 78 typedef struct vmxnet3_mf_table { 79 void *mfTableBase; /* Multicast addresses list */ 80 uint64_t mfTablePA; /* Physical address of the list */ 81 uint16_t num_addrs; /* number of multicast addrs */ 82 } vmxnet3_mf_table_t; 83 84 struct vmxnet3_hw { 85 uint8_t *hw_addr0; /* BAR0: PT-Passthrough Regs */ 86 uint8_t *hw_addr1; /* BAR1: VD-Virtual Device Regs */ 87 /* BAR2: MSI-X Regs */ 88 /* BAR3: Port IO */ 89 void *back; 90 91 uint16_t device_id; 92 uint16_t vendor_id; 93 uint16_t subsystem_device_id; 94 uint16_t subsystem_vendor_id; 95 bool adapter_stopped; 96 97 uint8_t perm_addr[ETHER_ADDR_LEN]; 98 uint8_t num_tx_queues; 99 uint8_t num_rx_queues; 100 uint8_t bufs_per_pkt; 101 102 Vmxnet3_TxQueueDesc *tqd_start; /* start address of all tx queue desc */ 103 Vmxnet3_RxQueueDesc *rqd_start; /* start address of all rx queue desc */ 104 105 Vmxnet3_DriverShared *shared; 106 uint64_t sharedPA; 107 108 uint64_t queueDescPA; 109 uint16_t queue_desc_len; 110 111 VMXNET3_RSSConf *rss_conf; 112 uint64_t rss_confPA; 113 vmxnet3_mf_table_t *mf_table; 114 uint32_t shadow_vfta[VMXNET3_VFT_SIZE]; 115 #define VMXNET3_VFT_TABLE_SIZE (VMXNET3_VFT_SIZE * sizeof(uint32_t)) 116 }; 117 118 #define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg)) 119 #define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32)) 120 121 /* Config space read/writes */ 122 123 #define VMXNET3_PCI_REG(reg) (*((volatile uint32_t *)(reg))) 124 125 static inline uint32_t 126 vmxnet3_read_addr(volatile void *addr) 127 { 128 return VMXNET3_PCI_REG(addr); 129 } 130 131 #define VMXNET3_PCI_REG_WRITE(reg, value) do { \ 132 VMXNET3_PCI_REG((reg)) = (value); \ 133 } while(0) 134 135 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \ 136 ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg))) 137 #define VMXNET3_READ_BAR0_REG(hw, reg) \ 138 vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg))) 139 #define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \ 140 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value)) 141 142 #define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \ 143 ((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg))) 144 #define VMXNET3_READ_BAR1_REG(hw, reg) \ 145 vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg))) 146 #define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \ 147 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value)) 148 149 /* 150 * RX/TX function prototypes 151 */ 152 153 void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev); 154 155 void vmxnet3_dev_rx_queue_release(void *rxq); 156 void vmxnet3_dev_tx_queue_release(void *txq); 157 158 int vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 159 uint16_t nb_rx_desc, unsigned int socket_id, 160 const struct rte_eth_rxconf *rx_conf, 161 struct rte_mempool *mb_pool); 162 int vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 163 uint16_t nb_tx_desc, unsigned int socket_id, 164 const struct rte_eth_txconf *tx_conf); 165 166 int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev); 167 168 int vmxnet3_rss_configure(struct rte_eth_dev *dev); 169 170 uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 171 uint16_t nb_pkts); 172 uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 173 uint16_t nb_pkts); 174 175 #endif /* _VMXNET3_ETHDEV_H_ */ 176