1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2014 Intel Corporation 3 */ 4 5 #ifndef _VMXNET3_ETHDEV_H_ 6 #define _VMXNET3_ETHDEV_H_ 7 8 #include <rte_io.h> 9 10 #define VMXNET3_MAX_MAC_ADDRS 1 11 12 /* UPT feature to negotiate */ 13 #define VMXNET3_F_RXCSUM 0x0001 14 #define VMXNET3_F_RSS 0x0002 15 #define VMXNET3_F_RXVLAN 0x0004 16 #define VMXNET3_F_LRO 0x0008 17 18 /* Hash Types supported by device */ 19 #define VMXNET3_RSS_HASH_TYPE_NONE 0x0 20 #define VMXNET3_RSS_HASH_TYPE_IPV4 0x01 21 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV4 0x02 22 #define VMXNET3_RSS_HASH_TYPE_IPV6 0x04 23 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV6 0x08 24 25 #define VMXNET3_RSS_HASH_FUNC_NONE 0x0 26 #define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 0x01 27 28 #define VMXNET3_RSS_MAX_KEY_SIZE 40 29 #define VMXNET3_RSS_MAX_IND_TABLE_SIZE 128 30 31 #define VMXNET3_RSS_OFFLOAD_ALL ( \ 32 ETH_RSS_IPV4 | \ 33 ETH_RSS_NONFRAG_IPV4_TCP | \ 34 ETH_RSS_IPV6 | \ 35 ETH_RSS_NONFRAG_IPV6_TCP) 36 37 /* RSS configuration structure - shared with device through GPA */ 38 typedef struct VMXNET3_RSSConf { 39 uint16_t hashType; 40 uint16_t hashFunc; 41 uint16_t hashKeySize; 42 uint16_t indTableSize; 43 uint8_t hashKey[VMXNET3_RSS_MAX_KEY_SIZE]; 44 /* 45 * indTable is only element that can be changed without 46 * device quiesce-reset-update-activation cycle 47 */ 48 uint8_t indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE]; 49 } VMXNET3_RSSConf; 50 51 typedef struct vmxnet3_mf_table { 52 void *mfTableBase; /* Multicast addresses list */ 53 uint64_t mfTablePA; /* Physical address of the list */ 54 uint16_t num_addrs; /* number of multicast addrs */ 55 } vmxnet3_mf_table_t; 56 57 struct vmxnet3_hw { 58 uint8_t *hw_addr0; /* BAR0: PT-Passthrough Regs */ 59 uint8_t *hw_addr1; /* BAR1: VD-Virtual Device Regs */ 60 /* BAR2: MSI-X Regs */ 61 /* BAR3: Port IO */ 62 void *back; 63 64 uint16_t device_id; 65 uint16_t vendor_id; 66 uint16_t subsystem_device_id; 67 uint16_t subsystem_vendor_id; 68 bool adapter_stopped; 69 70 uint8_t perm_addr[ETHER_ADDR_LEN]; 71 uint8_t num_tx_queues; 72 uint8_t num_rx_queues; 73 uint8_t bufs_per_pkt; 74 75 uint8_t version; 76 77 uint16_t txdata_desc_size; /* tx data ring buffer size */ 78 uint16_t rxdata_desc_size; /* rx data ring buffer size */ 79 80 uint8_t num_intrs; 81 82 Vmxnet3_TxQueueDesc *tqd_start; /* start address of all tx queue desc */ 83 Vmxnet3_RxQueueDesc *rqd_start; /* start address of all rx queue desc */ 84 85 Vmxnet3_DriverShared *shared; 86 uint64_t sharedPA; 87 88 uint64_t queueDescPA; 89 uint16_t queue_desc_len; 90 91 VMXNET3_RSSConf *rss_conf; 92 uint64_t rss_confPA; 93 vmxnet3_mf_table_t *mf_table; 94 uint32_t shadow_vfta[VMXNET3_VFT_SIZE]; 95 Vmxnet3_MemRegs *memRegs; 96 uint64_t memRegsPA; 97 #define VMXNET3_VFT_TABLE_SIZE (VMXNET3_VFT_SIZE * sizeof(uint32_t)) 98 UPT1_TxStats saved_tx_stats[VMXNET3_MAX_TX_QUEUES]; 99 UPT1_RxStats saved_rx_stats[VMXNET3_MAX_RX_QUEUES]; 100 }; 101 102 #define VMXNET3_REV_3 2 /* Vmxnet3 Rev. 3 */ 103 #define VMXNET3_REV_2 1 /* Vmxnet3 Rev. 2 */ 104 #define VMXNET3_REV_1 0 /* Vmxnet3 Rev. 1 */ 105 106 #define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1) 107 #define VMXNET3_VERSION_GE_2(hw) ((hw)->version >= VMXNET3_REV_2 + 1) 108 109 #define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg)) 110 #define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32)) 111 112 /* Config space read/writes */ 113 114 #define VMXNET3_PCI_REG(reg) rte_read32(reg) 115 116 static inline uint32_t 117 vmxnet3_read_addr(volatile void *addr) 118 { 119 return VMXNET3_PCI_REG(addr); 120 } 121 122 #define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg)) 123 124 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \ 125 ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg))) 126 #define VMXNET3_READ_BAR0_REG(hw, reg) \ 127 vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg))) 128 #define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \ 129 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value)) 130 131 #define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \ 132 ((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg))) 133 #define VMXNET3_READ_BAR1_REG(hw, reg) \ 134 vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg))) 135 #define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \ 136 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value)) 137 138 static inline uint8_t 139 vmxnet3_get_ring_idx(struct vmxnet3_hw *hw, uint32 rqID) 140 { 141 return (rqID >= hw->num_rx_queues && 142 rqID < 2 * hw->num_rx_queues) ? 1 : 0; 143 } 144 145 static inline bool 146 vmxnet3_rx_data_ring(struct vmxnet3_hw *hw, uint32 rqID) 147 { 148 return (rqID >= 2 * hw->num_rx_queues && 149 rqID < 3 * hw->num_rx_queues); 150 } 151 152 /* 153 * RX/TX function prototypes 154 */ 155 156 void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev); 157 158 void vmxnet3_dev_rx_queue_release(void *rxq); 159 void vmxnet3_dev_tx_queue_release(void *txq); 160 161 int vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 162 uint16_t nb_rx_desc, unsigned int socket_id, 163 const struct rte_eth_rxconf *rx_conf, 164 struct rte_mempool *mb_pool); 165 int vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 166 uint16_t nb_tx_desc, unsigned int socket_id, 167 const struct rte_eth_txconf *tx_conf); 168 169 int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev); 170 171 int vmxnet3_rss_configure(struct rte_eth_dev *dev); 172 173 uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 174 uint16_t nb_pkts); 175 uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 176 uint16_t nb_pkts); 177 uint16_t vmxnet3_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 178 uint16_t nb_pkts); 179 180 #endif /* _VMXNET3_ETHDEV_H_ */ 181