1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2014 Intel Corporation 3 */ 4 5 #ifndef _VMXNET3_ETHDEV_H_ 6 #define _VMXNET3_ETHDEV_H_ 7 8 #include <rte_io.h> 9 #include <rte_mbuf_dyn.h> 10 11 #define VMXNET3_MAX_MAC_ADDRS 1 12 13 /* UPT feature to negotiate */ 14 #define VMXNET3_F_RXCSUM 0x0001 15 #define VMXNET3_F_RSS 0x0002 16 #define VMXNET3_F_RXVLAN 0x0004 17 #define VMXNET3_F_LRO 0x0008 18 19 /* Hash Types supported by device */ 20 #define VMXNET3_RSS_HASH_TYPE_NONE 0x0 21 #define VMXNET3_RSS_HASH_TYPE_IPV4 0x01 22 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV4 0x02 23 #define VMXNET3_RSS_HASH_TYPE_IPV6 0x04 24 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV6 0x08 25 26 #define VMXNET3_RSS_HASH_FUNC_NONE 0x0 27 #define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 0x01 28 29 #define VMXNET3_RSS_MAX_KEY_SIZE 40 30 #define VMXNET3_RSS_MAX_IND_TABLE_SIZE 128 31 32 #define VMXNET3_RSS_OFFLOAD_ALL ( \ 33 ETH_RSS_IPV4 | \ 34 ETH_RSS_NONFRAG_IPV4_TCP | \ 35 ETH_RSS_IPV6 | \ 36 ETH_RSS_NONFRAG_IPV6_TCP) 37 38 #define VMXNET3_V4_RSS_MASK ( \ 39 ETH_RSS_NONFRAG_IPV4_UDP | \ 40 ETH_RSS_NONFRAG_IPV6_UDP) 41 42 #define VMXNET3_MANDATORY_V4_RSS ( \ 43 ETH_RSS_NONFRAG_IPV4_TCP | \ 44 ETH_RSS_NONFRAG_IPV6_TCP) 45 46 /* RSS configuration structure - shared with device through GPA */ 47 typedef struct VMXNET3_RSSConf { 48 uint16_t hashType; 49 uint16_t hashFunc; 50 uint16_t hashKeySize; 51 uint16_t indTableSize; 52 uint8_t hashKey[VMXNET3_RSS_MAX_KEY_SIZE]; 53 /* 54 * indTable is only element that can be changed without 55 * device quiesce-reset-update-activation cycle 56 */ 57 uint8_t indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE]; 58 } VMXNET3_RSSConf; 59 60 typedef struct vmxnet3_mf_table { 61 void *mfTableBase; /* Multicast addresses list */ 62 uint64_t mfTablePA; /* Physical address of the list */ 63 uint16_t num_addrs; /* number of multicast addrs */ 64 } vmxnet3_mf_table_t; 65 66 struct vmxnet3_hw { 67 uint8_t *hw_addr0; /* BAR0: PT-Passthrough Regs */ 68 uint8_t *hw_addr1; /* BAR1: VD-Virtual Device Regs */ 69 /* BAR2: MSI-X Regs */ 70 /* BAR3: Port IO */ 71 void *back; 72 73 uint16_t device_id; 74 uint16_t vendor_id; 75 uint16_t subsystem_device_id; 76 uint16_t subsystem_vendor_id; 77 bool adapter_stopped; 78 79 uint8_t perm_addr[RTE_ETHER_ADDR_LEN]; 80 uint8_t num_tx_queues; 81 uint8_t num_rx_queues; 82 uint8_t bufs_per_pkt; 83 84 uint8_t version; 85 86 uint16_t txdata_desc_size; /* tx data ring buffer size */ 87 uint16_t rxdata_desc_size; /* rx data ring buffer size */ 88 89 uint8_t num_intrs; 90 91 Vmxnet3_TxQueueDesc *tqd_start; /* start address of all tx queue desc */ 92 Vmxnet3_RxQueueDesc *rqd_start; /* start address of all rx queue desc */ 93 94 Vmxnet3_DriverShared *shared; 95 uint64_t sharedPA; 96 97 uint64_t queueDescPA; 98 uint16_t queue_desc_len; 99 uint16_t mtu; 100 101 VMXNET3_RSSConf *rss_conf; 102 uint64_t rss_confPA; 103 vmxnet3_mf_table_t *mf_table; 104 uint32_t shadow_vfta[VMXNET3_VFT_SIZE]; 105 Vmxnet3_MemRegs *memRegs; 106 uint64_t memRegsPA; 107 #define VMXNET3_VFT_TABLE_SIZE (VMXNET3_VFT_SIZE * sizeof(uint32_t)) 108 UPT1_TxStats saved_tx_stats[VMXNET3_MAX_TX_QUEUES]; 109 UPT1_RxStats saved_rx_stats[VMXNET3_MAX_RX_QUEUES]; 110 111 UPT1_TxStats snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES]; 112 UPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES]; 113 }; 114 115 #define VMXNET3_REV_4 3 /* Vmxnet3 Rev. 4 */ 116 #define VMXNET3_REV_3 2 /* Vmxnet3 Rev. 3 */ 117 #define VMXNET3_REV_2 1 /* Vmxnet3 Rev. 2 */ 118 #define VMXNET3_REV_1 0 /* Vmxnet3 Rev. 1 */ 119 120 #define VMXNET3_VERSION_GE_4(hw) ((hw)->version >= VMXNET3_REV_4 + 1) 121 #define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1) 122 #define VMXNET3_VERSION_GE_2(hw) ((hw)->version >= VMXNET3_REV_2 + 1) 123 124 #define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg)) 125 #define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32)) 126 127 /* Config space read/writes */ 128 129 #define VMXNET3_PCI_REG(reg) rte_read32(reg) 130 131 static inline uint32_t 132 vmxnet3_read_addr(volatile void *addr) 133 { 134 return VMXNET3_PCI_REG(addr); 135 } 136 137 #define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg)) 138 139 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \ 140 ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg))) 141 #define VMXNET3_READ_BAR0_REG(hw, reg) \ 142 vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg))) 143 #define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \ 144 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value)) 145 146 #define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \ 147 ((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg))) 148 #define VMXNET3_READ_BAR1_REG(hw, reg) \ 149 vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg))) 150 #define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \ 151 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value)) 152 153 static inline uint8_t 154 vmxnet3_get_ring_idx(struct vmxnet3_hw *hw, uint32 rqID) 155 { 156 return (rqID >= hw->num_rx_queues && 157 rqID < 2 * hw->num_rx_queues) ? 1 : 0; 158 } 159 160 static inline bool 161 vmxnet3_rx_data_ring(struct vmxnet3_hw *hw, uint32 rqID) 162 { 163 return (rqID >= 2 * hw->num_rx_queues && 164 rqID < 3 * hw->num_rx_queues); 165 } 166 167 /* 168 * RX/TX function prototypes 169 */ 170 171 void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev); 172 173 void vmxnet3_dev_rx_queue_release(void *rxq); 174 void vmxnet3_dev_tx_queue_release(void *txq); 175 176 int vmxnet3_v4_rss_configure(struct rte_eth_dev *dev); 177 178 int vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 179 uint16_t nb_rx_desc, unsigned int socket_id, 180 const struct rte_eth_rxconf *rx_conf, 181 struct rte_mempool *mb_pool); 182 int vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 183 uint16_t nb_tx_desc, unsigned int socket_id, 184 const struct rte_eth_txconf *tx_conf); 185 186 int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev); 187 188 int vmxnet3_rss_configure(struct rte_eth_dev *dev); 189 190 uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 191 uint16_t nb_pkts); 192 uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 193 uint16_t nb_pkts); 194 uint16_t vmxnet3_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 195 uint16_t nb_pkts); 196 197 #define VMXNET3_SEGS_DYNFIELD_NAME "rte_net_vmxnet3_dynfield_segs" 198 typedef uint8_t vmxnet3_segs_dynfield_t; 199 extern int vmxnet3_segs_dynfield_offset; 200 201 static inline vmxnet3_segs_dynfield_t * 202 vmxnet3_segs_dynfield(struct rte_mbuf *mbuf) 203 { 204 return RTE_MBUF_DYNFIELD(mbuf, \ 205 vmxnet3_segs_dynfield_offset, vmxnet3_segs_dynfield_t *); 206 } 207 208 #endif /* _VMXNET3_ETHDEV_H_ */ 209