1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <stdlib.h> 9 #include <unistd.h> 10 #include <stdarg.h> 11 #include <inttypes.h> 12 13 #include <rte_interrupts.h> 14 #include <rte_log.h> 15 #include <rte_debug.h> 16 #include <rte_eal.h> 17 #include <rte_ether.h> 18 #include <rte_ethdev_driver.h> 19 #include <rte_memcpy.h> 20 #include <rte_malloc.h> 21 #include <rte_random.h> 22 #include <rte_bus_pci.h> 23 24 #include "base/txgbe.h" 25 #include "txgbe_ethdev.h" 26 #include "rte_pmd_txgbe.h" 27 28 #define TXGBE_MAX_VFTA (128) 29 #define TXGBE_VF_MSG_SIZE_DEFAULT 1 30 #define TXGBE_VF_GET_QUEUE_MSG_SIZE 5 31 32 static inline uint16_t 33 dev_num_vf(struct rte_eth_dev *eth_dev) 34 { 35 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 36 37 return pci_dev->max_vfs; 38 } 39 40 static inline 41 int txgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num) 42 { 43 unsigned char vf_mac_addr[RTE_ETHER_ADDR_LEN]; 44 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 45 uint16_t vfn; 46 47 for (vfn = 0; vfn < vf_num; vfn++) { 48 rte_eth_random_addr(vf_mac_addr); 49 /* keep the random address as default */ 50 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr, 51 RTE_ETHER_ADDR_LEN); 52 } 53 54 return 0; 55 } 56 57 static inline int 58 txgbe_mb_intr_setup(struct rte_eth_dev *dev) 59 { 60 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 61 62 intr->mask_misc |= TXGBE_ICRMISC_VFMBX; 63 64 return 0; 65 } 66 67 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev) 68 { 69 struct txgbe_vf_info **vfinfo = TXGBE_DEV_VFDATA(eth_dev); 70 struct txgbe_mirror_info *mirror_info = TXGBE_DEV_MR_INFO(eth_dev); 71 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(eth_dev); 72 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 73 uint16_t vf_num; 74 uint8_t nb_queue; 75 int ret = 0; 76 77 PMD_INIT_FUNC_TRACE(); 78 79 RTE_ETH_DEV_SRIOV(eth_dev).active = 0; 80 vf_num = dev_num_vf(eth_dev); 81 if (vf_num == 0) 82 return ret; 83 84 *vfinfo = rte_zmalloc("vf_info", 85 sizeof(struct txgbe_vf_info) * vf_num, 0); 86 if (*vfinfo == NULL) { 87 PMD_INIT_LOG(ERR, 88 "Cannot allocate memory for private VF data\n"); 89 return -ENOMEM; 90 } 91 92 ret = rte_eth_switch_domain_alloc(&(*vfinfo)->switch_domain_id); 93 if (ret) { 94 PMD_INIT_LOG(ERR, 95 "failed to allocate switch domain for device %d", ret); 96 rte_free(*vfinfo); 97 *vfinfo = NULL; 98 return ret; 99 } 100 101 memset(mirror_info, 0, sizeof(struct txgbe_mirror_info)); 102 memset(uta_info, 0, sizeof(struct txgbe_uta_info)); 103 hw->mac.mc_filter_type = 0; 104 105 if (vf_num >= ETH_32_POOLS) { 106 nb_queue = 2; 107 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS; 108 } else if (vf_num >= ETH_16_POOLS) { 109 nb_queue = 4; 110 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS; 111 } else { 112 nb_queue = 8; 113 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS; 114 } 115 116 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue; 117 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num; 118 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 119 (uint16_t)(vf_num * nb_queue); 120 121 txgbe_vf_perm_addr_gen(eth_dev, vf_num); 122 123 /* init_mailbox_params */ 124 hw->mbx.init_params(hw); 125 126 /* set mb interrupt mask */ 127 txgbe_mb_intr_setup(eth_dev); 128 129 return ret; 130 } 131 132 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev) 133 { 134 struct txgbe_vf_info **vfinfo; 135 uint16_t vf_num; 136 int ret; 137 138 PMD_INIT_FUNC_TRACE(); 139 140 RTE_ETH_DEV_SRIOV(eth_dev).active = 0; 141 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0; 142 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0; 143 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0; 144 145 vf_num = dev_num_vf(eth_dev); 146 if (vf_num == 0) 147 return; 148 149 vfinfo = TXGBE_DEV_VFDATA(eth_dev); 150 if (*vfinfo == NULL) 151 return; 152 153 ret = rte_eth_switch_domain_free((*vfinfo)->switch_domain_id); 154 if (ret) 155 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret); 156 157 rte_free(*vfinfo); 158 *vfinfo = NULL; 159 } 160 161 static void 162 txgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev) 163 { 164 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 165 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 166 uint16_t vf_num; 167 int i; 168 struct txgbe_ethertype_filter ethertype_filter; 169 170 if (!hw->mac.set_ethertype_anti_spoofing) { 171 PMD_DRV_LOG(INFO, "ether type anti-spoofing is not supported.\n"); 172 return; 173 } 174 175 i = txgbe_ethertype_filter_lookup(filter_info, 176 TXGBE_ETHERTYPE_FLOW_CTRL); 177 if (i >= 0) { 178 PMD_DRV_LOG(ERR, "A ether type filter entity for flow control already exists!\n"); 179 return; 180 } 181 182 ethertype_filter.ethertype = TXGBE_ETHERTYPE_FLOW_CTRL; 183 ethertype_filter.etqf = TXGBE_ETFLT_ENA | 184 TXGBE_ETFLT_TXAS | 185 TXGBE_ETHERTYPE_FLOW_CTRL; 186 ethertype_filter.etqs = 0; 187 ethertype_filter.conf = TRUE; 188 i = txgbe_ethertype_filter_insert(filter_info, 189 ðertype_filter); 190 if (i < 0) { 191 PMD_DRV_LOG(ERR, "Cannot find an unused ether type filter entity for flow control.\n"); 192 return; 193 } 194 195 wr32(hw, TXGBE_ETFLT(i), 196 (TXGBE_ETFLT_ENA | 197 TXGBE_ETFLT_TXAS | 198 TXGBE_ETHERTYPE_FLOW_CTRL)); 199 200 vf_num = dev_num_vf(eth_dev); 201 for (i = 0; i < vf_num; i++) 202 hw->mac.set_ethertype_anti_spoofing(hw, true, i); 203 } 204 205 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev) 206 { 207 uint32_t vtctl, fcrth; 208 uint32_t vfre_slot, vfre_offset; 209 uint16_t vf_num; 210 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ 211 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); 212 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 213 uint32_t gpie; 214 uint32_t gcr_ext; 215 uint32_t vlanctrl; 216 int i; 217 218 vf_num = dev_num_vf(eth_dev); 219 if (vf_num == 0) 220 return -1; 221 222 /* enable VMDq and set the default pool for PF */ 223 vtctl = rd32(hw, TXGBE_POOLCTL); 224 vtctl &= ~TXGBE_POOLCTL_DEFPL_MASK; 225 vtctl |= TXGBE_POOLCTL_DEFPL(RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx); 226 vtctl |= TXGBE_POOLCTL_RPLEN; 227 wr32(hw, TXGBE_POOLCTL, vtctl); 228 229 vfre_offset = vf_num & VFRE_MASK; 230 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0; 231 232 /* Enable pools reserved to PF only */ 233 wr32(hw, TXGBE_POOLRXENA(vfre_slot), (~0U) << vfre_offset); 234 wr32(hw, TXGBE_POOLRXENA(vfre_slot ^ 1), vfre_slot - 1); 235 wr32(hw, TXGBE_POOLTXENA(vfre_slot), (~0U) << vfre_offset); 236 wr32(hw, TXGBE_POOLTXENA(vfre_slot ^ 1), vfre_slot - 1); 237 238 wr32(hw, TXGBE_PSRCTL, TXGBE_PSRCTL_LBENA); 239 240 /* clear VMDq map to perment rar 0 */ 241 hw->mac.clear_vmdq(hw, 0, BIT_MASK32); 242 243 /* clear VMDq map to scan rar 127 */ 244 wr32(hw, TXGBE_ETHADDRIDX, hw->mac.num_rar_entries); 245 wr32(hw, TXGBE_ETHADDRASSL, 0); 246 wr32(hw, TXGBE_ETHADDRASSH, 0); 247 248 /* set VMDq map to default PF pool */ 249 hw->mac.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx); 250 251 /* 252 * SW msut set PORTCTL.VT_Mode the same as GPIE.VT_Mode 253 */ 254 gpie = rd32(hw, TXGBE_GPIE); 255 gpie |= TXGBE_GPIE_MSIX; 256 gcr_ext = rd32(hw, TXGBE_PORTCTL); 257 gcr_ext &= ~TXGBE_PORTCTL_NUMVT_MASK; 258 259 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) { 260 case ETH_64_POOLS: 261 gcr_ext |= TXGBE_PORTCTL_NUMVT_64; 262 break; 263 case ETH_32_POOLS: 264 gcr_ext |= TXGBE_PORTCTL_NUMVT_32; 265 break; 266 case ETH_16_POOLS: 267 gcr_ext |= TXGBE_PORTCTL_NUMVT_16; 268 break; 269 } 270 271 wr32(hw, TXGBE_PORTCTL, gcr_ext); 272 wr32(hw, TXGBE_GPIE, gpie); 273 274 /* 275 * enable vlan filtering and allow all vlan tags through 276 */ 277 vlanctrl = rd32(hw, TXGBE_VLANCTL); 278 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */ 279 wr32(hw, TXGBE_VLANCTL, vlanctrl); 280 281 /* enable all vlan filters */ 282 for (i = 0; i < TXGBE_MAX_VFTA; i++) 283 wr32(hw, TXGBE_VLANTBL(i), 0xFFFFFFFF); 284 285 /* Enable MAC Anti-Spoofing */ 286 hw->mac.set_mac_anti_spoofing(hw, FALSE, vf_num); 287 288 /* set flow control threshold to max to avoid tx switch hang */ 289 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 290 wr32(hw, TXGBE_FCWTRLO(i), 0); 291 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 32; 292 wr32(hw, TXGBE_FCWTRHI(i), fcrth); 293 } 294 295 txgbe_add_tx_flow_control_drop_filter(eth_dev); 296 297 return 0; 298 } 299 300 static void 301 txgbe_set_rx_mode(struct rte_eth_dev *eth_dev) 302 { 303 struct rte_eth_dev_data *dev_data = eth_dev->data; 304 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 305 u32 fctrl, vmolr; 306 uint16_t vfn = dev_num_vf(eth_dev); 307 308 /* disable store-bad-packets */ 309 wr32m(hw, TXGBE_SECRXCTL, TXGBE_SECRXCTL_SAVEBAD, 0); 310 311 /* Check for Promiscuous and All Multicast modes */ 312 fctrl = rd32m(hw, TXGBE_PSRCTL, 313 ~(TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP)); 314 fctrl |= TXGBE_PSRCTL_BCA | 315 TXGBE_PSRCTL_MCHFENA; 316 317 vmolr = rd32m(hw, TXGBE_POOLETHCTL(vfn), 318 ~(TXGBE_POOLETHCTL_UCP | 319 TXGBE_POOLETHCTL_MCP | 320 TXGBE_POOLETHCTL_UCHA | 321 TXGBE_POOLETHCTL_MCHA)); 322 vmolr |= TXGBE_POOLETHCTL_BCA | 323 TXGBE_POOLETHCTL_UTA | 324 TXGBE_POOLETHCTL_VLA; 325 326 if (dev_data->promiscuous) { 327 fctrl |= TXGBE_PSRCTL_UCP | 328 TXGBE_PSRCTL_MCP; 329 /* pf don't want packets routing to vf, so clear UPE */ 330 vmolr |= TXGBE_POOLETHCTL_MCP; 331 } else if (dev_data->all_multicast) { 332 fctrl |= TXGBE_PSRCTL_MCP; 333 vmolr |= TXGBE_POOLETHCTL_MCP; 334 } else { 335 vmolr |= TXGBE_POOLETHCTL_UCHA; 336 vmolr |= TXGBE_POOLETHCTL_MCHA; 337 } 338 339 wr32(hw, TXGBE_POOLETHCTL(vfn), vmolr); 340 341 wr32(hw, TXGBE_PSRCTL, fctrl); 342 343 txgbe_vlan_hw_strip_config(eth_dev); 344 } 345 346 static inline void 347 txgbe_vf_reset_event(struct rte_eth_dev *eth_dev, uint16_t vf) 348 { 349 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 350 struct txgbe_vf_info *vfinfo = *(TXGBE_DEV_VFDATA(eth_dev)); 351 int rar_entry = hw->mac.num_rar_entries - (vf + 1); 352 uint32_t vmolr = rd32(hw, TXGBE_POOLETHCTL(vf)); 353 354 vmolr |= (TXGBE_POOLETHCTL_UCHA | 355 TXGBE_POOLETHCTL_BCA | TXGBE_POOLETHCTL_UTA); 356 wr32(hw, TXGBE_POOLETHCTL(vf), vmolr); 357 358 wr32(hw, TXGBE_POOLTAG(vf), 0); 359 360 /* reset multicast table array for vf */ 361 vfinfo[vf].num_vf_mc_hashes = 0; 362 363 /* reset rx mode */ 364 txgbe_set_rx_mode(eth_dev); 365 366 hw->mac.clear_rar(hw, rar_entry); 367 } 368 369 static inline void 370 txgbe_vf_reset_msg(struct rte_eth_dev *eth_dev, uint16_t vf) 371 { 372 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 373 uint32_t reg; 374 uint32_t reg_offset, vf_shift; 375 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ 376 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); 377 uint8_t nb_q_per_pool; 378 int i; 379 380 vf_shift = vf & VFRE_MASK; 381 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0; 382 383 /* enable transmit for vf */ 384 reg = rd32(hw, TXGBE_POOLTXENA(reg_offset)); 385 reg |= (reg | (1 << vf_shift)); 386 wr32(hw, TXGBE_POOLTXENA(reg_offset), reg); 387 388 /* enable all queue drop for IOV */ 389 nb_q_per_pool = RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool; 390 for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) { 391 txgbe_flush(hw); 392 reg = 1 << (i % 32); 393 wr32m(hw, TXGBE_QPRXDROP(i / 32), reg, reg); 394 } 395 396 /* enable receive for vf */ 397 reg = rd32(hw, TXGBE_POOLRXENA(reg_offset)); 398 reg |= (reg | (1 << vf_shift)); 399 wr32(hw, TXGBE_POOLRXENA(reg_offset), reg); 400 401 txgbe_vf_reset_event(eth_dev, vf); 402 } 403 404 static int 405 txgbe_disable_vf_mc_promisc(struct rte_eth_dev *eth_dev, uint32_t vf) 406 { 407 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 408 uint32_t vmolr; 409 410 vmolr = rd32(hw, TXGBE_POOLETHCTL(vf)); 411 412 PMD_DRV_LOG(INFO, "VF %u: disabling multicast promiscuous\n", vf); 413 414 vmolr &= ~TXGBE_POOLETHCTL_MCP; 415 416 wr32(hw, TXGBE_POOLETHCTL(vf), vmolr); 417 418 return 0; 419 } 420 421 static int 422 txgbe_vf_reset(struct rte_eth_dev *eth_dev, uint16_t vf, uint32_t *msgbuf) 423 { 424 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 425 struct txgbe_vf_info *vfinfo = *(TXGBE_DEV_VFDATA(eth_dev)); 426 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses; 427 int rar_entry = hw->mac.num_rar_entries - (vf + 1); 428 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]); 429 430 txgbe_vf_reset_msg(eth_dev, vf); 431 432 hw->mac.set_rar(hw, rar_entry, vf_mac, vf, true); 433 434 /* Disable multicast promiscuous at reset */ 435 txgbe_disable_vf_mc_promisc(eth_dev, vf); 436 437 /* reply to reset with ack and vf mac address */ 438 msgbuf[0] = TXGBE_VF_RESET | TXGBE_VT_MSGTYPE_ACK; 439 rte_memcpy(new_mac, vf_mac, RTE_ETHER_ADDR_LEN); 440 /* 441 * Piggyback the multicast filter type so VF can compute the 442 * correct vectors 443 */ 444 msgbuf[3] = hw->mac.mc_filter_type; 445 txgbe_write_mbx(hw, msgbuf, TXGBE_VF_PERMADDR_MSG_LEN, vf); 446 447 return 0; 448 } 449 450 static int 451 txgbe_vf_set_mac_addr(struct rte_eth_dev *eth_dev, 452 uint32_t vf, uint32_t *msgbuf) 453 { 454 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 455 struct txgbe_vf_info *vfinfo = *(TXGBE_DEV_VFDATA(eth_dev)); 456 int rar_entry = hw->mac.num_rar_entries - (vf + 1); 457 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]); 458 struct rte_ether_addr *ea = (struct rte_ether_addr *)new_mac; 459 460 if (rte_is_valid_assigned_ether_addr(ea)) { 461 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6); 462 return hw->mac.set_rar(hw, rar_entry, new_mac, vf, true); 463 } 464 return -1; 465 } 466 467 static int 468 txgbe_vf_set_multicast(struct rte_eth_dev *eth_dev, 469 uint32_t vf, uint32_t *msgbuf) 470 { 471 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 472 struct txgbe_vf_info *vfinfo = *(TXGBE_DEV_VFDATA(eth_dev)); 473 int nb_entries = (msgbuf[0] & TXGBE_VT_MSGINFO_MASK) >> 474 TXGBE_VT_MSGINFO_SHIFT; 475 uint16_t *hash_list = (uint16_t *)&msgbuf[1]; 476 uint32_t mta_idx; 477 uint32_t mta_shift; 478 const uint32_t TXGBE_MTA_INDEX_MASK = 0x7F; 479 const uint32_t TXGBE_MTA_BIT_SHIFT = 5; 480 const uint32_t TXGBE_MTA_BIT_MASK = (0x1 << TXGBE_MTA_BIT_SHIFT) - 1; 481 uint32_t reg_val; 482 int i; 483 u32 vmolr = rd32(hw, TXGBE_POOLETHCTL(vf)); 484 485 /* Disable multicast promiscuous first */ 486 txgbe_disable_vf_mc_promisc(eth_dev, vf); 487 488 /* only so many hash values supported */ 489 nb_entries = RTE_MIN(nb_entries, TXGBE_MAX_VF_MC_ENTRIES); 490 491 /* store the mc entries */ 492 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries; 493 for (i = 0; i < nb_entries; i++) 494 vfinfo->vf_mc_hashes[i] = hash_list[i]; 495 496 if (nb_entries == 0) { 497 vmolr &= ~TXGBE_POOLETHCTL_MCHA; 498 wr32(hw, TXGBE_POOLETHCTL(vf), vmolr); 499 return 0; 500 } 501 502 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) { 503 mta_idx = (vfinfo->vf_mc_hashes[i] >> TXGBE_MTA_BIT_SHIFT) 504 & TXGBE_MTA_INDEX_MASK; 505 mta_shift = vfinfo->vf_mc_hashes[i] & TXGBE_MTA_BIT_MASK; 506 reg_val = rd32(hw, TXGBE_MCADDRTBL(mta_idx)); 507 reg_val |= (1 << mta_shift); 508 wr32(hw, TXGBE_MCADDRTBL(mta_idx), reg_val); 509 } 510 511 vmolr |= TXGBE_POOLETHCTL_MCHA; 512 wr32(hw, TXGBE_POOLETHCTL(vf), vmolr); 513 514 return 0; 515 } 516 517 static int 518 txgbe_vf_set_vlan(struct rte_eth_dev *eth_dev, uint32_t vf, uint32_t *msgbuf) 519 { 520 int add, vid; 521 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 522 struct txgbe_vf_info *vfinfo = *(TXGBE_DEV_VFDATA(eth_dev)); 523 524 add = (msgbuf[0] & TXGBE_VT_MSGINFO_MASK) 525 >> TXGBE_VT_MSGINFO_SHIFT; 526 vid = TXGBE_PSRVLAN_VID(msgbuf[1]); 527 528 if (add) 529 vfinfo[vf].vlan_count++; 530 else if (vfinfo[vf].vlan_count) 531 vfinfo[vf].vlan_count--; 532 return hw->mac.set_vfta(hw, vid, vf, (bool)add, false); 533 } 534 535 static int 536 txgbe_set_vf_lpe(struct rte_eth_dev *eth_dev, 537 __rte_unused uint32_t vf, uint32_t *msgbuf) 538 { 539 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 540 uint32_t max_frame = msgbuf[1]; 541 uint32_t max_frs; 542 543 if (max_frame < RTE_ETHER_MIN_LEN || 544 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN) 545 return -1; 546 547 max_frs = rd32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK); 548 if (max_frs < max_frame) { 549 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 550 TXGBE_FRMSZ_MAX(max_frame)); 551 } 552 553 return 0; 554 } 555 556 static int 557 txgbe_negotiate_vf_api(struct rte_eth_dev *eth_dev, 558 uint32_t vf, uint32_t *msgbuf) 559 { 560 uint32_t api_version = msgbuf[1]; 561 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(eth_dev); 562 563 switch (api_version) { 564 case txgbe_mbox_api_10: 565 case txgbe_mbox_api_11: 566 case txgbe_mbox_api_12: 567 case txgbe_mbox_api_13: 568 vfinfo[vf].api_version = (uint8_t)api_version; 569 return 0; 570 default: 571 break; 572 } 573 574 PMD_DRV_LOG(ERR, "Negotiate invalid api version %u from VF %d\n", 575 api_version, vf); 576 577 return -1; 578 } 579 580 static int 581 txgbe_get_vf_queues(struct rte_eth_dev *eth_dev, uint32_t vf, uint32_t *msgbuf) 582 { 583 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(eth_dev); 584 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool; 585 struct rte_eth_conf *eth_conf; 586 struct rte_eth_vmdq_dcb_tx_conf *vmdq_dcb_tx_conf; 587 u8 num_tcs; 588 struct txgbe_hw *hw; 589 u32 vmvir; 590 u32 vlana; 591 u32 vid; 592 u32 user_priority; 593 594 /* Verify if the PF supports the mbox APIs version or not */ 595 switch (vfinfo[vf].api_version) { 596 case txgbe_mbox_api_20: 597 case txgbe_mbox_api_11: 598 case txgbe_mbox_api_12: 599 case txgbe_mbox_api_13: 600 break; 601 default: 602 return -1; 603 } 604 605 /* Notify VF of Rx and Tx queue number */ 606 msgbuf[TXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool; 607 msgbuf[TXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool; 608 609 /* Notify VF of default queue */ 610 msgbuf[TXGBE_VF_DEF_QUEUE] = default_q; 611 612 /* Notify VF of number of DCB traffic classes */ 613 eth_conf = ð_dev->data->dev_conf; 614 switch (eth_conf->txmode.mq_mode) { 615 case ETH_MQ_TX_NONE: 616 case ETH_MQ_TX_DCB: 617 PMD_DRV_LOG(ERR, "PF must work with virtualization for VF %u" 618 ", but its tx mode = %d\n", vf, 619 eth_conf->txmode.mq_mode); 620 return -1; 621 622 case ETH_MQ_TX_VMDQ_DCB: 623 vmdq_dcb_tx_conf = ð_conf->tx_adv_conf.vmdq_dcb_tx_conf; 624 switch (vmdq_dcb_tx_conf->nb_queue_pools) { 625 case ETH_16_POOLS: 626 num_tcs = ETH_8_TCS; 627 break; 628 case ETH_32_POOLS: 629 num_tcs = ETH_4_TCS; 630 break; 631 default: 632 return -1; 633 } 634 break; 635 636 /* ETH_MQ_TX_VMDQ_ONLY, DCB not enabled */ 637 case ETH_MQ_TX_VMDQ_ONLY: 638 hw = TXGBE_DEV_HW(eth_dev); 639 vmvir = rd32(hw, TXGBE_POOLTAG(vf)); 640 vlana = vmvir & TXGBE_POOLTAG_ACT_MASK; 641 vid = vmvir & TXGBE_POOLTAG_VTAG_MASK; 642 user_priority = 643 TXGBD_POOLTAG_VTAG_UP(vmvir); 644 if (vlana == TXGBE_POOLTAG_ACT_ALWAYS && 645 (vid != 0 || user_priority != 0)) 646 num_tcs = 1; 647 else 648 num_tcs = 0; 649 break; 650 651 default: 652 PMD_DRV_LOG(ERR, "PF work with invalid mode = %d\n", 653 eth_conf->txmode.mq_mode); 654 return -1; 655 } 656 msgbuf[TXGBE_VF_TRANS_VLAN] = num_tcs; 657 658 return 0; 659 } 660 661 static int 662 txgbe_set_vf_mc_promisc(struct rte_eth_dev *eth_dev, 663 uint32_t vf, uint32_t *msgbuf) 664 { 665 struct txgbe_vf_info *vfinfo = *(TXGBE_DEV_VFDATA(eth_dev)); 666 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 667 int xcast_mode = msgbuf[1]; /* msgbuf contains the flag to enable */ 668 u32 vmolr, fctrl, disable, enable; 669 670 switch (vfinfo[vf].api_version) { 671 case txgbe_mbox_api_12: 672 /* promisc introduced in 1.3 version */ 673 if (xcast_mode == TXGBEVF_XCAST_MODE_PROMISC) 674 return -EOPNOTSUPP; 675 break; 676 /* Fall threw */ 677 case txgbe_mbox_api_13: 678 break; 679 default: 680 return -1; 681 } 682 683 if (vfinfo[vf].xcast_mode == xcast_mode) 684 goto out; 685 686 switch (xcast_mode) { 687 case TXGBEVF_XCAST_MODE_NONE: 688 disable = TXGBE_POOLETHCTL_BCA | TXGBE_POOLETHCTL_MCHA | 689 TXGBE_POOLETHCTL_MCP | TXGBE_POOLETHCTL_UCP | 690 TXGBE_POOLETHCTL_VLP; 691 enable = 0; 692 break; 693 case TXGBEVF_XCAST_MODE_MULTI: 694 disable = TXGBE_POOLETHCTL_MCP | TXGBE_POOLETHCTL_UCP | 695 TXGBE_POOLETHCTL_VLP; 696 enable = TXGBE_POOLETHCTL_BCA | TXGBE_POOLETHCTL_MCHA; 697 break; 698 case TXGBEVF_XCAST_MODE_ALLMULTI: 699 disable = TXGBE_POOLETHCTL_UCP | TXGBE_POOLETHCTL_VLP; 700 enable = TXGBE_POOLETHCTL_BCA | TXGBE_POOLETHCTL_MCHA | 701 TXGBE_POOLETHCTL_MCP; 702 break; 703 case TXGBEVF_XCAST_MODE_PROMISC: 704 fctrl = rd32(hw, TXGBE_PSRCTL); 705 if (!(fctrl & TXGBE_PSRCTL_UCP)) { 706 /* VF promisc requires PF in promisc */ 707 PMD_DRV_LOG(ERR, 708 "Enabling VF promisc requires PF in promisc\n"); 709 return -1; 710 } 711 712 disable = 0; 713 enable = TXGBE_POOLETHCTL_BCA | TXGBE_POOLETHCTL_MCHA | 714 TXGBE_POOLETHCTL_MCP | TXGBE_POOLETHCTL_UCP | 715 TXGBE_POOLETHCTL_VLP; 716 break; 717 default: 718 return -1; 719 } 720 721 vmolr = rd32(hw, TXGBE_POOLETHCTL(vf)); 722 vmolr &= ~disable; 723 vmolr |= enable; 724 wr32(hw, TXGBE_POOLETHCTL(vf), vmolr); 725 vfinfo[vf].xcast_mode = xcast_mode; 726 727 out: 728 msgbuf[1] = xcast_mode; 729 730 return 0; 731 } 732 733 static int 734 txgbe_set_vf_macvlan_msg(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 735 { 736 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 737 struct txgbe_vf_info *vf_info = *(TXGBE_DEV_VFDATA(dev)); 738 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]); 739 struct rte_ether_addr *ea = (struct rte_ether_addr *)new_mac; 740 int index = (msgbuf[0] & TXGBE_VT_MSGINFO_MASK) >> 741 TXGBE_VT_MSGINFO_SHIFT; 742 743 if (index) { 744 if (!rte_is_valid_assigned_ether_addr(ea)) { 745 PMD_DRV_LOG(ERR, "set invalid mac vf:%d\n", vf); 746 return -1; 747 } 748 749 vf_info[vf].mac_count++; 750 751 hw->mac.set_rar(hw, vf_info[vf].mac_count, 752 new_mac, vf, true); 753 } else { 754 if (vf_info[vf].mac_count) { 755 hw->mac.clear_rar(hw, vf_info[vf].mac_count); 756 vf_info[vf].mac_count = 0; 757 } 758 } 759 return 0; 760 } 761 762 static int 763 txgbe_rcv_msg_from_vf(struct rte_eth_dev *eth_dev, uint16_t vf) 764 { 765 uint16_t mbx_size = TXGBE_P2VMBX_SIZE; 766 uint16_t msg_size = TXGBE_VF_MSG_SIZE_DEFAULT; 767 uint32_t msgbuf[TXGBE_P2VMBX_SIZE]; 768 int32_t retval; 769 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 770 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(eth_dev); 771 struct rte_pmd_txgbe_mb_event_param ret_param; 772 773 retval = txgbe_read_mbx(hw, msgbuf, mbx_size, vf); 774 if (retval) { 775 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf); 776 return retval; 777 } 778 779 /* do nothing with the message already been processed */ 780 if (msgbuf[0] & (TXGBE_VT_MSGTYPE_ACK | TXGBE_VT_MSGTYPE_NACK)) 781 return retval; 782 783 /* flush the ack before we write any messages back */ 784 txgbe_flush(hw); 785 786 /** 787 * initialise structure to send to user application 788 * will return response from user in retval field 789 */ 790 ret_param.retval = RTE_PMD_TXGBE_MB_EVENT_PROCEED; 791 ret_param.vfid = vf; 792 ret_param.msg_type = msgbuf[0] & 0xFFFF; 793 ret_param.msg = (void *)msgbuf; 794 795 /* perform VF reset */ 796 if (msgbuf[0] == TXGBE_VF_RESET) { 797 int ret = txgbe_vf_reset(eth_dev, vf, msgbuf); 798 799 vfinfo[vf].clear_to_send = true; 800 801 /* notify application about VF reset */ 802 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_VF_MBOX, 803 &ret_param); 804 return ret; 805 } 806 807 /** 808 * ask user application if we allowed to perform those functions 809 * if we get ret_param.retval == RTE_PMD_TXGBE_MB_EVENT_PROCEED 810 * then business as usual, 811 * if 0, do nothing and send ACK to VF 812 * if ret_param.retval > 1, do nothing and send NAK to VF 813 */ 814 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_VF_MBOX, 815 &ret_param); 816 817 retval = ret_param.retval; 818 819 /* check & process VF to PF mailbox message */ 820 switch ((msgbuf[0] & 0xFFFF)) { 821 case TXGBE_VF_SET_MAC_ADDR: 822 if (retval == RTE_PMD_TXGBE_MB_EVENT_PROCEED) 823 retval = txgbe_vf_set_mac_addr(eth_dev, vf, msgbuf); 824 break; 825 case TXGBE_VF_SET_MULTICAST: 826 if (retval == RTE_PMD_TXGBE_MB_EVENT_PROCEED) 827 retval = txgbe_vf_set_multicast(eth_dev, vf, msgbuf); 828 break; 829 case TXGBE_VF_SET_LPE: 830 if (retval == RTE_PMD_TXGBE_MB_EVENT_PROCEED) 831 retval = txgbe_set_vf_lpe(eth_dev, vf, msgbuf); 832 break; 833 case TXGBE_VF_SET_VLAN: 834 if (retval == RTE_PMD_TXGBE_MB_EVENT_PROCEED) 835 retval = txgbe_vf_set_vlan(eth_dev, vf, msgbuf); 836 break; 837 case TXGBE_VF_API_NEGOTIATE: 838 retval = txgbe_negotiate_vf_api(eth_dev, vf, msgbuf); 839 break; 840 case TXGBE_VF_GET_QUEUES: 841 retval = txgbe_get_vf_queues(eth_dev, vf, msgbuf); 842 msg_size = TXGBE_VF_GET_QUEUE_MSG_SIZE; 843 break; 844 case TXGBE_VF_UPDATE_XCAST_MODE: 845 if (retval == RTE_PMD_TXGBE_MB_EVENT_PROCEED) 846 retval = txgbe_set_vf_mc_promisc(eth_dev, vf, msgbuf); 847 break; 848 case TXGBE_VF_SET_MACVLAN: 849 if (retval == RTE_PMD_TXGBE_MB_EVENT_PROCEED) 850 retval = txgbe_set_vf_macvlan_msg(eth_dev, vf, msgbuf); 851 break; 852 default: 853 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (uint32_t)msgbuf[0]); 854 retval = TXGBE_ERR_MBX; 855 break; 856 } 857 858 /* response the VF according to the message process result */ 859 if (retval) 860 msgbuf[0] |= TXGBE_VT_MSGTYPE_NACK; 861 else 862 msgbuf[0] |= TXGBE_VT_MSGTYPE_ACK; 863 864 msgbuf[0] |= TXGBE_VT_MSGTYPE_CTS; 865 866 txgbe_write_mbx(hw, msgbuf, msg_size, vf); 867 868 return retval; 869 } 870 871 static inline void 872 txgbe_rcv_ack_from_vf(struct rte_eth_dev *eth_dev, uint16_t vf) 873 { 874 uint32_t msg = TXGBE_VT_MSGTYPE_NACK; 875 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 876 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(eth_dev); 877 878 if (!vfinfo[vf].clear_to_send) 879 txgbe_write_mbx(hw, &msg, 1, vf); 880 } 881 882 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev) 883 { 884 uint16_t vf; 885 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 886 887 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) { 888 /* check & process vf function level reset */ 889 if (!txgbe_check_for_rst(hw, vf)) 890 txgbe_vf_reset_event(eth_dev, vf); 891 892 /* check & process vf mailbox messages */ 893 if (!txgbe_check_for_msg(hw, vf)) 894 txgbe_rcv_msg_from_vf(eth_dev, vf); 895 896 /* check & process acks from vf */ 897 if (!txgbe_check_for_ack(hw, vf)) 898 txgbe_rcv_ack_from_vf(eth_dev, vf); 899 } 900 } 901