1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <rte_common.h> 11 #include <ethdev_pci.h> 12 13 #include <rte_interrupts.h> 14 #include <rte_log.h> 15 #include <rte_debug.h> 16 #include <rte_pci.h> 17 #include <rte_memory.h> 18 #include <rte_eal.h> 19 #include <rte_alarm.h> 20 #include <rte_kvargs.h> 21 22 #include "txgbe_logs.h" 23 #include "base/txgbe.h" 24 #include "txgbe_ethdev.h" 25 #include "txgbe_rxtx.h" 26 #include "txgbe_regs_group.h" 27 28 static const struct reg_info txgbe_regs_general[] = { 29 {TXGBE_RST, 1, 1, "TXGBE_RST"}, 30 {TXGBE_STAT, 1, 1, "TXGBE_STAT"}, 31 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"}, 32 {TXGBE_SDP, 1, 1, "TXGBE_SDP"}, 33 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"}, 34 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"}, 35 {0, 0, 0, ""} 36 }; 37 38 static const struct reg_info txgbe_regs_nvm[] = { 39 {0, 0, 0, ""} 40 }; 41 42 static const struct reg_info txgbe_regs_interrupt[] = { 43 {0, 0, 0, ""} 44 }; 45 46 static const struct reg_info txgbe_regs_fctl_others[] = { 47 {0, 0, 0, ""} 48 }; 49 50 static const struct reg_info txgbe_regs_rxdma[] = { 51 {0, 0, 0, ""} 52 }; 53 54 static const struct reg_info txgbe_regs_rx[] = { 55 {0, 0, 0, ""} 56 }; 57 58 static struct reg_info txgbe_regs_tx[] = { 59 {0, 0, 0, ""} 60 }; 61 62 static const struct reg_info txgbe_regs_wakeup[] = { 63 {0, 0, 0, ""} 64 }; 65 66 static const struct reg_info txgbe_regs_dcb[] = { 67 {0, 0, 0, ""} 68 }; 69 70 static const struct reg_info txgbe_regs_mac[] = { 71 {0, 0, 0, ""} 72 }; 73 74 static const struct reg_info txgbe_regs_diagnostic[] = { 75 {0, 0, 0, ""}, 76 }; 77 78 /* PF registers */ 79 static const struct reg_info *txgbe_regs_others[] = { 80 txgbe_regs_general, 81 txgbe_regs_nvm, 82 txgbe_regs_interrupt, 83 txgbe_regs_fctl_others, 84 txgbe_regs_rxdma, 85 txgbe_regs_rx, 86 txgbe_regs_tx, 87 txgbe_regs_wakeup, 88 txgbe_regs_dcb, 89 txgbe_regs_mac, 90 txgbe_regs_diagnostic, 91 NULL}; 92 93 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 94 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 95 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 96 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 97 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev); 98 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev); 99 static int txgbe_dev_close(struct rte_eth_dev *dev); 100 static int txgbe_dev_link_update(struct rte_eth_dev *dev, 101 int wait_to_complete); 102 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev); 103 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 104 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, 105 uint16_t queue); 106 107 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev); 108 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 109 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 110 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev); 111 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 112 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, 113 struct rte_intr_handle *handle); 114 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 115 struct rte_intr_handle *handle); 116 static void txgbe_dev_interrupt_handler(void *param); 117 static void txgbe_dev_interrupt_delayed_handler(void *param); 118 static void txgbe_configure_msix(struct rte_eth_dev *dev); 119 120 static int txgbe_filter_restore(struct rte_eth_dev *dev); 121 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 122 123 #define TXGBE_SET_HWSTRIP(h, q) do {\ 124 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 125 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 126 (h)->bitmap[idx] |= 1 << bit;\ 127 } while (0) 128 129 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\ 130 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 131 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 132 (h)->bitmap[idx] &= ~(1 << bit);\ 133 } while (0) 134 135 #define TXGBE_GET_HWSTRIP(h, q, r) do {\ 136 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 137 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 138 (r) = (h)->bitmap[idx] >> bit & 1;\ 139 } while (0) 140 141 /* 142 * The set of PCI devices this driver supports 143 */ 144 static const struct rte_pci_id pci_id_txgbe_map[] = { 145 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) }, 146 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) }, 147 { .vendor_id = 0, /* sentinel */ }, 148 }; 149 150 static const struct rte_eth_desc_lim rx_desc_lim = { 151 .nb_max = TXGBE_RING_DESC_MAX, 152 .nb_min = TXGBE_RING_DESC_MIN, 153 .nb_align = TXGBE_RXD_ALIGN, 154 }; 155 156 static const struct rte_eth_desc_lim tx_desc_lim = { 157 .nb_max = TXGBE_RING_DESC_MAX, 158 .nb_min = TXGBE_RING_DESC_MIN, 159 .nb_align = TXGBE_TXD_ALIGN, 160 .nb_seg_max = TXGBE_TX_MAX_SEG, 161 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG, 162 }; 163 164 static const struct eth_dev_ops txgbe_eth_dev_ops; 165 166 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)} 167 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)} 168 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = { 169 /* MNG RxTx */ 170 HW_XSTAT(mng_bmc2host_packets), 171 HW_XSTAT(mng_host2bmc_packets), 172 /* Basic RxTx */ 173 HW_XSTAT(rx_packets), 174 HW_XSTAT(tx_packets), 175 HW_XSTAT(rx_bytes), 176 HW_XSTAT(tx_bytes), 177 HW_XSTAT(rx_total_bytes), 178 HW_XSTAT(rx_total_packets), 179 HW_XSTAT(tx_total_packets), 180 HW_XSTAT(rx_total_missed_packets), 181 HW_XSTAT(rx_broadcast_packets), 182 HW_XSTAT(rx_multicast_packets), 183 HW_XSTAT(rx_management_packets), 184 HW_XSTAT(tx_management_packets), 185 HW_XSTAT(rx_management_dropped), 186 187 /* Basic Error */ 188 HW_XSTAT(rx_crc_errors), 189 HW_XSTAT(rx_illegal_byte_errors), 190 HW_XSTAT(rx_error_bytes), 191 HW_XSTAT(rx_mac_short_packet_dropped), 192 HW_XSTAT(rx_length_errors), 193 HW_XSTAT(rx_undersize_errors), 194 HW_XSTAT(rx_fragment_errors), 195 HW_XSTAT(rx_oversize_errors), 196 HW_XSTAT(rx_jabber_errors), 197 HW_XSTAT(rx_l3_l4_xsum_error), 198 HW_XSTAT(mac_local_errors), 199 HW_XSTAT(mac_remote_errors), 200 201 /* Flow Director */ 202 HW_XSTAT(flow_director_added_filters), 203 HW_XSTAT(flow_director_removed_filters), 204 HW_XSTAT(flow_director_filter_add_errors), 205 HW_XSTAT(flow_director_filter_remove_errors), 206 HW_XSTAT(flow_director_matched_filters), 207 HW_XSTAT(flow_director_missed_filters), 208 209 /* FCoE */ 210 HW_XSTAT(rx_fcoe_crc_errors), 211 HW_XSTAT(rx_fcoe_mbuf_allocation_errors), 212 HW_XSTAT(rx_fcoe_dropped), 213 HW_XSTAT(rx_fcoe_packets), 214 HW_XSTAT(tx_fcoe_packets), 215 HW_XSTAT(rx_fcoe_bytes), 216 HW_XSTAT(tx_fcoe_bytes), 217 HW_XSTAT(rx_fcoe_no_ddp), 218 HW_XSTAT(rx_fcoe_no_ddp_ext_buff), 219 220 /* MACSEC */ 221 HW_XSTAT(tx_macsec_pkts_untagged), 222 HW_XSTAT(tx_macsec_pkts_encrypted), 223 HW_XSTAT(tx_macsec_pkts_protected), 224 HW_XSTAT(tx_macsec_octets_encrypted), 225 HW_XSTAT(tx_macsec_octets_protected), 226 HW_XSTAT(rx_macsec_pkts_untagged), 227 HW_XSTAT(rx_macsec_pkts_badtag), 228 HW_XSTAT(rx_macsec_pkts_nosci), 229 HW_XSTAT(rx_macsec_pkts_unknownsci), 230 HW_XSTAT(rx_macsec_octets_decrypted), 231 HW_XSTAT(rx_macsec_octets_validated), 232 HW_XSTAT(rx_macsec_sc_pkts_unchecked), 233 HW_XSTAT(rx_macsec_sc_pkts_delayed), 234 HW_XSTAT(rx_macsec_sc_pkts_late), 235 HW_XSTAT(rx_macsec_sa_pkts_ok), 236 HW_XSTAT(rx_macsec_sa_pkts_invalid), 237 HW_XSTAT(rx_macsec_sa_pkts_notvalid), 238 HW_XSTAT(rx_macsec_sa_pkts_unusedsa), 239 HW_XSTAT(rx_macsec_sa_pkts_notusingsa), 240 241 /* MAC RxTx */ 242 HW_XSTAT(rx_size_64_packets), 243 HW_XSTAT(rx_size_65_to_127_packets), 244 HW_XSTAT(rx_size_128_to_255_packets), 245 HW_XSTAT(rx_size_256_to_511_packets), 246 HW_XSTAT(rx_size_512_to_1023_packets), 247 HW_XSTAT(rx_size_1024_to_max_packets), 248 HW_XSTAT(tx_size_64_packets), 249 HW_XSTAT(tx_size_65_to_127_packets), 250 HW_XSTAT(tx_size_128_to_255_packets), 251 HW_XSTAT(tx_size_256_to_511_packets), 252 HW_XSTAT(tx_size_512_to_1023_packets), 253 HW_XSTAT(tx_size_1024_to_max_packets), 254 255 /* Flow Control */ 256 HW_XSTAT(tx_xon_packets), 257 HW_XSTAT(rx_xon_packets), 258 HW_XSTAT(tx_xoff_packets), 259 HW_XSTAT(rx_xoff_packets), 260 261 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"), 262 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"), 263 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"), 264 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"), 265 }; 266 267 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \ 268 sizeof(rte_txgbe_stats_strings[0])) 269 270 /* Per-priority statistics */ 271 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)} 272 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = { 273 UP_XSTAT(rx_up_packets), 274 UP_XSTAT(tx_up_packets), 275 UP_XSTAT(rx_up_bytes), 276 UP_XSTAT(tx_up_bytes), 277 UP_XSTAT(rx_up_drop_packets), 278 279 UP_XSTAT(tx_up_xon_packets), 280 UP_XSTAT(rx_up_xon_packets), 281 UP_XSTAT(tx_up_xoff_packets), 282 UP_XSTAT(rx_up_xoff_packets), 283 UP_XSTAT(rx_up_dropped), 284 UP_XSTAT(rx_up_mbuf_alloc_errors), 285 UP_XSTAT(tx_up_xon2off_packets), 286 }; 287 288 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \ 289 sizeof(rte_txgbe_up_strings[0])) 290 291 /* Per-queue statistics */ 292 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)} 293 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = { 294 QP_XSTAT(rx_qp_packets), 295 QP_XSTAT(tx_qp_packets), 296 QP_XSTAT(rx_qp_bytes), 297 QP_XSTAT(tx_qp_bytes), 298 QP_XSTAT(rx_qp_mc_packets), 299 }; 300 301 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \ 302 sizeof(rte_txgbe_qp_strings[0])) 303 304 static inline int 305 txgbe_is_sfp(struct txgbe_hw *hw) 306 { 307 switch (hw->phy.type) { 308 case txgbe_phy_sfp_avago: 309 case txgbe_phy_sfp_ftl: 310 case txgbe_phy_sfp_intel: 311 case txgbe_phy_sfp_unknown: 312 case txgbe_phy_sfp_tyco_passive: 313 case txgbe_phy_sfp_unknown_passive: 314 return 1; 315 default: 316 return 0; 317 } 318 } 319 320 static inline int32_t 321 txgbe_pf_reset_hw(struct txgbe_hw *hw) 322 { 323 uint32_t ctrl_ext; 324 int32_t status; 325 326 status = hw->mac.reset_hw(hw); 327 328 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 329 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 330 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 331 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 332 txgbe_flush(hw); 333 334 if (status == TXGBE_ERR_SFP_NOT_PRESENT) 335 status = 0; 336 return status; 337 } 338 339 static inline void 340 txgbe_enable_intr(struct rte_eth_dev *dev) 341 { 342 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 343 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 344 345 wr32(hw, TXGBE_IENMISC, intr->mask_misc); 346 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK); 347 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK); 348 txgbe_flush(hw); 349 } 350 351 static void 352 txgbe_disable_intr(struct txgbe_hw *hw) 353 { 354 PMD_INIT_FUNC_TRACE(); 355 356 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32); 357 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK); 358 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK); 359 txgbe_flush(hw); 360 } 361 362 static int 363 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 364 uint16_t queue_id, 365 uint8_t stat_idx, 366 uint8_t is_rx) 367 { 368 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 369 struct txgbe_stat_mappings *stat_mappings = 370 TXGBE_DEV_STAT_MAPPINGS(eth_dev); 371 uint32_t qsmr_mask = 0; 372 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 373 uint32_t q_map; 374 uint8_t n, offset; 375 376 if (hw->mac.type != txgbe_mac_raptor) 377 return -ENOSYS; 378 379 if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK) 380 return -EIO; 381 382 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 383 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 384 queue_id, stat_idx); 385 386 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 387 if (n >= TXGBE_NB_STAT_MAPPING) { 388 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 389 return -EIO; 390 } 391 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 392 393 /* Now clear any previous stat_idx set */ 394 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 395 if (!is_rx) 396 stat_mappings->tqsm[n] &= ~clearing_mask; 397 else 398 stat_mappings->rqsm[n] &= ~clearing_mask; 399 400 q_map = (uint32_t)stat_idx; 401 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 402 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 403 if (!is_rx) 404 stat_mappings->tqsm[n] |= qsmr_mask; 405 else 406 stat_mappings->rqsm[n] |= qsmr_mask; 407 408 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 409 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 410 queue_id, stat_idx); 411 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 412 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]); 413 return 0; 414 } 415 416 static void 417 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config) 418 { 419 int i; 420 u8 bwgp; 421 struct txgbe_dcb_tc_config *tc; 422 423 UNREFERENCED_PARAMETER(hw); 424 425 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX; 426 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX; 427 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX); 428 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 429 tc = &dcb_config->tc_config[i]; 430 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i; 431 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1); 432 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i; 433 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1); 434 tc->pfc = txgbe_dcb_pfc_disabled; 435 } 436 437 /* Initialize default user to priority mapping, UPx->TC0 */ 438 tc = &dcb_config->tc_config[0]; 439 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 440 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 441 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) { 442 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100; 443 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100; 444 } 445 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal; 446 dcb_config->pfc_mode_enable = false; 447 dcb_config->vt_mode = true; 448 dcb_config->round_robin_enable = false; 449 /* support all DCB capabilities */ 450 dcb_config->support.capabilities = 0xFF; 451 } 452 453 /* 454 * Ensure that all locks are released before first NVM or PHY access 455 */ 456 static void 457 txgbe_swfw_lock_reset(struct txgbe_hw *hw) 458 { 459 uint16_t mask; 460 461 /* 462 * These ones are more tricky since they are common to all ports; but 463 * swfw_sync retries last long enough (1s) to be almost sure that if 464 * lock can not be taken it is due to an improper lock of the 465 * semaphore. 466 */ 467 mask = TXGBE_MNGSEM_SWPHY | 468 TXGBE_MNGSEM_SWMBX | 469 TXGBE_MNGSEM_SWFLASH; 470 if (hw->mac.acquire_swfw_sync(hw, mask) < 0) 471 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 472 473 hw->mac.release_swfw_sync(hw, mask); 474 } 475 476 static int 477 txgbe_handle_devarg(__rte_unused const char *key, const char *value, 478 void *extra_args) 479 { 480 uint16_t *n = extra_args; 481 482 if (value == NULL || extra_args == NULL) 483 return -EINVAL; 484 485 *n = (uint16_t)strtoul(value, NULL, 10); 486 if (*n == USHRT_MAX && errno == ERANGE) 487 return -1; 488 489 return 0; 490 } 491 492 static void 493 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) 494 { 495 struct rte_kvargs *kvlist; 496 u16 auto_neg = 1; 497 u16 poll = 0; 498 u16 present = 0; 499 u16 sgmii = 0; 500 u16 ffe_set = 0; 501 u16 ffe_main = 27; 502 u16 ffe_pre = 8; 503 u16 ffe_post = 44; 504 505 if (devargs == NULL) 506 goto null; 507 508 kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments); 509 if (kvlist == NULL) 510 goto null; 511 512 rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO, 513 &txgbe_handle_devarg, &auto_neg); 514 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL, 515 &txgbe_handle_devarg, &poll); 516 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT, 517 &txgbe_handle_devarg, &present); 518 rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII, 519 &txgbe_handle_devarg, &sgmii); 520 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET, 521 &txgbe_handle_devarg, &ffe_set); 522 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN, 523 &txgbe_handle_devarg, &ffe_main); 524 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE, 525 &txgbe_handle_devarg, &ffe_pre); 526 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST, 527 &txgbe_handle_devarg, &ffe_post); 528 rte_kvargs_free(kvlist); 529 530 null: 531 hw->devarg.auto_neg = auto_neg; 532 hw->devarg.poll = poll; 533 hw->devarg.present = present; 534 hw->devarg.sgmii = sgmii; 535 hw->phy.ffe_set = ffe_set; 536 hw->phy.ffe_main = ffe_main; 537 hw->phy.ffe_pre = ffe_pre; 538 hw->phy.ffe_post = ffe_post; 539 } 540 541 static int 542 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 543 { 544 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 545 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 546 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev); 547 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev); 548 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev); 549 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 550 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev); 551 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 552 const struct rte_memzone *mz; 553 uint32_t ctrl_ext; 554 uint16_t csum; 555 int err, i, ret; 556 557 PMD_INIT_FUNC_TRACE(); 558 559 eth_dev->dev_ops = &txgbe_eth_dev_ops; 560 eth_dev->rx_queue_count = txgbe_dev_rx_queue_count; 561 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status; 562 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status; 563 eth_dev->rx_pkt_burst = &txgbe_recv_pkts; 564 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts; 565 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts; 566 567 /* 568 * For secondary processes, we don't initialise any further as primary 569 * has already done this work. Only check we don't need a different 570 * RX and TX function. 571 */ 572 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 573 struct txgbe_tx_queue *txq; 574 /* TX queue function in primary, set by last queue initialized 575 * Tx queue may not initialized by primary process 576 */ 577 if (eth_dev->data->tx_queues) { 578 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues; 579 txq = eth_dev->data->tx_queues[nb_tx_queues - 1]; 580 txgbe_set_tx_function(eth_dev, txq); 581 } else { 582 /* Use default TX function if we get here */ 583 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 584 "Using default TX function."); 585 } 586 587 txgbe_set_rx_function(eth_dev); 588 589 return 0; 590 } 591 592 rte_eth_copy_pci_info(eth_dev, pci_dev); 593 594 /* Vendor and Device ID need to be set before init of shared code */ 595 hw->device_id = pci_dev->id.device_id; 596 hw->vendor_id = pci_dev->id.vendor_id; 597 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 598 hw->allow_unsupported_sfp = 1; 599 600 /* Reserve memory for interrupt status block */ 601 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1, 602 16, TXGBE_ALIGN, SOCKET_ID_ANY); 603 if (mz == NULL) 604 return -ENOMEM; 605 606 hw->isb_dma = TMZ_PADDR(mz); 607 hw->isb_mem = TMZ_VADDR(mz); 608 609 txgbe_parse_devargs(hw, pci_dev->device.devargs); 610 /* Initialize the shared code (base driver) */ 611 err = txgbe_init_shared_code(hw); 612 if (err != 0) { 613 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err); 614 return -EIO; 615 } 616 617 /* Unlock any pending hardware semaphore */ 618 txgbe_swfw_lock_reset(hw); 619 620 #ifdef RTE_LIB_SECURITY 621 /* Initialize security_ctx only for primary process*/ 622 if (txgbe_ipsec_ctx_create(eth_dev)) 623 return -ENOMEM; 624 #endif 625 626 /* Initialize DCB configuration*/ 627 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config)); 628 txgbe_dcb_init(hw, dcb_config); 629 630 /* Get Hardware Flow Control setting */ 631 hw->fc.requested_mode = txgbe_fc_full; 632 hw->fc.current_mode = txgbe_fc_full; 633 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME; 634 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 635 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH; 636 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH; 637 } 638 hw->fc.send_xon = 1; 639 640 err = hw->rom.init_params(hw); 641 if (err != 0) { 642 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err); 643 return -EIO; 644 } 645 646 /* Make sure we have a good EEPROM before we read from it */ 647 err = hw->rom.validate_checksum(hw, &csum); 648 if (err != 0) { 649 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err); 650 return -EIO; 651 } 652 653 err = hw->mac.init_hw(hw); 654 655 /* 656 * Devices with copper phys will fail to initialise if txgbe_init_hw() 657 * is called too soon after the kernel driver unbinding/binding occurs. 658 * The failure occurs in txgbe_identify_phy() for all devices, 659 * but for non-copper devies, txgbe_identify_sfp_module() is 660 * also called. See txgbe_identify_phy(). The reason for the 661 * failure is not known, and only occuts when virtualisation features 662 * are disabled in the bios. A delay of 200ms was found to be enough by 663 * trial-and-error, and is doubled to be safe. 664 */ 665 if (err && hw->phy.media_type == txgbe_media_type_copper) { 666 rte_delay_ms(200); 667 err = hw->mac.init_hw(hw); 668 } 669 670 if (err == TXGBE_ERR_SFP_NOT_PRESENT) 671 err = 0; 672 673 if (err == TXGBE_ERR_EEPROM_VERSION) { 674 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 675 "LOM. Please be aware there may be issues associated " 676 "with your hardware."); 677 PMD_INIT_LOG(ERR, "If you are experiencing problems " 678 "please contact your hardware representative " 679 "who provided you with this hardware."); 680 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) { 681 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 682 } 683 if (err) { 684 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err); 685 return -EIO; 686 } 687 688 /* Reset the hw statistics */ 689 txgbe_dev_stats_reset(eth_dev); 690 691 /* disable interrupt */ 692 txgbe_disable_intr(hw); 693 694 /* Allocate memory for storing MAC addresses */ 695 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN * 696 hw->mac.num_rar_entries, 0); 697 if (eth_dev->data->mac_addrs == NULL) { 698 PMD_INIT_LOG(ERR, 699 "Failed to allocate %u bytes needed to store " 700 "MAC addresses", 701 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 702 return -ENOMEM; 703 } 704 705 /* Copy the permanent MAC address */ 706 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 707 ð_dev->data->mac_addrs[0]); 708 709 /* Allocate memory for storing hash filter MAC addresses */ 710 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe", 711 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0); 712 if (eth_dev->data->hash_mac_addrs == NULL) { 713 PMD_INIT_LOG(ERR, 714 "Failed to allocate %d bytes needed to store MAC addresses", 715 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC); 716 return -ENOMEM; 717 } 718 719 /* initialize the vfta */ 720 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 721 722 /* initialize the hw strip bitmap*/ 723 memset(hwstrip, 0, sizeof(*hwstrip)); 724 725 /* initialize PF if max_vfs not zero */ 726 ret = txgbe_pf_host_init(eth_dev); 727 if (ret) { 728 rte_free(eth_dev->data->mac_addrs); 729 eth_dev->data->mac_addrs = NULL; 730 rte_free(eth_dev->data->hash_mac_addrs); 731 eth_dev->data->hash_mac_addrs = NULL; 732 return ret; 733 } 734 735 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 736 /* let hardware know driver is loaded */ 737 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD; 738 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 739 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 740 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 741 txgbe_flush(hw); 742 743 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present) 744 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 745 (int)hw->mac.type, (int)hw->phy.type, 746 (int)hw->phy.sfp_type); 747 else 748 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 749 (int)hw->mac.type, (int)hw->phy.type); 750 751 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 752 eth_dev->data->port_id, pci_dev->id.vendor_id, 753 pci_dev->id.device_id); 754 755 rte_intr_callback_register(intr_handle, 756 txgbe_dev_interrupt_handler, eth_dev); 757 758 /* enable uio/vfio intr/eventfd mapping */ 759 rte_intr_enable(intr_handle); 760 761 /* enable support intr */ 762 txgbe_enable_intr(eth_dev); 763 764 /* initialize filter info */ 765 memset(filter_info, 0, 766 sizeof(struct txgbe_filter_info)); 767 768 /* initialize 5tuple filter list */ 769 TAILQ_INIT(&filter_info->fivetuple_list); 770 771 /* initialize flow director filter list & hash */ 772 txgbe_fdir_filter_init(eth_dev); 773 774 /* initialize l2 tunnel filter list & hash */ 775 txgbe_l2_tn_filter_init(eth_dev); 776 777 /* initialize flow filter lists */ 778 txgbe_filterlist_init(); 779 780 /* initialize bandwidth configuration info */ 781 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf)); 782 783 /* initialize Traffic Manager configuration */ 784 txgbe_tm_conf_init(eth_dev); 785 786 return 0; 787 } 788 789 static int 790 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev) 791 { 792 PMD_INIT_FUNC_TRACE(); 793 794 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 795 return 0; 796 797 txgbe_dev_close(eth_dev); 798 799 return 0; 800 } 801 802 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 803 { 804 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 805 struct txgbe_5tuple_filter *p_5tuple; 806 807 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 808 TAILQ_REMOVE(&filter_info->fivetuple_list, 809 p_5tuple, 810 entries); 811 rte_free(p_5tuple); 812 } 813 memset(filter_info->fivetuple_mask, 0, 814 sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE); 815 816 return 0; 817 } 818 819 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 820 { 821 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 822 struct txgbe_fdir_filter *fdir_filter; 823 824 rte_free(fdir_info->hash_map); 825 rte_hash_free(fdir_info->hash_handle); 826 827 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 828 TAILQ_REMOVE(&fdir_info->fdir_list, 829 fdir_filter, 830 entries); 831 rte_free(fdir_filter); 832 } 833 834 return 0; 835 } 836 837 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 838 { 839 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 840 struct txgbe_l2_tn_filter *l2_tn_filter; 841 842 rte_free(l2_tn_info->hash_map); 843 rte_hash_free(l2_tn_info->hash_handle); 844 845 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 846 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 847 l2_tn_filter, 848 entries); 849 rte_free(l2_tn_filter); 850 } 851 852 return 0; 853 } 854 855 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 856 { 857 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 858 char fdir_hash_name[RTE_HASH_NAMESIZE]; 859 struct rte_hash_parameters fdir_hash_params = { 860 .name = fdir_hash_name, 861 .entries = TXGBE_MAX_FDIR_FILTER_NUM, 862 .key_len = sizeof(struct txgbe_atr_input), 863 .hash_func = rte_hash_crc, 864 .hash_func_init_val = 0, 865 .socket_id = rte_socket_id(), 866 }; 867 868 TAILQ_INIT(&fdir_info->fdir_list); 869 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 870 "fdir_%s", TDEV_NAME(eth_dev)); 871 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 872 if (!fdir_info->hash_handle) { 873 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 874 return -EINVAL; 875 } 876 fdir_info->hash_map = rte_zmalloc("txgbe", 877 sizeof(struct txgbe_fdir_filter *) * 878 TXGBE_MAX_FDIR_FILTER_NUM, 879 0); 880 if (!fdir_info->hash_map) { 881 PMD_INIT_LOG(ERR, 882 "Failed to allocate memory for fdir hash map!"); 883 return -ENOMEM; 884 } 885 fdir_info->mask_added = FALSE; 886 887 return 0; 888 } 889 890 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 891 { 892 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 893 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 894 struct rte_hash_parameters l2_tn_hash_params = { 895 .name = l2_tn_hash_name, 896 .entries = TXGBE_MAX_L2_TN_FILTER_NUM, 897 .key_len = sizeof(struct txgbe_l2_tn_key), 898 .hash_func = rte_hash_crc, 899 .hash_func_init_val = 0, 900 .socket_id = rte_socket_id(), 901 }; 902 903 TAILQ_INIT(&l2_tn_info->l2_tn_list); 904 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 905 "l2_tn_%s", TDEV_NAME(eth_dev)); 906 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 907 if (!l2_tn_info->hash_handle) { 908 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 909 return -EINVAL; 910 } 911 l2_tn_info->hash_map = rte_zmalloc("txgbe", 912 sizeof(struct txgbe_l2_tn_filter *) * 913 TXGBE_MAX_L2_TN_FILTER_NUM, 914 0); 915 if (!l2_tn_info->hash_map) { 916 PMD_INIT_LOG(ERR, 917 "Failed to allocate memory for L2 TN hash map!"); 918 return -ENOMEM; 919 } 920 l2_tn_info->e_tag_en = FALSE; 921 l2_tn_info->e_tag_fwd_en = FALSE; 922 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 923 924 return 0; 925 } 926 927 static int 928 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 929 struct rte_pci_device *pci_dev) 930 { 931 return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 932 sizeof(struct txgbe_adapter), 933 eth_dev_pci_specific_init, pci_dev, 934 eth_txgbe_dev_init, NULL); 935 } 936 937 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev) 938 { 939 struct rte_eth_dev *ethdev; 940 941 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 942 if (!ethdev) 943 return 0; 944 945 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit); 946 } 947 948 static struct rte_pci_driver rte_txgbe_pmd = { 949 .id_table = pci_id_txgbe_map, 950 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | 951 RTE_PCI_DRV_INTR_LSC, 952 .probe = eth_txgbe_pci_probe, 953 .remove = eth_txgbe_pci_remove, 954 }; 955 956 static int 957 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 958 { 959 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 960 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 961 uint32_t vfta; 962 uint32_t vid_idx; 963 uint32_t vid_bit; 964 965 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F); 966 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F)); 967 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx)); 968 if (on) 969 vfta |= vid_bit; 970 else 971 vfta &= ~vid_bit; 972 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta); 973 974 /* update local VFTA copy */ 975 shadow_vfta->vfta[vid_idx] = vfta; 976 977 return 0; 978 } 979 980 static void 981 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 982 { 983 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 984 struct txgbe_rx_queue *rxq; 985 bool restart; 986 uint32_t rxcfg, rxbal, rxbah; 987 988 if (on) 989 txgbe_vlan_hw_strip_enable(dev, queue); 990 else 991 txgbe_vlan_hw_strip_disable(dev, queue); 992 993 rxq = dev->data->rx_queues[queue]; 994 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx)); 995 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx)); 996 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx)); 997 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 998 restart = (rxcfg & TXGBE_RXCFG_ENA) && 999 !(rxcfg & TXGBE_RXCFG_VLAN); 1000 rxcfg |= TXGBE_RXCFG_VLAN; 1001 } else { 1002 restart = (rxcfg & TXGBE_RXCFG_ENA) && 1003 (rxcfg & TXGBE_RXCFG_VLAN); 1004 rxcfg &= ~TXGBE_RXCFG_VLAN; 1005 } 1006 rxcfg &= ~TXGBE_RXCFG_ENA; 1007 1008 if (restart) { 1009 /* set vlan strip for ring */ 1010 txgbe_dev_rx_queue_stop(dev, queue); 1011 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal); 1012 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah); 1013 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg); 1014 txgbe_dev_rx_queue_start(dev, queue); 1015 } 1016 } 1017 1018 static int 1019 txgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1020 enum rte_vlan_type vlan_type, 1021 uint16_t tpid) 1022 { 1023 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1024 int ret = 0; 1025 uint32_t portctrl, vlan_ext, qinq; 1026 1027 portctrl = rd32(hw, TXGBE_PORTCTL); 1028 1029 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT); 1030 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ); 1031 switch (vlan_type) { 1032 case RTE_ETH_VLAN_TYPE_INNER: 1033 if (vlan_ext) { 1034 wr32m(hw, TXGBE_VLANCTL, 1035 TXGBE_VLANCTL_TPID_MASK, 1036 TXGBE_VLANCTL_TPID(tpid)); 1037 wr32m(hw, TXGBE_DMATXCTRL, 1038 TXGBE_DMATXCTRL_TPID_MASK, 1039 TXGBE_DMATXCTRL_TPID(tpid)); 1040 } else { 1041 ret = -ENOTSUP; 1042 PMD_DRV_LOG(ERR, "Inner type is not supported" 1043 " by single VLAN"); 1044 } 1045 1046 if (qinq) { 1047 wr32m(hw, TXGBE_TAGTPID(0), 1048 TXGBE_TAGTPID_LSB_MASK, 1049 TXGBE_TAGTPID_LSB(tpid)); 1050 } 1051 break; 1052 case RTE_ETH_VLAN_TYPE_OUTER: 1053 if (vlan_ext) { 1054 /* Only the high 16-bits is valid */ 1055 wr32m(hw, TXGBE_EXTAG, 1056 TXGBE_EXTAG_VLAN_MASK, 1057 TXGBE_EXTAG_VLAN(tpid)); 1058 } else { 1059 wr32m(hw, TXGBE_VLANCTL, 1060 TXGBE_VLANCTL_TPID_MASK, 1061 TXGBE_VLANCTL_TPID(tpid)); 1062 wr32m(hw, TXGBE_DMATXCTRL, 1063 TXGBE_DMATXCTRL_TPID_MASK, 1064 TXGBE_DMATXCTRL_TPID(tpid)); 1065 } 1066 1067 if (qinq) { 1068 wr32m(hw, TXGBE_TAGTPID(0), 1069 TXGBE_TAGTPID_MSB_MASK, 1070 TXGBE_TAGTPID_MSB(tpid)); 1071 } 1072 break; 1073 default: 1074 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1075 return -EINVAL; 1076 } 1077 1078 return ret; 1079 } 1080 1081 void 1082 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1083 { 1084 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1085 uint32_t vlnctrl; 1086 1087 PMD_INIT_FUNC_TRACE(); 1088 1089 /* Filter Table Disable */ 1090 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1091 vlnctrl &= ~TXGBE_VLANCTL_VFE; 1092 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1093 } 1094 1095 void 1096 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1097 { 1098 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1099 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 1100 uint32_t vlnctrl; 1101 uint16_t i; 1102 1103 PMD_INIT_FUNC_TRACE(); 1104 1105 /* Filter Table Enable */ 1106 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1107 vlnctrl &= ~TXGBE_VLANCTL_CFIENA; 1108 vlnctrl |= TXGBE_VLANCTL_VFE; 1109 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1110 1111 /* write whatever is in local vfta copy */ 1112 for (i = 0; i < TXGBE_VFTA_SIZE; i++) 1113 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]); 1114 } 1115 1116 void 1117 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1118 { 1119 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev); 1120 struct txgbe_rx_queue *rxq; 1121 1122 if (queue >= TXGBE_MAX_RX_QUEUE_NUM) 1123 return; 1124 1125 if (on) 1126 TXGBE_SET_HWSTRIP(hwstrip, queue); 1127 else 1128 TXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1129 1130 if (queue >= dev->data->nb_rx_queues) 1131 return; 1132 1133 rxq = dev->data->rx_queues[queue]; 1134 1135 if (on) { 1136 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED; 1137 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1138 } else { 1139 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN; 1140 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1141 } 1142 } 1143 1144 static void 1145 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1146 { 1147 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1148 uint32_t ctrl; 1149 1150 PMD_INIT_FUNC_TRACE(); 1151 1152 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1153 ctrl &= ~TXGBE_RXCFG_VLAN; 1154 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1155 1156 /* record those setting for HW strip per queue */ 1157 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 1158 } 1159 1160 static void 1161 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 1162 { 1163 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1164 uint32_t ctrl; 1165 1166 PMD_INIT_FUNC_TRACE(); 1167 1168 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1169 ctrl |= TXGBE_RXCFG_VLAN; 1170 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1171 1172 /* record those setting for HW strip per queue */ 1173 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 1174 } 1175 1176 static void 1177 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 1178 { 1179 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1180 uint32_t ctrl; 1181 1182 PMD_INIT_FUNC_TRACE(); 1183 1184 ctrl = rd32(hw, TXGBE_PORTCTL); 1185 ctrl &= ~TXGBE_PORTCTL_VLANEXT; 1186 wr32(hw, TXGBE_PORTCTL, ctrl); 1187 } 1188 1189 static void 1190 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 1191 { 1192 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1193 uint32_t ctrl; 1194 1195 PMD_INIT_FUNC_TRACE(); 1196 1197 ctrl = rd32(hw, TXGBE_PORTCTL); 1198 ctrl |= TXGBE_PORTCTL_VLANEXT; 1199 wr32(hw, TXGBE_PORTCTL, ctrl); 1200 } 1201 1202 static void 1203 txgbe_qinq_hw_strip_disable(struct rte_eth_dev *dev) 1204 { 1205 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1206 uint32_t ctrl; 1207 1208 PMD_INIT_FUNC_TRACE(); 1209 1210 ctrl = rd32(hw, TXGBE_PORTCTL); 1211 ctrl &= ~TXGBE_PORTCTL_QINQ; 1212 wr32(hw, TXGBE_PORTCTL, ctrl); 1213 } 1214 1215 static void 1216 txgbe_qinq_hw_strip_enable(struct rte_eth_dev *dev) 1217 { 1218 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1219 uint32_t ctrl; 1220 1221 PMD_INIT_FUNC_TRACE(); 1222 1223 ctrl = rd32(hw, TXGBE_PORTCTL); 1224 ctrl |= TXGBE_PORTCTL_QINQ | TXGBE_PORTCTL_VLANEXT; 1225 wr32(hw, TXGBE_PORTCTL, ctrl); 1226 } 1227 1228 void 1229 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 1230 { 1231 struct txgbe_rx_queue *rxq; 1232 uint16_t i; 1233 1234 PMD_INIT_FUNC_TRACE(); 1235 1236 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1237 rxq = dev->data->rx_queues[i]; 1238 1239 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 1240 txgbe_vlan_strip_queue_set(dev, i, 1); 1241 else 1242 txgbe_vlan_strip_queue_set(dev, i, 0); 1243 } 1244 } 1245 1246 void 1247 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 1248 { 1249 uint16_t i; 1250 struct rte_eth_rxmode *rxmode; 1251 struct txgbe_rx_queue *rxq; 1252 1253 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1254 rxmode = &dev->data->dev_conf.rxmode; 1255 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 1256 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1257 rxq = dev->data->rx_queues[i]; 1258 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1259 } 1260 else 1261 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1262 rxq = dev->data->rx_queues[i]; 1263 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1264 } 1265 } 1266 } 1267 1268 static int 1269 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 1270 { 1271 struct rte_eth_rxmode *rxmode; 1272 rxmode = &dev->data->dev_conf.rxmode; 1273 1274 if (mask & RTE_ETH_VLAN_STRIP_MASK) 1275 txgbe_vlan_hw_strip_config(dev); 1276 1277 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1278 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 1279 txgbe_vlan_hw_filter_enable(dev); 1280 else 1281 txgbe_vlan_hw_filter_disable(dev); 1282 } 1283 1284 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1285 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) 1286 txgbe_vlan_hw_extend_enable(dev); 1287 else 1288 txgbe_vlan_hw_extend_disable(dev); 1289 } 1290 1291 if (mask & RTE_ETH_QINQ_STRIP_MASK) { 1292 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) 1293 txgbe_qinq_hw_strip_enable(dev); 1294 else 1295 txgbe_qinq_hw_strip_disable(dev); 1296 } 1297 1298 return 0; 1299 } 1300 1301 static int 1302 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1303 { 1304 txgbe_config_vlan_strip_on_all_queues(dev, mask); 1305 1306 txgbe_vlan_offload_config(dev, mask); 1307 1308 return 0; 1309 } 1310 1311 static void 1312 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1313 { 1314 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1315 /* VLNCTL: enable vlan filtering and allow all vlan tags through */ 1316 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL); 1317 1318 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */ 1319 wr32(hw, TXGBE_VLANCTL, vlanctrl); 1320 } 1321 1322 static int 1323 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 1324 { 1325 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1326 1327 switch (nb_rx_q) { 1328 case 1: 1329 case 2: 1330 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_64_POOLS; 1331 break; 1332 case 4: 1333 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_32_POOLS; 1334 break; 1335 default: 1336 return -EINVAL; 1337 } 1338 1339 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1340 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1341 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 1342 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1343 return 0; 1344 } 1345 1346 static int 1347 txgbe_check_mq_mode(struct rte_eth_dev *dev) 1348 { 1349 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1350 uint16_t nb_rx_q = dev->data->nb_rx_queues; 1351 uint16_t nb_tx_q = dev->data->nb_tx_queues; 1352 1353 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 1354 /* check multi-queue mode */ 1355 switch (dev_conf->rxmode.mq_mode) { 1356 case RTE_ETH_MQ_RX_VMDQ_DCB: 1357 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 1358 break; 1359 case RTE_ETH_MQ_RX_VMDQ_DCB_RSS: 1360 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 1361 PMD_INIT_LOG(ERR, "SRIOV active," 1362 " unsupported mq_mode rx %d.", 1363 dev_conf->rxmode.mq_mode); 1364 return -EINVAL; 1365 case RTE_ETH_MQ_RX_RSS: 1366 case RTE_ETH_MQ_RX_VMDQ_RSS: 1367 dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_RSS; 1368 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 1369 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 1370 PMD_INIT_LOG(ERR, "SRIOV is active," 1371 " invalid queue number" 1372 " for VMDQ RSS, allowed" 1373 " value are 1, 2 or 4."); 1374 return -EINVAL; 1375 } 1376 break; 1377 case RTE_ETH_MQ_RX_VMDQ_ONLY: 1378 case RTE_ETH_MQ_RX_NONE: 1379 /* if nothing mq mode configure, use default scheme */ 1380 dev->data->dev_conf.rxmode.mq_mode = 1381 RTE_ETH_MQ_RX_VMDQ_ONLY; 1382 break; 1383 default: /* RTE_ETH_MQ_RX_DCB, RTE_ETH_MQ_RX_DCB_RSS or RTE_ETH_MQ_TX_DCB*/ 1384 /* SRIOV only works in VMDq enable mode */ 1385 PMD_INIT_LOG(ERR, "SRIOV is active," 1386 " wrong mq_mode rx %d.", 1387 dev_conf->rxmode.mq_mode); 1388 return -EINVAL; 1389 } 1390 1391 switch (dev_conf->txmode.mq_mode) { 1392 case RTE_ETH_MQ_TX_VMDQ_DCB: 1393 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 1394 dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_DCB; 1395 break; 1396 default: /* RTE_ETH_MQ_TX_VMDQ_ONLY or RTE_ETH_MQ_TX_NONE */ 1397 dev->data->dev_conf.txmode.mq_mode = 1398 RTE_ETH_MQ_TX_VMDQ_ONLY; 1399 break; 1400 } 1401 1402 /* check valid queue number */ 1403 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 1404 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 1405 PMD_INIT_LOG(ERR, "SRIOV is active," 1406 " nb_rx_q=%d nb_tx_q=%d queue number" 1407 " must be less than or equal to %d.", 1408 nb_rx_q, nb_tx_q, 1409 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 1410 return -EINVAL; 1411 } 1412 } else { 1413 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB_RSS) { 1414 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 1415 " not supported."); 1416 return -EINVAL; 1417 } 1418 /* check configuration for vmdb+dcb mode */ 1419 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB) { 1420 const struct rte_eth_vmdq_dcb_conf *conf; 1421 1422 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1423 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 1424 TXGBE_VMDQ_DCB_NB_QUEUES); 1425 return -EINVAL; 1426 } 1427 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 1428 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS || 1429 conf->nb_queue_pools == RTE_ETH_32_POOLS)) { 1430 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1431 " nb_queue_pools must be %d or %d.", 1432 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS); 1433 return -EINVAL; 1434 } 1435 } 1436 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) { 1437 const struct rte_eth_vmdq_dcb_tx_conf *conf; 1438 1439 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1440 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 1441 TXGBE_VMDQ_DCB_NB_QUEUES); 1442 return -EINVAL; 1443 } 1444 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 1445 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS || 1446 conf->nb_queue_pools == RTE_ETH_32_POOLS)) { 1447 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1448 " nb_queue_pools != %d and" 1449 " nb_queue_pools != %d.", 1450 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS); 1451 return -EINVAL; 1452 } 1453 } 1454 1455 /* For DCB mode check our configuration before we go further */ 1456 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_DCB) { 1457 const struct rte_eth_dcb_rx_conf *conf; 1458 1459 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 1460 if (!(conf->nb_tcs == RTE_ETH_4_TCS || 1461 conf->nb_tcs == RTE_ETH_8_TCS)) { 1462 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1463 " and nb_tcs != %d.", 1464 RTE_ETH_4_TCS, RTE_ETH_8_TCS); 1465 return -EINVAL; 1466 } 1467 } 1468 1469 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_DCB) { 1470 const struct rte_eth_dcb_tx_conf *conf; 1471 1472 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 1473 if (!(conf->nb_tcs == RTE_ETH_4_TCS || 1474 conf->nb_tcs == RTE_ETH_8_TCS)) { 1475 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1476 " and nb_tcs != %d.", 1477 RTE_ETH_4_TCS, RTE_ETH_8_TCS); 1478 return -EINVAL; 1479 } 1480 } 1481 } 1482 return 0; 1483 } 1484 1485 static int 1486 txgbe_dev_configure(struct rte_eth_dev *dev) 1487 { 1488 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1489 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1490 int ret; 1491 1492 PMD_INIT_FUNC_TRACE(); 1493 1494 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 1495 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 1496 1497 /* multiple queue mode checking */ 1498 ret = txgbe_check_mq_mode(dev); 1499 if (ret != 0) { 1500 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.", 1501 ret); 1502 return ret; 1503 } 1504 1505 /* set flag to update link status after init */ 1506 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 1507 1508 /* 1509 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 1510 * allocation Rx preconditions we will reset it. 1511 */ 1512 adapter->rx_bulk_alloc_allowed = true; 1513 1514 return 0; 1515 } 1516 1517 static void 1518 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 1519 { 1520 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1521 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1522 uint32_t gpie; 1523 1524 gpie = rd32(hw, TXGBE_GPIOINTEN); 1525 gpie |= TXGBE_GPIOBIT_6; 1526 wr32(hw, TXGBE_GPIOINTEN, gpie); 1527 intr->mask_misc |= TXGBE_ICRMISC_GPIO; 1528 intr->mask_misc |= TXGBE_ICRMISC_ANDONE; 1529 } 1530 1531 int 1532 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 1533 uint16_t tx_rate, uint64_t q_msk) 1534 { 1535 struct txgbe_hw *hw; 1536 struct txgbe_vf_info *vfinfo; 1537 struct rte_eth_link link; 1538 uint8_t nb_q_per_pool; 1539 uint32_t queue_stride; 1540 uint32_t queue_idx, idx = 0, vf_idx; 1541 uint32_t queue_end; 1542 uint16_t total_rate = 0; 1543 struct rte_pci_device *pci_dev; 1544 int ret; 1545 1546 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1547 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 1548 if (ret < 0) 1549 return ret; 1550 1551 if (vf >= pci_dev->max_vfs) 1552 return -EINVAL; 1553 1554 if (tx_rate > link.link_speed) 1555 return -EINVAL; 1556 1557 if (q_msk == 0) 1558 return 0; 1559 1560 hw = TXGBE_DEV_HW(dev); 1561 vfinfo = *(TXGBE_DEV_VFDATA(dev)); 1562 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1563 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1564 queue_idx = vf * queue_stride; 1565 queue_end = queue_idx + nb_q_per_pool - 1; 1566 if (queue_end >= hw->mac.max_tx_queues) 1567 return -EINVAL; 1568 1569 if (vfinfo) { 1570 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 1571 if (vf_idx == vf) 1572 continue; 1573 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 1574 idx++) 1575 total_rate += vfinfo[vf_idx].tx_rate[idx]; 1576 } 1577 } else { 1578 return -EINVAL; 1579 } 1580 1581 /* Store tx_rate for this vf. */ 1582 for (idx = 0; idx < nb_q_per_pool; idx++) { 1583 if (((uint64_t)0x1 << idx) & q_msk) { 1584 if (vfinfo[vf].tx_rate[idx] != tx_rate) 1585 vfinfo[vf].tx_rate[idx] = tx_rate; 1586 total_rate += tx_rate; 1587 } 1588 } 1589 1590 if (total_rate > dev->data->dev_link.link_speed) { 1591 /* Reset stored TX rate of the VF if it causes exceed 1592 * link speed. 1593 */ 1594 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 1595 return -EINVAL; 1596 } 1597 1598 /* Set ARBTXRATE of each queue/pool for vf X */ 1599 for (; queue_idx <= queue_end; queue_idx++) { 1600 if (0x1 & q_msk) 1601 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 1602 q_msk = q_msk >> 1; 1603 } 1604 1605 return 0; 1606 } 1607 1608 /* 1609 * Configure device link speed and setup link. 1610 * It returns 0 on success. 1611 */ 1612 static int 1613 txgbe_dev_start(struct rte_eth_dev *dev) 1614 { 1615 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1616 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 1617 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1618 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1619 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1620 uint32_t intr_vector = 0; 1621 int err; 1622 bool link_up = false, negotiate = 0; 1623 uint32_t speed = 0; 1624 uint32_t allowed_speeds = 0; 1625 int mask = 0; 1626 int status; 1627 uint16_t vf, idx; 1628 uint32_t *link_speeds; 1629 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1630 1631 PMD_INIT_FUNC_TRACE(); 1632 1633 /* Stop the link setup handler before resetting the HW. */ 1634 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1635 1636 /* disable uio/vfio intr/eventfd mapping */ 1637 rte_intr_disable(intr_handle); 1638 1639 /* stop adapter */ 1640 hw->adapter_stopped = 0; 1641 txgbe_stop_hw(hw); 1642 1643 /* reinitialize adapter 1644 * this calls reset and start 1645 */ 1646 hw->nb_rx_queues = dev->data->nb_rx_queues; 1647 hw->nb_tx_queues = dev->data->nb_tx_queues; 1648 status = txgbe_pf_reset_hw(hw); 1649 if (status != 0) 1650 return -1; 1651 hw->mac.start_hw(hw); 1652 hw->mac.get_link_status = true; 1653 hw->dev_start = true; 1654 1655 /* configure PF module if SRIOV enabled */ 1656 txgbe_pf_host_configure(dev); 1657 1658 txgbe_dev_phy_intr_setup(dev); 1659 1660 /* check and configure queue intr-vector mapping */ 1661 if ((rte_intr_cap_multiple(intr_handle) || 1662 !RTE_ETH_DEV_SRIOV(dev).active) && 1663 dev->data->dev_conf.intr_conf.rxq != 0) { 1664 intr_vector = dev->data->nb_rx_queues; 1665 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1666 return -1; 1667 } 1668 1669 if (rte_intr_dp_is_en(intr_handle)) { 1670 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 1671 dev->data->nb_rx_queues)) { 1672 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 1673 " intr_vec", dev->data->nb_rx_queues); 1674 return -ENOMEM; 1675 } 1676 } 1677 /* configure msix for sleep until rx interrupt */ 1678 txgbe_configure_msix(dev); 1679 1680 /* initialize transmission unit */ 1681 txgbe_dev_tx_init(dev); 1682 1683 /* This can fail when allocating mbufs for descriptor rings */ 1684 err = txgbe_dev_rx_init(dev); 1685 if (err) { 1686 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 1687 goto error; 1688 } 1689 1690 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 1691 RTE_ETH_VLAN_EXTEND_MASK; 1692 err = txgbe_vlan_offload_config(dev, mask); 1693 if (err) { 1694 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 1695 goto error; 1696 } 1697 1698 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) { 1699 /* Enable vlan filtering for VMDq */ 1700 txgbe_vmdq_vlan_hw_filter_enable(dev); 1701 } 1702 1703 /* Configure DCB hw */ 1704 txgbe_configure_pb(dev); 1705 txgbe_configure_port(dev); 1706 txgbe_configure_dcb(dev); 1707 1708 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1709 err = txgbe_fdir_configure(dev); 1710 if (err) 1711 goto error; 1712 } 1713 1714 /* Restore vf rate limit */ 1715 if (vfinfo != NULL) { 1716 for (vf = 0; vf < pci_dev->max_vfs; vf++) 1717 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 1718 if (vfinfo[vf].tx_rate[idx] != 0) 1719 txgbe_set_vf_rate_limit(dev, vf, 1720 vfinfo[vf].tx_rate[idx], 1721 1 << idx); 1722 } 1723 1724 err = txgbe_dev_rxtx_start(dev); 1725 if (err < 0) { 1726 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 1727 goto error; 1728 } 1729 1730 /* Skip link setup if loopback mode is enabled. */ 1731 if (hw->mac.type == txgbe_mac_raptor && 1732 dev->data->dev_conf.lpbk_mode) 1733 goto skip_link_setup; 1734 1735 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 1736 err = hw->mac.setup_sfp(hw); 1737 if (err) 1738 goto error; 1739 } 1740 1741 if (hw->phy.media_type == txgbe_media_type_copper) { 1742 /* Turn on the copper */ 1743 hw->phy.set_phy_power(hw, true); 1744 } else { 1745 /* Turn on the laser */ 1746 hw->mac.enable_tx_laser(hw); 1747 } 1748 1749 if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4) 1750 err = hw->mac.check_link(hw, &speed, &link_up, 0); 1751 if (err) 1752 goto error; 1753 dev->data->dev_link.link_status = link_up; 1754 1755 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate); 1756 if (err) 1757 goto error; 1758 1759 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G | 1760 RTE_ETH_LINK_SPEED_10G; 1761 1762 link_speeds = &dev->data->dev_conf.link_speeds; 1763 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { 1764 PMD_INIT_LOG(ERR, "Invalid link setting"); 1765 goto error; 1766 } 1767 1768 speed = 0x0; 1769 if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 1770 speed = (TXGBE_LINK_SPEED_100M_FULL | 1771 TXGBE_LINK_SPEED_1GB_FULL | 1772 TXGBE_LINK_SPEED_10GB_FULL); 1773 } else { 1774 if (*link_speeds & RTE_ETH_LINK_SPEED_10G) 1775 speed |= TXGBE_LINK_SPEED_10GB_FULL; 1776 if (*link_speeds & RTE_ETH_LINK_SPEED_5G) 1777 speed |= TXGBE_LINK_SPEED_5GB_FULL; 1778 if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G) 1779 speed |= TXGBE_LINK_SPEED_2_5GB_FULL; 1780 if (*link_speeds & RTE_ETH_LINK_SPEED_1G) 1781 speed |= TXGBE_LINK_SPEED_1GB_FULL; 1782 if (*link_speeds & RTE_ETH_LINK_SPEED_100M) 1783 speed |= TXGBE_LINK_SPEED_100M_FULL; 1784 } 1785 1786 err = hw->mac.setup_link(hw, speed, link_up); 1787 if (err) 1788 goto error; 1789 1790 skip_link_setup: 1791 1792 if (rte_intr_allow_others(intr_handle)) { 1793 txgbe_dev_misc_interrupt_setup(dev); 1794 /* check if lsc interrupt is enabled */ 1795 if (dev->data->dev_conf.intr_conf.lsc != 0) 1796 txgbe_dev_lsc_interrupt_setup(dev, TRUE); 1797 else 1798 txgbe_dev_lsc_interrupt_setup(dev, FALSE); 1799 txgbe_dev_macsec_interrupt_setup(dev); 1800 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 1801 } else { 1802 rte_intr_callback_unregister(intr_handle, 1803 txgbe_dev_interrupt_handler, dev); 1804 if (dev->data->dev_conf.intr_conf.lsc != 0) 1805 PMD_INIT_LOG(INFO, "lsc won't enable because of" 1806 " no intr multiplex"); 1807 } 1808 1809 /* check if rxq interrupt is enabled */ 1810 if (dev->data->dev_conf.intr_conf.rxq != 0 && 1811 rte_intr_dp_is_en(intr_handle)) 1812 txgbe_dev_rxq_interrupt_setup(dev); 1813 1814 /* enable uio/vfio intr/eventfd mapping */ 1815 rte_intr_enable(intr_handle); 1816 1817 /* resume enabled intr since hw reset */ 1818 txgbe_enable_intr(dev); 1819 txgbe_l2_tunnel_conf(dev); 1820 txgbe_filter_restore(dev); 1821 1822 if (tm_conf->root && !tm_conf->committed) 1823 PMD_DRV_LOG(WARNING, 1824 "please call hierarchy_commit() " 1825 "before starting the port"); 1826 1827 /* 1828 * Update link status right before return, because it may 1829 * start link configuration process in a separate thread. 1830 */ 1831 txgbe_dev_link_update(dev, 0); 1832 1833 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK); 1834 1835 txgbe_read_stats_registers(hw, hw_stats); 1836 hw->offset_loaded = 1; 1837 1838 return 0; 1839 1840 error: 1841 PMD_INIT_LOG(ERR, "failure in dev start: %d", err); 1842 txgbe_dev_clear_queues(dev); 1843 return -EIO; 1844 } 1845 1846 /* 1847 * Stop device: disable rx and tx functions to allow for reconfiguring. 1848 */ 1849 static int 1850 txgbe_dev_stop(struct rte_eth_dev *dev) 1851 { 1852 struct rte_eth_link link; 1853 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1854 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1855 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1856 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1857 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1858 int vf; 1859 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1860 1861 if (hw->adapter_stopped) 1862 return 0; 1863 1864 PMD_INIT_FUNC_TRACE(); 1865 1866 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1867 1868 /* disable interrupts */ 1869 txgbe_disable_intr(hw); 1870 1871 /* reset the NIC */ 1872 txgbe_pf_reset_hw(hw); 1873 hw->adapter_stopped = 0; 1874 1875 /* stop adapter */ 1876 txgbe_stop_hw(hw); 1877 1878 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 1879 vfinfo[vf].clear_to_send = false; 1880 1881 if (hw->phy.media_type == txgbe_media_type_copper) { 1882 /* Turn off the copper */ 1883 hw->phy.set_phy_power(hw, false); 1884 } else { 1885 /* Turn off the laser */ 1886 hw->mac.disable_tx_laser(hw); 1887 } 1888 1889 txgbe_dev_clear_queues(dev); 1890 1891 /* Clear stored conf */ 1892 dev->data->scattered_rx = 0; 1893 dev->data->lro = 0; 1894 1895 /* Clear recorded link status */ 1896 memset(&link, 0, sizeof(link)); 1897 rte_eth_linkstatus_set(dev, &link); 1898 1899 if (!rte_intr_allow_others(intr_handle)) 1900 /* resume to the default handler */ 1901 rte_intr_callback_register(intr_handle, 1902 txgbe_dev_interrupt_handler, 1903 (void *)dev); 1904 1905 /* Clean datapath event and queue/vec mapping */ 1906 rte_intr_efd_disable(intr_handle); 1907 rte_intr_vec_list_free(intr_handle); 1908 1909 /* reset hierarchy commit */ 1910 tm_conf->committed = false; 1911 1912 adapter->rss_reta_updated = 0; 1913 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK); 1914 1915 hw->adapter_stopped = true; 1916 dev->data->dev_started = 0; 1917 hw->dev_start = false; 1918 1919 return 0; 1920 } 1921 1922 /* 1923 * Set device link up: enable tx. 1924 */ 1925 static int 1926 txgbe_dev_set_link_up(struct rte_eth_dev *dev) 1927 { 1928 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1929 1930 if (hw->phy.media_type == txgbe_media_type_copper) { 1931 /* Turn on the copper */ 1932 hw->phy.set_phy_power(hw, true); 1933 } else { 1934 /* Turn on the laser */ 1935 hw->mac.enable_tx_laser(hw); 1936 txgbe_dev_link_update(dev, 0); 1937 } 1938 1939 return 0; 1940 } 1941 1942 /* 1943 * Set device link down: disable tx. 1944 */ 1945 static int 1946 txgbe_dev_set_link_down(struct rte_eth_dev *dev) 1947 { 1948 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1949 1950 if (hw->phy.media_type == txgbe_media_type_copper) { 1951 /* Turn off the copper */ 1952 hw->phy.set_phy_power(hw, false); 1953 } else { 1954 /* Turn off the laser */ 1955 hw->mac.disable_tx_laser(hw); 1956 txgbe_dev_link_update(dev, 0); 1957 } 1958 1959 return 0; 1960 } 1961 1962 /* 1963 * Reset and stop device. 1964 */ 1965 static int 1966 txgbe_dev_close(struct rte_eth_dev *dev) 1967 { 1968 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1969 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1970 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1971 int retries = 0; 1972 int ret; 1973 1974 PMD_INIT_FUNC_TRACE(); 1975 1976 txgbe_pf_reset_hw(hw); 1977 1978 ret = txgbe_dev_stop(dev); 1979 1980 txgbe_dev_free_queues(dev); 1981 1982 /* reprogram the RAR[0] in case user changed it. */ 1983 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true); 1984 1985 /* Unlock any pending hardware semaphore */ 1986 txgbe_swfw_lock_reset(hw); 1987 1988 /* disable uio intr before callback unregister */ 1989 rte_intr_disable(intr_handle); 1990 1991 do { 1992 ret = rte_intr_callback_unregister(intr_handle, 1993 txgbe_dev_interrupt_handler, dev); 1994 if (ret >= 0 || ret == -ENOENT) { 1995 break; 1996 } else if (ret != -EAGAIN) { 1997 PMD_INIT_LOG(ERR, 1998 "intr callback unregister failed: %d", 1999 ret); 2000 } 2001 rte_delay_ms(100); 2002 } while (retries++ < (10 + TXGBE_LINK_UP_TIME)); 2003 2004 /* cancel the delay handler before remove dev */ 2005 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev); 2006 2007 /* uninitialize PF if max_vfs not zero */ 2008 txgbe_pf_host_uninit(dev); 2009 2010 rte_free(dev->data->mac_addrs); 2011 dev->data->mac_addrs = NULL; 2012 2013 rte_free(dev->data->hash_mac_addrs); 2014 dev->data->hash_mac_addrs = NULL; 2015 2016 /* remove all the fdir filters & hash */ 2017 txgbe_fdir_filter_uninit(dev); 2018 2019 /* remove all the L2 tunnel filters & hash */ 2020 txgbe_l2_tn_filter_uninit(dev); 2021 2022 /* Remove all ntuple filters of the device */ 2023 txgbe_ntuple_filter_uninit(dev); 2024 2025 /* clear all the filters list */ 2026 txgbe_filterlist_flush(); 2027 2028 /* Remove all Traffic Manager configuration */ 2029 txgbe_tm_conf_uninit(dev); 2030 2031 #ifdef RTE_LIB_SECURITY 2032 rte_free(dev->security_ctx); 2033 #endif 2034 2035 return ret; 2036 } 2037 2038 /* 2039 * Reset PF device. 2040 */ 2041 static int 2042 txgbe_dev_reset(struct rte_eth_dev *dev) 2043 { 2044 int ret; 2045 2046 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2047 * its VF to make them align with it. The detailed notification 2048 * mechanism is PMD specific. As to txgbe PF, it is rather complex. 2049 * To avoid unexpected behavior in VF, currently reset of PF with 2050 * SR-IOV activation is not supported. It might be supported later. 2051 */ 2052 if (dev->data->sriov.active) 2053 return -ENOTSUP; 2054 2055 ret = eth_txgbe_dev_uninit(dev); 2056 if (ret) 2057 return ret; 2058 2059 ret = eth_txgbe_dev_init(dev, NULL); 2060 2061 return ret; 2062 } 2063 2064 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \ 2065 { \ 2066 uint32_t current_counter = rd32(hw, reg); \ 2067 if (current_counter < last_counter) \ 2068 current_counter += 0x100000000LL; \ 2069 if (!hw->offset_loaded) \ 2070 last_counter = current_counter; \ 2071 counter = current_counter - last_counter; \ 2072 counter &= 0xFFFFFFFFLL; \ 2073 } 2074 2075 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ 2076 { \ 2077 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \ 2078 uint64_t current_counter_msb = rd32(hw, reg_msb); \ 2079 uint64_t current_counter = (current_counter_msb << 32) | \ 2080 current_counter_lsb; \ 2081 if (current_counter < last_counter) \ 2082 current_counter += 0x1000000000LL; \ 2083 if (!hw->offset_loaded) \ 2084 last_counter = current_counter; \ 2085 counter = current_counter - last_counter; \ 2086 counter &= 0xFFFFFFFFFLL; \ 2087 } 2088 2089 void 2090 txgbe_read_stats_registers(struct txgbe_hw *hw, 2091 struct txgbe_hw_stats *hw_stats) 2092 { 2093 unsigned int i; 2094 2095 /* QP Stats */ 2096 for (i = 0; i < hw->nb_rx_queues; i++) { 2097 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i), 2098 hw->qp_last[i].rx_qp_packets, 2099 hw_stats->qp[i].rx_qp_packets); 2100 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i), 2101 hw->qp_last[i].rx_qp_bytes, 2102 hw_stats->qp[i].rx_qp_bytes); 2103 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i), 2104 hw->qp_last[i].rx_qp_mc_packets, 2105 hw_stats->qp[i].rx_qp_mc_packets); 2106 } 2107 2108 for (i = 0; i < hw->nb_tx_queues; i++) { 2109 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i), 2110 hw->qp_last[i].tx_qp_packets, 2111 hw_stats->qp[i].tx_qp_packets); 2112 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i), 2113 hw->qp_last[i].tx_qp_bytes, 2114 hw_stats->qp[i].tx_qp_bytes); 2115 } 2116 /* PB Stats */ 2117 for (i = 0; i < TXGBE_MAX_UP; i++) { 2118 hw_stats->up[i].rx_up_xon_packets += 2119 rd32(hw, TXGBE_PBRXUPXON(i)); 2120 hw_stats->up[i].rx_up_xoff_packets += 2121 rd32(hw, TXGBE_PBRXUPXOFF(i)); 2122 hw_stats->up[i].tx_up_xon_packets += 2123 rd32(hw, TXGBE_PBTXUPXON(i)); 2124 hw_stats->up[i].tx_up_xoff_packets += 2125 rd32(hw, TXGBE_PBTXUPXOFF(i)); 2126 hw_stats->up[i].tx_up_xon2off_packets += 2127 rd32(hw, TXGBE_PBTXUPOFF(i)); 2128 hw_stats->up[i].rx_up_dropped += 2129 rd32(hw, TXGBE_PBRXMISS(i)); 2130 } 2131 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON); 2132 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF); 2133 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON); 2134 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF); 2135 2136 /* DMA Stats */ 2137 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT); 2138 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT); 2139 2140 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL); 2141 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL); 2142 hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP); 2143 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP); 2144 2145 /* MAC Stats */ 2146 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL); 2147 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL); 2148 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL); 2149 2150 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL); 2151 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL); 2152 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL); 2153 2154 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL); 2155 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL); 2156 2157 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L); 2158 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L); 2159 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L); 2160 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L); 2161 hw_stats->rx_size_512_to_1023_packets += 2162 rd64(hw, TXGBE_MACRX512TO1023L); 2163 hw_stats->rx_size_1024_to_max_packets += 2164 rd64(hw, TXGBE_MACRX1024TOMAXL); 2165 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L); 2166 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L); 2167 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L); 2168 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L); 2169 hw_stats->tx_size_512_to_1023_packets += 2170 rd64(hw, TXGBE_MACTX512TO1023L); 2171 hw_stats->tx_size_1024_to_max_packets += 2172 rd64(hw, TXGBE_MACTX1024TOMAXL); 2173 2174 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL); 2175 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE); 2176 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER); 2177 2178 /* MNG Stats */ 2179 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS); 2180 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC); 2181 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG); 2182 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG); 2183 2184 /* FCoE Stats */ 2185 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC); 2186 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST); 2187 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC); 2188 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC); 2189 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC); 2190 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC); 2191 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC); 2192 2193 /* Flow Director Stats */ 2194 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH); 2195 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS); 2196 hw_stats->flow_director_added_filters += 2197 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED)); 2198 hw_stats->flow_director_removed_filters += 2199 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED)); 2200 hw_stats->flow_director_filter_add_errors += 2201 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL)); 2202 hw_stats->flow_director_filter_remove_errors += 2203 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL)); 2204 2205 /* MACsec Stats */ 2206 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT); 2207 hw_stats->tx_macsec_pkts_encrypted += 2208 rd32(hw, TXGBE_LSECTX_ENCPKT); 2209 hw_stats->tx_macsec_pkts_protected += 2210 rd32(hw, TXGBE_LSECTX_PROTPKT); 2211 hw_stats->tx_macsec_octets_encrypted += 2212 rd32(hw, TXGBE_LSECTX_ENCOCT); 2213 hw_stats->tx_macsec_octets_protected += 2214 rd32(hw, TXGBE_LSECTX_PROTOCT); 2215 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT); 2216 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT); 2217 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT); 2218 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT); 2219 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT); 2220 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT); 2221 hw_stats->rx_macsec_sc_pkts_unchecked += 2222 rd32(hw, TXGBE_LSECRX_UNCHKPKT); 2223 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT); 2224 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT); 2225 for (i = 0; i < 2; i++) { 2226 hw_stats->rx_macsec_sa_pkts_ok += 2227 rd32(hw, TXGBE_LSECRX_OKPKT(i)); 2228 hw_stats->rx_macsec_sa_pkts_invalid += 2229 rd32(hw, TXGBE_LSECRX_INVPKT(i)); 2230 hw_stats->rx_macsec_sa_pkts_notvalid += 2231 rd32(hw, TXGBE_LSECRX_BADPKT(i)); 2232 } 2233 hw_stats->rx_macsec_sa_pkts_unusedsa += 2234 rd32(hw, TXGBE_LSECRX_INVSAPKT); 2235 hw_stats->rx_macsec_sa_pkts_notusingsa += 2236 rd32(hw, TXGBE_LSECRX_BADSAPKT); 2237 2238 hw_stats->rx_total_missed_packets = 0; 2239 for (i = 0; i < TXGBE_MAX_UP; i++) { 2240 hw_stats->rx_total_missed_packets += 2241 hw_stats->up[i].rx_up_dropped; 2242 } 2243 } 2244 2245 static int 2246 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 2247 { 2248 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2249 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2250 struct txgbe_stat_mappings *stat_mappings = 2251 TXGBE_DEV_STAT_MAPPINGS(dev); 2252 uint32_t i, j; 2253 2254 txgbe_read_stats_registers(hw, hw_stats); 2255 2256 if (stats == NULL) 2257 return -EINVAL; 2258 2259 /* Fill out the rte_eth_stats statistics structure */ 2260 stats->ipackets = hw_stats->rx_packets; 2261 stats->ibytes = hw_stats->rx_bytes; 2262 stats->opackets = hw_stats->tx_packets; 2263 stats->obytes = hw_stats->tx_bytes; 2264 2265 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets)); 2266 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets)); 2267 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes)); 2268 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes)); 2269 memset(&stats->q_errors, 0, sizeof(stats->q_errors)); 2270 for (i = 0; i < TXGBE_MAX_QP; i++) { 2271 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG; 2272 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8; 2273 uint32_t q_map; 2274 2275 q_map = (stat_mappings->rqsm[n] >> offset) 2276 & QMAP_FIELD_RESERVED_BITS_MASK; 2277 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2278 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2279 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets; 2280 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes; 2281 2282 q_map = (stat_mappings->tqsm[n] >> offset) 2283 & QMAP_FIELD_RESERVED_BITS_MASK; 2284 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2285 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2286 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets; 2287 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes; 2288 } 2289 2290 /* Rx Errors */ 2291 stats->imissed = hw_stats->rx_total_missed_packets + 2292 hw_stats->rx_dma_drop; 2293 stats->ierrors = hw_stats->rx_crc_errors + 2294 hw_stats->rx_mac_short_packet_dropped + 2295 hw_stats->rx_length_errors + 2296 hw_stats->rx_undersize_errors + 2297 hw_stats->rx_oversize_errors + 2298 hw_stats->rx_drop_packets + 2299 hw_stats->rx_illegal_byte_errors + 2300 hw_stats->rx_error_bytes + 2301 hw_stats->rx_fragment_errors + 2302 hw_stats->rx_fcoe_crc_errors + 2303 hw_stats->rx_fcoe_mbuf_allocation_errors; 2304 2305 /* Tx Errors */ 2306 stats->oerrors = 0; 2307 return 0; 2308 } 2309 2310 static int 2311 txgbe_dev_stats_reset(struct rte_eth_dev *dev) 2312 { 2313 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2314 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2315 2316 /* HW registers are cleared on read */ 2317 hw->offset_loaded = 0; 2318 txgbe_dev_stats_get(dev, NULL); 2319 hw->offset_loaded = 1; 2320 2321 /* Reset software totals */ 2322 memset(hw_stats, 0, sizeof(*hw_stats)); 2323 2324 return 0; 2325 } 2326 2327 /* This function calculates the number of xstats based on the current config */ 2328 static unsigned 2329 txgbe_xstats_calc_num(struct rte_eth_dev *dev) 2330 { 2331 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues); 2332 return TXGBE_NB_HW_STATS + 2333 TXGBE_NB_UP_STATS * TXGBE_MAX_UP + 2334 TXGBE_NB_QP_STATS * nb_queues; 2335 } 2336 2337 static inline int 2338 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size) 2339 { 2340 int nb, st; 2341 2342 /* Extended stats from txgbe_hw_stats */ 2343 if (id < TXGBE_NB_HW_STATS) { 2344 snprintf(name, size, "[hw]%s", 2345 rte_txgbe_stats_strings[id].name); 2346 return 0; 2347 } 2348 id -= TXGBE_NB_HW_STATS; 2349 2350 /* Priority Stats */ 2351 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2352 nb = id / TXGBE_NB_UP_STATS; 2353 st = id % TXGBE_NB_UP_STATS; 2354 snprintf(name, size, "[p%u]%s", nb, 2355 rte_txgbe_up_strings[st].name); 2356 return 0; 2357 } 2358 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2359 2360 /* Queue Stats */ 2361 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2362 nb = id / TXGBE_NB_QP_STATS; 2363 st = id % TXGBE_NB_QP_STATS; 2364 snprintf(name, size, "[q%u]%s", nb, 2365 rte_txgbe_qp_strings[st].name); 2366 return 0; 2367 } 2368 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP; 2369 2370 return -(int)(id + 1); 2371 } 2372 2373 static inline int 2374 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset) 2375 { 2376 int nb, st; 2377 2378 /* Extended stats from txgbe_hw_stats */ 2379 if (id < TXGBE_NB_HW_STATS) { 2380 *offset = rte_txgbe_stats_strings[id].offset; 2381 return 0; 2382 } 2383 id -= TXGBE_NB_HW_STATS; 2384 2385 /* Priority Stats */ 2386 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2387 nb = id / TXGBE_NB_UP_STATS; 2388 st = id % TXGBE_NB_UP_STATS; 2389 *offset = rte_txgbe_up_strings[st].offset + 2390 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t)); 2391 return 0; 2392 } 2393 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2394 2395 /* Queue Stats */ 2396 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2397 nb = id / TXGBE_NB_QP_STATS; 2398 st = id % TXGBE_NB_QP_STATS; 2399 *offset = rte_txgbe_qp_strings[st].offset + 2400 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t)); 2401 return 0; 2402 } 2403 2404 return -1; 2405 } 2406 2407 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 2408 struct rte_eth_xstat_name *xstats_names, unsigned int limit) 2409 { 2410 unsigned int i, count; 2411 2412 count = txgbe_xstats_calc_num(dev); 2413 if (xstats_names == NULL) 2414 return count; 2415 2416 /* Note: limit >= cnt_stats checked upstream 2417 * in rte_eth_xstats_names() 2418 */ 2419 limit = min(limit, count); 2420 2421 /* Extended stats from txgbe_hw_stats */ 2422 for (i = 0; i < limit; i++) { 2423 if (txgbe_get_name_by_id(i, xstats_names[i].name, 2424 sizeof(xstats_names[i].name))) { 2425 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2426 break; 2427 } 2428 } 2429 2430 return i; 2431 } 2432 2433 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 2434 const uint64_t *ids, 2435 struct rte_eth_xstat_name *xstats_names, 2436 unsigned int limit) 2437 { 2438 unsigned int i; 2439 2440 if (ids == NULL) 2441 return txgbe_dev_xstats_get_names(dev, xstats_names, limit); 2442 2443 for (i = 0; i < limit; i++) { 2444 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name, 2445 sizeof(xstats_names[i].name))) { 2446 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2447 return -1; 2448 } 2449 } 2450 2451 return i; 2452 } 2453 2454 static int 2455 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 2456 unsigned int limit) 2457 { 2458 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2459 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2460 unsigned int i, count; 2461 2462 txgbe_read_stats_registers(hw, hw_stats); 2463 2464 /* If this is a reset xstats is NULL, and we have cleared the 2465 * registers by reading them. 2466 */ 2467 count = txgbe_xstats_calc_num(dev); 2468 if (xstats == NULL) 2469 return count; 2470 2471 limit = min(limit, txgbe_xstats_calc_num(dev)); 2472 2473 /* Extended stats from txgbe_hw_stats */ 2474 for (i = 0; i < limit; i++) { 2475 uint32_t offset = 0; 2476 2477 if (txgbe_get_offset_by_id(i, &offset)) { 2478 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2479 break; 2480 } 2481 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset); 2482 xstats[i].id = i; 2483 } 2484 2485 return i; 2486 } 2487 2488 static int 2489 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values, 2490 unsigned int limit) 2491 { 2492 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2493 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2494 unsigned int i, count; 2495 2496 txgbe_read_stats_registers(hw, hw_stats); 2497 2498 /* If this is a reset xstats is NULL, and we have cleared the 2499 * registers by reading them. 2500 */ 2501 count = txgbe_xstats_calc_num(dev); 2502 if (values == NULL) 2503 return count; 2504 2505 limit = min(limit, txgbe_xstats_calc_num(dev)); 2506 2507 /* Extended stats from txgbe_hw_stats */ 2508 for (i = 0; i < limit; i++) { 2509 uint32_t offset; 2510 2511 if (txgbe_get_offset_by_id(i, &offset)) { 2512 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2513 break; 2514 } 2515 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2516 } 2517 2518 return i; 2519 } 2520 2521 static int 2522 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 2523 uint64_t *values, unsigned int limit) 2524 { 2525 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2526 unsigned int i; 2527 2528 if (ids == NULL) 2529 return txgbe_dev_xstats_get_(dev, values, limit); 2530 2531 for (i = 0; i < limit; i++) { 2532 uint32_t offset; 2533 2534 if (txgbe_get_offset_by_id(ids[i], &offset)) { 2535 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2536 break; 2537 } 2538 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2539 } 2540 2541 return i; 2542 } 2543 2544 static int 2545 txgbe_dev_xstats_reset(struct rte_eth_dev *dev) 2546 { 2547 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2548 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2549 2550 /* HW registers are cleared on read */ 2551 hw->offset_loaded = 0; 2552 txgbe_read_stats_registers(hw, hw_stats); 2553 hw->offset_loaded = 1; 2554 2555 /* Reset software totals */ 2556 memset(hw_stats, 0, sizeof(*hw_stats)); 2557 2558 return 0; 2559 } 2560 2561 static int 2562 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2563 { 2564 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2565 u32 etrack_id; 2566 int ret; 2567 2568 hw->phy.get_fw_version(hw, &etrack_id); 2569 2570 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 2571 if (ret < 0) 2572 return -EINVAL; 2573 2574 ret += 1; /* add the size of '\0' */ 2575 if (fw_size < (size_t)ret) 2576 return ret; 2577 else 2578 return 0; 2579 } 2580 2581 static int 2582 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2583 { 2584 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2585 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2586 2587 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 2588 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 2589 dev_info->min_rx_bufsize = 1024; 2590 dev_info->max_rx_pktlen = 15872; 2591 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 2592 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC; 2593 dev_info->max_vfs = pci_dev->max_vfs; 2594 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS; 2595 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 2596 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 2597 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev); 2598 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) | 2599 dev_info->rx_queue_offload_capa); 2600 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev); 2601 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev); 2602 2603 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2604 .rx_thresh = { 2605 .pthresh = TXGBE_DEFAULT_RX_PTHRESH, 2606 .hthresh = TXGBE_DEFAULT_RX_HTHRESH, 2607 .wthresh = TXGBE_DEFAULT_RX_WTHRESH, 2608 }, 2609 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH, 2610 .rx_drop_en = 0, 2611 .offloads = 0, 2612 }; 2613 2614 dev_info->default_txconf = (struct rte_eth_txconf) { 2615 .tx_thresh = { 2616 .pthresh = TXGBE_DEFAULT_TX_PTHRESH, 2617 .hthresh = TXGBE_DEFAULT_TX_HTHRESH, 2618 .wthresh = TXGBE_DEFAULT_TX_WTHRESH, 2619 }, 2620 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH, 2621 .offloads = 0, 2622 }; 2623 2624 dev_info->rx_desc_lim = rx_desc_lim; 2625 dev_info->tx_desc_lim = tx_desc_lim; 2626 2627 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 2628 dev_info->reta_size = RTE_ETH_RSS_RETA_SIZE_128; 2629 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL; 2630 2631 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G; 2632 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100M; 2633 2634 /* Driver-preferred Rx/Tx parameters */ 2635 dev_info->default_rxportconf.burst_size = 32; 2636 dev_info->default_txportconf.burst_size = 32; 2637 dev_info->default_rxportconf.nb_queues = 1; 2638 dev_info->default_txportconf.nb_queues = 1; 2639 dev_info->default_rxportconf.ring_size = 256; 2640 dev_info->default_txportconf.ring_size = 256; 2641 2642 return 0; 2643 } 2644 2645 const uint32_t * 2646 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 2647 { 2648 if (dev->rx_pkt_burst == txgbe_recv_pkts || 2649 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc || 2650 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc || 2651 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc) 2652 return txgbe_get_supported_ptypes(); 2653 2654 return NULL; 2655 } 2656 2657 void 2658 txgbe_dev_setup_link_alarm_handler(void *param) 2659 { 2660 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 2661 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2662 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2663 u32 speed; 2664 bool autoneg = false; 2665 2666 speed = hw->phy.autoneg_advertised; 2667 if (!speed) 2668 hw->mac.get_link_capabilities(hw, &speed, &autoneg); 2669 2670 hw->mac.setup_link(hw, speed, true); 2671 2672 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2673 } 2674 2675 /* return 0 means link status changed, -1 means not changed */ 2676 int 2677 txgbe_dev_link_update_share(struct rte_eth_dev *dev, 2678 int wait_to_complete) 2679 { 2680 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2681 struct rte_eth_link link; 2682 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; 2683 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2684 bool link_up; 2685 int err; 2686 int wait = 1; 2687 2688 memset(&link, 0, sizeof(link)); 2689 link.link_status = RTE_ETH_LINK_DOWN; 2690 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 2691 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 2692 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2693 RTE_ETH_LINK_SPEED_FIXED); 2694 2695 hw->mac.get_link_status = true; 2696 2697 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG) 2698 return rte_eth_linkstatus_set(dev, &link); 2699 2700 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 2701 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 2702 wait = 0; 2703 2704 err = hw->mac.check_link(hw, &link_speed, &link_up, wait); 2705 2706 if (err != 0) { 2707 link.link_speed = RTE_ETH_SPEED_NUM_100M; 2708 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 2709 return rte_eth_linkstatus_set(dev, &link); 2710 } 2711 2712 if (link_up == 0) { 2713 if ((hw->subsystem_device_id & 0xFF) == 2714 TXGBE_DEV_ID_KR_KX_KX4) { 2715 hw->mac.bp_down_event(hw); 2716 } else if (hw->phy.media_type == txgbe_media_type_fiber) { 2717 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG; 2718 rte_eal_alarm_set(10, 2719 txgbe_dev_setup_link_alarm_handler, dev); 2720 } 2721 return rte_eth_linkstatus_set(dev, &link); 2722 } else if (!hw->dev_start) { 2723 return rte_eth_linkstatus_set(dev, &link); 2724 } 2725 2726 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2727 link.link_status = RTE_ETH_LINK_UP; 2728 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 2729 2730 switch (link_speed) { 2731 default: 2732 case TXGBE_LINK_SPEED_UNKNOWN: 2733 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 2734 link.link_speed = RTE_ETH_SPEED_NUM_100M; 2735 break; 2736 2737 case TXGBE_LINK_SPEED_100M_FULL: 2738 link.link_speed = RTE_ETH_SPEED_NUM_100M; 2739 break; 2740 2741 case TXGBE_LINK_SPEED_1GB_FULL: 2742 link.link_speed = RTE_ETH_SPEED_NUM_1G; 2743 break; 2744 2745 case TXGBE_LINK_SPEED_2_5GB_FULL: 2746 link.link_speed = RTE_ETH_SPEED_NUM_2_5G; 2747 break; 2748 2749 case TXGBE_LINK_SPEED_5GB_FULL: 2750 link.link_speed = RTE_ETH_SPEED_NUM_5G; 2751 break; 2752 2753 case TXGBE_LINK_SPEED_10GB_FULL: 2754 link.link_speed = RTE_ETH_SPEED_NUM_10G; 2755 break; 2756 } 2757 2758 return rte_eth_linkstatus_set(dev, &link); 2759 } 2760 2761 static int 2762 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 2763 { 2764 return txgbe_dev_link_update_share(dev, wait_to_complete); 2765 } 2766 2767 static int 2768 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 2769 { 2770 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2771 uint32_t fctrl; 2772 2773 fctrl = rd32(hw, TXGBE_PSRCTL); 2774 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP); 2775 wr32(hw, TXGBE_PSRCTL, fctrl); 2776 2777 return 0; 2778 } 2779 2780 static int 2781 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 2782 { 2783 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2784 uint32_t fctrl; 2785 2786 fctrl = rd32(hw, TXGBE_PSRCTL); 2787 fctrl &= (~TXGBE_PSRCTL_UCP); 2788 if (dev->data->all_multicast == 1) 2789 fctrl |= TXGBE_PSRCTL_MCP; 2790 else 2791 fctrl &= (~TXGBE_PSRCTL_MCP); 2792 wr32(hw, TXGBE_PSRCTL, fctrl); 2793 2794 return 0; 2795 } 2796 2797 static int 2798 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 2799 { 2800 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2801 uint32_t fctrl; 2802 2803 fctrl = rd32(hw, TXGBE_PSRCTL); 2804 fctrl |= TXGBE_PSRCTL_MCP; 2805 wr32(hw, TXGBE_PSRCTL, fctrl); 2806 2807 return 0; 2808 } 2809 2810 static int 2811 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 2812 { 2813 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2814 uint32_t fctrl; 2815 2816 if (dev->data->promiscuous == 1) 2817 return 0; /* must remain in all_multicast mode */ 2818 2819 fctrl = rd32(hw, TXGBE_PSRCTL); 2820 fctrl &= (~TXGBE_PSRCTL_MCP); 2821 wr32(hw, TXGBE_PSRCTL, fctrl); 2822 2823 return 0; 2824 } 2825 2826 /** 2827 * It clears the interrupt causes and enables the interrupt. 2828 * It will be called once only during nic initialized. 2829 * 2830 * @param dev 2831 * Pointer to struct rte_eth_dev. 2832 * @param on 2833 * Enable or Disable. 2834 * 2835 * @return 2836 * - On success, zero. 2837 * - On failure, a negative value. 2838 */ 2839 static int 2840 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 2841 { 2842 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2843 2844 txgbe_dev_link_status_print(dev); 2845 if (on) 2846 intr->mask_misc |= TXGBE_ICRMISC_LSC; 2847 else 2848 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 2849 2850 return 0; 2851 } 2852 2853 static int 2854 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev) 2855 { 2856 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2857 u64 mask; 2858 2859 mask = TXGBE_ICR_MASK; 2860 mask &= (1ULL << TXGBE_MISC_VEC_ID); 2861 intr->mask |= mask; 2862 intr->mask_misc |= TXGBE_ICRMISC_GPIO; 2863 intr->mask_misc |= TXGBE_ICRMISC_ANDONE; 2864 return 0; 2865 } 2866 2867 /** 2868 * It clears the interrupt causes and enables the interrupt. 2869 * It will be called once only during nic initialized. 2870 * 2871 * @param dev 2872 * Pointer to struct rte_eth_dev. 2873 * 2874 * @return 2875 * - On success, zero. 2876 * - On failure, a negative value. 2877 */ 2878 static int 2879 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 2880 { 2881 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2882 u64 mask; 2883 2884 mask = TXGBE_ICR_MASK; 2885 mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1); 2886 intr->mask |= mask; 2887 2888 return 0; 2889 } 2890 2891 /** 2892 * It clears the interrupt causes and enables the interrupt. 2893 * It will be called once only during nic initialized. 2894 * 2895 * @param dev 2896 * Pointer to struct rte_eth_dev. 2897 * 2898 * @return 2899 * - On success, zero. 2900 * - On failure, a negative value. 2901 */ 2902 static int 2903 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 2904 { 2905 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2906 2907 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC; 2908 2909 return 0; 2910 } 2911 2912 /* 2913 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update. 2914 * 2915 * @param dev 2916 * Pointer to struct rte_eth_dev. 2917 * 2918 * @return 2919 * - On success, zero. 2920 * - On failure, a negative value. 2921 */ 2922 static int 2923 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, 2924 struct rte_intr_handle *intr_handle) 2925 { 2926 uint32_t eicr; 2927 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2928 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2929 2930 if (rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_UIO && 2931 rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX) 2932 wr32(hw, TXGBE_PX_INTA, 1); 2933 2934 /* clear all cause mask */ 2935 txgbe_disable_intr(hw); 2936 2937 /* read-on-clear nic registers here */ 2938 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 2939 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 2940 2941 intr->flags = 0; 2942 2943 /* set flag for async link update */ 2944 if (eicr & TXGBE_ICRMISC_LSC) 2945 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 2946 2947 if (eicr & TXGBE_ICRMISC_ANDONE) 2948 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG; 2949 2950 if (eicr & TXGBE_ICRMISC_VFMBX) 2951 intr->flags |= TXGBE_FLAG_MAILBOX; 2952 2953 if (eicr & TXGBE_ICRMISC_LNKSEC) 2954 intr->flags |= TXGBE_FLAG_MACSEC; 2955 2956 if (eicr & TXGBE_ICRMISC_GPIO) 2957 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT; 2958 2959 return 0; 2960 } 2961 2962 /** 2963 * It gets and then prints the link status. 2964 * 2965 * @param dev 2966 * Pointer to struct rte_eth_dev. 2967 * 2968 * @return 2969 * - On success, zero. 2970 * - On failure, a negative value. 2971 */ 2972 static void 2973 txgbe_dev_link_status_print(struct rte_eth_dev *dev) 2974 { 2975 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2976 struct rte_eth_link link; 2977 2978 rte_eth_linkstatus_get(dev, &link); 2979 2980 if (link.link_status) { 2981 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 2982 (int)(dev->data->port_id), 2983 (unsigned int)link.link_speed, 2984 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ? 2985 "full-duplex" : "half-duplex"); 2986 } else { 2987 PMD_INIT_LOG(INFO, " Port %d: Link Down", 2988 (int)(dev->data->port_id)); 2989 } 2990 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 2991 pci_dev->addr.domain, 2992 pci_dev->addr.bus, 2993 pci_dev->addr.devid, 2994 pci_dev->addr.function); 2995 } 2996 2997 /* 2998 * It executes link_update after knowing an interrupt occurred. 2999 * 3000 * @param dev 3001 * Pointer to struct rte_eth_dev. 3002 * 3003 * @return 3004 * - On success, zero. 3005 * - On failure, a negative value. 3006 */ 3007 static int 3008 txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 3009 struct rte_intr_handle *intr_handle) 3010 { 3011 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 3012 int64_t timeout; 3013 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3014 3015 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 3016 3017 if (intr->flags & TXGBE_FLAG_MAILBOX) { 3018 txgbe_pf_mbx_process(dev); 3019 intr->flags &= ~TXGBE_FLAG_MAILBOX; 3020 } 3021 3022 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 3023 hw->phy.handle_lasi(hw); 3024 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 3025 } 3026 3027 if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) { 3028 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) { 3029 hw->mac.kr_handle(hw); 3030 intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG; 3031 } 3032 } 3033 3034 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 3035 struct rte_eth_link link; 3036 3037 /*get the link status before link update, for predicting later*/ 3038 rte_eth_linkstatus_get(dev, &link); 3039 3040 txgbe_dev_link_update(dev, 0); 3041 3042 /* likely to up */ 3043 if (!link.link_status) 3044 /* handle it 1 sec later, wait it being stable */ 3045 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT; 3046 /* likely to down */ 3047 else if ((hw->subsystem_device_id & 0xFF) == 3048 TXGBE_DEV_ID_KR_KX_KX4 && 3049 hw->devarg.auto_neg == 1) 3050 /* handle it 2 sec later for backplane AN73 */ 3051 timeout = 2000; 3052 else 3053 /* handle it 4 sec later, wait it being stable */ 3054 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT; 3055 3056 txgbe_dev_link_status_print(dev); 3057 if (rte_eal_alarm_set(timeout * 1000, 3058 txgbe_dev_interrupt_delayed_handler, 3059 (void *)dev) < 0) { 3060 PMD_DRV_LOG(ERR, "Error setting alarm"); 3061 } else { 3062 /* only disable lsc interrupt */ 3063 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 3064 3065 intr->mask_orig = intr->mask; 3066 /* only disable all misc interrupts */ 3067 intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID); 3068 } 3069 } 3070 3071 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 3072 txgbe_enable_intr(dev); 3073 rte_intr_enable(intr_handle); 3074 3075 return 0; 3076 } 3077 3078 /** 3079 * Interrupt handler which shall be registered for alarm callback for delayed 3080 * handling specific interrupt to wait for the stable nic state. As the 3081 * NIC interrupt state is not stable for txgbe after link is just down, 3082 * it needs to wait 4 seconds to get the stable status. 3083 * 3084 * @param handle 3085 * Pointer to interrupt handle. 3086 * @param param 3087 * The address of parameter (struct rte_eth_dev *) registered before. 3088 * 3089 * @return 3090 * void 3091 */ 3092 static void 3093 txgbe_dev_interrupt_delayed_handler(void *param) 3094 { 3095 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3096 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3097 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3098 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 3099 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3100 uint32_t eicr; 3101 3102 txgbe_disable_intr(hw); 3103 3104 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 3105 if (eicr & TXGBE_ICRMISC_VFMBX) 3106 txgbe_pf_mbx_process(dev); 3107 3108 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 3109 hw->phy.handle_lasi(hw); 3110 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 3111 } 3112 3113 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 3114 txgbe_dev_link_update(dev, 0); 3115 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE; 3116 txgbe_dev_link_status_print(dev); 3117 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 3118 NULL); 3119 } 3120 3121 if (intr->flags & TXGBE_FLAG_MACSEC) { 3122 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 3123 NULL); 3124 intr->flags &= ~TXGBE_FLAG_MACSEC; 3125 } 3126 3127 /* restore original mask */ 3128 intr->mask_misc |= TXGBE_ICRMISC_LSC; 3129 3130 intr->mask = intr->mask_orig; 3131 intr->mask_orig = 0; 3132 3133 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 3134 txgbe_enable_intr(dev); 3135 rte_intr_enable(intr_handle); 3136 } 3137 3138 /** 3139 * Interrupt handler triggered by NIC for handling 3140 * specific interrupt. 3141 * 3142 * @param handle 3143 * Pointer to interrupt handle. 3144 * @param param 3145 * The address of parameter (struct rte_eth_dev *) registered before. 3146 * 3147 * @return 3148 * void 3149 */ 3150 static void 3151 txgbe_dev_interrupt_handler(void *param) 3152 { 3153 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3154 3155 txgbe_dev_interrupt_get_status(dev, dev->intr_handle); 3156 txgbe_dev_interrupt_action(dev, dev->intr_handle); 3157 } 3158 3159 static int 3160 txgbe_dev_led_on(struct rte_eth_dev *dev) 3161 { 3162 struct txgbe_hw *hw; 3163 3164 hw = TXGBE_DEV_HW(dev); 3165 return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP; 3166 } 3167 3168 static int 3169 txgbe_dev_led_off(struct rte_eth_dev *dev) 3170 { 3171 struct txgbe_hw *hw; 3172 3173 hw = TXGBE_DEV_HW(dev); 3174 return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP; 3175 } 3176 3177 static int 3178 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3179 { 3180 struct txgbe_hw *hw; 3181 uint32_t mflcn_reg; 3182 uint32_t fccfg_reg; 3183 int rx_pause; 3184 int tx_pause; 3185 3186 hw = TXGBE_DEV_HW(dev); 3187 3188 fc_conf->pause_time = hw->fc.pause_time; 3189 fc_conf->high_water = hw->fc.high_water[0]; 3190 fc_conf->low_water = hw->fc.low_water[0]; 3191 fc_conf->send_xon = hw->fc.send_xon; 3192 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 3193 3194 /* 3195 * Return rx_pause status according to actual setting of 3196 * RXFCCFG register. 3197 */ 3198 mflcn_reg = rd32(hw, TXGBE_RXFCCFG); 3199 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC)) 3200 rx_pause = 1; 3201 else 3202 rx_pause = 0; 3203 3204 /* 3205 * Return tx_pause status according to actual setting of 3206 * TXFCCFG register. 3207 */ 3208 fccfg_reg = rd32(hw, TXGBE_TXFCCFG); 3209 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC)) 3210 tx_pause = 1; 3211 else 3212 tx_pause = 0; 3213 3214 if (rx_pause && tx_pause) 3215 fc_conf->mode = RTE_ETH_FC_FULL; 3216 else if (rx_pause) 3217 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 3218 else if (tx_pause) 3219 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 3220 else 3221 fc_conf->mode = RTE_ETH_FC_NONE; 3222 3223 return 0; 3224 } 3225 3226 static int 3227 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3228 { 3229 struct txgbe_hw *hw; 3230 int err; 3231 uint32_t rx_buf_size; 3232 uint32_t max_high_water; 3233 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3234 txgbe_fc_none, 3235 txgbe_fc_rx_pause, 3236 txgbe_fc_tx_pause, 3237 txgbe_fc_full 3238 }; 3239 3240 PMD_INIT_FUNC_TRACE(); 3241 3242 hw = TXGBE_DEV_HW(dev); 3243 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0)); 3244 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3245 3246 /* 3247 * At least reserve one Ethernet frame for watermark 3248 * high_water/low_water in kilo bytes for txgbe 3249 */ 3250 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3251 if (fc_conf->high_water > max_high_water || 3252 fc_conf->high_water < fc_conf->low_water) { 3253 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3254 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3255 return -EINVAL; 3256 } 3257 3258 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode]; 3259 hw->fc.pause_time = fc_conf->pause_time; 3260 hw->fc.high_water[0] = fc_conf->high_water; 3261 hw->fc.low_water[0] = fc_conf->low_water; 3262 hw->fc.send_xon = fc_conf->send_xon; 3263 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 3264 3265 err = txgbe_fc_enable(hw); 3266 3267 /* Not negotiated is not an error case */ 3268 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) { 3269 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK, 3270 (fc_conf->mac_ctrl_frame_fwd 3271 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP)); 3272 txgbe_flush(hw); 3273 3274 return 0; 3275 } 3276 3277 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err); 3278 return -EIO; 3279 } 3280 3281 static int 3282 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 3283 struct rte_eth_pfc_conf *pfc_conf) 3284 { 3285 int err; 3286 uint32_t rx_buf_size; 3287 uint32_t max_high_water; 3288 uint8_t tc_num; 3289 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 }; 3290 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3291 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 3292 3293 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3294 txgbe_fc_none, 3295 txgbe_fc_rx_pause, 3296 txgbe_fc_tx_pause, 3297 txgbe_fc_full 3298 }; 3299 3300 PMD_INIT_FUNC_TRACE(); 3301 3302 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map); 3303 tc_num = map[pfc_conf->priority]; 3304 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num)); 3305 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3306 /* 3307 * At least reserve one Ethernet frame for watermark 3308 * high_water/low_water in kilo bytes for txgbe 3309 */ 3310 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3311 if (pfc_conf->fc.high_water > max_high_water || 3312 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) { 3313 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3314 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3315 return -EINVAL; 3316 } 3317 3318 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode]; 3319 hw->fc.pause_time = pfc_conf->fc.pause_time; 3320 hw->fc.send_xon = pfc_conf->fc.send_xon; 3321 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 3322 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 3323 3324 err = txgbe_dcb_pfc_enable(hw, tc_num); 3325 3326 /* Not negotiated is not an error case */ 3327 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) 3328 return 0; 3329 3330 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err); 3331 return -EIO; 3332 } 3333 3334 int 3335 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 3336 struct rte_eth_rss_reta_entry64 *reta_conf, 3337 uint16_t reta_size) 3338 { 3339 uint8_t i, j, mask; 3340 uint32_t reta; 3341 uint16_t idx, shift; 3342 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 3343 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3344 3345 PMD_INIT_FUNC_TRACE(); 3346 3347 if (!txgbe_rss_update_sp(hw->mac.type)) { 3348 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 3349 "NIC."); 3350 return -ENOTSUP; 3351 } 3352 3353 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) { 3354 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3355 "(%d) doesn't match the number hardware can supported " 3356 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128); 3357 return -EINVAL; 3358 } 3359 3360 for (i = 0; i < reta_size; i += 4) { 3361 idx = i / RTE_ETH_RETA_GROUP_SIZE; 3362 shift = i % RTE_ETH_RETA_GROUP_SIZE; 3363 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3364 if (!mask) 3365 continue; 3366 3367 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3368 for (j = 0; j < 4; j++) { 3369 if (RS8(mask, j, 0x1)) { 3370 reta &= ~(MS32(8 * j, 0xFF)); 3371 reta |= LS32(reta_conf[idx].reta[shift + j], 3372 8 * j, 0xFF); 3373 } 3374 } 3375 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta); 3376 } 3377 adapter->rss_reta_updated = 1; 3378 3379 return 0; 3380 } 3381 3382 int 3383 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 3384 struct rte_eth_rss_reta_entry64 *reta_conf, 3385 uint16_t reta_size) 3386 { 3387 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3388 uint8_t i, j, mask; 3389 uint32_t reta; 3390 uint16_t idx, shift; 3391 3392 PMD_INIT_FUNC_TRACE(); 3393 3394 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) { 3395 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3396 "(%d) doesn't match the number hardware can supported " 3397 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128); 3398 return -EINVAL; 3399 } 3400 3401 for (i = 0; i < reta_size; i += 4) { 3402 idx = i / RTE_ETH_RETA_GROUP_SIZE; 3403 shift = i % RTE_ETH_RETA_GROUP_SIZE; 3404 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3405 if (!mask) 3406 continue; 3407 3408 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3409 for (j = 0; j < 4; j++) { 3410 if (RS8(mask, j, 0x1)) 3411 reta_conf[idx].reta[shift + j] = 3412 (uint16_t)RS32(reta, 8 * j, 0xFF); 3413 } 3414 } 3415 3416 return 0; 3417 } 3418 3419 static int 3420 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 3421 uint32_t index, uint32_t pool) 3422 { 3423 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3424 uint32_t enable_addr = 1; 3425 3426 return txgbe_set_rar(hw, index, mac_addr->addr_bytes, 3427 pool, enable_addr); 3428 } 3429 3430 static void 3431 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 3432 { 3433 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3434 3435 txgbe_clear_rar(hw, index); 3436 } 3437 3438 static int 3439 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 3440 { 3441 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3442 3443 txgbe_remove_rar(dev, 0); 3444 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 3445 3446 return 0; 3447 } 3448 3449 static int 3450 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3451 { 3452 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3453 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 3454 struct rte_eth_dev_data *dev_data = dev->data; 3455 3456 /* If device is started, refuse mtu that requires the support of 3457 * scattered packets when this feature has not been enabled before. 3458 */ 3459 if (dev_data->dev_started && !dev_data->scattered_rx && 3460 (frame_size + 2 * RTE_VLAN_HLEN > 3461 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 3462 PMD_INIT_LOG(ERR, "Stop port first."); 3463 return -EINVAL; 3464 } 3465 3466 if (hw->mode) 3467 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3468 TXGBE_FRAME_SIZE_MAX); 3469 else 3470 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3471 TXGBE_FRMSZ_MAX(frame_size)); 3472 3473 return 0; 3474 } 3475 3476 static uint32_t 3477 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr) 3478 { 3479 uint32_t vector = 0; 3480 3481 switch (hw->mac.mc_filter_type) { 3482 case 0: /* use bits [47:36] of the address */ 3483 vector = ((uc_addr->addr_bytes[4] >> 4) | 3484 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 3485 break; 3486 case 1: /* use bits [46:35] of the address */ 3487 vector = ((uc_addr->addr_bytes[4] >> 3) | 3488 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 3489 break; 3490 case 2: /* use bits [45:34] of the address */ 3491 vector = ((uc_addr->addr_bytes[4] >> 2) | 3492 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 3493 break; 3494 case 3: /* use bits [43:32] of the address */ 3495 vector = ((uc_addr->addr_bytes[4]) | 3496 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 3497 break; 3498 default: /* Invalid mc_filter_type */ 3499 break; 3500 } 3501 3502 /* vector can only be 12-bits or boundary will be exceeded */ 3503 vector &= 0xFFF; 3504 return vector; 3505 } 3506 3507 static int 3508 txgbe_uc_hash_table_set(struct rte_eth_dev *dev, 3509 struct rte_ether_addr *mac_addr, uint8_t on) 3510 { 3511 uint32_t vector; 3512 uint32_t uta_idx; 3513 uint32_t reg_val; 3514 uint32_t uta_mask; 3515 uint32_t psrctl; 3516 3517 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3518 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3519 3520 /* The UTA table only exists on pf hardware */ 3521 if (hw->mac.type < txgbe_mac_raptor) 3522 return -ENOTSUP; 3523 3524 vector = txgbe_uta_vector(hw, mac_addr); 3525 uta_idx = (vector >> 5) & 0x7F; 3526 uta_mask = 0x1UL << (vector & 0x1F); 3527 3528 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask)) 3529 return 0; 3530 3531 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx)); 3532 if (on) { 3533 uta_info->uta_in_use++; 3534 reg_val |= uta_mask; 3535 uta_info->uta_shadow[uta_idx] |= uta_mask; 3536 } else { 3537 uta_info->uta_in_use--; 3538 reg_val &= ~uta_mask; 3539 uta_info->uta_shadow[uta_idx] &= ~uta_mask; 3540 } 3541 3542 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val); 3543 3544 psrctl = rd32(hw, TXGBE_PSRCTL); 3545 if (uta_info->uta_in_use > 0) 3546 psrctl |= TXGBE_PSRCTL_UCHFENA; 3547 else 3548 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3549 3550 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3551 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3552 wr32(hw, TXGBE_PSRCTL, psrctl); 3553 3554 return 0; 3555 } 3556 3557 static int 3558 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 3559 { 3560 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3561 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3562 uint32_t psrctl; 3563 int i; 3564 3565 /* The UTA table only exists on pf hardware */ 3566 if (hw->mac.type < txgbe_mac_raptor) 3567 return -ENOTSUP; 3568 3569 if (on) { 3570 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3571 uta_info->uta_shadow[i] = ~0; 3572 wr32(hw, TXGBE_UCADDRTBL(i), ~0); 3573 } 3574 } else { 3575 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3576 uta_info->uta_shadow[i] = 0; 3577 wr32(hw, TXGBE_UCADDRTBL(i), 0); 3578 } 3579 } 3580 3581 psrctl = rd32(hw, TXGBE_PSRCTL); 3582 if (on) 3583 psrctl |= TXGBE_PSRCTL_UCHFENA; 3584 else 3585 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3586 3587 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3588 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3589 wr32(hw, TXGBE_PSRCTL, psrctl); 3590 3591 return 0; 3592 } 3593 3594 uint32_t 3595 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 3596 { 3597 uint32_t new_val = orig_val; 3598 3599 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_UNTAG) 3600 new_val |= TXGBE_POOLETHCTL_UTA; 3601 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_MC) 3602 new_val |= TXGBE_POOLETHCTL_MCHA; 3603 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_UC) 3604 new_val |= TXGBE_POOLETHCTL_UCHA; 3605 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_BROADCAST) 3606 new_val |= TXGBE_POOLETHCTL_BCA; 3607 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_MULTICAST) 3608 new_val |= TXGBE_POOLETHCTL_MCP; 3609 3610 return new_val; 3611 } 3612 3613 static int 3614 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 3615 { 3616 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3617 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3618 uint32_t mask; 3619 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3620 3621 if (queue_id < 32) { 3622 mask = rd32(hw, TXGBE_IMS(0)); 3623 mask &= (1 << queue_id); 3624 wr32(hw, TXGBE_IMS(0), mask); 3625 } else if (queue_id < 64) { 3626 mask = rd32(hw, TXGBE_IMS(1)); 3627 mask &= (1 << (queue_id - 32)); 3628 wr32(hw, TXGBE_IMS(1), mask); 3629 } 3630 rte_intr_enable(intr_handle); 3631 3632 return 0; 3633 } 3634 3635 static int 3636 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 3637 { 3638 uint32_t mask; 3639 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3640 3641 if (queue_id < 32) { 3642 mask = rd32(hw, TXGBE_IMS(0)); 3643 mask &= ~(1 << queue_id); 3644 wr32(hw, TXGBE_IMS(0), mask); 3645 } else if (queue_id < 64) { 3646 mask = rd32(hw, TXGBE_IMS(1)); 3647 mask &= ~(1 << (queue_id - 32)); 3648 wr32(hw, TXGBE_IMS(1), mask); 3649 } 3650 3651 return 0; 3652 } 3653 3654 /** 3655 * set the IVAR registers, mapping interrupt causes to vectors 3656 * @param hw 3657 * pointer to txgbe_hw struct 3658 * @direction 3659 * 0 for Rx, 1 for Tx, -1 for other causes 3660 * @queue 3661 * queue to map the corresponding interrupt to 3662 * @msix_vector 3663 * the vector to map to the corresponding queue 3664 */ 3665 void 3666 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction, 3667 uint8_t queue, uint8_t msix_vector) 3668 { 3669 uint32_t tmp, idx; 3670 3671 if (direction == -1) { 3672 /* other causes */ 3673 msix_vector |= TXGBE_IVARMISC_VLD; 3674 idx = 0; 3675 tmp = rd32(hw, TXGBE_IVARMISC); 3676 tmp &= ~(0xFF << idx); 3677 tmp |= (msix_vector << idx); 3678 wr32(hw, TXGBE_IVARMISC, tmp); 3679 } else { 3680 /* rx or tx causes */ 3681 /* Workaround for ICR lost */ 3682 idx = ((16 * (queue & 1)) + (8 * direction)); 3683 tmp = rd32(hw, TXGBE_IVAR(queue >> 1)); 3684 tmp &= ~(0xFF << idx); 3685 tmp |= (msix_vector << idx); 3686 wr32(hw, TXGBE_IVAR(queue >> 1), tmp); 3687 } 3688 } 3689 3690 /** 3691 * Sets up the hardware to properly generate MSI-X interrupts 3692 * @hw 3693 * board private structure 3694 */ 3695 static void 3696 txgbe_configure_msix(struct rte_eth_dev *dev) 3697 { 3698 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3699 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3700 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3701 uint32_t queue_id, base = TXGBE_MISC_VEC_ID; 3702 uint32_t vec = TXGBE_MISC_VEC_ID; 3703 uint32_t gpie; 3704 3705 /* won't configure msix register if no mapping is done 3706 * between intr vector and event fd 3707 * but if misx has been enabled already, need to configure 3708 * auto clean, auto mask and throttling. 3709 */ 3710 gpie = rd32(hw, TXGBE_GPIE); 3711 if (!rte_intr_dp_is_en(intr_handle) && 3712 !(gpie & TXGBE_GPIE_MSIX)) 3713 return; 3714 3715 if (rte_intr_allow_others(intr_handle)) { 3716 base = TXGBE_RX_VEC_START; 3717 vec = base; 3718 } 3719 3720 /* setup GPIE for MSI-x mode */ 3721 gpie = rd32(hw, TXGBE_GPIE); 3722 gpie |= TXGBE_GPIE_MSIX; 3723 wr32(hw, TXGBE_GPIE, gpie); 3724 3725 /* Populate the IVAR table and set the ITR values to the 3726 * corresponding register. 3727 */ 3728 if (rte_intr_dp_is_en(intr_handle)) { 3729 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 3730 queue_id++) { 3731 /* by default, 1:1 mapping */ 3732 txgbe_set_ivar_map(hw, 0, queue_id, vec); 3733 rte_intr_vec_list_index_set(intr_handle, 3734 queue_id, vec); 3735 if (vec < base + rte_intr_nb_efd_get(intr_handle) 3736 - 1) 3737 vec++; 3738 } 3739 3740 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 3741 } 3742 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID), 3743 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 3744 | TXGBE_ITR_WRDSA); 3745 } 3746 3747 int 3748 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 3749 uint16_t queue_idx, uint16_t tx_rate) 3750 { 3751 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3752 uint32_t bcnrc_val; 3753 3754 if (queue_idx >= hw->mac.max_tx_queues) 3755 return -EINVAL; 3756 3757 if (tx_rate != 0) { 3758 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate); 3759 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2); 3760 } else { 3761 bcnrc_val = 0; 3762 } 3763 3764 /* 3765 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW 3766 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 3767 */ 3768 wr32(hw, TXGBE_ARBTXMMW, 0x14); 3769 3770 /* Set ARBTXRATE of queue X */ 3771 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx); 3772 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val); 3773 txgbe_flush(hw); 3774 3775 return 0; 3776 } 3777 3778 int 3779 txgbe_syn_filter_set(struct rte_eth_dev *dev, 3780 struct rte_eth_syn_filter *filter, 3781 bool add) 3782 { 3783 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3784 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3785 uint32_t syn_info; 3786 uint32_t synqf; 3787 3788 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 3789 return -EINVAL; 3790 3791 syn_info = filter_info->syn_info; 3792 3793 if (add) { 3794 if (syn_info & TXGBE_SYNCLS_ENA) 3795 return -EINVAL; 3796 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue); 3797 synqf |= TXGBE_SYNCLS_ENA; 3798 3799 if (filter->hig_pri) 3800 synqf |= TXGBE_SYNCLS_HIPRIO; 3801 else 3802 synqf &= ~TXGBE_SYNCLS_HIPRIO; 3803 } else { 3804 synqf = rd32(hw, TXGBE_SYNCLS); 3805 if (!(syn_info & TXGBE_SYNCLS_ENA)) 3806 return -ENOENT; 3807 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA); 3808 } 3809 3810 filter_info->syn_info = synqf; 3811 wr32(hw, TXGBE_SYNCLS, synqf); 3812 txgbe_flush(hw); 3813 return 0; 3814 } 3815 3816 static inline enum txgbe_5tuple_protocol 3817 convert_protocol_type(uint8_t protocol_value) 3818 { 3819 if (protocol_value == IPPROTO_TCP) 3820 return TXGBE_5TF_PROT_TCP; 3821 else if (protocol_value == IPPROTO_UDP) 3822 return TXGBE_5TF_PROT_UDP; 3823 else if (protocol_value == IPPROTO_SCTP) 3824 return TXGBE_5TF_PROT_SCTP; 3825 else 3826 return TXGBE_5TF_PROT_NONE; 3827 } 3828 3829 /* inject a 5-tuple filter to HW */ 3830 static inline void 3831 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 3832 struct txgbe_5tuple_filter *filter) 3833 { 3834 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3835 int i; 3836 uint32_t ftqf, sdpqf; 3837 uint32_t l34timir = 0; 3838 uint32_t mask = TXGBE_5TFCTL0_MASK; 3839 3840 i = filter->index; 3841 sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port)); 3842 sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port)); 3843 3844 ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto); 3845 ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority); 3846 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 3847 mask &= ~TXGBE_5TFCTL0_MSADDR; 3848 if (filter->filter_info.dst_ip_mask == 0) 3849 mask &= ~TXGBE_5TFCTL0_MDADDR; 3850 if (filter->filter_info.src_port_mask == 0) 3851 mask &= ~TXGBE_5TFCTL0_MSPORT; 3852 if (filter->filter_info.dst_port_mask == 0) 3853 mask &= ~TXGBE_5TFCTL0_MDPORT; 3854 if (filter->filter_info.proto_mask == 0) 3855 mask &= ~TXGBE_5TFCTL0_MPROTO; 3856 ftqf |= mask; 3857 ftqf |= TXGBE_5TFCTL0_MPOOL; 3858 ftqf |= TXGBE_5TFCTL0_ENA; 3859 3860 wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip)); 3861 wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip)); 3862 wr32(hw, TXGBE_5TFPORT(i), sdpqf); 3863 wr32(hw, TXGBE_5TFCTL0(i), ftqf); 3864 3865 l34timir |= TXGBE_5TFCTL1_QP(filter->queue); 3866 wr32(hw, TXGBE_5TFCTL1(i), l34timir); 3867 } 3868 3869 /* 3870 * add a 5tuple filter 3871 * 3872 * @param 3873 * dev: Pointer to struct rte_eth_dev. 3874 * index: the index the filter allocates. 3875 * filter: pointer to the filter that will be added. 3876 * rx_queue: the queue id the filter assigned to. 3877 * 3878 * @return 3879 * - On success, zero. 3880 * - On failure, a negative value. 3881 */ 3882 static int 3883 txgbe_add_5tuple_filter(struct rte_eth_dev *dev, 3884 struct txgbe_5tuple_filter *filter) 3885 { 3886 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3887 int i, idx, shift; 3888 3889 /* 3890 * look for an unused 5tuple filter index, 3891 * and insert the filter to list. 3892 */ 3893 for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) { 3894 idx = i / (sizeof(uint32_t) * NBBY); 3895 shift = i % (sizeof(uint32_t) * NBBY); 3896 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 3897 filter_info->fivetuple_mask[idx] |= 1 << shift; 3898 filter->index = i; 3899 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 3900 filter, 3901 entries); 3902 break; 3903 } 3904 } 3905 if (i >= TXGBE_MAX_FTQF_FILTERS) { 3906 PMD_DRV_LOG(ERR, "5tuple filters are full."); 3907 return -ENOSYS; 3908 } 3909 3910 txgbe_inject_5tuple_filter(dev, filter); 3911 3912 return 0; 3913 } 3914 3915 /* 3916 * remove a 5tuple filter 3917 * 3918 * @param 3919 * dev: Pointer to struct rte_eth_dev. 3920 * filter: the pointer of the filter will be removed. 3921 */ 3922 static void 3923 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 3924 struct txgbe_5tuple_filter *filter) 3925 { 3926 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3927 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3928 uint16_t index = filter->index; 3929 3930 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 3931 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 3932 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 3933 rte_free(filter); 3934 3935 wr32(hw, TXGBE_5TFDADDR(index), 0); 3936 wr32(hw, TXGBE_5TFSADDR(index), 0); 3937 wr32(hw, TXGBE_5TFPORT(index), 0); 3938 wr32(hw, TXGBE_5TFCTL0(index), 0); 3939 wr32(hw, TXGBE_5TFCTL1(index), 0); 3940 } 3941 3942 static inline struct txgbe_5tuple_filter * 3943 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list, 3944 struct txgbe_5tuple_filter_info *key) 3945 { 3946 struct txgbe_5tuple_filter *it; 3947 3948 TAILQ_FOREACH(it, filter_list, entries) { 3949 if (memcmp(key, &it->filter_info, 3950 sizeof(struct txgbe_5tuple_filter_info)) == 0) { 3951 return it; 3952 } 3953 } 3954 return NULL; 3955 } 3956 3957 /* translate elements in struct rte_eth_ntuple_filter 3958 * to struct txgbe_5tuple_filter_info 3959 */ 3960 static inline int 3961 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 3962 struct txgbe_5tuple_filter_info *filter_info) 3963 { 3964 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM || 3965 filter->priority > TXGBE_5TUPLE_MAX_PRI || 3966 filter->priority < TXGBE_5TUPLE_MIN_PRI) 3967 return -EINVAL; 3968 3969 switch (filter->dst_ip_mask) { 3970 case UINT32_MAX: 3971 filter_info->dst_ip_mask = 0; 3972 filter_info->dst_ip = filter->dst_ip; 3973 break; 3974 case 0: 3975 filter_info->dst_ip_mask = 1; 3976 break; 3977 default: 3978 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 3979 return -EINVAL; 3980 } 3981 3982 switch (filter->src_ip_mask) { 3983 case UINT32_MAX: 3984 filter_info->src_ip_mask = 0; 3985 filter_info->src_ip = filter->src_ip; 3986 break; 3987 case 0: 3988 filter_info->src_ip_mask = 1; 3989 break; 3990 default: 3991 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 3992 return -EINVAL; 3993 } 3994 3995 switch (filter->dst_port_mask) { 3996 case UINT16_MAX: 3997 filter_info->dst_port_mask = 0; 3998 filter_info->dst_port = filter->dst_port; 3999 break; 4000 case 0: 4001 filter_info->dst_port_mask = 1; 4002 break; 4003 default: 4004 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 4005 return -EINVAL; 4006 } 4007 4008 switch (filter->src_port_mask) { 4009 case UINT16_MAX: 4010 filter_info->src_port_mask = 0; 4011 filter_info->src_port = filter->src_port; 4012 break; 4013 case 0: 4014 filter_info->src_port_mask = 1; 4015 break; 4016 default: 4017 PMD_DRV_LOG(ERR, "invalid src_port mask."); 4018 return -EINVAL; 4019 } 4020 4021 switch (filter->proto_mask) { 4022 case UINT8_MAX: 4023 filter_info->proto_mask = 0; 4024 filter_info->proto = 4025 convert_protocol_type(filter->proto); 4026 break; 4027 case 0: 4028 filter_info->proto_mask = 1; 4029 break; 4030 default: 4031 PMD_DRV_LOG(ERR, "invalid protocol mask."); 4032 return -EINVAL; 4033 } 4034 4035 filter_info->priority = (uint8_t)filter->priority; 4036 return 0; 4037 } 4038 4039 /* 4040 * add or delete a ntuple filter 4041 * 4042 * @param 4043 * dev: Pointer to struct rte_eth_dev. 4044 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 4045 * add: if true, add filter, if false, remove filter 4046 * 4047 * @return 4048 * - On success, zero. 4049 * - On failure, a negative value. 4050 */ 4051 int 4052 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 4053 struct rte_eth_ntuple_filter *ntuple_filter, 4054 bool add) 4055 { 4056 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4057 struct txgbe_5tuple_filter_info filter_5tuple; 4058 struct txgbe_5tuple_filter *filter; 4059 int ret; 4060 4061 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 4062 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 4063 return -EINVAL; 4064 } 4065 4066 memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info)); 4067 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 4068 if (ret < 0) 4069 return ret; 4070 4071 filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 4072 &filter_5tuple); 4073 if (filter != NULL && add) { 4074 PMD_DRV_LOG(ERR, "filter exists."); 4075 return -EEXIST; 4076 } 4077 if (filter == NULL && !add) { 4078 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4079 return -ENOENT; 4080 } 4081 4082 if (add) { 4083 filter = rte_zmalloc("txgbe_5tuple_filter", 4084 sizeof(struct txgbe_5tuple_filter), 0); 4085 if (filter == NULL) 4086 return -ENOMEM; 4087 rte_memcpy(&filter->filter_info, 4088 &filter_5tuple, 4089 sizeof(struct txgbe_5tuple_filter_info)); 4090 filter->queue = ntuple_filter->queue; 4091 ret = txgbe_add_5tuple_filter(dev, filter); 4092 if (ret < 0) { 4093 rte_free(filter); 4094 return ret; 4095 } 4096 } else { 4097 txgbe_remove_5tuple_filter(dev, filter); 4098 } 4099 4100 return 0; 4101 } 4102 4103 int 4104 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 4105 struct rte_eth_ethertype_filter *filter, 4106 bool add) 4107 { 4108 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4109 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4110 uint32_t etqf = 0; 4111 uint32_t etqs = 0; 4112 int ret; 4113 struct txgbe_ethertype_filter ethertype_filter; 4114 4115 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 4116 return -EINVAL; 4117 4118 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 4119 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 4120 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 4121 " ethertype filter.", filter->ether_type); 4122 return -EINVAL; 4123 } 4124 4125 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 4126 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 4127 return -EINVAL; 4128 } 4129 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 4130 PMD_DRV_LOG(ERR, "drop option is unsupported."); 4131 return -EINVAL; 4132 } 4133 4134 ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 4135 if (ret >= 0 && add) { 4136 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 4137 filter->ether_type); 4138 return -EEXIST; 4139 } 4140 if (ret < 0 && !add) { 4141 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 4142 filter->ether_type); 4143 return -ENOENT; 4144 } 4145 4146 if (add) { 4147 etqf = TXGBE_ETFLT_ENA; 4148 etqf |= TXGBE_ETFLT_ETID(filter->ether_type); 4149 etqs |= TXGBE_ETCLS_QPID(filter->queue); 4150 etqs |= TXGBE_ETCLS_QENA; 4151 4152 ethertype_filter.ethertype = filter->ether_type; 4153 ethertype_filter.etqf = etqf; 4154 ethertype_filter.etqs = etqs; 4155 ethertype_filter.conf = FALSE; 4156 ret = txgbe_ethertype_filter_insert(filter_info, 4157 ðertype_filter); 4158 if (ret < 0) { 4159 PMD_DRV_LOG(ERR, "ethertype filters are full."); 4160 return -ENOSPC; 4161 } 4162 } else { 4163 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 4164 if (ret < 0) 4165 return -ENOSYS; 4166 } 4167 wr32(hw, TXGBE_ETFLT(ret), etqf); 4168 wr32(hw, TXGBE_ETCLS(ret), etqs); 4169 txgbe_flush(hw); 4170 4171 return 0; 4172 } 4173 4174 static int 4175 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev, 4176 const struct rte_flow_ops **ops) 4177 { 4178 *ops = &txgbe_flow_ops; 4179 return 0; 4180 } 4181 4182 static u8 * 4183 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw, 4184 u8 **mc_addr_ptr, u32 *vmdq) 4185 { 4186 u8 *mc_addr; 4187 4188 *vmdq = 0; 4189 mc_addr = *mc_addr_ptr; 4190 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 4191 return mc_addr; 4192 } 4193 4194 int 4195 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 4196 struct rte_ether_addr *mc_addr_set, 4197 uint32_t nb_mc_addr) 4198 { 4199 struct txgbe_hw *hw; 4200 u8 *mc_addr_list; 4201 4202 hw = TXGBE_DEV_HW(dev); 4203 mc_addr_list = (u8 *)mc_addr_set; 4204 return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 4205 txgbe_dev_addr_list_itr, TRUE); 4206 } 4207 4208 static uint64_t 4209 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 4210 { 4211 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4212 uint64_t systime_cycles; 4213 4214 systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL); 4215 systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32; 4216 4217 return systime_cycles; 4218 } 4219 4220 static uint64_t 4221 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4222 { 4223 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4224 uint64_t rx_tstamp_cycles; 4225 4226 /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */ 4227 rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL); 4228 rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32; 4229 4230 return rx_tstamp_cycles; 4231 } 4232 4233 static uint64_t 4234 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4235 { 4236 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4237 uint64_t tx_tstamp_cycles; 4238 4239 /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */ 4240 tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL); 4241 tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32; 4242 4243 return tx_tstamp_cycles; 4244 } 4245 4246 static void 4247 txgbe_start_timecounters(struct rte_eth_dev *dev) 4248 { 4249 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4250 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4251 struct rte_eth_link link; 4252 uint32_t incval = 0; 4253 uint32_t shift = 0; 4254 4255 /* Get current link speed. */ 4256 txgbe_dev_link_update(dev, 1); 4257 rte_eth_linkstatus_get(dev, &link); 4258 4259 switch (link.link_speed) { 4260 case RTE_ETH_SPEED_NUM_100M: 4261 incval = TXGBE_INCVAL_100; 4262 shift = TXGBE_INCVAL_SHIFT_100; 4263 break; 4264 case RTE_ETH_SPEED_NUM_1G: 4265 incval = TXGBE_INCVAL_1GB; 4266 shift = TXGBE_INCVAL_SHIFT_1GB; 4267 break; 4268 case RTE_ETH_SPEED_NUM_10G: 4269 default: 4270 incval = TXGBE_INCVAL_10GB; 4271 shift = TXGBE_INCVAL_SHIFT_10GB; 4272 break; 4273 } 4274 4275 wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2)); 4276 4277 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 4278 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4279 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4280 4281 adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4282 adapter->systime_tc.cc_shift = shift; 4283 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 4284 4285 adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4286 adapter->rx_tstamp_tc.cc_shift = shift; 4287 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4288 4289 adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4290 adapter->tx_tstamp_tc.cc_shift = shift; 4291 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4292 } 4293 4294 static int 4295 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 4296 { 4297 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4298 4299 adapter->systime_tc.nsec += delta; 4300 adapter->rx_tstamp_tc.nsec += delta; 4301 adapter->tx_tstamp_tc.nsec += delta; 4302 4303 return 0; 4304 } 4305 4306 static int 4307 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 4308 { 4309 uint64_t ns; 4310 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4311 4312 ns = rte_timespec_to_ns(ts); 4313 /* Set the timecounters to a new value. */ 4314 adapter->systime_tc.nsec = ns; 4315 adapter->rx_tstamp_tc.nsec = ns; 4316 adapter->tx_tstamp_tc.nsec = ns; 4317 4318 return 0; 4319 } 4320 4321 static int 4322 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 4323 { 4324 uint64_t ns, systime_cycles; 4325 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4326 4327 systime_cycles = txgbe_read_systime_cyclecounter(dev); 4328 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 4329 *ts = rte_ns_to_timespec(ns); 4330 4331 return 0; 4332 } 4333 4334 static int 4335 txgbe_timesync_enable(struct rte_eth_dev *dev) 4336 { 4337 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4338 uint32_t tsync_ctl; 4339 4340 /* Stop the timesync system time. */ 4341 wr32(hw, TXGBE_TSTIMEINC, 0x0); 4342 /* Reset the timesync system time value. */ 4343 wr32(hw, TXGBE_TSTIMEL, 0x0); 4344 wr32(hw, TXGBE_TSTIMEH, 0x0); 4345 4346 txgbe_start_timecounters(dev); 4347 4348 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4349 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 4350 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588); 4351 4352 /* Enable timestamping of received PTP packets. */ 4353 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4354 tsync_ctl |= TXGBE_TSRXCTL_ENA; 4355 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4356 4357 /* Enable timestamping of transmitted PTP packets. */ 4358 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4359 tsync_ctl |= TXGBE_TSTXCTL_ENA; 4360 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4361 4362 txgbe_flush(hw); 4363 4364 return 0; 4365 } 4366 4367 static int 4368 txgbe_timesync_disable(struct rte_eth_dev *dev) 4369 { 4370 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4371 uint32_t tsync_ctl; 4372 4373 /* Disable timestamping of transmitted PTP packets. */ 4374 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4375 tsync_ctl &= ~TXGBE_TSTXCTL_ENA; 4376 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4377 4378 /* Disable timestamping of received PTP packets. */ 4379 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4380 tsync_ctl &= ~TXGBE_TSRXCTL_ENA; 4381 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4382 4383 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4384 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0); 4385 4386 /* Stop incrementing the System Time registers. */ 4387 wr32(hw, TXGBE_TSTIMEINC, 0); 4388 4389 return 0; 4390 } 4391 4392 static int 4393 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 4394 struct timespec *timestamp, 4395 uint32_t flags __rte_unused) 4396 { 4397 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4398 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4399 uint32_t tsync_rxctl; 4400 uint64_t rx_tstamp_cycles; 4401 uint64_t ns; 4402 4403 tsync_rxctl = rd32(hw, TXGBE_TSRXCTL); 4404 if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0) 4405 return -EINVAL; 4406 4407 rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev); 4408 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 4409 *timestamp = rte_ns_to_timespec(ns); 4410 4411 return 0; 4412 } 4413 4414 static int 4415 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 4416 struct timespec *timestamp) 4417 { 4418 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4419 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4420 uint32_t tsync_txctl; 4421 uint64_t tx_tstamp_cycles; 4422 uint64_t ns; 4423 4424 tsync_txctl = rd32(hw, TXGBE_TSTXCTL); 4425 if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0) 4426 return -EINVAL; 4427 4428 tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev); 4429 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 4430 *timestamp = rte_ns_to_timespec(ns); 4431 4432 return 0; 4433 } 4434 4435 static int 4436 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused) 4437 { 4438 int count = 0; 4439 int g_ind = 0; 4440 const struct reg_info *reg_group; 4441 const struct reg_info **reg_set = txgbe_regs_others; 4442 4443 while ((reg_group = reg_set[g_ind++])) 4444 count += txgbe_regs_group_count(reg_group); 4445 4446 return count; 4447 } 4448 4449 static int 4450 txgbe_get_regs(struct rte_eth_dev *dev, 4451 struct rte_dev_reg_info *regs) 4452 { 4453 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4454 uint32_t *data = regs->data; 4455 int g_ind = 0; 4456 int count = 0; 4457 const struct reg_info *reg_group; 4458 const struct reg_info **reg_set = txgbe_regs_others; 4459 4460 if (data == NULL) { 4461 regs->length = txgbe_get_reg_length(dev); 4462 regs->width = sizeof(uint32_t); 4463 return 0; 4464 } 4465 4466 /* Support only full register dump */ 4467 if (regs->length == 0 || 4468 regs->length == (uint32_t)txgbe_get_reg_length(dev)) { 4469 regs->version = hw->mac.type << 24 | 4470 hw->revision_id << 16 | 4471 hw->device_id; 4472 while ((reg_group = reg_set[g_ind++])) 4473 count += txgbe_read_regs_group(dev, &data[count], 4474 reg_group); 4475 return 0; 4476 } 4477 4478 return -ENOTSUP; 4479 } 4480 4481 static int 4482 txgbe_get_eeprom_length(struct rte_eth_dev *dev) 4483 { 4484 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4485 4486 /* Return unit is byte count */ 4487 return hw->rom.word_size * 2; 4488 } 4489 4490 static int 4491 txgbe_get_eeprom(struct rte_eth_dev *dev, 4492 struct rte_dev_eeprom_info *in_eeprom) 4493 { 4494 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4495 struct txgbe_rom_info *eeprom = &hw->rom; 4496 uint16_t *data = in_eeprom->data; 4497 int first, length; 4498 4499 first = in_eeprom->offset >> 1; 4500 length = in_eeprom->length >> 1; 4501 if (first > hw->rom.word_size || 4502 ((first + length) > hw->rom.word_size)) 4503 return -EINVAL; 4504 4505 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4506 4507 return eeprom->readw_buffer(hw, first, length, data); 4508 } 4509 4510 static int 4511 txgbe_set_eeprom(struct rte_eth_dev *dev, 4512 struct rte_dev_eeprom_info *in_eeprom) 4513 { 4514 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4515 struct txgbe_rom_info *eeprom = &hw->rom; 4516 uint16_t *data = in_eeprom->data; 4517 int first, length; 4518 4519 first = in_eeprom->offset >> 1; 4520 length = in_eeprom->length >> 1; 4521 if (first > hw->rom.word_size || 4522 ((first + length) > hw->rom.word_size)) 4523 return -EINVAL; 4524 4525 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4526 4527 return eeprom->writew_buffer(hw, first, length, data); 4528 } 4529 4530 static int 4531 txgbe_get_module_info(struct rte_eth_dev *dev, 4532 struct rte_eth_dev_module_info *modinfo) 4533 { 4534 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4535 uint32_t status; 4536 uint8_t sff8472_rev, addr_mode; 4537 bool page_swap = false; 4538 4539 /* Check whether we support SFF-8472 or not */ 4540 status = hw->phy.read_i2c_eeprom(hw, 4541 TXGBE_SFF_SFF_8472_COMP, 4542 &sff8472_rev); 4543 if (status != 0) 4544 return -EIO; 4545 4546 /* addressing mode is not supported */ 4547 status = hw->phy.read_i2c_eeprom(hw, 4548 TXGBE_SFF_SFF_8472_SWAP, 4549 &addr_mode); 4550 if (status != 0) 4551 return -EIO; 4552 4553 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) { 4554 PMD_DRV_LOG(ERR, 4555 "Address change required to access page 0xA2, " 4556 "but not supported. Please report the module " 4557 "type to the driver maintainers."); 4558 page_swap = true; 4559 } 4560 4561 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) { 4562 /* We have a SFP, but it does not support SFF-8472 */ 4563 modinfo->type = RTE_ETH_MODULE_SFF_8079; 4564 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 4565 } else { 4566 /* We have a SFP which supports a revision of SFF-8472. */ 4567 modinfo->type = RTE_ETH_MODULE_SFF_8472; 4568 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 4569 } 4570 4571 return 0; 4572 } 4573 4574 static int 4575 txgbe_get_module_eeprom(struct rte_eth_dev *dev, 4576 struct rte_dev_eeprom_info *info) 4577 { 4578 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4579 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID; 4580 uint8_t databyte = 0xFF; 4581 uint8_t *data = info->data; 4582 uint32_t i = 0; 4583 4584 if (info->length == 0) 4585 return -EINVAL; 4586 4587 for (i = info->offset; i < info->offset + info->length; i++) { 4588 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 4589 status = hw->phy.read_i2c_eeprom(hw, i, &databyte); 4590 else 4591 status = hw->phy.read_i2c_sff8472(hw, i, &databyte); 4592 4593 if (status != 0) 4594 return -EIO; 4595 4596 data[i - info->offset] = databyte; 4597 } 4598 4599 return 0; 4600 } 4601 4602 bool 4603 txgbe_rss_update_sp(enum txgbe_mac_type mac_type) 4604 { 4605 switch (mac_type) { 4606 case txgbe_mac_raptor: 4607 case txgbe_mac_raptor_vf: 4608 return 1; 4609 default: 4610 return 0; 4611 } 4612 } 4613 4614 static int 4615 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 4616 struct rte_eth_dcb_info *dcb_info) 4617 { 4618 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 4619 struct txgbe_dcb_tc_config *tc; 4620 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 4621 uint8_t nb_tcs; 4622 uint8_t i, j; 4623 4624 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) 4625 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 4626 else 4627 dcb_info->nb_tcs = 1; 4628 4629 tc_queue = &dcb_info->tc_queue; 4630 nb_tcs = dcb_info->nb_tcs; 4631 4632 if (dcb_config->vt_mode) { /* vt is enabled */ 4633 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 4634 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 4635 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) 4636 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 4637 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 4638 for (j = 0; j < nb_tcs; j++) { 4639 tc_queue->tc_rxq[0][j].base = j; 4640 tc_queue->tc_rxq[0][j].nb_queue = 1; 4641 tc_queue->tc_txq[0][j].base = j; 4642 tc_queue->tc_txq[0][j].nb_queue = 1; 4643 } 4644 } else { 4645 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 4646 for (j = 0; j < nb_tcs; j++) { 4647 tc_queue->tc_rxq[i][j].base = 4648 i * nb_tcs + j; 4649 tc_queue->tc_rxq[i][j].nb_queue = 1; 4650 tc_queue->tc_txq[i][j].base = 4651 i * nb_tcs + j; 4652 tc_queue->tc_txq[i][j].nb_queue = 1; 4653 } 4654 } 4655 } 4656 } else { /* vt is disabled */ 4657 struct rte_eth_dcb_rx_conf *rx_conf = 4658 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 4659 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) 4660 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 4661 if (dcb_info->nb_tcs == RTE_ETH_4_TCS) { 4662 for (i = 0; i < dcb_info->nb_tcs; i++) { 4663 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 4664 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4665 } 4666 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4667 dcb_info->tc_queue.tc_txq[0][1].base = 64; 4668 dcb_info->tc_queue.tc_txq[0][2].base = 96; 4669 dcb_info->tc_queue.tc_txq[0][3].base = 112; 4670 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 4671 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4672 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4673 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4674 } else if (dcb_info->nb_tcs == RTE_ETH_8_TCS) { 4675 for (i = 0; i < dcb_info->nb_tcs; i++) { 4676 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 4677 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4678 } 4679 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4680 dcb_info->tc_queue.tc_txq[0][1].base = 32; 4681 dcb_info->tc_queue.tc_txq[0][2].base = 64; 4682 dcb_info->tc_queue.tc_txq[0][3].base = 80; 4683 dcb_info->tc_queue.tc_txq[0][4].base = 96; 4684 dcb_info->tc_queue.tc_txq[0][5].base = 104; 4685 dcb_info->tc_queue.tc_txq[0][6].base = 112; 4686 dcb_info->tc_queue.tc_txq[0][7].base = 120; 4687 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 4688 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4689 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4690 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4691 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 4692 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 4693 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 4694 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 4695 } 4696 } 4697 for (i = 0; i < dcb_info->nb_tcs; i++) { 4698 tc = &dcb_config->tc_config[i]; 4699 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent; 4700 } 4701 return 0; 4702 } 4703 4704 /* Update e-tag ether type */ 4705 static int 4706 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw, 4707 uint16_t ether_type) 4708 { 4709 uint32_t etag_etype; 4710 4711 etag_etype = rd32(hw, TXGBE_EXTAG); 4712 etag_etype &= ~TXGBE_EXTAG_ETAG_MASK; 4713 etag_etype |= ether_type; 4714 wr32(hw, TXGBE_EXTAG, etag_etype); 4715 txgbe_flush(hw); 4716 4717 return 0; 4718 } 4719 4720 /* Enable e-tag tunnel */ 4721 static int 4722 txgbe_e_tag_enable(struct txgbe_hw *hw) 4723 { 4724 uint32_t etag_etype; 4725 4726 etag_etype = rd32(hw, TXGBE_PORTCTL); 4727 etag_etype |= TXGBE_PORTCTL_ETAG; 4728 wr32(hw, TXGBE_PORTCTL, etag_etype); 4729 txgbe_flush(hw); 4730 4731 return 0; 4732 } 4733 4734 static int 4735 txgbe_e_tag_filter_del(struct rte_eth_dev *dev, 4736 struct txgbe_l2_tunnel_conf *l2_tunnel) 4737 { 4738 int ret = 0; 4739 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4740 uint32_t i, rar_entries; 4741 uint32_t rar_low, rar_high; 4742 4743 rar_entries = hw->mac.num_rar_entries; 4744 4745 for (i = 1; i < rar_entries; i++) { 4746 wr32(hw, TXGBE_ETHADDRIDX, i); 4747 rar_high = rd32(hw, TXGBE_ETHADDRH); 4748 rar_low = rd32(hw, TXGBE_ETHADDRL); 4749 if ((rar_high & TXGBE_ETHADDRH_VLD) && 4750 (rar_high & TXGBE_ETHADDRH_ETAG) && 4751 (TXGBE_ETHADDRL_ETAG(rar_low) == 4752 l2_tunnel->tunnel_id)) { 4753 wr32(hw, TXGBE_ETHADDRL, 0); 4754 wr32(hw, TXGBE_ETHADDRH, 0); 4755 4756 txgbe_clear_vmdq(hw, i, BIT_MASK32); 4757 4758 return ret; 4759 } 4760 } 4761 4762 return ret; 4763 } 4764 4765 static int 4766 txgbe_e_tag_filter_add(struct rte_eth_dev *dev, 4767 struct txgbe_l2_tunnel_conf *l2_tunnel) 4768 { 4769 int ret = 0; 4770 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4771 uint32_t i, rar_entries; 4772 uint32_t rar_low, rar_high; 4773 4774 /* One entry for one tunnel. Try to remove potential existing entry. */ 4775 txgbe_e_tag_filter_del(dev, l2_tunnel); 4776 4777 rar_entries = hw->mac.num_rar_entries; 4778 4779 for (i = 1; i < rar_entries; i++) { 4780 wr32(hw, TXGBE_ETHADDRIDX, i); 4781 rar_high = rd32(hw, TXGBE_ETHADDRH); 4782 if (rar_high & TXGBE_ETHADDRH_VLD) { 4783 continue; 4784 } else { 4785 txgbe_set_vmdq(hw, i, l2_tunnel->pool); 4786 rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG; 4787 rar_low = l2_tunnel->tunnel_id; 4788 4789 wr32(hw, TXGBE_ETHADDRL, rar_low); 4790 wr32(hw, TXGBE_ETHADDRH, rar_high); 4791 4792 return ret; 4793 } 4794 } 4795 4796 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 4797 " Please remove a rule before adding a new one."); 4798 return -EINVAL; 4799 } 4800 4801 static inline struct txgbe_l2_tn_filter * 4802 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info, 4803 struct txgbe_l2_tn_key *key) 4804 { 4805 int ret; 4806 4807 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 4808 if (ret < 0) 4809 return NULL; 4810 4811 return l2_tn_info->hash_map[ret]; 4812 } 4813 4814 static inline int 4815 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4816 struct txgbe_l2_tn_filter *l2_tn_filter) 4817 { 4818 int ret; 4819 4820 ret = rte_hash_add_key(l2_tn_info->hash_handle, 4821 &l2_tn_filter->key); 4822 4823 if (ret < 0) { 4824 PMD_DRV_LOG(ERR, 4825 "Failed to insert L2 tunnel filter" 4826 " to hash table %d!", 4827 ret); 4828 return ret; 4829 } 4830 4831 l2_tn_info->hash_map[ret] = l2_tn_filter; 4832 4833 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4834 4835 return 0; 4836 } 4837 4838 static inline int 4839 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4840 struct txgbe_l2_tn_key *key) 4841 { 4842 int ret; 4843 struct txgbe_l2_tn_filter *l2_tn_filter; 4844 4845 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 4846 4847 if (ret < 0) { 4848 PMD_DRV_LOG(ERR, 4849 "No such L2 tunnel filter to delete %d!", 4850 ret); 4851 return ret; 4852 } 4853 4854 l2_tn_filter = l2_tn_info->hash_map[ret]; 4855 l2_tn_info->hash_map[ret] = NULL; 4856 4857 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4858 rte_free(l2_tn_filter); 4859 4860 return 0; 4861 } 4862 4863 /* Add l2 tunnel filter */ 4864 int 4865 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 4866 struct txgbe_l2_tunnel_conf *l2_tunnel, 4867 bool restore) 4868 { 4869 int ret; 4870 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4871 struct txgbe_l2_tn_key key; 4872 struct txgbe_l2_tn_filter *node; 4873 4874 if (!restore) { 4875 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4876 key.tn_id = l2_tunnel->tunnel_id; 4877 4878 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key); 4879 4880 if (node) { 4881 PMD_DRV_LOG(ERR, 4882 "The L2 tunnel filter already exists!"); 4883 return -EINVAL; 4884 } 4885 4886 node = rte_zmalloc("txgbe_l2_tn", 4887 sizeof(struct txgbe_l2_tn_filter), 4888 0); 4889 if (!node) 4890 return -ENOMEM; 4891 4892 rte_memcpy(&node->key, 4893 &key, 4894 sizeof(struct txgbe_l2_tn_key)); 4895 node->pool = l2_tunnel->pool; 4896 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node); 4897 if (ret < 0) { 4898 rte_free(node); 4899 return ret; 4900 } 4901 } 4902 4903 switch (l2_tunnel->l2_tunnel_type) { 4904 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG: 4905 ret = txgbe_e_tag_filter_add(dev, l2_tunnel); 4906 break; 4907 default: 4908 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4909 ret = -EINVAL; 4910 break; 4911 } 4912 4913 if (!restore && ret < 0) 4914 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4915 4916 return ret; 4917 } 4918 4919 /* Delete l2 tunnel filter */ 4920 int 4921 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 4922 struct txgbe_l2_tunnel_conf *l2_tunnel) 4923 { 4924 int ret; 4925 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4926 struct txgbe_l2_tn_key key; 4927 4928 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4929 key.tn_id = l2_tunnel->tunnel_id; 4930 ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4931 if (ret < 0) 4932 return ret; 4933 4934 switch (l2_tunnel->l2_tunnel_type) { 4935 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG: 4936 ret = txgbe_e_tag_filter_del(dev, l2_tunnel); 4937 break; 4938 default: 4939 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4940 ret = -EINVAL; 4941 break; 4942 } 4943 4944 return ret; 4945 } 4946 4947 static int 4948 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 4949 { 4950 int ret = 0; 4951 uint32_t ctrl; 4952 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4953 4954 ctrl = rd32(hw, TXGBE_POOLCTL); 4955 ctrl &= ~TXGBE_POOLCTL_MODE_MASK; 4956 if (en) 4957 ctrl |= TXGBE_PSRPOOL_MODE_ETAG; 4958 wr32(hw, TXGBE_POOLCTL, ctrl); 4959 4960 return ret; 4961 } 4962 4963 /* Add UDP tunneling port */ 4964 static int 4965 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 4966 struct rte_eth_udp_tunnel *udp_tunnel) 4967 { 4968 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4969 int ret = 0; 4970 4971 if (udp_tunnel == NULL) 4972 return -EINVAL; 4973 4974 switch (udp_tunnel->prot_type) { 4975 case RTE_ETH_TUNNEL_TYPE_VXLAN: 4976 if (udp_tunnel->udp_port == 0) { 4977 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 4978 ret = -EINVAL; 4979 break; 4980 } 4981 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port); 4982 break; 4983 case RTE_ETH_TUNNEL_TYPE_GENEVE: 4984 if (udp_tunnel->udp_port == 0) { 4985 PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed."); 4986 ret = -EINVAL; 4987 break; 4988 } 4989 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port); 4990 break; 4991 case RTE_ETH_TUNNEL_TYPE_TEREDO: 4992 if (udp_tunnel->udp_port == 0) { 4993 PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed."); 4994 ret = -EINVAL; 4995 break; 4996 } 4997 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port); 4998 break; 4999 case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE: 5000 if (udp_tunnel->udp_port == 0) { 5001 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 5002 ret = -EINVAL; 5003 break; 5004 } 5005 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port); 5006 break; 5007 default: 5008 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5009 ret = -EINVAL; 5010 break; 5011 } 5012 5013 txgbe_flush(hw); 5014 5015 return ret; 5016 } 5017 5018 /* Remove UDP tunneling port */ 5019 static int 5020 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 5021 struct rte_eth_udp_tunnel *udp_tunnel) 5022 { 5023 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5024 int ret = 0; 5025 uint16_t cur_port; 5026 5027 if (udp_tunnel == NULL) 5028 return -EINVAL; 5029 5030 switch (udp_tunnel->prot_type) { 5031 case RTE_ETH_TUNNEL_TYPE_VXLAN: 5032 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT); 5033 if (cur_port != udp_tunnel->udp_port) { 5034 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5035 udp_tunnel->udp_port); 5036 ret = -EINVAL; 5037 break; 5038 } 5039 wr32(hw, TXGBE_VXLANPORT, 0); 5040 break; 5041 case RTE_ETH_TUNNEL_TYPE_GENEVE: 5042 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT); 5043 if (cur_port != udp_tunnel->udp_port) { 5044 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5045 udp_tunnel->udp_port); 5046 ret = -EINVAL; 5047 break; 5048 } 5049 wr32(hw, TXGBE_GENEVEPORT, 0); 5050 break; 5051 case RTE_ETH_TUNNEL_TYPE_TEREDO: 5052 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT); 5053 if (cur_port != udp_tunnel->udp_port) { 5054 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5055 udp_tunnel->udp_port); 5056 ret = -EINVAL; 5057 break; 5058 } 5059 wr32(hw, TXGBE_TEREDOPORT, 0); 5060 break; 5061 case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE: 5062 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORTGPE); 5063 if (cur_port != udp_tunnel->udp_port) { 5064 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5065 udp_tunnel->udp_port); 5066 ret = -EINVAL; 5067 break; 5068 } 5069 wr32(hw, TXGBE_VXLANPORTGPE, 0); 5070 break; 5071 default: 5072 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5073 ret = -EINVAL; 5074 break; 5075 } 5076 5077 txgbe_flush(hw); 5078 5079 return ret; 5080 } 5081 5082 /* restore n-tuple filter */ 5083 static inline void 5084 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 5085 { 5086 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5087 struct txgbe_5tuple_filter *node; 5088 5089 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 5090 txgbe_inject_5tuple_filter(dev, node); 5091 } 5092 } 5093 5094 /* restore ethernet type filter */ 5095 static inline void 5096 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 5097 { 5098 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5099 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5100 int i; 5101 5102 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5103 if (filter_info->ethertype_mask & (1 << i)) { 5104 wr32(hw, TXGBE_ETFLT(i), 5105 filter_info->ethertype_filters[i].etqf); 5106 wr32(hw, TXGBE_ETCLS(i), 5107 filter_info->ethertype_filters[i].etqs); 5108 txgbe_flush(hw); 5109 } 5110 } 5111 } 5112 5113 /* restore SYN filter */ 5114 static inline void 5115 txgbe_syn_filter_restore(struct rte_eth_dev *dev) 5116 { 5117 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5118 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5119 uint32_t synqf; 5120 5121 synqf = filter_info->syn_info; 5122 5123 if (synqf & TXGBE_SYNCLS_ENA) { 5124 wr32(hw, TXGBE_SYNCLS, synqf); 5125 txgbe_flush(hw); 5126 } 5127 } 5128 5129 /* restore L2 tunnel filter */ 5130 static inline void 5131 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 5132 { 5133 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5134 struct txgbe_l2_tn_filter *node; 5135 struct txgbe_l2_tunnel_conf l2_tn_conf; 5136 5137 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 5138 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 5139 l2_tn_conf.tunnel_id = node->key.tn_id; 5140 l2_tn_conf.pool = node->pool; 5141 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 5142 } 5143 } 5144 5145 /* restore rss filter */ 5146 static inline void 5147 txgbe_rss_filter_restore(struct rte_eth_dev *dev) 5148 { 5149 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5150 5151 if (filter_info->rss_info.conf.queue_num) 5152 txgbe_config_rss_filter(dev, 5153 &filter_info->rss_info, TRUE); 5154 } 5155 5156 static int 5157 txgbe_filter_restore(struct rte_eth_dev *dev) 5158 { 5159 txgbe_ntuple_filter_restore(dev); 5160 txgbe_ethertype_filter_restore(dev); 5161 txgbe_syn_filter_restore(dev); 5162 txgbe_fdir_filter_restore(dev); 5163 txgbe_l2_tn_filter_restore(dev); 5164 txgbe_rss_filter_restore(dev); 5165 5166 return 0; 5167 } 5168 5169 static void 5170 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 5171 { 5172 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5173 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5174 5175 if (l2_tn_info->e_tag_en) 5176 (void)txgbe_e_tag_enable(hw); 5177 5178 if (l2_tn_info->e_tag_fwd_en) 5179 (void)txgbe_e_tag_forwarding_en_dis(dev, 1); 5180 5181 (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 5182 } 5183 5184 /* remove all the n-tuple filters */ 5185 void 5186 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 5187 { 5188 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5189 struct txgbe_5tuple_filter *p_5tuple; 5190 5191 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 5192 txgbe_remove_5tuple_filter(dev, p_5tuple); 5193 } 5194 5195 /* remove all the ether type filters */ 5196 void 5197 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 5198 { 5199 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5200 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5201 int i; 5202 5203 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5204 if (filter_info->ethertype_mask & (1 << i) && 5205 !filter_info->ethertype_filters[i].conf) { 5206 (void)txgbe_ethertype_filter_remove(filter_info, 5207 (uint8_t)i); 5208 wr32(hw, TXGBE_ETFLT(i), 0); 5209 wr32(hw, TXGBE_ETCLS(i), 0); 5210 txgbe_flush(hw); 5211 } 5212 } 5213 } 5214 5215 /* remove the SYN filter */ 5216 void 5217 txgbe_clear_syn_filter(struct rte_eth_dev *dev) 5218 { 5219 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5220 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5221 5222 if (filter_info->syn_info & TXGBE_SYNCLS_ENA) { 5223 filter_info->syn_info = 0; 5224 5225 wr32(hw, TXGBE_SYNCLS, 0); 5226 txgbe_flush(hw); 5227 } 5228 } 5229 5230 /* remove all the L2 tunnel filters */ 5231 int 5232 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 5233 { 5234 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5235 struct txgbe_l2_tn_filter *l2_tn_filter; 5236 struct txgbe_l2_tunnel_conf l2_tn_conf; 5237 int ret = 0; 5238 5239 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 5240 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 5241 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 5242 l2_tn_conf.pool = l2_tn_filter->pool; 5243 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 5244 if (ret < 0) 5245 return ret; 5246 } 5247 5248 return 0; 5249 } 5250 5251 static const struct eth_dev_ops txgbe_eth_dev_ops = { 5252 .dev_configure = txgbe_dev_configure, 5253 .dev_infos_get = txgbe_dev_info_get, 5254 .dev_start = txgbe_dev_start, 5255 .dev_stop = txgbe_dev_stop, 5256 .dev_set_link_up = txgbe_dev_set_link_up, 5257 .dev_set_link_down = txgbe_dev_set_link_down, 5258 .dev_close = txgbe_dev_close, 5259 .dev_reset = txgbe_dev_reset, 5260 .promiscuous_enable = txgbe_dev_promiscuous_enable, 5261 .promiscuous_disable = txgbe_dev_promiscuous_disable, 5262 .allmulticast_enable = txgbe_dev_allmulticast_enable, 5263 .allmulticast_disable = txgbe_dev_allmulticast_disable, 5264 .link_update = txgbe_dev_link_update, 5265 .stats_get = txgbe_dev_stats_get, 5266 .xstats_get = txgbe_dev_xstats_get, 5267 .xstats_get_by_id = txgbe_dev_xstats_get_by_id, 5268 .stats_reset = txgbe_dev_stats_reset, 5269 .xstats_reset = txgbe_dev_xstats_reset, 5270 .xstats_get_names = txgbe_dev_xstats_get_names, 5271 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id, 5272 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set, 5273 .fw_version_get = txgbe_fw_version_get, 5274 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get, 5275 .mtu_set = txgbe_dev_mtu_set, 5276 .vlan_filter_set = txgbe_vlan_filter_set, 5277 .vlan_tpid_set = txgbe_vlan_tpid_set, 5278 .vlan_offload_set = txgbe_vlan_offload_set, 5279 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set, 5280 .rx_queue_start = txgbe_dev_rx_queue_start, 5281 .rx_queue_stop = txgbe_dev_rx_queue_stop, 5282 .tx_queue_start = txgbe_dev_tx_queue_start, 5283 .tx_queue_stop = txgbe_dev_tx_queue_stop, 5284 .rx_queue_setup = txgbe_dev_rx_queue_setup, 5285 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable, 5286 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable, 5287 .rx_queue_release = txgbe_dev_rx_queue_release, 5288 .tx_queue_setup = txgbe_dev_tx_queue_setup, 5289 .tx_queue_release = txgbe_dev_tx_queue_release, 5290 .dev_led_on = txgbe_dev_led_on, 5291 .dev_led_off = txgbe_dev_led_off, 5292 .flow_ctrl_get = txgbe_flow_ctrl_get, 5293 .flow_ctrl_set = txgbe_flow_ctrl_set, 5294 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set, 5295 .mac_addr_add = txgbe_add_rar, 5296 .mac_addr_remove = txgbe_remove_rar, 5297 .mac_addr_set = txgbe_set_default_mac_addr, 5298 .uc_hash_table_set = txgbe_uc_hash_table_set, 5299 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set, 5300 .set_queue_rate_limit = txgbe_set_queue_rate_limit, 5301 .reta_update = txgbe_dev_rss_reta_update, 5302 .reta_query = txgbe_dev_rss_reta_query, 5303 .rss_hash_update = txgbe_dev_rss_hash_update, 5304 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get, 5305 .flow_ops_get = txgbe_dev_flow_ops_get, 5306 .set_mc_addr_list = txgbe_dev_set_mc_addr_list, 5307 .rxq_info_get = txgbe_rxq_info_get, 5308 .txq_info_get = txgbe_txq_info_get, 5309 .timesync_enable = txgbe_timesync_enable, 5310 .timesync_disable = txgbe_timesync_disable, 5311 .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp, 5312 .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp, 5313 .get_reg = txgbe_get_regs, 5314 .get_eeprom_length = txgbe_get_eeprom_length, 5315 .get_eeprom = txgbe_get_eeprom, 5316 .set_eeprom = txgbe_set_eeprom, 5317 .get_module_info = txgbe_get_module_info, 5318 .get_module_eeprom = txgbe_get_module_eeprom, 5319 .get_dcb_info = txgbe_dev_get_dcb_info, 5320 .timesync_adjust_time = txgbe_timesync_adjust_time, 5321 .timesync_read_time = txgbe_timesync_read_time, 5322 .timesync_write_time = txgbe_timesync_write_time, 5323 .udp_tunnel_port_add = txgbe_dev_udp_tunnel_port_add, 5324 .udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del, 5325 .tm_ops_get = txgbe_tm_ops_get, 5326 .tx_done_cleanup = txgbe_dev_tx_done_cleanup, 5327 }; 5328 5329 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd); 5330 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map); 5331 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 5332 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe, 5333 TXGBE_DEVARG_BP_AUTO "=<0|1>" 5334 TXGBE_DEVARG_KR_POLL "=<0|1>" 5335 TXGBE_DEVARG_KR_PRESENT "=<0|1>" 5336 TXGBE_DEVARG_KX_SGMII "=<0|1>" 5337 TXGBE_DEVARG_FFE_SET "=<0-4>" 5338 TXGBE_DEVARG_FFE_MAIN "=<uint16>" 5339 TXGBE_DEVARG_FFE_PRE "=<uint16>" 5340 TXGBE_DEVARG_FFE_POST "=<uint16>"); 5341 5342 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE); 5343 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE); 5344 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_bp, bp, NOTICE); 5345 5346 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX 5347 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_rx, rx, DEBUG); 5348 #endif 5349 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX 5350 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx, tx, DEBUG); 5351 #endif 5352 5353 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE 5354 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx_free, tx_free, DEBUG); 5355 #endif 5356