1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <rte_common.h> 11 #include <ethdev_pci.h> 12 13 #include <rte_interrupts.h> 14 #include <rte_log.h> 15 #include <rte_debug.h> 16 #include <rte_pci.h> 17 #include <rte_memory.h> 18 #include <rte_eal.h> 19 #include <rte_alarm.h> 20 #include <rte_kvargs.h> 21 22 #include "txgbe_logs.h" 23 #include "base/txgbe.h" 24 #include "txgbe_ethdev.h" 25 #include "txgbe_rxtx.h" 26 #include "txgbe_regs_group.h" 27 28 static const struct reg_info txgbe_regs_general[] = { 29 {TXGBE_RST, 1, 1, "TXGBE_RST"}, 30 {TXGBE_STAT, 1, 1, "TXGBE_STAT"}, 31 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"}, 32 {TXGBE_SDP, 1, 1, "TXGBE_SDP"}, 33 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"}, 34 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"}, 35 {0, 0, 0, ""} 36 }; 37 38 static const struct reg_info txgbe_regs_nvm[] = { 39 {0, 0, 0, ""} 40 }; 41 42 static const struct reg_info txgbe_regs_interrupt[] = { 43 {0, 0, 0, ""} 44 }; 45 46 static const struct reg_info txgbe_regs_fctl_others[] = { 47 {0, 0, 0, ""} 48 }; 49 50 static const struct reg_info txgbe_regs_rxdma[] = { 51 {0, 0, 0, ""} 52 }; 53 54 static const struct reg_info txgbe_regs_rx[] = { 55 {0, 0, 0, ""} 56 }; 57 58 static struct reg_info txgbe_regs_tx[] = { 59 {0, 0, 0, ""} 60 }; 61 62 static const struct reg_info txgbe_regs_wakeup[] = { 63 {0, 0, 0, ""} 64 }; 65 66 static const struct reg_info txgbe_regs_dcb[] = { 67 {0, 0, 0, ""} 68 }; 69 70 static const struct reg_info txgbe_regs_mac[] = { 71 {0, 0, 0, ""} 72 }; 73 74 static const struct reg_info txgbe_regs_diagnostic[] = { 75 {0, 0, 0, ""}, 76 }; 77 78 /* PF registers */ 79 static const struct reg_info *txgbe_regs_others[] = { 80 txgbe_regs_general, 81 txgbe_regs_nvm, 82 txgbe_regs_interrupt, 83 txgbe_regs_fctl_others, 84 txgbe_regs_rxdma, 85 txgbe_regs_rx, 86 txgbe_regs_tx, 87 txgbe_regs_wakeup, 88 txgbe_regs_dcb, 89 txgbe_regs_mac, 90 txgbe_regs_diagnostic, 91 NULL}; 92 93 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 94 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 95 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 96 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 97 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev); 98 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev); 99 static int txgbe_dev_close(struct rte_eth_dev *dev); 100 static int txgbe_dev_link_update(struct rte_eth_dev *dev, 101 int wait_to_complete); 102 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev); 103 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 104 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, 105 uint16_t queue); 106 107 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev); 108 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 109 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 110 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev); 111 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 112 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, 113 struct rte_intr_handle *handle); 114 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 115 struct rte_intr_handle *handle); 116 static void txgbe_dev_interrupt_handler(void *param); 117 static void txgbe_dev_interrupt_delayed_handler(void *param); 118 static void txgbe_configure_msix(struct rte_eth_dev *dev); 119 120 static int txgbe_filter_restore(struct rte_eth_dev *dev); 121 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 122 123 #define TXGBE_SET_HWSTRIP(h, q) do {\ 124 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 125 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 126 (h)->bitmap[idx] |= 1 << bit;\ 127 } while (0) 128 129 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\ 130 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 131 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 132 (h)->bitmap[idx] &= ~(1 << bit);\ 133 } while (0) 134 135 #define TXGBE_GET_HWSTRIP(h, q, r) do {\ 136 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 137 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 138 (r) = (h)->bitmap[idx] >> bit & 1;\ 139 } while (0) 140 141 /* 142 * The set of PCI devices this driver supports 143 */ 144 static const struct rte_pci_id pci_id_txgbe_map[] = { 145 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) }, 146 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) }, 147 { .vendor_id = 0, /* sentinel */ }, 148 }; 149 150 static const struct rte_eth_desc_lim rx_desc_lim = { 151 .nb_max = TXGBE_RING_DESC_MAX, 152 .nb_min = TXGBE_RING_DESC_MIN, 153 .nb_align = TXGBE_RXD_ALIGN, 154 }; 155 156 static const struct rte_eth_desc_lim tx_desc_lim = { 157 .nb_max = TXGBE_RING_DESC_MAX, 158 .nb_min = TXGBE_RING_DESC_MIN, 159 .nb_align = TXGBE_TXD_ALIGN, 160 .nb_seg_max = TXGBE_TX_MAX_SEG, 161 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG, 162 }; 163 164 static const struct eth_dev_ops txgbe_eth_dev_ops; 165 166 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)} 167 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)} 168 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = { 169 /* MNG RxTx */ 170 HW_XSTAT(mng_bmc2host_packets), 171 HW_XSTAT(mng_host2bmc_packets), 172 /* Basic RxTx */ 173 HW_XSTAT(rx_packets), 174 HW_XSTAT(tx_packets), 175 HW_XSTAT(rx_bytes), 176 HW_XSTAT(tx_bytes), 177 HW_XSTAT(rx_total_bytes), 178 HW_XSTAT(rx_total_packets), 179 HW_XSTAT(tx_total_packets), 180 HW_XSTAT(rx_total_missed_packets), 181 HW_XSTAT(rx_broadcast_packets), 182 HW_XSTAT(rx_multicast_packets), 183 HW_XSTAT(rx_management_packets), 184 HW_XSTAT(tx_management_packets), 185 HW_XSTAT(rx_management_dropped), 186 187 /* Basic Error */ 188 HW_XSTAT(rx_crc_errors), 189 HW_XSTAT(rx_illegal_byte_errors), 190 HW_XSTAT(rx_error_bytes), 191 HW_XSTAT(rx_mac_short_packet_dropped), 192 HW_XSTAT(rx_length_errors), 193 HW_XSTAT(rx_undersize_errors), 194 HW_XSTAT(rx_fragment_errors), 195 HW_XSTAT(rx_oversize_errors), 196 HW_XSTAT(rx_jabber_errors), 197 HW_XSTAT(rx_l3_l4_xsum_error), 198 HW_XSTAT(mac_local_errors), 199 HW_XSTAT(mac_remote_errors), 200 201 /* Flow Director */ 202 HW_XSTAT(flow_director_added_filters), 203 HW_XSTAT(flow_director_removed_filters), 204 HW_XSTAT(flow_director_filter_add_errors), 205 HW_XSTAT(flow_director_filter_remove_errors), 206 HW_XSTAT(flow_director_matched_filters), 207 HW_XSTAT(flow_director_missed_filters), 208 209 /* FCoE */ 210 HW_XSTAT(rx_fcoe_crc_errors), 211 HW_XSTAT(rx_fcoe_mbuf_allocation_errors), 212 HW_XSTAT(rx_fcoe_dropped), 213 HW_XSTAT(rx_fcoe_packets), 214 HW_XSTAT(tx_fcoe_packets), 215 HW_XSTAT(rx_fcoe_bytes), 216 HW_XSTAT(tx_fcoe_bytes), 217 HW_XSTAT(rx_fcoe_no_ddp), 218 HW_XSTAT(rx_fcoe_no_ddp_ext_buff), 219 220 /* MACSEC */ 221 HW_XSTAT(tx_macsec_pkts_untagged), 222 HW_XSTAT(tx_macsec_pkts_encrypted), 223 HW_XSTAT(tx_macsec_pkts_protected), 224 HW_XSTAT(tx_macsec_octets_encrypted), 225 HW_XSTAT(tx_macsec_octets_protected), 226 HW_XSTAT(rx_macsec_pkts_untagged), 227 HW_XSTAT(rx_macsec_pkts_badtag), 228 HW_XSTAT(rx_macsec_pkts_nosci), 229 HW_XSTAT(rx_macsec_pkts_unknownsci), 230 HW_XSTAT(rx_macsec_octets_decrypted), 231 HW_XSTAT(rx_macsec_octets_validated), 232 HW_XSTAT(rx_macsec_sc_pkts_unchecked), 233 HW_XSTAT(rx_macsec_sc_pkts_delayed), 234 HW_XSTAT(rx_macsec_sc_pkts_late), 235 HW_XSTAT(rx_macsec_sa_pkts_ok), 236 HW_XSTAT(rx_macsec_sa_pkts_invalid), 237 HW_XSTAT(rx_macsec_sa_pkts_notvalid), 238 HW_XSTAT(rx_macsec_sa_pkts_unusedsa), 239 HW_XSTAT(rx_macsec_sa_pkts_notusingsa), 240 241 /* MAC RxTx */ 242 HW_XSTAT(rx_size_64_packets), 243 HW_XSTAT(rx_size_65_to_127_packets), 244 HW_XSTAT(rx_size_128_to_255_packets), 245 HW_XSTAT(rx_size_256_to_511_packets), 246 HW_XSTAT(rx_size_512_to_1023_packets), 247 HW_XSTAT(rx_size_1024_to_max_packets), 248 HW_XSTAT(tx_size_64_packets), 249 HW_XSTAT(tx_size_65_to_127_packets), 250 HW_XSTAT(tx_size_128_to_255_packets), 251 HW_XSTAT(tx_size_256_to_511_packets), 252 HW_XSTAT(tx_size_512_to_1023_packets), 253 HW_XSTAT(tx_size_1024_to_max_packets), 254 255 /* Flow Control */ 256 HW_XSTAT(tx_xon_packets), 257 HW_XSTAT(rx_xon_packets), 258 HW_XSTAT(tx_xoff_packets), 259 HW_XSTAT(rx_xoff_packets), 260 261 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"), 262 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"), 263 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"), 264 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"), 265 }; 266 267 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \ 268 sizeof(rte_txgbe_stats_strings[0])) 269 270 /* Per-priority statistics */ 271 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)} 272 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = { 273 UP_XSTAT(rx_up_packets), 274 UP_XSTAT(tx_up_packets), 275 UP_XSTAT(rx_up_bytes), 276 UP_XSTAT(tx_up_bytes), 277 UP_XSTAT(rx_up_drop_packets), 278 279 UP_XSTAT(tx_up_xon_packets), 280 UP_XSTAT(rx_up_xon_packets), 281 UP_XSTAT(tx_up_xoff_packets), 282 UP_XSTAT(rx_up_xoff_packets), 283 UP_XSTAT(rx_up_dropped), 284 UP_XSTAT(rx_up_mbuf_alloc_errors), 285 UP_XSTAT(tx_up_xon2off_packets), 286 }; 287 288 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \ 289 sizeof(rte_txgbe_up_strings[0])) 290 291 /* Per-queue statistics */ 292 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)} 293 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = { 294 QP_XSTAT(rx_qp_packets), 295 QP_XSTAT(tx_qp_packets), 296 QP_XSTAT(rx_qp_bytes), 297 QP_XSTAT(tx_qp_bytes), 298 QP_XSTAT(rx_qp_mc_packets), 299 }; 300 301 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \ 302 sizeof(rte_txgbe_qp_strings[0])) 303 304 static inline int 305 txgbe_is_sfp(struct txgbe_hw *hw) 306 { 307 switch (hw->phy.type) { 308 case txgbe_phy_sfp_avago: 309 case txgbe_phy_sfp_ftl: 310 case txgbe_phy_sfp_intel: 311 case txgbe_phy_sfp_unknown: 312 case txgbe_phy_sfp_tyco_passive: 313 case txgbe_phy_sfp_unknown_passive: 314 return 1; 315 default: 316 return 0; 317 } 318 } 319 320 static inline int32_t 321 txgbe_pf_reset_hw(struct txgbe_hw *hw) 322 { 323 uint32_t ctrl_ext; 324 int32_t status; 325 326 status = hw->mac.reset_hw(hw); 327 328 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 329 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 330 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 331 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 332 txgbe_flush(hw); 333 334 if (status == TXGBE_ERR_SFP_NOT_PRESENT) 335 status = 0; 336 return status; 337 } 338 339 static inline void 340 txgbe_enable_intr(struct rte_eth_dev *dev) 341 { 342 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 343 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 344 345 wr32(hw, TXGBE_IENMISC, intr->mask_misc); 346 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK); 347 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK); 348 txgbe_flush(hw); 349 } 350 351 static void 352 txgbe_disable_intr(struct txgbe_hw *hw) 353 { 354 PMD_INIT_FUNC_TRACE(); 355 356 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32); 357 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK); 358 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK); 359 txgbe_flush(hw); 360 } 361 362 static int 363 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 364 uint16_t queue_id, 365 uint8_t stat_idx, 366 uint8_t is_rx) 367 { 368 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 369 struct txgbe_stat_mappings *stat_mappings = 370 TXGBE_DEV_STAT_MAPPINGS(eth_dev); 371 uint32_t qsmr_mask = 0; 372 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 373 uint32_t q_map; 374 uint8_t n, offset; 375 376 if (hw->mac.type != txgbe_mac_raptor) 377 return -ENOSYS; 378 379 if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK) 380 return -EIO; 381 382 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 383 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 384 queue_id, stat_idx); 385 386 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 387 if (n >= TXGBE_NB_STAT_MAPPING) { 388 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 389 return -EIO; 390 } 391 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 392 393 /* Now clear any previous stat_idx set */ 394 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 395 if (!is_rx) 396 stat_mappings->tqsm[n] &= ~clearing_mask; 397 else 398 stat_mappings->rqsm[n] &= ~clearing_mask; 399 400 q_map = (uint32_t)stat_idx; 401 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 402 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 403 if (!is_rx) 404 stat_mappings->tqsm[n] |= qsmr_mask; 405 else 406 stat_mappings->rqsm[n] |= qsmr_mask; 407 408 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 409 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 410 queue_id, stat_idx); 411 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 412 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]); 413 return 0; 414 } 415 416 static void 417 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config) 418 { 419 int i; 420 u8 bwgp; 421 struct txgbe_dcb_tc_config *tc; 422 423 UNREFERENCED_PARAMETER(hw); 424 425 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX; 426 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX; 427 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX); 428 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 429 tc = &dcb_config->tc_config[i]; 430 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i; 431 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1); 432 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i; 433 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1); 434 tc->pfc = txgbe_dcb_pfc_disabled; 435 } 436 437 /* Initialize default user to priority mapping, UPx->TC0 */ 438 tc = &dcb_config->tc_config[0]; 439 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 440 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 441 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) { 442 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100; 443 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100; 444 } 445 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal; 446 dcb_config->pfc_mode_enable = false; 447 dcb_config->vt_mode = true; 448 dcb_config->round_robin_enable = false; 449 /* support all DCB capabilities */ 450 dcb_config->support.capabilities = 0xFF; 451 } 452 453 /* 454 * Ensure that all locks are released before first NVM or PHY access 455 */ 456 static void 457 txgbe_swfw_lock_reset(struct txgbe_hw *hw) 458 { 459 uint16_t mask; 460 461 /* 462 * These ones are more tricky since they are common to all ports; but 463 * swfw_sync retries last long enough (1s) to be almost sure that if 464 * lock can not be taken it is due to an improper lock of the 465 * semaphore. 466 */ 467 mask = TXGBE_MNGSEM_SWPHY | 468 TXGBE_MNGSEM_SWMBX | 469 TXGBE_MNGSEM_SWFLASH; 470 if (hw->mac.acquire_swfw_sync(hw, mask) < 0) 471 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 472 473 hw->mac.release_swfw_sync(hw, mask); 474 } 475 476 static int 477 txgbe_handle_devarg(__rte_unused const char *key, const char *value, 478 void *extra_args) 479 { 480 uint16_t *n = extra_args; 481 482 if (value == NULL || extra_args == NULL) 483 return -EINVAL; 484 485 *n = (uint16_t)strtoul(value, NULL, 10); 486 if (*n == USHRT_MAX && errno == ERANGE) 487 return -1; 488 489 return 0; 490 } 491 492 static void 493 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) 494 { 495 struct rte_kvargs *kvlist; 496 u16 auto_neg = 1; 497 u16 poll = 0; 498 u16 present = 0; 499 u16 sgmii = 0; 500 u16 ffe_set = 0; 501 u16 ffe_main = 27; 502 u16 ffe_pre = 8; 503 u16 ffe_post = 44; 504 505 if (devargs == NULL) 506 goto null; 507 508 kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments); 509 if (kvlist == NULL) 510 goto null; 511 512 rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO, 513 &txgbe_handle_devarg, &auto_neg); 514 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL, 515 &txgbe_handle_devarg, &poll); 516 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT, 517 &txgbe_handle_devarg, &present); 518 rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII, 519 &txgbe_handle_devarg, &sgmii); 520 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET, 521 &txgbe_handle_devarg, &ffe_set); 522 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN, 523 &txgbe_handle_devarg, &ffe_main); 524 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE, 525 &txgbe_handle_devarg, &ffe_pre); 526 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST, 527 &txgbe_handle_devarg, &ffe_post); 528 rte_kvargs_free(kvlist); 529 530 null: 531 hw->devarg.auto_neg = auto_neg; 532 hw->devarg.poll = poll; 533 hw->devarg.present = present; 534 hw->devarg.sgmii = sgmii; 535 hw->phy.ffe_set = ffe_set; 536 hw->phy.ffe_main = ffe_main; 537 hw->phy.ffe_pre = ffe_pre; 538 hw->phy.ffe_post = ffe_post; 539 } 540 541 static int 542 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 543 { 544 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 545 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 546 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev); 547 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev); 548 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev); 549 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 550 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev); 551 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 552 const struct rte_memzone *mz; 553 uint32_t ctrl_ext; 554 uint16_t csum; 555 int err, i, ret; 556 557 PMD_INIT_FUNC_TRACE(); 558 559 eth_dev->dev_ops = &txgbe_eth_dev_ops; 560 eth_dev->rx_queue_count = txgbe_dev_rx_queue_count; 561 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status; 562 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status; 563 eth_dev->rx_pkt_burst = &txgbe_recv_pkts; 564 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts; 565 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts; 566 567 /* 568 * For secondary processes, we don't initialise any further as primary 569 * has already done this work. Only check we don't need a different 570 * RX and TX function. 571 */ 572 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 573 struct txgbe_tx_queue *txq; 574 /* TX queue function in primary, set by last queue initialized 575 * Tx queue may not initialized by primary process 576 */ 577 if (eth_dev->data->tx_queues) { 578 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues; 579 txq = eth_dev->data->tx_queues[nb_tx_queues - 1]; 580 txgbe_set_tx_function(eth_dev, txq); 581 } else { 582 /* Use default TX function if we get here */ 583 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 584 "Using default TX function."); 585 } 586 587 txgbe_set_rx_function(eth_dev); 588 589 return 0; 590 } 591 592 rte_eth_copy_pci_info(eth_dev, pci_dev); 593 594 /* Vendor and Device ID need to be set before init of shared code */ 595 hw->device_id = pci_dev->id.device_id; 596 hw->vendor_id = pci_dev->id.vendor_id; 597 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 598 hw->allow_unsupported_sfp = 1; 599 600 /* Reserve memory for interrupt status block */ 601 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1, 602 16, TXGBE_ALIGN, SOCKET_ID_ANY); 603 if (mz == NULL) 604 return -ENOMEM; 605 606 hw->isb_dma = TMZ_PADDR(mz); 607 hw->isb_mem = TMZ_VADDR(mz); 608 609 txgbe_parse_devargs(hw, pci_dev->device.devargs); 610 /* Initialize the shared code (base driver) */ 611 err = txgbe_init_shared_code(hw); 612 if (err != 0) { 613 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err); 614 return -EIO; 615 } 616 617 /* Unlock any pending hardware semaphore */ 618 txgbe_swfw_lock_reset(hw); 619 620 #ifdef RTE_LIB_SECURITY 621 /* Initialize security_ctx only for primary process*/ 622 if (txgbe_ipsec_ctx_create(eth_dev)) 623 return -ENOMEM; 624 #endif 625 626 /* Initialize DCB configuration*/ 627 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config)); 628 txgbe_dcb_init(hw, dcb_config); 629 630 /* Get Hardware Flow Control setting */ 631 hw->fc.requested_mode = txgbe_fc_full; 632 hw->fc.current_mode = txgbe_fc_full; 633 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME; 634 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 635 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH; 636 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH; 637 } 638 hw->fc.send_xon = 1; 639 640 err = hw->rom.init_params(hw); 641 if (err != 0) { 642 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err); 643 return -EIO; 644 } 645 646 /* Make sure we have a good EEPROM before we read from it */ 647 err = hw->rom.validate_checksum(hw, &csum); 648 if (err != 0) { 649 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err); 650 return -EIO; 651 } 652 653 err = hw->mac.init_hw(hw); 654 655 /* 656 * Devices with copper phys will fail to initialise if txgbe_init_hw() 657 * is called too soon after the kernel driver unbinding/binding occurs. 658 * The failure occurs in txgbe_identify_phy() for all devices, 659 * but for non-copper devies, txgbe_identify_sfp_module() is 660 * also called. See txgbe_identify_phy(). The reason for the 661 * failure is not known, and only occuts when virtualisation features 662 * are disabled in the bios. A delay of 200ms was found to be enough by 663 * trial-and-error, and is doubled to be safe. 664 */ 665 if (err && hw->phy.media_type == txgbe_media_type_copper) { 666 rte_delay_ms(200); 667 err = hw->mac.init_hw(hw); 668 } 669 670 if (err == TXGBE_ERR_SFP_NOT_PRESENT) 671 err = 0; 672 673 if (err == TXGBE_ERR_EEPROM_VERSION) { 674 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 675 "LOM. Please be aware there may be issues associated " 676 "with your hardware."); 677 PMD_INIT_LOG(ERR, "If you are experiencing problems " 678 "please contact your hardware representative " 679 "who provided you with this hardware."); 680 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) { 681 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 682 } 683 if (err) { 684 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err); 685 return -EIO; 686 } 687 688 /* Reset the hw statistics */ 689 txgbe_dev_stats_reset(eth_dev); 690 691 /* disable interrupt */ 692 txgbe_disable_intr(hw); 693 694 /* Allocate memory for storing MAC addresses */ 695 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN * 696 hw->mac.num_rar_entries, 0); 697 if (eth_dev->data->mac_addrs == NULL) { 698 PMD_INIT_LOG(ERR, 699 "Failed to allocate %u bytes needed to store " 700 "MAC addresses", 701 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 702 return -ENOMEM; 703 } 704 705 /* Copy the permanent MAC address */ 706 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 707 ð_dev->data->mac_addrs[0]); 708 709 /* Allocate memory for storing hash filter MAC addresses */ 710 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe", 711 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0); 712 if (eth_dev->data->hash_mac_addrs == NULL) { 713 PMD_INIT_LOG(ERR, 714 "Failed to allocate %d bytes needed to store MAC addresses", 715 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC); 716 return -ENOMEM; 717 } 718 719 /* initialize the vfta */ 720 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 721 722 /* initialize the hw strip bitmap*/ 723 memset(hwstrip, 0, sizeof(*hwstrip)); 724 725 /* initialize PF if max_vfs not zero */ 726 ret = txgbe_pf_host_init(eth_dev); 727 if (ret) { 728 rte_free(eth_dev->data->mac_addrs); 729 eth_dev->data->mac_addrs = NULL; 730 rte_free(eth_dev->data->hash_mac_addrs); 731 eth_dev->data->hash_mac_addrs = NULL; 732 return ret; 733 } 734 735 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 736 /* let hardware know driver is loaded */ 737 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD; 738 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 739 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 740 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 741 txgbe_flush(hw); 742 743 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present) 744 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 745 (int)hw->mac.type, (int)hw->phy.type, 746 (int)hw->phy.sfp_type); 747 else 748 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 749 (int)hw->mac.type, (int)hw->phy.type); 750 751 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 752 eth_dev->data->port_id, pci_dev->id.vendor_id, 753 pci_dev->id.device_id); 754 755 rte_intr_callback_register(intr_handle, 756 txgbe_dev_interrupt_handler, eth_dev); 757 758 /* enable uio/vfio intr/eventfd mapping */ 759 rte_intr_enable(intr_handle); 760 761 /* enable support intr */ 762 txgbe_enable_intr(eth_dev); 763 764 /* initialize filter info */ 765 memset(filter_info, 0, 766 sizeof(struct txgbe_filter_info)); 767 768 /* initialize 5tuple filter list */ 769 TAILQ_INIT(&filter_info->fivetuple_list); 770 771 /* initialize flow director filter list & hash */ 772 txgbe_fdir_filter_init(eth_dev); 773 774 /* initialize l2 tunnel filter list & hash */ 775 txgbe_l2_tn_filter_init(eth_dev); 776 777 /* initialize flow filter lists */ 778 txgbe_filterlist_init(); 779 780 /* initialize bandwidth configuration info */ 781 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf)); 782 783 /* initialize Traffic Manager configuration */ 784 txgbe_tm_conf_init(eth_dev); 785 786 return 0; 787 } 788 789 static int 790 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev) 791 { 792 PMD_INIT_FUNC_TRACE(); 793 794 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 795 return 0; 796 797 txgbe_dev_close(eth_dev); 798 799 return 0; 800 } 801 802 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 803 { 804 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 805 struct txgbe_5tuple_filter *p_5tuple; 806 807 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 808 TAILQ_REMOVE(&filter_info->fivetuple_list, 809 p_5tuple, 810 entries); 811 rte_free(p_5tuple); 812 } 813 memset(filter_info->fivetuple_mask, 0, 814 sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE); 815 816 return 0; 817 } 818 819 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 820 { 821 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 822 struct txgbe_fdir_filter *fdir_filter; 823 824 if (fdir_info->hash_map) 825 rte_free(fdir_info->hash_map); 826 if (fdir_info->hash_handle) 827 rte_hash_free(fdir_info->hash_handle); 828 829 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 830 TAILQ_REMOVE(&fdir_info->fdir_list, 831 fdir_filter, 832 entries); 833 rte_free(fdir_filter); 834 } 835 836 return 0; 837 } 838 839 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 840 { 841 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 842 struct txgbe_l2_tn_filter *l2_tn_filter; 843 844 if (l2_tn_info->hash_map) 845 rte_free(l2_tn_info->hash_map); 846 if (l2_tn_info->hash_handle) 847 rte_hash_free(l2_tn_info->hash_handle); 848 849 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 850 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 851 l2_tn_filter, 852 entries); 853 rte_free(l2_tn_filter); 854 } 855 856 return 0; 857 } 858 859 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 860 { 861 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 862 char fdir_hash_name[RTE_HASH_NAMESIZE]; 863 struct rte_hash_parameters fdir_hash_params = { 864 .name = fdir_hash_name, 865 .entries = TXGBE_MAX_FDIR_FILTER_NUM, 866 .key_len = sizeof(struct txgbe_atr_input), 867 .hash_func = rte_hash_crc, 868 .hash_func_init_val = 0, 869 .socket_id = rte_socket_id(), 870 }; 871 872 TAILQ_INIT(&fdir_info->fdir_list); 873 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 874 "fdir_%s", TDEV_NAME(eth_dev)); 875 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 876 if (!fdir_info->hash_handle) { 877 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 878 return -EINVAL; 879 } 880 fdir_info->hash_map = rte_zmalloc("txgbe", 881 sizeof(struct txgbe_fdir_filter *) * 882 TXGBE_MAX_FDIR_FILTER_NUM, 883 0); 884 if (!fdir_info->hash_map) { 885 PMD_INIT_LOG(ERR, 886 "Failed to allocate memory for fdir hash map!"); 887 return -ENOMEM; 888 } 889 fdir_info->mask_added = FALSE; 890 891 return 0; 892 } 893 894 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 895 { 896 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 897 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 898 struct rte_hash_parameters l2_tn_hash_params = { 899 .name = l2_tn_hash_name, 900 .entries = TXGBE_MAX_L2_TN_FILTER_NUM, 901 .key_len = sizeof(struct txgbe_l2_tn_key), 902 .hash_func = rte_hash_crc, 903 .hash_func_init_val = 0, 904 .socket_id = rte_socket_id(), 905 }; 906 907 TAILQ_INIT(&l2_tn_info->l2_tn_list); 908 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 909 "l2_tn_%s", TDEV_NAME(eth_dev)); 910 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 911 if (!l2_tn_info->hash_handle) { 912 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 913 return -EINVAL; 914 } 915 l2_tn_info->hash_map = rte_zmalloc("txgbe", 916 sizeof(struct txgbe_l2_tn_filter *) * 917 TXGBE_MAX_L2_TN_FILTER_NUM, 918 0); 919 if (!l2_tn_info->hash_map) { 920 PMD_INIT_LOG(ERR, 921 "Failed to allocate memory for L2 TN hash map!"); 922 return -ENOMEM; 923 } 924 l2_tn_info->e_tag_en = FALSE; 925 l2_tn_info->e_tag_fwd_en = FALSE; 926 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 927 928 return 0; 929 } 930 931 static int 932 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 933 struct rte_pci_device *pci_dev) 934 { 935 return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 936 sizeof(struct txgbe_adapter), 937 eth_dev_pci_specific_init, pci_dev, 938 eth_txgbe_dev_init, NULL); 939 } 940 941 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev) 942 { 943 struct rte_eth_dev *ethdev; 944 945 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 946 if (!ethdev) 947 return 0; 948 949 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit); 950 } 951 952 static struct rte_pci_driver rte_txgbe_pmd = { 953 .id_table = pci_id_txgbe_map, 954 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | 955 RTE_PCI_DRV_INTR_LSC, 956 .probe = eth_txgbe_pci_probe, 957 .remove = eth_txgbe_pci_remove, 958 }; 959 960 static int 961 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 962 { 963 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 964 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 965 uint32_t vfta; 966 uint32_t vid_idx; 967 uint32_t vid_bit; 968 969 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F); 970 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F)); 971 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx)); 972 if (on) 973 vfta |= vid_bit; 974 else 975 vfta &= ~vid_bit; 976 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta); 977 978 /* update local VFTA copy */ 979 shadow_vfta->vfta[vid_idx] = vfta; 980 981 return 0; 982 } 983 984 static void 985 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 986 { 987 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 988 struct txgbe_rx_queue *rxq; 989 bool restart; 990 uint32_t rxcfg, rxbal, rxbah; 991 992 if (on) 993 txgbe_vlan_hw_strip_enable(dev, queue); 994 else 995 txgbe_vlan_hw_strip_disable(dev, queue); 996 997 rxq = dev->data->rx_queues[queue]; 998 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx)); 999 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx)); 1000 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx)); 1001 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 1002 restart = (rxcfg & TXGBE_RXCFG_ENA) && 1003 !(rxcfg & TXGBE_RXCFG_VLAN); 1004 rxcfg |= TXGBE_RXCFG_VLAN; 1005 } else { 1006 restart = (rxcfg & TXGBE_RXCFG_ENA) && 1007 (rxcfg & TXGBE_RXCFG_VLAN); 1008 rxcfg &= ~TXGBE_RXCFG_VLAN; 1009 } 1010 rxcfg &= ~TXGBE_RXCFG_ENA; 1011 1012 if (restart) { 1013 /* set vlan strip for ring */ 1014 txgbe_dev_rx_queue_stop(dev, queue); 1015 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal); 1016 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah); 1017 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg); 1018 txgbe_dev_rx_queue_start(dev, queue); 1019 } 1020 } 1021 1022 static int 1023 txgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1024 enum rte_vlan_type vlan_type, 1025 uint16_t tpid) 1026 { 1027 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1028 int ret = 0; 1029 uint32_t portctrl, vlan_ext, qinq; 1030 1031 portctrl = rd32(hw, TXGBE_PORTCTL); 1032 1033 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT); 1034 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ); 1035 switch (vlan_type) { 1036 case RTE_ETH_VLAN_TYPE_INNER: 1037 if (vlan_ext) { 1038 wr32m(hw, TXGBE_VLANCTL, 1039 TXGBE_VLANCTL_TPID_MASK, 1040 TXGBE_VLANCTL_TPID(tpid)); 1041 wr32m(hw, TXGBE_DMATXCTRL, 1042 TXGBE_DMATXCTRL_TPID_MASK, 1043 TXGBE_DMATXCTRL_TPID(tpid)); 1044 } else { 1045 ret = -ENOTSUP; 1046 PMD_DRV_LOG(ERR, "Inner type is not supported" 1047 " by single VLAN"); 1048 } 1049 1050 if (qinq) { 1051 wr32m(hw, TXGBE_TAGTPID(0), 1052 TXGBE_TAGTPID_LSB_MASK, 1053 TXGBE_TAGTPID_LSB(tpid)); 1054 } 1055 break; 1056 case RTE_ETH_VLAN_TYPE_OUTER: 1057 if (vlan_ext) { 1058 /* Only the high 16-bits is valid */ 1059 wr32m(hw, TXGBE_EXTAG, 1060 TXGBE_EXTAG_VLAN_MASK, 1061 TXGBE_EXTAG_VLAN(tpid)); 1062 } else { 1063 wr32m(hw, TXGBE_VLANCTL, 1064 TXGBE_VLANCTL_TPID_MASK, 1065 TXGBE_VLANCTL_TPID(tpid)); 1066 wr32m(hw, TXGBE_DMATXCTRL, 1067 TXGBE_DMATXCTRL_TPID_MASK, 1068 TXGBE_DMATXCTRL_TPID(tpid)); 1069 } 1070 1071 if (qinq) { 1072 wr32m(hw, TXGBE_TAGTPID(0), 1073 TXGBE_TAGTPID_MSB_MASK, 1074 TXGBE_TAGTPID_MSB(tpid)); 1075 } 1076 break; 1077 default: 1078 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1079 return -EINVAL; 1080 } 1081 1082 return ret; 1083 } 1084 1085 void 1086 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1087 { 1088 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1089 uint32_t vlnctrl; 1090 1091 PMD_INIT_FUNC_TRACE(); 1092 1093 /* Filter Table Disable */ 1094 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1095 vlnctrl &= ~TXGBE_VLANCTL_VFE; 1096 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1097 } 1098 1099 void 1100 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1101 { 1102 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1103 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 1104 uint32_t vlnctrl; 1105 uint16_t i; 1106 1107 PMD_INIT_FUNC_TRACE(); 1108 1109 /* Filter Table Enable */ 1110 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1111 vlnctrl &= ~TXGBE_VLANCTL_CFIENA; 1112 vlnctrl |= TXGBE_VLANCTL_VFE; 1113 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1114 1115 /* write whatever is in local vfta copy */ 1116 for (i = 0; i < TXGBE_VFTA_SIZE; i++) 1117 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]); 1118 } 1119 1120 void 1121 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1122 { 1123 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev); 1124 struct txgbe_rx_queue *rxq; 1125 1126 if (queue >= TXGBE_MAX_RX_QUEUE_NUM) 1127 return; 1128 1129 if (on) 1130 TXGBE_SET_HWSTRIP(hwstrip, queue); 1131 else 1132 TXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1133 1134 if (queue >= dev->data->nb_rx_queues) 1135 return; 1136 1137 rxq = dev->data->rx_queues[queue]; 1138 1139 if (on) { 1140 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED; 1141 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1142 } else { 1143 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN; 1144 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1145 } 1146 } 1147 1148 static void 1149 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1150 { 1151 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1152 uint32_t ctrl; 1153 1154 PMD_INIT_FUNC_TRACE(); 1155 1156 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1157 ctrl &= ~TXGBE_RXCFG_VLAN; 1158 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1159 1160 /* record those setting for HW strip per queue */ 1161 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 1162 } 1163 1164 static void 1165 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 1166 { 1167 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1168 uint32_t ctrl; 1169 1170 PMD_INIT_FUNC_TRACE(); 1171 1172 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1173 ctrl |= TXGBE_RXCFG_VLAN; 1174 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1175 1176 /* record those setting for HW strip per queue */ 1177 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 1178 } 1179 1180 static void 1181 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 1182 { 1183 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1184 uint32_t ctrl; 1185 1186 PMD_INIT_FUNC_TRACE(); 1187 1188 ctrl = rd32(hw, TXGBE_PORTCTL); 1189 ctrl &= ~TXGBE_PORTCTL_VLANEXT; 1190 wr32(hw, TXGBE_PORTCTL, ctrl); 1191 } 1192 1193 static void 1194 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 1195 { 1196 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1197 uint32_t ctrl; 1198 1199 PMD_INIT_FUNC_TRACE(); 1200 1201 ctrl = rd32(hw, TXGBE_PORTCTL); 1202 ctrl |= TXGBE_PORTCTL_VLANEXT; 1203 wr32(hw, TXGBE_PORTCTL, ctrl); 1204 } 1205 1206 static void 1207 txgbe_qinq_hw_strip_disable(struct rte_eth_dev *dev) 1208 { 1209 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1210 uint32_t ctrl; 1211 1212 PMD_INIT_FUNC_TRACE(); 1213 1214 ctrl = rd32(hw, TXGBE_PORTCTL); 1215 ctrl &= ~TXGBE_PORTCTL_QINQ; 1216 wr32(hw, TXGBE_PORTCTL, ctrl); 1217 } 1218 1219 static void 1220 txgbe_qinq_hw_strip_enable(struct rte_eth_dev *dev) 1221 { 1222 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1223 uint32_t ctrl; 1224 1225 PMD_INIT_FUNC_TRACE(); 1226 1227 ctrl = rd32(hw, TXGBE_PORTCTL); 1228 ctrl |= TXGBE_PORTCTL_QINQ | TXGBE_PORTCTL_VLANEXT; 1229 wr32(hw, TXGBE_PORTCTL, ctrl); 1230 } 1231 1232 void 1233 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 1234 { 1235 struct txgbe_rx_queue *rxq; 1236 uint16_t i; 1237 1238 PMD_INIT_FUNC_TRACE(); 1239 1240 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1241 rxq = dev->data->rx_queues[i]; 1242 1243 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 1244 txgbe_vlan_strip_queue_set(dev, i, 1); 1245 else 1246 txgbe_vlan_strip_queue_set(dev, i, 0); 1247 } 1248 } 1249 1250 void 1251 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 1252 { 1253 uint16_t i; 1254 struct rte_eth_rxmode *rxmode; 1255 struct txgbe_rx_queue *rxq; 1256 1257 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1258 rxmode = &dev->data->dev_conf.rxmode; 1259 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 1260 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1261 rxq = dev->data->rx_queues[i]; 1262 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1263 } 1264 else 1265 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1266 rxq = dev->data->rx_queues[i]; 1267 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1268 } 1269 } 1270 } 1271 1272 static int 1273 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 1274 { 1275 struct rte_eth_rxmode *rxmode; 1276 rxmode = &dev->data->dev_conf.rxmode; 1277 1278 if (mask & RTE_ETH_VLAN_STRIP_MASK) 1279 txgbe_vlan_hw_strip_config(dev); 1280 1281 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1282 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 1283 txgbe_vlan_hw_filter_enable(dev); 1284 else 1285 txgbe_vlan_hw_filter_disable(dev); 1286 } 1287 1288 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1289 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) 1290 txgbe_vlan_hw_extend_enable(dev); 1291 else 1292 txgbe_vlan_hw_extend_disable(dev); 1293 } 1294 1295 if (mask & RTE_ETH_QINQ_STRIP_MASK) { 1296 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) 1297 txgbe_qinq_hw_strip_enable(dev); 1298 else 1299 txgbe_qinq_hw_strip_disable(dev); 1300 } 1301 1302 return 0; 1303 } 1304 1305 static int 1306 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1307 { 1308 txgbe_config_vlan_strip_on_all_queues(dev, mask); 1309 1310 txgbe_vlan_offload_config(dev, mask); 1311 1312 return 0; 1313 } 1314 1315 static void 1316 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1317 { 1318 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1319 /* VLNCTL: enable vlan filtering and allow all vlan tags through */ 1320 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL); 1321 1322 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */ 1323 wr32(hw, TXGBE_VLANCTL, vlanctrl); 1324 } 1325 1326 static int 1327 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 1328 { 1329 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1330 1331 switch (nb_rx_q) { 1332 case 1: 1333 case 2: 1334 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_64_POOLS; 1335 break; 1336 case 4: 1337 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_32_POOLS; 1338 break; 1339 default: 1340 return -EINVAL; 1341 } 1342 1343 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1344 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1345 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 1346 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1347 return 0; 1348 } 1349 1350 static int 1351 txgbe_check_mq_mode(struct rte_eth_dev *dev) 1352 { 1353 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1354 uint16_t nb_rx_q = dev->data->nb_rx_queues; 1355 uint16_t nb_tx_q = dev->data->nb_tx_queues; 1356 1357 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 1358 /* check multi-queue mode */ 1359 switch (dev_conf->rxmode.mq_mode) { 1360 case RTE_ETH_MQ_RX_VMDQ_DCB: 1361 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 1362 break; 1363 case RTE_ETH_MQ_RX_VMDQ_DCB_RSS: 1364 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 1365 PMD_INIT_LOG(ERR, "SRIOV active," 1366 " unsupported mq_mode rx %d.", 1367 dev_conf->rxmode.mq_mode); 1368 return -EINVAL; 1369 case RTE_ETH_MQ_RX_RSS: 1370 case RTE_ETH_MQ_RX_VMDQ_RSS: 1371 dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_RSS; 1372 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 1373 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 1374 PMD_INIT_LOG(ERR, "SRIOV is active," 1375 " invalid queue number" 1376 " for VMDQ RSS, allowed" 1377 " value are 1, 2 or 4."); 1378 return -EINVAL; 1379 } 1380 break; 1381 case RTE_ETH_MQ_RX_VMDQ_ONLY: 1382 case RTE_ETH_MQ_RX_NONE: 1383 /* if nothing mq mode configure, use default scheme */ 1384 dev->data->dev_conf.rxmode.mq_mode = 1385 RTE_ETH_MQ_RX_VMDQ_ONLY; 1386 break; 1387 default: /* RTE_ETH_MQ_RX_DCB, RTE_ETH_MQ_RX_DCB_RSS or RTE_ETH_MQ_TX_DCB*/ 1388 /* SRIOV only works in VMDq enable mode */ 1389 PMD_INIT_LOG(ERR, "SRIOV is active," 1390 " wrong mq_mode rx %d.", 1391 dev_conf->rxmode.mq_mode); 1392 return -EINVAL; 1393 } 1394 1395 switch (dev_conf->txmode.mq_mode) { 1396 case RTE_ETH_MQ_TX_VMDQ_DCB: 1397 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 1398 dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_DCB; 1399 break; 1400 default: /* RTE_ETH_MQ_TX_VMDQ_ONLY or RTE_ETH_MQ_TX_NONE */ 1401 dev->data->dev_conf.txmode.mq_mode = 1402 RTE_ETH_MQ_TX_VMDQ_ONLY; 1403 break; 1404 } 1405 1406 /* check valid queue number */ 1407 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 1408 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 1409 PMD_INIT_LOG(ERR, "SRIOV is active," 1410 " nb_rx_q=%d nb_tx_q=%d queue number" 1411 " must be less than or equal to %d.", 1412 nb_rx_q, nb_tx_q, 1413 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 1414 return -EINVAL; 1415 } 1416 } else { 1417 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB_RSS) { 1418 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 1419 " not supported."); 1420 return -EINVAL; 1421 } 1422 /* check configuration for vmdb+dcb mode */ 1423 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB) { 1424 const struct rte_eth_vmdq_dcb_conf *conf; 1425 1426 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1427 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 1428 TXGBE_VMDQ_DCB_NB_QUEUES); 1429 return -EINVAL; 1430 } 1431 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 1432 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS || 1433 conf->nb_queue_pools == RTE_ETH_32_POOLS)) { 1434 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1435 " nb_queue_pools must be %d or %d.", 1436 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS); 1437 return -EINVAL; 1438 } 1439 } 1440 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) { 1441 const struct rte_eth_vmdq_dcb_tx_conf *conf; 1442 1443 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1444 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 1445 TXGBE_VMDQ_DCB_NB_QUEUES); 1446 return -EINVAL; 1447 } 1448 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 1449 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS || 1450 conf->nb_queue_pools == RTE_ETH_32_POOLS)) { 1451 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1452 " nb_queue_pools != %d and" 1453 " nb_queue_pools != %d.", 1454 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS); 1455 return -EINVAL; 1456 } 1457 } 1458 1459 /* For DCB mode check our configuration before we go further */ 1460 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_DCB) { 1461 const struct rte_eth_dcb_rx_conf *conf; 1462 1463 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 1464 if (!(conf->nb_tcs == RTE_ETH_4_TCS || 1465 conf->nb_tcs == RTE_ETH_8_TCS)) { 1466 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1467 " and nb_tcs != %d.", 1468 RTE_ETH_4_TCS, RTE_ETH_8_TCS); 1469 return -EINVAL; 1470 } 1471 } 1472 1473 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_DCB) { 1474 const struct rte_eth_dcb_tx_conf *conf; 1475 1476 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 1477 if (!(conf->nb_tcs == RTE_ETH_4_TCS || 1478 conf->nb_tcs == RTE_ETH_8_TCS)) { 1479 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1480 " and nb_tcs != %d.", 1481 RTE_ETH_4_TCS, RTE_ETH_8_TCS); 1482 return -EINVAL; 1483 } 1484 } 1485 } 1486 return 0; 1487 } 1488 1489 static int 1490 txgbe_dev_configure(struct rte_eth_dev *dev) 1491 { 1492 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1493 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1494 int ret; 1495 1496 PMD_INIT_FUNC_TRACE(); 1497 1498 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 1499 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 1500 1501 /* multiple queue mode checking */ 1502 ret = txgbe_check_mq_mode(dev); 1503 if (ret != 0) { 1504 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.", 1505 ret); 1506 return ret; 1507 } 1508 1509 /* set flag to update link status after init */ 1510 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 1511 1512 /* 1513 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 1514 * allocation Rx preconditions we will reset it. 1515 */ 1516 adapter->rx_bulk_alloc_allowed = true; 1517 1518 return 0; 1519 } 1520 1521 static void 1522 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 1523 { 1524 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1525 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1526 uint32_t gpie; 1527 1528 gpie = rd32(hw, TXGBE_GPIOINTEN); 1529 gpie |= TXGBE_GPIOBIT_6; 1530 wr32(hw, TXGBE_GPIOINTEN, gpie); 1531 intr->mask_misc |= TXGBE_ICRMISC_GPIO; 1532 intr->mask_misc |= TXGBE_ICRMISC_ANDONE; 1533 } 1534 1535 int 1536 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 1537 uint16_t tx_rate, uint64_t q_msk) 1538 { 1539 struct txgbe_hw *hw; 1540 struct txgbe_vf_info *vfinfo; 1541 struct rte_eth_link link; 1542 uint8_t nb_q_per_pool; 1543 uint32_t queue_stride; 1544 uint32_t queue_idx, idx = 0, vf_idx; 1545 uint32_t queue_end; 1546 uint16_t total_rate = 0; 1547 struct rte_pci_device *pci_dev; 1548 int ret; 1549 1550 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1551 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 1552 if (ret < 0) 1553 return ret; 1554 1555 if (vf >= pci_dev->max_vfs) 1556 return -EINVAL; 1557 1558 if (tx_rate > link.link_speed) 1559 return -EINVAL; 1560 1561 if (q_msk == 0) 1562 return 0; 1563 1564 hw = TXGBE_DEV_HW(dev); 1565 vfinfo = *(TXGBE_DEV_VFDATA(dev)); 1566 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1567 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1568 queue_idx = vf * queue_stride; 1569 queue_end = queue_idx + nb_q_per_pool - 1; 1570 if (queue_end >= hw->mac.max_tx_queues) 1571 return -EINVAL; 1572 1573 if (vfinfo) { 1574 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 1575 if (vf_idx == vf) 1576 continue; 1577 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 1578 idx++) 1579 total_rate += vfinfo[vf_idx].tx_rate[idx]; 1580 } 1581 } else { 1582 return -EINVAL; 1583 } 1584 1585 /* Store tx_rate for this vf. */ 1586 for (idx = 0; idx < nb_q_per_pool; idx++) { 1587 if (((uint64_t)0x1 << idx) & q_msk) { 1588 if (vfinfo[vf].tx_rate[idx] != tx_rate) 1589 vfinfo[vf].tx_rate[idx] = tx_rate; 1590 total_rate += tx_rate; 1591 } 1592 } 1593 1594 if (total_rate > dev->data->dev_link.link_speed) { 1595 /* Reset stored TX rate of the VF if it causes exceed 1596 * link speed. 1597 */ 1598 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 1599 return -EINVAL; 1600 } 1601 1602 /* Set ARBTXRATE of each queue/pool for vf X */ 1603 for (; queue_idx <= queue_end; queue_idx++) { 1604 if (0x1 & q_msk) 1605 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 1606 q_msk = q_msk >> 1; 1607 } 1608 1609 return 0; 1610 } 1611 1612 /* 1613 * Configure device link speed and setup link. 1614 * It returns 0 on success. 1615 */ 1616 static int 1617 txgbe_dev_start(struct rte_eth_dev *dev) 1618 { 1619 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1620 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 1621 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1622 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1623 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1624 uint32_t intr_vector = 0; 1625 int err; 1626 bool link_up = false, negotiate = 0; 1627 uint32_t speed = 0; 1628 uint32_t allowed_speeds = 0; 1629 int mask = 0; 1630 int status; 1631 uint16_t vf, idx; 1632 uint32_t *link_speeds; 1633 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1634 1635 PMD_INIT_FUNC_TRACE(); 1636 1637 /* Stop the link setup handler before resetting the HW. */ 1638 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1639 1640 /* disable uio/vfio intr/eventfd mapping */ 1641 rte_intr_disable(intr_handle); 1642 1643 /* stop adapter */ 1644 hw->adapter_stopped = 0; 1645 txgbe_stop_hw(hw); 1646 1647 /* reinitialize adapter 1648 * this calls reset and start 1649 */ 1650 hw->nb_rx_queues = dev->data->nb_rx_queues; 1651 hw->nb_tx_queues = dev->data->nb_tx_queues; 1652 status = txgbe_pf_reset_hw(hw); 1653 if (status != 0) 1654 return -1; 1655 hw->mac.start_hw(hw); 1656 hw->mac.get_link_status = true; 1657 hw->dev_start = true; 1658 1659 /* configure PF module if SRIOV enabled */ 1660 txgbe_pf_host_configure(dev); 1661 1662 txgbe_dev_phy_intr_setup(dev); 1663 1664 /* check and configure queue intr-vector mapping */ 1665 if ((rte_intr_cap_multiple(intr_handle) || 1666 !RTE_ETH_DEV_SRIOV(dev).active) && 1667 dev->data->dev_conf.intr_conf.rxq != 0) { 1668 intr_vector = dev->data->nb_rx_queues; 1669 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1670 return -1; 1671 } 1672 1673 if (rte_intr_dp_is_en(intr_handle)) { 1674 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 1675 dev->data->nb_rx_queues)) { 1676 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 1677 " intr_vec", dev->data->nb_rx_queues); 1678 return -ENOMEM; 1679 } 1680 } 1681 /* confiugre msix for sleep until rx interrupt */ 1682 txgbe_configure_msix(dev); 1683 1684 /* initialize transmission unit */ 1685 txgbe_dev_tx_init(dev); 1686 1687 /* This can fail when allocating mbufs for descriptor rings */ 1688 err = txgbe_dev_rx_init(dev); 1689 if (err) { 1690 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 1691 goto error; 1692 } 1693 1694 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 1695 RTE_ETH_VLAN_EXTEND_MASK; 1696 err = txgbe_vlan_offload_config(dev, mask); 1697 if (err) { 1698 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 1699 goto error; 1700 } 1701 1702 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) { 1703 /* Enable vlan filtering for VMDq */ 1704 txgbe_vmdq_vlan_hw_filter_enable(dev); 1705 } 1706 1707 /* Configure DCB hw */ 1708 txgbe_configure_pb(dev); 1709 txgbe_configure_port(dev); 1710 txgbe_configure_dcb(dev); 1711 1712 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1713 err = txgbe_fdir_configure(dev); 1714 if (err) 1715 goto error; 1716 } 1717 1718 /* Restore vf rate limit */ 1719 if (vfinfo != NULL) { 1720 for (vf = 0; vf < pci_dev->max_vfs; vf++) 1721 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 1722 if (vfinfo[vf].tx_rate[idx] != 0) 1723 txgbe_set_vf_rate_limit(dev, vf, 1724 vfinfo[vf].tx_rate[idx], 1725 1 << idx); 1726 } 1727 1728 err = txgbe_dev_rxtx_start(dev); 1729 if (err < 0) { 1730 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 1731 goto error; 1732 } 1733 1734 /* Skip link setup if loopback mode is enabled. */ 1735 if (hw->mac.type == txgbe_mac_raptor && 1736 dev->data->dev_conf.lpbk_mode) 1737 goto skip_link_setup; 1738 1739 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 1740 err = hw->mac.setup_sfp(hw); 1741 if (err) 1742 goto error; 1743 } 1744 1745 if (hw->phy.media_type == txgbe_media_type_copper) { 1746 /* Turn on the copper */ 1747 hw->phy.set_phy_power(hw, true); 1748 } else { 1749 /* Turn on the laser */ 1750 hw->mac.enable_tx_laser(hw); 1751 } 1752 1753 if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4) 1754 err = hw->mac.check_link(hw, &speed, &link_up, 0); 1755 if (err) 1756 goto error; 1757 dev->data->dev_link.link_status = link_up; 1758 1759 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate); 1760 if (err) 1761 goto error; 1762 1763 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G | 1764 RTE_ETH_LINK_SPEED_10G; 1765 1766 link_speeds = &dev->data->dev_conf.link_speeds; 1767 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { 1768 PMD_INIT_LOG(ERR, "Invalid link setting"); 1769 goto error; 1770 } 1771 1772 speed = 0x0; 1773 if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 1774 speed = (TXGBE_LINK_SPEED_100M_FULL | 1775 TXGBE_LINK_SPEED_1GB_FULL | 1776 TXGBE_LINK_SPEED_10GB_FULL); 1777 } else { 1778 if (*link_speeds & RTE_ETH_LINK_SPEED_10G) 1779 speed |= TXGBE_LINK_SPEED_10GB_FULL; 1780 if (*link_speeds & RTE_ETH_LINK_SPEED_5G) 1781 speed |= TXGBE_LINK_SPEED_5GB_FULL; 1782 if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G) 1783 speed |= TXGBE_LINK_SPEED_2_5GB_FULL; 1784 if (*link_speeds & RTE_ETH_LINK_SPEED_1G) 1785 speed |= TXGBE_LINK_SPEED_1GB_FULL; 1786 if (*link_speeds & RTE_ETH_LINK_SPEED_100M) 1787 speed |= TXGBE_LINK_SPEED_100M_FULL; 1788 } 1789 1790 err = hw->mac.setup_link(hw, speed, link_up); 1791 if (err) 1792 goto error; 1793 1794 skip_link_setup: 1795 1796 if (rte_intr_allow_others(intr_handle)) { 1797 txgbe_dev_misc_interrupt_setup(dev); 1798 /* check if lsc interrupt is enabled */ 1799 if (dev->data->dev_conf.intr_conf.lsc != 0) 1800 txgbe_dev_lsc_interrupt_setup(dev, TRUE); 1801 else 1802 txgbe_dev_lsc_interrupt_setup(dev, FALSE); 1803 txgbe_dev_macsec_interrupt_setup(dev); 1804 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 1805 } else { 1806 rte_intr_callback_unregister(intr_handle, 1807 txgbe_dev_interrupt_handler, dev); 1808 if (dev->data->dev_conf.intr_conf.lsc != 0) 1809 PMD_INIT_LOG(INFO, "lsc won't enable because of" 1810 " no intr multiplex"); 1811 } 1812 1813 /* check if rxq interrupt is enabled */ 1814 if (dev->data->dev_conf.intr_conf.rxq != 0 && 1815 rte_intr_dp_is_en(intr_handle)) 1816 txgbe_dev_rxq_interrupt_setup(dev); 1817 1818 /* enable uio/vfio intr/eventfd mapping */ 1819 rte_intr_enable(intr_handle); 1820 1821 /* resume enabled intr since hw reset */ 1822 txgbe_enable_intr(dev); 1823 txgbe_l2_tunnel_conf(dev); 1824 txgbe_filter_restore(dev); 1825 1826 if (tm_conf->root && !tm_conf->committed) 1827 PMD_DRV_LOG(WARNING, 1828 "please call hierarchy_commit() " 1829 "before starting the port"); 1830 1831 /* 1832 * Update link status right before return, because it may 1833 * start link configuration process in a separate thread. 1834 */ 1835 txgbe_dev_link_update(dev, 0); 1836 1837 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK); 1838 1839 txgbe_read_stats_registers(hw, hw_stats); 1840 hw->offset_loaded = 1; 1841 1842 return 0; 1843 1844 error: 1845 PMD_INIT_LOG(ERR, "failure in dev start: %d", err); 1846 txgbe_dev_clear_queues(dev); 1847 return -EIO; 1848 } 1849 1850 /* 1851 * Stop device: disable rx and tx functions to allow for reconfiguring. 1852 */ 1853 static int 1854 txgbe_dev_stop(struct rte_eth_dev *dev) 1855 { 1856 struct rte_eth_link link; 1857 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1858 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1859 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1860 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1861 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1862 int vf; 1863 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1864 1865 if (hw->adapter_stopped) 1866 return 0; 1867 1868 PMD_INIT_FUNC_TRACE(); 1869 1870 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1871 1872 /* disable interrupts */ 1873 txgbe_disable_intr(hw); 1874 1875 /* reset the NIC */ 1876 txgbe_pf_reset_hw(hw); 1877 hw->adapter_stopped = 0; 1878 1879 /* stop adapter */ 1880 txgbe_stop_hw(hw); 1881 1882 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 1883 vfinfo[vf].clear_to_send = false; 1884 1885 if (hw->phy.media_type == txgbe_media_type_copper) { 1886 /* Turn off the copper */ 1887 hw->phy.set_phy_power(hw, false); 1888 } else { 1889 /* Turn off the laser */ 1890 hw->mac.disable_tx_laser(hw); 1891 } 1892 1893 txgbe_dev_clear_queues(dev); 1894 1895 /* Clear stored conf */ 1896 dev->data->scattered_rx = 0; 1897 dev->data->lro = 0; 1898 1899 /* Clear recorded link status */ 1900 memset(&link, 0, sizeof(link)); 1901 rte_eth_linkstatus_set(dev, &link); 1902 1903 if (!rte_intr_allow_others(intr_handle)) 1904 /* resume to the default handler */ 1905 rte_intr_callback_register(intr_handle, 1906 txgbe_dev_interrupt_handler, 1907 (void *)dev); 1908 1909 /* Clean datapath event and queue/vec mapping */ 1910 rte_intr_efd_disable(intr_handle); 1911 rte_intr_vec_list_free(intr_handle); 1912 1913 /* reset hierarchy commit */ 1914 tm_conf->committed = false; 1915 1916 adapter->rss_reta_updated = 0; 1917 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK); 1918 1919 hw->adapter_stopped = true; 1920 dev->data->dev_started = 0; 1921 hw->dev_start = false; 1922 1923 return 0; 1924 } 1925 1926 /* 1927 * Set device link up: enable tx. 1928 */ 1929 static int 1930 txgbe_dev_set_link_up(struct rte_eth_dev *dev) 1931 { 1932 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1933 1934 if (hw->phy.media_type == txgbe_media_type_copper) { 1935 /* Turn on the copper */ 1936 hw->phy.set_phy_power(hw, true); 1937 } else { 1938 /* Turn on the laser */ 1939 hw->mac.enable_tx_laser(hw); 1940 txgbe_dev_link_update(dev, 0); 1941 } 1942 1943 return 0; 1944 } 1945 1946 /* 1947 * Set device link down: disable tx. 1948 */ 1949 static int 1950 txgbe_dev_set_link_down(struct rte_eth_dev *dev) 1951 { 1952 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1953 1954 if (hw->phy.media_type == txgbe_media_type_copper) { 1955 /* Turn off the copper */ 1956 hw->phy.set_phy_power(hw, false); 1957 } else { 1958 /* Turn off the laser */ 1959 hw->mac.disable_tx_laser(hw); 1960 txgbe_dev_link_update(dev, 0); 1961 } 1962 1963 return 0; 1964 } 1965 1966 /* 1967 * Reset and stop device. 1968 */ 1969 static int 1970 txgbe_dev_close(struct rte_eth_dev *dev) 1971 { 1972 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1973 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1974 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1975 int retries = 0; 1976 int ret; 1977 1978 PMD_INIT_FUNC_TRACE(); 1979 1980 txgbe_pf_reset_hw(hw); 1981 1982 ret = txgbe_dev_stop(dev); 1983 1984 txgbe_dev_free_queues(dev); 1985 1986 /* reprogram the RAR[0] in case user changed it. */ 1987 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true); 1988 1989 /* Unlock any pending hardware semaphore */ 1990 txgbe_swfw_lock_reset(hw); 1991 1992 /* disable uio intr before callback unregister */ 1993 rte_intr_disable(intr_handle); 1994 1995 do { 1996 ret = rte_intr_callback_unregister(intr_handle, 1997 txgbe_dev_interrupt_handler, dev); 1998 if (ret >= 0 || ret == -ENOENT) { 1999 break; 2000 } else if (ret != -EAGAIN) { 2001 PMD_INIT_LOG(ERR, 2002 "intr callback unregister failed: %d", 2003 ret); 2004 } 2005 rte_delay_ms(100); 2006 } while (retries++ < (10 + TXGBE_LINK_UP_TIME)); 2007 2008 /* cancel the delay handler before remove dev */ 2009 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev); 2010 2011 /* uninitialize PF if max_vfs not zero */ 2012 txgbe_pf_host_uninit(dev); 2013 2014 rte_free(dev->data->mac_addrs); 2015 dev->data->mac_addrs = NULL; 2016 2017 rte_free(dev->data->hash_mac_addrs); 2018 dev->data->hash_mac_addrs = NULL; 2019 2020 /* remove all the fdir filters & hash */ 2021 txgbe_fdir_filter_uninit(dev); 2022 2023 /* remove all the L2 tunnel filters & hash */ 2024 txgbe_l2_tn_filter_uninit(dev); 2025 2026 /* Remove all ntuple filters of the device */ 2027 txgbe_ntuple_filter_uninit(dev); 2028 2029 /* clear all the filters list */ 2030 txgbe_filterlist_flush(); 2031 2032 /* Remove all Traffic Manager configuration */ 2033 txgbe_tm_conf_uninit(dev); 2034 2035 #ifdef RTE_LIB_SECURITY 2036 rte_free(dev->security_ctx); 2037 #endif 2038 2039 return ret; 2040 } 2041 2042 /* 2043 * Reset PF device. 2044 */ 2045 static int 2046 txgbe_dev_reset(struct rte_eth_dev *dev) 2047 { 2048 int ret; 2049 2050 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2051 * its VF to make them align with it. The detailed notification 2052 * mechanism is PMD specific. As to txgbe PF, it is rather complex. 2053 * To avoid unexpected behavior in VF, currently reset of PF with 2054 * SR-IOV activation is not supported. It might be supported later. 2055 */ 2056 if (dev->data->sriov.active) 2057 return -ENOTSUP; 2058 2059 ret = eth_txgbe_dev_uninit(dev); 2060 if (ret) 2061 return ret; 2062 2063 ret = eth_txgbe_dev_init(dev, NULL); 2064 2065 return ret; 2066 } 2067 2068 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \ 2069 { \ 2070 uint32_t current_counter = rd32(hw, reg); \ 2071 if (current_counter < last_counter) \ 2072 current_counter += 0x100000000LL; \ 2073 if (!hw->offset_loaded) \ 2074 last_counter = current_counter; \ 2075 counter = current_counter - last_counter; \ 2076 counter &= 0xFFFFFFFFLL; \ 2077 } 2078 2079 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ 2080 { \ 2081 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \ 2082 uint64_t current_counter_msb = rd32(hw, reg_msb); \ 2083 uint64_t current_counter = (current_counter_msb << 32) | \ 2084 current_counter_lsb; \ 2085 if (current_counter < last_counter) \ 2086 current_counter += 0x1000000000LL; \ 2087 if (!hw->offset_loaded) \ 2088 last_counter = current_counter; \ 2089 counter = current_counter - last_counter; \ 2090 counter &= 0xFFFFFFFFFLL; \ 2091 } 2092 2093 void 2094 txgbe_read_stats_registers(struct txgbe_hw *hw, 2095 struct txgbe_hw_stats *hw_stats) 2096 { 2097 unsigned int i; 2098 2099 /* QP Stats */ 2100 for (i = 0; i < hw->nb_rx_queues; i++) { 2101 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i), 2102 hw->qp_last[i].rx_qp_packets, 2103 hw_stats->qp[i].rx_qp_packets); 2104 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i), 2105 hw->qp_last[i].rx_qp_bytes, 2106 hw_stats->qp[i].rx_qp_bytes); 2107 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i), 2108 hw->qp_last[i].rx_qp_mc_packets, 2109 hw_stats->qp[i].rx_qp_mc_packets); 2110 } 2111 2112 for (i = 0; i < hw->nb_tx_queues; i++) { 2113 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i), 2114 hw->qp_last[i].tx_qp_packets, 2115 hw_stats->qp[i].tx_qp_packets); 2116 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i), 2117 hw->qp_last[i].tx_qp_bytes, 2118 hw_stats->qp[i].tx_qp_bytes); 2119 } 2120 /* PB Stats */ 2121 for (i = 0; i < TXGBE_MAX_UP; i++) { 2122 hw_stats->up[i].rx_up_xon_packets += 2123 rd32(hw, TXGBE_PBRXUPXON(i)); 2124 hw_stats->up[i].rx_up_xoff_packets += 2125 rd32(hw, TXGBE_PBRXUPXOFF(i)); 2126 hw_stats->up[i].tx_up_xon_packets += 2127 rd32(hw, TXGBE_PBTXUPXON(i)); 2128 hw_stats->up[i].tx_up_xoff_packets += 2129 rd32(hw, TXGBE_PBTXUPXOFF(i)); 2130 hw_stats->up[i].tx_up_xon2off_packets += 2131 rd32(hw, TXGBE_PBTXUPOFF(i)); 2132 hw_stats->up[i].rx_up_dropped += 2133 rd32(hw, TXGBE_PBRXMISS(i)); 2134 } 2135 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON); 2136 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF); 2137 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON); 2138 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF); 2139 2140 /* DMA Stats */ 2141 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT); 2142 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT); 2143 2144 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL); 2145 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL); 2146 hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP); 2147 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP); 2148 2149 /* MAC Stats */ 2150 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL); 2151 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL); 2152 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL); 2153 2154 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL); 2155 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL); 2156 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL); 2157 2158 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL); 2159 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL); 2160 2161 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L); 2162 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L); 2163 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L); 2164 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L); 2165 hw_stats->rx_size_512_to_1023_packets += 2166 rd64(hw, TXGBE_MACRX512TO1023L); 2167 hw_stats->rx_size_1024_to_max_packets += 2168 rd64(hw, TXGBE_MACRX1024TOMAXL); 2169 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L); 2170 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L); 2171 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L); 2172 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L); 2173 hw_stats->tx_size_512_to_1023_packets += 2174 rd64(hw, TXGBE_MACTX512TO1023L); 2175 hw_stats->tx_size_1024_to_max_packets += 2176 rd64(hw, TXGBE_MACTX1024TOMAXL); 2177 2178 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL); 2179 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE); 2180 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER); 2181 2182 /* MNG Stats */ 2183 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS); 2184 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC); 2185 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG); 2186 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG); 2187 2188 /* FCoE Stats */ 2189 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC); 2190 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST); 2191 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC); 2192 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC); 2193 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC); 2194 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC); 2195 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC); 2196 2197 /* Flow Director Stats */ 2198 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH); 2199 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS); 2200 hw_stats->flow_director_added_filters += 2201 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED)); 2202 hw_stats->flow_director_removed_filters += 2203 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED)); 2204 hw_stats->flow_director_filter_add_errors += 2205 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL)); 2206 hw_stats->flow_director_filter_remove_errors += 2207 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL)); 2208 2209 /* MACsec Stats */ 2210 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT); 2211 hw_stats->tx_macsec_pkts_encrypted += 2212 rd32(hw, TXGBE_LSECTX_ENCPKT); 2213 hw_stats->tx_macsec_pkts_protected += 2214 rd32(hw, TXGBE_LSECTX_PROTPKT); 2215 hw_stats->tx_macsec_octets_encrypted += 2216 rd32(hw, TXGBE_LSECTX_ENCOCT); 2217 hw_stats->tx_macsec_octets_protected += 2218 rd32(hw, TXGBE_LSECTX_PROTOCT); 2219 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT); 2220 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT); 2221 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT); 2222 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT); 2223 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT); 2224 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT); 2225 hw_stats->rx_macsec_sc_pkts_unchecked += 2226 rd32(hw, TXGBE_LSECRX_UNCHKPKT); 2227 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT); 2228 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT); 2229 for (i = 0; i < 2; i++) { 2230 hw_stats->rx_macsec_sa_pkts_ok += 2231 rd32(hw, TXGBE_LSECRX_OKPKT(i)); 2232 hw_stats->rx_macsec_sa_pkts_invalid += 2233 rd32(hw, TXGBE_LSECRX_INVPKT(i)); 2234 hw_stats->rx_macsec_sa_pkts_notvalid += 2235 rd32(hw, TXGBE_LSECRX_BADPKT(i)); 2236 } 2237 hw_stats->rx_macsec_sa_pkts_unusedsa += 2238 rd32(hw, TXGBE_LSECRX_INVSAPKT); 2239 hw_stats->rx_macsec_sa_pkts_notusingsa += 2240 rd32(hw, TXGBE_LSECRX_BADSAPKT); 2241 2242 hw_stats->rx_total_missed_packets = 0; 2243 for (i = 0; i < TXGBE_MAX_UP; i++) { 2244 hw_stats->rx_total_missed_packets += 2245 hw_stats->up[i].rx_up_dropped; 2246 } 2247 } 2248 2249 static int 2250 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 2251 { 2252 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2253 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2254 struct txgbe_stat_mappings *stat_mappings = 2255 TXGBE_DEV_STAT_MAPPINGS(dev); 2256 uint32_t i, j; 2257 2258 txgbe_read_stats_registers(hw, hw_stats); 2259 2260 if (stats == NULL) 2261 return -EINVAL; 2262 2263 /* Fill out the rte_eth_stats statistics structure */ 2264 stats->ipackets = hw_stats->rx_packets; 2265 stats->ibytes = hw_stats->rx_bytes; 2266 stats->opackets = hw_stats->tx_packets; 2267 stats->obytes = hw_stats->tx_bytes; 2268 2269 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets)); 2270 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets)); 2271 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes)); 2272 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes)); 2273 memset(&stats->q_errors, 0, sizeof(stats->q_errors)); 2274 for (i = 0; i < TXGBE_MAX_QP; i++) { 2275 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG; 2276 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8; 2277 uint32_t q_map; 2278 2279 q_map = (stat_mappings->rqsm[n] >> offset) 2280 & QMAP_FIELD_RESERVED_BITS_MASK; 2281 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2282 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2283 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets; 2284 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes; 2285 2286 q_map = (stat_mappings->tqsm[n] >> offset) 2287 & QMAP_FIELD_RESERVED_BITS_MASK; 2288 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2289 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2290 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets; 2291 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes; 2292 } 2293 2294 /* Rx Errors */ 2295 stats->imissed = hw_stats->rx_total_missed_packets + 2296 hw_stats->rx_dma_drop; 2297 stats->ierrors = hw_stats->rx_crc_errors + 2298 hw_stats->rx_mac_short_packet_dropped + 2299 hw_stats->rx_length_errors + 2300 hw_stats->rx_undersize_errors + 2301 hw_stats->rx_oversize_errors + 2302 hw_stats->rx_drop_packets + 2303 hw_stats->rx_illegal_byte_errors + 2304 hw_stats->rx_error_bytes + 2305 hw_stats->rx_fragment_errors + 2306 hw_stats->rx_fcoe_crc_errors + 2307 hw_stats->rx_fcoe_mbuf_allocation_errors; 2308 2309 /* Tx Errors */ 2310 stats->oerrors = 0; 2311 return 0; 2312 } 2313 2314 static int 2315 txgbe_dev_stats_reset(struct rte_eth_dev *dev) 2316 { 2317 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2318 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2319 2320 /* HW registers are cleared on read */ 2321 hw->offset_loaded = 0; 2322 txgbe_dev_stats_get(dev, NULL); 2323 hw->offset_loaded = 1; 2324 2325 /* Reset software totals */ 2326 memset(hw_stats, 0, sizeof(*hw_stats)); 2327 2328 return 0; 2329 } 2330 2331 /* This function calculates the number of xstats based on the current config */ 2332 static unsigned 2333 txgbe_xstats_calc_num(struct rte_eth_dev *dev) 2334 { 2335 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues); 2336 return TXGBE_NB_HW_STATS + 2337 TXGBE_NB_UP_STATS * TXGBE_MAX_UP + 2338 TXGBE_NB_QP_STATS * nb_queues; 2339 } 2340 2341 static inline int 2342 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size) 2343 { 2344 int nb, st; 2345 2346 /* Extended stats from txgbe_hw_stats */ 2347 if (id < TXGBE_NB_HW_STATS) { 2348 snprintf(name, size, "[hw]%s", 2349 rte_txgbe_stats_strings[id].name); 2350 return 0; 2351 } 2352 id -= TXGBE_NB_HW_STATS; 2353 2354 /* Priority Stats */ 2355 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2356 nb = id / TXGBE_NB_UP_STATS; 2357 st = id % TXGBE_NB_UP_STATS; 2358 snprintf(name, size, "[p%u]%s", nb, 2359 rte_txgbe_up_strings[st].name); 2360 return 0; 2361 } 2362 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2363 2364 /* Queue Stats */ 2365 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2366 nb = id / TXGBE_NB_QP_STATS; 2367 st = id % TXGBE_NB_QP_STATS; 2368 snprintf(name, size, "[q%u]%s", nb, 2369 rte_txgbe_qp_strings[st].name); 2370 return 0; 2371 } 2372 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP; 2373 2374 return -(int)(id + 1); 2375 } 2376 2377 static inline int 2378 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset) 2379 { 2380 int nb, st; 2381 2382 /* Extended stats from txgbe_hw_stats */ 2383 if (id < TXGBE_NB_HW_STATS) { 2384 *offset = rte_txgbe_stats_strings[id].offset; 2385 return 0; 2386 } 2387 id -= TXGBE_NB_HW_STATS; 2388 2389 /* Priority Stats */ 2390 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2391 nb = id / TXGBE_NB_UP_STATS; 2392 st = id % TXGBE_NB_UP_STATS; 2393 *offset = rte_txgbe_up_strings[st].offset + 2394 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t)); 2395 return 0; 2396 } 2397 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2398 2399 /* Queue Stats */ 2400 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2401 nb = id / TXGBE_NB_QP_STATS; 2402 st = id % TXGBE_NB_QP_STATS; 2403 *offset = rte_txgbe_qp_strings[st].offset + 2404 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t)); 2405 return 0; 2406 } 2407 2408 return -1; 2409 } 2410 2411 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 2412 struct rte_eth_xstat_name *xstats_names, unsigned int limit) 2413 { 2414 unsigned int i, count; 2415 2416 count = txgbe_xstats_calc_num(dev); 2417 if (xstats_names == NULL) 2418 return count; 2419 2420 /* Note: limit >= cnt_stats checked upstream 2421 * in rte_eth_xstats_names() 2422 */ 2423 limit = min(limit, count); 2424 2425 /* Extended stats from txgbe_hw_stats */ 2426 for (i = 0; i < limit; i++) { 2427 if (txgbe_get_name_by_id(i, xstats_names[i].name, 2428 sizeof(xstats_names[i].name))) { 2429 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2430 break; 2431 } 2432 } 2433 2434 return i; 2435 } 2436 2437 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 2438 const uint64_t *ids, 2439 struct rte_eth_xstat_name *xstats_names, 2440 unsigned int limit) 2441 { 2442 unsigned int i; 2443 2444 if (ids == NULL) 2445 return txgbe_dev_xstats_get_names(dev, xstats_names, limit); 2446 2447 for (i = 0; i < limit; i++) { 2448 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name, 2449 sizeof(xstats_names[i].name))) { 2450 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2451 return -1; 2452 } 2453 } 2454 2455 return i; 2456 } 2457 2458 static int 2459 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 2460 unsigned int limit) 2461 { 2462 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2463 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2464 unsigned int i, count; 2465 2466 txgbe_read_stats_registers(hw, hw_stats); 2467 2468 /* If this is a reset xstats is NULL, and we have cleared the 2469 * registers by reading them. 2470 */ 2471 count = txgbe_xstats_calc_num(dev); 2472 if (xstats == NULL) 2473 return count; 2474 2475 limit = min(limit, txgbe_xstats_calc_num(dev)); 2476 2477 /* Extended stats from txgbe_hw_stats */ 2478 for (i = 0; i < limit; i++) { 2479 uint32_t offset = 0; 2480 2481 if (txgbe_get_offset_by_id(i, &offset)) { 2482 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2483 break; 2484 } 2485 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset); 2486 xstats[i].id = i; 2487 } 2488 2489 return i; 2490 } 2491 2492 static int 2493 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values, 2494 unsigned int limit) 2495 { 2496 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2497 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2498 unsigned int i, count; 2499 2500 txgbe_read_stats_registers(hw, hw_stats); 2501 2502 /* If this is a reset xstats is NULL, and we have cleared the 2503 * registers by reading them. 2504 */ 2505 count = txgbe_xstats_calc_num(dev); 2506 if (values == NULL) 2507 return count; 2508 2509 limit = min(limit, txgbe_xstats_calc_num(dev)); 2510 2511 /* Extended stats from txgbe_hw_stats */ 2512 for (i = 0; i < limit; i++) { 2513 uint32_t offset; 2514 2515 if (txgbe_get_offset_by_id(i, &offset)) { 2516 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2517 break; 2518 } 2519 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2520 } 2521 2522 return i; 2523 } 2524 2525 static int 2526 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 2527 uint64_t *values, unsigned int limit) 2528 { 2529 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2530 unsigned int i; 2531 2532 if (ids == NULL) 2533 return txgbe_dev_xstats_get_(dev, values, limit); 2534 2535 for (i = 0; i < limit; i++) { 2536 uint32_t offset; 2537 2538 if (txgbe_get_offset_by_id(ids[i], &offset)) { 2539 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2540 break; 2541 } 2542 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2543 } 2544 2545 return i; 2546 } 2547 2548 static int 2549 txgbe_dev_xstats_reset(struct rte_eth_dev *dev) 2550 { 2551 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2552 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2553 2554 /* HW registers are cleared on read */ 2555 hw->offset_loaded = 0; 2556 txgbe_read_stats_registers(hw, hw_stats); 2557 hw->offset_loaded = 1; 2558 2559 /* Reset software totals */ 2560 memset(hw_stats, 0, sizeof(*hw_stats)); 2561 2562 return 0; 2563 } 2564 2565 static int 2566 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2567 { 2568 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2569 u32 etrack_id; 2570 int ret; 2571 2572 hw->phy.get_fw_version(hw, &etrack_id); 2573 2574 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 2575 if (ret < 0) 2576 return -EINVAL; 2577 2578 ret += 1; /* add the size of '\0' */ 2579 if (fw_size < (size_t)ret) 2580 return ret; 2581 else 2582 return 0; 2583 } 2584 2585 static int 2586 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2587 { 2588 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2589 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2590 2591 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 2592 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 2593 dev_info->min_rx_bufsize = 1024; 2594 dev_info->max_rx_pktlen = 15872; 2595 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 2596 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC; 2597 dev_info->max_vfs = pci_dev->max_vfs; 2598 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS; 2599 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 2600 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 2601 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev); 2602 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) | 2603 dev_info->rx_queue_offload_capa); 2604 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev); 2605 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev); 2606 2607 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2608 .rx_thresh = { 2609 .pthresh = TXGBE_DEFAULT_RX_PTHRESH, 2610 .hthresh = TXGBE_DEFAULT_RX_HTHRESH, 2611 .wthresh = TXGBE_DEFAULT_RX_WTHRESH, 2612 }, 2613 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH, 2614 .rx_drop_en = 0, 2615 .offloads = 0, 2616 }; 2617 2618 dev_info->default_txconf = (struct rte_eth_txconf) { 2619 .tx_thresh = { 2620 .pthresh = TXGBE_DEFAULT_TX_PTHRESH, 2621 .hthresh = TXGBE_DEFAULT_TX_HTHRESH, 2622 .wthresh = TXGBE_DEFAULT_TX_WTHRESH, 2623 }, 2624 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH, 2625 .offloads = 0, 2626 }; 2627 2628 dev_info->rx_desc_lim = rx_desc_lim; 2629 dev_info->tx_desc_lim = tx_desc_lim; 2630 2631 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 2632 dev_info->reta_size = RTE_ETH_RSS_RETA_SIZE_128; 2633 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL; 2634 2635 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G; 2636 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100M; 2637 2638 /* Driver-preferred Rx/Tx parameters */ 2639 dev_info->default_rxportconf.burst_size = 32; 2640 dev_info->default_txportconf.burst_size = 32; 2641 dev_info->default_rxportconf.nb_queues = 1; 2642 dev_info->default_txportconf.nb_queues = 1; 2643 dev_info->default_rxportconf.ring_size = 256; 2644 dev_info->default_txportconf.ring_size = 256; 2645 2646 return 0; 2647 } 2648 2649 const uint32_t * 2650 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 2651 { 2652 if (dev->rx_pkt_burst == txgbe_recv_pkts || 2653 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc || 2654 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc || 2655 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc) 2656 return txgbe_get_supported_ptypes(); 2657 2658 return NULL; 2659 } 2660 2661 void 2662 txgbe_dev_setup_link_alarm_handler(void *param) 2663 { 2664 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 2665 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2666 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2667 u32 speed; 2668 bool autoneg = false; 2669 2670 speed = hw->phy.autoneg_advertised; 2671 if (!speed) 2672 hw->mac.get_link_capabilities(hw, &speed, &autoneg); 2673 2674 hw->mac.setup_link(hw, speed, true); 2675 2676 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2677 } 2678 2679 /* return 0 means link status changed, -1 means not changed */ 2680 int 2681 txgbe_dev_link_update_share(struct rte_eth_dev *dev, 2682 int wait_to_complete) 2683 { 2684 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2685 struct rte_eth_link link; 2686 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; 2687 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2688 bool link_up; 2689 int err; 2690 int wait = 1; 2691 2692 memset(&link, 0, sizeof(link)); 2693 link.link_status = RTE_ETH_LINK_DOWN; 2694 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 2695 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 2696 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2697 RTE_ETH_LINK_SPEED_FIXED); 2698 2699 hw->mac.get_link_status = true; 2700 2701 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG) 2702 return rte_eth_linkstatus_set(dev, &link); 2703 2704 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 2705 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 2706 wait = 0; 2707 2708 err = hw->mac.check_link(hw, &link_speed, &link_up, wait); 2709 2710 if (err != 0) { 2711 link.link_speed = RTE_ETH_SPEED_NUM_100M; 2712 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 2713 return rte_eth_linkstatus_set(dev, &link); 2714 } 2715 2716 if (link_up == 0) { 2717 if ((hw->subsystem_device_id & 0xFF) == 2718 TXGBE_DEV_ID_KR_KX_KX4) { 2719 hw->mac.bp_down_event(hw); 2720 } else if (hw->phy.media_type == txgbe_media_type_fiber) { 2721 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG; 2722 rte_eal_alarm_set(10, 2723 txgbe_dev_setup_link_alarm_handler, dev); 2724 } 2725 return rte_eth_linkstatus_set(dev, &link); 2726 } else if (!hw->dev_start) { 2727 return rte_eth_linkstatus_set(dev, &link); 2728 } 2729 2730 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2731 link.link_status = RTE_ETH_LINK_UP; 2732 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 2733 2734 switch (link_speed) { 2735 default: 2736 case TXGBE_LINK_SPEED_UNKNOWN: 2737 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 2738 link.link_speed = RTE_ETH_SPEED_NUM_100M; 2739 break; 2740 2741 case TXGBE_LINK_SPEED_100M_FULL: 2742 link.link_speed = RTE_ETH_SPEED_NUM_100M; 2743 break; 2744 2745 case TXGBE_LINK_SPEED_1GB_FULL: 2746 link.link_speed = RTE_ETH_SPEED_NUM_1G; 2747 break; 2748 2749 case TXGBE_LINK_SPEED_2_5GB_FULL: 2750 link.link_speed = RTE_ETH_SPEED_NUM_2_5G; 2751 break; 2752 2753 case TXGBE_LINK_SPEED_5GB_FULL: 2754 link.link_speed = RTE_ETH_SPEED_NUM_5G; 2755 break; 2756 2757 case TXGBE_LINK_SPEED_10GB_FULL: 2758 link.link_speed = RTE_ETH_SPEED_NUM_10G; 2759 break; 2760 } 2761 2762 return rte_eth_linkstatus_set(dev, &link); 2763 } 2764 2765 static int 2766 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 2767 { 2768 return txgbe_dev_link_update_share(dev, wait_to_complete); 2769 } 2770 2771 static int 2772 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 2773 { 2774 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2775 uint32_t fctrl; 2776 2777 fctrl = rd32(hw, TXGBE_PSRCTL); 2778 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP); 2779 wr32(hw, TXGBE_PSRCTL, fctrl); 2780 2781 return 0; 2782 } 2783 2784 static int 2785 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 2786 { 2787 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2788 uint32_t fctrl; 2789 2790 fctrl = rd32(hw, TXGBE_PSRCTL); 2791 fctrl &= (~TXGBE_PSRCTL_UCP); 2792 if (dev->data->all_multicast == 1) 2793 fctrl |= TXGBE_PSRCTL_MCP; 2794 else 2795 fctrl &= (~TXGBE_PSRCTL_MCP); 2796 wr32(hw, TXGBE_PSRCTL, fctrl); 2797 2798 return 0; 2799 } 2800 2801 static int 2802 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 2803 { 2804 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2805 uint32_t fctrl; 2806 2807 fctrl = rd32(hw, TXGBE_PSRCTL); 2808 fctrl |= TXGBE_PSRCTL_MCP; 2809 wr32(hw, TXGBE_PSRCTL, fctrl); 2810 2811 return 0; 2812 } 2813 2814 static int 2815 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 2816 { 2817 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2818 uint32_t fctrl; 2819 2820 if (dev->data->promiscuous == 1) 2821 return 0; /* must remain in all_multicast mode */ 2822 2823 fctrl = rd32(hw, TXGBE_PSRCTL); 2824 fctrl &= (~TXGBE_PSRCTL_MCP); 2825 wr32(hw, TXGBE_PSRCTL, fctrl); 2826 2827 return 0; 2828 } 2829 2830 /** 2831 * It clears the interrupt causes and enables the interrupt. 2832 * It will be called once only during nic initialized. 2833 * 2834 * @param dev 2835 * Pointer to struct rte_eth_dev. 2836 * @param on 2837 * Enable or Disable. 2838 * 2839 * @return 2840 * - On success, zero. 2841 * - On failure, a negative value. 2842 */ 2843 static int 2844 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 2845 { 2846 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2847 2848 txgbe_dev_link_status_print(dev); 2849 if (on) 2850 intr->mask_misc |= TXGBE_ICRMISC_LSC; 2851 else 2852 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 2853 2854 return 0; 2855 } 2856 2857 static int 2858 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev) 2859 { 2860 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2861 u64 mask; 2862 2863 mask = TXGBE_ICR_MASK; 2864 mask &= (1ULL << TXGBE_MISC_VEC_ID); 2865 intr->mask |= mask; 2866 intr->mask_misc |= TXGBE_ICRMISC_GPIO; 2867 intr->mask_misc |= TXGBE_ICRMISC_ANDONE; 2868 return 0; 2869 } 2870 2871 /** 2872 * It clears the interrupt causes and enables the interrupt. 2873 * It will be called once only during nic initialized. 2874 * 2875 * @param dev 2876 * Pointer to struct rte_eth_dev. 2877 * 2878 * @return 2879 * - On success, zero. 2880 * - On failure, a negative value. 2881 */ 2882 static int 2883 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 2884 { 2885 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2886 u64 mask; 2887 2888 mask = TXGBE_ICR_MASK; 2889 mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1); 2890 intr->mask |= mask; 2891 2892 return 0; 2893 } 2894 2895 /** 2896 * It clears the interrupt causes and enables the interrupt. 2897 * It will be called once only during nic initialized. 2898 * 2899 * @param dev 2900 * Pointer to struct rte_eth_dev. 2901 * 2902 * @return 2903 * - On success, zero. 2904 * - On failure, a negative value. 2905 */ 2906 static int 2907 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 2908 { 2909 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2910 2911 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC; 2912 2913 return 0; 2914 } 2915 2916 /* 2917 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update. 2918 * 2919 * @param dev 2920 * Pointer to struct rte_eth_dev. 2921 * 2922 * @return 2923 * - On success, zero. 2924 * - On failure, a negative value. 2925 */ 2926 static int 2927 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, 2928 struct rte_intr_handle *intr_handle) 2929 { 2930 uint32_t eicr; 2931 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2932 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2933 2934 if (rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_UIO && 2935 rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX) 2936 wr32(hw, TXGBE_PX_INTA, 1); 2937 2938 /* clear all cause mask */ 2939 txgbe_disable_intr(hw); 2940 2941 /* read-on-clear nic registers here */ 2942 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 2943 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 2944 2945 intr->flags = 0; 2946 2947 /* set flag for async link update */ 2948 if (eicr & TXGBE_ICRMISC_LSC) 2949 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 2950 2951 if (eicr & TXGBE_ICRMISC_ANDONE) 2952 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG; 2953 2954 if (eicr & TXGBE_ICRMISC_VFMBX) 2955 intr->flags |= TXGBE_FLAG_MAILBOX; 2956 2957 if (eicr & TXGBE_ICRMISC_LNKSEC) 2958 intr->flags |= TXGBE_FLAG_MACSEC; 2959 2960 if (eicr & TXGBE_ICRMISC_GPIO) 2961 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT; 2962 2963 return 0; 2964 } 2965 2966 /** 2967 * It gets and then prints the link status. 2968 * 2969 * @param dev 2970 * Pointer to struct rte_eth_dev. 2971 * 2972 * @return 2973 * - On success, zero. 2974 * - On failure, a negative value. 2975 */ 2976 static void 2977 txgbe_dev_link_status_print(struct rte_eth_dev *dev) 2978 { 2979 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2980 struct rte_eth_link link; 2981 2982 rte_eth_linkstatus_get(dev, &link); 2983 2984 if (link.link_status) { 2985 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 2986 (int)(dev->data->port_id), 2987 (unsigned int)link.link_speed, 2988 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ? 2989 "full-duplex" : "half-duplex"); 2990 } else { 2991 PMD_INIT_LOG(INFO, " Port %d: Link Down", 2992 (int)(dev->data->port_id)); 2993 } 2994 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 2995 pci_dev->addr.domain, 2996 pci_dev->addr.bus, 2997 pci_dev->addr.devid, 2998 pci_dev->addr.function); 2999 } 3000 3001 /* 3002 * It executes link_update after knowing an interrupt occurred. 3003 * 3004 * @param dev 3005 * Pointer to struct rte_eth_dev. 3006 * 3007 * @return 3008 * - On success, zero. 3009 * - On failure, a negative value. 3010 */ 3011 static int 3012 txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 3013 struct rte_intr_handle *intr_handle) 3014 { 3015 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 3016 int64_t timeout; 3017 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3018 3019 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 3020 3021 if (intr->flags & TXGBE_FLAG_MAILBOX) { 3022 txgbe_pf_mbx_process(dev); 3023 intr->flags &= ~TXGBE_FLAG_MAILBOX; 3024 } 3025 3026 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 3027 hw->phy.handle_lasi(hw); 3028 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 3029 } 3030 3031 if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) { 3032 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) { 3033 hw->mac.kr_handle(hw); 3034 intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG; 3035 } 3036 } 3037 3038 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 3039 struct rte_eth_link link; 3040 3041 /*get the link status before link update, for predicting later*/ 3042 rte_eth_linkstatus_get(dev, &link); 3043 3044 txgbe_dev_link_update(dev, 0); 3045 3046 /* likely to up */ 3047 if (!link.link_status) 3048 /* handle it 1 sec later, wait it being stable */ 3049 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT; 3050 /* likely to down */ 3051 else if ((hw->subsystem_device_id & 0xFF) == 3052 TXGBE_DEV_ID_KR_KX_KX4 && 3053 hw->devarg.auto_neg == 1) 3054 /* handle it 2 sec later for backplane AN73 */ 3055 timeout = 2000; 3056 else 3057 /* handle it 4 sec later, wait it being stable */ 3058 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT; 3059 3060 txgbe_dev_link_status_print(dev); 3061 if (rte_eal_alarm_set(timeout * 1000, 3062 txgbe_dev_interrupt_delayed_handler, 3063 (void *)dev) < 0) { 3064 PMD_DRV_LOG(ERR, "Error setting alarm"); 3065 } else { 3066 /* only disable lsc interrupt */ 3067 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 3068 3069 intr->mask_orig = intr->mask; 3070 /* only disable all misc interrupts */ 3071 intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID); 3072 } 3073 } 3074 3075 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 3076 txgbe_enable_intr(dev); 3077 rte_intr_enable(intr_handle); 3078 3079 return 0; 3080 } 3081 3082 /** 3083 * Interrupt handler which shall be registered for alarm callback for delayed 3084 * handling specific interrupt to wait for the stable nic state. As the 3085 * NIC interrupt state is not stable for txgbe after link is just down, 3086 * it needs to wait 4 seconds to get the stable status. 3087 * 3088 * @param handle 3089 * Pointer to interrupt handle. 3090 * @param param 3091 * The address of parameter (struct rte_eth_dev *) registered before. 3092 * 3093 * @return 3094 * void 3095 */ 3096 static void 3097 txgbe_dev_interrupt_delayed_handler(void *param) 3098 { 3099 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3100 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3101 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3102 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 3103 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3104 uint32_t eicr; 3105 3106 txgbe_disable_intr(hw); 3107 3108 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 3109 if (eicr & TXGBE_ICRMISC_VFMBX) 3110 txgbe_pf_mbx_process(dev); 3111 3112 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 3113 hw->phy.handle_lasi(hw); 3114 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 3115 } 3116 3117 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 3118 txgbe_dev_link_update(dev, 0); 3119 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE; 3120 txgbe_dev_link_status_print(dev); 3121 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 3122 NULL); 3123 } 3124 3125 if (intr->flags & TXGBE_FLAG_MACSEC) { 3126 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 3127 NULL); 3128 intr->flags &= ~TXGBE_FLAG_MACSEC; 3129 } 3130 3131 /* restore original mask */ 3132 intr->mask_misc |= TXGBE_ICRMISC_LSC; 3133 3134 intr->mask = intr->mask_orig; 3135 intr->mask_orig = 0; 3136 3137 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 3138 txgbe_enable_intr(dev); 3139 rte_intr_enable(intr_handle); 3140 } 3141 3142 /** 3143 * Interrupt handler triggered by NIC for handling 3144 * specific interrupt. 3145 * 3146 * @param handle 3147 * Pointer to interrupt handle. 3148 * @param param 3149 * The address of parameter (struct rte_eth_dev *) registered before. 3150 * 3151 * @return 3152 * void 3153 */ 3154 static void 3155 txgbe_dev_interrupt_handler(void *param) 3156 { 3157 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3158 3159 txgbe_dev_interrupt_get_status(dev, dev->intr_handle); 3160 txgbe_dev_interrupt_action(dev, dev->intr_handle); 3161 } 3162 3163 static int 3164 txgbe_dev_led_on(struct rte_eth_dev *dev) 3165 { 3166 struct txgbe_hw *hw; 3167 3168 hw = TXGBE_DEV_HW(dev); 3169 return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP; 3170 } 3171 3172 static int 3173 txgbe_dev_led_off(struct rte_eth_dev *dev) 3174 { 3175 struct txgbe_hw *hw; 3176 3177 hw = TXGBE_DEV_HW(dev); 3178 return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP; 3179 } 3180 3181 static int 3182 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3183 { 3184 struct txgbe_hw *hw; 3185 uint32_t mflcn_reg; 3186 uint32_t fccfg_reg; 3187 int rx_pause; 3188 int tx_pause; 3189 3190 hw = TXGBE_DEV_HW(dev); 3191 3192 fc_conf->pause_time = hw->fc.pause_time; 3193 fc_conf->high_water = hw->fc.high_water[0]; 3194 fc_conf->low_water = hw->fc.low_water[0]; 3195 fc_conf->send_xon = hw->fc.send_xon; 3196 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 3197 3198 /* 3199 * Return rx_pause status according to actual setting of 3200 * RXFCCFG register. 3201 */ 3202 mflcn_reg = rd32(hw, TXGBE_RXFCCFG); 3203 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC)) 3204 rx_pause = 1; 3205 else 3206 rx_pause = 0; 3207 3208 /* 3209 * Return tx_pause status according to actual setting of 3210 * TXFCCFG register. 3211 */ 3212 fccfg_reg = rd32(hw, TXGBE_TXFCCFG); 3213 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC)) 3214 tx_pause = 1; 3215 else 3216 tx_pause = 0; 3217 3218 if (rx_pause && tx_pause) 3219 fc_conf->mode = RTE_ETH_FC_FULL; 3220 else if (rx_pause) 3221 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 3222 else if (tx_pause) 3223 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 3224 else 3225 fc_conf->mode = RTE_ETH_FC_NONE; 3226 3227 return 0; 3228 } 3229 3230 static int 3231 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3232 { 3233 struct txgbe_hw *hw; 3234 int err; 3235 uint32_t rx_buf_size; 3236 uint32_t max_high_water; 3237 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3238 txgbe_fc_none, 3239 txgbe_fc_rx_pause, 3240 txgbe_fc_tx_pause, 3241 txgbe_fc_full 3242 }; 3243 3244 PMD_INIT_FUNC_TRACE(); 3245 3246 hw = TXGBE_DEV_HW(dev); 3247 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0)); 3248 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3249 3250 /* 3251 * At least reserve one Ethernet frame for watermark 3252 * high_water/low_water in kilo bytes for txgbe 3253 */ 3254 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3255 if (fc_conf->high_water > max_high_water || 3256 fc_conf->high_water < fc_conf->low_water) { 3257 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3258 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3259 return -EINVAL; 3260 } 3261 3262 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode]; 3263 hw->fc.pause_time = fc_conf->pause_time; 3264 hw->fc.high_water[0] = fc_conf->high_water; 3265 hw->fc.low_water[0] = fc_conf->low_water; 3266 hw->fc.send_xon = fc_conf->send_xon; 3267 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 3268 3269 err = txgbe_fc_enable(hw); 3270 3271 /* Not negotiated is not an error case */ 3272 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) { 3273 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK, 3274 (fc_conf->mac_ctrl_frame_fwd 3275 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP)); 3276 txgbe_flush(hw); 3277 3278 return 0; 3279 } 3280 3281 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err); 3282 return -EIO; 3283 } 3284 3285 static int 3286 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 3287 struct rte_eth_pfc_conf *pfc_conf) 3288 { 3289 int err; 3290 uint32_t rx_buf_size; 3291 uint32_t max_high_water; 3292 uint8_t tc_num; 3293 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 }; 3294 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3295 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 3296 3297 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3298 txgbe_fc_none, 3299 txgbe_fc_rx_pause, 3300 txgbe_fc_tx_pause, 3301 txgbe_fc_full 3302 }; 3303 3304 PMD_INIT_FUNC_TRACE(); 3305 3306 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map); 3307 tc_num = map[pfc_conf->priority]; 3308 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num)); 3309 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3310 /* 3311 * At least reserve one Ethernet frame for watermark 3312 * high_water/low_water in kilo bytes for txgbe 3313 */ 3314 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3315 if (pfc_conf->fc.high_water > max_high_water || 3316 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) { 3317 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3318 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3319 return -EINVAL; 3320 } 3321 3322 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode]; 3323 hw->fc.pause_time = pfc_conf->fc.pause_time; 3324 hw->fc.send_xon = pfc_conf->fc.send_xon; 3325 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 3326 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 3327 3328 err = txgbe_dcb_pfc_enable(hw, tc_num); 3329 3330 /* Not negotiated is not an error case */ 3331 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) 3332 return 0; 3333 3334 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err); 3335 return -EIO; 3336 } 3337 3338 int 3339 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 3340 struct rte_eth_rss_reta_entry64 *reta_conf, 3341 uint16_t reta_size) 3342 { 3343 uint8_t i, j, mask; 3344 uint32_t reta; 3345 uint16_t idx, shift; 3346 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 3347 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3348 3349 PMD_INIT_FUNC_TRACE(); 3350 3351 if (!txgbe_rss_update_sp(hw->mac.type)) { 3352 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 3353 "NIC."); 3354 return -ENOTSUP; 3355 } 3356 3357 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) { 3358 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3359 "(%d) doesn't match the number hardware can supported " 3360 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128); 3361 return -EINVAL; 3362 } 3363 3364 for (i = 0; i < reta_size; i += 4) { 3365 idx = i / RTE_ETH_RETA_GROUP_SIZE; 3366 shift = i % RTE_ETH_RETA_GROUP_SIZE; 3367 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3368 if (!mask) 3369 continue; 3370 3371 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3372 for (j = 0; j < 4; j++) { 3373 if (RS8(mask, j, 0x1)) { 3374 reta &= ~(MS32(8 * j, 0xFF)); 3375 reta |= LS32(reta_conf[idx].reta[shift + j], 3376 8 * j, 0xFF); 3377 } 3378 } 3379 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta); 3380 } 3381 adapter->rss_reta_updated = 1; 3382 3383 return 0; 3384 } 3385 3386 int 3387 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 3388 struct rte_eth_rss_reta_entry64 *reta_conf, 3389 uint16_t reta_size) 3390 { 3391 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3392 uint8_t i, j, mask; 3393 uint32_t reta; 3394 uint16_t idx, shift; 3395 3396 PMD_INIT_FUNC_TRACE(); 3397 3398 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) { 3399 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3400 "(%d) doesn't match the number hardware can supported " 3401 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128); 3402 return -EINVAL; 3403 } 3404 3405 for (i = 0; i < reta_size; i += 4) { 3406 idx = i / RTE_ETH_RETA_GROUP_SIZE; 3407 shift = i % RTE_ETH_RETA_GROUP_SIZE; 3408 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3409 if (!mask) 3410 continue; 3411 3412 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3413 for (j = 0; j < 4; j++) { 3414 if (RS8(mask, j, 0x1)) 3415 reta_conf[idx].reta[shift + j] = 3416 (uint16_t)RS32(reta, 8 * j, 0xFF); 3417 } 3418 } 3419 3420 return 0; 3421 } 3422 3423 static int 3424 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 3425 uint32_t index, uint32_t pool) 3426 { 3427 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3428 uint32_t enable_addr = 1; 3429 3430 return txgbe_set_rar(hw, index, mac_addr->addr_bytes, 3431 pool, enable_addr); 3432 } 3433 3434 static void 3435 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 3436 { 3437 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3438 3439 txgbe_clear_rar(hw, index); 3440 } 3441 3442 static int 3443 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 3444 { 3445 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3446 3447 txgbe_remove_rar(dev, 0); 3448 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 3449 3450 return 0; 3451 } 3452 3453 static int 3454 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3455 { 3456 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3457 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 3458 struct rte_eth_dev_data *dev_data = dev->data; 3459 3460 /* If device is started, refuse mtu that requires the support of 3461 * scattered packets when this feature has not been enabled before. 3462 */ 3463 if (dev_data->dev_started && !dev_data->scattered_rx && 3464 (frame_size + 2 * TXGBE_VLAN_TAG_SIZE > 3465 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 3466 PMD_INIT_LOG(ERR, "Stop port first."); 3467 return -EINVAL; 3468 } 3469 3470 if (hw->mode) 3471 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3472 TXGBE_FRAME_SIZE_MAX); 3473 else 3474 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3475 TXGBE_FRMSZ_MAX(frame_size)); 3476 3477 return 0; 3478 } 3479 3480 static uint32_t 3481 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr) 3482 { 3483 uint32_t vector = 0; 3484 3485 switch (hw->mac.mc_filter_type) { 3486 case 0: /* use bits [47:36] of the address */ 3487 vector = ((uc_addr->addr_bytes[4] >> 4) | 3488 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 3489 break; 3490 case 1: /* use bits [46:35] of the address */ 3491 vector = ((uc_addr->addr_bytes[4] >> 3) | 3492 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 3493 break; 3494 case 2: /* use bits [45:34] of the address */ 3495 vector = ((uc_addr->addr_bytes[4] >> 2) | 3496 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 3497 break; 3498 case 3: /* use bits [43:32] of the address */ 3499 vector = ((uc_addr->addr_bytes[4]) | 3500 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 3501 break; 3502 default: /* Invalid mc_filter_type */ 3503 break; 3504 } 3505 3506 /* vector can only be 12-bits or boundary will be exceeded */ 3507 vector &= 0xFFF; 3508 return vector; 3509 } 3510 3511 static int 3512 txgbe_uc_hash_table_set(struct rte_eth_dev *dev, 3513 struct rte_ether_addr *mac_addr, uint8_t on) 3514 { 3515 uint32_t vector; 3516 uint32_t uta_idx; 3517 uint32_t reg_val; 3518 uint32_t uta_mask; 3519 uint32_t psrctl; 3520 3521 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3522 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3523 3524 /* The UTA table only exists on pf hardware */ 3525 if (hw->mac.type < txgbe_mac_raptor) 3526 return -ENOTSUP; 3527 3528 vector = txgbe_uta_vector(hw, mac_addr); 3529 uta_idx = (vector >> 5) & 0x7F; 3530 uta_mask = 0x1UL << (vector & 0x1F); 3531 3532 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask)) 3533 return 0; 3534 3535 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx)); 3536 if (on) { 3537 uta_info->uta_in_use++; 3538 reg_val |= uta_mask; 3539 uta_info->uta_shadow[uta_idx] |= uta_mask; 3540 } else { 3541 uta_info->uta_in_use--; 3542 reg_val &= ~uta_mask; 3543 uta_info->uta_shadow[uta_idx] &= ~uta_mask; 3544 } 3545 3546 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val); 3547 3548 psrctl = rd32(hw, TXGBE_PSRCTL); 3549 if (uta_info->uta_in_use > 0) 3550 psrctl |= TXGBE_PSRCTL_UCHFENA; 3551 else 3552 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3553 3554 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3555 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3556 wr32(hw, TXGBE_PSRCTL, psrctl); 3557 3558 return 0; 3559 } 3560 3561 static int 3562 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 3563 { 3564 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3565 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3566 uint32_t psrctl; 3567 int i; 3568 3569 /* The UTA table only exists on pf hardware */ 3570 if (hw->mac.type < txgbe_mac_raptor) 3571 return -ENOTSUP; 3572 3573 if (on) { 3574 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3575 uta_info->uta_shadow[i] = ~0; 3576 wr32(hw, TXGBE_UCADDRTBL(i), ~0); 3577 } 3578 } else { 3579 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3580 uta_info->uta_shadow[i] = 0; 3581 wr32(hw, TXGBE_UCADDRTBL(i), 0); 3582 } 3583 } 3584 3585 psrctl = rd32(hw, TXGBE_PSRCTL); 3586 if (on) 3587 psrctl |= TXGBE_PSRCTL_UCHFENA; 3588 else 3589 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3590 3591 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3592 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3593 wr32(hw, TXGBE_PSRCTL, psrctl); 3594 3595 return 0; 3596 } 3597 3598 uint32_t 3599 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 3600 { 3601 uint32_t new_val = orig_val; 3602 3603 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_UNTAG) 3604 new_val |= TXGBE_POOLETHCTL_UTA; 3605 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_MC) 3606 new_val |= TXGBE_POOLETHCTL_MCHA; 3607 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_UC) 3608 new_val |= TXGBE_POOLETHCTL_UCHA; 3609 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_BROADCAST) 3610 new_val |= TXGBE_POOLETHCTL_BCA; 3611 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_MULTICAST) 3612 new_val |= TXGBE_POOLETHCTL_MCP; 3613 3614 return new_val; 3615 } 3616 3617 static int 3618 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 3619 { 3620 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3621 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3622 uint32_t mask; 3623 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3624 3625 if (queue_id < 32) { 3626 mask = rd32(hw, TXGBE_IMS(0)); 3627 mask &= (1 << queue_id); 3628 wr32(hw, TXGBE_IMS(0), mask); 3629 } else if (queue_id < 64) { 3630 mask = rd32(hw, TXGBE_IMS(1)); 3631 mask &= (1 << (queue_id - 32)); 3632 wr32(hw, TXGBE_IMS(1), mask); 3633 } 3634 rte_intr_enable(intr_handle); 3635 3636 return 0; 3637 } 3638 3639 static int 3640 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 3641 { 3642 uint32_t mask; 3643 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3644 3645 if (queue_id < 32) { 3646 mask = rd32(hw, TXGBE_IMS(0)); 3647 mask &= ~(1 << queue_id); 3648 wr32(hw, TXGBE_IMS(0), mask); 3649 } else if (queue_id < 64) { 3650 mask = rd32(hw, TXGBE_IMS(1)); 3651 mask &= ~(1 << (queue_id - 32)); 3652 wr32(hw, TXGBE_IMS(1), mask); 3653 } 3654 3655 return 0; 3656 } 3657 3658 /** 3659 * set the IVAR registers, mapping interrupt causes to vectors 3660 * @param hw 3661 * pointer to txgbe_hw struct 3662 * @direction 3663 * 0 for Rx, 1 for Tx, -1 for other causes 3664 * @queue 3665 * queue to map the corresponding interrupt to 3666 * @msix_vector 3667 * the vector to map to the corresponding queue 3668 */ 3669 void 3670 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction, 3671 uint8_t queue, uint8_t msix_vector) 3672 { 3673 uint32_t tmp, idx; 3674 3675 if (direction == -1) { 3676 /* other causes */ 3677 msix_vector |= TXGBE_IVARMISC_VLD; 3678 idx = 0; 3679 tmp = rd32(hw, TXGBE_IVARMISC); 3680 tmp &= ~(0xFF << idx); 3681 tmp |= (msix_vector << idx); 3682 wr32(hw, TXGBE_IVARMISC, tmp); 3683 } else { 3684 /* rx or tx causes */ 3685 /* Workround for ICR lost */ 3686 idx = ((16 * (queue & 1)) + (8 * direction)); 3687 tmp = rd32(hw, TXGBE_IVAR(queue >> 1)); 3688 tmp &= ~(0xFF << idx); 3689 tmp |= (msix_vector << idx); 3690 wr32(hw, TXGBE_IVAR(queue >> 1), tmp); 3691 } 3692 } 3693 3694 /** 3695 * Sets up the hardware to properly generate MSI-X interrupts 3696 * @hw 3697 * board private structure 3698 */ 3699 static void 3700 txgbe_configure_msix(struct rte_eth_dev *dev) 3701 { 3702 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3703 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 3704 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3705 uint32_t queue_id, base = TXGBE_MISC_VEC_ID; 3706 uint32_t vec = TXGBE_MISC_VEC_ID; 3707 uint32_t gpie; 3708 3709 /* won't configure msix register if no mapping is done 3710 * between intr vector and event fd 3711 * but if misx has been enabled already, need to configure 3712 * auto clean, auto mask and throttling. 3713 */ 3714 gpie = rd32(hw, TXGBE_GPIE); 3715 if (!rte_intr_dp_is_en(intr_handle) && 3716 !(gpie & TXGBE_GPIE_MSIX)) 3717 return; 3718 3719 if (rte_intr_allow_others(intr_handle)) { 3720 base = TXGBE_RX_VEC_START; 3721 vec = base; 3722 } 3723 3724 /* setup GPIE for MSI-x mode */ 3725 gpie = rd32(hw, TXGBE_GPIE); 3726 gpie |= TXGBE_GPIE_MSIX; 3727 wr32(hw, TXGBE_GPIE, gpie); 3728 3729 /* Populate the IVAR table and set the ITR values to the 3730 * corresponding register. 3731 */ 3732 if (rte_intr_dp_is_en(intr_handle)) { 3733 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 3734 queue_id++) { 3735 /* by default, 1:1 mapping */ 3736 txgbe_set_ivar_map(hw, 0, queue_id, vec); 3737 rte_intr_vec_list_index_set(intr_handle, 3738 queue_id, vec); 3739 if (vec < base + rte_intr_nb_efd_get(intr_handle) 3740 - 1) 3741 vec++; 3742 } 3743 3744 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 3745 } 3746 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID), 3747 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 3748 | TXGBE_ITR_WRDSA); 3749 } 3750 3751 int 3752 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 3753 uint16_t queue_idx, uint16_t tx_rate) 3754 { 3755 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3756 uint32_t bcnrc_val; 3757 3758 if (queue_idx >= hw->mac.max_tx_queues) 3759 return -EINVAL; 3760 3761 if (tx_rate != 0) { 3762 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate); 3763 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2); 3764 } else { 3765 bcnrc_val = 0; 3766 } 3767 3768 /* 3769 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW 3770 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 3771 */ 3772 wr32(hw, TXGBE_ARBTXMMW, 0x14); 3773 3774 /* Set ARBTXRATE of queue X */ 3775 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx); 3776 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val); 3777 txgbe_flush(hw); 3778 3779 return 0; 3780 } 3781 3782 int 3783 txgbe_syn_filter_set(struct rte_eth_dev *dev, 3784 struct rte_eth_syn_filter *filter, 3785 bool add) 3786 { 3787 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3788 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3789 uint32_t syn_info; 3790 uint32_t synqf; 3791 3792 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 3793 return -EINVAL; 3794 3795 syn_info = filter_info->syn_info; 3796 3797 if (add) { 3798 if (syn_info & TXGBE_SYNCLS_ENA) 3799 return -EINVAL; 3800 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue); 3801 synqf |= TXGBE_SYNCLS_ENA; 3802 3803 if (filter->hig_pri) 3804 synqf |= TXGBE_SYNCLS_HIPRIO; 3805 else 3806 synqf &= ~TXGBE_SYNCLS_HIPRIO; 3807 } else { 3808 synqf = rd32(hw, TXGBE_SYNCLS); 3809 if (!(syn_info & TXGBE_SYNCLS_ENA)) 3810 return -ENOENT; 3811 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA); 3812 } 3813 3814 filter_info->syn_info = synqf; 3815 wr32(hw, TXGBE_SYNCLS, synqf); 3816 txgbe_flush(hw); 3817 return 0; 3818 } 3819 3820 static inline enum txgbe_5tuple_protocol 3821 convert_protocol_type(uint8_t protocol_value) 3822 { 3823 if (protocol_value == IPPROTO_TCP) 3824 return TXGBE_5TF_PROT_TCP; 3825 else if (protocol_value == IPPROTO_UDP) 3826 return TXGBE_5TF_PROT_UDP; 3827 else if (protocol_value == IPPROTO_SCTP) 3828 return TXGBE_5TF_PROT_SCTP; 3829 else 3830 return TXGBE_5TF_PROT_NONE; 3831 } 3832 3833 /* inject a 5-tuple filter to HW */ 3834 static inline void 3835 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 3836 struct txgbe_5tuple_filter *filter) 3837 { 3838 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3839 int i; 3840 uint32_t ftqf, sdpqf; 3841 uint32_t l34timir = 0; 3842 uint32_t mask = TXGBE_5TFCTL0_MASK; 3843 3844 i = filter->index; 3845 sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port)); 3846 sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port)); 3847 3848 ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto); 3849 ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority); 3850 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 3851 mask &= ~TXGBE_5TFCTL0_MSADDR; 3852 if (filter->filter_info.dst_ip_mask == 0) 3853 mask &= ~TXGBE_5TFCTL0_MDADDR; 3854 if (filter->filter_info.src_port_mask == 0) 3855 mask &= ~TXGBE_5TFCTL0_MSPORT; 3856 if (filter->filter_info.dst_port_mask == 0) 3857 mask &= ~TXGBE_5TFCTL0_MDPORT; 3858 if (filter->filter_info.proto_mask == 0) 3859 mask &= ~TXGBE_5TFCTL0_MPROTO; 3860 ftqf |= mask; 3861 ftqf |= TXGBE_5TFCTL0_MPOOL; 3862 ftqf |= TXGBE_5TFCTL0_ENA; 3863 3864 wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip)); 3865 wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip)); 3866 wr32(hw, TXGBE_5TFPORT(i), sdpqf); 3867 wr32(hw, TXGBE_5TFCTL0(i), ftqf); 3868 3869 l34timir |= TXGBE_5TFCTL1_QP(filter->queue); 3870 wr32(hw, TXGBE_5TFCTL1(i), l34timir); 3871 } 3872 3873 /* 3874 * add a 5tuple filter 3875 * 3876 * @param 3877 * dev: Pointer to struct rte_eth_dev. 3878 * index: the index the filter allocates. 3879 * filter: pointer to the filter that will be added. 3880 * rx_queue: the queue id the filter assigned to. 3881 * 3882 * @return 3883 * - On success, zero. 3884 * - On failure, a negative value. 3885 */ 3886 static int 3887 txgbe_add_5tuple_filter(struct rte_eth_dev *dev, 3888 struct txgbe_5tuple_filter *filter) 3889 { 3890 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3891 int i, idx, shift; 3892 3893 /* 3894 * look for an unused 5tuple filter index, 3895 * and insert the filter to list. 3896 */ 3897 for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) { 3898 idx = i / (sizeof(uint32_t) * NBBY); 3899 shift = i % (sizeof(uint32_t) * NBBY); 3900 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 3901 filter_info->fivetuple_mask[idx] |= 1 << shift; 3902 filter->index = i; 3903 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 3904 filter, 3905 entries); 3906 break; 3907 } 3908 } 3909 if (i >= TXGBE_MAX_FTQF_FILTERS) { 3910 PMD_DRV_LOG(ERR, "5tuple filters are full."); 3911 return -ENOSYS; 3912 } 3913 3914 txgbe_inject_5tuple_filter(dev, filter); 3915 3916 return 0; 3917 } 3918 3919 /* 3920 * remove a 5tuple filter 3921 * 3922 * @param 3923 * dev: Pointer to struct rte_eth_dev. 3924 * filter: the pointer of the filter will be removed. 3925 */ 3926 static void 3927 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 3928 struct txgbe_5tuple_filter *filter) 3929 { 3930 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3931 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3932 uint16_t index = filter->index; 3933 3934 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 3935 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 3936 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 3937 rte_free(filter); 3938 3939 wr32(hw, TXGBE_5TFDADDR(index), 0); 3940 wr32(hw, TXGBE_5TFSADDR(index), 0); 3941 wr32(hw, TXGBE_5TFPORT(index), 0); 3942 wr32(hw, TXGBE_5TFCTL0(index), 0); 3943 wr32(hw, TXGBE_5TFCTL1(index), 0); 3944 } 3945 3946 static inline struct txgbe_5tuple_filter * 3947 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list, 3948 struct txgbe_5tuple_filter_info *key) 3949 { 3950 struct txgbe_5tuple_filter *it; 3951 3952 TAILQ_FOREACH(it, filter_list, entries) { 3953 if (memcmp(key, &it->filter_info, 3954 sizeof(struct txgbe_5tuple_filter_info)) == 0) { 3955 return it; 3956 } 3957 } 3958 return NULL; 3959 } 3960 3961 /* translate elements in struct rte_eth_ntuple_filter 3962 * to struct txgbe_5tuple_filter_info 3963 */ 3964 static inline int 3965 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 3966 struct txgbe_5tuple_filter_info *filter_info) 3967 { 3968 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM || 3969 filter->priority > TXGBE_5TUPLE_MAX_PRI || 3970 filter->priority < TXGBE_5TUPLE_MIN_PRI) 3971 return -EINVAL; 3972 3973 switch (filter->dst_ip_mask) { 3974 case UINT32_MAX: 3975 filter_info->dst_ip_mask = 0; 3976 filter_info->dst_ip = filter->dst_ip; 3977 break; 3978 case 0: 3979 filter_info->dst_ip_mask = 1; 3980 break; 3981 default: 3982 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 3983 return -EINVAL; 3984 } 3985 3986 switch (filter->src_ip_mask) { 3987 case UINT32_MAX: 3988 filter_info->src_ip_mask = 0; 3989 filter_info->src_ip = filter->src_ip; 3990 break; 3991 case 0: 3992 filter_info->src_ip_mask = 1; 3993 break; 3994 default: 3995 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 3996 return -EINVAL; 3997 } 3998 3999 switch (filter->dst_port_mask) { 4000 case UINT16_MAX: 4001 filter_info->dst_port_mask = 0; 4002 filter_info->dst_port = filter->dst_port; 4003 break; 4004 case 0: 4005 filter_info->dst_port_mask = 1; 4006 break; 4007 default: 4008 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 4009 return -EINVAL; 4010 } 4011 4012 switch (filter->src_port_mask) { 4013 case UINT16_MAX: 4014 filter_info->src_port_mask = 0; 4015 filter_info->src_port = filter->src_port; 4016 break; 4017 case 0: 4018 filter_info->src_port_mask = 1; 4019 break; 4020 default: 4021 PMD_DRV_LOG(ERR, "invalid src_port mask."); 4022 return -EINVAL; 4023 } 4024 4025 switch (filter->proto_mask) { 4026 case UINT8_MAX: 4027 filter_info->proto_mask = 0; 4028 filter_info->proto = 4029 convert_protocol_type(filter->proto); 4030 break; 4031 case 0: 4032 filter_info->proto_mask = 1; 4033 break; 4034 default: 4035 PMD_DRV_LOG(ERR, "invalid protocol mask."); 4036 return -EINVAL; 4037 } 4038 4039 filter_info->priority = (uint8_t)filter->priority; 4040 return 0; 4041 } 4042 4043 /* 4044 * add or delete a ntuple filter 4045 * 4046 * @param 4047 * dev: Pointer to struct rte_eth_dev. 4048 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 4049 * add: if true, add filter, if false, remove filter 4050 * 4051 * @return 4052 * - On success, zero. 4053 * - On failure, a negative value. 4054 */ 4055 int 4056 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 4057 struct rte_eth_ntuple_filter *ntuple_filter, 4058 bool add) 4059 { 4060 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4061 struct txgbe_5tuple_filter_info filter_5tuple; 4062 struct txgbe_5tuple_filter *filter; 4063 int ret; 4064 4065 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 4066 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 4067 return -EINVAL; 4068 } 4069 4070 memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info)); 4071 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 4072 if (ret < 0) 4073 return ret; 4074 4075 filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 4076 &filter_5tuple); 4077 if (filter != NULL && add) { 4078 PMD_DRV_LOG(ERR, "filter exists."); 4079 return -EEXIST; 4080 } 4081 if (filter == NULL && !add) { 4082 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4083 return -ENOENT; 4084 } 4085 4086 if (add) { 4087 filter = rte_zmalloc("txgbe_5tuple_filter", 4088 sizeof(struct txgbe_5tuple_filter), 0); 4089 if (filter == NULL) 4090 return -ENOMEM; 4091 rte_memcpy(&filter->filter_info, 4092 &filter_5tuple, 4093 sizeof(struct txgbe_5tuple_filter_info)); 4094 filter->queue = ntuple_filter->queue; 4095 ret = txgbe_add_5tuple_filter(dev, filter); 4096 if (ret < 0) { 4097 rte_free(filter); 4098 return ret; 4099 } 4100 } else { 4101 txgbe_remove_5tuple_filter(dev, filter); 4102 } 4103 4104 return 0; 4105 } 4106 4107 int 4108 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 4109 struct rte_eth_ethertype_filter *filter, 4110 bool add) 4111 { 4112 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4113 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4114 uint32_t etqf = 0; 4115 uint32_t etqs = 0; 4116 int ret; 4117 struct txgbe_ethertype_filter ethertype_filter; 4118 4119 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 4120 return -EINVAL; 4121 4122 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 4123 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 4124 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 4125 " ethertype filter.", filter->ether_type); 4126 return -EINVAL; 4127 } 4128 4129 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 4130 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 4131 return -EINVAL; 4132 } 4133 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 4134 PMD_DRV_LOG(ERR, "drop option is unsupported."); 4135 return -EINVAL; 4136 } 4137 4138 ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 4139 if (ret >= 0 && add) { 4140 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 4141 filter->ether_type); 4142 return -EEXIST; 4143 } 4144 if (ret < 0 && !add) { 4145 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 4146 filter->ether_type); 4147 return -ENOENT; 4148 } 4149 4150 if (add) { 4151 etqf = TXGBE_ETFLT_ENA; 4152 etqf |= TXGBE_ETFLT_ETID(filter->ether_type); 4153 etqs |= TXGBE_ETCLS_QPID(filter->queue); 4154 etqs |= TXGBE_ETCLS_QENA; 4155 4156 ethertype_filter.ethertype = filter->ether_type; 4157 ethertype_filter.etqf = etqf; 4158 ethertype_filter.etqs = etqs; 4159 ethertype_filter.conf = FALSE; 4160 ret = txgbe_ethertype_filter_insert(filter_info, 4161 ðertype_filter); 4162 if (ret < 0) { 4163 PMD_DRV_LOG(ERR, "ethertype filters are full."); 4164 return -ENOSPC; 4165 } 4166 } else { 4167 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 4168 if (ret < 0) 4169 return -ENOSYS; 4170 } 4171 wr32(hw, TXGBE_ETFLT(ret), etqf); 4172 wr32(hw, TXGBE_ETCLS(ret), etqs); 4173 txgbe_flush(hw); 4174 4175 return 0; 4176 } 4177 4178 static int 4179 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev, 4180 const struct rte_flow_ops **ops) 4181 { 4182 *ops = &txgbe_flow_ops; 4183 return 0; 4184 } 4185 4186 static u8 * 4187 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw, 4188 u8 **mc_addr_ptr, u32 *vmdq) 4189 { 4190 u8 *mc_addr; 4191 4192 *vmdq = 0; 4193 mc_addr = *mc_addr_ptr; 4194 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 4195 return mc_addr; 4196 } 4197 4198 int 4199 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 4200 struct rte_ether_addr *mc_addr_set, 4201 uint32_t nb_mc_addr) 4202 { 4203 struct txgbe_hw *hw; 4204 u8 *mc_addr_list; 4205 4206 hw = TXGBE_DEV_HW(dev); 4207 mc_addr_list = (u8 *)mc_addr_set; 4208 return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 4209 txgbe_dev_addr_list_itr, TRUE); 4210 } 4211 4212 static uint64_t 4213 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 4214 { 4215 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4216 uint64_t systime_cycles; 4217 4218 systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL); 4219 systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32; 4220 4221 return systime_cycles; 4222 } 4223 4224 static uint64_t 4225 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4226 { 4227 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4228 uint64_t rx_tstamp_cycles; 4229 4230 /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */ 4231 rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL); 4232 rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32; 4233 4234 return rx_tstamp_cycles; 4235 } 4236 4237 static uint64_t 4238 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4239 { 4240 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4241 uint64_t tx_tstamp_cycles; 4242 4243 /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */ 4244 tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL); 4245 tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32; 4246 4247 return tx_tstamp_cycles; 4248 } 4249 4250 static void 4251 txgbe_start_timecounters(struct rte_eth_dev *dev) 4252 { 4253 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4254 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4255 struct rte_eth_link link; 4256 uint32_t incval = 0; 4257 uint32_t shift = 0; 4258 4259 /* Get current link speed. */ 4260 txgbe_dev_link_update(dev, 1); 4261 rte_eth_linkstatus_get(dev, &link); 4262 4263 switch (link.link_speed) { 4264 case RTE_ETH_SPEED_NUM_100M: 4265 incval = TXGBE_INCVAL_100; 4266 shift = TXGBE_INCVAL_SHIFT_100; 4267 break; 4268 case RTE_ETH_SPEED_NUM_1G: 4269 incval = TXGBE_INCVAL_1GB; 4270 shift = TXGBE_INCVAL_SHIFT_1GB; 4271 break; 4272 case RTE_ETH_SPEED_NUM_10G: 4273 default: 4274 incval = TXGBE_INCVAL_10GB; 4275 shift = TXGBE_INCVAL_SHIFT_10GB; 4276 break; 4277 } 4278 4279 wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2)); 4280 4281 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 4282 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4283 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4284 4285 adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4286 adapter->systime_tc.cc_shift = shift; 4287 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 4288 4289 adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4290 adapter->rx_tstamp_tc.cc_shift = shift; 4291 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4292 4293 adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4294 adapter->tx_tstamp_tc.cc_shift = shift; 4295 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4296 } 4297 4298 static int 4299 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 4300 { 4301 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4302 4303 adapter->systime_tc.nsec += delta; 4304 adapter->rx_tstamp_tc.nsec += delta; 4305 adapter->tx_tstamp_tc.nsec += delta; 4306 4307 return 0; 4308 } 4309 4310 static int 4311 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 4312 { 4313 uint64_t ns; 4314 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4315 4316 ns = rte_timespec_to_ns(ts); 4317 /* Set the timecounters to a new value. */ 4318 adapter->systime_tc.nsec = ns; 4319 adapter->rx_tstamp_tc.nsec = ns; 4320 adapter->tx_tstamp_tc.nsec = ns; 4321 4322 return 0; 4323 } 4324 4325 static int 4326 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 4327 { 4328 uint64_t ns, systime_cycles; 4329 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4330 4331 systime_cycles = txgbe_read_systime_cyclecounter(dev); 4332 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 4333 *ts = rte_ns_to_timespec(ns); 4334 4335 return 0; 4336 } 4337 4338 static int 4339 txgbe_timesync_enable(struct rte_eth_dev *dev) 4340 { 4341 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4342 uint32_t tsync_ctl; 4343 4344 /* Stop the timesync system time. */ 4345 wr32(hw, TXGBE_TSTIMEINC, 0x0); 4346 /* Reset the timesync system time value. */ 4347 wr32(hw, TXGBE_TSTIMEL, 0x0); 4348 wr32(hw, TXGBE_TSTIMEH, 0x0); 4349 4350 txgbe_start_timecounters(dev); 4351 4352 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4353 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 4354 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588); 4355 4356 /* Enable timestamping of received PTP packets. */ 4357 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4358 tsync_ctl |= TXGBE_TSRXCTL_ENA; 4359 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4360 4361 /* Enable timestamping of transmitted PTP packets. */ 4362 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4363 tsync_ctl |= TXGBE_TSTXCTL_ENA; 4364 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4365 4366 txgbe_flush(hw); 4367 4368 return 0; 4369 } 4370 4371 static int 4372 txgbe_timesync_disable(struct rte_eth_dev *dev) 4373 { 4374 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4375 uint32_t tsync_ctl; 4376 4377 /* Disable timestamping of transmitted PTP packets. */ 4378 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4379 tsync_ctl &= ~TXGBE_TSTXCTL_ENA; 4380 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4381 4382 /* Disable timestamping of received PTP packets. */ 4383 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4384 tsync_ctl &= ~TXGBE_TSRXCTL_ENA; 4385 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4386 4387 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4388 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0); 4389 4390 /* Stop incrementating the System Time registers. */ 4391 wr32(hw, TXGBE_TSTIMEINC, 0); 4392 4393 return 0; 4394 } 4395 4396 static int 4397 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 4398 struct timespec *timestamp, 4399 uint32_t flags __rte_unused) 4400 { 4401 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4402 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4403 uint32_t tsync_rxctl; 4404 uint64_t rx_tstamp_cycles; 4405 uint64_t ns; 4406 4407 tsync_rxctl = rd32(hw, TXGBE_TSRXCTL); 4408 if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0) 4409 return -EINVAL; 4410 4411 rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev); 4412 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 4413 *timestamp = rte_ns_to_timespec(ns); 4414 4415 return 0; 4416 } 4417 4418 static int 4419 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 4420 struct timespec *timestamp) 4421 { 4422 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4423 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4424 uint32_t tsync_txctl; 4425 uint64_t tx_tstamp_cycles; 4426 uint64_t ns; 4427 4428 tsync_txctl = rd32(hw, TXGBE_TSTXCTL); 4429 if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0) 4430 return -EINVAL; 4431 4432 tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev); 4433 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 4434 *timestamp = rte_ns_to_timespec(ns); 4435 4436 return 0; 4437 } 4438 4439 static int 4440 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused) 4441 { 4442 int count = 0; 4443 int g_ind = 0; 4444 const struct reg_info *reg_group; 4445 const struct reg_info **reg_set = txgbe_regs_others; 4446 4447 while ((reg_group = reg_set[g_ind++])) 4448 count += txgbe_regs_group_count(reg_group); 4449 4450 return count; 4451 } 4452 4453 static int 4454 txgbe_get_regs(struct rte_eth_dev *dev, 4455 struct rte_dev_reg_info *regs) 4456 { 4457 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4458 uint32_t *data = regs->data; 4459 int g_ind = 0; 4460 int count = 0; 4461 const struct reg_info *reg_group; 4462 const struct reg_info **reg_set = txgbe_regs_others; 4463 4464 if (data == NULL) { 4465 regs->length = txgbe_get_reg_length(dev); 4466 regs->width = sizeof(uint32_t); 4467 return 0; 4468 } 4469 4470 /* Support only full register dump */ 4471 if (regs->length == 0 || 4472 regs->length == (uint32_t)txgbe_get_reg_length(dev)) { 4473 regs->version = hw->mac.type << 24 | 4474 hw->revision_id << 16 | 4475 hw->device_id; 4476 while ((reg_group = reg_set[g_ind++])) 4477 count += txgbe_read_regs_group(dev, &data[count], 4478 reg_group); 4479 return 0; 4480 } 4481 4482 return -ENOTSUP; 4483 } 4484 4485 static int 4486 txgbe_get_eeprom_length(struct rte_eth_dev *dev) 4487 { 4488 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4489 4490 /* Return unit is byte count */ 4491 return hw->rom.word_size * 2; 4492 } 4493 4494 static int 4495 txgbe_get_eeprom(struct rte_eth_dev *dev, 4496 struct rte_dev_eeprom_info *in_eeprom) 4497 { 4498 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4499 struct txgbe_rom_info *eeprom = &hw->rom; 4500 uint16_t *data = in_eeprom->data; 4501 int first, length; 4502 4503 first = in_eeprom->offset >> 1; 4504 length = in_eeprom->length >> 1; 4505 if (first > hw->rom.word_size || 4506 ((first + length) > hw->rom.word_size)) 4507 return -EINVAL; 4508 4509 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4510 4511 return eeprom->readw_buffer(hw, first, length, data); 4512 } 4513 4514 static int 4515 txgbe_set_eeprom(struct rte_eth_dev *dev, 4516 struct rte_dev_eeprom_info *in_eeprom) 4517 { 4518 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4519 struct txgbe_rom_info *eeprom = &hw->rom; 4520 uint16_t *data = in_eeprom->data; 4521 int first, length; 4522 4523 first = in_eeprom->offset >> 1; 4524 length = in_eeprom->length >> 1; 4525 if (first > hw->rom.word_size || 4526 ((first + length) > hw->rom.word_size)) 4527 return -EINVAL; 4528 4529 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4530 4531 return eeprom->writew_buffer(hw, first, length, data); 4532 } 4533 4534 static int 4535 txgbe_get_module_info(struct rte_eth_dev *dev, 4536 struct rte_eth_dev_module_info *modinfo) 4537 { 4538 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4539 uint32_t status; 4540 uint8_t sff8472_rev, addr_mode; 4541 bool page_swap = false; 4542 4543 /* Check whether we support SFF-8472 or not */ 4544 status = hw->phy.read_i2c_eeprom(hw, 4545 TXGBE_SFF_SFF_8472_COMP, 4546 &sff8472_rev); 4547 if (status != 0) 4548 return -EIO; 4549 4550 /* addressing mode is not supported */ 4551 status = hw->phy.read_i2c_eeprom(hw, 4552 TXGBE_SFF_SFF_8472_SWAP, 4553 &addr_mode); 4554 if (status != 0) 4555 return -EIO; 4556 4557 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) { 4558 PMD_DRV_LOG(ERR, 4559 "Address change required to access page 0xA2, " 4560 "but not supported. Please report the module " 4561 "type to the driver maintainers."); 4562 page_swap = true; 4563 } 4564 4565 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) { 4566 /* We have a SFP, but it does not support SFF-8472 */ 4567 modinfo->type = RTE_ETH_MODULE_SFF_8079; 4568 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 4569 } else { 4570 /* We have a SFP which supports a revision of SFF-8472. */ 4571 modinfo->type = RTE_ETH_MODULE_SFF_8472; 4572 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 4573 } 4574 4575 return 0; 4576 } 4577 4578 static int 4579 txgbe_get_module_eeprom(struct rte_eth_dev *dev, 4580 struct rte_dev_eeprom_info *info) 4581 { 4582 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4583 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID; 4584 uint8_t databyte = 0xFF; 4585 uint8_t *data = info->data; 4586 uint32_t i = 0; 4587 4588 if (info->length == 0) 4589 return -EINVAL; 4590 4591 for (i = info->offset; i < info->offset + info->length; i++) { 4592 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 4593 status = hw->phy.read_i2c_eeprom(hw, i, &databyte); 4594 else 4595 status = hw->phy.read_i2c_sff8472(hw, i, &databyte); 4596 4597 if (status != 0) 4598 return -EIO; 4599 4600 data[i - info->offset] = databyte; 4601 } 4602 4603 return 0; 4604 } 4605 4606 bool 4607 txgbe_rss_update_sp(enum txgbe_mac_type mac_type) 4608 { 4609 switch (mac_type) { 4610 case txgbe_mac_raptor: 4611 case txgbe_mac_raptor_vf: 4612 return 1; 4613 default: 4614 return 0; 4615 } 4616 } 4617 4618 static int 4619 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 4620 struct rte_eth_dcb_info *dcb_info) 4621 { 4622 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 4623 struct txgbe_dcb_tc_config *tc; 4624 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 4625 uint8_t nb_tcs; 4626 uint8_t i, j; 4627 4628 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) 4629 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 4630 else 4631 dcb_info->nb_tcs = 1; 4632 4633 tc_queue = &dcb_info->tc_queue; 4634 nb_tcs = dcb_info->nb_tcs; 4635 4636 if (dcb_config->vt_mode) { /* vt is enabled */ 4637 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 4638 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 4639 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) 4640 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 4641 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 4642 for (j = 0; j < nb_tcs; j++) { 4643 tc_queue->tc_rxq[0][j].base = j; 4644 tc_queue->tc_rxq[0][j].nb_queue = 1; 4645 tc_queue->tc_txq[0][j].base = j; 4646 tc_queue->tc_txq[0][j].nb_queue = 1; 4647 } 4648 } else { 4649 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 4650 for (j = 0; j < nb_tcs; j++) { 4651 tc_queue->tc_rxq[i][j].base = 4652 i * nb_tcs + j; 4653 tc_queue->tc_rxq[i][j].nb_queue = 1; 4654 tc_queue->tc_txq[i][j].base = 4655 i * nb_tcs + j; 4656 tc_queue->tc_txq[i][j].nb_queue = 1; 4657 } 4658 } 4659 } 4660 } else { /* vt is disabled */ 4661 struct rte_eth_dcb_rx_conf *rx_conf = 4662 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 4663 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) 4664 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 4665 if (dcb_info->nb_tcs == RTE_ETH_4_TCS) { 4666 for (i = 0; i < dcb_info->nb_tcs; i++) { 4667 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 4668 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4669 } 4670 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4671 dcb_info->tc_queue.tc_txq[0][1].base = 64; 4672 dcb_info->tc_queue.tc_txq[0][2].base = 96; 4673 dcb_info->tc_queue.tc_txq[0][3].base = 112; 4674 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 4675 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4676 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4677 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4678 } else if (dcb_info->nb_tcs == RTE_ETH_8_TCS) { 4679 for (i = 0; i < dcb_info->nb_tcs; i++) { 4680 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 4681 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4682 } 4683 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4684 dcb_info->tc_queue.tc_txq[0][1].base = 32; 4685 dcb_info->tc_queue.tc_txq[0][2].base = 64; 4686 dcb_info->tc_queue.tc_txq[0][3].base = 80; 4687 dcb_info->tc_queue.tc_txq[0][4].base = 96; 4688 dcb_info->tc_queue.tc_txq[0][5].base = 104; 4689 dcb_info->tc_queue.tc_txq[0][6].base = 112; 4690 dcb_info->tc_queue.tc_txq[0][7].base = 120; 4691 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 4692 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4693 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4694 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4695 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 4696 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 4697 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 4698 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 4699 } 4700 } 4701 for (i = 0; i < dcb_info->nb_tcs; i++) { 4702 tc = &dcb_config->tc_config[i]; 4703 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent; 4704 } 4705 return 0; 4706 } 4707 4708 /* Update e-tag ether type */ 4709 static int 4710 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw, 4711 uint16_t ether_type) 4712 { 4713 uint32_t etag_etype; 4714 4715 etag_etype = rd32(hw, TXGBE_EXTAG); 4716 etag_etype &= ~TXGBE_EXTAG_ETAG_MASK; 4717 etag_etype |= ether_type; 4718 wr32(hw, TXGBE_EXTAG, etag_etype); 4719 txgbe_flush(hw); 4720 4721 return 0; 4722 } 4723 4724 /* Enable e-tag tunnel */ 4725 static int 4726 txgbe_e_tag_enable(struct txgbe_hw *hw) 4727 { 4728 uint32_t etag_etype; 4729 4730 etag_etype = rd32(hw, TXGBE_PORTCTL); 4731 etag_etype |= TXGBE_PORTCTL_ETAG; 4732 wr32(hw, TXGBE_PORTCTL, etag_etype); 4733 txgbe_flush(hw); 4734 4735 return 0; 4736 } 4737 4738 static int 4739 txgbe_e_tag_filter_del(struct rte_eth_dev *dev, 4740 struct txgbe_l2_tunnel_conf *l2_tunnel) 4741 { 4742 int ret = 0; 4743 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4744 uint32_t i, rar_entries; 4745 uint32_t rar_low, rar_high; 4746 4747 rar_entries = hw->mac.num_rar_entries; 4748 4749 for (i = 1; i < rar_entries; i++) { 4750 wr32(hw, TXGBE_ETHADDRIDX, i); 4751 rar_high = rd32(hw, TXGBE_ETHADDRH); 4752 rar_low = rd32(hw, TXGBE_ETHADDRL); 4753 if ((rar_high & TXGBE_ETHADDRH_VLD) && 4754 (rar_high & TXGBE_ETHADDRH_ETAG) && 4755 (TXGBE_ETHADDRL_ETAG(rar_low) == 4756 l2_tunnel->tunnel_id)) { 4757 wr32(hw, TXGBE_ETHADDRL, 0); 4758 wr32(hw, TXGBE_ETHADDRH, 0); 4759 4760 txgbe_clear_vmdq(hw, i, BIT_MASK32); 4761 4762 return ret; 4763 } 4764 } 4765 4766 return ret; 4767 } 4768 4769 static int 4770 txgbe_e_tag_filter_add(struct rte_eth_dev *dev, 4771 struct txgbe_l2_tunnel_conf *l2_tunnel) 4772 { 4773 int ret = 0; 4774 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4775 uint32_t i, rar_entries; 4776 uint32_t rar_low, rar_high; 4777 4778 /* One entry for one tunnel. Try to remove potential existing entry. */ 4779 txgbe_e_tag_filter_del(dev, l2_tunnel); 4780 4781 rar_entries = hw->mac.num_rar_entries; 4782 4783 for (i = 1; i < rar_entries; i++) { 4784 wr32(hw, TXGBE_ETHADDRIDX, i); 4785 rar_high = rd32(hw, TXGBE_ETHADDRH); 4786 if (rar_high & TXGBE_ETHADDRH_VLD) { 4787 continue; 4788 } else { 4789 txgbe_set_vmdq(hw, i, l2_tunnel->pool); 4790 rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG; 4791 rar_low = l2_tunnel->tunnel_id; 4792 4793 wr32(hw, TXGBE_ETHADDRL, rar_low); 4794 wr32(hw, TXGBE_ETHADDRH, rar_high); 4795 4796 return ret; 4797 } 4798 } 4799 4800 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 4801 " Please remove a rule before adding a new one."); 4802 return -EINVAL; 4803 } 4804 4805 static inline struct txgbe_l2_tn_filter * 4806 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info, 4807 struct txgbe_l2_tn_key *key) 4808 { 4809 int ret; 4810 4811 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 4812 if (ret < 0) 4813 return NULL; 4814 4815 return l2_tn_info->hash_map[ret]; 4816 } 4817 4818 static inline int 4819 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4820 struct txgbe_l2_tn_filter *l2_tn_filter) 4821 { 4822 int ret; 4823 4824 ret = rte_hash_add_key(l2_tn_info->hash_handle, 4825 &l2_tn_filter->key); 4826 4827 if (ret < 0) { 4828 PMD_DRV_LOG(ERR, 4829 "Failed to insert L2 tunnel filter" 4830 " to hash table %d!", 4831 ret); 4832 return ret; 4833 } 4834 4835 l2_tn_info->hash_map[ret] = l2_tn_filter; 4836 4837 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4838 4839 return 0; 4840 } 4841 4842 static inline int 4843 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4844 struct txgbe_l2_tn_key *key) 4845 { 4846 int ret; 4847 struct txgbe_l2_tn_filter *l2_tn_filter; 4848 4849 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 4850 4851 if (ret < 0) { 4852 PMD_DRV_LOG(ERR, 4853 "No such L2 tunnel filter to delete %d!", 4854 ret); 4855 return ret; 4856 } 4857 4858 l2_tn_filter = l2_tn_info->hash_map[ret]; 4859 l2_tn_info->hash_map[ret] = NULL; 4860 4861 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4862 rte_free(l2_tn_filter); 4863 4864 return 0; 4865 } 4866 4867 /* Add l2 tunnel filter */ 4868 int 4869 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 4870 struct txgbe_l2_tunnel_conf *l2_tunnel, 4871 bool restore) 4872 { 4873 int ret; 4874 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4875 struct txgbe_l2_tn_key key; 4876 struct txgbe_l2_tn_filter *node; 4877 4878 if (!restore) { 4879 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4880 key.tn_id = l2_tunnel->tunnel_id; 4881 4882 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key); 4883 4884 if (node) { 4885 PMD_DRV_LOG(ERR, 4886 "The L2 tunnel filter already exists!"); 4887 return -EINVAL; 4888 } 4889 4890 node = rte_zmalloc("txgbe_l2_tn", 4891 sizeof(struct txgbe_l2_tn_filter), 4892 0); 4893 if (!node) 4894 return -ENOMEM; 4895 4896 rte_memcpy(&node->key, 4897 &key, 4898 sizeof(struct txgbe_l2_tn_key)); 4899 node->pool = l2_tunnel->pool; 4900 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node); 4901 if (ret < 0) { 4902 rte_free(node); 4903 return ret; 4904 } 4905 } 4906 4907 switch (l2_tunnel->l2_tunnel_type) { 4908 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG: 4909 ret = txgbe_e_tag_filter_add(dev, l2_tunnel); 4910 break; 4911 default: 4912 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4913 ret = -EINVAL; 4914 break; 4915 } 4916 4917 if (!restore && ret < 0) 4918 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4919 4920 return ret; 4921 } 4922 4923 /* Delete l2 tunnel filter */ 4924 int 4925 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 4926 struct txgbe_l2_tunnel_conf *l2_tunnel) 4927 { 4928 int ret; 4929 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4930 struct txgbe_l2_tn_key key; 4931 4932 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4933 key.tn_id = l2_tunnel->tunnel_id; 4934 ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4935 if (ret < 0) 4936 return ret; 4937 4938 switch (l2_tunnel->l2_tunnel_type) { 4939 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG: 4940 ret = txgbe_e_tag_filter_del(dev, l2_tunnel); 4941 break; 4942 default: 4943 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4944 ret = -EINVAL; 4945 break; 4946 } 4947 4948 return ret; 4949 } 4950 4951 static int 4952 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 4953 { 4954 int ret = 0; 4955 uint32_t ctrl; 4956 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4957 4958 ctrl = rd32(hw, TXGBE_POOLCTL); 4959 ctrl &= ~TXGBE_POOLCTL_MODE_MASK; 4960 if (en) 4961 ctrl |= TXGBE_PSRPOOL_MODE_ETAG; 4962 wr32(hw, TXGBE_POOLCTL, ctrl); 4963 4964 return ret; 4965 } 4966 4967 /* Add UDP tunneling port */ 4968 static int 4969 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 4970 struct rte_eth_udp_tunnel *udp_tunnel) 4971 { 4972 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4973 int ret = 0; 4974 4975 if (udp_tunnel == NULL) 4976 return -EINVAL; 4977 4978 switch (udp_tunnel->prot_type) { 4979 case RTE_ETH_TUNNEL_TYPE_VXLAN: 4980 if (udp_tunnel->udp_port == 0) { 4981 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 4982 ret = -EINVAL; 4983 break; 4984 } 4985 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port); 4986 break; 4987 case RTE_ETH_TUNNEL_TYPE_GENEVE: 4988 if (udp_tunnel->udp_port == 0) { 4989 PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed."); 4990 ret = -EINVAL; 4991 break; 4992 } 4993 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port); 4994 break; 4995 case RTE_ETH_TUNNEL_TYPE_TEREDO: 4996 if (udp_tunnel->udp_port == 0) { 4997 PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed."); 4998 ret = -EINVAL; 4999 break; 5000 } 5001 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port); 5002 break; 5003 case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE: 5004 if (udp_tunnel->udp_port == 0) { 5005 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 5006 ret = -EINVAL; 5007 break; 5008 } 5009 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port); 5010 break; 5011 default: 5012 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5013 ret = -EINVAL; 5014 break; 5015 } 5016 5017 txgbe_flush(hw); 5018 5019 return ret; 5020 } 5021 5022 /* Remove UDP tunneling port */ 5023 static int 5024 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 5025 struct rte_eth_udp_tunnel *udp_tunnel) 5026 { 5027 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5028 int ret = 0; 5029 uint16_t cur_port; 5030 5031 if (udp_tunnel == NULL) 5032 return -EINVAL; 5033 5034 switch (udp_tunnel->prot_type) { 5035 case RTE_ETH_TUNNEL_TYPE_VXLAN: 5036 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT); 5037 if (cur_port != udp_tunnel->udp_port) { 5038 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5039 udp_tunnel->udp_port); 5040 ret = -EINVAL; 5041 break; 5042 } 5043 wr32(hw, TXGBE_VXLANPORT, 0); 5044 break; 5045 case RTE_ETH_TUNNEL_TYPE_GENEVE: 5046 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT); 5047 if (cur_port != udp_tunnel->udp_port) { 5048 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5049 udp_tunnel->udp_port); 5050 ret = -EINVAL; 5051 break; 5052 } 5053 wr32(hw, TXGBE_GENEVEPORT, 0); 5054 break; 5055 case RTE_ETH_TUNNEL_TYPE_TEREDO: 5056 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT); 5057 if (cur_port != udp_tunnel->udp_port) { 5058 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5059 udp_tunnel->udp_port); 5060 ret = -EINVAL; 5061 break; 5062 } 5063 wr32(hw, TXGBE_TEREDOPORT, 0); 5064 break; 5065 case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE: 5066 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORTGPE); 5067 if (cur_port != udp_tunnel->udp_port) { 5068 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5069 udp_tunnel->udp_port); 5070 ret = -EINVAL; 5071 break; 5072 } 5073 wr32(hw, TXGBE_VXLANPORTGPE, 0); 5074 break; 5075 default: 5076 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5077 ret = -EINVAL; 5078 break; 5079 } 5080 5081 txgbe_flush(hw); 5082 5083 return ret; 5084 } 5085 5086 /* restore n-tuple filter */ 5087 static inline void 5088 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 5089 { 5090 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5091 struct txgbe_5tuple_filter *node; 5092 5093 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 5094 txgbe_inject_5tuple_filter(dev, node); 5095 } 5096 } 5097 5098 /* restore ethernet type filter */ 5099 static inline void 5100 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 5101 { 5102 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5103 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5104 int i; 5105 5106 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5107 if (filter_info->ethertype_mask & (1 << i)) { 5108 wr32(hw, TXGBE_ETFLT(i), 5109 filter_info->ethertype_filters[i].etqf); 5110 wr32(hw, TXGBE_ETCLS(i), 5111 filter_info->ethertype_filters[i].etqs); 5112 txgbe_flush(hw); 5113 } 5114 } 5115 } 5116 5117 /* restore SYN filter */ 5118 static inline void 5119 txgbe_syn_filter_restore(struct rte_eth_dev *dev) 5120 { 5121 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5122 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5123 uint32_t synqf; 5124 5125 synqf = filter_info->syn_info; 5126 5127 if (synqf & TXGBE_SYNCLS_ENA) { 5128 wr32(hw, TXGBE_SYNCLS, synqf); 5129 txgbe_flush(hw); 5130 } 5131 } 5132 5133 /* restore L2 tunnel filter */ 5134 static inline void 5135 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 5136 { 5137 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5138 struct txgbe_l2_tn_filter *node; 5139 struct txgbe_l2_tunnel_conf l2_tn_conf; 5140 5141 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 5142 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 5143 l2_tn_conf.tunnel_id = node->key.tn_id; 5144 l2_tn_conf.pool = node->pool; 5145 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 5146 } 5147 } 5148 5149 /* restore rss filter */ 5150 static inline void 5151 txgbe_rss_filter_restore(struct rte_eth_dev *dev) 5152 { 5153 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5154 5155 if (filter_info->rss_info.conf.queue_num) 5156 txgbe_config_rss_filter(dev, 5157 &filter_info->rss_info, TRUE); 5158 } 5159 5160 static int 5161 txgbe_filter_restore(struct rte_eth_dev *dev) 5162 { 5163 txgbe_ntuple_filter_restore(dev); 5164 txgbe_ethertype_filter_restore(dev); 5165 txgbe_syn_filter_restore(dev); 5166 txgbe_fdir_filter_restore(dev); 5167 txgbe_l2_tn_filter_restore(dev); 5168 txgbe_rss_filter_restore(dev); 5169 5170 return 0; 5171 } 5172 5173 static void 5174 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 5175 { 5176 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5177 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5178 5179 if (l2_tn_info->e_tag_en) 5180 (void)txgbe_e_tag_enable(hw); 5181 5182 if (l2_tn_info->e_tag_fwd_en) 5183 (void)txgbe_e_tag_forwarding_en_dis(dev, 1); 5184 5185 (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 5186 } 5187 5188 /* remove all the n-tuple filters */ 5189 void 5190 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 5191 { 5192 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5193 struct txgbe_5tuple_filter *p_5tuple; 5194 5195 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 5196 txgbe_remove_5tuple_filter(dev, p_5tuple); 5197 } 5198 5199 /* remove all the ether type filters */ 5200 void 5201 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 5202 { 5203 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5204 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5205 int i; 5206 5207 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5208 if (filter_info->ethertype_mask & (1 << i) && 5209 !filter_info->ethertype_filters[i].conf) { 5210 (void)txgbe_ethertype_filter_remove(filter_info, 5211 (uint8_t)i); 5212 wr32(hw, TXGBE_ETFLT(i), 0); 5213 wr32(hw, TXGBE_ETCLS(i), 0); 5214 txgbe_flush(hw); 5215 } 5216 } 5217 } 5218 5219 /* remove the SYN filter */ 5220 void 5221 txgbe_clear_syn_filter(struct rte_eth_dev *dev) 5222 { 5223 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5224 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5225 5226 if (filter_info->syn_info & TXGBE_SYNCLS_ENA) { 5227 filter_info->syn_info = 0; 5228 5229 wr32(hw, TXGBE_SYNCLS, 0); 5230 txgbe_flush(hw); 5231 } 5232 } 5233 5234 /* remove all the L2 tunnel filters */ 5235 int 5236 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 5237 { 5238 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5239 struct txgbe_l2_tn_filter *l2_tn_filter; 5240 struct txgbe_l2_tunnel_conf l2_tn_conf; 5241 int ret = 0; 5242 5243 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 5244 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 5245 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 5246 l2_tn_conf.pool = l2_tn_filter->pool; 5247 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 5248 if (ret < 0) 5249 return ret; 5250 } 5251 5252 return 0; 5253 } 5254 5255 static const struct eth_dev_ops txgbe_eth_dev_ops = { 5256 .dev_configure = txgbe_dev_configure, 5257 .dev_infos_get = txgbe_dev_info_get, 5258 .dev_start = txgbe_dev_start, 5259 .dev_stop = txgbe_dev_stop, 5260 .dev_set_link_up = txgbe_dev_set_link_up, 5261 .dev_set_link_down = txgbe_dev_set_link_down, 5262 .dev_close = txgbe_dev_close, 5263 .dev_reset = txgbe_dev_reset, 5264 .promiscuous_enable = txgbe_dev_promiscuous_enable, 5265 .promiscuous_disable = txgbe_dev_promiscuous_disable, 5266 .allmulticast_enable = txgbe_dev_allmulticast_enable, 5267 .allmulticast_disable = txgbe_dev_allmulticast_disable, 5268 .link_update = txgbe_dev_link_update, 5269 .stats_get = txgbe_dev_stats_get, 5270 .xstats_get = txgbe_dev_xstats_get, 5271 .xstats_get_by_id = txgbe_dev_xstats_get_by_id, 5272 .stats_reset = txgbe_dev_stats_reset, 5273 .xstats_reset = txgbe_dev_xstats_reset, 5274 .xstats_get_names = txgbe_dev_xstats_get_names, 5275 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id, 5276 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set, 5277 .fw_version_get = txgbe_fw_version_get, 5278 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get, 5279 .mtu_set = txgbe_dev_mtu_set, 5280 .vlan_filter_set = txgbe_vlan_filter_set, 5281 .vlan_tpid_set = txgbe_vlan_tpid_set, 5282 .vlan_offload_set = txgbe_vlan_offload_set, 5283 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set, 5284 .rx_queue_start = txgbe_dev_rx_queue_start, 5285 .rx_queue_stop = txgbe_dev_rx_queue_stop, 5286 .tx_queue_start = txgbe_dev_tx_queue_start, 5287 .tx_queue_stop = txgbe_dev_tx_queue_stop, 5288 .rx_queue_setup = txgbe_dev_rx_queue_setup, 5289 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable, 5290 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable, 5291 .rx_queue_release = txgbe_dev_rx_queue_release, 5292 .tx_queue_setup = txgbe_dev_tx_queue_setup, 5293 .tx_queue_release = txgbe_dev_tx_queue_release, 5294 .dev_led_on = txgbe_dev_led_on, 5295 .dev_led_off = txgbe_dev_led_off, 5296 .flow_ctrl_get = txgbe_flow_ctrl_get, 5297 .flow_ctrl_set = txgbe_flow_ctrl_set, 5298 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set, 5299 .mac_addr_add = txgbe_add_rar, 5300 .mac_addr_remove = txgbe_remove_rar, 5301 .mac_addr_set = txgbe_set_default_mac_addr, 5302 .uc_hash_table_set = txgbe_uc_hash_table_set, 5303 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set, 5304 .set_queue_rate_limit = txgbe_set_queue_rate_limit, 5305 .reta_update = txgbe_dev_rss_reta_update, 5306 .reta_query = txgbe_dev_rss_reta_query, 5307 .rss_hash_update = txgbe_dev_rss_hash_update, 5308 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get, 5309 .flow_ops_get = txgbe_dev_flow_ops_get, 5310 .set_mc_addr_list = txgbe_dev_set_mc_addr_list, 5311 .rxq_info_get = txgbe_rxq_info_get, 5312 .txq_info_get = txgbe_txq_info_get, 5313 .timesync_enable = txgbe_timesync_enable, 5314 .timesync_disable = txgbe_timesync_disable, 5315 .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp, 5316 .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp, 5317 .get_reg = txgbe_get_regs, 5318 .get_eeprom_length = txgbe_get_eeprom_length, 5319 .get_eeprom = txgbe_get_eeprom, 5320 .set_eeprom = txgbe_set_eeprom, 5321 .get_module_info = txgbe_get_module_info, 5322 .get_module_eeprom = txgbe_get_module_eeprom, 5323 .get_dcb_info = txgbe_dev_get_dcb_info, 5324 .timesync_adjust_time = txgbe_timesync_adjust_time, 5325 .timesync_read_time = txgbe_timesync_read_time, 5326 .timesync_write_time = txgbe_timesync_write_time, 5327 .udp_tunnel_port_add = txgbe_dev_udp_tunnel_port_add, 5328 .udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del, 5329 .tm_ops_get = txgbe_tm_ops_get, 5330 .tx_done_cleanup = txgbe_dev_tx_done_cleanup, 5331 }; 5332 5333 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd); 5334 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map); 5335 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 5336 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe, 5337 TXGBE_DEVARG_BP_AUTO "=<0|1>" 5338 TXGBE_DEVARG_KR_POLL "=<0|1>" 5339 TXGBE_DEVARG_KR_PRESENT "=<0|1>" 5340 TXGBE_DEVARG_KX_SGMII "=<0|1>" 5341 TXGBE_DEVARG_FFE_SET "=<0-4>" 5342 TXGBE_DEVARG_FFE_MAIN "=<uint16>" 5343 TXGBE_DEVARG_FFE_PRE "=<uint16>" 5344 TXGBE_DEVARG_FFE_POST "=<uint16>"); 5345 5346 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE); 5347 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE); 5348 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_bp, bp, NOTICE); 5349 5350 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX 5351 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_rx, rx, DEBUG); 5352 #endif 5353 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX 5354 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx, tx, DEBUG); 5355 #endif 5356 5357 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE 5358 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx_free, tx_free, DEBUG); 5359 #endif 5360