1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <rte_common.h> 10 #include <ethdev_pci.h> 11 12 #include <rte_interrupts.h> 13 #include <rte_log.h> 14 #include <rte_debug.h> 15 #include <rte_pci.h> 16 #include <rte_memory.h> 17 #include <rte_eal.h> 18 #include <rte_alarm.h> 19 #include <rte_kvargs.h> 20 21 #include "txgbe_logs.h" 22 #include "base/txgbe.h" 23 #include "txgbe_ethdev.h" 24 #include "txgbe_rxtx.h" 25 #include "txgbe_regs_group.h" 26 27 static const struct reg_info txgbe_regs_general[] = { 28 {TXGBE_RST, 1, 1, "TXGBE_RST"}, 29 {TXGBE_STAT, 1, 1, "TXGBE_STAT"}, 30 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"}, 31 {TXGBE_SDP, 1, 1, "TXGBE_SDP"}, 32 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"}, 33 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"}, 34 {0, 0, 0, ""} 35 }; 36 37 static const struct reg_info txgbe_regs_nvm[] = { 38 {0, 0, 0, ""} 39 }; 40 41 static const struct reg_info txgbe_regs_interrupt[] = { 42 {0, 0, 0, ""} 43 }; 44 45 static const struct reg_info txgbe_regs_fctl_others[] = { 46 {0, 0, 0, ""} 47 }; 48 49 static const struct reg_info txgbe_regs_rxdma[] = { 50 {0, 0, 0, ""} 51 }; 52 53 static const struct reg_info txgbe_regs_rx[] = { 54 {0, 0, 0, ""} 55 }; 56 57 static struct reg_info txgbe_regs_tx[] = { 58 {0, 0, 0, ""} 59 }; 60 61 static const struct reg_info txgbe_regs_wakeup[] = { 62 {0, 0, 0, ""} 63 }; 64 65 static const struct reg_info txgbe_regs_dcb[] = { 66 {0, 0, 0, ""} 67 }; 68 69 static const struct reg_info txgbe_regs_mac[] = { 70 {0, 0, 0, ""} 71 }; 72 73 static const struct reg_info txgbe_regs_diagnostic[] = { 74 {0, 0, 0, ""}, 75 }; 76 77 /* PF registers */ 78 static const struct reg_info *txgbe_regs_others[] = { 79 txgbe_regs_general, 80 txgbe_regs_nvm, 81 txgbe_regs_interrupt, 82 txgbe_regs_fctl_others, 83 txgbe_regs_rxdma, 84 txgbe_regs_rx, 85 txgbe_regs_tx, 86 txgbe_regs_wakeup, 87 txgbe_regs_dcb, 88 txgbe_regs_mac, 89 txgbe_regs_diagnostic, 90 NULL}; 91 92 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 93 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 94 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 95 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 96 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev); 97 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev); 98 static int txgbe_dev_close(struct rte_eth_dev *dev); 99 static int txgbe_dev_link_update(struct rte_eth_dev *dev, 100 int wait_to_complete); 101 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev); 102 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 103 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, 104 uint16_t queue); 105 106 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev); 107 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 108 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 109 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev); 110 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 111 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 112 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 113 struct rte_intr_handle *handle); 114 static void txgbe_dev_interrupt_handler(void *param); 115 static void txgbe_dev_interrupt_delayed_handler(void *param); 116 static void txgbe_configure_msix(struct rte_eth_dev *dev); 117 118 static int txgbe_filter_restore(struct rte_eth_dev *dev); 119 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 120 121 #define TXGBE_SET_HWSTRIP(h, q) do {\ 122 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 123 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 124 (h)->bitmap[idx] |= 1 << bit;\ 125 } while (0) 126 127 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\ 128 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 129 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 130 (h)->bitmap[idx] &= ~(1 << bit);\ 131 } while (0) 132 133 #define TXGBE_GET_HWSTRIP(h, q, r) do {\ 134 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 135 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 136 (r) = (h)->bitmap[idx] >> bit & 1;\ 137 } while (0) 138 139 /* 140 * The set of PCI devices this driver supports 141 */ 142 static const struct rte_pci_id pci_id_txgbe_map[] = { 143 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) }, 144 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) }, 145 { .vendor_id = 0, /* sentinel */ }, 146 }; 147 148 static const struct rte_eth_desc_lim rx_desc_lim = { 149 .nb_max = TXGBE_RING_DESC_MAX, 150 .nb_min = TXGBE_RING_DESC_MIN, 151 .nb_align = TXGBE_RXD_ALIGN, 152 }; 153 154 static const struct rte_eth_desc_lim tx_desc_lim = { 155 .nb_max = TXGBE_RING_DESC_MAX, 156 .nb_min = TXGBE_RING_DESC_MIN, 157 .nb_align = TXGBE_TXD_ALIGN, 158 .nb_seg_max = TXGBE_TX_MAX_SEG, 159 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG, 160 }; 161 162 static const struct eth_dev_ops txgbe_eth_dev_ops; 163 164 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)} 165 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)} 166 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = { 167 /* MNG RxTx */ 168 HW_XSTAT(mng_bmc2host_packets), 169 HW_XSTAT(mng_host2bmc_packets), 170 /* Basic RxTx */ 171 HW_XSTAT(rx_packets), 172 HW_XSTAT(tx_packets), 173 HW_XSTAT(rx_bytes), 174 HW_XSTAT(tx_bytes), 175 HW_XSTAT(rx_total_bytes), 176 HW_XSTAT(rx_total_packets), 177 HW_XSTAT(tx_total_packets), 178 HW_XSTAT(rx_total_missed_packets), 179 HW_XSTAT(rx_broadcast_packets), 180 HW_XSTAT(rx_multicast_packets), 181 HW_XSTAT(rx_management_packets), 182 HW_XSTAT(tx_management_packets), 183 HW_XSTAT(rx_management_dropped), 184 185 /* Basic Error */ 186 HW_XSTAT(rx_crc_errors), 187 HW_XSTAT(rx_illegal_byte_errors), 188 HW_XSTAT(rx_error_bytes), 189 HW_XSTAT(rx_mac_short_packet_dropped), 190 HW_XSTAT(rx_length_errors), 191 HW_XSTAT(rx_undersize_errors), 192 HW_XSTAT(rx_fragment_errors), 193 HW_XSTAT(rx_oversize_errors), 194 HW_XSTAT(rx_jabber_errors), 195 HW_XSTAT(rx_l3_l4_xsum_error), 196 HW_XSTAT(mac_local_errors), 197 HW_XSTAT(mac_remote_errors), 198 199 /* Flow Director */ 200 HW_XSTAT(flow_director_added_filters), 201 HW_XSTAT(flow_director_removed_filters), 202 HW_XSTAT(flow_director_filter_add_errors), 203 HW_XSTAT(flow_director_filter_remove_errors), 204 HW_XSTAT(flow_director_matched_filters), 205 HW_XSTAT(flow_director_missed_filters), 206 207 /* FCoE */ 208 HW_XSTAT(rx_fcoe_crc_errors), 209 HW_XSTAT(rx_fcoe_mbuf_allocation_errors), 210 HW_XSTAT(rx_fcoe_dropped), 211 HW_XSTAT(rx_fcoe_packets), 212 HW_XSTAT(tx_fcoe_packets), 213 HW_XSTAT(rx_fcoe_bytes), 214 HW_XSTAT(tx_fcoe_bytes), 215 HW_XSTAT(rx_fcoe_no_ddp), 216 HW_XSTAT(rx_fcoe_no_ddp_ext_buff), 217 218 /* MACSEC */ 219 HW_XSTAT(tx_macsec_pkts_untagged), 220 HW_XSTAT(tx_macsec_pkts_encrypted), 221 HW_XSTAT(tx_macsec_pkts_protected), 222 HW_XSTAT(tx_macsec_octets_encrypted), 223 HW_XSTAT(tx_macsec_octets_protected), 224 HW_XSTAT(rx_macsec_pkts_untagged), 225 HW_XSTAT(rx_macsec_pkts_badtag), 226 HW_XSTAT(rx_macsec_pkts_nosci), 227 HW_XSTAT(rx_macsec_pkts_unknownsci), 228 HW_XSTAT(rx_macsec_octets_decrypted), 229 HW_XSTAT(rx_macsec_octets_validated), 230 HW_XSTAT(rx_macsec_sc_pkts_unchecked), 231 HW_XSTAT(rx_macsec_sc_pkts_delayed), 232 HW_XSTAT(rx_macsec_sc_pkts_late), 233 HW_XSTAT(rx_macsec_sa_pkts_ok), 234 HW_XSTAT(rx_macsec_sa_pkts_invalid), 235 HW_XSTAT(rx_macsec_sa_pkts_notvalid), 236 HW_XSTAT(rx_macsec_sa_pkts_unusedsa), 237 HW_XSTAT(rx_macsec_sa_pkts_notusingsa), 238 239 /* MAC RxTx */ 240 HW_XSTAT(rx_size_64_packets), 241 HW_XSTAT(rx_size_65_to_127_packets), 242 HW_XSTAT(rx_size_128_to_255_packets), 243 HW_XSTAT(rx_size_256_to_511_packets), 244 HW_XSTAT(rx_size_512_to_1023_packets), 245 HW_XSTAT(rx_size_1024_to_max_packets), 246 HW_XSTAT(tx_size_64_packets), 247 HW_XSTAT(tx_size_65_to_127_packets), 248 HW_XSTAT(tx_size_128_to_255_packets), 249 HW_XSTAT(tx_size_256_to_511_packets), 250 HW_XSTAT(tx_size_512_to_1023_packets), 251 HW_XSTAT(tx_size_1024_to_max_packets), 252 253 /* Flow Control */ 254 HW_XSTAT(tx_xon_packets), 255 HW_XSTAT(rx_xon_packets), 256 HW_XSTAT(tx_xoff_packets), 257 HW_XSTAT(rx_xoff_packets), 258 259 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"), 260 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"), 261 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"), 262 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"), 263 }; 264 265 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \ 266 sizeof(rte_txgbe_stats_strings[0])) 267 268 /* Per-priority statistics */ 269 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)} 270 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = { 271 UP_XSTAT(rx_up_packets), 272 UP_XSTAT(tx_up_packets), 273 UP_XSTAT(rx_up_bytes), 274 UP_XSTAT(tx_up_bytes), 275 UP_XSTAT(rx_up_drop_packets), 276 277 UP_XSTAT(tx_up_xon_packets), 278 UP_XSTAT(rx_up_xon_packets), 279 UP_XSTAT(tx_up_xoff_packets), 280 UP_XSTAT(rx_up_xoff_packets), 281 UP_XSTAT(rx_up_dropped), 282 UP_XSTAT(rx_up_mbuf_alloc_errors), 283 UP_XSTAT(tx_up_xon2off_packets), 284 }; 285 286 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \ 287 sizeof(rte_txgbe_up_strings[0])) 288 289 /* Per-queue statistics */ 290 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)} 291 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = { 292 QP_XSTAT(rx_qp_packets), 293 QP_XSTAT(tx_qp_packets), 294 QP_XSTAT(rx_qp_bytes), 295 QP_XSTAT(tx_qp_bytes), 296 QP_XSTAT(rx_qp_mc_packets), 297 }; 298 299 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \ 300 sizeof(rte_txgbe_qp_strings[0])) 301 302 static inline int 303 txgbe_is_sfp(struct txgbe_hw *hw) 304 { 305 switch (hw->phy.type) { 306 case txgbe_phy_sfp_avago: 307 case txgbe_phy_sfp_ftl: 308 case txgbe_phy_sfp_intel: 309 case txgbe_phy_sfp_unknown: 310 case txgbe_phy_sfp_tyco_passive: 311 case txgbe_phy_sfp_unknown_passive: 312 return 1; 313 default: 314 return 0; 315 } 316 } 317 318 static inline int32_t 319 txgbe_pf_reset_hw(struct txgbe_hw *hw) 320 { 321 uint32_t ctrl_ext; 322 int32_t status; 323 324 status = hw->mac.reset_hw(hw); 325 326 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 327 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 328 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 329 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 330 txgbe_flush(hw); 331 332 if (status == TXGBE_ERR_SFP_NOT_PRESENT) 333 status = 0; 334 return status; 335 } 336 337 static inline void 338 txgbe_enable_intr(struct rte_eth_dev *dev) 339 { 340 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 341 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 342 343 wr32(hw, TXGBE_IENMISC, intr->mask_misc); 344 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK); 345 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK); 346 txgbe_flush(hw); 347 } 348 349 static void 350 txgbe_disable_intr(struct txgbe_hw *hw) 351 { 352 PMD_INIT_FUNC_TRACE(); 353 354 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32); 355 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK); 356 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK); 357 txgbe_flush(hw); 358 } 359 360 static int 361 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 362 uint16_t queue_id, 363 uint8_t stat_idx, 364 uint8_t is_rx) 365 { 366 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 367 struct txgbe_stat_mappings *stat_mappings = 368 TXGBE_DEV_STAT_MAPPINGS(eth_dev); 369 uint32_t qsmr_mask = 0; 370 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 371 uint32_t q_map; 372 uint8_t n, offset; 373 374 if (hw->mac.type != txgbe_mac_raptor) 375 return -ENOSYS; 376 377 if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK) 378 return -EIO; 379 380 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 381 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 382 queue_id, stat_idx); 383 384 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 385 if (n >= TXGBE_NB_STAT_MAPPING) { 386 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 387 return -EIO; 388 } 389 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 390 391 /* Now clear any previous stat_idx set */ 392 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 393 if (!is_rx) 394 stat_mappings->tqsm[n] &= ~clearing_mask; 395 else 396 stat_mappings->rqsm[n] &= ~clearing_mask; 397 398 q_map = (uint32_t)stat_idx; 399 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 400 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 401 if (!is_rx) 402 stat_mappings->tqsm[n] |= qsmr_mask; 403 else 404 stat_mappings->rqsm[n] |= qsmr_mask; 405 406 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 407 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 408 queue_id, stat_idx); 409 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 410 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]); 411 return 0; 412 } 413 414 static void 415 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config) 416 { 417 int i; 418 u8 bwgp; 419 struct txgbe_dcb_tc_config *tc; 420 421 UNREFERENCED_PARAMETER(hw); 422 423 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX; 424 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX; 425 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX); 426 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 427 tc = &dcb_config->tc_config[i]; 428 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i; 429 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1); 430 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i; 431 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1); 432 tc->pfc = txgbe_dcb_pfc_disabled; 433 } 434 435 /* Initialize default user to priority mapping, UPx->TC0 */ 436 tc = &dcb_config->tc_config[0]; 437 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 438 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 439 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) { 440 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100; 441 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100; 442 } 443 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal; 444 dcb_config->pfc_mode_enable = false; 445 dcb_config->vt_mode = true; 446 dcb_config->round_robin_enable = false; 447 /* support all DCB capabilities */ 448 dcb_config->support.capabilities = 0xFF; 449 } 450 451 /* 452 * Ensure that all locks are released before first NVM or PHY access 453 */ 454 static void 455 txgbe_swfw_lock_reset(struct txgbe_hw *hw) 456 { 457 uint16_t mask; 458 459 /* 460 * These ones are more tricky since they are common to all ports; but 461 * swfw_sync retries last long enough (1s) to be almost sure that if 462 * lock can not be taken it is due to an improper lock of the 463 * semaphore. 464 */ 465 mask = TXGBE_MNGSEM_SWPHY | 466 TXGBE_MNGSEM_SWMBX | 467 TXGBE_MNGSEM_SWFLASH; 468 if (hw->mac.acquire_swfw_sync(hw, mask) < 0) 469 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 470 471 hw->mac.release_swfw_sync(hw, mask); 472 } 473 474 static int 475 txgbe_handle_devarg(__rte_unused const char *key, const char *value, 476 void *extra_args) 477 { 478 uint16_t *n = extra_args; 479 480 if (value == NULL || extra_args == NULL) 481 return -EINVAL; 482 483 *n = (uint16_t)strtoul(value, NULL, 10); 484 if (*n == USHRT_MAX && errno == ERANGE) 485 return -1; 486 487 return 0; 488 } 489 490 static void 491 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) 492 { 493 struct rte_kvargs *kvlist; 494 u16 auto_neg = 1; 495 u16 poll = 0; 496 u16 present = 1; 497 u16 sgmii = 0; 498 u16 ffe_set = 0; 499 u16 ffe_main = 27; 500 u16 ffe_pre = 8; 501 u16 ffe_post = 44; 502 503 if (devargs == NULL) 504 goto null; 505 506 kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments); 507 if (kvlist == NULL) 508 goto null; 509 510 rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO, 511 &txgbe_handle_devarg, &auto_neg); 512 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL, 513 &txgbe_handle_devarg, &poll); 514 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT, 515 &txgbe_handle_devarg, &present); 516 rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII, 517 &txgbe_handle_devarg, &sgmii); 518 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET, 519 &txgbe_handle_devarg, &ffe_set); 520 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN, 521 &txgbe_handle_devarg, &ffe_main); 522 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE, 523 &txgbe_handle_devarg, &ffe_pre); 524 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST, 525 &txgbe_handle_devarg, &ffe_post); 526 rte_kvargs_free(kvlist); 527 528 null: 529 hw->devarg.auto_neg = auto_neg; 530 hw->devarg.poll = poll; 531 hw->devarg.present = present; 532 hw->devarg.sgmii = sgmii; 533 hw->phy.ffe_set = ffe_set; 534 hw->phy.ffe_main = ffe_main; 535 hw->phy.ffe_pre = ffe_pre; 536 hw->phy.ffe_post = ffe_post; 537 } 538 539 static int 540 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 541 { 542 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 543 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 544 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev); 545 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev); 546 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev); 547 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 548 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev); 549 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 550 const struct rte_memzone *mz; 551 uint32_t ctrl_ext; 552 uint16_t csum; 553 int err, i, ret; 554 555 PMD_INIT_FUNC_TRACE(); 556 557 eth_dev->dev_ops = &txgbe_eth_dev_ops; 558 eth_dev->rx_queue_count = txgbe_dev_rx_queue_count; 559 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status; 560 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status; 561 eth_dev->rx_pkt_burst = &txgbe_recv_pkts; 562 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts; 563 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts; 564 565 /* 566 * For secondary processes, we don't initialise any further as primary 567 * has already done this work. Only check we don't need a different 568 * RX and TX function. 569 */ 570 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 571 struct txgbe_tx_queue *txq; 572 /* TX queue function in primary, set by last queue initialized 573 * Tx queue may not initialized by primary process 574 */ 575 if (eth_dev->data->tx_queues) { 576 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues; 577 txq = eth_dev->data->tx_queues[nb_tx_queues - 1]; 578 txgbe_set_tx_function(eth_dev, txq); 579 } else { 580 /* Use default TX function if we get here */ 581 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 582 "Using default TX function."); 583 } 584 585 txgbe_set_rx_function(eth_dev); 586 587 return 0; 588 } 589 590 rte_eth_copy_pci_info(eth_dev, pci_dev); 591 592 /* Vendor and Device ID need to be set before init of shared code */ 593 hw->device_id = pci_dev->id.device_id; 594 hw->vendor_id = pci_dev->id.vendor_id; 595 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 596 hw->allow_unsupported_sfp = 1; 597 598 /* Reserve memory for interrupt status block */ 599 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1, 600 16, TXGBE_ALIGN, SOCKET_ID_ANY); 601 if (mz == NULL) 602 return -ENOMEM; 603 604 hw->isb_dma = TMZ_PADDR(mz); 605 hw->isb_mem = TMZ_VADDR(mz); 606 607 txgbe_parse_devargs(hw, pci_dev->device.devargs); 608 /* Initialize the shared code (base driver) */ 609 err = txgbe_init_shared_code(hw); 610 if (err != 0) { 611 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err); 612 return -EIO; 613 } 614 615 /* Unlock any pending hardware semaphore */ 616 txgbe_swfw_lock_reset(hw); 617 618 #ifdef RTE_LIB_SECURITY 619 /* Initialize security_ctx only for primary process*/ 620 if (txgbe_ipsec_ctx_create(eth_dev)) 621 return -ENOMEM; 622 #endif 623 624 /* Initialize DCB configuration*/ 625 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config)); 626 txgbe_dcb_init(hw, dcb_config); 627 628 /* Get Hardware Flow Control setting */ 629 hw->fc.requested_mode = txgbe_fc_full; 630 hw->fc.current_mode = txgbe_fc_full; 631 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME; 632 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 633 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH; 634 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH; 635 } 636 hw->fc.send_xon = 1; 637 638 err = hw->rom.init_params(hw); 639 if (err != 0) { 640 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err); 641 return -EIO; 642 } 643 644 /* Make sure we have a good EEPROM before we read from it */ 645 err = hw->rom.validate_checksum(hw, &csum); 646 if (err != 0) { 647 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err); 648 return -EIO; 649 } 650 651 err = hw->mac.init_hw(hw); 652 653 /* 654 * Devices with copper phys will fail to initialise if txgbe_init_hw() 655 * is called too soon after the kernel driver unbinding/binding occurs. 656 * The failure occurs in txgbe_identify_phy() for all devices, 657 * but for non-copper devies, txgbe_identify_sfp_module() is 658 * also called. See txgbe_identify_phy(). The reason for the 659 * failure is not known, and only occuts when virtualisation features 660 * are disabled in the bios. A delay of 200ms was found to be enough by 661 * trial-and-error, and is doubled to be safe. 662 */ 663 if (err && hw->phy.media_type == txgbe_media_type_copper) { 664 rte_delay_ms(200); 665 err = hw->mac.init_hw(hw); 666 } 667 668 if (err == TXGBE_ERR_SFP_NOT_PRESENT) 669 err = 0; 670 671 if (err == TXGBE_ERR_EEPROM_VERSION) { 672 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 673 "LOM. Please be aware there may be issues associated " 674 "with your hardware."); 675 PMD_INIT_LOG(ERR, "If you are experiencing problems " 676 "please contact your hardware representative " 677 "who provided you with this hardware."); 678 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) { 679 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 680 } 681 if (err) { 682 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err); 683 return -EIO; 684 } 685 686 /* Reset the hw statistics */ 687 txgbe_dev_stats_reset(eth_dev); 688 689 /* disable interrupt */ 690 txgbe_disable_intr(hw); 691 692 /* Allocate memory for storing MAC addresses */ 693 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN * 694 hw->mac.num_rar_entries, 0); 695 if (eth_dev->data->mac_addrs == NULL) { 696 PMD_INIT_LOG(ERR, 697 "Failed to allocate %u bytes needed to store " 698 "MAC addresses", 699 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 700 return -ENOMEM; 701 } 702 703 /* Copy the permanent MAC address */ 704 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 705 ð_dev->data->mac_addrs[0]); 706 707 /* Allocate memory for storing hash filter MAC addresses */ 708 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe", 709 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0); 710 if (eth_dev->data->hash_mac_addrs == NULL) { 711 PMD_INIT_LOG(ERR, 712 "Failed to allocate %d bytes needed to store MAC addresses", 713 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC); 714 return -ENOMEM; 715 } 716 717 /* initialize the vfta */ 718 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 719 720 /* initialize the hw strip bitmap*/ 721 memset(hwstrip, 0, sizeof(*hwstrip)); 722 723 /* initialize PF if max_vfs not zero */ 724 ret = txgbe_pf_host_init(eth_dev); 725 if (ret) { 726 rte_free(eth_dev->data->mac_addrs); 727 eth_dev->data->mac_addrs = NULL; 728 rte_free(eth_dev->data->hash_mac_addrs); 729 eth_dev->data->hash_mac_addrs = NULL; 730 return ret; 731 } 732 733 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 734 /* let hardware know driver is loaded */ 735 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD; 736 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 737 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 738 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 739 txgbe_flush(hw); 740 741 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present) 742 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 743 (int)hw->mac.type, (int)hw->phy.type, 744 (int)hw->phy.sfp_type); 745 else 746 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 747 (int)hw->mac.type, (int)hw->phy.type); 748 749 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 750 eth_dev->data->port_id, pci_dev->id.vendor_id, 751 pci_dev->id.device_id); 752 753 rte_intr_callback_register(intr_handle, 754 txgbe_dev_interrupt_handler, eth_dev); 755 756 /* enable uio/vfio intr/eventfd mapping */ 757 rte_intr_enable(intr_handle); 758 759 /* enable support intr */ 760 txgbe_enable_intr(eth_dev); 761 762 /* initialize filter info */ 763 memset(filter_info, 0, 764 sizeof(struct txgbe_filter_info)); 765 766 /* initialize 5tuple filter list */ 767 TAILQ_INIT(&filter_info->fivetuple_list); 768 769 /* initialize flow director filter list & hash */ 770 txgbe_fdir_filter_init(eth_dev); 771 772 /* initialize l2 tunnel filter list & hash */ 773 txgbe_l2_tn_filter_init(eth_dev); 774 775 /* initialize flow filter lists */ 776 txgbe_filterlist_init(); 777 778 /* initialize bandwidth configuration info */ 779 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf)); 780 781 /* initialize Traffic Manager configuration */ 782 txgbe_tm_conf_init(eth_dev); 783 784 return 0; 785 } 786 787 static int 788 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev) 789 { 790 PMD_INIT_FUNC_TRACE(); 791 792 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 793 return 0; 794 795 txgbe_dev_close(eth_dev); 796 797 return 0; 798 } 799 800 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 801 { 802 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 803 struct txgbe_5tuple_filter *p_5tuple; 804 805 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 806 TAILQ_REMOVE(&filter_info->fivetuple_list, 807 p_5tuple, 808 entries); 809 rte_free(p_5tuple); 810 } 811 memset(filter_info->fivetuple_mask, 0, 812 sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE); 813 814 return 0; 815 } 816 817 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 818 { 819 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 820 struct txgbe_fdir_filter *fdir_filter; 821 822 if (fdir_info->hash_map) 823 rte_free(fdir_info->hash_map); 824 if (fdir_info->hash_handle) 825 rte_hash_free(fdir_info->hash_handle); 826 827 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 828 TAILQ_REMOVE(&fdir_info->fdir_list, 829 fdir_filter, 830 entries); 831 rte_free(fdir_filter); 832 } 833 834 return 0; 835 } 836 837 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 838 { 839 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 840 struct txgbe_l2_tn_filter *l2_tn_filter; 841 842 if (l2_tn_info->hash_map) 843 rte_free(l2_tn_info->hash_map); 844 if (l2_tn_info->hash_handle) 845 rte_hash_free(l2_tn_info->hash_handle); 846 847 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 848 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 849 l2_tn_filter, 850 entries); 851 rte_free(l2_tn_filter); 852 } 853 854 return 0; 855 } 856 857 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 858 { 859 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 860 char fdir_hash_name[RTE_HASH_NAMESIZE]; 861 struct rte_hash_parameters fdir_hash_params = { 862 .name = fdir_hash_name, 863 .entries = TXGBE_MAX_FDIR_FILTER_NUM, 864 .key_len = sizeof(struct txgbe_atr_input), 865 .hash_func = rte_hash_crc, 866 .hash_func_init_val = 0, 867 .socket_id = rte_socket_id(), 868 }; 869 870 TAILQ_INIT(&fdir_info->fdir_list); 871 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 872 "fdir_%s", TDEV_NAME(eth_dev)); 873 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 874 if (!fdir_info->hash_handle) { 875 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 876 return -EINVAL; 877 } 878 fdir_info->hash_map = rte_zmalloc("txgbe", 879 sizeof(struct txgbe_fdir_filter *) * 880 TXGBE_MAX_FDIR_FILTER_NUM, 881 0); 882 if (!fdir_info->hash_map) { 883 PMD_INIT_LOG(ERR, 884 "Failed to allocate memory for fdir hash map!"); 885 return -ENOMEM; 886 } 887 fdir_info->mask_added = FALSE; 888 889 return 0; 890 } 891 892 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 893 { 894 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 895 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 896 struct rte_hash_parameters l2_tn_hash_params = { 897 .name = l2_tn_hash_name, 898 .entries = TXGBE_MAX_L2_TN_FILTER_NUM, 899 .key_len = sizeof(struct txgbe_l2_tn_key), 900 .hash_func = rte_hash_crc, 901 .hash_func_init_val = 0, 902 .socket_id = rte_socket_id(), 903 }; 904 905 TAILQ_INIT(&l2_tn_info->l2_tn_list); 906 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 907 "l2_tn_%s", TDEV_NAME(eth_dev)); 908 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 909 if (!l2_tn_info->hash_handle) { 910 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 911 return -EINVAL; 912 } 913 l2_tn_info->hash_map = rte_zmalloc("txgbe", 914 sizeof(struct txgbe_l2_tn_filter *) * 915 TXGBE_MAX_L2_TN_FILTER_NUM, 916 0); 917 if (!l2_tn_info->hash_map) { 918 PMD_INIT_LOG(ERR, 919 "Failed to allocate memory for L2 TN hash map!"); 920 return -ENOMEM; 921 } 922 l2_tn_info->e_tag_en = FALSE; 923 l2_tn_info->e_tag_fwd_en = FALSE; 924 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 925 926 return 0; 927 } 928 929 static int 930 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 931 struct rte_pci_device *pci_dev) 932 { 933 struct rte_eth_dev *pf_ethdev; 934 struct rte_eth_devargs eth_da; 935 int retval; 936 937 if (pci_dev->device.devargs) { 938 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 939 ð_da); 940 if (retval) 941 return retval; 942 } else { 943 memset(ð_da, 0, sizeof(eth_da)); 944 } 945 946 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 947 sizeof(struct txgbe_adapter), 948 eth_dev_pci_specific_init, pci_dev, 949 eth_txgbe_dev_init, NULL); 950 951 if (retval || eth_da.nb_representor_ports < 1) 952 return retval; 953 if (eth_da.type != RTE_ETH_REPRESENTOR_VF) 954 return -ENOTSUP; 955 956 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 957 if (pf_ethdev == NULL) 958 return -ENODEV; 959 960 return 0; 961 } 962 963 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev) 964 { 965 struct rte_eth_dev *ethdev; 966 967 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 968 if (!ethdev) 969 return -ENODEV; 970 971 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit); 972 } 973 974 static struct rte_pci_driver rte_txgbe_pmd = { 975 .id_table = pci_id_txgbe_map, 976 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | 977 RTE_PCI_DRV_INTR_LSC, 978 .probe = eth_txgbe_pci_probe, 979 .remove = eth_txgbe_pci_remove, 980 }; 981 982 static int 983 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 984 { 985 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 986 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 987 uint32_t vfta; 988 uint32_t vid_idx; 989 uint32_t vid_bit; 990 991 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F); 992 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F)); 993 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx)); 994 if (on) 995 vfta |= vid_bit; 996 else 997 vfta &= ~vid_bit; 998 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta); 999 1000 /* update local VFTA copy */ 1001 shadow_vfta->vfta[vid_idx] = vfta; 1002 1003 return 0; 1004 } 1005 1006 static void 1007 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1008 { 1009 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1010 struct txgbe_rx_queue *rxq; 1011 bool restart; 1012 uint32_t rxcfg, rxbal, rxbah; 1013 1014 if (on) 1015 txgbe_vlan_hw_strip_enable(dev, queue); 1016 else 1017 txgbe_vlan_hw_strip_disable(dev, queue); 1018 1019 rxq = dev->data->rx_queues[queue]; 1020 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx)); 1021 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx)); 1022 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx)); 1023 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 1024 restart = (rxcfg & TXGBE_RXCFG_ENA) && 1025 !(rxcfg & TXGBE_RXCFG_VLAN); 1026 rxcfg |= TXGBE_RXCFG_VLAN; 1027 } else { 1028 restart = (rxcfg & TXGBE_RXCFG_ENA) && 1029 (rxcfg & TXGBE_RXCFG_VLAN); 1030 rxcfg &= ~TXGBE_RXCFG_VLAN; 1031 } 1032 rxcfg &= ~TXGBE_RXCFG_ENA; 1033 1034 if (restart) { 1035 /* set vlan strip for ring */ 1036 txgbe_dev_rx_queue_stop(dev, queue); 1037 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal); 1038 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah); 1039 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg); 1040 txgbe_dev_rx_queue_start(dev, queue); 1041 } 1042 } 1043 1044 static int 1045 txgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1046 enum rte_vlan_type vlan_type, 1047 uint16_t tpid) 1048 { 1049 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1050 int ret = 0; 1051 uint32_t portctrl, vlan_ext, qinq; 1052 1053 portctrl = rd32(hw, TXGBE_PORTCTL); 1054 1055 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT); 1056 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ); 1057 switch (vlan_type) { 1058 case ETH_VLAN_TYPE_INNER: 1059 if (vlan_ext) { 1060 wr32m(hw, TXGBE_VLANCTL, 1061 TXGBE_VLANCTL_TPID_MASK, 1062 TXGBE_VLANCTL_TPID(tpid)); 1063 wr32m(hw, TXGBE_DMATXCTRL, 1064 TXGBE_DMATXCTRL_TPID_MASK, 1065 TXGBE_DMATXCTRL_TPID(tpid)); 1066 } else { 1067 ret = -ENOTSUP; 1068 PMD_DRV_LOG(ERR, "Inner type is not supported" 1069 " by single VLAN"); 1070 } 1071 1072 if (qinq) { 1073 wr32m(hw, TXGBE_TAGTPID(0), 1074 TXGBE_TAGTPID_LSB_MASK, 1075 TXGBE_TAGTPID_LSB(tpid)); 1076 } 1077 break; 1078 case ETH_VLAN_TYPE_OUTER: 1079 if (vlan_ext) { 1080 /* Only the high 16-bits is valid */ 1081 wr32m(hw, TXGBE_EXTAG, 1082 TXGBE_EXTAG_VLAN_MASK, 1083 TXGBE_EXTAG_VLAN(tpid)); 1084 } else { 1085 wr32m(hw, TXGBE_VLANCTL, 1086 TXGBE_VLANCTL_TPID_MASK, 1087 TXGBE_VLANCTL_TPID(tpid)); 1088 wr32m(hw, TXGBE_DMATXCTRL, 1089 TXGBE_DMATXCTRL_TPID_MASK, 1090 TXGBE_DMATXCTRL_TPID(tpid)); 1091 } 1092 1093 if (qinq) { 1094 wr32m(hw, TXGBE_TAGTPID(0), 1095 TXGBE_TAGTPID_MSB_MASK, 1096 TXGBE_TAGTPID_MSB(tpid)); 1097 } 1098 break; 1099 default: 1100 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1101 return -EINVAL; 1102 } 1103 1104 return ret; 1105 } 1106 1107 void 1108 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1109 { 1110 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1111 uint32_t vlnctrl; 1112 1113 PMD_INIT_FUNC_TRACE(); 1114 1115 /* Filter Table Disable */ 1116 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1117 vlnctrl &= ~TXGBE_VLANCTL_VFE; 1118 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1119 } 1120 1121 void 1122 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1123 { 1124 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1125 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 1126 uint32_t vlnctrl; 1127 uint16_t i; 1128 1129 PMD_INIT_FUNC_TRACE(); 1130 1131 /* Filter Table Enable */ 1132 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1133 vlnctrl &= ~TXGBE_VLANCTL_CFIENA; 1134 vlnctrl |= TXGBE_VLANCTL_VFE; 1135 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1136 1137 /* write whatever is in local vfta copy */ 1138 for (i = 0; i < TXGBE_VFTA_SIZE; i++) 1139 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]); 1140 } 1141 1142 void 1143 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1144 { 1145 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev); 1146 struct txgbe_rx_queue *rxq; 1147 1148 if (queue >= TXGBE_MAX_RX_QUEUE_NUM) 1149 return; 1150 1151 if (on) 1152 TXGBE_SET_HWSTRIP(hwstrip, queue); 1153 else 1154 TXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1155 1156 if (queue >= dev->data->nb_rx_queues) 1157 return; 1158 1159 rxq = dev->data->rx_queues[queue]; 1160 1161 if (on) { 1162 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1163 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1164 } else { 1165 rxq->vlan_flags = PKT_RX_VLAN; 1166 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1167 } 1168 } 1169 1170 static void 1171 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1172 { 1173 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1174 uint32_t ctrl; 1175 1176 PMD_INIT_FUNC_TRACE(); 1177 1178 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1179 ctrl &= ~TXGBE_RXCFG_VLAN; 1180 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1181 1182 /* record those setting for HW strip per queue */ 1183 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 1184 } 1185 1186 static void 1187 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 1188 { 1189 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1190 uint32_t ctrl; 1191 1192 PMD_INIT_FUNC_TRACE(); 1193 1194 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1195 ctrl |= TXGBE_RXCFG_VLAN; 1196 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1197 1198 /* record those setting for HW strip per queue */ 1199 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 1200 } 1201 1202 static void 1203 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 1204 { 1205 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1206 uint32_t ctrl; 1207 1208 PMD_INIT_FUNC_TRACE(); 1209 1210 ctrl = rd32(hw, TXGBE_PORTCTL); 1211 ctrl &= ~TXGBE_PORTCTL_VLANEXT; 1212 ctrl &= ~TXGBE_PORTCTL_QINQ; 1213 wr32(hw, TXGBE_PORTCTL, ctrl); 1214 } 1215 1216 static void 1217 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 1218 { 1219 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1220 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1221 struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode; 1222 uint32_t ctrl; 1223 1224 PMD_INIT_FUNC_TRACE(); 1225 1226 ctrl = rd32(hw, TXGBE_PORTCTL); 1227 ctrl |= TXGBE_PORTCTL_VLANEXT; 1228 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP || 1229 txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT) 1230 ctrl |= TXGBE_PORTCTL_QINQ; 1231 wr32(hw, TXGBE_PORTCTL, ctrl); 1232 } 1233 1234 void 1235 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 1236 { 1237 struct txgbe_rx_queue *rxq; 1238 uint16_t i; 1239 1240 PMD_INIT_FUNC_TRACE(); 1241 1242 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1243 rxq = dev->data->rx_queues[i]; 1244 1245 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1246 txgbe_vlan_strip_queue_set(dev, i, 1); 1247 else 1248 txgbe_vlan_strip_queue_set(dev, i, 0); 1249 } 1250 } 1251 1252 void 1253 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 1254 { 1255 uint16_t i; 1256 struct rte_eth_rxmode *rxmode; 1257 struct txgbe_rx_queue *rxq; 1258 1259 if (mask & ETH_VLAN_STRIP_MASK) { 1260 rxmode = &dev->data->dev_conf.rxmode; 1261 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1262 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1263 rxq = dev->data->rx_queues[i]; 1264 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1265 } 1266 else 1267 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1268 rxq = dev->data->rx_queues[i]; 1269 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1270 } 1271 } 1272 } 1273 1274 static int 1275 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 1276 { 1277 struct rte_eth_rxmode *rxmode; 1278 rxmode = &dev->data->dev_conf.rxmode; 1279 1280 if (mask & ETH_VLAN_STRIP_MASK) 1281 txgbe_vlan_hw_strip_config(dev); 1282 1283 if (mask & ETH_VLAN_FILTER_MASK) { 1284 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1285 txgbe_vlan_hw_filter_enable(dev); 1286 else 1287 txgbe_vlan_hw_filter_disable(dev); 1288 } 1289 1290 if (mask & ETH_VLAN_EXTEND_MASK) { 1291 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 1292 txgbe_vlan_hw_extend_enable(dev); 1293 else 1294 txgbe_vlan_hw_extend_disable(dev); 1295 } 1296 1297 return 0; 1298 } 1299 1300 static int 1301 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1302 { 1303 txgbe_config_vlan_strip_on_all_queues(dev, mask); 1304 1305 txgbe_vlan_offload_config(dev, mask); 1306 1307 return 0; 1308 } 1309 1310 static void 1311 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1312 { 1313 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1314 /* VLNCTL: enable vlan filtering and allow all vlan tags through */ 1315 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL); 1316 1317 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */ 1318 wr32(hw, TXGBE_VLANCTL, vlanctrl); 1319 } 1320 1321 static int 1322 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 1323 { 1324 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1325 1326 switch (nb_rx_q) { 1327 case 1: 1328 case 2: 1329 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 1330 break; 1331 case 4: 1332 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 1333 break; 1334 default: 1335 return -EINVAL; 1336 } 1337 1338 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1339 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1340 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 1341 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1342 return 0; 1343 } 1344 1345 static int 1346 txgbe_check_mq_mode(struct rte_eth_dev *dev) 1347 { 1348 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1349 uint16_t nb_rx_q = dev->data->nb_rx_queues; 1350 uint16_t nb_tx_q = dev->data->nb_tx_queues; 1351 1352 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 1353 /* check multi-queue mode */ 1354 switch (dev_conf->rxmode.mq_mode) { 1355 case ETH_MQ_RX_VMDQ_DCB: 1356 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 1357 break; 1358 case ETH_MQ_RX_VMDQ_DCB_RSS: 1359 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 1360 PMD_INIT_LOG(ERR, "SRIOV active," 1361 " unsupported mq_mode rx %d.", 1362 dev_conf->rxmode.mq_mode); 1363 return -EINVAL; 1364 case ETH_MQ_RX_RSS: 1365 case ETH_MQ_RX_VMDQ_RSS: 1366 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 1367 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 1368 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 1369 PMD_INIT_LOG(ERR, "SRIOV is active," 1370 " invalid queue number" 1371 " for VMDQ RSS, allowed" 1372 " value are 1, 2 or 4."); 1373 return -EINVAL; 1374 } 1375 break; 1376 case ETH_MQ_RX_VMDQ_ONLY: 1377 case ETH_MQ_RX_NONE: 1378 /* if nothing mq mode configure, use default scheme */ 1379 dev->data->dev_conf.rxmode.mq_mode = 1380 ETH_MQ_RX_VMDQ_ONLY; 1381 break; 1382 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 1383 /* SRIOV only works in VMDq enable mode */ 1384 PMD_INIT_LOG(ERR, "SRIOV is active," 1385 " wrong mq_mode rx %d.", 1386 dev_conf->rxmode.mq_mode); 1387 return -EINVAL; 1388 } 1389 1390 switch (dev_conf->txmode.mq_mode) { 1391 case ETH_MQ_TX_VMDQ_DCB: 1392 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 1393 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 1394 break; 1395 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 1396 dev->data->dev_conf.txmode.mq_mode = 1397 ETH_MQ_TX_VMDQ_ONLY; 1398 break; 1399 } 1400 1401 /* check valid queue number */ 1402 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 1403 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 1404 PMD_INIT_LOG(ERR, "SRIOV is active," 1405 " nb_rx_q=%d nb_tx_q=%d queue number" 1406 " must be less than or equal to %d.", 1407 nb_rx_q, nb_tx_q, 1408 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 1409 return -EINVAL; 1410 } 1411 } else { 1412 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 1413 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 1414 " not supported."); 1415 return -EINVAL; 1416 } 1417 /* check configuration for vmdb+dcb mode */ 1418 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 1419 const struct rte_eth_vmdq_dcb_conf *conf; 1420 1421 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1422 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 1423 TXGBE_VMDQ_DCB_NB_QUEUES); 1424 return -EINVAL; 1425 } 1426 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 1427 if (!(conf->nb_queue_pools == ETH_16_POOLS || 1428 conf->nb_queue_pools == ETH_32_POOLS)) { 1429 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1430 " nb_queue_pools must be %d or %d.", 1431 ETH_16_POOLS, ETH_32_POOLS); 1432 return -EINVAL; 1433 } 1434 } 1435 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 1436 const struct rte_eth_vmdq_dcb_tx_conf *conf; 1437 1438 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1439 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 1440 TXGBE_VMDQ_DCB_NB_QUEUES); 1441 return -EINVAL; 1442 } 1443 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 1444 if (!(conf->nb_queue_pools == ETH_16_POOLS || 1445 conf->nb_queue_pools == ETH_32_POOLS)) { 1446 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1447 " nb_queue_pools != %d and" 1448 " nb_queue_pools != %d.", 1449 ETH_16_POOLS, ETH_32_POOLS); 1450 return -EINVAL; 1451 } 1452 } 1453 1454 /* For DCB mode check our configuration before we go further */ 1455 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 1456 const struct rte_eth_dcb_rx_conf *conf; 1457 1458 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 1459 if (!(conf->nb_tcs == ETH_4_TCS || 1460 conf->nb_tcs == ETH_8_TCS)) { 1461 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1462 " and nb_tcs != %d.", 1463 ETH_4_TCS, ETH_8_TCS); 1464 return -EINVAL; 1465 } 1466 } 1467 1468 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 1469 const struct rte_eth_dcb_tx_conf *conf; 1470 1471 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 1472 if (!(conf->nb_tcs == ETH_4_TCS || 1473 conf->nb_tcs == ETH_8_TCS)) { 1474 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1475 " and nb_tcs != %d.", 1476 ETH_4_TCS, ETH_8_TCS); 1477 return -EINVAL; 1478 } 1479 } 1480 } 1481 return 0; 1482 } 1483 1484 static int 1485 txgbe_dev_configure(struct rte_eth_dev *dev) 1486 { 1487 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1488 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1489 int ret; 1490 1491 PMD_INIT_FUNC_TRACE(); 1492 1493 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1494 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1495 1496 /* multiple queue mode checking */ 1497 ret = txgbe_check_mq_mode(dev); 1498 if (ret != 0) { 1499 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.", 1500 ret); 1501 return ret; 1502 } 1503 1504 /* set flag to update link status after init */ 1505 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 1506 1507 /* 1508 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 1509 * allocation Rx preconditions we will reset it. 1510 */ 1511 adapter->rx_bulk_alloc_allowed = true; 1512 1513 return 0; 1514 } 1515 1516 static void 1517 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 1518 { 1519 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1520 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1521 uint32_t gpie; 1522 1523 gpie = rd32(hw, TXGBE_GPIOINTEN); 1524 gpie |= TXGBE_GPIOBIT_6; 1525 wr32(hw, TXGBE_GPIOINTEN, gpie); 1526 intr->mask_misc |= TXGBE_ICRMISC_GPIO; 1527 intr->mask_misc |= TXGBE_ICRMISC_ANDONE; 1528 } 1529 1530 int 1531 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 1532 uint16_t tx_rate, uint64_t q_msk) 1533 { 1534 struct txgbe_hw *hw; 1535 struct txgbe_vf_info *vfinfo; 1536 struct rte_eth_link link; 1537 uint8_t nb_q_per_pool; 1538 uint32_t queue_stride; 1539 uint32_t queue_idx, idx = 0, vf_idx; 1540 uint32_t queue_end; 1541 uint16_t total_rate = 0; 1542 struct rte_pci_device *pci_dev; 1543 int ret; 1544 1545 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1546 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 1547 if (ret < 0) 1548 return ret; 1549 1550 if (vf >= pci_dev->max_vfs) 1551 return -EINVAL; 1552 1553 if (tx_rate > link.link_speed) 1554 return -EINVAL; 1555 1556 if (q_msk == 0) 1557 return 0; 1558 1559 hw = TXGBE_DEV_HW(dev); 1560 vfinfo = *(TXGBE_DEV_VFDATA(dev)); 1561 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1562 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1563 queue_idx = vf * queue_stride; 1564 queue_end = queue_idx + nb_q_per_pool - 1; 1565 if (queue_end >= hw->mac.max_tx_queues) 1566 return -EINVAL; 1567 1568 if (vfinfo) { 1569 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 1570 if (vf_idx == vf) 1571 continue; 1572 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 1573 idx++) 1574 total_rate += vfinfo[vf_idx].tx_rate[idx]; 1575 } 1576 } else { 1577 return -EINVAL; 1578 } 1579 1580 /* Store tx_rate for this vf. */ 1581 for (idx = 0; idx < nb_q_per_pool; idx++) { 1582 if (((uint64_t)0x1 << idx) & q_msk) { 1583 if (vfinfo[vf].tx_rate[idx] != tx_rate) 1584 vfinfo[vf].tx_rate[idx] = tx_rate; 1585 total_rate += tx_rate; 1586 } 1587 } 1588 1589 if (total_rate > dev->data->dev_link.link_speed) { 1590 /* Reset stored TX rate of the VF if it causes exceed 1591 * link speed. 1592 */ 1593 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 1594 return -EINVAL; 1595 } 1596 1597 /* Set ARBTXRATE of each queue/pool for vf X */ 1598 for (; queue_idx <= queue_end; queue_idx++) { 1599 if (0x1 & q_msk) 1600 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 1601 q_msk = q_msk >> 1; 1602 } 1603 1604 return 0; 1605 } 1606 1607 /* 1608 * Configure device link speed and setup link. 1609 * It returns 0 on success. 1610 */ 1611 static int 1612 txgbe_dev_start(struct rte_eth_dev *dev) 1613 { 1614 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1615 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 1616 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1617 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1618 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1619 uint32_t intr_vector = 0; 1620 int err; 1621 bool link_up = false, negotiate = 0; 1622 uint32_t speed = 0; 1623 uint32_t allowed_speeds = 0; 1624 int mask = 0; 1625 int status; 1626 uint16_t vf, idx; 1627 uint32_t *link_speeds; 1628 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1629 1630 PMD_INIT_FUNC_TRACE(); 1631 1632 /* TXGBE devices don't support: 1633 * - half duplex (checked afterwards for valid speeds) 1634 * - fixed speed: TODO implement 1635 */ 1636 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 1637 PMD_INIT_LOG(ERR, 1638 "Invalid link_speeds for port %u, fix speed not supported", 1639 dev->data->port_id); 1640 return -EINVAL; 1641 } 1642 1643 /* Stop the link setup handler before resetting the HW. */ 1644 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1645 1646 /* disable uio/vfio intr/eventfd mapping */ 1647 rte_intr_disable(intr_handle); 1648 1649 /* stop adapter */ 1650 hw->adapter_stopped = 0; 1651 txgbe_stop_hw(hw); 1652 1653 /* reinitialize adapter 1654 * this calls reset and start 1655 */ 1656 hw->nb_rx_queues = dev->data->nb_rx_queues; 1657 hw->nb_tx_queues = dev->data->nb_tx_queues; 1658 status = txgbe_pf_reset_hw(hw); 1659 if (status != 0) 1660 return -1; 1661 hw->mac.start_hw(hw); 1662 hw->mac.get_link_status = true; 1663 1664 /* configure PF module if SRIOV enabled */ 1665 txgbe_pf_host_configure(dev); 1666 1667 txgbe_dev_phy_intr_setup(dev); 1668 1669 /* check and configure queue intr-vector mapping */ 1670 if ((rte_intr_cap_multiple(intr_handle) || 1671 !RTE_ETH_DEV_SRIOV(dev).active) && 1672 dev->data->dev_conf.intr_conf.rxq != 0) { 1673 intr_vector = dev->data->nb_rx_queues; 1674 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1675 return -1; 1676 } 1677 1678 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1679 intr_handle->intr_vec = 1680 rte_zmalloc("intr_vec", 1681 dev->data->nb_rx_queues * sizeof(int), 0); 1682 if (intr_handle->intr_vec == NULL) { 1683 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 1684 " intr_vec", dev->data->nb_rx_queues); 1685 return -ENOMEM; 1686 } 1687 } 1688 1689 /* confiugre msix for sleep until rx interrupt */ 1690 txgbe_configure_msix(dev); 1691 1692 /* initialize transmission unit */ 1693 txgbe_dev_tx_init(dev); 1694 1695 /* This can fail when allocating mbufs for descriptor rings */ 1696 err = txgbe_dev_rx_init(dev); 1697 if (err) { 1698 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 1699 goto error; 1700 } 1701 1702 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 1703 ETH_VLAN_EXTEND_MASK; 1704 err = txgbe_vlan_offload_config(dev, mask); 1705 if (err) { 1706 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 1707 goto error; 1708 } 1709 1710 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 1711 /* Enable vlan filtering for VMDq */ 1712 txgbe_vmdq_vlan_hw_filter_enable(dev); 1713 } 1714 1715 /* Configure DCB hw */ 1716 txgbe_configure_pb(dev); 1717 txgbe_configure_port(dev); 1718 txgbe_configure_dcb(dev); 1719 1720 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1721 err = txgbe_fdir_configure(dev); 1722 if (err) 1723 goto error; 1724 } 1725 1726 /* Restore vf rate limit */ 1727 if (vfinfo != NULL) { 1728 for (vf = 0; vf < pci_dev->max_vfs; vf++) 1729 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 1730 if (vfinfo[vf].tx_rate[idx] != 0) 1731 txgbe_set_vf_rate_limit(dev, vf, 1732 vfinfo[vf].tx_rate[idx], 1733 1 << idx); 1734 } 1735 1736 err = txgbe_dev_rxtx_start(dev); 1737 if (err < 0) { 1738 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 1739 goto error; 1740 } 1741 1742 /* Skip link setup if loopback mode is enabled. */ 1743 if (hw->mac.type == txgbe_mac_raptor && 1744 dev->data->dev_conf.lpbk_mode) 1745 goto skip_link_setup; 1746 1747 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 1748 err = hw->mac.setup_sfp(hw); 1749 if (err) 1750 goto error; 1751 } 1752 1753 if (hw->phy.media_type == txgbe_media_type_copper) { 1754 /* Turn on the copper */ 1755 hw->phy.set_phy_power(hw, true); 1756 } else { 1757 /* Turn on the laser */ 1758 hw->mac.enable_tx_laser(hw); 1759 } 1760 1761 if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4) 1762 err = hw->mac.check_link(hw, &speed, &link_up, 0); 1763 if (err) 1764 goto error; 1765 dev->data->dev_link.link_status = link_up; 1766 1767 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate); 1768 if (err) 1769 goto error; 1770 1771 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 1772 ETH_LINK_SPEED_10G; 1773 1774 link_speeds = &dev->data->dev_conf.link_speeds; 1775 if (*link_speeds & ~allowed_speeds) { 1776 PMD_INIT_LOG(ERR, "Invalid link setting"); 1777 goto error; 1778 } 1779 1780 speed = 0x0; 1781 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 1782 speed = (TXGBE_LINK_SPEED_100M_FULL | 1783 TXGBE_LINK_SPEED_1GB_FULL | 1784 TXGBE_LINK_SPEED_10GB_FULL); 1785 } else { 1786 if (*link_speeds & ETH_LINK_SPEED_10G) 1787 speed |= TXGBE_LINK_SPEED_10GB_FULL; 1788 if (*link_speeds & ETH_LINK_SPEED_5G) 1789 speed |= TXGBE_LINK_SPEED_5GB_FULL; 1790 if (*link_speeds & ETH_LINK_SPEED_2_5G) 1791 speed |= TXGBE_LINK_SPEED_2_5GB_FULL; 1792 if (*link_speeds & ETH_LINK_SPEED_1G) 1793 speed |= TXGBE_LINK_SPEED_1GB_FULL; 1794 if (*link_speeds & ETH_LINK_SPEED_100M) 1795 speed |= TXGBE_LINK_SPEED_100M_FULL; 1796 } 1797 1798 err = hw->mac.setup_link(hw, speed, link_up); 1799 if (err) 1800 goto error; 1801 1802 skip_link_setup: 1803 1804 if (rte_intr_allow_others(intr_handle)) { 1805 txgbe_dev_misc_interrupt_setup(dev); 1806 /* check if lsc interrupt is enabled */ 1807 if (dev->data->dev_conf.intr_conf.lsc != 0) 1808 txgbe_dev_lsc_interrupt_setup(dev, TRUE); 1809 else 1810 txgbe_dev_lsc_interrupt_setup(dev, FALSE); 1811 txgbe_dev_macsec_interrupt_setup(dev); 1812 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 1813 } else { 1814 rte_intr_callback_unregister(intr_handle, 1815 txgbe_dev_interrupt_handler, dev); 1816 if (dev->data->dev_conf.intr_conf.lsc != 0) 1817 PMD_INIT_LOG(INFO, "lsc won't enable because of" 1818 " no intr multiplex"); 1819 } 1820 1821 /* check if rxq interrupt is enabled */ 1822 if (dev->data->dev_conf.intr_conf.rxq != 0 && 1823 rte_intr_dp_is_en(intr_handle)) 1824 txgbe_dev_rxq_interrupt_setup(dev); 1825 1826 /* enable uio/vfio intr/eventfd mapping */ 1827 rte_intr_enable(intr_handle); 1828 1829 /* resume enabled intr since hw reset */ 1830 txgbe_enable_intr(dev); 1831 txgbe_l2_tunnel_conf(dev); 1832 txgbe_filter_restore(dev); 1833 1834 if (tm_conf->root && !tm_conf->committed) 1835 PMD_DRV_LOG(WARNING, 1836 "please call hierarchy_commit() " 1837 "before starting the port"); 1838 1839 /* 1840 * Update link status right before return, because it may 1841 * start link configuration process in a separate thread. 1842 */ 1843 txgbe_dev_link_update(dev, 0); 1844 1845 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK); 1846 1847 txgbe_read_stats_registers(hw, hw_stats); 1848 hw->offset_loaded = 1; 1849 1850 return 0; 1851 1852 error: 1853 PMD_INIT_LOG(ERR, "failure in dev start: %d", err); 1854 txgbe_dev_clear_queues(dev); 1855 return -EIO; 1856 } 1857 1858 /* 1859 * Stop device: disable rx and tx functions to allow for reconfiguring. 1860 */ 1861 static int 1862 txgbe_dev_stop(struct rte_eth_dev *dev) 1863 { 1864 struct rte_eth_link link; 1865 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1866 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1867 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1868 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1869 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1870 int vf; 1871 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1872 1873 if (hw->adapter_stopped) 1874 return 0; 1875 1876 PMD_INIT_FUNC_TRACE(); 1877 1878 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1879 1880 /* disable interrupts */ 1881 txgbe_disable_intr(hw); 1882 1883 /* reset the NIC */ 1884 txgbe_pf_reset_hw(hw); 1885 hw->adapter_stopped = 0; 1886 1887 /* stop adapter */ 1888 txgbe_stop_hw(hw); 1889 1890 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 1891 vfinfo[vf].clear_to_send = false; 1892 1893 if (hw->phy.media_type == txgbe_media_type_copper) { 1894 /* Turn off the copper */ 1895 hw->phy.set_phy_power(hw, false); 1896 } else { 1897 /* Turn off the laser */ 1898 hw->mac.disable_tx_laser(hw); 1899 } 1900 1901 txgbe_dev_clear_queues(dev); 1902 1903 /* Clear stored conf */ 1904 dev->data->scattered_rx = 0; 1905 dev->data->lro = 0; 1906 1907 /* Clear recorded link status */ 1908 memset(&link, 0, sizeof(link)); 1909 rte_eth_linkstatus_set(dev, &link); 1910 1911 if (!rte_intr_allow_others(intr_handle)) 1912 /* resume to the default handler */ 1913 rte_intr_callback_register(intr_handle, 1914 txgbe_dev_interrupt_handler, 1915 (void *)dev); 1916 1917 /* Clean datapath event and queue/vec mapping */ 1918 rte_intr_efd_disable(intr_handle); 1919 if (intr_handle->intr_vec != NULL) { 1920 rte_free(intr_handle->intr_vec); 1921 intr_handle->intr_vec = NULL; 1922 } 1923 1924 /* reset hierarchy commit */ 1925 tm_conf->committed = false; 1926 1927 adapter->rss_reta_updated = 0; 1928 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK); 1929 1930 hw->adapter_stopped = true; 1931 dev->data->dev_started = 0; 1932 1933 return 0; 1934 } 1935 1936 /* 1937 * Set device link up: enable tx. 1938 */ 1939 static int 1940 txgbe_dev_set_link_up(struct rte_eth_dev *dev) 1941 { 1942 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1943 1944 if (hw->phy.media_type == txgbe_media_type_copper) { 1945 /* Turn on the copper */ 1946 hw->phy.set_phy_power(hw, true); 1947 } else { 1948 /* Turn on the laser */ 1949 hw->mac.enable_tx_laser(hw); 1950 txgbe_dev_link_update(dev, 0); 1951 } 1952 1953 return 0; 1954 } 1955 1956 /* 1957 * Set device link down: disable tx. 1958 */ 1959 static int 1960 txgbe_dev_set_link_down(struct rte_eth_dev *dev) 1961 { 1962 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1963 1964 if (hw->phy.media_type == txgbe_media_type_copper) { 1965 /* Turn off the copper */ 1966 hw->phy.set_phy_power(hw, false); 1967 } else { 1968 /* Turn off the laser */ 1969 hw->mac.disable_tx_laser(hw); 1970 txgbe_dev_link_update(dev, 0); 1971 } 1972 1973 return 0; 1974 } 1975 1976 /* 1977 * Reset and stop device. 1978 */ 1979 static int 1980 txgbe_dev_close(struct rte_eth_dev *dev) 1981 { 1982 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1983 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1984 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1985 int retries = 0; 1986 int ret; 1987 1988 PMD_INIT_FUNC_TRACE(); 1989 1990 txgbe_pf_reset_hw(hw); 1991 1992 ret = txgbe_dev_stop(dev); 1993 1994 txgbe_dev_free_queues(dev); 1995 1996 /* reprogram the RAR[0] in case user changed it. */ 1997 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true); 1998 1999 /* Unlock any pending hardware semaphore */ 2000 txgbe_swfw_lock_reset(hw); 2001 2002 /* disable uio intr before callback unregister */ 2003 rte_intr_disable(intr_handle); 2004 2005 do { 2006 ret = rte_intr_callback_unregister(intr_handle, 2007 txgbe_dev_interrupt_handler, dev); 2008 if (ret >= 0 || ret == -ENOENT) { 2009 break; 2010 } else if (ret != -EAGAIN) { 2011 PMD_INIT_LOG(ERR, 2012 "intr callback unregister failed: %d", 2013 ret); 2014 } 2015 rte_delay_ms(100); 2016 } while (retries++ < (10 + TXGBE_LINK_UP_TIME)); 2017 2018 /* cancel the delay handler before remove dev */ 2019 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev); 2020 2021 /* uninitialize PF if max_vfs not zero */ 2022 txgbe_pf_host_uninit(dev); 2023 2024 rte_free(dev->data->mac_addrs); 2025 dev->data->mac_addrs = NULL; 2026 2027 rte_free(dev->data->hash_mac_addrs); 2028 dev->data->hash_mac_addrs = NULL; 2029 2030 /* remove all the fdir filters & hash */ 2031 txgbe_fdir_filter_uninit(dev); 2032 2033 /* remove all the L2 tunnel filters & hash */ 2034 txgbe_l2_tn_filter_uninit(dev); 2035 2036 /* Remove all ntuple filters of the device */ 2037 txgbe_ntuple_filter_uninit(dev); 2038 2039 /* clear all the filters list */ 2040 txgbe_filterlist_flush(); 2041 2042 /* Remove all Traffic Manager configuration */ 2043 txgbe_tm_conf_uninit(dev); 2044 2045 #ifdef RTE_LIB_SECURITY 2046 rte_free(dev->security_ctx); 2047 #endif 2048 2049 return ret; 2050 } 2051 2052 /* 2053 * Reset PF device. 2054 */ 2055 static int 2056 txgbe_dev_reset(struct rte_eth_dev *dev) 2057 { 2058 int ret; 2059 2060 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2061 * its VF to make them align with it. The detailed notification 2062 * mechanism is PMD specific. As to txgbe PF, it is rather complex. 2063 * To avoid unexpected behavior in VF, currently reset of PF with 2064 * SR-IOV activation is not supported. It might be supported later. 2065 */ 2066 if (dev->data->sriov.active) 2067 return -ENOTSUP; 2068 2069 ret = eth_txgbe_dev_uninit(dev); 2070 if (ret) 2071 return ret; 2072 2073 ret = eth_txgbe_dev_init(dev, NULL); 2074 2075 return ret; 2076 } 2077 2078 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \ 2079 { \ 2080 uint32_t current_counter = rd32(hw, reg); \ 2081 if (current_counter < last_counter) \ 2082 current_counter += 0x100000000LL; \ 2083 if (!hw->offset_loaded) \ 2084 last_counter = current_counter; \ 2085 counter = current_counter - last_counter; \ 2086 counter &= 0xFFFFFFFFLL; \ 2087 } 2088 2089 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ 2090 { \ 2091 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \ 2092 uint64_t current_counter_msb = rd32(hw, reg_msb); \ 2093 uint64_t current_counter = (current_counter_msb << 32) | \ 2094 current_counter_lsb; \ 2095 if (current_counter < last_counter) \ 2096 current_counter += 0x1000000000LL; \ 2097 if (!hw->offset_loaded) \ 2098 last_counter = current_counter; \ 2099 counter = current_counter - last_counter; \ 2100 counter &= 0xFFFFFFFFFLL; \ 2101 } 2102 2103 void 2104 txgbe_read_stats_registers(struct txgbe_hw *hw, 2105 struct txgbe_hw_stats *hw_stats) 2106 { 2107 unsigned int i; 2108 2109 /* QP Stats */ 2110 for (i = 0; i < hw->nb_rx_queues; i++) { 2111 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i), 2112 hw->qp_last[i].rx_qp_packets, 2113 hw_stats->qp[i].rx_qp_packets); 2114 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i), 2115 hw->qp_last[i].rx_qp_bytes, 2116 hw_stats->qp[i].rx_qp_bytes); 2117 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i), 2118 hw->qp_last[i].rx_qp_mc_packets, 2119 hw_stats->qp[i].rx_qp_mc_packets); 2120 } 2121 2122 for (i = 0; i < hw->nb_tx_queues; i++) { 2123 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i), 2124 hw->qp_last[i].tx_qp_packets, 2125 hw_stats->qp[i].tx_qp_packets); 2126 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i), 2127 hw->qp_last[i].tx_qp_bytes, 2128 hw_stats->qp[i].tx_qp_bytes); 2129 } 2130 /* PB Stats */ 2131 for (i = 0; i < TXGBE_MAX_UP; i++) { 2132 hw_stats->up[i].rx_up_xon_packets += 2133 rd32(hw, TXGBE_PBRXUPXON(i)); 2134 hw_stats->up[i].rx_up_xoff_packets += 2135 rd32(hw, TXGBE_PBRXUPXOFF(i)); 2136 hw_stats->up[i].tx_up_xon_packets += 2137 rd32(hw, TXGBE_PBTXUPXON(i)); 2138 hw_stats->up[i].tx_up_xoff_packets += 2139 rd32(hw, TXGBE_PBTXUPXOFF(i)); 2140 hw_stats->up[i].tx_up_xon2off_packets += 2141 rd32(hw, TXGBE_PBTXUPOFF(i)); 2142 hw_stats->up[i].rx_up_dropped += 2143 rd32(hw, TXGBE_PBRXMISS(i)); 2144 } 2145 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON); 2146 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF); 2147 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON); 2148 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF); 2149 2150 /* DMA Stats */ 2151 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT); 2152 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT); 2153 2154 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL); 2155 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL); 2156 hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP); 2157 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP); 2158 2159 /* MAC Stats */ 2160 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL); 2161 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL); 2162 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL); 2163 2164 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL); 2165 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL); 2166 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL); 2167 2168 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL); 2169 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL); 2170 2171 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L); 2172 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L); 2173 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L); 2174 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L); 2175 hw_stats->rx_size_512_to_1023_packets += 2176 rd64(hw, TXGBE_MACRX512TO1023L); 2177 hw_stats->rx_size_1024_to_max_packets += 2178 rd64(hw, TXGBE_MACRX1024TOMAXL); 2179 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L); 2180 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L); 2181 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L); 2182 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L); 2183 hw_stats->tx_size_512_to_1023_packets += 2184 rd64(hw, TXGBE_MACTX512TO1023L); 2185 hw_stats->tx_size_1024_to_max_packets += 2186 rd64(hw, TXGBE_MACTX1024TOMAXL); 2187 2188 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL); 2189 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE); 2190 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER); 2191 2192 /* MNG Stats */ 2193 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS); 2194 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC); 2195 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG); 2196 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG); 2197 2198 /* FCoE Stats */ 2199 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC); 2200 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST); 2201 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC); 2202 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC); 2203 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC); 2204 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC); 2205 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC); 2206 2207 /* Flow Director Stats */ 2208 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH); 2209 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS); 2210 hw_stats->flow_director_added_filters += 2211 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED)); 2212 hw_stats->flow_director_removed_filters += 2213 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED)); 2214 hw_stats->flow_director_filter_add_errors += 2215 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL)); 2216 hw_stats->flow_director_filter_remove_errors += 2217 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL)); 2218 2219 /* MACsec Stats */ 2220 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT); 2221 hw_stats->tx_macsec_pkts_encrypted += 2222 rd32(hw, TXGBE_LSECTX_ENCPKT); 2223 hw_stats->tx_macsec_pkts_protected += 2224 rd32(hw, TXGBE_LSECTX_PROTPKT); 2225 hw_stats->tx_macsec_octets_encrypted += 2226 rd32(hw, TXGBE_LSECTX_ENCOCT); 2227 hw_stats->tx_macsec_octets_protected += 2228 rd32(hw, TXGBE_LSECTX_PROTOCT); 2229 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT); 2230 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT); 2231 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT); 2232 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT); 2233 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT); 2234 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT); 2235 hw_stats->rx_macsec_sc_pkts_unchecked += 2236 rd32(hw, TXGBE_LSECRX_UNCHKPKT); 2237 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT); 2238 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT); 2239 for (i = 0; i < 2; i++) { 2240 hw_stats->rx_macsec_sa_pkts_ok += 2241 rd32(hw, TXGBE_LSECRX_OKPKT(i)); 2242 hw_stats->rx_macsec_sa_pkts_invalid += 2243 rd32(hw, TXGBE_LSECRX_INVPKT(i)); 2244 hw_stats->rx_macsec_sa_pkts_notvalid += 2245 rd32(hw, TXGBE_LSECRX_BADPKT(i)); 2246 } 2247 hw_stats->rx_macsec_sa_pkts_unusedsa += 2248 rd32(hw, TXGBE_LSECRX_INVSAPKT); 2249 hw_stats->rx_macsec_sa_pkts_notusingsa += 2250 rd32(hw, TXGBE_LSECRX_BADSAPKT); 2251 2252 hw_stats->rx_total_missed_packets = 0; 2253 for (i = 0; i < TXGBE_MAX_UP; i++) { 2254 hw_stats->rx_total_missed_packets += 2255 hw_stats->up[i].rx_up_dropped; 2256 } 2257 } 2258 2259 static int 2260 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 2261 { 2262 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2263 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2264 struct txgbe_stat_mappings *stat_mappings = 2265 TXGBE_DEV_STAT_MAPPINGS(dev); 2266 uint32_t i, j; 2267 2268 txgbe_read_stats_registers(hw, hw_stats); 2269 2270 if (stats == NULL) 2271 return -EINVAL; 2272 2273 /* Fill out the rte_eth_stats statistics structure */ 2274 stats->ipackets = hw_stats->rx_packets; 2275 stats->ibytes = hw_stats->rx_bytes; 2276 stats->opackets = hw_stats->tx_packets; 2277 stats->obytes = hw_stats->tx_bytes; 2278 2279 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets)); 2280 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets)); 2281 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes)); 2282 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes)); 2283 memset(&stats->q_errors, 0, sizeof(stats->q_errors)); 2284 for (i = 0; i < TXGBE_MAX_QP; i++) { 2285 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG; 2286 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8; 2287 uint32_t q_map; 2288 2289 q_map = (stat_mappings->rqsm[n] >> offset) 2290 & QMAP_FIELD_RESERVED_BITS_MASK; 2291 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2292 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2293 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets; 2294 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes; 2295 2296 q_map = (stat_mappings->tqsm[n] >> offset) 2297 & QMAP_FIELD_RESERVED_BITS_MASK; 2298 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2299 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2300 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets; 2301 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes; 2302 } 2303 2304 /* Rx Errors */ 2305 stats->imissed = hw_stats->rx_total_missed_packets + 2306 hw_stats->rx_dma_drop; 2307 stats->ierrors = hw_stats->rx_crc_errors + 2308 hw_stats->rx_mac_short_packet_dropped + 2309 hw_stats->rx_length_errors + 2310 hw_stats->rx_undersize_errors + 2311 hw_stats->rx_oversize_errors + 2312 hw_stats->rx_drop_packets + 2313 hw_stats->rx_illegal_byte_errors + 2314 hw_stats->rx_error_bytes + 2315 hw_stats->rx_fragment_errors + 2316 hw_stats->rx_fcoe_crc_errors + 2317 hw_stats->rx_fcoe_mbuf_allocation_errors; 2318 2319 /* Tx Errors */ 2320 stats->oerrors = 0; 2321 return 0; 2322 } 2323 2324 static int 2325 txgbe_dev_stats_reset(struct rte_eth_dev *dev) 2326 { 2327 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2328 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2329 2330 /* HW registers are cleared on read */ 2331 hw->offset_loaded = 0; 2332 txgbe_dev_stats_get(dev, NULL); 2333 hw->offset_loaded = 1; 2334 2335 /* Reset software totals */ 2336 memset(hw_stats, 0, sizeof(*hw_stats)); 2337 2338 return 0; 2339 } 2340 2341 /* This function calculates the number of xstats based on the current config */ 2342 static unsigned 2343 txgbe_xstats_calc_num(struct rte_eth_dev *dev) 2344 { 2345 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues); 2346 return TXGBE_NB_HW_STATS + 2347 TXGBE_NB_UP_STATS * TXGBE_MAX_UP + 2348 TXGBE_NB_QP_STATS * nb_queues; 2349 } 2350 2351 static inline int 2352 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size) 2353 { 2354 int nb, st; 2355 2356 /* Extended stats from txgbe_hw_stats */ 2357 if (id < TXGBE_NB_HW_STATS) { 2358 snprintf(name, size, "[hw]%s", 2359 rte_txgbe_stats_strings[id].name); 2360 return 0; 2361 } 2362 id -= TXGBE_NB_HW_STATS; 2363 2364 /* Priority Stats */ 2365 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2366 nb = id / TXGBE_NB_UP_STATS; 2367 st = id % TXGBE_NB_UP_STATS; 2368 snprintf(name, size, "[p%u]%s", nb, 2369 rte_txgbe_up_strings[st].name); 2370 return 0; 2371 } 2372 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2373 2374 /* Queue Stats */ 2375 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2376 nb = id / TXGBE_NB_QP_STATS; 2377 st = id % TXGBE_NB_QP_STATS; 2378 snprintf(name, size, "[q%u]%s", nb, 2379 rte_txgbe_qp_strings[st].name); 2380 return 0; 2381 } 2382 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP; 2383 2384 return -(int)(id + 1); 2385 } 2386 2387 static inline int 2388 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset) 2389 { 2390 int nb, st; 2391 2392 /* Extended stats from txgbe_hw_stats */ 2393 if (id < TXGBE_NB_HW_STATS) { 2394 *offset = rte_txgbe_stats_strings[id].offset; 2395 return 0; 2396 } 2397 id -= TXGBE_NB_HW_STATS; 2398 2399 /* Priority Stats */ 2400 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2401 nb = id / TXGBE_NB_UP_STATS; 2402 st = id % TXGBE_NB_UP_STATS; 2403 *offset = rte_txgbe_up_strings[st].offset + 2404 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t)); 2405 return 0; 2406 } 2407 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2408 2409 /* Queue Stats */ 2410 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2411 nb = id / TXGBE_NB_QP_STATS; 2412 st = id % TXGBE_NB_QP_STATS; 2413 *offset = rte_txgbe_qp_strings[st].offset + 2414 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t)); 2415 return 0; 2416 } 2417 2418 return -1; 2419 } 2420 2421 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 2422 struct rte_eth_xstat_name *xstats_names, unsigned int limit) 2423 { 2424 unsigned int i, count; 2425 2426 count = txgbe_xstats_calc_num(dev); 2427 if (xstats_names == NULL) 2428 return count; 2429 2430 /* Note: limit >= cnt_stats checked upstream 2431 * in rte_eth_xstats_names() 2432 */ 2433 limit = min(limit, count); 2434 2435 /* Extended stats from txgbe_hw_stats */ 2436 for (i = 0; i < limit; i++) { 2437 if (txgbe_get_name_by_id(i, xstats_names[i].name, 2438 sizeof(xstats_names[i].name))) { 2439 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2440 break; 2441 } 2442 } 2443 2444 return i; 2445 } 2446 2447 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 2448 struct rte_eth_xstat_name *xstats_names, 2449 const uint64_t *ids, 2450 unsigned int limit) 2451 { 2452 unsigned int i; 2453 2454 if (ids == NULL) 2455 return txgbe_dev_xstats_get_names(dev, xstats_names, limit); 2456 2457 for (i = 0; i < limit; i++) { 2458 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name, 2459 sizeof(xstats_names[i].name))) { 2460 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2461 return -1; 2462 } 2463 } 2464 2465 return i; 2466 } 2467 2468 static int 2469 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 2470 unsigned int limit) 2471 { 2472 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2473 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2474 unsigned int i, count; 2475 2476 txgbe_read_stats_registers(hw, hw_stats); 2477 2478 /* If this is a reset xstats is NULL, and we have cleared the 2479 * registers by reading them. 2480 */ 2481 count = txgbe_xstats_calc_num(dev); 2482 if (xstats == NULL) 2483 return count; 2484 2485 limit = min(limit, txgbe_xstats_calc_num(dev)); 2486 2487 /* Extended stats from txgbe_hw_stats */ 2488 for (i = 0; i < limit; i++) { 2489 uint32_t offset = 0; 2490 2491 if (txgbe_get_offset_by_id(i, &offset)) { 2492 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2493 break; 2494 } 2495 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset); 2496 xstats[i].id = i; 2497 } 2498 2499 return i; 2500 } 2501 2502 static int 2503 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values, 2504 unsigned int limit) 2505 { 2506 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2507 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2508 unsigned int i, count; 2509 2510 txgbe_read_stats_registers(hw, hw_stats); 2511 2512 /* If this is a reset xstats is NULL, and we have cleared the 2513 * registers by reading them. 2514 */ 2515 count = txgbe_xstats_calc_num(dev); 2516 if (values == NULL) 2517 return count; 2518 2519 limit = min(limit, txgbe_xstats_calc_num(dev)); 2520 2521 /* Extended stats from txgbe_hw_stats */ 2522 for (i = 0; i < limit; i++) { 2523 uint32_t offset; 2524 2525 if (txgbe_get_offset_by_id(i, &offset)) { 2526 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2527 break; 2528 } 2529 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2530 } 2531 2532 return i; 2533 } 2534 2535 static int 2536 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 2537 uint64_t *values, unsigned int limit) 2538 { 2539 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2540 unsigned int i; 2541 2542 if (ids == NULL) 2543 return txgbe_dev_xstats_get_(dev, values, limit); 2544 2545 for (i = 0; i < limit; i++) { 2546 uint32_t offset; 2547 2548 if (txgbe_get_offset_by_id(ids[i], &offset)) { 2549 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2550 break; 2551 } 2552 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2553 } 2554 2555 return i; 2556 } 2557 2558 static int 2559 txgbe_dev_xstats_reset(struct rte_eth_dev *dev) 2560 { 2561 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2562 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2563 2564 /* HW registers are cleared on read */ 2565 hw->offset_loaded = 0; 2566 txgbe_read_stats_registers(hw, hw_stats); 2567 hw->offset_loaded = 1; 2568 2569 /* Reset software totals */ 2570 memset(hw_stats, 0, sizeof(*hw_stats)); 2571 2572 return 0; 2573 } 2574 2575 static int 2576 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2577 { 2578 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2579 u32 etrack_id; 2580 int ret; 2581 2582 hw->phy.get_fw_version(hw, &etrack_id); 2583 2584 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 2585 if (ret < 0) 2586 return -EINVAL; 2587 2588 ret += 1; /* add the size of '\0' */ 2589 if (fw_size < (size_t)ret) 2590 return ret; 2591 else 2592 return 0; 2593 } 2594 2595 static int 2596 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2597 { 2598 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2599 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2600 2601 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 2602 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 2603 dev_info->min_rx_bufsize = 1024; 2604 dev_info->max_rx_pktlen = 15872; 2605 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 2606 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC; 2607 dev_info->max_vfs = pci_dev->max_vfs; 2608 dev_info->max_vmdq_pools = ETH_64_POOLS; 2609 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 2610 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev); 2611 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) | 2612 dev_info->rx_queue_offload_capa); 2613 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev); 2614 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev); 2615 2616 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2617 .rx_thresh = { 2618 .pthresh = TXGBE_DEFAULT_RX_PTHRESH, 2619 .hthresh = TXGBE_DEFAULT_RX_HTHRESH, 2620 .wthresh = TXGBE_DEFAULT_RX_WTHRESH, 2621 }, 2622 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH, 2623 .rx_drop_en = 0, 2624 .offloads = 0, 2625 }; 2626 2627 dev_info->default_txconf = (struct rte_eth_txconf) { 2628 .tx_thresh = { 2629 .pthresh = TXGBE_DEFAULT_TX_PTHRESH, 2630 .hthresh = TXGBE_DEFAULT_TX_HTHRESH, 2631 .wthresh = TXGBE_DEFAULT_TX_WTHRESH, 2632 }, 2633 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH, 2634 .offloads = 0, 2635 }; 2636 2637 dev_info->rx_desc_lim = rx_desc_lim; 2638 dev_info->tx_desc_lim = tx_desc_lim; 2639 2640 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 2641 dev_info->reta_size = ETH_RSS_RETA_SIZE_128; 2642 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL; 2643 2644 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 2645 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 2646 2647 /* Driver-preferred Rx/Tx parameters */ 2648 dev_info->default_rxportconf.burst_size = 32; 2649 dev_info->default_txportconf.burst_size = 32; 2650 dev_info->default_rxportconf.nb_queues = 1; 2651 dev_info->default_txportconf.nb_queues = 1; 2652 dev_info->default_rxportconf.ring_size = 256; 2653 dev_info->default_txportconf.ring_size = 256; 2654 2655 return 0; 2656 } 2657 2658 const uint32_t * 2659 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 2660 { 2661 if (dev->rx_pkt_burst == txgbe_recv_pkts || 2662 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc || 2663 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc || 2664 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc) 2665 return txgbe_get_supported_ptypes(); 2666 2667 return NULL; 2668 } 2669 2670 void 2671 txgbe_dev_setup_link_alarm_handler(void *param) 2672 { 2673 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 2674 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2675 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2676 u32 speed; 2677 bool autoneg = false; 2678 2679 speed = hw->phy.autoneg_advertised; 2680 if (!speed) 2681 hw->mac.get_link_capabilities(hw, &speed, &autoneg); 2682 2683 hw->mac.setup_link(hw, speed, true); 2684 2685 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2686 } 2687 2688 /* return 0 means link status changed, -1 means not changed */ 2689 int 2690 txgbe_dev_link_update_share(struct rte_eth_dev *dev, 2691 int wait_to_complete) 2692 { 2693 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2694 struct rte_eth_link link; 2695 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; 2696 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2697 bool link_up; 2698 int err; 2699 int wait = 1; 2700 2701 memset(&link, 0, sizeof(link)); 2702 link.link_status = ETH_LINK_DOWN; 2703 link.link_speed = ETH_SPEED_NUM_NONE; 2704 link.link_duplex = ETH_LINK_HALF_DUPLEX; 2705 link.link_autoneg = ETH_LINK_AUTONEG; 2706 2707 hw->mac.get_link_status = true; 2708 2709 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG) 2710 return rte_eth_linkstatus_set(dev, &link); 2711 2712 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 2713 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 2714 wait = 0; 2715 2716 err = hw->mac.check_link(hw, &link_speed, &link_up, wait); 2717 2718 if (err != 0) { 2719 link.link_speed = ETH_SPEED_NUM_100M; 2720 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2721 return rte_eth_linkstatus_set(dev, &link); 2722 } 2723 2724 if (link_up == 0) { 2725 if ((hw->subsystem_device_id & 0xFF) == 2726 TXGBE_DEV_ID_KR_KX_KX4) { 2727 hw->mac.bp_down_event(hw); 2728 } else if (hw->phy.media_type == txgbe_media_type_fiber) { 2729 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG; 2730 rte_eal_alarm_set(10, 2731 txgbe_dev_setup_link_alarm_handler, dev); 2732 } 2733 return rte_eth_linkstatus_set(dev, &link); 2734 } 2735 2736 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2737 link.link_status = ETH_LINK_UP; 2738 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2739 2740 switch (link_speed) { 2741 default: 2742 case TXGBE_LINK_SPEED_UNKNOWN: 2743 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2744 link.link_speed = ETH_SPEED_NUM_100M; 2745 break; 2746 2747 case TXGBE_LINK_SPEED_100M_FULL: 2748 link.link_speed = ETH_SPEED_NUM_100M; 2749 break; 2750 2751 case TXGBE_LINK_SPEED_1GB_FULL: 2752 link.link_speed = ETH_SPEED_NUM_1G; 2753 break; 2754 2755 case TXGBE_LINK_SPEED_2_5GB_FULL: 2756 link.link_speed = ETH_SPEED_NUM_2_5G; 2757 break; 2758 2759 case TXGBE_LINK_SPEED_5GB_FULL: 2760 link.link_speed = ETH_SPEED_NUM_5G; 2761 break; 2762 2763 case TXGBE_LINK_SPEED_10GB_FULL: 2764 link.link_speed = ETH_SPEED_NUM_10G; 2765 break; 2766 } 2767 2768 return rte_eth_linkstatus_set(dev, &link); 2769 } 2770 2771 static int 2772 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 2773 { 2774 return txgbe_dev_link_update_share(dev, wait_to_complete); 2775 } 2776 2777 static int 2778 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 2779 { 2780 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2781 uint32_t fctrl; 2782 2783 fctrl = rd32(hw, TXGBE_PSRCTL); 2784 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP); 2785 wr32(hw, TXGBE_PSRCTL, fctrl); 2786 2787 return 0; 2788 } 2789 2790 static int 2791 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 2792 { 2793 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2794 uint32_t fctrl; 2795 2796 fctrl = rd32(hw, TXGBE_PSRCTL); 2797 fctrl &= (~TXGBE_PSRCTL_UCP); 2798 if (dev->data->all_multicast == 1) 2799 fctrl |= TXGBE_PSRCTL_MCP; 2800 else 2801 fctrl &= (~TXGBE_PSRCTL_MCP); 2802 wr32(hw, TXGBE_PSRCTL, fctrl); 2803 2804 return 0; 2805 } 2806 2807 static int 2808 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 2809 { 2810 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2811 uint32_t fctrl; 2812 2813 fctrl = rd32(hw, TXGBE_PSRCTL); 2814 fctrl |= TXGBE_PSRCTL_MCP; 2815 wr32(hw, TXGBE_PSRCTL, fctrl); 2816 2817 return 0; 2818 } 2819 2820 static int 2821 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 2822 { 2823 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2824 uint32_t fctrl; 2825 2826 if (dev->data->promiscuous == 1) 2827 return 0; /* must remain in all_multicast mode */ 2828 2829 fctrl = rd32(hw, TXGBE_PSRCTL); 2830 fctrl &= (~TXGBE_PSRCTL_MCP); 2831 wr32(hw, TXGBE_PSRCTL, fctrl); 2832 2833 return 0; 2834 } 2835 2836 /** 2837 * It clears the interrupt causes and enables the interrupt. 2838 * It will be called once only during nic initialized. 2839 * 2840 * @param dev 2841 * Pointer to struct rte_eth_dev. 2842 * @param on 2843 * Enable or Disable. 2844 * 2845 * @return 2846 * - On success, zero. 2847 * - On failure, a negative value. 2848 */ 2849 static int 2850 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 2851 { 2852 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2853 2854 txgbe_dev_link_status_print(dev); 2855 if (on) 2856 intr->mask_misc |= TXGBE_ICRMISC_LSC; 2857 else 2858 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 2859 2860 return 0; 2861 } 2862 2863 static int 2864 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev) 2865 { 2866 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2867 u64 mask; 2868 2869 mask = TXGBE_ICR_MASK; 2870 mask &= (1ULL << TXGBE_MISC_VEC_ID); 2871 intr->mask |= mask; 2872 intr->mask_misc |= TXGBE_ICRMISC_GPIO; 2873 intr->mask_misc |= TXGBE_ICRMISC_ANDONE; 2874 return 0; 2875 } 2876 2877 /** 2878 * It clears the interrupt causes and enables the interrupt. 2879 * It will be called once only during nic initialized. 2880 * 2881 * @param dev 2882 * Pointer to struct rte_eth_dev. 2883 * 2884 * @return 2885 * - On success, zero. 2886 * - On failure, a negative value. 2887 */ 2888 static int 2889 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 2890 { 2891 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2892 u64 mask; 2893 2894 mask = TXGBE_ICR_MASK; 2895 mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1); 2896 intr->mask |= mask; 2897 2898 return 0; 2899 } 2900 2901 /** 2902 * It clears the interrupt causes and enables the interrupt. 2903 * It will be called once only during nic initialized. 2904 * 2905 * @param dev 2906 * Pointer to struct rte_eth_dev. 2907 * 2908 * @return 2909 * - On success, zero. 2910 * - On failure, a negative value. 2911 */ 2912 static int 2913 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 2914 { 2915 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2916 2917 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC; 2918 2919 return 0; 2920 } 2921 2922 /* 2923 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update. 2924 * 2925 * @param dev 2926 * Pointer to struct rte_eth_dev. 2927 * 2928 * @return 2929 * - On success, zero. 2930 * - On failure, a negative value. 2931 */ 2932 static int 2933 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 2934 { 2935 uint32_t eicr; 2936 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2937 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2938 2939 /* clear all cause mask */ 2940 txgbe_disable_intr(hw); 2941 2942 /* read-on-clear nic registers here */ 2943 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 2944 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 2945 2946 intr->flags = 0; 2947 2948 /* set flag for async link update */ 2949 if (eicr & TXGBE_ICRMISC_LSC) 2950 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 2951 2952 if (eicr & TXGBE_ICRMISC_ANDONE) 2953 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG; 2954 2955 if (eicr & TXGBE_ICRMISC_VFMBX) 2956 intr->flags |= TXGBE_FLAG_MAILBOX; 2957 2958 if (eicr & TXGBE_ICRMISC_LNKSEC) 2959 intr->flags |= TXGBE_FLAG_MACSEC; 2960 2961 if (eicr & TXGBE_ICRMISC_GPIO) 2962 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT; 2963 2964 return 0; 2965 } 2966 2967 /** 2968 * It gets and then prints the link status. 2969 * 2970 * @param dev 2971 * Pointer to struct rte_eth_dev. 2972 * 2973 * @return 2974 * - On success, zero. 2975 * - On failure, a negative value. 2976 */ 2977 static void 2978 txgbe_dev_link_status_print(struct rte_eth_dev *dev) 2979 { 2980 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2981 struct rte_eth_link link; 2982 2983 rte_eth_linkstatus_get(dev, &link); 2984 2985 if (link.link_status) { 2986 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 2987 (int)(dev->data->port_id), 2988 (unsigned int)link.link_speed, 2989 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 2990 "full-duplex" : "half-duplex"); 2991 } else { 2992 PMD_INIT_LOG(INFO, " Port %d: Link Down", 2993 (int)(dev->data->port_id)); 2994 } 2995 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 2996 pci_dev->addr.domain, 2997 pci_dev->addr.bus, 2998 pci_dev->addr.devid, 2999 pci_dev->addr.function); 3000 } 3001 3002 /* 3003 * It executes link_update after knowing an interrupt occurred. 3004 * 3005 * @param dev 3006 * Pointer to struct rte_eth_dev. 3007 * 3008 * @return 3009 * - On success, zero. 3010 * - On failure, a negative value. 3011 */ 3012 static int 3013 txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 3014 struct rte_intr_handle *intr_handle) 3015 { 3016 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 3017 int64_t timeout; 3018 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3019 3020 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 3021 3022 if (intr->flags & TXGBE_FLAG_MAILBOX) { 3023 txgbe_pf_mbx_process(dev); 3024 intr->flags &= ~TXGBE_FLAG_MAILBOX; 3025 } 3026 3027 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 3028 hw->phy.handle_lasi(hw); 3029 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 3030 } 3031 3032 if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) { 3033 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) { 3034 hw->mac.kr_handle(hw); 3035 intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG; 3036 } 3037 } 3038 3039 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 3040 struct rte_eth_link link; 3041 3042 /*get the link status before link update, for predicting later*/ 3043 rte_eth_linkstatus_get(dev, &link); 3044 3045 txgbe_dev_link_update(dev, 0); 3046 3047 /* likely to up */ 3048 if (!link.link_status) 3049 /* handle it 1 sec later, wait it being stable */ 3050 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT; 3051 /* likely to down */ 3052 else if ((hw->subsystem_device_id & 0xFF) == 3053 TXGBE_DEV_ID_KR_KX_KX4 && 3054 hw->devarg.auto_neg == 1) 3055 /* handle it 2 sec later for backplane AN73 */ 3056 timeout = 2000; 3057 else 3058 /* handle it 4 sec later, wait it being stable */ 3059 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT; 3060 3061 txgbe_dev_link_status_print(dev); 3062 if (rte_eal_alarm_set(timeout * 1000, 3063 txgbe_dev_interrupt_delayed_handler, 3064 (void *)dev) < 0) { 3065 PMD_DRV_LOG(ERR, "Error setting alarm"); 3066 } else { 3067 /* only disable lsc interrupt */ 3068 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 3069 3070 intr->mask_orig = intr->mask; 3071 /* only disable all misc interrupts */ 3072 intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID); 3073 } 3074 } 3075 3076 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 3077 txgbe_enable_intr(dev); 3078 rte_intr_enable(intr_handle); 3079 3080 return 0; 3081 } 3082 3083 /** 3084 * Interrupt handler which shall be registered for alarm callback for delayed 3085 * handling specific interrupt to wait for the stable nic state. As the 3086 * NIC interrupt state is not stable for txgbe after link is just down, 3087 * it needs to wait 4 seconds to get the stable status. 3088 * 3089 * @param handle 3090 * Pointer to interrupt handle. 3091 * @param param 3092 * The address of parameter (struct rte_eth_dev *) registered before. 3093 * 3094 * @return 3095 * void 3096 */ 3097 static void 3098 txgbe_dev_interrupt_delayed_handler(void *param) 3099 { 3100 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3101 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3102 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3103 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 3104 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3105 uint32_t eicr; 3106 3107 txgbe_disable_intr(hw); 3108 3109 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 3110 if (eicr & TXGBE_ICRMISC_VFMBX) 3111 txgbe_pf_mbx_process(dev); 3112 3113 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 3114 hw->phy.handle_lasi(hw); 3115 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 3116 } 3117 3118 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 3119 txgbe_dev_link_update(dev, 0); 3120 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE; 3121 txgbe_dev_link_status_print(dev); 3122 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 3123 NULL); 3124 } 3125 3126 if (intr->flags & TXGBE_FLAG_MACSEC) { 3127 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 3128 NULL); 3129 intr->flags &= ~TXGBE_FLAG_MACSEC; 3130 } 3131 3132 /* restore original mask */ 3133 intr->mask_misc |= TXGBE_ICRMISC_LSC; 3134 3135 intr->mask = intr->mask_orig; 3136 intr->mask_orig = 0; 3137 3138 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 3139 txgbe_enable_intr(dev); 3140 rte_intr_enable(intr_handle); 3141 } 3142 3143 /** 3144 * Interrupt handler triggered by NIC for handling 3145 * specific interrupt. 3146 * 3147 * @param handle 3148 * Pointer to interrupt handle. 3149 * @param param 3150 * The address of parameter (struct rte_eth_dev *) registered before. 3151 * 3152 * @return 3153 * void 3154 */ 3155 static void 3156 txgbe_dev_interrupt_handler(void *param) 3157 { 3158 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3159 3160 txgbe_dev_interrupt_get_status(dev); 3161 txgbe_dev_interrupt_action(dev, dev->intr_handle); 3162 } 3163 3164 static int 3165 txgbe_dev_led_on(struct rte_eth_dev *dev) 3166 { 3167 struct txgbe_hw *hw; 3168 3169 hw = TXGBE_DEV_HW(dev); 3170 return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP; 3171 } 3172 3173 static int 3174 txgbe_dev_led_off(struct rte_eth_dev *dev) 3175 { 3176 struct txgbe_hw *hw; 3177 3178 hw = TXGBE_DEV_HW(dev); 3179 return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP; 3180 } 3181 3182 static int 3183 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3184 { 3185 struct txgbe_hw *hw; 3186 uint32_t mflcn_reg; 3187 uint32_t fccfg_reg; 3188 int rx_pause; 3189 int tx_pause; 3190 3191 hw = TXGBE_DEV_HW(dev); 3192 3193 fc_conf->pause_time = hw->fc.pause_time; 3194 fc_conf->high_water = hw->fc.high_water[0]; 3195 fc_conf->low_water = hw->fc.low_water[0]; 3196 fc_conf->send_xon = hw->fc.send_xon; 3197 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 3198 3199 /* 3200 * Return rx_pause status according to actual setting of 3201 * RXFCCFG register. 3202 */ 3203 mflcn_reg = rd32(hw, TXGBE_RXFCCFG); 3204 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC)) 3205 rx_pause = 1; 3206 else 3207 rx_pause = 0; 3208 3209 /* 3210 * Return tx_pause status according to actual setting of 3211 * TXFCCFG register. 3212 */ 3213 fccfg_reg = rd32(hw, TXGBE_TXFCCFG); 3214 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC)) 3215 tx_pause = 1; 3216 else 3217 tx_pause = 0; 3218 3219 if (rx_pause && tx_pause) 3220 fc_conf->mode = RTE_FC_FULL; 3221 else if (rx_pause) 3222 fc_conf->mode = RTE_FC_RX_PAUSE; 3223 else if (tx_pause) 3224 fc_conf->mode = RTE_FC_TX_PAUSE; 3225 else 3226 fc_conf->mode = RTE_FC_NONE; 3227 3228 return 0; 3229 } 3230 3231 static int 3232 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3233 { 3234 struct txgbe_hw *hw; 3235 int err; 3236 uint32_t rx_buf_size; 3237 uint32_t max_high_water; 3238 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3239 txgbe_fc_none, 3240 txgbe_fc_rx_pause, 3241 txgbe_fc_tx_pause, 3242 txgbe_fc_full 3243 }; 3244 3245 PMD_INIT_FUNC_TRACE(); 3246 3247 hw = TXGBE_DEV_HW(dev); 3248 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0)); 3249 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3250 3251 /* 3252 * At least reserve one Ethernet frame for watermark 3253 * high_water/low_water in kilo bytes for txgbe 3254 */ 3255 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3256 if (fc_conf->high_water > max_high_water || 3257 fc_conf->high_water < fc_conf->low_water) { 3258 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3259 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3260 return -EINVAL; 3261 } 3262 3263 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode]; 3264 hw->fc.pause_time = fc_conf->pause_time; 3265 hw->fc.high_water[0] = fc_conf->high_water; 3266 hw->fc.low_water[0] = fc_conf->low_water; 3267 hw->fc.send_xon = fc_conf->send_xon; 3268 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 3269 3270 err = txgbe_fc_enable(hw); 3271 3272 /* Not negotiated is not an error case */ 3273 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) { 3274 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK, 3275 (fc_conf->mac_ctrl_frame_fwd 3276 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP)); 3277 txgbe_flush(hw); 3278 3279 return 0; 3280 } 3281 3282 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err); 3283 return -EIO; 3284 } 3285 3286 static int 3287 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 3288 struct rte_eth_pfc_conf *pfc_conf) 3289 { 3290 int err; 3291 uint32_t rx_buf_size; 3292 uint32_t max_high_water; 3293 uint8_t tc_num; 3294 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 }; 3295 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3296 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 3297 3298 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3299 txgbe_fc_none, 3300 txgbe_fc_rx_pause, 3301 txgbe_fc_tx_pause, 3302 txgbe_fc_full 3303 }; 3304 3305 PMD_INIT_FUNC_TRACE(); 3306 3307 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map); 3308 tc_num = map[pfc_conf->priority]; 3309 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num)); 3310 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3311 /* 3312 * At least reserve one Ethernet frame for watermark 3313 * high_water/low_water in kilo bytes for txgbe 3314 */ 3315 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3316 if (pfc_conf->fc.high_water > max_high_water || 3317 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) { 3318 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3319 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3320 return -EINVAL; 3321 } 3322 3323 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode]; 3324 hw->fc.pause_time = pfc_conf->fc.pause_time; 3325 hw->fc.send_xon = pfc_conf->fc.send_xon; 3326 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 3327 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 3328 3329 err = txgbe_dcb_pfc_enable(hw, tc_num); 3330 3331 /* Not negotiated is not an error case */ 3332 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) 3333 return 0; 3334 3335 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err); 3336 return -EIO; 3337 } 3338 3339 int 3340 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 3341 struct rte_eth_rss_reta_entry64 *reta_conf, 3342 uint16_t reta_size) 3343 { 3344 uint8_t i, j, mask; 3345 uint32_t reta; 3346 uint16_t idx, shift; 3347 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 3348 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3349 3350 PMD_INIT_FUNC_TRACE(); 3351 3352 if (!txgbe_rss_update_sp(hw->mac.type)) { 3353 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 3354 "NIC."); 3355 return -ENOTSUP; 3356 } 3357 3358 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3359 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3360 "(%d) doesn't match the number hardware can supported " 3361 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3362 return -EINVAL; 3363 } 3364 3365 for (i = 0; i < reta_size; i += 4) { 3366 idx = i / RTE_RETA_GROUP_SIZE; 3367 shift = i % RTE_RETA_GROUP_SIZE; 3368 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3369 if (!mask) 3370 continue; 3371 3372 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3373 for (j = 0; j < 4; j++) { 3374 if (RS8(mask, j, 0x1)) { 3375 reta &= ~(MS32(8 * j, 0xFF)); 3376 reta |= LS32(reta_conf[idx].reta[shift + j], 3377 8 * j, 0xFF); 3378 } 3379 } 3380 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta); 3381 } 3382 adapter->rss_reta_updated = 1; 3383 3384 return 0; 3385 } 3386 3387 int 3388 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 3389 struct rte_eth_rss_reta_entry64 *reta_conf, 3390 uint16_t reta_size) 3391 { 3392 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3393 uint8_t i, j, mask; 3394 uint32_t reta; 3395 uint16_t idx, shift; 3396 3397 PMD_INIT_FUNC_TRACE(); 3398 3399 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3400 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3401 "(%d) doesn't match the number hardware can supported " 3402 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3403 return -EINVAL; 3404 } 3405 3406 for (i = 0; i < reta_size; i += 4) { 3407 idx = i / RTE_RETA_GROUP_SIZE; 3408 shift = i % RTE_RETA_GROUP_SIZE; 3409 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3410 if (!mask) 3411 continue; 3412 3413 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3414 for (j = 0; j < 4; j++) { 3415 if (RS8(mask, j, 0x1)) 3416 reta_conf[idx].reta[shift + j] = 3417 (uint16_t)RS32(reta, 8 * j, 0xFF); 3418 } 3419 } 3420 3421 return 0; 3422 } 3423 3424 static int 3425 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 3426 uint32_t index, uint32_t pool) 3427 { 3428 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3429 uint32_t enable_addr = 1; 3430 3431 return txgbe_set_rar(hw, index, mac_addr->addr_bytes, 3432 pool, enable_addr); 3433 } 3434 3435 static void 3436 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 3437 { 3438 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3439 3440 txgbe_clear_rar(hw, index); 3441 } 3442 3443 static int 3444 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 3445 { 3446 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3447 3448 txgbe_remove_rar(dev, 0); 3449 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 3450 3451 return 0; 3452 } 3453 3454 static int 3455 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3456 { 3457 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3458 struct rte_eth_dev_info dev_info; 3459 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 3460 struct rte_eth_dev_data *dev_data = dev->data; 3461 int ret; 3462 3463 ret = txgbe_dev_info_get(dev, &dev_info); 3464 if (ret != 0) 3465 return ret; 3466 3467 /* check that mtu is within the allowed range */ 3468 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 3469 return -EINVAL; 3470 3471 /* If device is started, refuse mtu that requires the support of 3472 * scattered packets when this feature has not been enabled before. 3473 */ 3474 if (dev_data->dev_started && !dev_data->scattered_rx && 3475 (frame_size + 2 * TXGBE_VLAN_TAG_SIZE > 3476 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 3477 PMD_INIT_LOG(ERR, "Stop port first."); 3478 return -EINVAL; 3479 } 3480 3481 /* update max frame size */ 3482 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 3483 3484 if (hw->mode) 3485 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3486 TXGBE_FRAME_SIZE_MAX); 3487 else 3488 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3489 TXGBE_FRMSZ_MAX(frame_size)); 3490 3491 return 0; 3492 } 3493 3494 static uint32_t 3495 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr) 3496 { 3497 uint32_t vector = 0; 3498 3499 switch (hw->mac.mc_filter_type) { 3500 case 0: /* use bits [47:36] of the address */ 3501 vector = ((uc_addr->addr_bytes[4] >> 4) | 3502 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 3503 break; 3504 case 1: /* use bits [46:35] of the address */ 3505 vector = ((uc_addr->addr_bytes[4] >> 3) | 3506 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 3507 break; 3508 case 2: /* use bits [45:34] of the address */ 3509 vector = ((uc_addr->addr_bytes[4] >> 2) | 3510 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 3511 break; 3512 case 3: /* use bits [43:32] of the address */ 3513 vector = ((uc_addr->addr_bytes[4]) | 3514 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 3515 break; 3516 default: /* Invalid mc_filter_type */ 3517 break; 3518 } 3519 3520 /* vector can only be 12-bits or boundary will be exceeded */ 3521 vector &= 0xFFF; 3522 return vector; 3523 } 3524 3525 static int 3526 txgbe_uc_hash_table_set(struct rte_eth_dev *dev, 3527 struct rte_ether_addr *mac_addr, uint8_t on) 3528 { 3529 uint32_t vector; 3530 uint32_t uta_idx; 3531 uint32_t reg_val; 3532 uint32_t uta_mask; 3533 uint32_t psrctl; 3534 3535 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3536 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3537 3538 /* The UTA table only exists on pf hardware */ 3539 if (hw->mac.type < txgbe_mac_raptor) 3540 return -ENOTSUP; 3541 3542 vector = txgbe_uta_vector(hw, mac_addr); 3543 uta_idx = (vector >> 5) & 0x7F; 3544 uta_mask = 0x1UL << (vector & 0x1F); 3545 3546 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask)) 3547 return 0; 3548 3549 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx)); 3550 if (on) { 3551 uta_info->uta_in_use++; 3552 reg_val |= uta_mask; 3553 uta_info->uta_shadow[uta_idx] |= uta_mask; 3554 } else { 3555 uta_info->uta_in_use--; 3556 reg_val &= ~uta_mask; 3557 uta_info->uta_shadow[uta_idx] &= ~uta_mask; 3558 } 3559 3560 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val); 3561 3562 psrctl = rd32(hw, TXGBE_PSRCTL); 3563 if (uta_info->uta_in_use > 0) 3564 psrctl |= TXGBE_PSRCTL_UCHFENA; 3565 else 3566 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3567 3568 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3569 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3570 wr32(hw, TXGBE_PSRCTL, psrctl); 3571 3572 return 0; 3573 } 3574 3575 static int 3576 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 3577 { 3578 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3579 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3580 uint32_t psrctl; 3581 int i; 3582 3583 /* The UTA table only exists on pf hardware */ 3584 if (hw->mac.type < txgbe_mac_raptor) 3585 return -ENOTSUP; 3586 3587 if (on) { 3588 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3589 uta_info->uta_shadow[i] = ~0; 3590 wr32(hw, TXGBE_UCADDRTBL(i), ~0); 3591 } 3592 } else { 3593 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3594 uta_info->uta_shadow[i] = 0; 3595 wr32(hw, TXGBE_UCADDRTBL(i), 0); 3596 } 3597 } 3598 3599 psrctl = rd32(hw, TXGBE_PSRCTL); 3600 if (on) 3601 psrctl |= TXGBE_PSRCTL_UCHFENA; 3602 else 3603 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3604 3605 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3606 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3607 wr32(hw, TXGBE_PSRCTL, psrctl); 3608 3609 return 0; 3610 } 3611 3612 uint32_t 3613 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 3614 { 3615 uint32_t new_val = orig_val; 3616 3617 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 3618 new_val |= TXGBE_POOLETHCTL_UTA; 3619 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 3620 new_val |= TXGBE_POOLETHCTL_MCHA; 3621 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 3622 new_val |= TXGBE_POOLETHCTL_UCHA; 3623 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 3624 new_val |= TXGBE_POOLETHCTL_BCA; 3625 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 3626 new_val |= TXGBE_POOLETHCTL_MCP; 3627 3628 return new_val; 3629 } 3630 3631 static int 3632 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 3633 { 3634 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3635 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3636 uint32_t mask; 3637 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3638 3639 if (queue_id < 32) { 3640 mask = rd32(hw, TXGBE_IMS(0)); 3641 mask &= (1 << queue_id); 3642 wr32(hw, TXGBE_IMS(0), mask); 3643 } else if (queue_id < 64) { 3644 mask = rd32(hw, TXGBE_IMS(1)); 3645 mask &= (1 << (queue_id - 32)); 3646 wr32(hw, TXGBE_IMS(1), mask); 3647 } 3648 rte_intr_enable(intr_handle); 3649 3650 return 0; 3651 } 3652 3653 static int 3654 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 3655 { 3656 uint32_t mask; 3657 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3658 3659 if (queue_id < 32) { 3660 mask = rd32(hw, TXGBE_IMS(0)); 3661 mask &= ~(1 << queue_id); 3662 wr32(hw, TXGBE_IMS(0), mask); 3663 } else if (queue_id < 64) { 3664 mask = rd32(hw, TXGBE_IMS(1)); 3665 mask &= ~(1 << (queue_id - 32)); 3666 wr32(hw, TXGBE_IMS(1), mask); 3667 } 3668 3669 return 0; 3670 } 3671 3672 /** 3673 * set the IVAR registers, mapping interrupt causes to vectors 3674 * @param hw 3675 * pointer to txgbe_hw struct 3676 * @direction 3677 * 0 for Rx, 1 for Tx, -1 for other causes 3678 * @queue 3679 * queue to map the corresponding interrupt to 3680 * @msix_vector 3681 * the vector to map to the corresponding queue 3682 */ 3683 void 3684 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction, 3685 uint8_t queue, uint8_t msix_vector) 3686 { 3687 uint32_t tmp, idx; 3688 3689 if (direction == -1) { 3690 /* other causes */ 3691 msix_vector |= TXGBE_IVARMISC_VLD; 3692 idx = 0; 3693 tmp = rd32(hw, TXGBE_IVARMISC); 3694 tmp &= ~(0xFF << idx); 3695 tmp |= (msix_vector << idx); 3696 wr32(hw, TXGBE_IVARMISC, tmp); 3697 } else { 3698 /* rx or tx causes */ 3699 /* Workround for ICR lost */ 3700 idx = ((16 * (queue & 1)) + (8 * direction)); 3701 tmp = rd32(hw, TXGBE_IVAR(queue >> 1)); 3702 tmp &= ~(0xFF << idx); 3703 tmp |= (msix_vector << idx); 3704 wr32(hw, TXGBE_IVAR(queue >> 1), tmp); 3705 } 3706 } 3707 3708 /** 3709 * Sets up the hardware to properly generate MSI-X interrupts 3710 * @hw 3711 * board private structure 3712 */ 3713 static void 3714 txgbe_configure_msix(struct rte_eth_dev *dev) 3715 { 3716 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3717 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3718 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3719 uint32_t queue_id, base = TXGBE_MISC_VEC_ID; 3720 uint32_t vec = TXGBE_MISC_VEC_ID; 3721 uint32_t gpie; 3722 3723 /* won't configure msix register if no mapping is done 3724 * between intr vector and event fd 3725 * but if misx has been enabled already, need to configure 3726 * auto clean, auto mask and throttling. 3727 */ 3728 gpie = rd32(hw, TXGBE_GPIE); 3729 if (!rte_intr_dp_is_en(intr_handle) && 3730 !(gpie & TXGBE_GPIE_MSIX)) 3731 return; 3732 3733 if (rte_intr_allow_others(intr_handle)) { 3734 base = TXGBE_RX_VEC_START; 3735 vec = base; 3736 } 3737 3738 /* setup GPIE for MSI-x mode */ 3739 gpie = rd32(hw, TXGBE_GPIE); 3740 gpie |= TXGBE_GPIE_MSIX; 3741 wr32(hw, TXGBE_GPIE, gpie); 3742 3743 /* Populate the IVAR table and set the ITR values to the 3744 * corresponding register. 3745 */ 3746 if (rte_intr_dp_is_en(intr_handle)) { 3747 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 3748 queue_id++) { 3749 /* by default, 1:1 mapping */ 3750 txgbe_set_ivar_map(hw, 0, queue_id, vec); 3751 intr_handle->intr_vec[queue_id] = vec; 3752 if (vec < base + intr_handle->nb_efd - 1) 3753 vec++; 3754 } 3755 3756 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 3757 } 3758 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID), 3759 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 3760 | TXGBE_ITR_WRDSA); 3761 } 3762 3763 int 3764 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 3765 uint16_t queue_idx, uint16_t tx_rate) 3766 { 3767 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3768 uint32_t bcnrc_val; 3769 3770 if (queue_idx >= hw->mac.max_tx_queues) 3771 return -EINVAL; 3772 3773 if (tx_rate != 0) { 3774 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate); 3775 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2); 3776 } else { 3777 bcnrc_val = 0; 3778 } 3779 3780 /* 3781 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW 3782 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 3783 */ 3784 wr32(hw, TXGBE_ARBTXMMW, 0x14); 3785 3786 /* Set ARBTXRATE of queue X */ 3787 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx); 3788 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val); 3789 txgbe_flush(hw); 3790 3791 return 0; 3792 } 3793 3794 int 3795 txgbe_syn_filter_set(struct rte_eth_dev *dev, 3796 struct rte_eth_syn_filter *filter, 3797 bool add) 3798 { 3799 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3800 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3801 uint32_t syn_info; 3802 uint32_t synqf; 3803 3804 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 3805 return -EINVAL; 3806 3807 syn_info = filter_info->syn_info; 3808 3809 if (add) { 3810 if (syn_info & TXGBE_SYNCLS_ENA) 3811 return -EINVAL; 3812 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue); 3813 synqf |= TXGBE_SYNCLS_ENA; 3814 3815 if (filter->hig_pri) 3816 synqf |= TXGBE_SYNCLS_HIPRIO; 3817 else 3818 synqf &= ~TXGBE_SYNCLS_HIPRIO; 3819 } else { 3820 synqf = rd32(hw, TXGBE_SYNCLS); 3821 if (!(syn_info & TXGBE_SYNCLS_ENA)) 3822 return -ENOENT; 3823 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA); 3824 } 3825 3826 filter_info->syn_info = synqf; 3827 wr32(hw, TXGBE_SYNCLS, synqf); 3828 txgbe_flush(hw); 3829 return 0; 3830 } 3831 3832 static inline enum txgbe_5tuple_protocol 3833 convert_protocol_type(uint8_t protocol_value) 3834 { 3835 if (protocol_value == IPPROTO_TCP) 3836 return TXGBE_5TF_PROT_TCP; 3837 else if (protocol_value == IPPROTO_UDP) 3838 return TXGBE_5TF_PROT_UDP; 3839 else if (protocol_value == IPPROTO_SCTP) 3840 return TXGBE_5TF_PROT_SCTP; 3841 else 3842 return TXGBE_5TF_PROT_NONE; 3843 } 3844 3845 /* inject a 5-tuple filter to HW */ 3846 static inline void 3847 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 3848 struct txgbe_5tuple_filter *filter) 3849 { 3850 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3851 int i; 3852 uint32_t ftqf, sdpqf; 3853 uint32_t l34timir = 0; 3854 uint32_t mask = TXGBE_5TFCTL0_MASK; 3855 3856 i = filter->index; 3857 sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port)); 3858 sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port)); 3859 3860 ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto); 3861 ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority); 3862 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 3863 mask &= ~TXGBE_5TFCTL0_MSADDR; 3864 if (filter->filter_info.dst_ip_mask == 0) 3865 mask &= ~TXGBE_5TFCTL0_MDADDR; 3866 if (filter->filter_info.src_port_mask == 0) 3867 mask &= ~TXGBE_5TFCTL0_MSPORT; 3868 if (filter->filter_info.dst_port_mask == 0) 3869 mask &= ~TXGBE_5TFCTL0_MDPORT; 3870 if (filter->filter_info.proto_mask == 0) 3871 mask &= ~TXGBE_5TFCTL0_MPROTO; 3872 ftqf |= mask; 3873 ftqf |= TXGBE_5TFCTL0_MPOOL; 3874 ftqf |= TXGBE_5TFCTL0_ENA; 3875 3876 wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip)); 3877 wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip)); 3878 wr32(hw, TXGBE_5TFPORT(i), sdpqf); 3879 wr32(hw, TXGBE_5TFCTL0(i), ftqf); 3880 3881 l34timir |= TXGBE_5TFCTL1_QP(filter->queue); 3882 wr32(hw, TXGBE_5TFCTL1(i), l34timir); 3883 } 3884 3885 /* 3886 * add a 5tuple filter 3887 * 3888 * @param 3889 * dev: Pointer to struct rte_eth_dev. 3890 * index: the index the filter allocates. 3891 * filter: pointer to the filter that will be added. 3892 * rx_queue: the queue id the filter assigned to. 3893 * 3894 * @return 3895 * - On success, zero. 3896 * - On failure, a negative value. 3897 */ 3898 static int 3899 txgbe_add_5tuple_filter(struct rte_eth_dev *dev, 3900 struct txgbe_5tuple_filter *filter) 3901 { 3902 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3903 int i, idx, shift; 3904 3905 /* 3906 * look for an unused 5tuple filter index, 3907 * and insert the filter to list. 3908 */ 3909 for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) { 3910 idx = i / (sizeof(uint32_t) * NBBY); 3911 shift = i % (sizeof(uint32_t) * NBBY); 3912 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 3913 filter_info->fivetuple_mask[idx] |= 1 << shift; 3914 filter->index = i; 3915 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 3916 filter, 3917 entries); 3918 break; 3919 } 3920 } 3921 if (i >= TXGBE_MAX_FTQF_FILTERS) { 3922 PMD_DRV_LOG(ERR, "5tuple filters are full."); 3923 return -ENOSYS; 3924 } 3925 3926 txgbe_inject_5tuple_filter(dev, filter); 3927 3928 return 0; 3929 } 3930 3931 /* 3932 * remove a 5tuple filter 3933 * 3934 * @param 3935 * dev: Pointer to struct rte_eth_dev. 3936 * filter: the pointer of the filter will be removed. 3937 */ 3938 static void 3939 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 3940 struct txgbe_5tuple_filter *filter) 3941 { 3942 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3943 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3944 uint16_t index = filter->index; 3945 3946 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 3947 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 3948 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 3949 rte_free(filter); 3950 3951 wr32(hw, TXGBE_5TFDADDR(index), 0); 3952 wr32(hw, TXGBE_5TFSADDR(index), 0); 3953 wr32(hw, TXGBE_5TFPORT(index), 0); 3954 wr32(hw, TXGBE_5TFCTL0(index), 0); 3955 wr32(hw, TXGBE_5TFCTL1(index), 0); 3956 } 3957 3958 static inline struct txgbe_5tuple_filter * 3959 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list, 3960 struct txgbe_5tuple_filter_info *key) 3961 { 3962 struct txgbe_5tuple_filter *it; 3963 3964 TAILQ_FOREACH(it, filter_list, entries) { 3965 if (memcmp(key, &it->filter_info, 3966 sizeof(struct txgbe_5tuple_filter_info)) == 0) { 3967 return it; 3968 } 3969 } 3970 return NULL; 3971 } 3972 3973 /* translate elements in struct rte_eth_ntuple_filter 3974 * to struct txgbe_5tuple_filter_info 3975 */ 3976 static inline int 3977 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 3978 struct txgbe_5tuple_filter_info *filter_info) 3979 { 3980 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM || 3981 filter->priority > TXGBE_5TUPLE_MAX_PRI || 3982 filter->priority < TXGBE_5TUPLE_MIN_PRI) 3983 return -EINVAL; 3984 3985 switch (filter->dst_ip_mask) { 3986 case UINT32_MAX: 3987 filter_info->dst_ip_mask = 0; 3988 filter_info->dst_ip = filter->dst_ip; 3989 break; 3990 case 0: 3991 filter_info->dst_ip_mask = 1; 3992 break; 3993 default: 3994 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 3995 return -EINVAL; 3996 } 3997 3998 switch (filter->src_ip_mask) { 3999 case UINT32_MAX: 4000 filter_info->src_ip_mask = 0; 4001 filter_info->src_ip = filter->src_ip; 4002 break; 4003 case 0: 4004 filter_info->src_ip_mask = 1; 4005 break; 4006 default: 4007 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 4008 return -EINVAL; 4009 } 4010 4011 switch (filter->dst_port_mask) { 4012 case UINT16_MAX: 4013 filter_info->dst_port_mask = 0; 4014 filter_info->dst_port = filter->dst_port; 4015 break; 4016 case 0: 4017 filter_info->dst_port_mask = 1; 4018 break; 4019 default: 4020 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 4021 return -EINVAL; 4022 } 4023 4024 switch (filter->src_port_mask) { 4025 case UINT16_MAX: 4026 filter_info->src_port_mask = 0; 4027 filter_info->src_port = filter->src_port; 4028 break; 4029 case 0: 4030 filter_info->src_port_mask = 1; 4031 break; 4032 default: 4033 PMD_DRV_LOG(ERR, "invalid src_port mask."); 4034 return -EINVAL; 4035 } 4036 4037 switch (filter->proto_mask) { 4038 case UINT8_MAX: 4039 filter_info->proto_mask = 0; 4040 filter_info->proto = 4041 convert_protocol_type(filter->proto); 4042 break; 4043 case 0: 4044 filter_info->proto_mask = 1; 4045 break; 4046 default: 4047 PMD_DRV_LOG(ERR, "invalid protocol mask."); 4048 return -EINVAL; 4049 } 4050 4051 filter_info->priority = (uint8_t)filter->priority; 4052 return 0; 4053 } 4054 4055 /* 4056 * add or delete a ntuple filter 4057 * 4058 * @param 4059 * dev: Pointer to struct rte_eth_dev. 4060 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 4061 * add: if true, add filter, if false, remove filter 4062 * 4063 * @return 4064 * - On success, zero. 4065 * - On failure, a negative value. 4066 */ 4067 int 4068 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 4069 struct rte_eth_ntuple_filter *ntuple_filter, 4070 bool add) 4071 { 4072 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4073 struct txgbe_5tuple_filter_info filter_5tuple; 4074 struct txgbe_5tuple_filter *filter; 4075 int ret; 4076 4077 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 4078 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 4079 return -EINVAL; 4080 } 4081 4082 memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info)); 4083 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 4084 if (ret < 0) 4085 return ret; 4086 4087 filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 4088 &filter_5tuple); 4089 if (filter != NULL && add) { 4090 PMD_DRV_LOG(ERR, "filter exists."); 4091 return -EEXIST; 4092 } 4093 if (filter == NULL && !add) { 4094 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4095 return -ENOENT; 4096 } 4097 4098 if (add) { 4099 filter = rte_zmalloc("txgbe_5tuple_filter", 4100 sizeof(struct txgbe_5tuple_filter), 0); 4101 if (filter == NULL) 4102 return -ENOMEM; 4103 rte_memcpy(&filter->filter_info, 4104 &filter_5tuple, 4105 sizeof(struct txgbe_5tuple_filter_info)); 4106 filter->queue = ntuple_filter->queue; 4107 ret = txgbe_add_5tuple_filter(dev, filter); 4108 if (ret < 0) { 4109 rte_free(filter); 4110 return ret; 4111 } 4112 } else { 4113 txgbe_remove_5tuple_filter(dev, filter); 4114 } 4115 4116 return 0; 4117 } 4118 4119 int 4120 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 4121 struct rte_eth_ethertype_filter *filter, 4122 bool add) 4123 { 4124 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4125 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4126 uint32_t etqf = 0; 4127 uint32_t etqs = 0; 4128 int ret; 4129 struct txgbe_ethertype_filter ethertype_filter; 4130 4131 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 4132 return -EINVAL; 4133 4134 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 4135 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 4136 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 4137 " ethertype filter.", filter->ether_type); 4138 return -EINVAL; 4139 } 4140 4141 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 4142 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 4143 return -EINVAL; 4144 } 4145 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 4146 PMD_DRV_LOG(ERR, "drop option is unsupported."); 4147 return -EINVAL; 4148 } 4149 4150 ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 4151 if (ret >= 0 && add) { 4152 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 4153 filter->ether_type); 4154 return -EEXIST; 4155 } 4156 if (ret < 0 && !add) { 4157 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 4158 filter->ether_type); 4159 return -ENOENT; 4160 } 4161 4162 if (add) { 4163 etqf = TXGBE_ETFLT_ENA; 4164 etqf |= TXGBE_ETFLT_ETID(filter->ether_type); 4165 etqs |= TXGBE_ETCLS_QPID(filter->queue); 4166 etqs |= TXGBE_ETCLS_QENA; 4167 4168 ethertype_filter.ethertype = filter->ether_type; 4169 ethertype_filter.etqf = etqf; 4170 ethertype_filter.etqs = etqs; 4171 ethertype_filter.conf = FALSE; 4172 ret = txgbe_ethertype_filter_insert(filter_info, 4173 ðertype_filter); 4174 if (ret < 0) { 4175 PMD_DRV_LOG(ERR, "ethertype filters are full."); 4176 return -ENOSPC; 4177 } 4178 } else { 4179 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 4180 if (ret < 0) 4181 return -ENOSYS; 4182 } 4183 wr32(hw, TXGBE_ETFLT(ret), etqf); 4184 wr32(hw, TXGBE_ETCLS(ret), etqs); 4185 txgbe_flush(hw); 4186 4187 return 0; 4188 } 4189 4190 static int 4191 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev, 4192 const struct rte_flow_ops **ops) 4193 { 4194 *ops = &txgbe_flow_ops; 4195 return 0; 4196 } 4197 4198 static u8 * 4199 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw, 4200 u8 **mc_addr_ptr, u32 *vmdq) 4201 { 4202 u8 *mc_addr; 4203 4204 *vmdq = 0; 4205 mc_addr = *mc_addr_ptr; 4206 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 4207 return mc_addr; 4208 } 4209 4210 int 4211 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 4212 struct rte_ether_addr *mc_addr_set, 4213 uint32_t nb_mc_addr) 4214 { 4215 struct txgbe_hw *hw; 4216 u8 *mc_addr_list; 4217 4218 hw = TXGBE_DEV_HW(dev); 4219 mc_addr_list = (u8 *)mc_addr_set; 4220 return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 4221 txgbe_dev_addr_list_itr, TRUE); 4222 } 4223 4224 static uint64_t 4225 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 4226 { 4227 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4228 uint64_t systime_cycles; 4229 4230 systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL); 4231 systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32; 4232 4233 return systime_cycles; 4234 } 4235 4236 static uint64_t 4237 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4238 { 4239 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4240 uint64_t rx_tstamp_cycles; 4241 4242 /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */ 4243 rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL); 4244 rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32; 4245 4246 return rx_tstamp_cycles; 4247 } 4248 4249 static uint64_t 4250 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4251 { 4252 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4253 uint64_t tx_tstamp_cycles; 4254 4255 /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */ 4256 tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL); 4257 tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32; 4258 4259 return tx_tstamp_cycles; 4260 } 4261 4262 static void 4263 txgbe_start_timecounters(struct rte_eth_dev *dev) 4264 { 4265 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4266 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4267 struct rte_eth_link link; 4268 uint32_t incval = 0; 4269 uint32_t shift = 0; 4270 4271 /* Get current link speed. */ 4272 txgbe_dev_link_update(dev, 1); 4273 rte_eth_linkstatus_get(dev, &link); 4274 4275 switch (link.link_speed) { 4276 case ETH_SPEED_NUM_100M: 4277 incval = TXGBE_INCVAL_100; 4278 shift = TXGBE_INCVAL_SHIFT_100; 4279 break; 4280 case ETH_SPEED_NUM_1G: 4281 incval = TXGBE_INCVAL_1GB; 4282 shift = TXGBE_INCVAL_SHIFT_1GB; 4283 break; 4284 case ETH_SPEED_NUM_10G: 4285 default: 4286 incval = TXGBE_INCVAL_10GB; 4287 shift = TXGBE_INCVAL_SHIFT_10GB; 4288 break; 4289 } 4290 4291 wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2)); 4292 4293 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 4294 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4295 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4296 4297 adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4298 adapter->systime_tc.cc_shift = shift; 4299 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 4300 4301 adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4302 adapter->rx_tstamp_tc.cc_shift = shift; 4303 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4304 4305 adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4306 adapter->tx_tstamp_tc.cc_shift = shift; 4307 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4308 } 4309 4310 static int 4311 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 4312 { 4313 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4314 4315 adapter->systime_tc.nsec += delta; 4316 adapter->rx_tstamp_tc.nsec += delta; 4317 adapter->tx_tstamp_tc.nsec += delta; 4318 4319 return 0; 4320 } 4321 4322 static int 4323 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 4324 { 4325 uint64_t ns; 4326 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4327 4328 ns = rte_timespec_to_ns(ts); 4329 /* Set the timecounters to a new value. */ 4330 adapter->systime_tc.nsec = ns; 4331 adapter->rx_tstamp_tc.nsec = ns; 4332 adapter->tx_tstamp_tc.nsec = ns; 4333 4334 return 0; 4335 } 4336 4337 static int 4338 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 4339 { 4340 uint64_t ns, systime_cycles; 4341 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4342 4343 systime_cycles = txgbe_read_systime_cyclecounter(dev); 4344 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 4345 *ts = rte_ns_to_timespec(ns); 4346 4347 return 0; 4348 } 4349 4350 static int 4351 txgbe_timesync_enable(struct rte_eth_dev *dev) 4352 { 4353 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4354 uint32_t tsync_ctl; 4355 4356 /* Stop the timesync system time. */ 4357 wr32(hw, TXGBE_TSTIMEINC, 0x0); 4358 /* Reset the timesync system time value. */ 4359 wr32(hw, TXGBE_TSTIMEL, 0x0); 4360 wr32(hw, TXGBE_TSTIMEH, 0x0); 4361 4362 txgbe_start_timecounters(dev); 4363 4364 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4365 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 4366 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588); 4367 4368 /* Enable timestamping of received PTP packets. */ 4369 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4370 tsync_ctl |= TXGBE_TSRXCTL_ENA; 4371 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4372 4373 /* Enable timestamping of transmitted PTP packets. */ 4374 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4375 tsync_ctl |= TXGBE_TSTXCTL_ENA; 4376 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4377 4378 txgbe_flush(hw); 4379 4380 return 0; 4381 } 4382 4383 static int 4384 txgbe_timesync_disable(struct rte_eth_dev *dev) 4385 { 4386 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4387 uint32_t tsync_ctl; 4388 4389 /* Disable timestamping of transmitted PTP packets. */ 4390 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4391 tsync_ctl &= ~TXGBE_TSTXCTL_ENA; 4392 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4393 4394 /* Disable timestamping of received PTP packets. */ 4395 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4396 tsync_ctl &= ~TXGBE_TSRXCTL_ENA; 4397 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4398 4399 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4400 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0); 4401 4402 /* Stop incrementating the System Time registers. */ 4403 wr32(hw, TXGBE_TSTIMEINC, 0); 4404 4405 return 0; 4406 } 4407 4408 static int 4409 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 4410 struct timespec *timestamp, 4411 uint32_t flags __rte_unused) 4412 { 4413 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4414 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4415 uint32_t tsync_rxctl; 4416 uint64_t rx_tstamp_cycles; 4417 uint64_t ns; 4418 4419 tsync_rxctl = rd32(hw, TXGBE_TSRXCTL); 4420 if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0) 4421 return -EINVAL; 4422 4423 rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev); 4424 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 4425 *timestamp = rte_ns_to_timespec(ns); 4426 4427 return 0; 4428 } 4429 4430 static int 4431 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 4432 struct timespec *timestamp) 4433 { 4434 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4435 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4436 uint32_t tsync_txctl; 4437 uint64_t tx_tstamp_cycles; 4438 uint64_t ns; 4439 4440 tsync_txctl = rd32(hw, TXGBE_TSTXCTL); 4441 if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0) 4442 return -EINVAL; 4443 4444 tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev); 4445 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 4446 *timestamp = rte_ns_to_timespec(ns); 4447 4448 return 0; 4449 } 4450 4451 static int 4452 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused) 4453 { 4454 int count = 0; 4455 int g_ind = 0; 4456 const struct reg_info *reg_group; 4457 const struct reg_info **reg_set = txgbe_regs_others; 4458 4459 while ((reg_group = reg_set[g_ind++])) 4460 count += txgbe_regs_group_count(reg_group); 4461 4462 return count; 4463 } 4464 4465 static int 4466 txgbe_get_regs(struct rte_eth_dev *dev, 4467 struct rte_dev_reg_info *regs) 4468 { 4469 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4470 uint32_t *data = regs->data; 4471 int g_ind = 0; 4472 int count = 0; 4473 const struct reg_info *reg_group; 4474 const struct reg_info **reg_set = txgbe_regs_others; 4475 4476 if (data == NULL) { 4477 regs->length = txgbe_get_reg_length(dev); 4478 regs->width = sizeof(uint32_t); 4479 return 0; 4480 } 4481 4482 /* Support only full register dump */ 4483 if (regs->length == 0 || 4484 regs->length == (uint32_t)txgbe_get_reg_length(dev)) { 4485 regs->version = hw->mac.type << 24 | 4486 hw->revision_id << 16 | 4487 hw->device_id; 4488 while ((reg_group = reg_set[g_ind++])) 4489 count += txgbe_read_regs_group(dev, &data[count], 4490 reg_group); 4491 return 0; 4492 } 4493 4494 return -ENOTSUP; 4495 } 4496 4497 static int 4498 txgbe_get_eeprom_length(struct rte_eth_dev *dev) 4499 { 4500 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4501 4502 /* Return unit is byte count */ 4503 return hw->rom.word_size * 2; 4504 } 4505 4506 static int 4507 txgbe_get_eeprom(struct rte_eth_dev *dev, 4508 struct rte_dev_eeprom_info *in_eeprom) 4509 { 4510 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4511 struct txgbe_rom_info *eeprom = &hw->rom; 4512 uint16_t *data = in_eeprom->data; 4513 int first, length; 4514 4515 first = in_eeprom->offset >> 1; 4516 length = in_eeprom->length >> 1; 4517 if (first > hw->rom.word_size || 4518 ((first + length) > hw->rom.word_size)) 4519 return -EINVAL; 4520 4521 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4522 4523 return eeprom->readw_buffer(hw, first, length, data); 4524 } 4525 4526 static int 4527 txgbe_set_eeprom(struct rte_eth_dev *dev, 4528 struct rte_dev_eeprom_info *in_eeprom) 4529 { 4530 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4531 struct txgbe_rom_info *eeprom = &hw->rom; 4532 uint16_t *data = in_eeprom->data; 4533 int first, length; 4534 4535 first = in_eeprom->offset >> 1; 4536 length = in_eeprom->length >> 1; 4537 if (first > hw->rom.word_size || 4538 ((first + length) > hw->rom.word_size)) 4539 return -EINVAL; 4540 4541 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4542 4543 return eeprom->writew_buffer(hw, first, length, data); 4544 } 4545 4546 static int 4547 txgbe_get_module_info(struct rte_eth_dev *dev, 4548 struct rte_eth_dev_module_info *modinfo) 4549 { 4550 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4551 uint32_t status; 4552 uint8_t sff8472_rev, addr_mode; 4553 bool page_swap = false; 4554 4555 /* Check whether we support SFF-8472 or not */ 4556 status = hw->phy.read_i2c_eeprom(hw, 4557 TXGBE_SFF_SFF_8472_COMP, 4558 &sff8472_rev); 4559 if (status != 0) 4560 return -EIO; 4561 4562 /* addressing mode is not supported */ 4563 status = hw->phy.read_i2c_eeprom(hw, 4564 TXGBE_SFF_SFF_8472_SWAP, 4565 &addr_mode); 4566 if (status != 0) 4567 return -EIO; 4568 4569 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) { 4570 PMD_DRV_LOG(ERR, 4571 "Address change required to access page 0xA2, " 4572 "but not supported. Please report the module " 4573 "type to the driver maintainers."); 4574 page_swap = true; 4575 } 4576 4577 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) { 4578 /* We have a SFP, but it does not support SFF-8472 */ 4579 modinfo->type = RTE_ETH_MODULE_SFF_8079; 4580 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 4581 } else { 4582 /* We have a SFP which supports a revision of SFF-8472. */ 4583 modinfo->type = RTE_ETH_MODULE_SFF_8472; 4584 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 4585 } 4586 4587 return 0; 4588 } 4589 4590 static int 4591 txgbe_get_module_eeprom(struct rte_eth_dev *dev, 4592 struct rte_dev_eeprom_info *info) 4593 { 4594 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4595 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID; 4596 uint8_t databyte = 0xFF; 4597 uint8_t *data = info->data; 4598 uint32_t i = 0; 4599 4600 if (info->length == 0) 4601 return -EINVAL; 4602 4603 for (i = info->offset; i < info->offset + info->length; i++) { 4604 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 4605 status = hw->phy.read_i2c_eeprom(hw, i, &databyte); 4606 else 4607 status = hw->phy.read_i2c_sff8472(hw, i, &databyte); 4608 4609 if (status != 0) 4610 return -EIO; 4611 4612 data[i - info->offset] = databyte; 4613 } 4614 4615 return 0; 4616 } 4617 4618 bool 4619 txgbe_rss_update_sp(enum txgbe_mac_type mac_type) 4620 { 4621 switch (mac_type) { 4622 case txgbe_mac_raptor: 4623 case txgbe_mac_raptor_vf: 4624 return 1; 4625 default: 4626 return 0; 4627 } 4628 } 4629 4630 static int 4631 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 4632 struct rte_eth_dcb_info *dcb_info) 4633 { 4634 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 4635 struct txgbe_dcb_tc_config *tc; 4636 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 4637 uint8_t nb_tcs; 4638 uint8_t i, j; 4639 4640 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 4641 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 4642 else 4643 dcb_info->nb_tcs = 1; 4644 4645 tc_queue = &dcb_info->tc_queue; 4646 nb_tcs = dcb_info->nb_tcs; 4647 4648 if (dcb_config->vt_mode) { /* vt is enabled */ 4649 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 4650 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 4651 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 4652 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 4653 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 4654 for (j = 0; j < nb_tcs; j++) { 4655 tc_queue->tc_rxq[0][j].base = j; 4656 tc_queue->tc_rxq[0][j].nb_queue = 1; 4657 tc_queue->tc_txq[0][j].base = j; 4658 tc_queue->tc_txq[0][j].nb_queue = 1; 4659 } 4660 } else { 4661 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 4662 for (j = 0; j < nb_tcs; j++) { 4663 tc_queue->tc_rxq[i][j].base = 4664 i * nb_tcs + j; 4665 tc_queue->tc_rxq[i][j].nb_queue = 1; 4666 tc_queue->tc_txq[i][j].base = 4667 i * nb_tcs + j; 4668 tc_queue->tc_txq[i][j].nb_queue = 1; 4669 } 4670 } 4671 } 4672 } else { /* vt is disabled */ 4673 struct rte_eth_dcb_rx_conf *rx_conf = 4674 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 4675 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 4676 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 4677 if (dcb_info->nb_tcs == ETH_4_TCS) { 4678 for (i = 0; i < dcb_info->nb_tcs; i++) { 4679 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 4680 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4681 } 4682 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4683 dcb_info->tc_queue.tc_txq[0][1].base = 64; 4684 dcb_info->tc_queue.tc_txq[0][2].base = 96; 4685 dcb_info->tc_queue.tc_txq[0][3].base = 112; 4686 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 4687 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4688 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4689 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4690 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 4691 for (i = 0; i < dcb_info->nb_tcs; i++) { 4692 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 4693 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4694 } 4695 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4696 dcb_info->tc_queue.tc_txq[0][1].base = 32; 4697 dcb_info->tc_queue.tc_txq[0][2].base = 64; 4698 dcb_info->tc_queue.tc_txq[0][3].base = 80; 4699 dcb_info->tc_queue.tc_txq[0][4].base = 96; 4700 dcb_info->tc_queue.tc_txq[0][5].base = 104; 4701 dcb_info->tc_queue.tc_txq[0][6].base = 112; 4702 dcb_info->tc_queue.tc_txq[0][7].base = 120; 4703 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 4704 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4705 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4706 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4707 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 4708 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 4709 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 4710 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 4711 } 4712 } 4713 for (i = 0; i < dcb_info->nb_tcs; i++) { 4714 tc = &dcb_config->tc_config[i]; 4715 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent; 4716 } 4717 return 0; 4718 } 4719 4720 /* Update e-tag ether type */ 4721 static int 4722 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw, 4723 uint16_t ether_type) 4724 { 4725 uint32_t etag_etype; 4726 4727 etag_etype = rd32(hw, TXGBE_EXTAG); 4728 etag_etype &= ~TXGBE_EXTAG_ETAG_MASK; 4729 etag_etype |= ether_type; 4730 wr32(hw, TXGBE_EXTAG, etag_etype); 4731 txgbe_flush(hw); 4732 4733 return 0; 4734 } 4735 4736 /* Enable e-tag tunnel */ 4737 static int 4738 txgbe_e_tag_enable(struct txgbe_hw *hw) 4739 { 4740 uint32_t etag_etype; 4741 4742 etag_etype = rd32(hw, TXGBE_PORTCTL); 4743 etag_etype |= TXGBE_PORTCTL_ETAG; 4744 wr32(hw, TXGBE_PORTCTL, etag_etype); 4745 txgbe_flush(hw); 4746 4747 return 0; 4748 } 4749 4750 static int 4751 txgbe_e_tag_filter_del(struct rte_eth_dev *dev, 4752 struct txgbe_l2_tunnel_conf *l2_tunnel) 4753 { 4754 int ret = 0; 4755 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4756 uint32_t i, rar_entries; 4757 uint32_t rar_low, rar_high; 4758 4759 rar_entries = hw->mac.num_rar_entries; 4760 4761 for (i = 1; i < rar_entries; i++) { 4762 wr32(hw, TXGBE_ETHADDRIDX, i); 4763 rar_high = rd32(hw, TXGBE_ETHADDRH); 4764 rar_low = rd32(hw, TXGBE_ETHADDRL); 4765 if ((rar_high & TXGBE_ETHADDRH_VLD) && 4766 (rar_high & TXGBE_ETHADDRH_ETAG) && 4767 (TXGBE_ETHADDRL_ETAG(rar_low) == 4768 l2_tunnel->tunnel_id)) { 4769 wr32(hw, TXGBE_ETHADDRL, 0); 4770 wr32(hw, TXGBE_ETHADDRH, 0); 4771 4772 txgbe_clear_vmdq(hw, i, BIT_MASK32); 4773 4774 return ret; 4775 } 4776 } 4777 4778 return ret; 4779 } 4780 4781 static int 4782 txgbe_e_tag_filter_add(struct rte_eth_dev *dev, 4783 struct txgbe_l2_tunnel_conf *l2_tunnel) 4784 { 4785 int ret = 0; 4786 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4787 uint32_t i, rar_entries; 4788 uint32_t rar_low, rar_high; 4789 4790 /* One entry for one tunnel. Try to remove potential existing entry. */ 4791 txgbe_e_tag_filter_del(dev, l2_tunnel); 4792 4793 rar_entries = hw->mac.num_rar_entries; 4794 4795 for (i = 1; i < rar_entries; i++) { 4796 wr32(hw, TXGBE_ETHADDRIDX, i); 4797 rar_high = rd32(hw, TXGBE_ETHADDRH); 4798 if (rar_high & TXGBE_ETHADDRH_VLD) { 4799 continue; 4800 } else { 4801 txgbe_set_vmdq(hw, i, l2_tunnel->pool); 4802 rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG; 4803 rar_low = l2_tunnel->tunnel_id; 4804 4805 wr32(hw, TXGBE_ETHADDRL, rar_low); 4806 wr32(hw, TXGBE_ETHADDRH, rar_high); 4807 4808 return ret; 4809 } 4810 } 4811 4812 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 4813 " Please remove a rule before adding a new one."); 4814 return -EINVAL; 4815 } 4816 4817 static inline struct txgbe_l2_tn_filter * 4818 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info, 4819 struct txgbe_l2_tn_key *key) 4820 { 4821 int ret; 4822 4823 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 4824 if (ret < 0) 4825 return NULL; 4826 4827 return l2_tn_info->hash_map[ret]; 4828 } 4829 4830 static inline int 4831 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4832 struct txgbe_l2_tn_filter *l2_tn_filter) 4833 { 4834 int ret; 4835 4836 ret = rte_hash_add_key(l2_tn_info->hash_handle, 4837 &l2_tn_filter->key); 4838 4839 if (ret < 0) { 4840 PMD_DRV_LOG(ERR, 4841 "Failed to insert L2 tunnel filter" 4842 " to hash table %d!", 4843 ret); 4844 return ret; 4845 } 4846 4847 l2_tn_info->hash_map[ret] = l2_tn_filter; 4848 4849 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4850 4851 return 0; 4852 } 4853 4854 static inline int 4855 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4856 struct txgbe_l2_tn_key *key) 4857 { 4858 int ret; 4859 struct txgbe_l2_tn_filter *l2_tn_filter; 4860 4861 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 4862 4863 if (ret < 0) { 4864 PMD_DRV_LOG(ERR, 4865 "No such L2 tunnel filter to delete %d!", 4866 ret); 4867 return ret; 4868 } 4869 4870 l2_tn_filter = l2_tn_info->hash_map[ret]; 4871 l2_tn_info->hash_map[ret] = NULL; 4872 4873 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4874 rte_free(l2_tn_filter); 4875 4876 return 0; 4877 } 4878 4879 /* Add l2 tunnel filter */ 4880 int 4881 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 4882 struct txgbe_l2_tunnel_conf *l2_tunnel, 4883 bool restore) 4884 { 4885 int ret; 4886 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4887 struct txgbe_l2_tn_key key; 4888 struct txgbe_l2_tn_filter *node; 4889 4890 if (!restore) { 4891 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4892 key.tn_id = l2_tunnel->tunnel_id; 4893 4894 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key); 4895 4896 if (node) { 4897 PMD_DRV_LOG(ERR, 4898 "The L2 tunnel filter already exists!"); 4899 return -EINVAL; 4900 } 4901 4902 node = rte_zmalloc("txgbe_l2_tn", 4903 sizeof(struct txgbe_l2_tn_filter), 4904 0); 4905 if (!node) 4906 return -ENOMEM; 4907 4908 rte_memcpy(&node->key, 4909 &key, 4910 sizeof(struct txgbe_l2_tn_key)); 4911 node->pool = l2_tunnel->pool; 4912 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node); 4913 if (ret < 0) { 4914 rte_free(node); 4915 return ret; 4916 } 4917 } 4918 4919 switch (l2_tunnel->l2_tunnel_type) { 4920 case RTE_L2_TUNNEL_TYPE_E_TAG: 4921 ret = txgbe_e_tag_filter_add(dev, l2_tunnel); 4922 break; 4923 default: 4924 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4925 ret = -EINVAL; 4926 break; 4927 } 4928 4929 if (!restore && ret < 0) 4930 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4931 4932 return ret; 4933 } 4934 4935 /* Delete l2 tunnel filter */ 4936 int 4937 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 4938 struct txgbe_l2_tunnel_conf *l2_tunnel) 4939 { 4940 int ret; 4941 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4942 struct txgbe_l2_tn_key key; 4943 4944 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4945 key.tn_id = l2_tunnel->tunnel_id; 4946 ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4947 if (ret < 0) 4948 return ret; 4949 4950 switch (l2_tunnel->l2_tunnel_type) { 4951 case RTE_L2_TUNNEL_TYPE_E_TAG: 4952 ret = txgbe_e_tag_filter_del(dev, l2_tunnel); 4953 break; 4954 default: 4955 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4956 ret = -EINVAL; 4957 break; 4958 } 4959 4960 return ret; 4961 } 4962 4963 static int 4964 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 4965 { 4966 int ret = 0; 4967 uint32_t ctrl; 4968 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4969 4970 ctrl = rd32(hw, TXGBE_POOLCTL); 4971 ctrl &= ~TXGBE_POOLCTL_MODE_MASK; 4972 if (en) 4973 ctrl |= TXGBE_PSRPOOL_MODE_ETAG; 4974 wr32(hw, TXGBE_POOLCTL, ctrl); 4975 4976 return ret; 4977 } 4978 4979 /* Add UDP tunneling port */ 4980 static int 4981 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 4982 struct rte_eth_udp_tunnel *udp_tunnel) 4983 { 4984 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4985 int ret = 0; 4986 4987 if (udp_tunnel == NULL) 4988 return -EINVAL; 4989 4990 switch (udp_tunnel->prot_type) { 4991 case RTE_TUNNEL_TYPE_VXLAN: 4992 if (udp_tunnel->udp_port == 0) { 4993 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 4994 ret = -EINVAL; 4995 break; 4996 } 4997 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port); 4998 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port); 4999 break; 5000 case RTE_TUNNEL_TYPE_GENEVE: 5001 if (udp_tunnel->udp_port == 0) { 5002 PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed."); 5003 ret = -EINVAL; 5004 break; 5005 } 5006 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port); 5007 break; 5008 case RTE_TUNNEL_TYPE_TEREDO: 5009 if (udp_tunnel->udp_port == 0) { 5010 PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed."); 5011 ret = -EINVAL; 5012 break; 5013 } 5014 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port); 5015 break; 5016 default: 5017 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5018 ret = -EINVAL; 5019 break; 5020 } 5021 5022 txgbe_flush(hw); 5023 5024 return ret; 5025 } 5026 5027 /* Remove UDP tunneling port */ 5028 static int 5029 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 5030 struct rte_eth_udp_tunnel *udp_tunnel) 5031 { 5032 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5033 int ret = 0; 5034 uint16_t cur_port; 5035 5036 if (udp_tunnel == NULL) 5037 return -EINVAL; 5038 5039 switch (udp_tunnel->prot_type) { 5040 case RTE_TUNNEL_TYPE_VXLAN: 5041 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT); 5042 if (cur_port != udp_tunnel->udp_port) { 5043 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5044 udp_tunnel->udp_port); 5045 ret = -EINVAL; 5046 break; 5047 } 5048 wr32(hw, TXGBE_VXLANPORT, 0); 5049 wr32(hw, TXGBE_VXLANPORTGPE, 0); 5050 break; 5051 case RTE_TUNNEL_TYPE_GENEVE: 5052 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT); 5053 if (cur_port != udp_tunnel->udp_port) { 5054 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5055 udp_tunnel->udp_port); 5056 ret = -EINVAL; 5057 break; 5058 } 5059 wr32(hw, TXGBE_GENEVEPORT, 0); 5060 break; 5061 case RTE_TUNNEL_TYPE_TEREDO: 5062 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT); 5063 if (cur_port != udp_tunnel->udp_port) { 5064 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5065 udp_tunnel->udp_port); 5066 ret = -EINVAL; 5067 break; 5068 } 5069 wr32(hw, TXGBE_TEREDOPORT, 0); 5070 break; 5071 default: 5072 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5073 ret = -EINVAL; 5074 break; 5075 } 5076 5077 txgbe_flush(hw); 5078 5079 return ret; 5080 } 5081 5082 /* restore n-tuple filter */ 5083 static inline void 5084 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 5085 { 5086 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5087 struct txgbe_5tuple_filter *node; 5088 5089 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 5090 txgbe_inject_5tuple_filter(dev, node); 5091 } 5092 } 5093 5094 /* restore ethernet type filter */ 5095 static inline void 5096 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 5097 { 5098 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5099 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5100 int i; 5101 5102 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5103 if (filter_info->ethertype_mask & (1 << i)) { 5104 wr32(hw, TXGBE_ETFLT(i), 5105 filter_info->ethertype_filters[i].etqf); 5106 wr32(hw, TXGBE_ETCLS(i), 5107 filter_info->ethertype_filters[i].etqs); 5108 txgbe_flush(hw); 5109 } 5110 } 5111 } 5112 5113 /* restore SYN filter */ 5114 static inline void 5115 txgbe_syn_filter_restore(struct rte_eth_dev *dev) 5116 { 5117 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5118 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5119 uint32_t synqf; 5120 5121 synqf = filter_info->syn_info; 5122 5123 if (synqf & TXGBE_SYNCLS_ENA) { 5124 wr32(hw, TXGBE_SYNCLS, synqf); 5125 txgbe_flush(hw); 5126 } 5127 } 5128 5129 /* restore L2 tunnel filter */ 5130 static inline void 5131 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 5132 { 5133 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5134 struct txgbe_l2_tn_filter *node; 5135 struct txgbe_l2_tunnel_conf l2_tn_conf; 5136 5137 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 5138 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 5139 l2_tn_conf.tunnel_id = node->key.tn_id; 5140 l2_tn_conf.pool = node->pool; 5141 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 5142 } 5143 } 5144 5145 /* restore rss filter */ 5146 static inline void 5147 txgbe_rss_filter_restore(struct rte_eth_dev *dev) 5148 { 5149 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5150 5151 if (filter_info->rss_info.conf.queue_num) 5152 txgbe_config_rss_filter(dev, 5153 &filter_info->rss_info, TRUE); 5154 } 5155 5156 static int 5157 txgbe_filter_restore(struct rte_eth_dev *dev) 5158 { 5159 txgbe_ntuple_filter_restore(dev); 5160 txgbe_ethertype_filter_restore(dev); 5161 txgbe_syn_filter_restore(dev); 5162 txgbe_fdir_filter_restore(dev); 5163 txgbe_l2_tn_filter_restore(dev); 5164 txgbe_rss_filter_restore(dev); 5165 5166 return 0; 5167 } 5168 5169 static void 5170 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 5171 { 5172 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5173 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5174 5175 if (l2_tn_info->e_tag_en) 5176 (void)txgbe_e_tag_enable(hw); 5177 5178 if (l2_tn_info->e_tag_fwd_en) 5179 (void)txgbe_e_tag_forwarding_en_dis(dev, 1); 5180 5181 (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 5182 } 5183 5184 /* remove all the n-tuple filters */ 5185 void 5186 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 5187 { 5188 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5189 struct txgbe_5tuple_filter *p_5tuple; 5190 5191 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 5192 txgbe_remove_5tuple_filter(dev, p_5tuple); 5193 } 5194 5195 /* remove all the ether type filters */ 5196 void 5197 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 5198 { 5199 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5200 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5201 int i; 5202 5203 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5204 if (filter_info->ethertype_mask & (1 << i) && 5205 !filter_info->ethertype_filters[i].conf) { 5206 (void)txgbe_ethertype_filter_remove(filter_info, 5207 (uint8_t)i); 5208 wr32(hw, TXGBE_ETFLT(i), 0); 5209 wr32(hw, TXGBE_ETCLS(i), 0); 5210 txgbe_flush(hw); 5211 } 5212 } 5213 } 5214 5215 /* remove the SYN filter */ 5216 void 5217 txgbe_clear_syn_filter(struct rte_eth_dev *dev) 5218 { 5219 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5220 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5221 5222 if (filter_info->syn_info & TXGBE_SYNCLS_ENA) { 5223 filter_info->syn_info = 0; 5224 5225 wr32(hw, TXGBE_SYNCLS, 0); 5226 txgbe_flush(hw); 5227 } 5228 } 5229 5230 /* remove all the L2 tunnel filters */ 5231 int 5232 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 5233 { 5234 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5235 struct txgbe_l2_tn_filter *l2_tn_filter; 5236 struct txgbe_l2_tunnel_conf l2_tn_conf; 5237 int ret = 0; 5238 5239 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 5240 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 5241 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 5242 l2_tn_conf.pool = l2_tn_filter->pool; 5243 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 5244 if (ret < 0) 5245 return ret; 5246 } 5247 5248 return 0; 5249 } 5250 5251 static const struct eth_dev_ops txgbe_eth_dev_ops = { 5252 .dev_configure = txgbe_dev_configure, 5253 .dev_infos_get = txgbe_dev_info_get, 5254 .dev_start = txgbe_dev_start, 5255 .dev_stop = txgbe_dev_stop, 5256 .dev_set_link_up = txgbe_dev_set_link_up, 5257 .dev_set_link_down = txgbe_dev_set_link_down, 5258 .dev_close = txgbe_dev_close, 5259 .dev_reset = txgbe_dev_reset, 5260 .promiscuous_enable = txgbe_dev_promiscuous_enable, 5261 .promiscuous_disable = txgbe_dev_promiscuous_disable, 5262 .allmulticast_enable = txgbe_dev_allmulticast_enable, 5263 .allmulticast_disable = txgbe_dev_allmulticast_disable, 5264 .link_update = txgbe_dev_link_update, 5265 .stats_get = txgbe_dev_stats_get, 5266 .xstats_get = txgbe_dev_xstats_get, 5267 .xstats_get_by_id = txgbe_dev_xstats_get_by_id, 5268 .stats_reset = txgbe_dev_stats_reset, 5269 .xstats_reset = txgbe_dev_xstats_reset, 5270 .xstats_get_names = txgbe_dev_xstats_get_names, 5271 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id, 5272 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set, 5273 .fw_version_get = txgbe_fw_version_get, 5274 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get, 5275 .mtu_set = txgbe_dev_mtu_set, 5276 .vlan_filter_set = txgbe_vlan_filter_set, 5277 .vlan_tpid_set = txgbe_vlan_tpid_set, 5278 .vlan_offload_set = txgbe_vlan_offload_set, 5279 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set, 5280 .rx_queue_start = txgbe_dev_rx_queue_start, 5281 .rx_queue_stop = txgbe_dev_rx_queue_stop, 5282 .tx_queue_start = txgbe_dev_tx_queue_start, 5283 .tx_queue_stop = txgbe_dev_tx_queue_stop, 5284 .rx_queue_setup = txgbe_dev_rx_queue_setup, 5285 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable, 5286 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable, 5287 .rx_queue_release = txgbe_dev_rx_queue_release, 5288 .tx_queue_setup = txgbe_dev_tx_queue_setup, 5289 .tx_queue_release = txgbe_dev_tx_queue_release, 5290 .dev_led_on = txgbe_dev_led_on, 5291 .dev_led_off = txgbe_dev_led_off, 5292 .flow_ctrl_get = txgbe_flow_ctrl_get, 5293 .flow_ctrl_set = txgbe_flow_ctrl_set, 5294 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set, 5295 .mac_addr_add = txgbe_add_rar, 5296 .mac_addr_remove = txgbe_remove_rar, 5297 .mac_addr_set = txgbe_set_default_mac_addr, 5298 .uc_hash_table_set = txgbe_uc_hash_table_set, 5299 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set, 5300 .set_queue_rate_limit = txgbe_set_queue_rate_limit, 5301 .reta_update = txgbe_dev_rss_reta_update, 5302 .reta_query = txgbe_dev_rss_reta_query, 5303 .rss_hash_update = txgbe_dev_rss_hash_update, 5304 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get, 5305 .flow_ops_get = txgbe_dev_flow_ops_get, 5306 .set_mc_addr_list = txgbe_dev_set_mc_addr_list, 5307 .rxq_info_get = txgbe_rxq_info_get, 5308 .txq_info_get = txgbe_txq_info_get, 5309 .timesync_enable = txgbe_timesync_enable, 5310 .timesync_disable = txgbe_timesync_disable, 5311 .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp, 5312 .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp, 5313 .get_reg = txgbe_get_regs, 5314 .get_eeprom_length = txgbe_get_eeprom_length, 5315 .get_eeprom = txgbe_get_eeprom, 5316 .set_eeprom = txgbe_set_eeprom, 5317 .get_module_info = txgbe_get_module_info, 5318 .get_module_eeprom = txgbe_get_module_eeprom, 5319 .get_dcb_info = txgbe_dev_get_dcb_info, 5320 .timesync_adjust_time = txgbe_timesync_adjust_time, 5321 .timesync_read_time = txgbe_timesync_read_time, 5322 .timesync_write_time = txgbe_timesync_write_time, 5323 .udp_tunnel_port_add = txgbe_dev_udp_tunnel_port_add, 5324 .udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del, 5325 .tm_ops_get = txgbe_tm_ops_get, 5326 .tx_done_cleanup = txgbe_dev_tx_done_cleanup, 5327 }; 5328 5329 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd); 5330 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map); 5331 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 5332 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe, 5333 TXGBE_DEVARG_BP_AUTO "=<0|1>" 5334 TXGBE_DEVARG_KR_POLL "=<0|1>" 5335 TXGBE_DEVARG_KR_PRESENT "=<0|1>" 5336 TXGBE_DEVARG_KX_SGMII "=<0|1>" 5337 TXGBE_DEVARG_FFE_SET "=<0-4>" 5338 TXGBE_DEVARG_FFE_MAIN "=<uint16>" 5339 TXGBE_DEVARG_FFE_PRE "=<uint16>" 5340 TXGBE_DEVARG_FFE_POST "=<uint16>"); 5341 5342 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE); 5343 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE); 5344 RTE_LOG_REGISTER(txgbe_logtype_bp, pmd.net.txgbe.bp, NOTICE); 5345 5346 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX 5347 RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG); 5348 #endif 5349 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX 5350 RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG); 5351 #endif 5352 5353 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE 5354 RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG); 5355 #endif 5356