1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <rte_common.h> 10 #include <ethdev_pci.h> 11 12 #include <rte_interrupts.h> 13 #include <rte_log.h> 14 #include <rte_debug.h> 15 #include <rte_pci.h> 16 #include <rte_memory.h> 17 #include <rte_eal.h> 18 #include <rte_alarm.h> 19 20 #include "txgbe_logs.h" 21 #include "base/txgbe.h" 22 #include "txgbe_ethdev.h" 23 #include "txgbe_rxtx.h" 24 #include "txgbe_regs_group.h" 25 26 static const struct reg_info txgbe_regs_general[] = { 27 {TXGBE_RST, 1, 1, "TXGBE_RST"}, 28 {TXGBE_STAT, 1, 1, "TXGBE_STAT"}, 29 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"}, 30 {TXGBE_SDP, 1, 1, "TXGBE_SDP"}, 31 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"}, 32 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"}, 33 {0, 0, 0, ""} 34 }; 35 36 static const struct reg_info txgbe_regs_nvm[] = { 37 {0, 0, 0, ""} 38 }; 39 40 static const struct reg_info txgbe_regs_interrupt[] = { 41 {0, 0, 0, ""} 42 }; 43 44 static const struct reg_info txgbe_regs_fctl_others[] = { 45 {0, 0, 0, ""} 46 }; 47 48 static const struct reg_info txgbe_regs_rxdma[] = { 49 {0, 0, 0, ""} 50 }; 51 52 static const struct reg_info txgbe_regs_rx[] = { 53 {0, 0, 0, ""} 54 }; 55 56 static struct reg_info txgbe_regs_tx[] = { 57 {0, 0, 0, ""} 58 }; 59 60 static const struct reg_info txgbe_regs_wakeup[] = { 61 {0, 0, 0, ""} 62 }; 63 64 static const struct reg_info txgbe_regs_dcb[] = { 65 {0, 0, 0, ""} 66 }; 67 68 static const struct reg_info txgbe_regs_mac[] = { 69 {0, 0, 0, ""} 70 }; 71 72 static const struct reg_info txgbe_regs_diagnostic[] = { 73 {0, 0, 0, ""}, 74 }; 75 76 /* PF registers */ 77 static const struct reg_info *txgbe_regs_others[] = { 78 txgbe_regs_general, 79 txgbe_regs_nvm, 80 txgbe_regs_interrupt, 81 txgbe_regs_fctl_others, 82 txgbe_regs_rxdma, 83 txgbe_regs_rx, 84 txgbe_regs_tx, 85 txgbe_regs_wakeup, 86 txgbe_regs_dcb, 87 txgbe_regs_mac, 88 txgbe_regs_diagnostic, 89 NULL}; 90 91 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 92 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 93 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 94 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 95 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev); 96 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev); 97 static int txgbe_dev_close(struct rte_eth_dev *dev); 98 static int txgbe_dev_link_update(struct rte_eth_dev *dev, 99 int wait_to_complete); 100 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev); 101 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 102 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, 103 uint16_t queue); 104 105 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev); 106 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 107 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 108 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 109 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 110 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 111 struct rte_intr_handle *handle); 112 static void txgbe_dev_interrupt_handler(void *param); 113 static void txgbe_dev_interrupt_delayed_handler(void *param); 114 static void txgbe_configure_msix(struct rte_eth_dev *dev); 115 116 static int txgbe_filter_restore(struct rte_eth_dev *dev); 117 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 118 119 #define TXGBE_SET_HWSTRIP(h, q) do {\ 120 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 121 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 122 (h)->bitmap[idx] |= 1 << bit;\ 123 } while (0) 124 125 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\ 126 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 127 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 128 (h)->bitmap[idx] &= ~(1 << bit);\ 129 } while (0) 130 131 #define TXGBE_GET_HWSTRIP(h, q, r) do {\ 132 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 133 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 134 (r) = (h)->bitmap[idx] >> bit & 1;\ 135 } while (0) 136 137 /* 138 * The set of PCI devices this driver supports 139 */ 140 static const struct rte_pci_id pci_id_txgbe_map[] = { 141 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) }, 142 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) }, 143 { .vendor_id = 0, /* sentinel */ }, 144 }; 145 146 static const struct rte_eth_desc_lim rx_desc_lim = { 147 .nb_max = TXGBE_RING_DESC_MAX, 148 .nb_min = TXGBE_RING_DESC_MIN, 149 .nb_align = TXGBE_RXD_ALIGN, 150 }; 151 152 static const struct rte_eth_desc_lim tx_desc_lim = { 153 .nb_max = TXGBE_RING_DESC_MAX, 154 .nb_min = TXGBE_RING_DESC_MIN, 155 .nb_align = TXGBE_TXD_ALIGN, 156 .nb_seg_max = TXGBE_TX_MAX_SEG, 157 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG, 158 }; 159 160 static const struct eth_dev_ops txgbe_eth_dev_ops; 161 162 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)} 163 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)} 164 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = { 165 /* MNG RxTx */ 166 HW_XSTAT(mng_bmc2host_packets), 167 HW_XSTAT(mng_host2bmc_packets), 168 /* Basic RxTx */ 169 HW_XSTAT(rx_packets), 170 HW_XSTAT(tx_packets), 171 HW_XSTAT(rx_bytes), 172 HW_XSTAT(tx_bytes), 173 HW_XSTAT(rx_total_bytes), 174 HW_XSTAT(rx_total_packets), 175 HW_XSTAT(tx_total_packets), 176 HW_XSTAT(rx_total_missed_packets), 177 HW_XSTAT(rx_broadcast_packets), 178 HW_XSTAT(rx_multicast_packets), 179 HW_XSTAT(rx_management_packets), 180 HW_XSTAT(tx_management_packets), 181 HW_XSTAT(rx_management_dropped), 182 183 /* Basic Error */ 184 HW_XSTAT(rx_crc_errors), 185 HW_XSTAT(rx_illegal_byte_errors), 186 HW_XSTAT(rx_error_bytes), 187 HW_XSTAT(rx_mac_short_packet_dropped), 188 HW_XSTAT(rx_length_errors), 189 HW_XSTAT(rx_undersize_errors), 190 HW_XSTAT(rx_fragment_errors), 191 HW_XSTAT(rx_oversize_errors), 192 HW_XSTAT(rx_jabber_errors), 193 HW_XSTAT(rx_l3_l4_xsum_error), 194 HW_XSTAT(mac_local_errors), 195 HW_XSTAT(mac_remote_errors), 196 197 /* Flow Director */ 198 HW_XSTAT(flow_director_added_filters), 199 HW_XSTAT(flow_director_removed_filters), 200 HW_XSTAT(flow_director_filter_add_errors), 201 HW_XSTAT(flow_director_filter_remove_errors), 202 HW_XSTAT(flow_director_matched_filters), 203 HW_XSTAT(flow_director_missed_filters), 204 205 /* FCoE */ 206 HW_XSTAT(rx_fcoe_crc_errors), 207 HW_XSTAT(rx_fcoe_mbuf_allocation_errors), 208 HW_XSTAT(rx_fcoe_dropped), 209 HW_XSTAT(rx_fcoe_packets), 210 HW_XSTAT(tx_fcoe_packets), 211 HW_XSTAT(rx_fcoe_bytes), 212 HW_XSTAT(tx_fcoe_bytes), 213 HW_XSTAT(rx_fcoe_no_ddp), 214 HW_XSTAT(rx_fcoe_no_ddp_ext_buff), 215 216 /* MACSEC */ 217 HW_XSTAT(tx_macsec_pkts_untagged), 218 HW_XSTAT(tx_macsec_pkts_encrypted), 219 HW_XSTAT(tx_macsec_pkts_protected), 220 HW_XSTAT(tx_macsec_octets_encrypted), 221 HW_XSTAT(tx_macsec_octets_protected), 222 HW_XSTAT(rx_macsec_pkts_untagged), 223 HW_XSTAT(rx_macsec_pkts_badtag), 224 HW_XSTAT(rx_macsec_pkts_nosci), 225 HW_XSTAT(rx_macsec_pkts_unknownsci), 226 HW_XSTAT(rx_macsec_octets_decrypted), 227 HW_XSTAT(rx_macsec_octets_validated), 228 HW_XSTAT(rx_macsec_sc_pkts_unchecked), 229 HW_XSTAT(rx_macsec_sc_pkts_delayed), 230 HW_XSTAT(rx_macsec_sc_pkts_late), 231 HW_XSTAT(rx_macsec_sa_pkts_ok), 232 HW_XSTAT(rx_macsec_sa_pkts_invalid), 233 HW_XSTAT(rx_macsec_sa_pkts_notvalid), 234 HW_XSTAT(rx_macsec_sa_pkts_unusedsa), 235 HW_XSTAT(rx_macsec_sa_pkts_notusingsa), 236 237 /* MAC RxTx */ 238 HW_XSTAT(rx_size_64_packets), 239 HW_XSTAT(rx_size_65_to_127_packets), 240 HW_XSTAT(rx_size_128_to_255_packets), 241 HW_XSTAT(rx_size_256_to_511_packets), 242 HW_XSTAT(rx_size_512_to_1023_packets), 243 HW_XSTAT(rx_size_1024_to_max_packets), 244 HW_XSTAT(tx_size_64_packets), 245 HW_XSTAT(tx_size_65_to_127_packets), 246 HW_XSTAT(tx_size_128_to_255_packets), 247 HW_XSTAT(tx_size_256_to_511_packets), 248 HW_XSTAT(tx_size_512_to_1023_packets), 249 HW_XSTAT(tx_size_1024_to_max_packets), 250 251 /* Flow Control */ 252 HW_XSTAT(tx_xon_packets), 253 HW_XSTAT(rx_xon_packets), 254 HW_XSTAT(tx_xoff_packets), 255 HW_XSTAT(rx_xoff_packets), 256 257 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"), 258 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"), 259 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"), 260 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"), 261 }; 262 263 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \ 264 sizeof(rte_txgbe_stats_strings[0])) 265 266 /* Per-priority statistics */ 267 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)} 268 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = { 269 UP_XSTAT(rx_up_packets), 270 UP_XSTAT(tx_up_packets), 271 UP_XSTAT(rx_up_bytes), 272 UP_XSTAT(tx_up_bytes), 273 UP_XSTAT(rx_up_drop_packets), 274 275 UP_XSTAT(tx_up_xon_packets), 276 UP_XSTAT(rx_up_xon_packets), 277 UP_XSTAT(tx_up_xoff_packets), 278 UP_XSTAT(rx_up_xoff_packets), 279 UP_XSTAT(rx_up_dropped), 280 UP_XSTAT(rx_up_mbuf_alloc_errors), 281 UP_XSTAT(tx_up_xon2off_packets), 282 }; 283 284 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \ 285 sizeof(rte_txgbe_up_strings[0])) 286 287 /* Per-queue statistics */ 288 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)} 289 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = { 290 QP_XSTAT(rx_qp_packets), 291 QP_XSTAT(tx_qp_packets), 292 QP_XSTAT(rx_qp_bytes), 293 QP_XSTAT(tx_qp_bytes), 294 QP_XSTAT(rx_qp_mc_packets), 295 }; 296 297 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \ 298 sizeof(rte_txgbe_qp_strings[0])) 299 300 static inline int 301 txgbe_is_sfp(struct txgbe_hw *hw) 302 { 303 switch (hw->phy.type) { 304 case txgbe_phy_sfp_avago: 305 case txgbe_phy_sfp_ftl: 306 case txgbe_phy_sfp_intel: 307 case txgbe_phy_sfp_unknown: 308 case txgbe_phy_sfp_tyco_passive: 309 case txgbe_phy_sfp_unknown_passive: 310 return 1; 311 default: 312 return 0; 313 } 314 } 315 316 static inline int32_t 317 txgbe_pf_reset_hw(struct txgbe_hw *hw) 318 { 319 uint32_t ctrl_ext; 320 int32_t status; 321 322 status = hw->mac.reset_hw(hw); 323 324 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 325 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 326 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 327 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 328 txgbe_flush(hw); 329 330 if (status == TXGBE_ERR_SFP_NOT_PRESENT) 331 status = 0; 332 return status; 333 } 334 335 static inline void 336 txgbe_enable_intr(struct rte_eth_dev *dev) 337 { 338 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 339 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 340 341 wr32(hw, TXGBE_IENMISC, intr->mask_misc); 342 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK); 343 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK); 344 txgbe_flush(hw); 345 } 346 347 static void 348 txgbe_disable_intr(struct txgbe_hw *hw) 349 { 350 PMD_INIT_FUNC_TRACE(); 351 352 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32); 353 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK); 354 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK); 355 txgbe_flush(hw); 356 } 357 358 static int 359 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 360 uint16_t queue_id, 361 uint8_t stat_idx, 362 uint8_t is_rx) 363 { 364 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 365 struct txgbe_stat_mappings *stat_mappings = 366 TXGBE_DEV_STAT_MAPPINGS(eth_dev); 367 uint32_t qsmr_mask = 0; 368 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 369 uint32_t q_map; 370 uint8_t n, offset; 371 372 if (hw->mac.type != txgbe_mac_raptor) 373 return -ENOSYS; 374 375 if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK) 376 return -EIO; 377 378 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 379 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 380 queue_id, stat_idx); 381 382 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 383 if (n >= TXGBE_NB_STAT_MAPPING) { 384 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 385 return -EIO; 386 } 387 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 388 389 /* Now clear any previous stat_idx set */ 390 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 391 if (!is_rx) 392 stat_mappings->tqsm[n] &= ~clearing_mask; 393 else 394 stat_mappings->rqsm[n] &= ~clearing_mask; 395 396 q_map = (uint32_t)stat_idx; 397 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 398 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 399 if (!is_rx) 400 stat_mappings->tqsm[n] |= qsmr_mask; 401 else 402 stat_mappings->rqsm[n] |= qsmr_mask; 403 404 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 405 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 406 queue_id, stat_idx); 407 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 408 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]); 409 return 0; 410 } 411 412 static void 413 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config) 414 { 415 int i; 416 u8 bwgp; 417 struct txgbe_dcb_tc_config *tc; 418 419 UNREFERENCED_PARAMETER(hw); 420 421 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX; 422 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX; 423 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX); 424 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 425 tc = &dcb_config->tc_config[i]; 426 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i; 427 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1); 428 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i; 429 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1); 430 tc->pfc = txgbe_dcb_pfc_disabled; 431 } 432 433 /* Initialize default user to priority mapping, UPx->TC0 */ 434 tc = &dcb_config->tc_config[0]; 435 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 436 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 437 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) { 438 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100; 439 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100; 440 } 441 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal; 442 dcb_config->pfc_mode_enable = false; 443 dcb_config->vt_mode = true; 444 dcb_config->round_robin_enable = false; 445 /* support all DCB capabilities */ 446 dcb_config->support.capabilities = 0xFF; 447 } 448 449 /* 450 * Ensure that all locks are released before first NVM or PHY access 451 */ 452 static void 453 txgbe_swfw_lock_reset(struct txgbe_hw *hw) 454 { 455 uint16_t mask; 456 457 /* 458 * These ones are more tricky since they are common to all ports; but 459 * swfw_sync retries last long enough (1s) to be almost sure that if 460 * lock can not be taken it is due to an improper lock of the 461 * semaphore. 462 */ 463 mask = TXGBE_MNGSEM_SWPHY | 464 TXGBE_MNGSEM_SWMBX | 465 TXGBE_MNGSEM_SWFLASH; 466 if (hw->mac.acquire_swfw_sync(hw, mask) < 0) 467 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 468 469 hw->mac.release_swfw_sync(hw, mask); 470 } 471 472 static int 473 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 474 { 475 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 476 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 477 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev); 478 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev); 479 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev); 480 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 481 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev); 482 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 483 const struct rte_memzone *mz; 484 uint32_t ctrl_ext; 485 uint16_t csum; 486 int err, i, ret; 487 488 PMD_INIT_FUNC_TRACE(); 489 490 eth_dev->dev_ops = &txgbe_eth_dev_ops; 491 eth_dev->rx_queue_count = txgbe_dev_rx_queue_count; 492 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status; 493 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status; 494 eth_dev->rx_pkt_burst = &txgbe_recv_pkts; 495 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts; 496 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts; 497 498 /* 499 * For secondary processes, we don't initialise any further as primary 500 * has already done this work. Only check we don't need a different 501 * RX and TX function. 502 */ 503 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 504 struct txgbe_tx_queue *txq; 505 /* TX queue function in primary, set by last queue initialized 506 * Tx queue may not initialized by primary process 507 */ 508 if (eth_dev->data->tx_queues) { 509 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues; 510 txq = eth_dev->data->tx_queues[nb_tx_queues - 1]; 511 txgbe_set_tx_function(eth_dev, txq); 512 } else { 513 /* Use default TX function if we get here */ 514 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 515 "Using default TX function."); 516 } 517 518 txgbe_set_rx_function(eth_dev); 519 520 return 0; 521 } 522 523 rte_eth_copy_pci_info(eth_dev, pci_dev); 524 525 /* Vendor and Device ID need to be set before init of shared code */ 526 hw->device_id = pci_dev->id.device_id; 527 hw->vendor_id = pci_dev->id.vendor_id; 528 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 529 hw->allow_unsupported_sfp = 1; 530 531 /* Reserve memory for interrupt status block */ 532 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1, 533 16, TXGBE_ALIGN, SOCKET_ID_ANY); 534 if (mz == NULL) 535 return -ENOMEM; 536 537 hw->isb_dma = TMZ_PADDR(mz); 538 hw->isb_mem = TMZ_VADDR(mz); 539 540 /* Initialize the shared code (base driver) */ 541 err = txgbe_init_shared_code(hw); 542 if (err != 0) { 543 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err); 544 return -EIO; 545 } 546 547 /* Unlock any pending hardware semaphore */ 548 txgbe_swfw_lock_reset(hw); 549 550 #ifdef RTE_LIB_SECURITY 551 /* Initialize security_ctx only for primary process*/ 552 if (txgbe_ipsec_ctx_create(eth_dev)) 553 return -ENOMEM; 554 #endif 555 556 /* Initialize DCB configuration*/ 557 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config)); 558 txgbe_dcb_init(hw, dcb_config); 559 560 /* Get Hardware Flow Control setting */ 561 hw->fc.requested_mode = txgbe_fc_full; 562 hw->fc.current_mode = txgbe_fc_full; 563 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME; 564 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 565 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH; 566 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH; 567 } 568 hw->fc.send_xon = 1; 569 570 err = hw->rom.init_params(hw); 571 if (err != 0) { 572 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err); 573 return -EIO; 574 } 575 576 /* Make sure we have a good EEPROM before we read from it */ 577 err = hw->rom.validate_checksum(hw, &csum); 578 if (err != 0) { 579 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err); 580 return -EIO; 581 } 582 583 err = hw->mac.init_hw(hw); 584 585 /* 586 * Devices with copper phys will fail to initialise if txgbe_init_hw() 587 * is called too soon after the kernel driver unbinding/binding occurs. 588 * The failure occurs in txgbe_identify_phy() for all devices, 589 * but for non-copper devies, txgbe_identify_sfp_module() is 590 * also called. See txgbe_identify_phy(). The reason for the 591 * failure is not known, and only occuts when virtualisation features 592 * are disabled in the bios. A delay of 200ms was found to be enough by 593 * trial-and-error, and is doubled to be safe. 594 */ 595 if (err && hw->phy.media_type == txgbe_media_type_copper) { 596 rte_delay_ms(200); 597 err = hw->mac.init_hw(hw); 598 } 599 600 if (err == TXGBE_ERR_SFP_NOT_PRESENT) 601 err = 0; 602 603 if (err == TXGBE_ERR_EEPROM_VERSION) { 604 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 605 "LOM. Please be aware there may be issues associated " 606 "with your hardware."); 607 PMD_INIT_LOG(ERR, "If you are experiencing problems " 608 "please contact your hardware representative " 609 "who provided you with this hardware."); 610 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) { 611 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 612 } 613 if (err) { 614 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err); 615 return -EIO; 616 } 617 618 /* Reset the hw statistics */ 619 txgbe_dev_stats_reset(eth_dev); 620 621 /* disable interrupt */ 622 txgbe_disable_intr(hw); 623 624 /* Allocate memory for storing MAC addresses */ 625 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN * 626 hw->mac.num_rar_entries, 0); 627 if (eth_dev->data->mac_addrs == NULL) { 628 PMD_INIT_LOG(ERR, 629 "Failed to allocate %u bytes needed to store " 630 "MAC addresses", 631 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 632 return -ENOMEM; 633 } 634 635 /* Copy the permanent MAC address */ 636 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 637 ð_dev->data->mac_addrs[0]); 638 639 /* Allocate memory for storing hash filter MAC addresses */ 640 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe", 641 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0); 642 if (eth_dev->data->hash_mac_addrs == NULL) { 643 PMD_INIT_LOG(ERR, 644 "Failed to allocate %d bytes needed to store MAC addresses", 645 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC); 646 return -ENOMEM; 647 } 648 649 /* initialize the vfta */ 650 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 651 652 /* initialize the hw strip bitmap*/ 653 memset(hwstrip, 0, sizeof(*hwstrip)); 654 655 /* initialize PF if max_vfs not zero */ 656 ret = txgbe_pf_host_init(eth_dev); 657 if (ret) { 658 rte_free(eth_dev->data->mac_addrs); 659 eth_dev->data->mac_addrs = NULL; 660 rte_free(eth_dev->data->hash_mac_addrs); 661 eth_dev->data->hash_mac_addrs = NULL; 662 return ret; 663 } 664 665 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 666 /* let hardware know driver is loaded */ 667 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD; 668 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 669 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 670 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 671 txgbe_flush(hw); 672 673 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present) 674 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 675 (int)hw->mac.type, (int)hw->phy.type, 676 (int)hw->phy.sfp_type); 677 else 678 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 679 (int)hw->mac.type, (int)hw->phy.type); 680 681 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 682 eth_dev->data->port_id, pci_dev->id.vendor_id, 683 pci_dev->id.device_id); 684 685 rte_intr_callback_register(intr_handle, 686 txgbe_dev_interrupt_handler, eth_dev); 687 688 /* enable uio/vfio intr/eventfd mapping */ 689 rte_intr_enable(intr_handle); 690 691 /* enable support intr */ 692 txgbe_enable_intr(eth_dev); 693 694 /* initialize filter info */ 695 memset(filter_info, 0, 696 sizeof(struct txgbe_filter_info)); 697 698 /* initialize 5tuple filter list */ 699 TAILQ_INIT(&filter_info->fivetuple_list); 700 701 /* initialize flow director filter list & hash */ 702 txgbe_fdir_filter_init(eth_dev); 703 704 /* initialize l2 tunnel filter list & hash */ 705 txgbe_l2_tn_filter_init(eth_dev); 706 707 /* initialize flow filter lists */ 708 txgbe_filterlist_init(); 709 710 /* initialize bandwidth configuration info */ 711 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf)); 712 713 /* initialize Traffic Manager configuration */ 714 txgbe_tm_conf_init(eth_dev); 715 716 return 0; 717 } 718 719 static int 720 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev) 721 { 722 PMD_INIT_FUNC_TRACE(); 723 724 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 725 return 0; 726 727 txgbe_dev_close(eth_dev); 728 729 return 0; 730 } 731 732 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 733 { 734 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 735 struct txgbe_5tuple_filter *p_5tuple; 736 737 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 738 TAILQ_REMOVE(&filter_info->fivetuple_list, 739 p_5tuple, 740 entries); 741 rte_free(p_5tuple); 742 } 743 memset(filter_info->fivetuple_mask, 0, 744 sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE); 745 746 return 0; 747 } 748 749 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 750 { 751 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 752 struct txgbe_fdir_filter *fdir_filter; 753 754 if (fdir_info->hash_map) 755 rte_free(fdir_info->hash_map); 756 if (fdir_info->hash_handle) 757 rte_hash_free(fdir_info->hash_handle); 758 759 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 760 TAILQ_REMOVE(&fdir_info->fdir_list, 761 fdir_filter, 762 entries); 763 rte_free(fdir_filter); 764 } 765 766 return 0; 767 } 768 769 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 770 { 771 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 772 struct txgbe_l2_tn_filter *l2_tn_filter; 773 774 if (l2_tn_info->hash_map) 775 rte_free(l2_tn_info->hash_map); 776 if (l2_tn_info->hash_handle) 777 rte_hash_free(l2_tn_info->hash_handle); 778 779 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 780 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 781 l2_tn_filter, 782 entries); 783 rte_free(l2_tn_filter); 784 } 785 786 return 0; 787 } 788 789 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 790 { 791 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 792 char fdir_hash_name[RTE_HASH_NAMESIZE]; 793 struct rte_hash_parameters fdir_hash_params = { 794 .name = fdir_hash_name, 795 .entries = TXGBE_MAX_FDIR_FILTER_NUM, 796 .key_len = sizeof(struct txgbe_atr_input), 797 .hash_func = rte_hash_crc, 798 .hash_func_init_val = 0, 799 .socket_id = rte_socket_id(), 800 }; 801 802 TAILQ_INIT(&fdir_info->fdir_list); 803 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 804 "fdir_%s", TDEV_NAME(eth_dev)); 805 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 806 if (!fdir_info->hash_handle) { 807 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 808 return -EINVAL; 809 } 810 fdir_info->hash_map = rte_zmalloc("txgbe", 811 sizeof(struct txgbe_fdir_filter *) * 812 TXGBE_MAX_FDIR_FILTER_NUM, 813 0); 814 if (!fdir_info->hash_map) { 815 PMD_INIT_LOG(ERR, 816 "Failed to allocate memory for fdir hash map!"); 817 return -ENOMEM; 818 } 819 fdir_info->mask_added = FALSE; 820 821 return 0; 822 } 823 824 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 825 { 826 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 827 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 828 struct rte_hash_parameters l2_tn_hash_params = { 829 .name = l2_tn_hash_name, 830 .entries = TXGBE_MAX_L2_TN_FILTER_NUM, 831 .key_len = sizeof(struct txgbe_l2_tn_key), 832 .hash_func = rte_hash_crc, 833 .hash_func_init_val = 0, 834 .socket_id = rte_socket_id(), 835 }; 836 837 TAILQ_INIT(&l2_tn_info->l2_tn_list); 838 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 839 "l2_tn_%s", TDEV_NAME(eth_dev)); 840 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 841 if (!l2_tn_info->hash_handle) { 842 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 843 return -EINVAL; 844 } 845 l2_tn_info->hash_map = rte_zmalloc("txgbe", 846 sizeof(struct txgbe_l2_tn_filter *) * 847 TXGBE_MAX_L2_TN_FILTER_NUM, 848 0); 849 if (!l2_tn_info->hash_map) { 850 PMD_INIT_LOG(ERR, 851 "Failed to allocate memory for L2 TN hash map!"); 852 return -ENOMEM; 853 } 854 l2_tn_info->e_tag_en = FALSE; 855 l2_tn_info->e_tag_fwd_en = FALSE; 856 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 857 858 return 0; 859 } 860 861 static int 862 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 863 struct rte_pci_device *pci_dev) 864 { 865 struct rte_eth_dev *pf_ethdev; 866 struct rte_eth_devargs eth_da; 867 int retval; 868 869 if (pci_dev->device.devargs) { 870 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 871 ð_da); 872 if (retval) 873 return retval; 874 } else { 875 memset(ð_da, 0, sizeof(eth_da)); 876 } 877 878 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 879 sizeof(struct txgbe_adapter), 880 eth_dev_pci_specific_init, pci_dev, 881 eth_txgbe_dev_init, NULL); 882 883 if (retval || eth_da.nb_representor_ports < 1) 884 return retval; 885 if (eth_da.type != RTE_ETH_REPRESENTOR_VF) 886 return -ENOTSUP; 887 888 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 889 if (pf_ethdev == NULL) 890 return -ENODEV; 891 892 return 0; 893 } 894 895 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev) 896 { 897 struct rte_eth_dev *ethdev; 898 899 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 900 if (!ethdev) 901 return -ENODEV; 902 903 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit); 904 } 905 906 static struct rte_pci_driver rte_txgbe_pmd = { 907 .id_table = pci_id_txgbe_map, 908 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | 909 RTE_PCI_DRV_INTR_LSC, 910 .probe = eth_txgbe_pci_probe, 911 .remove = eth_txgbe_pci_remove, 912 }; 913 914 static int 915 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 916 { 917 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 918 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 919 uint32_t vfta; 920 uint32_t vid_idx; 921 uint32_t vid_bit; 922 923 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F); 924 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F)); 925 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx)); 926 if (on) 927 vfta |= vid_bit; 928 else 929 vfta &= ~vid_bit; 930 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta); 931 932 /* update local VFTA copy */ 933 shadow_vfta->vfta[vid_idx] = vfta; 934 935 return 0; 936 } 937 938 static void 939 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 940 { 941 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 942 struct txgbe_rx_queue *rxq; 943 bool restart; 944 uint32_t rxcfg, rxbal, rxbah; 945 946 if (on) 947 txgbe_vlan_hw_strip_enable(dev, queue); 948 else 949 txgbe_vlan_hw_strip_disable(dev, queue); 950 951 rxq = dev->data->rx_queues[queue]; 952 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx)); 953 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx)); 954 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx)); 955 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 956 restart = (rxcfg & TXGBE_RXCFG_ENA) && 957 !(rxcfg & TXGBE_RXCFG_VLAN); 958 rxcfg |= TXGBE_RXCFG_VLAN; 959 } else { 960 restart = (rxcfg & TXGBE_RXCFG_ENA) && 961 (rxcfg & TXGBE_RXCFG_VLAN); 962 rxcfg &= ~TXGBE_RXCFG_VLAN; 963 } 964 rxcfg &= ~TXGBE_RXCFG_ENA; 965 966 if (restart) { 967 /* set vlan strip for ring */ 968 txgbe_dev_rx_queue_stop(dev, queue); 969 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal); 970 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah); 971 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg); 972 txgbe_dev_rx_queue_start(dev, queue); 973 } 974 } 975 976 static int 977 txgbe_vlan_tpid_set(struct rte_eth_dev *dev, 978 enum rte_vlan_type vlan_type, 979 uint16_t tpid) 980 { 981 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 982 int ret = 0; 983 uint32_t portctrl, vlan_ext, qinq; 984 985 portctrl = rd32(hw, TXGBE_PORTCTL); 986 987 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT); 988 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ); 989 switch (vlan_type) { 990 case ETH_VLAN_TYPE_INNER: 991 if (vlan_ext) { 992 wr32m(hw, TXGBE_VLANCTL, 993 TXGBE_VLANCTL_TPID_MASK, 994 TXGBE_VLANCTL_TPID(tpid)); 995 wr32m(hw, TXGBE_DMATXCTRL, 996 TXGBE_DMATXCTRL_TPID_MASK, 997 TXGBE_DMATXCTRL_TPID(tpid)); 998 } else { 999 ret = -ENOTSUP; 1000 PMD_DRV_LOG(ERR, "Inner type is not supported" 1001 " by single VLAN"); 1002 } 1003 1004 if (qinq) { 1005 wr32m(hw, TXGBE_TAGTPID(0), 1006 TXGBE_TAGTPID_LSB_MASK, 1007 TXGBE_TAGTPID_LSB(tpid)); 1008 } 1009 break; 1010 case ETH_VLAN_TYPE_OUTER: 1011 if (vlan_ext) { 1012 /* Only the high 16-bits is valid */ 1013 wr32m(hw, TXGBE_EXTAG, 1014 TXGBE_EXTAG_VLAN_MASK, 1015 TXGBE_EXTAG_VLAN(tpid)); 1016 } else { 1017 wr32m(hw, TXGBE_VLANCTL, 1018 TXGBE_VLANCTL_TPID_MASK, 1019 TXGBE_VLANCTL_TPID(tpid)); 1020 wr32m(hw, TXGBE_DMATXCTRL, 1021 TXGBE_DMATXCTRL_TPID_MASK, 1022 TXGBE_DMATXCTRL_TPID(tpid)); 1023 } 1024 1025 if (qinq) { 1026 wr32m(hw, TXGBE_TAGTPID(0), 1027 TXGBE_TAGTPID_MSB_MASK, 1028 TXGBE_TAGTPID_MSB(tpid)); 1029 } 1030 break; 1031 default: 1032 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1033 return -EINVAL; 1034 } 1035 1036 return ret; 1037 } 1038 1039 void 1040 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1041 { 1042 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1043 uint32_t vlnctrl; 1044 1045 PMD_INIT_FUNC_TRACE(); 1046 1047 /* Filter Table Disable */ 1048 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1049 vlnctrl &= ~TXGBE_VLANCTL_VFE; 1050 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1051 } 1052 1053 void 1054 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1055 { 1056 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1057 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 1058 uint32_t vlnctrl; 1059 uint16_t i; 1060 1061 PMD_INIT_FUNC_TRACE(); 1062 1063 /* Filter Table Enable */ 1064 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1065 vlnctrl &= ~TXGBE_VLANCTL_CFIENA; 1066 vlnctrl |= TXGBE_VLANCTL_VFE; 1067 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1068 1069 /* write whatever is in local vfta copy */ 1070 for (i = 0; i < TXGBE_VFTA_SIZE; i++) 1071 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]); 1072 } 1073 1074 void 1075 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1076 { 1077 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev); 1078 struct txgbe_rx_queue *rxq; 1079 1080 if (queue >= TXGBE_MAX_RX_QUEUE_NUM) 1081 return; 1082 1083 if (on) 1084 TXGBE_SET_HWSTRIP(hwstrip, queue); 1085 else 1086 TXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1087 1088 if (queue >= dev->data->nb_rx_queues) 1089 return; 1090 1091 rxq = dev->data->rx_queues[queue]; 1092 1093 if (on) { 1094 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1095 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1096 } else { 1097 rxq->vlan_flags = PKT_RX_VLAN; 1098 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1099 } 1100 } 1101 1102 static void 1103 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1104 { 1105 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1106 uint32_t ctrl; 1107 1108 PMD_INIT_FUNC_TRACE(); 1109 1110 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1111 ctrl &= ~TXGBE_RXCFG_VLAN; 1112 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1113 1114 /* record those setting for HW strip per queue */ 1115 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 1116 } 1117 1118 static void 1119 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 1120 { 1121 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1122 uint32_t ctrl; 1123 1124 PMD_INIT_FUNC_TRACE(); 1125 1126 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1127 ctrl |= TXGBE_RXCFG_VLAN; 1128 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1129 1130 /* record those setting for HW strip per queue */ 1131 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 1132 } 1133 1134 static void 1135 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 1136 { 1137 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1138 uint32_t ctrl; 1139 1140 PMD_INIT_FUNC_TRACE(); 1141 1142 ctrl = rd32(hw, TXGBE_PORTCTL); 1143 ctrl &= ~TXGBE_PORTCTL_VLANEXT; 1144 ctrl &= ~TXGBE_PORTCTL_QINQ; 1145 wr32(hw, TXGBE_PORTCTL, ctrl); 1146 } 1147 1148 static void 1149 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 1150 { 1151 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1152 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1153 struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode; 1154 uint32_t ctrl; 1155 1156 PMD_INIT_FUNC_TRACE(); 1157 1158 ctrl = rd32(hw, TXGBE_PORTCTL); 1159 ctrl |= TXGBE_PORTCTL_VLANEXT; 1160 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP || 1161 txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT) 1162 ctrl |= TXGBE_PORTCTL_QINQ; 1163 wr32(hw, TXGBE_PORTCTL, ctrl); 1164 } 1165 1166 void 1167 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 1168 { 1169 struct txgbe_rx_queue *rxq; 1170 uint16_t i; 1171 1172 PMD_INIT_FUNC_TRACE(); 1173 1174 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1175 rxq = dev->data->rx_queues[i]; 1176 1177 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1178 txgbe_vlan_strip_queue_set(dev, i, 1); 1179 else 1180 txgbe_vlan_strip_queue_set(dev, i, 0); 1181 } 1182 } 1183 1184 void 1185 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 1186 { 1187 uint16_t i; 1188 struct rte_eth_rxmode *rxmode; 1189 struct txgbe_rx_queue *rxq; 1190 1191 if (mask & ETH_VLAN_STRIP_MASK) { 1192 rxmode = &dev->data->dev_conf.rxmode; 1193 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1194 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1195 rxq = dev->data->rx_queues[i]; 1196 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1197 } 1198 else 1199 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1200 rxq = dev->data->rx_queues[i]; 1201 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1202 } 1203 } 1204 } 1205 1206 static int 1207 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 1208 { 1209 struct rte_eth_rxmode *rxmode; 1210 rxmode = &dev->data->dev_conf.rxmode; 1211 1212 if (mask & ETH_VLAN_STRIP_MASK) 1213 txgbe_vlan_hw_strip_config(dev); 1214 1215 if (mask & ETH_VLAN_FILTER_MASK) { 1216 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1217 txgbe_vlan_hw_filter_enable(dev); 1218 else 1219 txgbe_vlan_hw_filter_disable(dev); 1220 } 1221 1222 if (mask & ETH_VLAN_EXTEND_MASK) { 1223 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 1224 txgbe_vlan_hw_extend_enable(dev); 1225 else 1226 txgbe_vlan_hw_extend_disable(dev); 1227 } 1228 1229 return 0; 1230 } 1231 1232 static int 1233 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1234 { 1235 txgbe_config_vlan_strip_on_all_queues(dev, mask); 1236 1237 txgbe_vlan_offload_config(dev, mask); 1238 1239 return 0; 1240 } 1241 1242 static void 1243 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1244 { 1245 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1246 /* VLNCTL: enable vlan filtering and allow all vlan tags through */ 1247 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL); 1248 1249 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */ 1250 wr32(hw, TXGBE_VLANCTL, vlanctrl); 1251 } 1252 1253 static int 1254 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 1255 { 1256 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1257 1258 switch (nb_rx_q) { 1259 case 1: 1260 case 2: 1261 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 1262 break; 1263 case 4: 1264 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 1265 break; 1266 default: 1267 return -EINVAL; 1268 } 1269 1270 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1271 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1272 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 1273 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1274 return 0; 1275 } 1276 1277 static int 1278 txgbe_check_mq_mode(struct rte_eth_dev *dev) 1279 { 1280 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1281 uint16_t nb_rx_q = dev->data->nb_rx_queues; 1282 uint16_t nb_tx_q = dev->data->nb_tx_queues; 1283 1284 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 1285 /* check multi-queue mode */ 1286 switch (dev_conf->rxmode.mq_mode) { 1287 case ETH_MQ_RX_VMDQ_DCB: 1288 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 1289 break; 1290 case ETH_MQ_RX_VMDQ_DCB_RSS: 1291 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 1292 PMD_INIT_LOG(ERR, "SRIOV active," 1293 " unsupported mq_mode rx %d.", 1294 dev_conf->rxmode.mq_mode); 1295 return -EINVAL; 1296 case ETH_MQ_RX_RSS: 1297 case ETH_MQ_RX_VMDQ_RSS: 1298 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 1299 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 1300 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 1301 PMD_INIT_LOG(ERR, "SRIOV is active," 1302 " invalid queue number" 1303 " for VMDQ RSS, allowed" 1304 " value are 1, 2 or 4."); 1305 return -EINVAL; 1306 } 1307 break; 1308 case ETH_MQ_RX_VMDQ_ONLY: 1309 case ETH_MQ_RX_NONE: 1310 /* if nothing mq mode configure, use default scheme */ 1311 dev->data->dev_conf.rxmode.mq_mode = 1312 ETH_MQ_RX_VMDQ_ONLY; 1313 break; 1314 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 1315 /* SRIOV only works in VMDq enable mode */ 1316 PMD_INIT_LOG(ERR, "SRIOV is active," 1317 " wrong mq_mode rx %d.", 1318 dev_conf->rxmode.mq_mode); 1319 return -EINVAL; 1320 } 1321 1322 switch (dev_conf->txmode.mq_mode) { 1323 case ETH_MQ_TX_VMDQ_DCB: 1324 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 1325 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 1326 break; 1327 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 1328 dev->data->dev_conf.txmode.mq_mode = 1329 ETH_MQ_TX_VMDQ_ONLY; 1330 break; 1331 } 1332 1333 /* check valid queue number */ 1334 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 1335 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 1336 PMD_INIT_LOG(ERR, "SRIOV is active," 1337 " nb_rx_q=%d nb_tx_q=%d queue number" 1338 " must be less than or equal to %d.", 1339 nb_rx_q, nb_tx_q, 1340 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 1341 return -EINVAL; 1342 } 1343 } else { 1344 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 1345 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 1346 " not supported."); 1347 return -EINVAL; 1348 } 1349 /* check configuration for vmdb+dcb mode */ 1350 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 1351 const struct rte_eth_vmdq_dcb_conf *conf; 1352 1353 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1354 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 1355 TXGBE_VMDQ_DCB_NB_QUEUES); 1356 return -EINVAL; 1357 } 1358 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 1359 if (!(conf->nb_queue_pools == ETH_16_POOLS || 1360 conf->nb_queue_pools == ETH_32_POOLS)) { 1361 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1362 " nb_queue_pools must be %d or %d.", 1363 ETH_16_POOLS, ETH_32_POOLS); 1364 return -EINVAL; 1365 } 1366 } 1367 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 1368 const struct rte_eth_vmdq_dcb_tx_conf *conf; 1369 1370 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1371 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 1372 TXGBE_VMDQ_DCB_NB_QUEUES); 1373 return -EINVAL; 1374 } 1375 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 1376 if (!(conf->nb_queue_pools == ETH_16_POOLS || 1377 conf->nb_queue_pools == ETH_32_POOLS)) { 1378 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1379 " nb_queue_pools != %d and" 1380 " nb_queue_pools != %d.", 1381 ETH_16_POOLS, ETH_32_POOLS); 1382 return -EINVAL; 1383 } 1384 } 1385 1386 /* For DCB mode check our configuration before we go further */ 1387 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 1388 const struct rte_eth_dcb_rx_conf *conf; 1389 1390 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 1391 if (!(conf->nb_tcs == ETH_4_TCS || 1392 conf->nb_tcs == ETH_8_TCS)) { 1393 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1394 " and nb_tcs != %d.", 1395 ETH_4_TCS, ETH_8_TCS); 1396 return -EINVAL; 1397 } 1398 } 1399 1400 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 1401 const struct rte_eth_dcb_tx_conf *conf; 1402 1403 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 1404 if (!(conf->nb_tcs == ETH_4_TCS || 1405 conf->nb_tcs == ETH_8_TCS)) { 1406 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1407 " and nb_tcs != %d.", 1408 ETH_4_TCS, ETH_8_TCS); 1409 return -EINVAL; 1410 } 1411 } 1412 } 1413 return 0; 1414 } 1415 1416 static int 1417 txgbe_dev_configure(struct rte_eth_dev *dev) 1418 { 1419 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1420 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1421 int ret; 1422 1423 PMD_INIT_FUNC_TRACE(); 1424 1425 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1426 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1427 1428 /* multiple queue mode checking */ 1429 ret = txgbe_check_mq_mode(dev); 1430 if (ret != 0) { 1431 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.", 1432 ret); 1433 return ret; 1434 } 1435 1436 /* set flag to update link status after init */ 1437 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 1438 1439 /* 1440 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 1441 * allocation Rx preconditions we will reset it. 1442 */ 1443 adapter->rx_bulk_alloc_allowed = true; 1444 1445 return 0; 1446 } 1447 1448 static void 1449 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 1450 { 1451 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1452 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1453 uint32_t gpie; 1454 1455 gpie = rd32(hw, TXGBE_GPIOINTEN); 1456 gpie |= TXGBE_GPIOBIT_6; 1457 wr32(hw, TXGBE_GPIOINTEN, gpie); 1458 intr->mask_misc |= TXGBE_ICRMISC_GPIO; 1459 } 1460 1461 int 1462 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 1463 uint16_t tx_rate, uint64_t q_msk) 1464 { 1465 struct txgbe_hw *hw; 1466 struct txgbe_vf_info *vfinfo; 1467 struct rte_eth_link link; 1468 uint8_t nb_q_per_pool; 1469 uint32_t queue_stride; 1470 uint32_t queue_idx, idx = 0, vf_idx; 1471 uint32_t queue_end; 1472 uint16_t total_rate = 0; 1473 struct rte_pci_device *pci_dev; 1474 int ret; 1475 1476 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1477 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 1478 if (ret < 0) 1479 return ret; 1480 1481 if (vf >= pci_dev->max_vfs) 1482 return -EINVAL; 1483 1484 if (tx_rate > link.link_speed) 1485 return -EINVAL; 1486 1487 if (q_msk == 0) 1488 return 0; 1489 1490 hw = TXGBE_DEV_HW(dev); 1491 vfinfo = *(TXGBE_DEV_VFDATA(dev)); 1492 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1493 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1494 queue_idx = vf * queue_stride; 1495 queue_end = queue_idx + nb_q_per_pool - 1; 1496 if (queue_end >= hw->mac.max_tx_queues) 1497 return -EINVAL; 1498 1499 if (vfinfo) { 1500 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 1501 if (vf_idx == vf) 1502 continue; 1503 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 1504 idx++) 1505 total_rate += vfinfo[vf_idx].tx_rate[idx]; 1506 } 1507 } else { 1508 return -EINVAL; 1509 } 1510 1511 /* Store tx_rate for this vf. */ 1512 for (idx = 0; idx < nb_q_per_pool; idx++) { 1513 if (((uint64_t)0x1 << idx) & q_msk) { 1514 if (vfinfo[vf].tx_rate[idx] != tx_rate) 1515 vfinfo[vf].tx_rate[idx] = tx_rate; 1516 total_rate += tx_rate; 1517 } 1518 } 1519 1520 if (total_rate > dev->data->dev_link.link_speed) { 1521 /* Reset stored TX rate of the VF if it causes exceed 1522 * link speed. 1523 */ 1524 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 1525 return -EINVAL; 1526 } 1527 1528 /* Set ARBTXRATE of each queue/pool for vf X */ 1529 for (; queue_idx <= queue_end; queue_idx++) { 1530 if (0x1 & q_msk) 1531 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 1532 q_msk = q_msk >> 1; 1533 } 1534 1535 return 0; 1536 } 1537 1538 /* 1539 * Configure device link speed and setup link. 1540 * It returns 0 on success. 1541 */ 1542 static int 1543 txgbe_dev_start(struct rte_eth_dev *dev) 1544 { 1545 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1546 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 1547 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1548 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1549 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1550 uint32_t intr_vector = 0; 1551 int err; 1552 bool link_up = false, negotiate = 0; 1553 uint32_t speed = 0; 1554 uint32_t allowed_speeds = 0; 1555 int mask = 0; 1556 int status; 1557 uint16_t vf, idx; 1558 uint32_t *link_speeds; 1559 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1560 1561 PMD_INIT_FUNC_TRACE(); 1562 1563 /* TXGBE devices don't support: 1564 * - half duplex (checked afterwards for valid speeds) 1565 * - fixed speed: TODO implement 1566 */ 1567 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 1568 PMD_INIT_LOG(ERR, 1569 "Invalid link_speeds for port %u, fix speed not supported", 1570 dev->data->port_id); 1571 return -EINVAL; 1572 } 1573 1574 /* Stop the link setup handler before resetting the HW. */ 1575 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1576 1577 /* disable uio/vfio intr/eventfd mapping */ 1578 rte_intr_disable(intr_handle); 1579 1580 /* stop adapter */ 1581 hw->adapter_stopped = 0; 1582 txgbe_stop_hw(hw); 1583 1584 /* reinitialize adapter 1585 * this calls reset and start 1586 */ 1587 hw->nb_rx_queues = dev->data->nb_rx_queues; 1588 hw->nb_tx_queues = dev->data->nb_tx_queues; 1589 status = txgbe_pf_reset_hw(hw); 1590 if (status != 0) 1591 return -1; 1592 hw->mac.start_hw(hw); 1593 hw->mac.get_link_status = true; 1594 1595 /* configure PF module if SRIOV enabled */ 1596 txgbe_pf_host_configure(dev); 1597 1598 txgbe_dev_phy_intr_setup(dev); 1599 1600 /* check and configure queue intr-vector mapping */ 1601 if ((rte_intr_cap_multiple(intr_handle) || 1602 !RTE_ETH_DEV_SRIOV(dev).active) && 1603 dev->data->dev_conf.intr_conf.rxq != 0) { 1604 intr_vector = dev->data->nb_rx_queues; 1605 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1606 return -1; 1607 } 1608 1609 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1610 intr_handle->intr_vec = 1611 rte_zmalloc("intr_vec", 1612 dev->data->nb_rx_queues * sizeof(int), 0); 1613 if (intr_handle->intr_vec == NULL) { 1614 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 1615 " intr_vec", dev->data->nb_rx_queues); 1616 return -ENOMEM; 1617 } 1618 } 1619 1620 /* confiugre msix for sleep until rx interrupt */ 1621 txgbe_configure_msix(dev); 1622 1623 /* initialize transmission unit */ 1624 txgbe_dev_tx_init(dev); 1625 1626 /* This can fail when allocating mbufs for descriptor rings */ 1627 err = txgbe_dev_rx_init(dev); 1628 if (err) { 1629 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 1630 goto error; 1631 } 1632 1633 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 1634 ETH_VLAN_EXTEND_MASK; 1635 err = txgbe_vlan_offload_config(dev, mask); 1636 if (err) { 1637 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 1638 goto error; 1639 } 1640 1641 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 1642 /* Enable vlan filtering for VMDq */ 1643 txgbe_vmdq_vlan_hw_filter_enable(dev); 1644 } 1645 1646 /* Configure DCB hw */ 1647 txgbe_configure_pb(dev); 1648 txgbe_configure_port(dev); 1649 txgbe_configure_dcb(dev); 1650 1651 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1652 err = txgbe_fdir_configure(dev); 1653 if (err) 1654 goto error; 1655 } 1656 1657 /* Restore vf rate limit */ 1658 if (vfinfo != NULL) { 1659 for (vf = 0; vf < pci_dev->max_vfs; vf++) 1660 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 1661 if (vfinfo[vf].tx_rate[idx] != 0) 1662 txgbe_set_vf_rate_limit(dev, vf, 1663 vfinfo[vf].tx_rate[idx], 1664 1 << idx); 1665 } 1666 1667 err = txgbe_dev_rxtx_start(dev); 1668 if (err < 0) { 1669 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 1670 goto error; 1671 } 1672 1673 /* Skip link setup if loopback mode is enabled. */ 1674 if (hw->mac.type == txgbe_mac_raptor && 1675 dev->data->dev_conf.lpbk_mode) 1676 goto skip_link_setup; 1677 1678 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 1679 err = hw->mac.setup_sfp(hw); 1680 if (err) 1681 goto error; 1682 } 1683 1684 if (hw->phy.media_type == txgbe_media_type_copper) { 1685 /* Turn on the copper */ 1686 hw->phy.set_phy_power(hw, true); 1687 } else { 1688 /* Turn on the laser */ 1689 hw->mac.enable_tx_laser(hw); 1690 } 1691 1692 err = hw->mac.check_link(hw, &speed, &link_up, 0); 1693 if (err) 1694 goto error; 1695 dev->data->dev_link.link_status = link_up; 1696 1697 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate); 1698 if (err) 1699 goto error; 1700 1701 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 1702 ETH_LINK_SPEED_10G; 1703 1704 link_speeds = &dev->data->dev_conf.link_speeds; 1705 if (*link_speeds & ~allowed_speeds) { 1706 PMD_INIT_LOG(ERR, "Invalid link setting"); 1707 goto error; 1708 } 1709 1710 speed = 0x0; 1711 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 1712 speed = (TXGBE_LINK_SPEED_100M_FULL | 1713 TXGBE_LINK_SPEED_1GB_FULL | 1714 TXGBE_LINK_SPEED_10GB_FULL); 1715 } else { 1716 if (*link_speeds & ETH_LINK_SPEED_10G) 1717 speed |= TXGBE_LINK_SPEED_10GB_FULL; 1718 if (*link_speeds & ETH_LINK_SPEED_5G) 1719 speed |= TXGBE_LINK_SPEED_5GB_FULL; 1720 if (*link_speeds & ETH_LINK_SPEED_2_5G) 1721 speed |= TXGBE_LINK_SPEED_2_5GB_FULL; 1722 if (*link_speeds & ETH_LINK_SPEED_1G) 1723 speed |= TXGBE_LINK_SPEED_1GB_FULL; 1724 if (*link_speeds & ETH_LINK_SPEED_100M) 1725 speed |= TXGBE_LINK_SPEED_100M_FULL; 1726 } 1727 1728 err = hw->mac.setup_link(hw, speed, link_up); 1729 if (err) 1730 goto error; 1731 1732 skip_link_setup: 1733 1734 if (rte_intr_allow_others(intr_handle)) { 1735 /* check if lsc interrupt is enabled */ 1736 if (dev->data->dev_conf.intr_conf.lsc != 0) 1737 txgbe_dev_lsc_interrupt_setup(dev, TRUE); 1738 else 1739 txgbe_dev_lsc_interrupt_setup(dev, FALSE); 1740 txgbe_dev_macsec_interrupt_setup(dev); 1741 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 1742 } else { 1743 rte_intr_callback_unregister(intr_handle, 1744 txgbe_dev_interrupt_handler, dev); 1745 if (dev->data->dev_conf.intr_conf.lsc != 0) 1746 PMD_INIT_LOG(INFO, "lsc won't enable because of" 1747 " no intr multiplex"); 1748 } 1749 1750 /* check if rxq interrupt is enabled */ 1751 if (dev->data->dev_conf.intr_conf.rxq != 0 && 1752 rte_intr_dp_is_en(intr_handle)) 1753 txgbe_dev_rxq_interrupt_setup(dev); 1754 1755 /* enable uio/vfio intr/eventfd mapping */ 1756 rte_intr_enable(intr_handle); 1757 1758 /* resume enabled intr since hw reset */ 1759 txgbe_enable_intr(dev); 1760 txgbe_l2_tunnel_conf(dev); 1761 txgbe_filter_restore(dev); 1762 1763 if (tm_conf->root && !tm_conf->committed) 1764 PMD_DRV_LOG(WARNING, 1765 "please call hierarchy_commit() " 1766 "before starting the port"); 1767 1768 /* 1769 * Update link status right before return, because it may 1770 * start link configuration process in a separate thread. 1771 */ 1772 txgbe_dev_link_update(dev, 0); 1773 1774 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK); 1775 1776 txgbe_read_stats_registers(hw, hw_stats); 1777 hw->offset_loaded = 1; 1778 1779 return 0; 1780 1781 error: 1782 PMD_INIT_LOG(ERR, "failure in dev start: %d", err); 1783 txgbe_dev_clear_queues(dev); 1784 return -EIO; 1785 } 1786 1787 /* 1788 * Stop device: disable rx and tx functions to allow for reconfiguring. 1789 */ 1790 static int 1791 txgbe_dev_stop(struct rte_eth_dev *dev) 1792 { 1793 struct rte_eth_link link; 1794 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1795 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1796 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1797 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1798 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1799 int vf; 1800 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1801 1802 if (hw->adapter_stopped) 1803 return 0; 1804 1805 PMD_INIT_FUNC_TRACE(); 1806 1807 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1808 1809 /* disable interrupts */ 1810 txgbe_disable_intr(hw); 1811 1812 /* reset the NIC */ 1813 txgbe_pf_reset_hw(hw); 1814 hw->adapter_stopped = 0; 1815 1816 /* stop adapter */ 1817 txgbe_stop_hw(hw); 1818 1819 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 1820 vfinfo[vf].clear_to_send = false; 1821 1822 if (hw->phy.media_type == txgbe_media_type_copper) { 1823 /* Turn off the copper */ 1824 hw->phy.set_phy_power(hw, false); 1825 } else { 1826 /* Turn off the laser */ 1827 hw->mac.disable_tx_laser(hw); 1828 } 1829 1830 txgbe_dev_clear_queues(dev); 1831 1832 /* Clear stored conf */ 1833 dev->data->scattered_rx = 0; 1834 dev->data->lro = 0; 1835 1836 /* Clear recorded link status */ 1837 memset(&link, 0, sizeof(link)); 1838 rte_eth_linkstatus_set(dev, &link); 1839 1840 if (!rte_intr_allow_others(intr_handle)) 1841 /* resume to the default handler */ 1842 rte_intr_callback_register(intr_handle, 1843 txgbe_dev_interrupt_handler, 1844 (void *)dev); 1845 1846 /* Clean datapath event and queue/vec mapping */ 1847 rte_intr_efd_disable(intr_handle); 1848 if (intr_handle->intr_vec != NULL) { 1849 rte_free(intr_handle->intr_vec); 1850 intr_handle->intr_vec = NULL; 1851 } 1852 1853 /* reset hierarchy commit */ 1854 tm_conf->committed = false; 1855 1856 adapter->rss_reta_updated = 0; 1857 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK); 1858 1859 hw->adapter_stopped = true; 1860 dev->data->dev_started = 0; 1861 1862 return 0; 1863 } 1864 1865 /* 1866 * Set device link up: enable tx. 1867 */ 1868 static int 1869 txgbe_dev_set_link_up(struct rte_eth_dev *dev) 1870 { 1871 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1872 1873 if (hw->phy.media_type == txgbe_media_type_copper) { 1874 /* Turn on the copper */ 1875 hw->phy.set_phy_power(hw, true); 1876 } else { 1877 /* Turn on the laser */ 1878 hw->mac.enable_tx_laser(hw); 1879 txgbe_dev_link_update(dev, 0); 1880 } 1881 1882 return 0; 1883 } 1884 1885 /* 1886 * Set device link down: disable tx. 1887 */ 1888 static int 1889 txgbe_dev_set_link_down(struct rte_eth_dev *dev) 1890 { 1891 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1892 1893 if (hw->phy.media_type == txgbe_media_type_copper) { 1894 /* Turn off the copper */ 1895 hw->phy.set_phy_power(hw, false); 1896 } else { 1897 /* Turn off the laser */ 1898 hw->mac.disable_tx_laser(hw); 1899 txgbe_dev_link_update(dev, 0); 1900 } 1901 1902 return 0; 1903 } 1904 1905 /* 1906 * Reset and stop device. 1907 */ 1908 static int 1909 txgbe_dev_close(struct rte_eth_dev *dev) 1910 { 1911 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1912 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1913 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1914 int retries = 0; 1915 int ret; 1916 1917 PMD_INIT_FUNC_TRACE(); 1918 1919 txgbe_pf_reset_hw(hw); 1920 1921 ret = txgbe_dev_stop(dev); 1922 1923 txgbe_dev_free_queues(dev); 1924 1925 /* reprogram the RAR[0] in case user changed it. */ 1926 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true); 1927 1928 /* Unlock any pending hardware semaphore */ 1929 txgbe_swfw_lock_reset(hw); 1930 1931 /* disable uio intr before callback unregister */ 1932 rte_intr_disable(intr_handle); 1933 1934 do { 1935 ret = rte_intr_callback_unregister(intr_handle, 1936 txgbe_dev_interrupt_handler, dev); 1937 if (ret >= 0 || ret == -ENOENT) { 1938 break; 1939 } else if (ret != -EAGAIN) { 1940 PMD_INIT_LOG(ERR, 1941 "intr callback unregister failed: %d", 1942 ret); 1943 } 1944 rte_delay_ms(100); 1945 } while (retries++ < (10 + TXGBE_LINK_UP_TIME)); 1946 1947 /* cancel the delay handler before remove dev */ 1948 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev); 1949 1950 /* uninitialize PF if max_vfs not zero */ 1951 txgbe_pf_host_uninit(dev); 1952 1953 rte_free(dev->data->mac_addrs); 1954 dev->data->mac_addrs = NULL; 1955 1956 rte_free(dev->data->hash_mac_addrs); 1957 dev->data->hash_mac_addrs = NULL; 1958 1959 /* remove all the fdir filters & hash */ 1960 txgbe_fdir_filter_uninit(dev); 1961 1962 /* remove all the L2 tunnel filters & hash */ 1963 txgbe_l2_tn_filter_uninit(dev); 1964 1965 /* Remove all ntuple filters of the device */ 1966 txgbe_ntuple_filter_uninit(dev); 1967 1968 /* clear all the filters list */ 1969 txgbe_filterlist_flush(); 1970 1971 /* Remove all Traffic Manager configuration */ 1972 txgbe_tm_conf_uninit(dev); 1973 1974 #ifdef RTE_LIB_SECURITY 1975 rte_free(dev->security_ctx); 1976 #endif 1977 1978 return ret; 1979 } 1980 1981 /* 1982 * Reset PF device. 1983 */ 1984 static int 1985 txgbe_dev_reset(struct rte_eth_dev *dev) 1986 { 1987 int ret; 1988 1989 /* When a DPDK PMD PF begin to reset PF port, it should notify all 1990 * its VF to make them align with it. The detailed notification 1991 * mechanism is PMD specific. As to txgbe PF, it is rather complex. 1992 * To avoid unexpected behavior in VF, currently reset of PF with 1993 * SR-IOV activation is not supported. It might be supported later. 1994 */ 1995 if (dev->data->sriov.active) 1996 return -ENOTSUP; 1997 1998 ret = eth_txgbe_dev_uninit(dev); 1999 if (ret) 2000 return ret; 2001 2002 ret = eth_txgbe_dev_init(dev, NULL); 2003 2004 return ret; 2005 } 2006 2007 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \ 2008 { \ 2009 uint32_t current_counter = rd32(hw, reg); \ 2010 if (current_counter < last_counter) \ 2011 current_counter += 0x100000000LL; \ 2012 if (!hw->offset_loaded) \ 2013 last_counter = current_counter; \ 2014 counter = current_counter - last_counter; \ 2015 counter &= 0xFFFFFFFFLL; \ 2016 } 2017 2018 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ 2019 { \ 2020 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \ 2021 uint64_t current_counter_msb = rd32(hw, reg_msb); \ 2022 uint64_t current_counter = (current_counter_msb << 32) | \ 2023 current_counter_lsb; \ 2024 if (current_counter < last_counter) \ 2025 current_counter += 0x1000000000LL; \ 2026 if (!hw->offset_loaded) \ 2027 last_counter = current_counter; \ 2028 counter = current_counter - last_counter; \ 2029 counter &= 0xFFFFFFFFFLL; \ 2030 } 2031 2032 void 2033 txgbe_read_stats_registers(struct txgbe_hw *hw, 2034 struct txgbe_hw_stats *hw_stats) 2035 { 2036 unsigned int i; 2037 2038 /* QP Stats */ 2039 for (i = 0; i < hw->nb_rx_queues; i++) { 2040 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i), 2041 hw->qp_last[i].rx_qp_packets, 2042 hw_stats->qp[i].rx_qp_packets); 2043 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i), 2044 hw->qp_last[i].rx_qp_bytes, 2045 hw_stats->qp[i].rx_qp_bytes); 2046 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i), 2047 hw->qp_last[i].rx_qp_mc_packets, 2048 hw_stats->qp[i].rx_qp_mc_packets); 2049 } 2050 2051 for (i = 0; i < hw->nb_tx_queues; i++) { 2052 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i), 2053 hw->qp_last[i].tx_qp_packets, 2054 hw_stats->qp[i].tx_qp_packets); 2055 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i), 2056 hw->qp_last[i].tx_qp_bytes, 2057 hw_stats->qp[i].tx_qp_bytes); 2058 } 2059 /* PB Stats */ 2060 for (i = 0; i < TXGBE_MAX_UP; i++) { 2061 hw_stats->up[i].rx_up_xon_packets += 2062 rd32(hw, TXGBE_PBRXUPXON(i)); 2063 hw_stats->up[i].rx_up_xoff_packets += 2064 rd32(hw, TXGBE_PBRXUPXOFF(i)); 2065 hw_stats->up[i].tx_up_xon_packets += 2066 rd32(hw, TXGBE_PBTXUPXON(i)); 2067 hw_stats->up[i].tx_up_xoff_packets += 2068 rd32(hw, TXGBE_PBTXUPXOFF(i)); 2069 hw_stats->up[i].tx_up_xon2off_packets += 2070 rd32(hw, TXGBE_PBTXUPOFF(i)); 2071 hw_stats->up[i].rx_up_dropped += 2072 rd32(hw, TXGBE_PBRXMISS(i)); 2073 } 2074 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON); 2075 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF); 2076 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON); 2077 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF); 2078 2079 /* DMA Stats */ 2080 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT); 2081 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT); 2082 2083 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL); 2084 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL); 2085 hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP); 2086 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP); 2087 2088 /* MAC Stats */ 2089 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL); 2090 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL); 2091 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL); 2092 2093 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL); 2094 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL); 2095 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL); 2096 2097 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL); 2098 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL); 2099 2100 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L); 2101 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L); 2102 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L); 2103 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L); 2104 hw_stats->rx_size_512_to_1023_packets += 2105 rd64(hw, TXGBE_MACRX512TO1023L); 2106 hw_stats->rx_size_1024_to_max_packets += 2107 rd64(hw, TXGBE_MACRX1024TOMAXL); 2108 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L); 2109 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L); 2110 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L); 2111 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L); 2112 hw_stats->tx_size_512_to_1023_packets += 2113 rd64(hw, TXGBE_MACTX512TO1023L); 2114 hw_stats->tx_size_1024_to_max_packets += 2115 rd64(hw, TXGBE_MACTX1024TOMAXL); 2116 2117 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL); 2118 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE); 2119 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER); 2120 2121 /* MNG Stats */ 2122 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS); 2123 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC); 2124 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG); 2125 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG); 2126 2127 /* FCoE Stats */ 2128 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC); 2129 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST); 2130 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC); 2131 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC); 2132 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC); 2133 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC); 2134 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC); 2135 2136 /* Flow Director Stats */ 2137 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH); 2138 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS); 2139 hw_stats->flow_director_added_filters += 2140 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED)); 2141 hw_stats->flow_director_removed_filters += 2142 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED)); 2143 hw_stats->flow_director_filter_add_errors += 2144 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL)); 2145 hw_stats->flow_director_filter_remove_errors += 2146 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL)); 2147 2148 /* MACsec Stats */ 2149 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT); 2150 hw_stats->tx_macsec_pkts_encrypted += 2151 rd32(hw, TXGBE_LSECTX_ENCPKT); 2152 hw_stats->tx_macsec_pkts_protected += 2153 rd32(hw, TXGBE_LSECTX_PROTPKT); 2154 hw_stats->tx_macsec_octets_encrypted += 2155 rd32(hw, TXGBE_LSECTX_ENCOCT); 2156 hw_stats->tx_macsec_octets_protected += 2157 rd32(hw, TXGBE_LSECTX_PROTOCT); 2158 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT); 2159 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT); 2160 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT); 2161 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT); 2162 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT); 2163 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT); 2164 hw_stats->rx_macsec_sc_pkts_unchecked += 2165 rd32(hw, TXGBE_LSECRX_UNCHKPKT); 2166 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT); 2167 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT); 2168 for (i = 0; i < 2; i++) { 2169 hw_stats->rx_macsec_sa_pkts_ok += 2170 rd32(hw, TXGBE_LSECRX_OKPKT(i)); 2171 hw_stats->rx_macsec_sa_pkts_invalid += 2172 rd32(hw, TXGBE_LSECRX_INVPKT(i)); 2173 hw_stats->rx_macsec_sa_pkts_notvalid += 2174 rd32(hw, TXGBE_LSECRX_BADPKT(i)); 2175 } 2176 hw_stats->rx_macsec_sa_pkts_unusedsa += 2177 rd32(hw, TXGBE_LSECRX_INVSAPKT); 2178 hw_stats->rx_macsec_sa_pkts_notusingsa += 2179 rd32(hw, TXGBE_LSECRX_BADSAPKT); 2180 2181 hw_stats->rx_total_missed_packets = 0; 2182 for (i = 0; i < TXGBE_MAX_UP; i++) { 2183 hw_stats->rx_total_missed_packets += 2184 hw_stats->up[i].rx_up_dropped; 2185 } 2186 } 2187 2188 static int 2189 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 2190 { 2191 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2192 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2193 struct txgbe_stat_mappings *stat_mappings = 2194 TXGBE_DEV_STAT_MAPPINGS(dev); 2195 uint32_t i, j; 2196 2197 txgbe_read_stats_registers(hw, hw_stats); 2198 2199 if (stats == NULL) 2200 return -EINVAL; 2201 2202 /* Fill out the rte_eth_stats statistics structure */ 2203 stats->ipackets = hw_stats->rx_packets; 2204 stats->ibytes = hw_stats->rx_bytes; 2205 stats->opackets = hw_stats->tx_packets; 2206 stats->obytes = hw_stats->tx_bytes; 2207 2208 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets)); 2209 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets)); 2210 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes)); 2211 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes)); 2212 memset(&stats->q_errors, 0, sizeof(stats->q_errors)); 2213 for (i = 0; i < TXGBE_MAX_QP; i++) { 2214 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG; 2215 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8; 2216 uint32_t q_map; 2217 2218 q_map = (stat_mappings->rqsm[n] >> offset) 2219 & QMAP_FIELD_RESERVED_BITS_MASK; 2220 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2221 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2222 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets; 2223 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes; 2224 2225 q_map = (stat_mappings->tqsm[n] >> offset) 2226 & QMAP_FIELD_RESERVED_BITS_MASK; 2227 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2228 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2229 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets; 2230 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes; 2231 } 2232 2233 /* Rx Errors */ 2234 stats->imissed = hw_stats->rx_total_missed_packets + 2235 hw_stats->rx_dma_drop; 2236 stats->ierrors = hw_stats->rx_crc_errors + 2237 hw_stats->rx_mac_short_packet_dropped + 2238 hw_stats->rx_length_errors + 2239 hw_stats->rx_undersize_errors + 2240 hw_stats->rx_oversize_errors + 2241 hw_stats->rx_drop_packets + 2242 hw_stats->rx_illegal_byte_errors + 2243 hw_stats->rx_error_bytes + 2244 hw_stats->rx_fragment_errors + 2245 hw_stats->rx_fcoe_crc_errors + 2246 hw_stats->rx_fcoe_mbuf_allocation_errors; 2247 2248 /* Tx Errors */ 2249 stats->oerrors = 0; 2250 return 0; 2251 } 2252 2253 static int 2254 txgbe_dev_stats_reset(struct rte_eth_dev *dev) 2255 { 2256 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2257 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2258 2259 /* HW registers are cleared on read */ 2260 hw->offset_loaded = 0; 2261 txgbe_dev_stats_get(dev, NULL); 2262 hw->offset_loaded = 1; 2263 2264 /* Reset software totals */ 2265 memset(hw_stats, 0, sizeof(*hw_stats)); 2266 2267 return 0; 2268 } 2269 2270 /* This function calculates the number of xstats based on the current config */ 2271 static unsigned 2272 txgbe_xstats_calc_num(struct rte_eth_dev *dev) 2273 { 2274 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues); 2275 return TXGBE_NB_HW_STATS + 2276 TXGBE_NB_UP_STATS * TXGBE_MAX_UP + 2277 TXGBE_NB_QP_STATS * nb_queues; 2278 } 2279 2280 static inline int 2281 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size) 2282 { 2283 int nb, st; 2284 2285 /* Extended stats from txgbe_hw_stats */ 2286 if (id < TXGBE_NB_HW_STATS) { 2287 snprintf(name, size, "[hw]%s", 2288 rte_txgbe_stats_strings[id].name); 2289 return 0; 2290 } 2291 id -= TXGBE_NB_HW_STATS; 2292 2293 /* Priority Stats */ 2294 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2295 nb = id / TXGBE_NB_UP_STATS; 2296 st = id % TXGBE_NB_UP_STATS; 2297 snprintf(name, size, "[p%u]%s", nb, 2298 rte_txgbe_up_strings[st].name); 2299 return 0; 2300 } 2301 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2302 2303 /* Queue Stats */ 2304 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2305 nb = id / TXGBE_NB_QP_STATS; 2306 st = id % TXGBE_NB_QP_STATS; 2307 snprintf(name, size, "[q%u]%s", nb, 2308 rte_txgbe_qp_strings[st].name); 2309 return 0; 2310 } 2311 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP; 2312 2313 return -(int)(id + 1); 2314 } 2315 2316 static inline int 2317 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset) 2318 { 2319 int nb, st; 2320 2321 /* Extended stats from txgbe_hw_stats */ 2322 if (id < TXGBE_NB_HW_STATS) { 2323 *offset = rte_txgbe_stats_strings[id].offset; 2324 return 0; 2325 } 2326 id -= TXGBE_NB_HW_STATS; 2327 2328 /* Priority Stats */ 2329 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2330 nb = id / TXGBE_NB_UP_STATS; 2331 st = id % TXGBE_NB_UP_STATS; 2332 *offset = rte_txgbe_up_strings[st].offset + 2333 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t)); 2334 return 0; 2335 } 2336 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2337 2338 /* Queue Stats */ 2339 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2340 nb = id / TXGBE_NB_QP_STATS; 2341 st = id % TXGBE_NB_QP_STATS; 2342 *offset = rte_txgbe_qp_strings[st].offset + 2343 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t)); 2344 return 0; 2345 } 2346 2347 return -1; 2348 } 2349 2350 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 2351 struct rte_eth_xstat_name *xstats_names, unsigned int limit) 2352 { 2353 unsigned int i, count; 2354 2355 count = txgbe_xstats_calc_num(dev); 2356 if (xstats_names == NULL) 2357 return count; 2358 2359 /* Note: limit >= cnt_stats checked upstream 2360 * in rte_eth_xstats_names() 2361 */ 2362 limit = min(limit, count); 2363 2364 /* Extended stats from txgbe_hw_stats */ 2365 for (i = 0; i < limit; i++) { 2366 if (txgbe_get_name_by_id(i, xstats_names[i].name, 2367 sizeof(xstats_names[i].name))) { 2368 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2369 break; 2370 } 2371 } 2372 2373 return i; 2374 } 2375 2376 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 2377 struct rte_eth_xstat_name *xstats_names, 2378 const uint64_t *ids, 2379 unsigned int limit) 2380 { 2381 unsigned int i; 2382 2383 if (ids == NULL) 2384 return txgbe_dev_xstats_get_names(dev, xstats_names, limit); 2385 2386 for (i = 0; i < limit; i++) { 2387 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name, 2388 sizeof(xstats_names[i].name))) { 2389 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2390 return -1; 2391 } 2392 } 2393 2394 return i; 2395 } 2396 2397 static int 2398 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 2399 unsigned int limit) 2400 { 2401 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2402 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2403 unsigned int i, count; 2404 2405 txgbe_read_stats_registers(hw, hw_stats); 2406 2407 /* If this is a reset xstats is NULL, and we have cleared the 2408 * registers by reading them. 2409 */ 2410 count = txgbe_xstats_calc_num(dev); 2411 if (xstats == NULL) 2412 return count; 2413 2414 limit = min(limit, txgbe_xstats_calc_num(dev)); 2415 2416 /* Extended stats from txgbe_hw_stats */ 2417 for (i = 0; i < limit; i++) { 2418 uint32_t offset = 0; 2419 2420 if (txgbe_get_offset_by_id(i, &offset)) { 2421 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2422 break; 2423 } 2424 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset); 2425 xstats[i].id = i; 2426 } 2427 2428 return i; 2429 } 2430 2431 static int 2432 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values, 2433 unsigned int limit) 2434 { 2435 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2436 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2437 unsigned int i, count; 2438 2439 txgbe_read_stats_registers(hw, hw_stats); 2440 2441 /* If this is a reset xstats is NULL, and we have cleared the 2442 * registers by reading them. 2443 */ 2444 count = txgbe_xstats_calc_num(dev); 2445 if (values == NULL) 2446 return count; 2447 2448 limit = min(limit, txgbe_xstats_calc_num(dev)); 2449 2450 /* Extended stats from txgbe_hw_stats */ 2451 for (i = 0; i < limit; i++) { 2452 uint32_t offset; 2453 2454 if (txgbe_get_offset_by_id(i, &offset)) { 2455 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2456 break; 2457 } 2458 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2459 } 2460 2461 return i; 2462 } 2463 2464 static int 2465 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 2466 uint64_t *values, unsigned int limit) 2467 { 2468 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2469 unsigned int i; 2470 2471 if (ids == NULL) 2472 return txgbe_dev_xstats_get_(dev, values, limit); 2473 2474 for (i = 0; i < limit; i++) { 2475 uint32_t offset; 2476 2477 if (txgbe_get_offset_by_id(ids[i], &offset)) { 2478 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2479 break; 2480 } 2481 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2482 } 2483 2484 return i; 2485 } 2486 2487 static int 2488 txgbe_dev_xstats_reset(struct rte_eth_dev *dev) 2489 { 2490 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2491 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2492 2493 /* HW registers are cleared on read */ 2494 hw->offset_loaded = 0; 2495 txgbe_read_stats_registers(hw, hw_stats); 2496 hw->offset_loaded = 1; 2497 2498 /* Reset software totals */ 2499 memset(hw_stats, 0, sizeof(*hw_stats)); 2500 2501 return 0; 2502 } 2503 2504 static int 2505 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2506 { 2507 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2508 u16 eeprom_verh, eeprom_verl; 2509 u32 etrack_id; 2510 int ret; 2511 2512 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh); 2513 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl); 2514 2515 etrack_id = (eeprom_verh << 16) | eeprom_verl; 2516 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 2517 2518 ret += 1; /* add the size of '\0' */ 2519 if (fw_size < (u32)ret) 2520 return ret; 2521 else 2522 return 0; 2523 } 2524 2525 static int 2526 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2527 { 2528 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2529 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2530 2531 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 2532 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 2533 dev_info->min_rx_bufsize = 1024; 2534 dev_info->max_rx_pktlen = 15872; 2535 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 2536 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC; 2537 dev_info->max_vfs = pci_dev->max_vfs; 2538 dev_info->max_vmdq_pools = ETH_64_POOLS; 2539 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 2540 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev); 2541 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) | 2542 dev_info->rx_queue_offload_capa); 2543 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev); 2544 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev); 2545 2546 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2547 .rx_thresh = { 2548 .pthresh = TXGBE_DEFAULT_RX_PTHRESH, 2549 .hthresh = TXGBE_DEFAULT_RX_HTHRESH, 2550 .wthresh = TXGBE_DEFAULT_RX_WTHRESH, 2551 }, 2552 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH, 2553 .rx_drop_en = 0, 2554 .offloads = 0, 2555 }; 2556 2557 dev_info->default_txconf = (struct rte_eth_txconf) { 2558 .tx_thresh = { 2559 .pthresh = TXGBE_DEFAULT_TX_PTHRESH, 2560 .hthresh = TXGBE_DEFAULT_TX_HTHRESH, 2561 .wthresh = TXGBE_DEFAULT_TX_WTHRESH, 2562 }, 2563 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH, 2564 .offloads = 0, 2565 }; 2566 2567 dev_info->rx_desc_lim = rx_desc_lim; 2568 dev_info->tx_desc_lim = tx_desc_lim; 2569 2570 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 2571 dev_info->reta_size = ETH_RSS_RETA_SIZE_128; 2572 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL; 2573 2574 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 2575 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 2576 2577 /* Driver-preferred Rx/Tx parameters */ 2578 dev_info->default_rxportconf.burst_size = 32; 2579 dev_info->default_txportconf.burst_size = 32; 2580 dev_info->default_rxportconf.nb_queues = 1; 2581 dev_info->default_txportconf.nb_queues = 1; 2582 dev_info->default_rxportconf.ring_size = 256; 2583 dev_info->default_txportconf.ring_size = 256; 2584 2585 return 0; 2586 } 2587 2588 const uint32_t * 2589 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 2590 { 2591 if (dev->rx_pkt_burst == txgbe_recv_pkts || 2592 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc || 2593 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc || 2594 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc) 2595 return txgbe_get_supported_ptypes(); 2596 2597 return NULL; 2598 } 2599 2600 void 2601 txgbe_dev_setup_link_alarm_handler(void *param) 2602 { 2603 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 2604 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2605 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2606 u32 speed; 2607 bool autoneg = false; 2608 2609 speed = hw->phy.autoneg_advertised; 2610 if (!speed) 2611 hw->mac.get_link_capabilities(hw, &speed, &autoneg); 2612 2613 hw->mac.setup_link(hw, speed, true); 2614 2615 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2616 } 2617 2618 /* return 0 means link status changed, -1 means not changed */ 2619 int 2620 txgbe_dev_link_update_share(struct rte_eth_dev *dev, 2621 int wait_to_complete) 2622 { 2623 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2624 struct rte_eth_link link; 2625 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; 2626 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2627 bool link_up; 2628 int err; 2629 int wait = 1; 2630 2631 memset(&link, 0, sizeof(link)); 2632 link.link_status = ETH_LINK_DOWN; 2633 link.link_speed = ETH_SPEED_NUM_NONE; 2634 link.link_duplex = ETH_LINK_HALF_DUPLEX; 2635 link.link_autoneg = ETH_LINK_AUTONEG; 2636 2637 hw->mac.get_link_status = true; 2638 2639 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG) 2640 return rte_eth_linkstatus_set(dev, &link); 2641 2642 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 2643 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 2644 wait = 0; 2645 2646 err = hw->mac.check_link(hw, &link_speed, &link_up, wait); 2647 2648 if (err != 0) { 2649 link.link_speed = ETH_SPEED_NUM_100M; 2650 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2651 return rte_eth_linkstatus_set(dev, &link); 2652 } 2653 2654 if (link_up == 0) { 2655 if (hw->phy.media_type == txgbe_media_type_fiber) { 2656 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG; 2657 rte_eal_alarm_set(10, 2658 txgbe_dev_setup_link_alarm_handler, dev); 2659 } 2660 return rte_eth_linkstatus_set(dev, &link); 2661 } 2662 2663 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2664 link.link_status = ETH_LINK_UP; 2665 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2666 2667 switch (link_speed) { 2668 default: 2669 case TXGBE_LINK_SPEED_UNKNOWN: 2670 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2671 link.link_speed = ETH_SPEED_NUM_100M; 2672 break; 2673 2674 case TXGBE_LINK_SPEED_100M_FULL: 2675 link.link_speed = ETH_SPEED_NUM_100M; 2676 break; 2677 2678 case TXGBE_LINK_SPEED_1GB_FULL: 2679 link.link_speed = ETH_SPEED_NUM_1G; 2680 break; 2681 2682 case TXGBE_LINK_SPEED_2_5GB_FULL: 2683 link.link_speed = ETH_SPEED_NUM_2_5G; 2684 break; 2685 2686 case TXGBE_LINK_SPEED_5GB_FULL: 2687 link.link_speed = ETH_SPEED_NUM_5G; 2688 break; 2689 2690 case TXGBE_LINK_SPEED_10GB_FULL: 2691 link.link_speed = ETH_SPEED_NUM_10G; 2692 break; 2693 } 2694 2695 return rte_eth_linkstatus_set(dev, &link); 2696 } 2697 2698 static int 2699 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 2700 { 2701 return txgbe_dev_link_update_share(dev, wait_to_complete); 2702 } 2703 2704 static int 2705 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 2706 { 2707 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2708 uint32_t fctrl; 2709 2710 fctrl = rd32(hw, TXGBE_PSRCTL); 2711 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP); 2712 wr32(hw, TXGBE_PSRCTL, fctrl); 2713 2714 return 0; 2715 } 2716 2717 static int 2718 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 2719 { 2720 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2721 uint32_t fctrl; 2722 2723 fctrl = rd32(hw, TXGBE_PSRCTL); 2724 fctrl &= (~TXGBE_PSRCTL_UCP); 2725 if (dev->data->all_multicast == 1) 2726 fctrl |= TXGBE_PSRCTL_MCP; 2727 else 2728 fctrl &= (~TXGBE_PSRCTL_MCP); 2729 wr32(hw, TXGBE_PSRCTL, fctrl); 2730 2731 return 0; 2732 } 2733 2734 static int 2735 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 2736 { 2737 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2738 uint32_t fctrl; 2739 2740 fctrl = rd32(hw, TXGBE_PSRCTL); 2741 fctrl |= TXGBE_PSRCTL_MCP; 2742 wr32(hw, TXGBE_PSRCTL, fctrl); 2743 2744 return 0; 2745 } 2746 2747 static int 2748 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 2749 { 2750 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2751 uint32_t fctrl; 2752 2753 if (dev->data->promiscuous == 1) 2754 return 0; /* must remain in all_multicast mode */ 2755 2756 fctrl = rd32(hw, TXGBE_PSRCTL); 2757 fctrl &= (~TXGBE_PSRCTL_MCP); 2758 wr32(hw, TXGBE_PSRCTL, fctrl); 2759 2760 return 0; 2761 } 2762 2763 /** 2764 * It clears the interrupt causes and enables the interrupt. 2765 * It will be called once only during nic initialized. 2766 * 2767 * @param dev 2768 * Pointer to struct rte_eth_dev. 2769 * @param on 2770 * Enable or Disable. 2771 * 2772 * @return 2773 * - On success, zero. 2774 * - On failure, a negative value. 2775 */ 2776 static int 2777 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 2778 { 2779 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2780 2781 txgbe_dev_link_status_print(dev); 2782 if (on) 2783 intr->mask_misc |= TXGBE_ICRMISC_LSC; 2784 else 2785 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 2786 2787 return 0; 2788 } 2789 2790 /** 2791 * It clears the interrupt causes and enables the interrupt. 2792 * It will be called once only during nic initialized. 2793 * 2794 * @param dev 2795 * Pointer to struct rte_eth_dev. 2796 * 2797 * @return 2798 * - On success, zero. 2799 * - On failure, a negative value. 2800 */ 2801 static int 2802 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 2803 { 2804 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2805 2806 intr->mask[0] |= TXGBE_ICR_MASK; 2807 intr->mask[1] |= TXGBE_ICR_MASK; 2808 2809 return 0; 2810 } 2811 2812 /** 2813 * It clears the interrupt causes and enables the interrupt. 2814 * It will be called once only during nic initialized. 2815 * 2816 * @param dev 2817 * Pointer to struct rte_eth_dev. 2818 * 2819 * @return 2820 * - On success, zero. 2821 * - On failure, a negative value. 2822 */ 2823 static int 2824 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 2825 { 2826 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2827 2828 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC; 2829 2830 return 0; 2831 } 2832 2833 /* 2834 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update. 2835 * 2836 * @param dev 2837 * Pointer to struct rte_eth_dev. 2838 * 2839 * @return 2840 * - On success, zero. 2841 * - On failure, a negative value. 2842 */ 2843 static int 2844 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 2845 { 2846 uint32_t eicr; 2847 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2848 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2849 2850 /* clear all cause mask */ 2851 txgbe_disable_intr(hw); 2852 2853 /* read-on-clear nic registers here */ 2854 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 2855 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 2856 2857 intr->flags = 0; 2858 2859 /* set flag for async link update */ 2860 if (eicr & TXGBE_ICRMISC_LSC) 2861 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 2862 2863 if (eicr & TXGBE_ICRMISC_VFMBX) 2864 intr->flags |= TXGBE_FLAG_MAILBOX; 2865 2866 if (eicr & TXGBE_ICRMISC_LNKSEC) 2867 intr->flags |= TXGBE_FLAG_MACSEC; 2868 2869 if (eicr & TXGBE_ICRMISC_GPIO) 2870 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT; 2871 2872 return 0; 2873 } 2874 2875 /** 2876 * It gets and then prints the link status. 2877 * 2878 * @param dev 2879 * Pointer to struct rte_eth_dev. 2880 * 2881 * @return 2882 * - On success, zero. 2883 * - On failure, a negative value. 2884 */ 2885 static void 2886 txgbe_dev_link_status_print(struct rte_eth_dev *dev) 2887 { 2888 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2889 struct rte_eth_link link; 2890 2891 rte_eth_linkstatus_get(dev, &link); 2892 2893 if (link.link_status) { 2894 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 2895 (int)(dev->data->port_id), 2896 (unsigned int)link.link_speed, 2897 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 2898 "full-duplex" : "half-duplex"); 2899 } else { 2900 PMD_INIT_LOG(INFO, " Port %d: Link Down", 2901 (int)(dev->data->port_id)); 2902 } 2903 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 2904 pci_dev->addr.domain, 2905 pci_dev->addr.bus, 2906 pci_dev->addr.devid, 2907 pci_dev->addr.function); 2908 } 2909 2910 /* 2911 * It executes link_update after knowing an interrupt occurred. 2912 * 2913 * @param dev 2914 * Pointer to struct rte_eth_dev. 2915 * 2916 * @return 2917 * - On success, zero. 2918 * - On failure, a negative value. 2919 */ 2920 static int 2921 txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 2922 struct rte_intr_handle *intr_handle) 2923 { 2924 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2925 int64_t timeout; 2926 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2927 2928 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 2929 2930 if (intr->flags & TXGBE_FLAG_MAILBOX) { 2931 txgbe_pf_mbx_process(dev); 2932 intr->flags &= ~TXGBE_FLAG_MAILBOX; 2933 } 2934 2935 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 2936 hw->phy.handle_lasi(hw); 2937 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 2938 } 2939 2940 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 2941 struct rte_eth_link link; 2942 2943 /*get the link status before link update, for predicting later*/ 2944 rte_eth_linkstatus_get(dev, &link); 2945 2946 txgbe_dev_link_update(dev, 0); 2947 2948 /* likely to up */ 2949 if (!link.link_status) 2950 /* handle it 1 sec later, wait it being stable */ 2951 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT; 2952 /* likely to down */ 2953 else 2954 /* handle it 4 sec later, wait it being stable */ 2955 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT; 2956 2957 txgbe_dev_link_status_print(dev); 2958 if (rte_eal_alarm_set(timeout * 1000, 2959 txgbe_dev_interrupt_delayed_handler, 2960 (void *)dev) < 0) { 2961 PMD_DRV_LOG(ERR, "Error setting alarm"); 2962 } else { 2963 /* remember original mask */ 2964 intr->mask_misc_orig = intr->mask_misc; 2965 /* only disable lsc interrupt */ 2966 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 2967 } 2968 } 2969 2970 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 2971 txgbe_enable_intr(dev); 2972 rte_intr_enable(intr_handle); 2973 2974 return 0; 2975 } 2976 2977 /** 2978 * Interrupt handler which shall be registered for alarm callback for delayed 2979 * handling specific interrupt to wait for the stable nic state. As the 2980 * NIC interrupt state is not stable for txgbe after link is just down, 2981 * it needs to wait 4 seconds to get the stable status. 2982 * 2983 * @param handle 2984 * Pointer to interrupt handle. 2985 * @param param 2986 * The address of parameter (struct rte_eth_dev *) registered before. 2987 * 2988 * @return 2989 * void 2990 */ 2991 static void 2992 txgbe_dev_interrupt_delayed_handler(void *param) 2993 { 2994 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 2995 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2996 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2997 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2998 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2999 uint32_t eicr; 3000 3001 txgbe_disable_intr(hw); 3002 3003 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 3004 if (eicr & TXGBE_ICRMISC_VFMBX) 3005 txgbe_pf_mbx_process(dev); 3006 3007 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 3008 hw->phy.handle_lasi(hw); 3009 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 3010 } 3011 3012 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 3013 txgbe_dev_link_update(dev, 0); 3014 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE; 3015 txgbe_dev_link_status_print(dev); 3016 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 3017 NULL); 3018 } 3019 3020 if (intr->flags & TXGBE_FLAG_MACSEC) { 3021 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 3022 NULL); 3023 intr->flags &= ~TXGBE_FLAG_MACSEC; 3024 } 3025 3026 /* restore original mask */ 3027 intr->mask_misc = intr->mask_misc_orig; 3028 intr->mask_misc_orig = 0; 3029 3030 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 3031 txgbe_enable_intr(dev); 3032 rte_intr_enable(intr_handle); 3033 } 3034 3035 /** 3036 * Interrupt handler triggered by NIC for handling 3037 * specific interrupt. 3038 * 3039 * @param handle 3040 * Pointer to interrupt handle. 3041 * @param param 3042 * The address of parameter (struct rte_eth_dev *) registered before. 3043 * 3044 * @return 3045 * void 3046 */ 3047 static void 3048 txgbe_dev_interrupt_handler(void *param) 3049 { 3050 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3051 3052 txgbe_dev_interrupt_get_status(dev); 3053 txgbe_dev_interrupt_action(dev, dev->intr_handle); 3054 } 3055 3056 static int 3057 txgbe_dev_led_on(struct rte_eth_dev *dev) 3058 { 3059 struct txgbe_hw *hw; 3060 3061 hw = TXGBE_DEV_HW(dev); 3062 return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP; 3063 } 3064 3065 static int 3066 txgbe_dev_led_off(struct rte_eth_dev *dev) 3067 { 3068 struct txgbe_hw *hw; 3069 3070 hw = TXGBE_DEV_HW(dev); 3071 return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP; 3072 } 3073 3074 static int 3075 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3076 { 3077 struct txgbe_hw *hw; 3078 uint32_t mflcn_reg; 3079 uint32_t fccfg_reg; 3080 int rx_pause; 3081 int tx_pause; 3082 3083 hw = TXGBE_DEV_HW(dev); 3084 3085 fc_conf->pause_time = hw->fc.pause_time; 3086 fc_conf->high_water = hw->fc.high_water[0]; 3087 fc_conf->low_water = hw->fc.low_water[0]; 3088 fc_conf->send_xon = hw->fc.send_xon; 3089 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 3090 3091 /* 3092 * Return rx_pause status according to actual setting of 3093 * RXFCCFG register. 3094 */ 3095 mflcn_reg = rd32(hw, TXGBE_RXFCCFG); 3096 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC)) 3097 rx_pause = 1; 3098 else 3099 rx_pause = 0; 3100 3101 /* 3102 * Return tx_pause status according to actual setting of 3103 * TXFCCFG register. 3104 */ 3105 fccfg_reg = rd32(hw, TXGBE_TXFCCFG); 3106 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC)) 3107 tx_pause = 1; 3108 else 3109 tx_pause = 0; 3110 3111 if (rx_pause && tx_pause) 3112 fc_conf->mode = RTE_FC_FULL; 3113 else if (rx_pause) 3114 fc_conf->mode = RTE_FC_RX_PAUSE; 3115 else if (tx_pause) 3116 fc_conf->mode = RTE_FC_TX_PAUSE; 3117 else 3118 fc_conf->mode = RTE_FC_NONE; 3119 3120 return 0; 3121 } 3122 3123 static int 3124 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3125 { 3126 struct txgbe_hw *hw; 3127 int err; 3128 uint32_t rx_buf_size; 3129 uint32_t max_high_water; 3130 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3131 txgbe_fc_none, 3132 txgbe_fc_rx_pause, 3133 txgbe_fc_tx_pause, 3134 txgbe_fc_full 3135 }; 3136 3137 PMD_INIT_FUNC_TRACE(); 3138 3139 hw = TXGBE_DEV_HW(dev); 3140 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0)); 3141 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3142 3143 /* 3144 * At least reserve one Ethernet frame for watermark 3145 * high_water/low_water in kilo bytes for txgbe 3146 */ 3147 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3148 if (fc_conf->high_water > max_high_water || 3149 fc_conf->high_water < fc_conf->low_water) { 3150 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3151 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3152 return -EINVAL; 3153 } 3154 3155 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode]; 3156 hw->fc.pause_time = fc_conf->pause_time; 3157 hw->fc.high_water[0] = fc_conf->high_water; 3158 hw->fc.low_water[0] = fc_conf->low_water; 3159 hw->fc.send_xon = fc_conf->send_xon; 3160 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 3161 3162 err = txgbe_fc_enable(hw); 3163 3164 /* Not negotiated is not an error case */ 3165 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) { 3166 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK, 3167 (fc_conf->mac_ctrl_frame_fwd 3168 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP)); 3169 txgbe_flush(hw); 3170 3171 return 0; 3172 } 3173 3174 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err); 3175 return -EIO; 3176 } 3177 3178 static int 3179 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 3180 struct rte_eth_pfc_conf *pfc_conf) 3181 { 3182 int err; 3183 uint32_t rx_buf_size; 3184 uint32_t max_high_water; 3185 uint8_t tc_num; 3186 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 }; 3187 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3188 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 3189 3190 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3191 txgbe_fc_none, 3192 txgbe_fc_rx_pause, 3193 txgbe_fc_tx_pause, 3194 txgbe_fc_full 3195 }; 3196 3197 PMD_INIT_FUNC_TRACE(); 3198 3199 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map); 3200 tc_num = map[pfc_conf->priority]; 3201 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num)); 3202 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3203 /* 3204 * At least reserve one Ethernet frame for watermark 3205 * high_water/low_water in kilo bytes for txgbe 3206 */ 3207 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3208 if (pfc_conf->fc.high_water > max_high_water || 3209 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) { 3210 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3211 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3212 return -EINVAL; 3213 } 3214 3215 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode]; 3216 hw->fc.pause_time = pfc_conf->fc.pause_time; 3217 hw->fc.send_xon = pfc_conf->fc.send_xon; 3218 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 3219 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 3220 3221 err = txgbe_dcb_pfc_enable(hw, tc_num); 3222 3223 /* Not negotiated is not an error case */ 3224 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) 3225 return 0; 3226 3227 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err); 3228 return -EIO; 3229 } 3230 3231 int 3232 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 3233 struct rte_eth_rss_reta_entry64 *reta_conf, 3234 uint16_t reta_size) 3235 { 3236 uint8_t i, j, mask; 3237 uint32_t reta; 3238 uint16_t idx, shift; 3239 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 3240 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3241 3242 PMD_INIT_FUNC_TRACE(); 3243 3244 if (!txgbe_rss_update_sp(hw->mac.type)) { 3245 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 3246 "NIC."); 3247 return -ENOTSUP; 3248 } 3249 3250 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3251 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3252 "(%d) doesn't match the number hardware can supported " 3253 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3254 return -EINVAL; 3255 } 3256 3257 for (i = 0; i < reta_size; i += 4) { 3258 idx = i / RTE_RETA_GROUP_SIZE; 3259 shift = i % RTE_RETA_GROUP_SIZE; 3260 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3261 if (!mask) 3262 continue; 3263 3264 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3265 for (j = 0; j < 4; j++) { 3266 if (RS8(mask, j, 0x1)) { 3267 reta &= ~(MS32(8 * j, 0xFF)); 3268 reta |= LS32(reta_conf[idx].reta[shift + j], 3269 8 * j, 0xFF); 3270 } 3271 } 3272 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta); 3273 } 3274 adapter->rss_reta_updated = 1; 3275 3276 return 0; 3277 } 3278 3279 int 3280 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 3281 struct rte_eth_rss_reta_entry64 *reta_conf, 3282 uint16_t reta_size) 3283 { 3284 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3285 uint8_t i, j, mask; 3286 uint32_t reta; 3287 uint16_t idx, shift; 3288 3289 PMD_INIT_FUNC_TRACE(); 3290 3291 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3292 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3293 "(%d) doesn't match the number hardware can supported " 3294 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3295 return -EINVAL; 3296 } 3297 3298 for (i = 0; i < reta_size; i += 4) { 3299 idx = i / RTE_RETA_GROUP_SIZE; 3300 shift = i % RTE_RETA_GROUP_SIZE; 3301 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3302 if (!mask) 3303 continue; 3304 3305 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3306 for (j = 0; j < 4; j++) { 3307 if (RS8(mask, j, 0x1)) 3308 reta_conf[idx].reta[shift + j] = 3309 (uint16_t)RS32(reta, 8 * j, 0xFF); 3310 } 3311 } 3312 3313 return 0; 3314 } 3315 3316 static int 3317 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 3318 uint32_t index, uint32_t pool) 3319 { 3320 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3321 uint32_t enable_addr = 1; 3322 3323 return txgbe_set_rar(hw, index, mac_addr->addr_bytes, 3324 pool, enable_addr); 3325 } 3326 3327 static void 3328 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 3329 { 3330 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3331 3332 txgbe_clear_rar(hw, index); 3333 } 3334 3335 static int 3336 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 3337 { 3338 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3339 3340 txgbe_remove_rar(dev, 0); 3341 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 3342 3343 return 0; 3344 } 3345 3346 static int 3347 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3348 { 3349 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3350 struct rte_eth_dev_info dev_info; 3351 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 3352 struct rte_eth_dev_data *dev_data = dev->data; 3353 int ret; 3354 3355 ret = txgbe_dev_info_get(dev, &dev_info); 3356 if (ret != 0) 3357 return ret; 3358 3359 /* check that mtu is within the allowed range */ 3360 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 3361 return -EINVAL; 3362 3363 /* If device is started, refuse mtu that requires the support of 3364 * scattered packets when this feature has not been enabled before. 3365 */ 3366 if (dev_data->dev_started && !dev_data->scattered_rx && 3367 (frame_size + 2 * TXGBE_VLAN_TAG_SIZE > 3368 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 3369 PMD_INIT_LOG(ERR, "Stop port first."); 3370 return -EINVAL; 3371 } 3372 3373 /* update max frame size */ 3374 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 3375 3376 if (hw->mode) 3377 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3378 TXGBE_FRAME_SIZE_MAX); 3379 else 3380 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3381 TXGBE_FRMSZ_MAX(frame_size)); 3382 3383 return 0; 3384 } 3385 3386 static uint32_t 3387 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr) 3388 { 3389 uint32_t vector = 0; 3390 3391 switch (hw->mac.mc_filter_type) { 3392 case 0: /* use bits [47:36] of the address */ 3393 vector = ((uc_addr->addr_bytes[4] >> 4) | 3394 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 3395 break; 3396 case 1: /* use bits [46:35] of the address */ 3397 vector = ((uc_addr->addr_bytes[4] >> 3) | 3398 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 3399 break; 3400 case 2: /* use bits [45:34] of the address */ 3401 vector = ((uc_addr->addr_bytes[4] >> 2) | 3402 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 3403 break; 3404 case 3: /* use bits [43:32] of the address */ 3405 vector = ((uc_addr->addr_bytes[4]) | 3406 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 3407 break; 3408 default: /* Invalid mc_filter_type */ 3409 break; 3410 } 3411 3412 /* vector can only be 12-bits or boundary will be exceeded */ 3413 vector &= 0xFFF; 3414 return vector; 3415 } 3416 3417 static int 3418 txgbe_uc_hash_table_set(struct rte_eth_dev *dev, 3419 struct rte_ether_addr *mac_addr, uint8_t on) 3420 { 3421 uint32_t vector; 3422 uint32_t uta_idx; 3423 uint32_t reg_val; 3424 uint32_t uta_mask; 3425 uint32_t psrctl; 3426 3427 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3428 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3429 3430 /* The UTA table only exists on pf hardware */ 3431 if (hw->mac.type < txgbe_mac_raptor) 3432 return -ENOTSUP; 3433 3434 vector = txgbe_uta_vector(hw, mac_addr); 3435 uta_idx = (vector >> 5) & 0x7F; 3436 uta_mask = 0x1UL << (vector & 0x1F); 3437 3438 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask)) 3439 return 0; 3440 3441 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx)); 3442 if (on) { 3443 uta_info->uta_in_use++; 3444 reg_val |= uta_mask; 3445 uta_info->uta_shadow[uta_idx] |= uta_mask; 3446 } else { 3447 uta_info->uta_in_use--; 3448 reg_val &= ~uta_mask; 3449 uta_info->uta_shadow[uta_idx] &= ~uta_mask; 3450 } 3451 3452 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val); 3453 3454 psrctl = rd32(hw, TXGBE_PSRCTL); 3455 if (uta_info->uta_in_use > 0) 3456 psrctl |= TXGBE_PSRCTL_UCHFENA; 3457 else 3458 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3459 3460 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3461 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3462 wr32(hw, TXGBE_PSRCTL, psrctl); 3463 3464 return 0; 3465 } 3466 3467 static int 3468 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 3469 { 3470 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3471 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3472 uint32_t psrctl; 3473 int i; 3474 3475 /* The UTA table only exists on pf hardware */ 3476 if (hw->mac.type < txgbe_mac_raptor) 3477 return -ENOTSUP; 3478 3479 if (on) { 3480 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3481 uta_info->uta_shadow[i] = ~0; 3482 wr32(hw, TXGBE_UCADDRTBL(i), ~0); 3483 } 3484 } else { 3485 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3486 uta_info->uta_shadow[i] = 0; 3487 wr32(hw, TXGBE_UCADDRTBL(i), 0); 3488 } 3489 } 3490 3491 psrctl = rd32(hw, TXGBE_PSRCTL); 3492 if (on) 3493 psrctl |= TXGBE_PSRCTL_UCHFENA; 3494 else 3495 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3496 3497 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3498 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3499 wr32(hw, TXGBE_PSRCTL, psrctl); 3500 3501 return 0; 3502 } 3503 3504 uint32_t 3505 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 3506 { 3507 uint32_t new_val = orig_val; 3508 3509 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 3510 new_val |= TXGBE_POOLETHCTL_UTA; 3511 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 3512 new_val |= TXGBE_POOLETHCTL_MCHA; 3513 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 3514 new_val |= TXGBE_POOLETHCTL_UCHA; 3515 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 3516 new_val |= TXGBE_POOLETHCTL_BCA; 3517 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 3518 new_val |= TXGBE_POOLETHCTL_MCP; 3519 3520 return new_val; 3521 } 3522 3523 static int 3524 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 3525 { 3526 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3527 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3528 uint32_t mask; 3529 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3530 3531 if (queue_id < 32) { 3532 mask = rd32(hw, TXGBE_IMS(0)); 3533 mask &= (1 << queue_id); 3534 wr32(hw, TXGBE_IMS(0), mask); 3535 } else if (queue_id < 64) { 3536 mask = rd32(hw, TXGBE_IMS(1)); 3537 mask &= (1 << (queue_id - 32)); 3538 wr32(hw, TXGBE_IMS(1), mask); 3539 } 3540 rte_intr_enable(intr_handle); 3541 3542 return 0; 3543 } 3544 3545 static int 3546 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 3547 { 3548 uint32_t mask; 3549 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3550 3551 if (queue_id < 32) { 3552 mask = rd32(hw, TXGBE_IMS(0)); 3553 mask &= ~(1 << queue_id); 3554 wr32(hw, TXGBE_IMS(0), mask); 3555 } else if (queue_id < 64) { 3556 mask = rd32(hw, TXGBE_IMS(1)); 3557 mask &= ~(1 << (queue_id - 32)); 3558 wr32(hw, TXGBE_IMS(1), mask); 3559 } 3560 3561 return 0; 3562 } 3563 3564 /** 3565 * set the IVAR registers, mapping interrupt causes to vectors 3566 * @param hw 3567 * pointer to txgbe_hw struct 3568 * @direction 3569 * 0 for Rx, 1 for Tx, -1 for other causes 3570 * @queue 3571 * queue to map the corresponding interrupt to 3572 * @msix_vector 3573 * the vector to map to the corresponding queue 3574 */ 3575 void 3576 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction, 3577 uint8_t queue, uint8_t msix_vector) 3578 { 3579 uint32_t tmp, idx; 3580 3581 if (direction == -1) { 3582 /* other causes */ 3583 msix_vector |= TXGBE_IVARMISC_VLD; 3584 idx = 0; 3585 tmp = rd32(hw, TXGBE_IVARMISC); 3586 tmp &= ~(0xFF << idx); 3587 tmp |= (msix_vector << idx); 3588 wr32(hw, TXGBE_IVARMISC, tmp); 3589 } else { 3590 /* rx or tx causes */ 3591 /* Workround for ICR lost */ 3592 idx = ((16 * (queue & 1)) + (8 * direction)); 3593 tmp = rd32(hw, TXGBE_IVAR(queue >> 1)); 3594 tmp &= ~(0xFF << idx); 3595 tmp |= (msix_vector << idx); 3596 wr32(hw, TXGBE_IVAR(queue >> 1), tmp); 3597 } 3598 } 3599 3600 /** 3601 * Sets up the hardware to properly generate MSI-X interrupts 3602 * @hw 3603 * board private structure 3604 */ 3605 static void 3606 txgbe_configure_msix(struct rte_eth_dev *dev) 3607 { 3608 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3609 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3610 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3611 uint32_t queue_id, base = TXGBE_MISC_VEC_ID; 3612 uint32_t vec = TXGBE_MISC_VEC_ID; 3613 uint32_t gpie; 3614 3615 /* won't configure msix register if no mapping is done 3616 * between intr vector and event fd 3617 * but if misx has been enabled already, need to configure 3618 * auto clean, auto mask and throttling. 3619 */ 3620 gpie = rd32(hw, TXGBE_GPIE); 3621 if (!rte_intr_dp_is_en(intr_handle) && 3622 !(gpie & TXGBE_GPIE_MSIX)) 3623 return; 3624 3625 if (rte_intr_allow_others(intr_handle)) { 3626 base = TXGBE_RX_VEC_START; 3627 vec = base; 3628 } 3629 3630 /* setup GPIE for MSI-x mode */ 3631 gpie = rd32(hw, TXGBE_GPIE); 3632 gpie |= TXGBE_GPIE_MSIX; 3633 wr32(hw, TXGBE_GPIE, gpie); 3634 3635 /* Populate the IVAR table and set the ITR values to the 3636 * corresponding register. 3637 */ 3638 if (rte_intr_dp_is_en(intr_handle)) { 3639 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 3640 queue_id++) { 3641 /* by default, 1:1 mapping */ 3642 txgbe_set_ivar_map(hw, 0, queue_id, vec); 3643 intr_handle->intr_vec[queue_id] = vec; 3644 if (vec < base + intr_handle->nb_efd - 1) 3645 vec++; 3646 } 3647 3648 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 3649 } 3650 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID), 3651 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 3652 | TXGBE_ITR_WRDSA); 3653 } 3654 3655 int 3656 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 3657 uint16_t queue_idx, uint16_t tx_rate) 3658 { 3659 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3660 uint32_t bcnrc_val; 3661 3662 if (queue_idx >= hw->mac.max_tx_queues) 3663 return -EINVAL; 3664 3665 if (tx_rate != 0) { 3666 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate); 3667 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2); 3668 } else { 3669 bcnrc_val = 0; 3670 } 3671 3672 /* 3673 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW 3674 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 3675 */ 3676 wr32(hw, TXGBE_ARBTXMMW, 0x14); 3677 3678 /* Set ARBTXRATE of queue X */ 3679 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx); 3680 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val); 3681 txgbe_flush(hw); 3682 3683 return 0; 3684 } 3685 3686 int 3687 txgbe_syn_filter_set(struct rte_eth_dev *dev, 3688 struct rte_eth_syn_filter *filter, 3689 bool add) 3690 { 3691 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3692 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3693 uint32_t syn_info; 3694 uint32_t synqf; 3695 3696 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 3697 return -EINVAL; 3698 3699 syn_info = filter_info->syn_info; 3700 3701 if (add) { 3702 if (syn_info & TXGBE_SYNCLS_ENA) 3703 return -EINVAL; 3704 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue); 3705 synqf |= TXGBE_SYNCLS_ENA; 3706 3707 if (filter->hig_pri) 3708 synqf |= TXGBE_SYNCLS_HIPRIO; 3709 else 3710 synqf &= ~TXGBE_SYNCLS_HIPRIO; 3711 } else { 3712 synqf = rd32(hw, TXGBE_SYNCLS); 3713 if (!(syn_info & TXGBE_SYNCLS_ENA)) 3714 return -ENOENT; 3715 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA); 3716 } 3717 3718 filter_info->syn_info = synqf; 3719 wr32(hw, TXGBE_SYNCLS, synqf); 3720 txgbe_flush(hw); 3721 return 0; 3722 } 3723 3724 static inline enum txgbe_5tuple_protocol 3725 convert_protocol_type(uint8_t protocol_value) 3726 { 3727 if (protocol_value == IPPROTO_TCP) 3728 return TXGBE_5TF_PROT_TCP; 3729 else if (protocol_value == IPPROTO_UDP) 3730 return TXGBE_5TF_PROT_UDP; 3731 else if (protocol_value == IPPROTO_SCTP) 3732 return TXGBE_5TF_PROT_SCTP; 3733 else 3734 return TXGBE_5TF_PROT_NONE; 3735 } 3736 3737 /* inject a 5-tuple filter to HW */ 3738 static inline void 3739 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 3740 struct txgbe_5tuple_filter *filter) 3741 { 3742 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3743 int i; 3744 uint32_t ftqf, sdpqf; 3745 uint32_t l34timir = 0; 3746 uint32_t mask = TXGBE_5TFCTL0_MASK; 3747 3748 i = filter->index; 3749 sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port)); 3750 sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port)); 3751 3752 ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto); 3753 ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority); 3754 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 3755 mask &= ~TXGBE_5TFCTL0_MSADDR; 3756 if (filter->filter_info.dst_ip_mask == 0) 3757 mask &= ~TXGBE_5TFCTL0_MDADDR; 3758 if (filter->filter_info.src_port_mask == 0) 3759 mask &= ~TXGBE_5TFCTL0_MSPORT; 3760 if (filter->filter_info.dst_port_mask == 0) 3761 mask &= ~TXGBE_5TFCTL0_MDPORT; 3762 if (filter->filter_info.proto_mask == 0) 3763 mask &= ~TXGBE_5TFCTL0_MPROTO; 3764 ftqf |= mask; 3765 ftqf |= TXGBE_5TFCTL0_MPOOL; 3766 ftqf |= TXGBE_5TFCTL0_ENA; 3767 3768 wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip)); 3769 wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip)); 3770 wr32(hw, TXGBE_5TFPORT(i), sdpqf); 3771 wr32(hw, TXGBE_5TFCTL0(i), ftqf); 3772 3773 l34timir |= TXGBE_5TFCTL1_QP(filter->queue); 3774 wr32(hw, TXGBE_5TFCTL1(i), l34timir); 3775 } 3776 3777 /* 3778 * add a 5tuple filter 3779 * 3780 * @param 3781 * dev: Pointer to struct rte_eth_dev. 3782 * index: the index the filter allocates. 3783 * filter: pointer to the filter that will be added. 3784 * rx_queue: the queue id the filter assigned to. 3785 * 3786 * @return 3787 * - On success, zero. 3788 * - On failure, a negative value. 3789 */ 3790 static int 3791 txgbe_add_5tuple_filter(struct rte_eth_dev *dev, 3792 struct txgbe_5tuple_filter *filter) 3793 { 3794 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3795 int i, idx, shift; 3796 3797 /* 3798 * look for an unused 5tuple filter index, 3799 * and insert the filter to list. 3800 */ 3801 for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) { 3802 idx = i / (sizeof(uint32_t) * NBBY); 3803 shift = i % (sizeof(uint32_t) * NBBY); 3804 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 3805 filter_info->fivetuple_mask[idx] |= 1 << shift; 3806 filter->index = i; 3807 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 3808 filter, 3809 entries); 3810 break; 3811 } 3812 } 3813 if (i >= TXGBE_MAX_FTQF_FILTERS) { 3814 PMD_DRV_LOG(ERR, "5tuple filters are full."); 3815 return -ENOSYS; 3816 } 3817 3818 txgbe_inject_5tuple_filter(dev, filter); 3819 3820 return 0; 3821 } 3822 3823 /* 3824 * remove a 5tuple filter 3825 * 3826 * @param 3827 * dev: Pointer to struct rte_eth_dev. 3828 * filter: the pointer of the filter will be removed. 3829 */ 3830 static void 3831 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 3832 struct txgbe_5tuple_filter *filter) 3833 { 3834 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3835 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3836 uint16_t index = filter->index; 3837 3838 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 3839 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 3840 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 3841 rte_free(filter); 3842 3843 wr32(hw, TXGBE_5TFDADDR(index), 0); 3844 wr32(hw, TXGBE_5TFSADDR(index), 0); 3845 wr32(hw, TXGBE_5TFPORT(index), 0); 3846 wr32(hw, TXGBE_5TFCTL0(index), 0); 3847 wr32(hw, TXGBE_5TFCTL1(index), 0); 3848 } 3849 3850 static inline struct txgbe_5tuple_filter * 3851 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list, 3852 struct txgbe_5tuple_filter_info *key) 3853 { 3854 struct txgbe_5tuple_filter *it; 3855 3856 TAILQ_FOREACH(it, filter_list, entries) { 3857 if (memcmp(key, &it->filter_info, 3858 sizeof(struct txgbe_5tuple_filter_info)) == 0) { 3859 return it; 3860 } 3861 } 3862 return NULL; 3863 } 3864 3865 /* translate elements in struct rte_eth_ntuple_filter 3866 * to struct txgbe_5tuple_filter_info 3867 */ 3868 static inline int 3869 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 3870 struct txgbe_5tuple_filter_info *filter_info) 3871 { 3872 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM || 3873 filter->priority > TXGBE_5TUPLE_MAX_PRI || 3874 filter->priority < TXGBE_5TUPLE_MIN_PRI) 3875 return -EINVAL; 3876 3877 switch (filter->dst_ip_mask) { 3878 case UINT32_MAX: 3879 filter_info->dst_ip_mask = 0; 3880 filter_info->dst_ip = filter->dst_ip; 3881 break; 3882 case 0: 3883 filter_info->dst_ip_mask = 1; 3884 break; 3885 default: 3886 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 3887 return -EINVAL; 3888 } 3889 3890 switch (filter->src_ip_mask) { 3891 case UINT32_MAX: 3892 filter_info->src_ip_mask = 0; 3893 filter_info->src_ip = filter->src_ip; 3894 break; 3895 case 0: 3896 filter_info->src_ip_mask = 1; 3897 break; 3898 default: 3899 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 3900 return -EINVAL; 3901 } 3902 3903 switch (filter->dst_port_mask) { 3904 case UINT16_MAX: 3905 filter_info->dst_port_mask = 0; 3906 filter_info->dst_port = filter->dst_port; 3907 break; 3908 case 0: 3909 filter_info->dst_port_mask = 1; 3910 break; 3911 default: 3912 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 3913 return -EINVAL; 3914 } 3915 3916 switch (filter->src_port_mask) { 3917 case UINT16_MAX: 3918 filter_info->src_port_mask = 0; 3919 filter_info->src_port = filter->src_port; 3920 break; 3921 case 0: 3922 filter_info->src_port_mask = 1; 3923 break; 3924 default: 3925 PMD_DRV_LOG(ERR, "invalid src_port mask."); 3926 return -EINVAL; 3927 } 3928 3929 switch (filter->proto_mask) { 3930 case UINT8_MAX: 3931 filter_info->proto_mask = 0; 3932 filter_info->proto = 3933 convert_protocol_type(filter->proto); 3934 break; 3935 case 0: 3936 filter_info->proto_mask = 1; 3937 break; 3938 default: 3939 PMD_DRV_LOG(ERR, "invalid protocol mask."); 3940 return -EINVAL; 3941 } 3942 3943 filter_info->priority = (uint8_t)filter->priority; 3944 return 0; 3945 } 3946 3947 /* 3948 * add or delete a ntuple filter 3949 * 3950 * @param 3951 * dev: Pointer to struct rte_eth_dev. 3952 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 3953 * add: if true, add filter, if false, remove filter 3954 * 3955 * @return 3956 * - On success, zero. 3957 * - On failure, a negative value. 3958 */ 3959 int 3960 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 3961 struct rte_eth_ntuple_filter *ntuple_filter, 3962 bool add) 3963 { 3964 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3965 struct txgbe_5tuple_filter_info filter_5tuple; 3966 struct txgbe_5tuple_filter *filter; 3967 int ret; 3968 3969 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 3970 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 3971 return -EINVAL; 3972 } 3973 3974 memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info)); 3975 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 3976 if (ret < 0) 3977 return ret; 3978 3979 filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 3980 &filter_5tuple); 3981 if (filter != NULL && add) { 3982 PMD_DRV_LOG(ERR, "filter exists."); 3983 return -EEXIST; 3984 } 3985 if (filter == NULL && !add) { 3986 PMD_DRV_LOG(ERR, "filter doesn't exist."); 3987 return -ENOENT; 3988 } 3989 3990 if (add) { 3991 filter = rte_zmalloc("txgbe_5tuple_filter", 3992 sizeof(struct txgbe_5tuple_filter), 0); 3993 if (filter == NULL) 3994 return -ENOMEM; 3995 rte_memcpy(&filter->filter_info, 3996 &filter_5tuple, 3997 sizeof(struct txgbe_5tuple_filter_info)); 3998 filter->queue = ntuple_filter->queue; 3999 ret = txgbe_add_5tuple_filter(dev, filter); 4000 if (ret < 0) { 4001 rte_free(filter); 4002 return ret; 4003 } 4004 } else { 4005 txgbe_remove_5tuple_filter(dev, filter); 4006 } 4007 4008 return 0; 4009 } 4010 4011 int 4012 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 4013 struct rte_eth_ethertype_filter *filter, 4014 bool add) 4015 { 4016 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4017 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4018 uint32_t etqf = 0; 4019 uint32_t etqs = 0; 4020 int ret; 4021 struct txgbe_ethertype_filter ethertype_filter; 4022 4023 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 4024 return -EINVAL; 4025 4026 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 4027 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 4028 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 4029 " ethertype filter.", filter->ether_type); 4030 return -EINVAL; 4031 } 4032 4033 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 4034 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 4035 return -EINVAL; 4036 } 4037 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 4038 PMD_DRV_LOG(ERR, "drop option is unsupported."); 4039 return -EINVAL; 4040 } 4041 4042 ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 4043 if (ret >= 0 && add) { 4044 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 4045 filter->ether_type); 4046 return -EEXIST; 4047 } 4048 if (ret < 0 && !add) { 4049 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 4050 filter->ether_type); 4051 return -ENOENT; 4052 } 4053 4054 if (add) { 4055 etqf = TXGBE_ETFLT_ENA; 4056 etqf |= TXGBE_ETFLT_ETID(filter->ether_type); 4057 etqs |= TXGBE_ETCLS_QPID(filter->queue); 4058 etqs |= TXGBE_ETCLS_QENA; 4059 4060 ethertype_filter.ethertype = filter->ether_type; 4061 ethertype_filter.etqf = etqf; 4062 ethertype_filter.etqs = etqs; 4063 ethertype_filter.conf = FALSE; 4064 ret = txgbe_ethertype_filter_insert(filter_info, 4065 ðertype_filter); 4066 if (ret < 0) { 4067 PMD_DRV_LOG(ERR, "ethertype filters are full."); 4068 return -ENOSPC; 4069 } 4070 } else { 4071 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 4072 if (ret < 0) 4073 return -ENOSYS; 4074 } 4075 wr32(hw, TXGBE_ETFLT(ret), etqf); 4076 wr32(hw, TXGBE_ETCLS(ret), etqs); 4077 txgbe_flush(hw); 4078 4079 return 0; 4080 } 4081 4082 static int 4083 txgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev, 4084 enum rte_filter_type filter_type, 4085 enum rte_filter_op filter_op, 4086 void *arg) 4087 { 4088 int ret = 0; 4089 4090 switch (filter_type) { 4091 case RTE_ETH_FILTER_GENERIC: 4092 if (filter_op != RTE_ETH_FILTER_GET) 4093 return -EINVAL; 4094 *(const void **)arg = &txgbe_flow_ops; 4095 break; 4096 default: 4097 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 4098 filter_type); 4099 ret = -EINVAL; 4100 break; 4101 } 4102 4103 return ret; 4104 } 4105 4106 static u8 * 4107 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw, 4108 u8 **mc_addr_ptr, u32 *vmdq) 4109 { 4110 u8 *mc_addr; 4111 4112 *vmdq = 0; 4113 mc_addr = *mc_addr_ptr; 4114 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 4115 return mc_addr; 4116 } 4117 4118 int 4119 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 4120 struct rte_ether_addr *mc_addr_set, 4121 uint32_t nb_mc_addr) 4122 { 4123 struct txgbe_hw *hw; 4124 u8 *mc_addr_list; 4125 4126 hw = TXGBE_DEV_HW(dev); 4127 mc_addr_list = (u8 *)mc_addr_set; 4128 return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 4129 txgbe_dev_addr_list_itr, TRUE); 4130 } 4131 4132 static uint64_t 4133 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 4134 { 4135 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4136 uint64_t systime_cycles; 4137 4138 systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL); 4139 systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32; 4140 4141 return systime_cycles; 4142 } 4143 4144 static uint64_t 4145 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4146 { 4147 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4148 uint64_t rx_tstamp_cycles; 4149 4150 /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */ 4151 rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL); 4152 rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32; 4153 4154 return rx_tstamp_cycles; 4155 } 4156 4157 static uint64_t 4158 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4159 { 4160 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4161 uint64_t tx_tstamp_cycles; 4162 4163 /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */ 4164 tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL); 4165 tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32; 4166 4167 return tx_tstamp_cycles; 4168 } 4169 4170 static void 4171 txgbe_start_timecounters(struct rte_eth_dev *dev) 4172 { 4173 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4174 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4175 struct rte_eth_link link; 4176 uint32_t incval = 0; 4177 uint32_t shift = 0; 4178 4179 /* Get current link speed. */ 4180 txgbe_dev_link_update(dev, 1); 4181 rte_eth_linkstatus_get(dev, &link); 4182 4183 switch (link.link_speed) { 4184 case ETH_SPEED_NUM_100M: 4185 incval = TXGBE_INCVAL_100; 4186 shift = TXGBE_INCVAL_SHIFT_100; 4187 break; 4188 case ETH_SPEED_NUM_1G: 4189 incval = TXGBE_INCVAL_1GB; 4190 shift = TXGBE_INCVAL_SHIFT_1GB; 4191 break; 4192 case ETH_SPEED_NUM_10G: 4193 default: 4194 incval = TXGBE_INCVAL_10GB; 4195 shift = TXGBE_INCVAL_SHIFT_10GB; 4196 break; 4197 } 4198 4199 wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2)); 4200 4201 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 4202 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4203 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4204 4205 adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4206 adapter->systime_tc.cc_shift = shift; 4207 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 4208 4209 adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4210 adapter->rx_tstamp_tc.cc_shift = shift; 4211 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4212 4213 adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4214 adapter->tx_tstamp_tc.cc_shift = shift; 4215 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4216 } 4217 4218 static int 4219 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 4220 { 4221 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4222 4223 adapter->systime_tc.nsec += delta; 4224 adapter->rx_tstamp_tc.nsec += delta; 4225 adapter->tx_tstamp_tc.nsec += delta; 4226 4227 return 0; 4228 } 4229 4230 static int 4231 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 4232 { 4233 uint64_t ns; 4234 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4235 4236 ns = rte_timespec_to_ns(ts); 4237 /* Set the timecounters to a new value. */ 4238 adapter->systime_tc.nsec = ns; 4239 adapter->rx_tstamp_tc.nsec = ns; 4240 adapter->tx_tstamp_tc.nsec = ns; 4241 4242 return 0; 4243 } 4244 4245 static int 4246 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 4247 { 4248 uint64_t ns, systime_cycles; 4249 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4250 4251 systime_cycles = txgbe_read_systime_cyclecounter(dev); 4252 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 4253 *ts = rte_ns_to_timespec(ns); 4254 4255 return 0; 4256 } 4257 4258 static int 4259 txgbe_timesync_enable(struct rte_eth_dev *dev) 4260 { 4261 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4262 uint32_t tsync_ctl; 4263 4264 /* Stop the timesync system time. */ 4265 wr32(hw, TXGBE_TSTIMEINC, 0x0); 4266 /* Reset the timesync system time value. */ 4267 wr32(hw, TXGBE_TSTIMEL, 0x0); 4268 wr32(hw, TXGBE_TSTIMEH, 0x0); 4269 4270 txgbe_start_timecounters(dev); 4271 4272 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4273 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 4274 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588); 4275 4276 /* Enable timestamping of received PTP packets. */ 4277 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4278 tsync_ctl |= TXGBE_TSRXCTL_ENA; 4279 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4280 4281 /* Enable timestamping of transmitted PTP packets. */ 4282 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4283 tsync_ctl |= TXGBE_TSTXCTL_ENA; 4284 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4285 4286 txgbe_flush(hw); 4287 4288 return 0; 4289 } 4290 4291 static int 4292 txgbe_timesync_disable(struct rte_eth_dev *dev) 4293 { 4294 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4295 uint32_t tsync_ctl; 4296 4297 /* Disable timestamping of transmitted PTP packets. */ 4298 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4299 tsync_ctl &= ~TXGBE_TSTXCTL_ENA; 4300 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4301 4302 /* Disable timestamping of received PTP packets. */ 4303 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4304 tsync_ctl &= ~TXGBE_TSRXCTL_ENA; 4305 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4306 4307 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4308 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0); 4309 4310 /* Stop incrementating the System Time registers. */ 4311 wr32(hw, TXGBE_TSTIMEINC, 0); 4312 4313 return 0; 4314 } 4315 4316 static int 4317 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 4318 struct timespec *timestamp, 4319 uint32_t flags __rte_unused) 4320 { 4321 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4322 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4323 uint32_t tsync_rxctl; 4324 uint64_t rx_tstamp_cycles; 4325 uint64_t ns; 4326 4327 tsync_rxctl = rd32(hw, TXGBE_TSRXCTL); 4328 if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0) 4329 return -EINVAL; 4330 4331 rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev); 4332 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 4333 *timestamp = rte_ns_to_timespec(ns); 4334 4335 return 0; 4336 } 4337 4338 static int 4339 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 4340 struct timespec *timestamp) 4341 { 4342 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4343 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4344 uint32_t tsync_txctl; 4345 uint64_t tx_tstamp_cycles; 4346 uint64_t ns; 4347 4348 tsync_txctl = rd32(hw, TXGBE_TSTXCTL); 4349 if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0) 4350 return -EINVAL; 4351 4352 tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev); 4353 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 4354 *timestamp = rte_ns_to_timespec(ns); 4355 4356 return 0; 4357 } 4358 4359 static int 4360 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused) 4361 { 4362 int count = 0; 4363 int g_ind = 0; 4364 const struct reg_info *reg_group; 4365 const struct reg_info **reg_set = txgbe_regs_others; 4366 4367 while ((reg_group = reg_set[g_ind++])) 4368 count += txgbe_regs_group_count(reg_group); 4369 4370 return count; 4371 } 4372 4373 static int 4374 txgbe_get_regs(struct rte_eth_dev *dev, 4375 struct rte_dev_reg_info *regs) 4376 { 4377 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4378 uint32_t *data = regs->data; 4379 int g_ind = 0; 4380 int count = 0; 4381 const struct reg_info *reg_group; 4382 const struct reg_info **reg_set = txgbe_regs_others; 4383 4384 if (data == NULL) { 4385 regs->length = txgbe_get_reg_length(dev); 4386 regs->width = sizeof(uint32_t); 4387 return 0; 4388 } 4389 4390 /* Support only full register dump */ 4391 if (regs->length == 0 || 4392 regs->length == (uint32_t)txgbe_get_reg_length(dev)) { 4393 regs->version = hw->mac.type << 24 | 4394 hw->revision_id << 16 | 4395 hw->device_id; 4396 while ((reg_group = reg_set[g_ind++])) 4397 count += txgbe_read_regs_group(dev, &data[count], 4398 reg_group); 4399 return 0; 4400 } 4401 4402 return -ENOTSUP; 4403 } 4404 4405 static int 4406 txgbe_get_eeprom_length(struct rte_eth_dev *dev) 4407 { 4408 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4409 4410 /* Return unit is byte count */ 4411 return hw->rom.word_size * 2; 4412 } 4413 4414 static int 4415 txgbe_get_eeprom(struct rte_eth_dev *dev, 4416 struct rte_dev_eeprom_info *in_eeprom) 4417 { 4418 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4419 struct txgbe_rom_info *eeprom = &hw->rom; 4420 uint16_t *data = in_eeprom->data; 4421 int first, length; 4422 4423 first = in_eeprom->offset >> 1; 4424 length = in_eeprom->length >> 1; 4425 if (first > hw->rom.word_size || 4426 ((first + length) > hw->rom.word_size)) 4427 return -EINVAL; 4428 4429 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4430 4431 return eeprom->readw_buffer(hw, first, length, data); 4432 } 4433 4434 static int 4435 txgbe_set_eeprom(struct rte_eth_dev *dev, 4436 struct rte_dev_eeprom_info *in_eeprom) 4437 { 4438 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4439 struct txgbe_rom_info *eeprom = &hw->rom; 4440 uint16_t *data = in_eeprom->data; 4441 int first, length; 4442 4443 first = in_eeprom->offset >> 1; 4444 length = in_eeprom->length >> 1; 4445 if (first > hw->rom.word_size || 4446 ((first + length) > hw->rom.word_size)) 4447 return -EINVAL; 4448 4449 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4450 4451 return eeprom->writew_buffer(hw, first, length, data); 4452 } 4453 4454 static int 4455 txgbe_get_module_info(struct rte_eth_dev *dev, 4456 struct rte_eth_dev_module_info *modinfo) 4457 { 4458 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4459 uint32_t status; 4460 uint8_t sff8472_rev, addr_mode; 4461 bool page_swap = false; 4462 4463 /* Check whether we support SFF-8472 or not */ 4464 status = hw->phy.read_i2c_eeprom(hw, 4465 TXGBE_SFF_SFF_8472_COMP, 4466 &sff8472_rev); 4467 if (status != 0) 4468 return -EIO; 4469 4470 /* addressing mode is not supported */ 4471 status = hw->phy.read_i2c_eeprom(hw, 4472 TXGBE_SFF_SFF_8472_SWAP, 4473 &addr_mode); 4474 if (status != 0) 4475 return -EIO; 4476 4477 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) { 4478 PMD_DRV_LOG(ERR, 4479 "Address change required to access page 0xA2, " 4480 "but not supported. Please report the module " 4481 "type to the driver maintainers."); 4482 page_swap = true; 4483 } 4484 4485 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) { 4486 /* We have a SFP, but it does not support SFF-8472 */ 4487 modinfo->type = RTE_ETH_MODULE_SFF_8079; 4488 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 4489 } else { 4490 /* We have a SFP which supports a revision of SFF-8472. */ 4491 modinfo->type = RTE_ETH_MODULE_SFF_8472; 4492 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 4493 } 4494 4495 return 0; 4496 } 4497 4498 static int 4499 txgbe_get_module_eeprom(struct rte_eth_dev *dev, 4500 struct rte_dev_eeprom_info *info) 4501 { 4502 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4503 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID; 4504 uint8_t databyte = 0xFF; 4505 uint8_t *data = info->data; 4506 uint32_t i = 0; 4507 4508 if (info->length == 0) 4509 return -EINVAL; 4510 4511 for (i = info->offset; i < info->offset + info->length; i++) { 4512 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 4513 status = hw->phy.read_i2c_eeprom(hw, i, &databyte); 4514 else 4515 status = hw->phy.read_i2c_sff8472(hw, i, &databyte); 4516 4517 if (status != 0) 4518 return -EIO; 4519 4520 data[i - info->offset] = databyte; 4521 } 4522 4523 return 0; 4524 } 4525 4526 bool 4527 txgbe_rss_update_sp(enum txgbe_mac_type mac_type) 4528 { 4529 switch (mac_type) { 4530 case txgbe_mac_raptor: 4531 case txgbe_mac_raptor_vf: 4532 return 1; 4533 default: 4534 return 0; 4535 } 4536 } 4537 4538 static int 4539 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 4540 struct rte_eth_dcb_info *dcb_info) 4541 { 4542 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 4543 struct txgbe_dcb_tc_config *tc; 4544 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 4545 uint8_t nb_tcs; 4546 uint8_t i, j; 4547 4548 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 4549 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 4550 else 4551 dcb_info->nb_tcs = 1; 4552 4553 tc_queue = &dcb_info->tc_queue; 4554 nb_tcs = dcb_info->nb_tcs; 4555 4556 if (dcb_config->vt_mode) { /* vt is enabled */ 4557 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 4558 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 4559 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 4560 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 4561 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 4562 for (j = 0; j < nb_tcs; j++) { 4563 tc_queue->tc_rxq[0][j].base = j; 4564 tc_queue->tc_rxq[0][j].nb_queue = 1; 4565 tc_queue->tc_txq[0][j].base = j; 4566 tc_queue->tc_txq[0][j].nb_queue = 1; 4567 } 4568 } else { 4569 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 4570 for (j = 0; j < nb_tcs; j++) { 4571 tc_queue->tc_rxq[i][j].base = 4572 i * nb_tcs + j; 4573 tc_queue->tc_rxq[i][j].nb_queue = 1; 4574 tc_queue->tc_txq[i][j].base = 4575 i * nb_tcs + j; 4576 tc_queue->tc_txq[i][j].nb_queue = 1; 4577 } 4578 } 4579 } 4580 } else { /* vt is disabled */ 4581 struct rte_eth_dcb_rx_conf *rx_conf = 4582 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 4583 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 4584 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 4585 if (dcb_info->nb_tcs == ETH_4_TCS) { 4586 for (i = 0; i < dcb_info->nb_tcs; i++) { 4587 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 4588 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4589 } 4590 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4591 dcb_info->tc_queue.tc_txq[0][1].base = 64; 4592 dcb_info->tc_queue.tc_txq[0][2].base = 96; 4593 dcb_info->tc_queue.tc_txq[0][3].base = 112; 4594 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 4595 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4596 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4597 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4598 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 4599 for (i = 0; i < dcb_info->nb_tcs; i++) { 4600 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 4601 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4602 } 4603 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4604 dcb_info->tc_queue.tc_txq[0][1].base = 32; 4605 dcb_info->tc_queue.tc_txq[0][2].base = 64; 4606 dcb_info->tc_queue.tc_txq[0][3].base = 80; 4607 dcb_info->tc_queue.tc_txq[0][4].base = 96; 4608 dcb_info->tc_queue.tc_txq[0][5].base = 104; 4609 dcb_info->tc_queue.tc_txq[0][6].base = 112; 4610 dcb_info->tc_queue.tc_txq[0][7].base = 120; 4611 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 4612 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4613 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4614 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4615 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 4616 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 4617 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 4618 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 4619 } 4620 } 4621 for (i = 0; i < dcb_info->nb_tcs; i++) { 4622 tc = &dcb_config->tc_config[i]; 4623 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent; 4624 } 4625 return 0; 4626 } 4627 4628 /* Update e-tag ether type */ 4629 static int 4630 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw, 4631 uint16_t ether_type) 4632 { 4633 uint32_t etag_etype; 4634 4635 etag_etype = rd32(hw, TXGBE_EXTAG); 4636 etag_etype &= ~TXGBE_EXTAG_ETAG_MASK; 4637 etag_etype |= ether_type; 4638 wr32(hw, TXGBE_EXTAG, etag_etype); 4639 txgbe_flush(hw); 4640 4641 return 0; 4642 } 4643 4644 /* Enable e-tag tunnel */ 4645 static int 4646 txgbe_e_tag_enable(struct txgbe_hw *hw) 4647 { 4648 uint32_t etag_etype; 4649 4650 etag_etype = rd32(hw, TXGBE_PORTCTL); 4651 etag_etype |= TXGBE_PORTCTL_ETAG; 4652 wr32(hw, TXGBE_PORTCTL, etag_etype); 4653 txgbe_flush(hw); 4654 4655 return 0; 4656 } 4657 4658 static int 4659 txgbe_e_tag_filter_del(struct rte_eth_dev *dev, 4660 struct txgbe_l2_tunnel_conf *l2_tunnel) 4661 { 4662 int ret = 0; 4663 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4664 uint32_t i, rar_entries; 4665 uint32_t rar_low, rar_high; 4666 4667 rar_entries = hw->mac.num_rar_entries; 4668 4669 for (i = 1; i < rar_entries; i++) { 4670 wr32(hw, TXGBE_ETHADDRIDX, i); 4671 rar_high = rd32(hw, TXGBE_ETHADDRH); 4672 rar_low = rd32(hw, TXGBE_ETHADDRL); 4673 if ((rar_high & TXGBE_ETHADDRH_VLD) && 4674 (rar_high & TXGBE_ETHADDRH_ETAG) && 4675 (TXGBE_ETHADDRL_ETAG(rar_low) == 4676 l2_tunnel->tunnel_id)) { 4677 wr32(hw, TXGBE_ETHADDRL, 0); 4678 wr32(hw, TXGBE_ETHADDRH, 0); 4679 4680 txgbe_clear_vmdq(hw, i, BIT_MASK32); 4681 4682 return ret; 4683 } 4684 } 4685 4686 return ret; 4687 } 4688 4689 static int 4690 txgbe_e_tag_filter_add(struct rte_eth_dev *dev, 4691 struct txgbe_l2_tunnel_conf *l2_tunnel) 4692 { 4693 int ret = 0; 4694 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4695 uint32_t i, rar_entries; 4696 uint32_t rar_low, rar_high; 4697 4698 /* One entry for one tunnel. Try to remove potential existing entry. */ 4699 txgbe_e_tag_filter_del(dev, l2_tunnel); 4700 4701 rar_entries = hw->mac.num_rar_entries; 4702 4703 for (i = 1; i < rar_entries; i++) { 4704 wr32(hw, TXGBE_ETHADDRIDX, i); 4705 rar_high = rd32(hw, TXGBE_ETHADDRH); 4706 if (rar_high & TXGBE_ETHADDRH_VLD) { 4707 continue; 4708 } else { 4709 txgbe_set_vmdq(hw, i, l2_tunnel->pool); 4710 rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG; 4711 rar_low = l2_tunnel->tunnel_id; 4712 4713 wr32(hw, TXGBE_ETHADDRL, rar_low); 4714 wr32(hw, TXGBE_ETHADDRH, rar_high); 4715 4716 return ret; 4717 } 4718 } 4719 4720 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 4721 " Please remove a rule before adding a new one."); 4722 return -EINVAL; 4723 } 4724 4725 static inline struct txgbe_l2_tn_filter * 4726 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info, 4727 struct txgbe_l2_tn_key *key) 4728 { 4729 int ret; 4730 4731 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 4732 if (ret < 0) 4733 return NULL; 4734 4735 return l2_tn_info->hash_map[ret]; 4736 } 4737 4738 static inline int 4739 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4740 struct txgbe_l2_tn_filter *l2_tn_filter) 4741 { 4742 int ret; 4743 4744 ret = rte_hash_add_key(l2_tn_info->hash_handle, 4745 &l2_tn_filter->key); 4746 4747 if (ret < 0) { 4748 PMD_DRV_LOG(ERR, 4749 "Failed to insert L2 tunnel filter" 4750 " to hash table %d!", 4751 ret); 4752 return ret; 4753 } 4754 4755 l2_tn_info->hash_map[ret] = l2_tn_filter; 4756 4757 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4758 4759 return 0; 4760 } 4761 4762 static inline int 4763 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4764 struct txgbe_l2_tn_key *key) 4765 { 4766 int ret; 4767 struct txgbe_l2_tn_filter *l2_tn_filter; 4768 4769 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 4770 4771 if (ret < 0) { 4772 PMD_DRV_LOG(ERR, 4773 "No such L2 tunnel filter to delete %d!", 4774 ret); 4775 return ret; 4776 } 4777 4778 l2_tn_filter = l2_tn_info->hash_map[ret]; 4779 l2_tn_info->hash_map[ret] = NULL; 4780 4781 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4782 rte_free(l2_tn_filter); 4783 4784 return 0; 4785 } 4786 4787 /* Add l2 tunnel filter */ 4788 int 4789 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 4790 struct txgbe_l2_tunnel_conf *l2_tunnel, 4791 bool restore) 4792 { 4793 int ret; 4794 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4795 struct txgbe_l2_tn_key key; 4796 struct txgbe_l2_tn_filter *node; 4797 4798 if (!restore) { 4799 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4800 key.tn_id = l2_tunnel->tunnel_id; 4801 4802 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key); 4803 4804 if (node) { 4805 PMD_DRV_LOG(ERR, 4806 "The L2 tunnel filter already exists!"); 4807 return -EINVAL; 4808 } 4809 4810 node = rte_zmalloc("txgbe_l2_tn", 4811 sizeof(struct txgbe_l2_tn_filter), 4812 0); 4813 if (!node) 4814 return -ENOMEM; 4815 4816 rte_memcpy(&node->key, 4817 &key, 4818 sizeof(struct txgbe_l2_tn_key)); 4819 node->pool = l2_tunnel->pool; 4820 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node); 4821 if (ret < 0) { 4822 rte_free(node); 4823 return ret; 4824 } 4825 } 4826 4827 switch (l2_tunnel->l2_tunnel_type) { 4828 case RTE_L2_TUNNEL_TYPE_E_TAG: 4829 ret = txgbe_e_tag_filter_add(dev, l2_tunnel); 4830 break; 4831 default: 4832 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4833 ret = -EINVAL; 4834 break; 4835 } 4836 4837 if (!restore && ret < 0) 4838 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4839 4840 return ret; 4841 } 4842 4843 /* Delete l2 tunnel filter */ 4844 int 4845 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 4846 struct txgbe_l2_tunnel_conf *l2_tunnel) 4847 { 4848 int ret; 4849 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4850 struct txgbe_l2_tn_key key; 4851 4852 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4853 key.tn_id = l2_tunnel->tunnel_id; 4854 ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4855 if (ret < 0) 4856 return ret; 4857 4858 switch (l2_tunnel->l2_tunnel_type) { 4859 case RTE_L2_TUNNEL_TYPE_E_TAG: 4860 ret = txgbe_e_tag_filter_del(dev, l2_tunnel); 4861 break; 4862 default: 4863 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4864 ret = -EINVAL; 4865 break; 4866 } 4867 4868 return ret; 4869 } 4870 4871 static int 4872 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 4873 { 4874 int ret = 0; 4875 uint32_t ctrl; 4876 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4877 4878 ctrl = rd32(hw, TXGBE_POOLCTL); 4879 ctrl &= ~TXGBE_POOLCTL_MODE_MASK; 4880 if (en) 4881 ctrl |= TXGBE_PSRPOOL_MODE_ETAG; 4882 wr32(hw, TXGBE_POOLCTL, ctrl); 4883 4884 return ret; 4885 } 4886 4887 /* Add UDP tunneling port */ 4888 static int 4889 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 4890 struct rte_eth_udp_tunnel *udp_tunnel) 4891 { 4892 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4893 int ret = 0; 4894 4895 if (udp_tunnel == NULL) 4896 return -EINVAL; 4897 4898 switch (udp_tunnel->prot_type) { 4899 case RTE_TUNNEL_TYPE_VXLAN: 4900 if (udp_tunnel->udp_port == 0) { 4901 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 4902 ret = -EINVAL; 4903 break; 4904 } 4905 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port); 4906 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port); 4907 break; 4908 case RTE_TUNNEL_TYPE_GENEVE: 4909 if (udp_tunnel->udp_port == 0) { 4910 PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed."); 4911 ret = -EINVAL; 4912 break; 4913 } 4914 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port); 4915 break; 4916 case RTE_TUNNEL_TYPE_TEREDO: 4917 if (udp_tunnel->udp_port == 0) { 4918 PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed."); 4919 ret = -EINVAL; 4920 break; 4921 } 4922 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port); 4923 break; 4924 default: 4925 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4926 ret = -EINVAL; 4927 break; 4928 } 4929 4930 txgbe_flush(hw); 4931 4932 return ret; 4933 } 4934 4935 /* Remove UDP tunneling port */ 4936 static int 4937 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 4938 struct rte_eth_udp_tunnel *udp_tunnel) 4939 { 4940 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4941 int ret = 0; 4942 uint16_t cur_port; 4943 4944 if (udp_tunnel == NULL) 4945 return -EINVAL; 4946 4947 switch (udp_tunnel->prot_type) { 4948 case RTE_TUNNEL_TYPE_VXLAN: 4949 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT); 4950 if (cur_port != udp_tunnel->udp_port) { 4951 PMD_DRV_LOG(ERR, "Port %u does not exist.", 4952 udp_tunnel->udp_port); 4953 ret = -EINVAL; 4954 break; 4955 } 4956 wr32(hw, TXGBE_VXLANPORT, 0); 4957 wr32(hw, TXGBE_VXLANPORTGPE, 0); 4958 break; 4959 case RTE_TUNNEL_TYPE_GENEVE: 4960 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT); 4961 if (cur_port != udp_tunnel->udp_port) { 4962 PMD_DRV_LOG(ERR, "Port %u does not exist.", 4963 udp_tunnel->udp_port); 4964 ret = -EINVAL; 4965 break; 4966 } 4967 wr32(hw, TXGBE_GENEVEPORT, 0); 4968 break; 4969 case RTE_TUNNEL_TYPE_TEREDO: 4970 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT); 4971 if (cur_port != udp_tunnel->udp_port) { 4972 PMD_DRV_LOG(ERR, "Port %u does not exist.", 4973 udp_tunnel->udp_port); 4974 ret = -EINVAL; 4975 break; 4976 } 4977 wr32(hw, TXGBE_TEREDOPORT, 0); 4978 break; 4979 default: 4980 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4981 ret = -EINVAL; 4982 break; 4983 } 4984 4985 txgbe_flush(hw); 4986 4987 return ret; 4988 } 4989 4990 /* restore n-tuple filter */ 4991 static inline void 4992 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 4993 { 4994 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4995 struct txgbe_5tuple_filter *node; 4996 4997 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 4998 txgbe_inject_5tuple_filter(dev, node); 4999 } 5000 } 5001 5002 /* restore ethernet type filter */ 5003 static inline void 5004 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 5005 { 5006 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5007 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5008 int i; 5009 5010 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5011 if (filter_info->ethertype_mask & (1 << i)) { 5012 wr32(hw, TXGBE_ETFLT(i), 5013 filter_info->ethertype_filters[i].etqf); 5014 wr32(hw, TXGBE_ETCLS(i), 5015 filter_info->ethertype_filters[i].etqs); 5016 txgbe_flush(hw); 5017 } 5018 } 5019 } 5020 5021 /* restore SYN filter */ 5022 static inline void 5023 txgbe_syn_filter_restore(struct rte_eth_dev *dev) 5024 { 5025 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5026 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5027 uint32_t synqf; 5028 5029 synqf = filter_info->syn_info; 5030 5031 if (synqf & TXGBE_SYNCLS_ENA) { 5032 wr32(hw, TXGBE_SYNCLS, synqf); 5033 txgbe_flush(hw); 5034 } 5035 } 5036 5037 /* restore L2 tunnel filter */ 5038 static inline void 5039 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 5040 { 5041 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5042 struct txgbe_l2_tn_filter *node; 5043 struct txgbe_l2_tunnel_conf l2_tn_conf; 5044 5045 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 5046 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 5047 l2_tn_conf.tunnel_id = node->key.tn_id; 5048 l2_tn_conf.pool = node->pool; 5049 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 5050 } 5051 } 5052 5053 /* restore rss filter */ 5054 static inline void 5055 txgbe_rss_filter_restore(struct rte_eth_dev *dev) 5056 { 5057 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5058 5059 if (filter_info->rss_info.conf.queue_num) 5060 txgbe_config_rss_filter(dev, 5061 &filter_info->rss_info, TRUE); 5062 } 5063 5064 static int 5065 txgbe_filter_restore(struct rte_eth_dev *dev) 5066 { 5067 txgbe_ntuple_filter_restore(dev); 5068 txgbe_ethertype_filter_restore(dev); 5069 txgbe_syn_filter_restore(dev); 5070 txgbe_fdir_filter_restore(dev); 5071 txgbe_l2_tn_filter_restore(dev); 5072 txgbe_rss_filter_restore(dev); 5073 5074 return 0; 5075 } 5076 5077 static void 5078 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 5079 { 5080 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5081 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5082 5083 if (l2_tn_info->e_tag_en) 5084 (void)txgbe_e_tag_enable(hw); 5085 5086 if (l2_tn_info->e_tag_fwd_en) 5087 (void)txgbe_e_tag_forwarding_en_dis(dev, 1); 5088 5089 (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 5090 } 5091 5092 /* remove all the n-tuple filters */ 5093 void 5094 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 5095 { 5096 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5097 struct txgbe_5tuple_filter *p_5tuple; 5098 5099 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 5100 txgbe_remove_5tuple_filter(dev, p_5tuple); 5101 } 5102 5103 /* remove all the ether type filters */ 5104 void 5105 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 5106 { 5107 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5108 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5109 int i; 5110 5111 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5112 if (filter_info->ethertype_mask & (1 << i) && 5113 !filter_info->ethertype_filters[i].conf) { 5114 (void)txgbe_ethertype_filter_remove(filter_info, 5115 (uint8_t)i); 5116 wr32(hw, TXGBE_ETFLT(i), 0); 5117 wr32(hw, TXGBE_ETCLS(i), 0); 5118 txgbe_flush(hw); 5119 } 5120 } 5121 } 5122 5123 /* remove the SYN filter */ 5124 void 5125 txgbe_clear_syn_filter(struct rte_eth_dev *dev) 5126 { 5127 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5128 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5129 5130 if (filter_info->syn_info & TXGBE_SYNCLS_ENA) { 5131 filter_info->syn_info = 0; 5132 5133 wr32(hw, TXGBE_SYNCLS, 0); 5134 txgbe_flush(hw); 5135 } 5136 } 5137 5138 /* remove all the L2 tunnel filters */ 5139 int 5140 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 5141 { 5142 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5143 struct txgbe_l2_tn_filter *l2_tn_filter; 5144 struct txgbe_l2_tunnel_conf l2_tn_conf; 5145 int ret = 0; 5146 5147 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 5148 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 5149 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 5150 l2_tn_conf.pool = l2_tn_filter->pool; 5151 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 5152 if (ret < 0) 5153 return ret; 5154 } 5155 5156 return 0; 5157 } 5158 5159 static const struct eth_dev_ops txgbe_eth_dev_ops = { 5160 .dev_configure = txgbe_dev_configure, 5161 .dev_infos_get = txgbe_dev_info_get, 5162 .dev_start = txgbe_dev_start, 5163 .dev_stop = txgbe_dev_stop, 5164 .dev_set_link_up = txgbe_dev_set_link_up, 5165 .dev_set_link_down = txgbe_dev_set_link_down, 5166 .dev_close = txgbe_dev_close, 5167 .dev_reset = txgbe_dev_reset, 5168 .promiscuous_enable = txgbe_dev_promiscuous_enable, 5169 .promiscuous_disable = txgbe_dev_promiscuous_disable, 5170 .allmulticast_enable = txgbe_dev_allmulticast_enable, 5171 .allmulticast_disable = txgbe_dev_allmulticast_disable, 5172 .link_update = txgbe_dev_link_update, 5173 .stats_get = txgbe_dev_stats_get, 5174 .xstats_get = txgbe_dev_xstats_get, 5175 .xstats_get_by_id = txgbe_dev_xstats_get_by_id, 5176 .stats_reset = txgbe_dev_stats_reset, 5177 .xstats_reset = txgbe_dev_xstats_reset, 5178 .xstats_get_names = txgbe_dev_xstats_get_names, 5179 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id, 5180 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set, 5181 .fw_version_get = txgbe_fw_version_get, 5182 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get, 5183 .mtu_set = txgbe_dev_mtu_set, 5184 .vlan_filter_set = txgbe_vlan_filter_set, 5185 .vlan_tpid_set = txgbe_vlan_tpid_set, 5186 .vlan_offload_set = txgbe_vlan_offload_set, 5187 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set, 5188 .rx_queue_start = txgbe_dev_rx_queue_start, 5189 .rx_queue_stop = txgbe_dev_rx_queue_stop, 5190 .tx_queue_start = txgbe_dev_tx_queue_start, 5191 .tx_queue_stop = txgbe_dev_tx_queue_stop, 5192 .rx_queue_setup = txgbe_dev_rx_queue_setup, 5193 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable, 5194 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable, 5195 .rx_queue_release = txgbe_dev_rx_queue_release, 5196 .tx_queue_setup = txgbe_dev_tx_queue_setup, 5197 .tx_queue_release = txgbe_dev_tx_queue_release, 5198 .dev_led_on = txgbe_dev_led_on, 5199 .dev_led_off = txgbe_dev_led_off, 5200 .flow_ctrl_get = txgbe_flow_ctrl_get, 5201 .flow_ctrl_set = txgbe_flow_ctrl_set, 5202 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set, 5203 .mac_addr_add = txgbe_add_rar, 5204 .mac_addr_remove = txgbe_remove_rar, 5205 .mac_addr_set = txgbe_set_default_mac_addr, 5206 .uc_hash_table_set = txgbe_uc_hash_table_set, 5207 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set, 5208 .set_queue_rate_limit = txgbe_set_queue_rate_limit, 5209 .reta_update = txgbe_dev_rss_reta_update, 5210 .reta_query = txgbe_dev_rss_reta_query, 5211 .rss_hash_update = txgbe_dev_rss_hash_update, 5212 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get, 5213 .filter_ctrl = txgbe_dev_filter_ctrl, 5214 .set_mc_addr_list = txgbe_dev_set_mc_addr_list, 5215 .rxq_info_get = txgbe_rxq_info_get, 5216 .txq_info_get = txgbe_txq_info_get, 5217 .timesync_enable = txgbe_timesync_enable, 5218 .timesync_disable = txgbe_timesync_disable, 5219 .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp, 5220 .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp, 5221 .get_reg = txgbe_get_regs, 5222 .get_eeprom_length = txgbe_get_eeprom_length, 5223 .get_eeprom = txgbe_get_eeprom, 5224 .set_eeprom = txgbe_set_eeprom, 5225 .get_module_info = txgbe_get_module_info, 5226 .get_module_eeprom = txgbe_get_module_eeprom, 5227 .get_dcb_info = txgbe_dev_get_dcb_info, 5228 .timesync_adjust_time = txgbe_timesync_adjust_time, 5229 .timesync_read_time = txgbe_timesync_read_time, 5230 .timesync_write_time = txgbe_timesync_write_time, 5231 .udp_tunnel_port_add = txgbe_dev_udp_tunnel_port_add, 5232 .udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del, 5233 .tm_ops_get = txgbe_tm_ops_get, 5234 .tx_done_cleanup = txgbe_dev_tx_done_cleanup, 5235 }; 5236 5237 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd); 5238 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map); 5239 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 5240 5241 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE); 5242 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE); 5243 5244 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX 5245 RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG); 5246 #endif 5247 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX 5248 RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG); 5249 #endif 5250 5251 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE 5252 RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG); 5253 #endif 5254