1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <rte_common.h> 11 #include <ethdev_pci.h> 12 13 #include <rte_interrupts.h> 14 #include <rte_log.h> 15 #include <rte_debug.h> 16 #include <rte_pci.h> 17 #include <rte_memory.h> 18 #include <rte_eal.h> 19 #include <rte_alarm.h> 20 #include <rte_kvargs.h> 21 22 #include "txgbe_logs.h" 23 #include "base/txgbe.h" 24 #include "txgbe_ethdev.h" 25 #include "txgbe_rxtx.h" 26 #include "txgbe_regs_group.h" 27 28 static const struct reg_info txgbe_regs_general[] = { 29 {TXGBE_RST, 1, 1, "TXGBE_RST"}, 30 {TXGBE_STAT, 1, 1, "TXGBE_STAT"}, 31 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"}, 32 {TXGBE_SDP, 1, 1, "TXGBE_SDP"}, 33 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"}, 34 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"}, 35 {0, 0, 0, ""} 36 }; 37 38 static const struct reg_info txgbe_regs_nvm[] = { 39 {0, 0, 0, ""} 40 }; 41 42 static const struct reg_info txgbe_regs_interrupt[] = { 43 {0, 0, 0, ""} 44 }; 45 46 static const struct reg_info txgbe_regs_fctl_others[] = { 47 {0, 0, 0, ""} 48 }; 49 50 static const struct reg_info txgbe_regs_rxdma[] = { 51 {0, 0, 0, ""} 52 }; 53 54 static const struct reg_info txgbe_regs_rx[] = { 55 {0, 0, 0, ""} 56 }; 57 58 static struct reg_info txgbe_regs_tx[] = { 59 {0, 0, 0, ""} 60 }; 61 62 static const struct reg_info txgbe_regs_wakeup[] = { 63 {0, 0, 0, ""} 64 }; 65 66 static const struct reg_info txgbe_regs_dcb[] = { 67 {0, 0, 0, ""} 68 }; 69 70 static const struct reg_info txgbe_regs_mac[] = { 71 {0, 0, 0, ""} 72 }; 73 74 static const struct reg_info txgbe_regs_diagnostic[] = { 75 {0, 0, 0, ""}, 76 }; 77 78 /* PF registers */ 79 static const struct reg_info *txgbe_regs_others[] = { 80 txgbe_regs_general, 81 txgbe_regs_nvm, 82 txgbe_regs_interrupt, 83 txgbe_regs_fctl_others, 84 txgbe_regs_rxdma, 85 txgbe_regs_rx, 86 txgbe_regs_tx, 87 txgbe_regs_wakeup, 88 txgbe_regs_dcb, 89 txgbe_regs_mac, 90 txgbe_regs_diagnostic, 91 NULL}; 92 93 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 94 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 95 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 96 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 97 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev); 98 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev); 99 static int txgbe_dev_close(struct rte_eth_dev *dev); 100 static int txgbe_dev_link_update(struct rte_eth_dev *dev, 101 int wait_to_complete); 102 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev); 103 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 104 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, 105 uint16_t queue); 106 107 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev); 108 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 109 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 110 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev); 111 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 112 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, 113 struct rte_intr_handle *handle); 114 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 115 struct rte_intr_handle *handle); 116 static void txgbe_dev_interrupt_handler(void *param); 117 static void txgbe_dev_interrupt_delayed_handler(void *param); 118 static void txgbe_configure_msix(struct rte_eth_dev *dev); 119 120 static int txgbe_filter_restore(struct rte_eth_dev *dev); 121 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 122 123 #define TXGBE_SET_HWSTRIP(h, q) do {\ 124 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 125 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 126 (h)->bitmap[idx] |= 1 << bit;\ 127 } while (0) 128 129 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\ 130 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 131 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 132 (h)->bitmap[idx] &= ~(1 << bit);\ 133 } while (0) 134 135 #define TXGBE_GET_HWSTRIP(h, q, r) do {\ 136 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 137 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 138 (r) = (h)->bitmap[idx] >> bit & 1;\ 139 } while (0) 140 141 /* 142 * The set of PCI devices this driver supports 143 */ 144 static const struct rte_pci_id pci_id_txgbe_map[] = { 145 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) }, 146 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) }, 147 { .vendor_id = 0, /* sentinel */ }, 148 }; 149 150 static const struct rte_eth_desc_lim rx_desc_lim = { 151 .nb_max = TXGBE_RING_DESC_MAX, 152 .nb_min = TXGBE_RING_DESC_MIN, 153 .nb_align = TXGBE_RXD_ALIGN, 154 }; 155 156 static const struct rte_eth_desc_lim tx_desc_lim = { 157 .nb_max = TXGBE_RING_DESC_MAX, 158 .nb_min = TXGBE_RING_DESC_MIN, 159 .nb_align = TXGBE_TXD_ALIGN, 160 .nb_seg_max = TXGBE_TX_MAX_SEG, 161 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG, 162 }; 163 164 static const struct eth_dev_ops txgbe_eth_dev_ops; 165 166 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)} 167 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)} 168 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = { 169 /* MNG RxTx */ 170 HW_XSTAT(mng_bmc2host_packets), 171 HW_XSTAT(mng_host2bmc_packets), 172 /* Basic RxTx */ 173 HW_XSTAT(rx_packets), 174 HW_XSTAT(tx_packets), 175 HW_XSTAT(rx_bytes), 176 HW_XSTAT(tx_bytes), 177 HW_XSTAT(rx_total_bytes), 178 HW_XSTAT(rx_total_packets), 179 HW_XSTAT(tx_total_packets), 180 HW_XSTAT(rx_total_missed_packets), 181 HW_XSTAT(rx_broadcast_packets), 182 HW_XSTAT(rx_multicast_packets), 183 HW_XSTAT(rx_management_packets), 184 HW_XSTAT(tx_management_packets), 185 HW_XSTAT(rx_management_dropped), 186 187 /* Basic Error */ 188 HW_XSTAT(rx_crc_errors), 189 HW_XSTAT(rx_illegal_byte_errors), 190 HW_XSTAT(rx_error_bytes), 191 HW_XSTAT(rx_mac_short_packet_dropped), 192 HW_XSTAT(rx_length_errors), 193 HW_XSTAT(rx_undersize_errors), 194 HW_XSTAT(rx_fragment_errors), 195 HW_XSTAT(rx_oversize_errors), 196 HW_XSTAT(rx_jabber_errors), 197 HW_XSTAT(rx_l3_l4_xsum_error), 198 HW_XSTAT(mac_local_errors), 199 HW_XSTAT(mac_remote_errors), 200 201 /* Flow Director */ 202 HW_XSTAT(flow_director_added_filters), 203 HW_XSTAT(flow_director_removed_filters), 204 HW_XSTAT(flow_director_filter_add_errors), 205 HW_XSTAT(flow_director_filter_remove_errors), 206 HW_XSTAT(flow_director_matched_filters), 207 HW_XSTAT(flow_director_missed_filters), 208 209 /* FCoE */ 210 HW_XSTAT(rx_fcoe_crc_errors), 211 HW_XSTAT(rx_fcoe_mbuf_allocation_errors), 212 HW_XSTAT(rx_fcoe_dropped), 213 HW_XSTAT(rx_fcoe_packets), 214 HW_XSTAT(tx_fcoe_packets), 215 HW_XSTAT(rx_fcoe_bytes), 216 HW_XSTAT(tx_fcoe_bytes), 217 HW_XSTAT(rx_fcoe_no_ddp), 218 HW_XSTAT(rx_fcoe_no_ddp_ext_buff), 219 220 /* MACSEC */ 221 HW_XSTAT(tx_macsec_pkts_untagged), 222 HW_XSTAT(tx_macsec_pkts_encrypted), 223 HW_XSTAT(tx_macsec_pkts_protected), 224 HW_XSTAT(tx_macsec_octets_encrypted), 225 HW_XSTAT(tx_macsec_octets_protected), 226 HW_XSTAT(rx_macsec_pkts_untagged), 227 HW_XSTAT(rx_macsec_pkts_badtag), 228 HW_XSTAT(rx_macsec_pkts_nosci), 229 HW_XSTAT(rx_macsec_pkts_unknownsci), 230 HW_XSTAT(rx_macsec_octets_decrypted), 231 HW_XSTAT(rx_macsec_octets_validated), 232 HW_XSTAT(rx_macsec_sc_pkts_unchecked), 233 HW_XSTAT(rx_macsec_sc_pkts_delayed), 234 HW_XSTAT(rx_macsec_sc_pkts_late), 235 HW_XSTAT(rx_macsec_sa_pkts_ok), 236 HW_XSTAT(rx_macsec_sa_pkts_invalid), 237 HW_XSTAT(rx_macsec_sa_pkts_notvalid), 238 HW_XSTAT(rx_macsec_sa_pkts_unusedsa), 239 HW_XSTAT(rx_macsec_sa_pkts_notusingsa), 240 241 /* MAC RxTx */ 242 HW_XSTAT(rx_size_64_packets), 243 HW_XSTAT(rx_size_65_to_127_packets), 244 HW_XSTAT(rx_size_128_to_255_packets), 245 HW_XSTAT(rx_size_256_to_511_packets), 246 HW_XSTAT(rx_size_512_to_1023_packets), 247 HW_XSTAT(rx_size_1024_to_max_packets), 248 HW_XSTAT(tx_size_64_packets), 249 HW_XSTAT(tx_size_65_to_127_packets), 250 HW_XSTAT(tx_size_128_to_255_packets), 251 HW_XSTAT(tx_size_256_to_511_packets), 252 HW_XSTAT(tx_size_512_to_1023_packets), 253 HW_XSTAT(tx_size_1024_to_max_packets), 254 255 /* Flow Control */ 256 HW_XSTAT(tx_xon_packets), 257 HW_XSTAT(rx_xon_packets), 258 HW_XSTAT(tx_xoff_packets), 259 HW_XSTAT(rx_xoff_packets), 260 261 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"), 262 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"), 263 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"), 264 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"), 265 }; 266 267 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \ 268 sizeof(rte_txgbe_stats_strings[0])) 269 270 /* Per-priority statistics */ 271 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)} 272 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = { 273 UP_XSTAT(rx_up_packets), 274 UP_XSTAT(tx_up_packets), 275 UP_XSTAT(rx_up_bytes), 276 UP_XSTAT(tx_up_bytes), 277 UP_XSTAT(rx_up_drop_packets), 278 279 UP_XSTAT(tx_up_xon_packets), 280 UP_XSTAT(rx_up_xon_packets), 281 UP_XSTAT(tx_up_xoff_packets), 282 UP_XSTAT(rx_up_xoff_packets), 283 UP_XSTAT(rx_up_dropped), 284 UP_XSTAT(rx_up_mbuf_alloc_errors), 285 UP_XSTAT(tx_up_xon2off_packets), 286 }; 287 288 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \ 289 sizeof(rte_txgbe_up_strings[0])) 290 291 /* Per-queue statistics */ 292 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)} 293 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = { 294 QP_XSTAT(rx_qp_packets), 295 QP_XSTAT(tx_qp_packets), 296 QP_XSTAT(rx_qp_bytes), 297 QP_XSTAT(tx_qp_bytes), 298 QP_XSTAT(rx_qp_mc_packets), 299 }; 300 301 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \ 302 sizeof(rte_txgbe_qp_strings[0])) 303 304 static inline int 305 txgbe_is_sfp(struct txgbe_hw *hw) 306 { 307 switch (hw->phy.type) { 308 case txgbe_phy_sfp_avago: 309 case txgbe_phy_sfp_ftl: 310 case txgbe_phy_sfp_intel: 311 case txgbe_phy_sfp_unknown: 312 case txgbe_phy_sfp_tyco_passive: 313 case txgbe_phy_sfp_unknown_passive: 314 return 1; 315 default: 316 return 0; 317 } 318 } 319 320 static inline int32_t 321 txgbe_pf_reset_hw(struct txgbe_hw *hw) 322 { 323 uint32_t ctrl_ext; 324 int32_t status; 325 326 status = hw->mac.reset_hw(hw); 327 328 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 329 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 330 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 331 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 332 txgbe_flush(hw); 333 334 if (status == TXGBE_ERR_SFP_NOT_PRESENT) 335 status = 0; 336 return status; 337 } 338 339 static inline void 340 txgbe_enable_intr(struct rte_eth_dev *dev) 341 { 342 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 343 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 344 345 wr32(hw, TXGBE_IENMISC, intr->mask_misc); 346 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK); 347 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK); 348 txgbe_flush(hw); 349 } 350 351 static void 352 txgbe_disable_intr(struct txgbe_hw *hw) 353 { 354 PMD_INIT_FUNC_TRACE(); 355 356 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32); 357 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK); 358 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK); 359 txgbe_flush(hw); 360 } 361 362 static int 363 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 364 uint16_t queue_id, 365 uint8_t stat_idx, 366 uint8_t is_rx) 367 { 368 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 369 struct txgbe_stat_mappings *stat_mappings = 370 TXGBE_DEV_STAT_MAPPINGS(eth_dev); 371 uint32_t qsmr_mask = 0; 372 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 373 uint32_t q_map; 374 uint8_t n, offset; 375 376 if (hw->mac.type != txgbe_mac_raptor) 377 return -ENOSYS; 378 379 if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK) 380 return -EIO; 381 382 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 383 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 384 queue_id, stat_idx); 385 386 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 387 if (n >= TXGBE_NB_STAT_MAPPING) { 388 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 389 return -EIO; 390 } 391 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 392 393 /* Now clear any previous stat_idx set */ 394 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 395 if (!is_rx) 396 stat_mappings->tqsm[n] &= ~clearing_mask; 397 else 398 stat_mappings->rqsm[n] &= ~clearing_mask; 399 400 q_map = (uint32_t)stat_idx; 401 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 402 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 403 if (!is_rx) 404 stat_mappings->tqsm[n] |= qsmr_mask; 405 else 406 stat_mappings->rqsm[n] |= qsmr_mask; 407 408 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 409 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 410 queue_id, stat_idx); 411 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 412 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]); 413 return 0; 414 } 415 416 static void 417 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config) 418 { 419 int i; 420 u8 bwgp; 421 struct txgbe_dcb_tc_config *tc; 422 423 UNREFERENCED_PARAMETER(hw); 424 425 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX; 426 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX; 427 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX); 428 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 429 tc = &dcb_config->tc_config[i]; 430 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i; 431 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1); 432 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i; 433 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1); 434 tc->pfc = txgbe_dcb_pfc_disabled; 435 } 436 437 /* Initialize default user to priority mapping, UPx->TC0 */ 438 tc = &dcb_config->tc_config[0]; 439 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 440 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 441 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) { 442 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100; 443 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100; 444 } 445 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal; 446 dcb_config->pfc_mode_enable = false; 447 dcb_config->vt_mode = true; 448 dcb_config->round_robin_enable = false; 449 /* support all DCB capabilities */ 450 dcb_config->support.capabilities = 0xFF; 451 } 452 453 /* 454 * Ensure that all locks are released before first NVM or PHY access 455 */ 456 static void 457 txgbe_swfw_lock_reset(struct txgbe_hw *hw) 458 { 459 uint16_t mask; 460 461 /* 462 * These ones are more tricky since they are common to all ports; but 463 * swfw_sync retries last long enough (1s) to be almost sure that if 464 * lock can not be taken it is due to an improper lock of the 465 * semaphore. 466 */ 467 mask = TXGBE_MNGSEM_SWPHY | 468 TXGBE_MNGSEM_SWMBX | 469 TXGBE_MNGSEM_SWFLASH; 470 if (hw->mac.acquire_swfw_sync(hw, mask) < 0) 471 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 472 473 hw->mac.release_swfw_sync(hw, mask); 474 } 475 476 static int 477 txgbe_handle_devarg(__rte_unused const char *key, const char *value, 478 void *extra_args) 479 { 480 uint16_t *n = extra_args; 481 482 if (value == NULL || extra_args == NULL) 483 return -EINVAL; 484 485 *n = (uint16_t)strtoul(value, NULL, 10); 486 if (*n == USHRT_MAX && errno == ERANGE) 487 return -1; 488 489 return 0; 490 } 491 492 static void 493 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs) 494 { 495 struct rte_kvargs *kvlist; 496 u16 auto_neg = 1; 497 u16 poll = 0; 498 u16 present = 1; 499 u16 sgmii = 0; 500 u16 ffe_set = 0; 501 u16 ffe_main = 27; 502 u16 ffe_pre = 8; 503 u16 ffe_post = 44; 504 505 if (devargs == NULL) 506 goto null; 507 508 kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments); 509 if (kvlist == NULL) 510 goto null; 511 512 rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO, 513 &txgbe_handle_devarg, &auto_neg); 514 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL, 515 &txgbe_handle_devarg, &poll); 516 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT, 517 &txgbe_handle_devarg, &present); 518 rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII, 519 &txgbe_handle_devarg, &sgmii); 520 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET, 521 &txgbe_handle_devarg, &ffe_set); 522 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN, 523 &txgbe_handle_devarg, &ffe_main); 524 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE, 525 &txgbe_handle_devarg, &ffe_pre); 526 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST, 527 &txgbe_handle_devarg, &ffe_post); 528 rte_kvargs_free(kvlist); 529 530 null: 531 hw->devarg.auto_neg = auto_neg; 532 hw->devarg.poll = poll; 533 hw->devarg.present = present; 534 hw->devarg.sgmii = sgmii; 535 hw->phy.ffe_set = ffe_set; 536 hw->phy.ffe_main = ffe_main; 537 hw->phy.ffe_pre = ffe_pre; 538 hw->phy.ffe_post = ffe_post; 539 } 540 541 static int 542 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 543 { 544 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 545 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev); 546 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev); 547 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev); 548 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev); 549 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 550 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev); 551 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 552 const struct rte_memzone *mz; 553 uint32_t ctrl_ext; 554 uint16_t csum; 555 int err, i, ret; 556 557 PMD_INIT_FUNC_TRACE(); 558 559 eth_dev->dev_ops = &txgbe_eth_dev_ops; 560 eth_dev->rx_queue_count = txgbe_dev_rx_queue_count; 561 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status; 562 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status; 563 eth_dev->rx_pkt_burst = &txgbe_recv_pkts; 564 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts; 565 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts; 566 567 /* 568 * For secondary processes, we don't initialise any further as primary 569 * has already done this work. Only check we don't need a different 570 * RX and TX function. 571 */ 572 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 573 struct txgbe_tx_queue *txq; 574 /* TX queue function in primary, set by last queue initialized 575 * Tx queue may not initialized by primary process 576 */ 577 if (eth_dev->data->tx_queues) { 578 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues; 579 txq = eth_dev->data->tx_queues[nb_tx_queues - 1]; 580 txgbe_set_tx_function(eth_dev, txq); 581 } else { 582 /* Use default TX function if we get here */ 583 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 584 "Using default TX function."); 585 } 586 587 txgbe_set_rx_function(eth_dev); 588 589 return 0; 590 } 591 592 rte_eth_copy_pci_info(eth_dev, pci_dev); 593 594 /* Vendor and Device ID need to be set before init of shared code */ 595 hw->device_id = pci_dev->id.device_id; 596 hw->vendor_id = pci_dev->id.vendor_id; 597 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 598 hw->allow_unsupported_sfp = 1; 599 600 /* Reserve memory for interrupt status block */ 601 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1, 602 16, TXGBE_ALIGN, SOCKET_ID_ANY); 603 if (mz == NULL) 604 return -ENOMEM; 605 606 hw->isb_dma = TMZ_PADDR(mz); 607 hw->isb_mem = TMZ_VADDR(mz); 608 609 txgbe_parse_devargs(hw, pci_dev->device.devargs); 610 /* Initialize the shared code (base driver) */ 611 err = txgbe_init_shared_code(hw); 612 if (err != 0) { 613 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err); 614 return -EIO; 615 } 616 617 /* Unlock any pending hardware semaphore */ 618 txgbe_swfw_lock_reset(hw); 619 620 #ifdef RTE_LIB_SECURITY 621 /* Initialize security_ctx only for primary process*/ 622 if (txgbe_ipsec_ctx_create(eth_dev)) 623 return -ENOMEM; 624 #endif 625 626 /* Initialize DCB configuration*/ 627 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config)); 628 txgbe_dcb_init(hw, dcb_config); 629 630 /* Get Hardware Flow Control setting */ 631 hw->fc.requested_mode = txgbe_fc_full; 632 hw->fc.current_mode = txgbe_fc_full; 633 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME; 634 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 635 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH; 636 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH; 637 } 638 hw->fc.send_xon = 1; 639 640 err = hw->rom.init_params(hw); 641 if (err != 0) { 642 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err); 643 return -EIO; 644 } 645 646 /* Make sure we have a good EEPROM before we read from it */ 647 err = hw->rom.validate_checksum(hw, &csum); 648 if (err != 0) { 649 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err); 650 return -EIO; 651 } 652 653 err = hw->mac.init_hw(hw); 654 655 /* 656 * Devices with copper phys will fail to initialise if txgbe_init_hw() 657 * is called too soon after the kernel driver unbinding/binding occurs. 658 * The failure occurs in txgbe_identify_phy() for all devices, 659 * but for non-copper devies, txgbe_identify_sfp_module() is 660 * also called. See txgbe_identify_phy(). The reason for the 661 * failure is not known, and only occuts when virtualisation features 662 * are disabled in the bios. A delay of 200ms was found to be enough by 663 * trial-and-error, and is doubled to be safe. 664 */ 665 if (err && hw->phy.media_type == txgbe_media_type_copper) { 666 rte_delay_ms(200); 667 err = hw->mac.init_hw(hw); 668 } 669 670 if (err == TXGBE_ERR_SFP_NOT_PRESENT) 671 err = 0; 672 673 if (err == TXGBE_ERR_EEPROM_VERSION) { 674 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 675 "LOM. Please be aware there may be issues associated " 676 "with your hardware."); 677 PMD_INIT_LOG(ERR, "If you are experiencing problems " 678 "please contact your hardware representative " 679 "who provided you with this hardware."); 680 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) { 681 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 682 } 683 if (err) { 684 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err); 685 return -EIO; 686 } 687 688 /* Reset the hw statistics */ 689 txgbe_dev_stats_reset(eth_dev); 690 691 /* disable interrupt */ 692 txgbe_disable_intr(hw); 693 694 /* Allocate memory for storing MAC addresses */ 695 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN * 696 hw->mac.num_rar_entries, 0); 697 if (eth_dev->data->mac_addrs == NULL) { 698 PMD_INIT_LOG(ERR, 699 "Failed to allocate %u bytes needed to store " 700 "MAC addresses", 701 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries); 702 return -ENOMEM; 703 } 704 705 /* Copy the permanent MAC address */ 706 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr, 707 ð_dev->data->mac_addrs[0]); 708 709 /* Allocate memory for storing hash filter MAC addresses */ 710 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe", 711 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0); 712 if (eth_dev->data->hash_mac_addrs == NULL) { 713 PMD_INIT_LOG(ERR, 714 "Failed to allocate %d bytes needed to store MAC addresses", 715 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC); 716 return -ENOMEM; 717 } 718 719 /* initialize the vfta */ 720 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 721 722 /* initialize the hw strip bitmap*/ 723 memset(hwstrip, 0, sizeof(*hwstrip)); 724 725 /* initialize PF if max_vfs not zero */ 726 ret = txgbe_pf_host_init(eth_dev); 727 if (ret) { 728 rte_free(eth_dev->data->mac_addrs); 729 eth_dev->data->mac_addrs = NULL; 730 rte_free(eth_dev->data->hash_mac_addrs); 731 eth_dev->data->hash_mac_addrs = NULL; 732 return ret; 733 } 734 735 ctrl_ext = rd32(hw, TXGBE_PORTCTL); 736 /* let hardware know driver is loaded */ 737 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD; 738 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 739 ctrl_ext |= TXGBE_PORTCTL_RSTDONE; 740 wr32(hw, TXGBE_PORTCTL, ctrl_ext); 741 txgbe_flush(hw); 742 743 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present) 744 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 745 (int)hw->mac.type, (int)hw->phy.type, 746 (int)hw->phy.sfp_type); 747 else 748 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 749 (int)hw->mac.type, (int)hw->phy.type); 750 751 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 752 eth_dev->data->port_id, pci_dev->id.vendor_id, 753 pci_dev->id.device_id); 754 755 rte_intr_callback_register(intr_handle, 756 txgbe_dev_interrupt_handler, eth_dev); 757 758 /* enable uio/vfio intr/eventfd mapping */ 759 rte_intr_enable(intr_handle); 760 761 /* enable support intr */ 762 txgbe_enable_intr(eth_dev); 763 764 /* initialize filter info */ 765 memset(filter_info, 0, 766 sizeof(struct txgbe_filter_info)); 767 768 /* initialize 5tuple filter list */ 769 TAILQ_INIT(&filter_info->fivetuple_list); 770 771 /* initialize flow director filter list & hash */ 772 txgbe_fdir_filter_init(eth_dev); 773 774 /* initialize l2 tunnel filter list & hash */ 775 txgbe_l2_tn_filter_init(eth_dev); 776 777 /* initialize flow filter lists */ 778 txgbe_filterlist_init(); 779 780 /* initialize bandwidth configuration info */ 781 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf)); 782 783 /* initialize Traffic Manager configuration */ 784 txgbe_tm_conf_init(eth_dev); 785 786 return 0; 787 } 788 789 static int 790 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev) 791 { 792 PMD_INIT_FUNC_TRACE(); 793 794 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 795 return 0; 796 797 txgbe_dev_close(eth_dev); 798 799 return 0; 800 } 801 802 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 803 { 804 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev); 805 struct txgbe_5tuple_filter *p_5tuple; 806 807 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 808 TAILQ_REMOVE(&filter_info->fivetuple_list, 809 p_5tuple, 810 entries); 811 rte_free(p_5tuple); 812 } 813 memset(filter_info->fivetuple_mask, 0, 814 sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE); 815 816 return 0; 817 } 818 819 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 820 { 821 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 822 struct txgbe_fdir_filter *fdir_filter; 823 824 if (fdir_info->hash_map) 825 rte_free(fdir_info->hash_map); 826 if (fdir_info->hash_handle) 827 rte_hash_free(fdir_info->hash_handle); 828 829 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 830 TAILQ_REMOVE(&fdir_info->fdir_list, 831 fdir_filter, 832 entries); 833 rte_free(fdir_filter); 834 } 835 836 return 0; 837 } 838 839 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 840 { 841 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 842 struct txgbe_l2_tn_filter *l2_tn_filter; 843 844 if (l2_tn_info->hash_map) 845 rte_free(l2_tn_info->hash_map); 846 if (l2_tn_info->hash_handle) 847 rte_hash_free(l2_tn_info->hash_handle); 848 849 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 850 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 851 l2_tn_filter, 852 entries); 853 rte_free(l2_tn_filter); 854 } 855 856 return 0; 857 } 858 859 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 860 { 861 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev); 862 char fdir_hash_name[RTE_HASH_NAMESIZE]; 863 struct rte_hash_parameters fdir_hash_params = { 864 .name = fdir_hash_name, 865 .entries = TXGBE_MAX_FDIR_FILTER_NUM, 866 .key_len = sizeof(struct txgbe_atr_input), 867 .hash_func = rte_hash_crc, 868 .hash_func_init_val = 0, 869 .socket_id = rte_socket_id(), 870 }; 871 872 TAILQ_INIT(&fdir_info->fdir_list); 873 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 874 "fdir_%s", TDEV_NAME(eth_dev)); 875 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 876 if (!fdir_info->hash_handle) { 877 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 878 return -EINVAL; 879 } 880 fdir_info->hash_map = rte_zmalloc("txgbe", 881 sizeof(struct txgbe_fdir_filter *) * 882 TXGBE_MAX_FDIR_FILTER_NUM, 883 0); 884 if (!fdir_info->hash_map) { 885 PMD_INIT_LOG(ERR, 886 "Failed to allocate memory for fdir hash map!"); 887 return -ENOMEM; 888 } 889 fdir_info->mask_added = FALSE; 890 891 return 0; 892 } 893 894 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 895 { 896 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev); 897 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 898 struct rte_hash_parameters l2_tn_hash_params = { 899 .name = l2_tn_hash_name, 900 .entries = TXGBE_MAX_L2_TN_FILTER_NUM, 901 .key_len = sizeof(struct txgbe_l2_tn_key), 902 .hash_func = rte_hash_crc, 903 .hash_func_init_val = 0, 904 .socket_id = rte_socket_id(), 905 }; 906 907 TAILQ_INIT(&l2_tn_info->l2_tn_list); 908 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 909 "l2_tn_%s", TDEV_NAME(eth_dev)); 910 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 911 if (!l2_tn_info->hash_handle) { 912 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 913 return -EINVAL; 914 } 915 l2_tn_info->hash_map = rte_zmalloc("txgbe", 916 sizeof(struct txgbe_l2_tn_filter *) * 917 TXGBE_MAX_L2_TN_FILTER_NUM, 918 0); 919 if (!l2_tn_info->hash_map) { 920 PMD_INIT_LOG(ERR, 921 "Failed to allocate memory for L2 TN hash map!"); 922 return -ENOMEM; 923 } 924 l2_tn_info->e_tag_en = FALSE; 925 l2_tn_info->e_tag_fwd_en = FALSE; 926 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG; 927 928 return 0; 929 } 930 931 static int 932 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 933 struct rte_pci_device *pci_dev) 934 { 935 return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 936 sizeof(struct txgbe_adapter), 937 eth_dev_pci_specific_init, pci_dev, 938 eth_txgbe_dev_init, NULL); 939 } 940 941 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev) 942 { 943 struct rte_eth_dev *ethdev; 944 945 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 946 if (!ethdev) 947 return 0; 948 949 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit); 950 } 951 952 static struct rte_pci_driver rte_txgbe_pmd = { 953 .id_table = pci_id_txgbe_map, 954 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | 955 RTE_PCI_DRV_INTR_LSC, 956 .probe = eth_txgbe_pci_probe, 957 .remove = eth_txgbe_pci_remove, 958 }; 959 960 static int 961 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 962 { 963 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 964 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 965 uint32_t vfta; 966 uint32_t vid_idx; 967 uint32_t vid_bit; 968 969 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F); 970 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F)); 971 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx)); 972 if (on) 973 vfta |= vid_bit; 974 else 975 vfta &= ~vid_bit; 976 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta); 977 978 /* update local VFTA copy */ 979 shadow_vfta->vfta[vid_idx] = vfta; 980 981 return 0; 982 } 983 984 static void 985 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 986 { 987 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 988 struct txgbe_rx_queue *rxq; 989 bool restart; 990 uint32_t rxcfg, rxbal, rxbah; 991 992 if (on) 993 txgbe_vlan_hw_strip_enable(dev, queue); 994 else 995 txgbe_vlan_hw_strip_disable(dev, queue); 996 997 rxq = dev->data->rx_queues[queue]; 998 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx)); 999 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx)); 1000 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx)); 1001 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 1002 restart = (rxcfg & TXGBE_RXCFG_ENA) && 1003 !(rxcfg & TXGBE_RXCFG_VLAN); 1004 rxcfg |= TXGBE_RXCFG_VLAN; 1005 } else { 1006 restart = (rxcfg & TXGBE_RXCFG_ENA) && 1007 (rxcfg & TXGBE_RXCFG_VLAN); 1008 rxcfg &= ~TXGBE_RXCFG_VLAN; 1009 } 1010 rxcfg &= ~TXGBE_RXCFG_ENA; 1011 1012 if (restart) { 1013 /* set vlan strip for ring */ 1014 txgbe_dev_rx_queue_stop(dev, queue); 1015 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal); 1016 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah); 1017 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg); 1018 txgbe_dev_rx_queue_start(dev, queue); 1019 } 1020 } 1021 1022 static int 1023 txgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1024 enum rte_vlan_type vlan_type, 1025 uint16_t tpid) 1026 { 1027 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1028 int ret = 0; 1029 uint32_t portctrl, vlan_ext, qinq; 1030 1031 portctrl = rd32(hw, TXGBE_PORTCTL); 1032 1033 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT); 1034 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ); 1035 switch (vlan_type) { 1036 case ETH_VLAN_TYPE_INNER: 1037 if (vlan_ext) { 1038 wr32m(hw, TXGBE_VLANCTL, 1039 TXGBE_VLANCTL_TPID_MASK, 1040 TXGBE_VLANCTL_TPID(tpid)); 1041 wr32m(hw, TXGBE_DMATXCTRL, 1042 TXGBE_DMATXCTRL_TPID_MASK, 1043 TXGBE_DMATXCTRL_TPID(tpid)); 1044 } else { 1045 ret = -ENOTSUP; 1046 PMD_DRV_LOG(ERR, "Inner type is not supported" 1047 " by single VLAN"); 1048 } 1049 1050 if (qinq) { 1051 wr32m(hw, TXGBE_TAGTPID(0), 1052 TXGBE_TAGTPID_LSB_MASK, 1053 TXGBE_TAGTPID_LSB(tpid)); 1054 } 1055 break; 1056 case ETH_VLAN_TYPE_OUTER: 1057 if (vlan_ext) { 1058 /* Only the high 16-bits is valid */ 1059 wr32m(hw, TXGBE_EXTAG, 1060 TXGBE_EXTAG_VLAN_MASK, 1061 TXGBE_EXTAG_VLAN(tpid)); 1062 } else { 1063 wr32m(hw, TXGBE_VLANCTL, 1064 TXGBE_VLANCTL_TPID_MASK, 1065 TXGBE_VLANCTL_TPID(tpid)); 1066 wr32m(hw, TXGBE_DMATXCTRL, 1067 TXGBE_DMATXCTRL_TPID_MASK, 1068 TXGBE_DMATXCTRL_TPID(tpid)); 1069 } 1070 1071 if (qinq) { 1072 wr32m(hw, TXGBE_TAGTPID(0), 1073 TXGBE_TAGTPID_MSB_MASK, 1074 TXGBE_TAGTPID_MSB(tpid)); 1075 } 1076 break; 1077 default: 1078 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1079 return -EINVAL; 1080 } 1081 1082 return ret; 1083 } 1084 1085 void 1086 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1087 { 1088 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1089 uint32_t vlnctrl; 1090 1091 PMD_INIT_FUNC_TRACE(); 1092 1093 /* Filter Table Disable */ 1094 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1095 vlnctrl &= ~TXGBE_VLANCTL_VFE; 1096 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1097 } 1098 1099 void 1100 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1101 { 1102 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1103 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev); 1104 uint32_t vlnctrl; 1105 uint16_t i; 1106 1107 PMD_INIT_FUNC_TRACE(); 1108 1109 /* Filter Table Enable */ 1110 vlnctrl = rd32(hw, TXGBE_VLANCTL); 1111 vlnctrl &= ~TXGBE_VLANCTL_CFIENA; 1112 vlnctrl |= TXGBE_VLANCTL_VFE; 1113 wr32(hw, TXGBE_VLANCTL, vlnctrl); 1114 1115 /* write whatever is in local vfta copy */ 1116 for (i = 0; i < TXGBE_VFTA_SIZE; i++) 1117 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]); 1118 } 1119 1120 void 1121 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1122 { 1123 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev); 1124 struct txgbe_rx_queue *rxq; 1125 1126 if (queue >= TXGBE_MAX_RX_QUEUE_NUM) 1127 return; 1128 1129 if (on) 1130 TXGBE_SET_HWSTRIP(hwstrip, queue); 1131 else 1132 TXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1133 1134 if (queue >= dev->data->nb_rx_queues) 1135 return; 1136 1137 rxq = dev->data->rx_queues[queue]; 1138 1139 if (on) { 1140 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1141 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1142 } else { 1143 rxq->vlan_flags = PKT_RX_VLAN; 1144 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1145 } 1146 } 1147 1148 static void 1149 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1150 { 1151 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1152 uint32_t ctrl; 1153 1154 PMD_INIT_FUNC_TRACE(); 1155 1156 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1157 ctrl &= ~TXGBE_RXCFG_VLAN; 1158 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1159 1160 /* record those setting for HW strip per queue */ 1161 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 1162 } 1163 1164 static void 1165 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 1166 { 1167 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1168 uint32_t ctrl; 1169 1170 PMD_INIT_FUNC_TRACE(); 1171 1172 ctrl = rd32(hw, TXGBE_RXCFG(queue)); 1173 ctrl |= TXGBE_RXCFG_VLAN; 1174 wr32(hw, TXGBE_RXCFG(queue), ctrl); 1175 1176 /* record those setting for HW strip per queue */ 1177 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 1178 } 1179 1180 static void 1181 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 1182 { 1183 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1184 uint32_t ctrl; 1185 1186 PMD_INIT_FUNC_TRACE(); 1187 1188 ctrl = rd32(hw, TXGBE_PORTCTL); 1189 ctrl &= ~TXGBE_PORTCTL_VLANEXT; 1190 wr32(hw, TXGBE_PORTCTL, ctrl); 1191 } 1192 1193 static void 1194 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 1195 { 1196 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1197 uint32_t ctrl; 1198 1199 PMD_INIT_FUNC_TRACE(); 1200 1201 ctrl = rd32(hw, TXGBE_PORTCTL); 1202 ctrl |= TXGBE_PORTCTL_VLANEXT; 1203 wr32(hw, TXGBE_PORTCTL, ctrl); 1204 } 1205 1206 static void 1207 txgbe_qinq_hw_strip_disable(struct rte_eth_dev *dev) 1208 { 1209 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1210 uint32_t ctrl; 1211 1212 PMD_INIT_FUNC_TRACE(); 1213 1214 ctrl = rd32(hw, TXGBE_PORTCTL); 1215 ctrl &= ~TXGBE_PORTCTL_QINQ; 1216 wr32(hw, TXGBE_PORTCTL, ctrl); 1217 } 1218 1219 static void 1220 txgbe_qinq_hw_strip_enable(struct rte_eth_dev *dev) 1221 { 1222 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1223 uint32_t ctrl; 1224 1225 PMD_INIT_FUNC_TRACE(); 1226 1227 ctrl = rd32(hw, TXGBE_PORTCTL); 1228 ctrl |= TXGBE_PORTCTL_QINQ | TXGBE_PORTCTL_VLANEXT; 1229 wr32(hw, TXGBE_PORTCTL, ctrl); 1230 } 1231 1232 void 1233 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 1234 { 1235 struct txgbe_rx_queue *rxq; 1236 uint16_t i; 1237 1238 PMD_INIT_FUNC_TRACE(); 1239 1240 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1241 rxq = dev->data->rx_queues[i]; 1242 1243 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1244 txgbe_vlan_strip_queue_set(dev, i, 1); 1245 else 1246 txgbe_vlan_strip_queue_set(dev, i, 0); 1247 } 1248 } 1249 1250 void 1251 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 1252 { 1253 uint16_t i; 1254 struct rte_eth_rxmode *rxmode; 1255 struct txgbe_rx_queue *rxq; 1256 1257 if (mask & ETH_VLAN_STRIP_MASK) { 1258 rxmode = &dev->data->dev_conf.rxmode; 1259 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1260 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1261 rxq = dev->data->rx_queues[i]; 1262 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1263 } 1264 else 1265 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1266 rxq = dev->data->rx_queues[i]; 1267 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1268 } 1269 } 1270 } 1271 1272 static int 1273 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 1274 { 1275 struct rte_eth_rxmode *rxmode; 1276 rxmode = &dev->data->dev_conf.rxmode; 1277 1278 if (mask & ETH_VLAN_STRIP_MASK) 1279 txgbe_vlan_hw_strip_config(dev); 1280 1281 if (mask & ETH_VLAN_FILTER_MASK) { 1282 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1283 txgbe_vlan_hw_filter_enable(dev); 1284 else 1285 txgbe_vlan_hw_filter_disable(dev); 1286 } 1287 1288 if (mask & ETH_VLAN_EXTEND_MASK) { 1289 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 1290 txgbe_vlan_hw_extend_enable(dev); 1291 else 1292 txgbe_vlan_hw_extend_disable(dev); 1293 } 1294 1295 if (mask & ETH_QINQ_STRIP_MASK) { 1296 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP) 1297 txgbe_qinq_hw_strip_enable(dev); 1298 else 1299 txgbe_qinq_hw_strip_disable(dev); 1300 } 1301 1302 return 0; 1303 } 1304 1305 static int 1306 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1307 { 1308 txgbe_config_vlan_strip_on_all_queues(dev, mask); 1309 1310 txgbe_vlan_offload_config(dev, mask); 1311 1312 return 0; 1313 } 1314 1315 static void 1316 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1317 { 1318 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1319 /* VLNCTL: enable vlan filtering and allow all vlan tags through */ 1320 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL); 1321 1322 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */ 1323 wr32(hw, TXGBE_VLANCTL, vlanctrl); 1324 } 1325 1326 static int 1327 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 1328 { 1329 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1330 1331 switch (nb_rx_q) { 1332 case 1: 1333 case 2: 1334 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 1335 break; 1336 case 4: 1337 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 1338 break; 1339 default: 1340 return -EINVAL; 1341 } 1342 1343 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1344 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1345 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 1346 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1347 return 0; 1348 } 1349 1350 static int 1351 txgbe_check_mq_mode(struct rte_eth_dev *dev) 1352 { 1353 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 1354 uint16_t nb_rx_q = dev->data->nb_rx_queues; 1355 uint16_t nb_tx_q = dev->data->nb_tx_queues; 1356 1357 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 1358 /* check multi-queue mode */ 1359 switch (dev_conf->rxmode.mq_mode) { 1360 case ETH_MQ_RX_VMDQ_DCB: 1361 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 1362 break; 1363 case ETH_MQ_RX_VMDQ_DCB_RSS: 1364 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 1365 PMD_INIT_LOG(ERR, "SRIOV active," 1366 " unsupported mq_mode rx %d.", 1367 dev_conf->rxmode.mq_mode); 1368 return -EINVAL; 1369 case ETH_MQ_RX_RSS: 1370 case ETH_MQ_RX_VMDQ_RSS: 1371 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 1372 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 1373 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 1374 PMD_INIT_LOG(ERR, "SRIOV is active," 1375 " invalid queue number" 1376 " for VMDQ RSS, allowed" 1377 " value are 1, 2 or 4."); 1378 return -EINVAL; 1379 } 1380 break; 1381 case ETH_MQ_RX_VMDQ_ONLY: 1382 case ETH_MQ_RX_NONE: 1383 /* if nothing mq mode configure, use default scheme */ 1384 dev->data->dev_conf.rxmode.mq_mode = 1385 ETH_MQ_RX_VMDQ_ONLY; 1386 break; 1387 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 1388 /* SRIOV only works in VMDq enable mode */ 1389 PMD_INIT_LOG(ERR, "SRIOV is active," 1390 " wrong mq_mode rx %d.", 1391 dev_conf->rxmode.mq_mode); 1392 return -EINVAL; 1393 } 1394 1395 switch (dev_conf->txmode.mq_mode) { 1396 case ETH_MQ_TX_VMDQ_DCB: 1397 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 1398 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 1399 break; 1400 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 1401 dev->data->dev_conf.txmode.mq_mode = 1402 ETH_MQ_TX_VMDQ_ONLY; 1403 break; 1404 } 1405 1406 /* check valid queue number */ 1407 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 1408 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 1409 PMD_INIT_LOG(ERR, "SRIOV is active," 1410 " nb_rx_q=%d nb_tx_q=%d queue number" 1411 " must be less than or equal to %d.", 1412 nb_rx_q, nb_tx_q, 1413 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 1414 return -EINVAL; 1415 } 1416 } else { 1417 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 1418 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 1419 " not supported."); 1420 return -EINVAL; 1421 } 1422 /* check configuration for vmdb+dcb mode */ 1423 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 1424 const struct rte_eth_vmdq_dcb_conf *conf; 1425 1426 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1427 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 1428 TXGBE_VMDQ_DCB_NB_QUEUES); 1429 return -EINVAL; 1430 } 1431 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 1432 if (!(conf->nb_queue_pools == ETH_16_POOLS || 1433 conf->nb_queue_pools == ETH_32_POOLS)) { 1434 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1435 " nb_queue_pools must be %d or %d.", 1436 ETH_16_POOLS, ETH_32_POOLS); 1437 return -EINVAL; 1438 } 1439 } 1440 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 1441 const struct rte_eth_vmdq_dcb_tx_conf *conf; 1442 1443 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) { 1444 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 1445 TXGBE_VMDQ_DCB_NB_QUEUES); 1446 return -EINVAL; 1447 } 1448 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 1449 if (!(conf->nb_queue_pools == ETH_16_POOLS || 1450 conf->nb_queue_pools == ETH_32_POOLS)) { 1451 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 1452 " nb_queue_pools != %d and" 1453 " nb_queue_pools != %d.", 1454 ETH_16_POOLS, ETH_32_POOLS); 1455 return -EINVAL; 1456 } 1457 } 1458 1459 /* For DCB mode check our configuration before we go further */ 1460 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 1461 const struct rte_eth_dcb_rx_conf *conf; 1462 1463 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 1464 if (!(conf->nb_tcs == ETH_4_TCS || 1465 conf->nb_tcs == ETH_8_TCS)) { 1466 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1467 " and nb_tcs != %d.", 1468 ETH_4_TCS, ETH_8_TCS); 1469 return -EINVAL; 1470 } 1471 } 1472 1473 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 1474 const struct rte_eth_dcb_tx_conf *conf; 1475 1476 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 1477 if (!(conf->nb_tcs == ETH_4_TCS || 1478 conf->nb_tcs == ETH_8_TCS)) { 1479 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 1480 " and nb_tcs != %d.", 1481 ETH_4_TCS, ETH_8_TCS); 1482 return -EINVAL; 1483 } 1484 } 1485 } 1486 return 0; 1487 } 1488 1489 static int 1490 txgbe_dev_configure(struct rte_eth_dev *dev) 1491 { 1492 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1493 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1494 int ret; 1495 1496 PMD_INIT_FUNC_TRACE(); 1497 1498 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1499 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1500 1501 /* multiple queue mode checking */ 1502 ret = txgbe_check_mq_mode(dev); 1503 if (ret != 0) { 1504 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.", 1505 ret); 1506 return ret; 1507 } 1508 1509 /* set flag to update link status after init */ 1510 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 1511 1512 /* 1513 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 1514 * allocation Rx preconditions we will reset it. 1515 */ 1516 adapter->rx_bulk_alloc_allowed = true; 1517 1518 return 0; 1519 } 1520 1521 static void 1522 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 1523 { 1524 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1525 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 1526 uint32_t gpie; 1527 1528 gpie = rd32(hw, TXGBE_GPIOINTEN); 1529 gpie |= TXGBE_GPIOBIT_6; 1530 wr32(hw, TXGBE_GPIOINTEN, gpie); 1531 intr->mask_misc |= TXGBE_ICRMISC_GPIO; 1532 intr->mask_misc |= TXGBE_ICRMISC_ANDONE; 1533 } 1534 1535 int 1536 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 1537 uint16_t tx_rate, uint64_t q_msk) 1538 { 1539 struct txgbe_hw *hw; 1540 struct txgbe_vf_info *vfinfo; 1541 struct rte_eth_link link; 1542 uint8_t nb_q_per_pool; 1543 uint32_t queue_stride; 1544 uint32_t queue_idx, idx = 0, vf_idx; 1545 uint32_t queue_end; 1546 uint16_t total_rate = 0; 1547 struct rte_pci_device *pci_dev; 1548 int ret; 1549 1550 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1551 ret = rte_eth_link_get_nowait(dev->data->port_id, &link); 1552 if (ret < 0) 1553 return ret; 1554 1555 if (vf >= pci_dev->max_vfs) 1556 return -EINVAL; 1557 1558 if (tx_rate > link.link_speed) 1559 return -EINVAL; 1560 1561 if (q_msk == 0) 1562 return 0; 1563 1564 hw = TXGBE_DEV_HW(dev); 1565 vfinfo = *(TXGBE_DEV_VFDATA(dev)); 1566 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 1567 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 1568 queue_idx = vf * queue_stride; 1569 queue_end = queue_idx + nb_q_per_pool - 1; 1570 if (queue_end >= hw->mac.max_tx_queues) 1571 return -EINVAL; 1572 1573 if (vfinfo) { 1574 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 1575 if (vf_idx == vf) 1576 continue; 1577 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 1578 idx++) 1579 total_rate += vfinfo[vf_idx].tx_rate[idx]; 1580 } 1581 } else { 1582 return -EINVAL; 1583 } 1584 1585 /* Store tx_rate for this vf. */ 1586 for (idx = 0; idx < nb_q_per_pool; idx++) { 1587 if (((uint64_t)0x1 << idx) & q_msk) { 1588 if (vfinfo[vf].tx_rate[idx] != tx_rate) 1589 vfinfo[vf].tx_rate[idx] = tx_rate; 1590 total_rate += tx_rate; 1591 } 1592 } 1593 1594 if (total_rate > dev->data->dev_link.link_speed) { 1595 /* Reset stored TX rate of the VF if it causes exceed 1596 * link speed. 1597 */ 1598 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 1599 return -EINVAL; 1600 } 1601 1602 /* Set ARBTXRATE of each queue/pool for vf X */ 1603 for (; queue_idx <= queue_end; queue_idx++) { 1604 if (0x1 & q_msk) 1605 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 1606 q_msk = q_msk >> 1; 1607 } 1608 1609 return 0; 1610 } 1611 1612 /* 1613 * Configure device link speed and setup link. 1614 * It returns 0 on success. 1615 */ 1616 static int 1617 txgbe_dev_start(struct rte_eth_dev *dev) 1618 { 1619 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1620 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 1621 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1622 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1623 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1624 uint32_t intr_vector = 0; 1625 int err; 1626 bool link_up = false, negotiate = 0; 1627 uint32_t speed = 0; 1628 uint32_t allowed_speeds = 0; 1629 int mask = 0; 1630 int status; 1631 uint16_t vf, idx; 1632 uint32_t *link_speeds; 1633 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1634 1635 PMD_INIT_FUNC_TRACE(); 1636 1637 /* Stop the link setup handler before resetting the HW. */ 1638 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1639 1640 /* disable uio/vfio intr/eventfd mapping */ 1641 rte_intr_disable(intr_handle); 1642 1643 /* stop adapter */ 1644 hw->adapter_stopped = 0; 1645 txgbe_stop_hw(hw); 1646 1647 /* reinitialize adapter 1648 * this calls reset and start 1649 */ 1650 hw->nb_rx_queues = dev->data->nb_rx_queues; 1651 hw->nb_tx_queues = dev->data->nb_tx_queues; 1652 status = txgbe_pf_reset_hw(hw); 1653 if (status != 0) 1654 return -1; 1655 hw->mac.start_hw(hw); 1656 hw->mac.get_link_status = true; 1657 hw->dev_start = true; 1658 1659 /* configure PF module if SRIOV enabled */ 1660 txgbe_pf_host_configure(dev); 1661 1662 txgbe_dev_phy_intr_setup(dev); 1663 1664 /* check and configure queue intr-vector mapping */ 1665 if ((rte_intr_cap_multiple(intr_handle) || 1666 !RTE_ETH_DEV_SRIOV(dev).active) && 1667 dev->data->dev_conf.intr_conf.rxq != 0) { 1668 intr_vector = dev->data->nb_rx_queues; 1669 if (rte_intr_efd_enable(intr_handle, intr_vector)) 1670 return -1; 1671 } 1672 1673 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 1674 intr_handle->intr_vec = 1675 rte_zmalloc("intr_vec", 1676 dev->data->nb_rx_queues * sizeof(int), 0); 1677 if (intr_handle->intr_vec == NULL) { 1678 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 1679 " intr_vec", dev->data->nb_rx_queues); 1680 return -ENOMEM; 1681 } 1682 } 1683 1684 /* confiugre msix for sleep until rx interrupt */ 1685 txgbe_configure_msix(dev); 1686 1687 /* initialize transmission unit */ 1688 txgbe_dev_tx_init(dev); 1689 1690 /* This can fail when allocating mbufs for descriptor rings */ 1691 err = txgbe_dev_rx_init(dev); 1692 if (err) { 1693 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 1694 goto error; 1695 } 1696 1697 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 1698 ETH_VLAN_EXTEND_MASK; 1699 err = txgbe_vlan_offload_config(dev, mask); 1700 if (err) { 1701 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 1702 goto error; 1703 } 1704 1705 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 1706 /* Enable vlan filtering for VMDq */ 1707 txgbe_vmdq_vlan_hw_filter_enable(dev); 1708 } 1709 1710 /* Configure DCB hw */ 1711 txgbe_configure_pb(dev); 1712 txgbe_configure_port(dev); 1713 txgbe_configure_dcb(dev); 1714 1715 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1716 err = txgbe_fdir_configure(dev); 1717 if (err) 1718 goto error; 1719 } 1720 1721 /* Restore vf rate limit */ 1722 if (vfinfo != NULL) { 1723 for (vf = 0; vf < pci_dev->max_vfs; vf++) 1724 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 1725 if (vfinfo[vf].tx_rate[idx] != 0) 1726 txgbe_set_vf_rate_limit(dev, vf, 1727 vfinfo[vf].tx_rate[idx], 1728 1 << idx); 1729 } 1730 1731 err = txgbe_dev_rxtx_start(dev); 1732 if (err < 0) { 1733 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 1734 goto error; 1735 } 1736 1737 /* Skip link setup if loopback mode is enabled. */ 1738 if (hw->mac.type == txgbe_mac_raptor && 1739 dev->data->dev_conf.lpbk_mode) 1740 goto skip_link_setup; 1741 1742 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 1743 err = hw->mac.setup_sfp(hw); 1744 if (err) 1745 goto error; 1746 } 1747 1748 if (hw->phy.media_type == txgbe_media_type_copper) { 1749 /* Turn on the copper */ 1750 hw->phy.set_phy_power(hw, true); 1751 } else { 1752 /* Turn on the laser */ 1753 hw->mac.enable_tx_laser(hw); 1754 } 1755 1756 if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4) 1757 err = hw->mac.check_link(hw, &speed, &link_up, 0); 1758 if (err) 1759 goto error; 1760 dev->data->dev_link.link_status = link_up; 1761 1762 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate); 1763 if (err) 1764 goto error; 1765 1766 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 1767 ETH_LINK_SPEED_10G; 1768 1769 link_speeds = &dev->data->dev_conf.link_speeds; 1770 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) { 1771 PMD_INIT_LOG(ERR, "Invalid link setting"); 1772 goto error; 1773 } 1774 1775 speed = 0x0; 1776 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 1777 speed = (TXGBE_LINK_SPEED_100M_FULL | 1778 TXGBE_LINK_SPEED_1GB_FULL | 1779 TXGBE_LINK_SPEED_10GB_FULL); 1780 } else { 1781 if (*link_speeds & ETH_LINK_SPEED_10G) 1782 speed |= TXGBE_LINK_SPEED_10GB_FULL; 1783 if (*link_speeds & ETH_LINK_SPEED_5G) 1784 speed |= TXGBE_LINK_SPEED_5GB_FULL; 1785 if (*link_speeds & ETH_LINK_SPEED_2_5G) 1786 speed |= TXGBE_LINK_SPEED_2_5GB_FULL; 1787 if (*link_speeds & ETH_LINK_SPEED_1G) 1788 speed |= TXGBE_LINK_SPEED_1GB_FULL; 1789 if (*link_speeds & ETH_LINK_SPEED_100M) 1790 speed |= TXGBE_LINK_SPEED_100M_FULL; 1791 } 1792 1793 err = hw->mac.setup_link(hw, speed, link_up); 1794 if (err) 1795 goto error; 1796 1797 skip_link_setup: 1798 1799 if (rte_intr_allow_others(intr_handle)) { 1800 txgbe_dev_misc_interrupt_setup(dev); 1801 /* check if lsc interrupt is enabled */ 1802 if (dev->data->dev_conf.intr_conf.lsc != 0) 1803 txgbe_dev_lsc_interrupt_setup(dev, TRUE); 1804 else 1805 txgbe_dev_lsc_interrupt_setup(dev, FALSE); 1806 txgbe_dev_macsec_interrupt_setup(dev); 1807 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 1808 } else { 1809 rte_intr_callback_unregister(intr_handle, 1810 txgbe_dev_interrupt_handler, dev); 1811 if (dev->data->dev_conf.intr_conf.lsc != 0) 1812 PMD_INIT_LOG(INFO, "lsc won't enable because of" 1813 " no intr multiplex"); 1814 } 1815 1816 /* check if rxq interrupt is enabled */ 1817 if (dev->data->dev_conf.intr_conf.rxq != 0 && 1818 rte_intr_dp_is_en(intr_handle)) 1819 txgbe_dev_rxq_interrupt_setup(dev); 1820 1821 /* enable uio/vfio intr/eventfd mapping */ 1822 rte_intr_enable(intr_handle); 1823 1824 /* resume enabled intr since hw reset */ 1825 txgbe_enable_intr(dev); 1826 txgbe_l2_tunnel_conf(dev); 1827 txgbe_filter_restore(dev); 1828 1829 if (tm_conf->root && !tm_conf->committed) 1830 PMD_DRV_LOG(WARNING, 1831 "please call hierarchy_commit() " 1832 "before starting the port"); 1833 1834 /* 1835 * Update link status right before return, because it may 1836 * start link configuration process in a separate thread. 1837 */ 1838 txgbe_dev_link_update(dev, 0); 1839 1840 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK); 1841 1842 txgbe_read_stats_registers(hw, hw_stats); 1843 hw->offset_loaded = 1; 1844 1845 return 0; 1846 1847 error: 1848 PMD_INIT_LOG(ERR, "failure in dev start: %d", err); 1849 txgbe_dev_clear_queues(dev); 1850 return -EIO; 1851 } 1852 1853 /* 1854 * Stop device: disable rx and tx functions to allow for reconfiguring. 1855 */ 1856 static int 1857 txgbe_dev_stop(struct rte_eth_dev *dev) 1858 { 1859 struct rte_eth_link link; 1860 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 1861 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1862 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev); 1863 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1864 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1865 int vf; 1866 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev); 1867 1868 if (hw->adapter_stopped) 1869 return 0; 1870 1871 PMD_INIT_FUNC_TRACE(); 1872 1873 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); 1874 1875 /* disable interrupts */ 1876 txgbe_disable_intr(hw); 1877 1878 /* reset the NIC */ 1879 txgbe_pf_reset_hw(hw); 1880 hw->adapter_stopped = 0; 1881 1882 /* stop adapter */ 1883 txgbe_stop_hw(hw); 1884 1885 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 1886 vfinfo[vf].clear_to_send = false; 1887 1888 if (hw->phy.media_type == txgbe_media_type_copper) { 1889 /* Turn off the copper */ 1890 hw->phy.set_phy_power(hw, false); 1891 } else { 1892 /* Turn off the laser */ 1893 hw->mac.disable_tx_laser(hw); 1894 } 1895 1896 txgbe_dev_clear_queues(dev); 1897 1898 /* Clear stored conf */ 1899 dev->data->scattered_rx = 0; 1900 dev->data->lro = 0; 1901 1902 /* Clear recorded link status */ 1903 memset(&link, 0, sizeof(link)); 1904 rte_eth_linkstatus_set(dev, &link); 1905 1906 if (!rte_intr_allow_others(intr_handle)) 1907 /* resume to the default handler */ 1908 rte_intr_callback_register(intr_handle, 1909 txgbe_dev_interrupt_handler, 1910 (void *)dev); 1911 1912 /* Clean datapath event and queue/vec mapping */ 1913 rte_intr_efd_disable(intr_handle); 1914 if (intr_handle->intr_vec != NULL) { 1915 rte_free(intr_handle->intr_vec); 1916 intr_handle->intr_vec = NULL; 1917 } 1918 1919 /* reset hierarchy commit */ 1920 tm_conf->committed = false; 1921 1922 adapter->rss_reta_updated = 0; 1923 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK); 1924 1925 hw->adapter_stopped = true; 1926 dev->data->dev_started = 0; 1927 hw->dev_start = false; 1928 1929 return 0; 1930 } 1931 1932 /* 1933 * Set device link up: enable tx. 1934 */ 1935 static int 1936 txgbe_dev_set_link_up(struct rte_eth_dev *dev) 1937 { 1938 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1939 1940 if (hw->phy.media_type == txgbe_media_type_copper) { 1941 /* Turn on the copper */ 1942 hw->phy.set_phy_power(hw, true); 1943 } else { 1944 /* Turn on the laser */ 1945 hw->mac.enable_tx_laser(hw); 1946 txgbe_dev_link_update(dev, 0); 1947 } 1948 1949 return 0; 1950 } 1951 1952 /* 1953 * Set device link down: disable tx. 1954 */ 1955 static int 1956 txgbe_dev_set_link_down(struct rte_eth_dev *dev) 1957 { 1958 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1959 1960 if (hw->phy.media_type == txgbe_media_type_copper) { 1961 /* Turn off the copper */ 1962 hw->phy.set_phy_power(hw, false); 1963 } else { 1964 /* Turn off the laser */ 1965 hw->mac.disable_tx_laser(hw); 1966 txgbe_dev_link_update(dev, 0); 1967 } 1968 1969 return 0; 1970 } 1971 1972 /* 1973 * Reset and stop device. 1974 */ 1975 static int 1976 txgbe_dev_close(struct rte_eth_dev *dev) 1977 { 1978 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 1979 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1980 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1981 int retries = 0; 1982 int ret; 1983 1984 PMD_INIT_FUNC_TRACE(); 1985 1986 txgbe_pf_reset_hw(hw); 1987 1988 ret = txgbe_dev_stop(dev); 1989 1990 txgbe_dev_free_queues(dev); 1991 1992 /* reprogram the RAR[0] in case user changed it. */ 1993 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true); 1994 1995 /* Unlock any pending hardware semaphore */ 1996 txgbe_swfw_lock_reset(hw); 1997 1998 /* disable uio intr before callback unregister */ 1999 rte_intr_disable(intr_handle); 2000 2001 do { 2002 ret = rte_intr_callback_unregister(intr_handle, 2003 txgbe_dev_interrupt_handler, dev); 2004 if (ret >= 0 || ret == -ENOENT) { 2005 break; 2006 } else if (ret != -EAGAIN) { 2007 PMD_INIT_LOG(ERR, 2008 "intr callback unregister failed: %d", 2009 ret); 2010 } 2011 rte_delay_ms(100); 2012 } while (retries++ < (10 + TXGBE_LINK_UP_TIME)); 2013 2014 /* cancel the delay handler before remove dev */ 2015 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev); 2016 2017 /* uninitialize PF if max_vfs not zero */ 2018 txgbe_pf_host_uninit(dev); 2019 2020 rte_free(dev->data->mac_addrs); 2021 dev->data->mac_addrs = NULL; 2022 2023 rte_free(dev->data->hash_mac_addrs); 2024 dev->data->hash_mac_addrs = NULL; 2025 2026 /* remove all the fdir filters & hash */ 2027 txgbe_fdir_filter_uninit(dev); 2028 2029 /* remove all the L2 tunnel filters & hash */ 2030 txgbe_l2_tn_filter_uninit(dev); 2031 2032 /* Remove all ntuple filters of the device */ 2033 txgbe_ntuple_filter_uninit(dev); 2034 2035 /* clear all the filters list */ 2036 txgbe_filterlist_flush(); 2037 2038 /* Remove all Traffic Manager configuration */ 2039 txgbe_tm_conf_uninit(dev); 2040 2041 #ifdef RTE_LIB_SECURITY 2042 rte_free(dev->security_ctx); 2043 #endif 2044 2045 return ret; 2046 } 2047 2048 /* 2049 * Reset PF device. 2050 */ 2051 static int 2052 txgbe_dev_reset(struct rte_eth_dev *dev) 2053 { 2054 int ret; 2055 2056 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2057 * its VF to make them align with it. The detailed notification 2058 * mechanism is PMD specific. As to txgbe PF, it is rather complex. 2059 * To avoid unexpected behavior in VF, currently reset of PF with 2060 * SR-IOV activation is not supported. It might be supported later. 2061 */ 2062 if (dev->data->sriov.active) 2063 return -ENOTSUP; 2064 2065 ret = eth_txgbe_dev_uninit(dev); 2066 if (ret) 2067 return ret; 2068 2069 ret = eth_txgbe_dev_init(dev, NULL); 2070 2071 return ret; 2072 } 2073 2074 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \ 2075 { \ 2076 uint32_t current_counter = rd32(hw, reg); \ 2077 if (current_counter < last_counter) \ 2078 current_counter += 0x100000000LL; \ 2079 if (!hw->offset_loaded) \ 2080 last_counter = current_counter; \ 2081 counter = current_counter - last_counter; \ 2082 counter &= 0xFFFFFFFFLL; \ 2083 } 2084 2085 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ 2086 { \ 2087 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \ 2088 uint64_t current_counter_msb = rd32(hw, reg_msb); \ 2089 uint64_t current_counter = (current_counter_msb << 32) | \ 2090 current_counter_lsb; \ 2091 if (current_counter < last_counter) \ 2092 current_counter += 0x1000000000LL; \ 2093 if (!hw->offset_loaded) \ 2094 last_counter = current_counter; \ 2095 counter = current_counter - last_counter; \ 2096 counter &= 0xFFFFFFFFFLL; \ 2097 } 2098 2099 void 2100 txgbe_read_stats_registers(struct txgbe_hw *hw, 2101 struct txgbe_hw_stats *hw_stats) 2102 { 2103 unsigned int i; 2104 2105 /* QP Stats */ 2106 for (i = 0; i < hw->nb_rx_queues; i++) { 2107 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i), 2108 hw->qp_last[i].rx_qp_packets, 2109 hw_stats->qp[i].rx_qp_packets); 2110 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i), 2111 hw->qp_last[i].rx_qp_bytes, 2112 hw_stats->qp[i].rx_qp_bytes); 2113 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i), 2114 hw->qp_last[i].rx_qp_mc_packets, 2115 hw_stats->qp[i].rx_qp_mc_packets); 2116 } 2117 2118 for (i = 0; i < hw->nb_tx_queues; i++) { 2119 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i), 2120 hw->qp_last[i].tx_qp_packets, 2121 hw_stats->qp[i].tx_qp_packets); 2122 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i), 2123 hw->qp_last[i].tx_qp_bytes, 2124 hw_stats->qp[i].tx_qp_bytes); 2125 } 2126 /* PB Stats */ 2127 for (i = 0; i < TXGBE_MAX_UP; i++) { 2128 hw_stats->up[i].rx_up_xon_packets += 2129 rd32(hw, TXGBE_PBRXUPXON(i)); 2130 hw_stats->up[i].rx_up_xoff_packets += 2131 rd32(hw, TXGBE_PBRXUPXOFF(i)); 2132 hw_stats->up[i].tx_up_xon_packets += 2133 rd32(hw, TXGBE_PBTXUPXON(i)); 2134 hw_stats->up[i].tx_up_xoff_packets += 2135 rd32(hw, TXGBE_PBTXUPXOFF(i)); 2136 hw_stats->up[i].tx_up_xon2off_packets += 2137 rd32(hw, TXGBE_PBTXUPOFF(i)); 2138 hw_stats->up[i].rx_up_dropped += 2139 rd32(hw, TXGBE_PBRXMISS(i)); 2140 } 2141 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON); 2142 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF); 2143 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON); 2144 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF); 2145 2146 /* DMA Stats */ 2147 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT); 2148 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT); 2149 2150 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL); 2151 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL); 2152 hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP); 2153 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP); 2154 2155 /* MAC Stats */ 2156 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL); 2157 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL); 2158 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL); 2159 2160 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL); 2161 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL); 2162 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL); 2163 2164 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL); 2165 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL); 2166 2167 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L); 2168 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L); 2169 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L); 2170 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L); 2171 hw_stats->rx_size_512_to_1023_packets += 2172 rd64(hw, TXGBE_MACRX512TO1023L); 2173 hw_stats->rx_size_1024_to_max_packets += 2174 rd64(hw, TXGBE_MACRX1024TOMAXL); 2175 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L); 2176 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L); 2177 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L); 2178 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L); 2179 hw_stats->tx_size_512_to_1023_packets += 2180 rd64(hw, TXGBE_MACTX512TO1023L); 2181 hw_stats->tx_size_1024_to_max_packets += 2182 rd64(hw, TXGBE_MACTX1024TOMAXL); 2183 2184 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL); 2185 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE); 2186 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER); 2187 2188 /* MNG Stats */ 2189 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS); 2190 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC); 2191 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG); 2192 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG); 2193 2194 /* FCoE Stats */ 2195 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC); 2196 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST); 2197 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC); 2198 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC); 2199 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC); 2200 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC); 2201 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC); 2202 2203 /* Flow Director Stats */ 2204 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH); 2205 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS); 2206 hw_stats->flow_director_added_filters += 2207 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED)); 2208 hw_stats->flow_director_removed_filters += 2209 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED)); 2210 hw_stats->flow_director_filter_add_errors += 2211 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL)); 2212 hw_stats->flow_director_filter_remove_errors += 2213 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL)); 2214 2215 /* MACsec Stats */ 2216 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT); 2217 hw_stats->tx_macsec_pkts_encrypted += 2218 rd32(hw, TXGBE_LSECTX_ENCPKT); 2219 hw_stats->tx_macsec_pkts_protected += 2220 rd32(hw, TXGBE_LSECTX_PROTPKT); 2221 hw_stats->tx_macsec_octets_encrypted += 2222 rd32(hw, TXGBE_LSECTX_ENCOCT); 2223 hw_stats->tx_macsec_octets_protected += 2224 rd32(hw, TXGBE_LSECTX_PROTOCT); 2225 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT); 2226 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT); 2227 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT); 2228 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT); 2229 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT); 2230 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT); 2231 hw_stats->rx_macsec_sc_pkts_unchecked += 2232 rd32(hw, TXGBE_LSECRX_UNCHKPKT); 2233 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT); 2234 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT); 2235 for (i = 0; i < 2; i++) { 2236 hw_stats->rx_macsec_sa_pkts_ok += 2237 rd32(hw, TXGBE_LSECRX_OKPKT(i)); 2238 hw_stats->rx_macsec_sa_pkts_invalid += 2239 rd32(hw, TXGBE_LSECRX_INVPKT(i)); 2240 hw_stats->rx_macsec_sa_pkts_notvalid += 2241 rd32(hw, TXGBE_LSECRX_BADPKT(i)); 2242 } 2243 hw_stats->rx_macsec_sa_pkts_unusedsa += 2244 rd32(hw, TXGBE_LSECRX_INVSAPKT); 2245 hw_stats->rx_macsec_sa_pkts_notusingsa += 2246 rd32(hw, TXGBE_LSECRX_BADSAPKT); 2247 2248 hw_stats->rx_total_missed_packets = 0; 2249 for (i = 0; i < TXGBE_MAX_UP; i++) { 2250 hw_stats->rx_total_missed_packets += 2251 hw_stats->up[i].rx_up_dropped; 2252 } 2253 } 2254 2255 static int 2256 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 2257 { 2258 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2259 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2260 struct txgbe_stat_mappings *stat_mappings = 2261 TXGBE_DEV_STAT_MAPPINGS(dev); 2262 uint32_t i, j; 2263 2264 txgbe_read_stats_registers(hw, hw_stats); 2265 2266 if (stats == NULL) 2267 return -EINVAL; 2268 2269 /* Fill out the rte_eth_stats statistics structure */ 2270 stats->ipackets = hw_stats->rx_packets; 2271 stats->ibytes = hw_stats->rx_bytes; 2272 stats->opackets = hw_stats->tx_packets; 2273 stats->obytes = hw_stats->tx_bytes; 2274 2275 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets)); 2276 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets)); 2277 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes)); 2278 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes)); 2279 memset(&stats->q_errors, 0, sizeof(stats->q_errors)); 2280 for (i = 0; i < TXGBE_MAX_QP; i++) { 2281 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG; 2282 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8; 2283 uint32_t q_map; 2284 2285 q_map = (stat_mappings->rqsm[n] >> offset) 2286 & QMAP_FIELD_RESERVED_BITS_MASK; 2287 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2288 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2289 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets; 2290 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes; 2291 2292 q_map = (stat_mappings->tqsm[n] >> offset) 2293 & QMAP_FIELD_RESERVED_BITS_MASK; 2294 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS 2295 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS); 2296 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets; 2297 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes; 2298 } 2299 2300 /* Rx Errors */ 2301 stats->imissed = hw_stats->rx_total_missed_packets + 2302 hw_stats->rx_dma_drop; 2303 stats->ierrors = hw_stats->rx_crc_errors + 2304 hw_stats->rx_mac_short_packet_dropped + 2305 hw_stats->rx_length_errors + 2306 hw_stats->rx_undersize_errors + 2307 hw_stats->rx_oversize_errors + 2308 hw_stats->rx_drop_packets + 2309 hw_stats->rx_illegal_byte_errors + 2310 hw_stats->rx_error_bytes + 2311 hw_stats->rx_fragment_errors + 2312 hw_stats->rx_fcoe_crc_errors + 2313 hw_stats->rx_fcoe_mbuf_allocation_errors; 2314 2315 /* Tx Errors */ 2316 stats->oerrors = 0; 2317 return 0; 2318 } 2319 2320 static int 2321 txgbe_dev_stats_reset(struct rte_eth_dev *dev) 2322 { 2323 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2324 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2325 2326 /* HW registers are cleared on read */ 2327 hw->offset_loaded = 0; 2328 txgbe_dev_stats_get(dev, NULL); 2329 hw->offset_loaded = 1; 2330 2331 /* Reset software totals */ 2332 memset(hw_stats, 0, sizeof(*hw_stats)); 2333 2334 return 0; 2335 } 2336 2337 /* This function calculates the number of xstats based on the current config */ 2338 static unsigned 2339 txgbe_xstats_calc_num(struct rte_eth_dev *dev) 2340 { 2341 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues); 2342 return TXGBE_NB_HW_STATS + 2343 TXGBE_NB_UP_STATS * TXGBE_MAX_UP + 2344 TXGBE_NB_QP_STATS * nb_queues; 2345 } 2346 2347 static inline int 2348 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size) 2349 { 2350 int nb, st; 2351 2352 /* Extended stats from txgbe_hw_stats */ 2353 if (id < TXGBE_NB_HW_STATS) { 2354 snprintf(name, size, "[hw]%s", 2355 rte_txgbe_stats_strings[id].name); 2356 return 0; 2357 } 2358 id -= TXGBE_NB_HW_STATS; 2359 2360 /* Priority Stats */ 2361 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2362 nb = id / TXGBE_NB_UP_STATS; 2363 st = id % TXGBE_NB_UP_STATS; 2364 snprintf(name, size, "[p%u]%s", nb, 2365 rte_txgbe_up_strings[st].name); 2366 return 0; 2367 } 2368 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2369 2370 /* Queue Stats */ 2371 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2372 nb = id / TXGBE_NB_QP_STATS; 2373 st = id % TXGBE_NB_QP_STATS; 2374 snprintf(name, size, "[q%u]%s", nb, 2375 rte_txgbe_qp_strings[st].name); 2376 return 0; 2377 } 2378 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP; 2379 2380 return -(int)(id + 1); 2381 } 2382 2383 static inline int 2384 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset) 2385 { 2386 int nb, st; 2387 2388 /* Extended stats from txgbe_hw_stats */ 2389 if (id < TXGBE_NB_HW_STATS) { 2390 *offset = rte_txgbe_stats_strings[id].offset; 2391 return 0; 2392 } 2393 id -= TXGBE_NB_HW_STATS; 2394 2395 /* Priority Stats */ 2396 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) { 2397 nb = id / TXGBE_NB_UP_STATS; 2398 st = id % TXGBE_NB_UP_STATS; 2399 *offset = rte_txgbe_up_strings[st].offset + 2400 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t)); 2401 return 0; 2402 } 2403 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP; 2404 2405 /* Queue Stats */ 2406 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) { 2407 nb = id / TXGBE_NB_QP_STATS; 2408 st = id % TXGBE_NB_QP_STATS; 2409 *offset = rte_txgbe_qp_strings[st].offset + 2410 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t)); 2411 return 0; 2412 } 2413 2414 return -1; 2415 } 2416 2417 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 2418 struct rte_eth_xstat_name *xstats_names, unsigned int limit) 2419 { 2420 unsigned int i, count; 2421 2422 count = txgbe_xstats_calc_num(dev); 2423 if (xstats_names == NULL) 2424 return count; 2425 2426 /* Note: limit >= cnt_stats checked upstream 2427 * in rte_eth_xstats_names() 2428 */ 2429 limit = min(limit, count); 2430 2431 /* Extended stats from txgbe_hw_stats */ 2432 for (i = 0; i < limit; i++) { 2433 if (txgbe_get_name_by_id(i, xstats_names[i].name, 2434 sizeof(xstats_names[i].name))) { 2435 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2436 break; 2437 } 2438 } 2439 2440 return i; 2441 } 2442 2443 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 2444 const uint64_t *ids, 2445 struct rte_eth_xstat_name *xstats_names, 2446 unsigned int limit) 2447 { 2448 unsigned int i; 2449 2450 if (ids == NULL) 2451 return txgbe_dev_xstats_get_names(dev, xstats_names, limit); 2452 2453 for (i = 0; i < limit; i++) { 2454 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name, 2455 sizeof(xstats_names[i].name))) { 2456 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2457 return -1; 2458 } 2459 } 2460 2461 return i; 2462 } 2463 2464 static int 2465 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 2466 unsigned int limit) 2467 { 2468 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2469 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2470 unsigned int i, count; 2471 2472 txgbe_read_stats_registers(hw, hw_stats); 2473 2474 /* If this is a reset xstats is NULL, and we have cleared the 2475 * registers by reading them. 2476 */ 2477 count = txgbe_xstats_calc_num(dev); 2478 if (xstats == NULL) 2479 return count; 2480 2481 limit = min(limit, txgbe_xstats_calc_num(dev)); 2482 2483 /* Extended stats from txgbe_hw_stats */ 2484 for (i = 0; i < limit; i++) { 2485 uint32_t offset = 0; 2486 2487 if (txgbe_get_offset_by_id(i, &offset)) { 2488 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2489 break; 2490 } 2491 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset); 2492 xstats[i].id = i; 2493 } 2494 2495 return i; 2496 } 2497 2498 static int 2499 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values, 2500 unsigned int limit) 2501 { 2502 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2503 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2504 unsigned int i, count; 2505 2506 txgbe_read_stats_registers(hw, hw_stats); 2507 2508 /* If this is a reset xstats is NULL, and we have cleared the 2509 * registers by reading them. 2510 */ 2511 count = txgbe_xstats_calc_num(dev); 2512 if (values == NULL) 2513 return count; 2514 2515 limit = min(limit, txgbe_xstats_calc_num(dev)); 2516 2517 /* Extended stats from txgbe_hw_stats */ 2518 for (i = 0; i < limit; i++) { 2519 uint32_t offset; 2520 2521 if (txgbe_get_offset_by_id(i, &offset)) { 2522 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2523 break; 2524 } 2525 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2526 } 2527 2528 return i; 2529 } 2530 2531 static int 2532 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 2533 uint64_t *values, unsigned int limit) 2534 { 2535 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2536 unsigned int i; 2537 2538 if (ids == NULL) 2539 return txgbe_dev_xstats_get_(dev, values, limit); 2540 2541 for (i = 0; i < limit; i++) { 2542 uint32_t offset; 2543 2544 if (txgbe_get_offset_by_id(ids[i], &offset)) { 2545 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i); 2546 break; 2547 } 2548 values[i] = *(uint64_t *)(((char *)hw_stats) + offset); 2549 } 2550 2551 return i; 2552 } 2553 2554 static int 2555 txgbe_dev_xstats_reset(struct rte_eth_dev *dev) 2556 { 2557 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2558 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev); 2559 2560 /* HW registers are cleared on read */ 2561 hw->offset_loaded = 0; 2562 txgbe_read_stats_registers(hw, hw_stats); 2563 hw->offset_loaded = 1; 2564 2565 /* Reset software totals */ 2566 memset(hw_stats, 0, sizeof(*hw_stats)); 2567 2568 return 0; 2569 } 2570 2571 static int 2572 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2573 { 2574 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2575 u32 etrack_id; 2576 int ret; 2577 2578 hw->phy.get_fw_version(hw, &etrack_id); 2579 2580 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 2581 if (ret < 0) 2582 return -EINVAL; 2583 2584 ret += 1; /* add the size of '\0' */ 2585 if (fw_size < (size_t)ret) 2586 return ret; 2587 else 2588 return 0; 2589 } 2590 2591 static int 2592 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 2593 { 2594 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2595 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2596 2597 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 2598 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 2599 dev_info->min_rx_bufsize = 1024; 2600 dev_info->max_rx_pktlen = 15872; 2601 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 2602 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC; 2603 dev_info->max_vfs = pci_dev->max_vfs; 2604 dev_info->max_vmdq_pools = ETH_64_POOLS; 2605 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 2606 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev); 2607 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) | 2608 dev_info->rx_queue_offload_capa); 2609 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev); 2610 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev); 2611 2612 dev_info->default_rxconf = (struct rte_eth_rxconf) { 2613 .rx_thresh = { 2614 .pthresh = TXGBE_DEFAULT_RX_PTHRESH, 2615 .hthresh = TXGBE_DEFAULT_RX_HTHRESH, 2616 .wthresh = TXGBE_DEFAULT_RX_WTHRESH, 2617 }, 2618 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH, 2619 .rx_drop_en = 0, 2620 .offloads = 0, 2621 }; 2622 2623 dev_info->default_txconf = (struct rte_eth_txconf) { 2624 .tx_thresh = { 2625 .pthresh = TXGBE_DEFAULT_TX_PTHRESH, 2626 .hthresh = TXGBE_DEFAULT_TX_HTHRESH, 2627 .wthresh = TXGBE_DEFAULT_TX_WTHRESH, 2628 }, 2629 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH, 2630 .offloads = 0, 2631 }; 2632 2633 dev_info->rx_desc_lim = rx_desc_lim; 2634 dev_info->tx_desc_lim = tx_desc_lim; 2635 2636 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 2637 dev_info->reta_size = ETH_RSS_RETA_SIZE_128; 2638 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL; 2639 2640 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 2641 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 2642 2643 /* Driver-preferred Rx/Tx parameters */ 2644 dev_info->default_rxportconf.burst_size = 32; 2645 dev_info->default_txportconf.burst_size = 32; 2646 dev_info->default_rxportconf.nb_queues = 1; 2647 dev_info->default_txportconf.nb_queues = 1; 2648 dev_info->default_rxportconf.ring_size = 256; 2649 dev_info->default_txportconf.ring_size = 256; 2650 2651 return 0; 2652 } 2653 2654 const uint32_t * 2655 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 2656 { 2657 if (dev->rx_pkt_burst == txgbe_recv_pkts || 2658 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc || 2659 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc || 2660 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc) 2661 return txgbe_get_supported_ptypes(); 2662 2663 return NULL; 2664 } 2665 2666 void 2667 txgbe_dev_setup_link_alarm_handler(void *param) 2668 { 2669 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 2670 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2671 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2672 u32 speed; 2673 bool autoneg = false; 2674 2675 speed = hw->phy.autoneg_advertised; 2676 if (!speed) 2677 hw->mac.get_link_capabilities(hw, &speed, &autoneg); 2678 2679 hw->mac.setup_link(hw, speed, true); 2680 2681 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2682 } 2683 2684 /* return 0 means link status changed, -1 means not changed */ 2685 int 2686 txgbe_dev_link_update_share(struct rte_eth_dev *dev, 2687 int wait_to_complete) 2688 { 2689 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2690 struct rte_eth_link link; 2691 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN; 2692 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2693 bool link_up; 2694 int err; 2695 int wait = 1; 2696 2697 memset(&link, 0, sizeof(link)); 2698 link.link_status = ETH_LINK_DOWN; 2699 link.link_speed = ETH_SPEED_NUM_NONE; 2700 link.link_duplex = ETH_LINK_HALF_DUPLEX; 2701 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 2702 ETH_LINK_SPEED_FIXED); 2703 2704 hw->mac.get_link_status = true; 2705 2706 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG) 2707 return rte_eth_linkstatus_set(dev, &link); 2708 2709 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 2710 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 2711 wait = 0; 2712 2713 err = hw->mac.check_link(hw, &link_speed, &link_up, wait); 2714 2715 if (err != 0) { 2716 link.link_speed = ETH_SPEED_NUM_100M; 2717 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2718 return rte_eth_linkstatus_set(dev, &link); 2719 } 2720 2721 if (link_up == 0) { 2722 if ((hw->subsystem_device_id & 0xFF) == 2723 TXGBE_DEV_ID_KR_KX_KX4) { 2724 hw->mac.bp_down_event(hw); 2725 } else if (hw->phy.media_type == txgbe_media_type_fiber) { 2726 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG; 2727 rte_eal_alarm_set(10, 2728 txgbe_dev_setup_link_alarm_handler, dev); 2729 } 2730 return rte_eth_linkstatus_set(dev, &link); 2731 } else if (!hw->dev_start) { 2732 return rte_eth_linkstatus_set(dev, &link); 2733 } 2734 2735 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG; 2736 link.link_status = ETH_LINK_UP; 2737 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2738 2739 switch (link_speed) { 2740 default: 2741 case TXGBE_LINK_SPEED_UNKNOWN: 2742 link.link_duplex = ETH_LINK_FULL_DUPLEX; 2743 link.link_speed = ETH_SPEED_NUM_100M; 2744 break; 2745 2746 case TXGBE_LINK_SPEED_100M_FULL: 2747 link.link_speed = ETH_SPEED_NUM_100M; 2748 break; 2749 2750 case TXGBE_LINK_SPEED_1GB_FULL: 2751 link.link_speed = ETH_SPEED_NUM_1G; 2752 break; 2753 2754 case TXGBE_LINK_SPEED_2_5GB_FULL: 2755 link.link_speed = ETH_SPEED_NUM_2_5G; 2756 break; 2757 2758 case TXGBE_LINK_SPEED_5GB_FULL: 2759 link.link_speed = ETH_SPEED_NUM_5G; 2760 break; 2761 2762 case TXGBE_LINK_SPEED_10GB_FULL: 2763 link.link_speed = ETH_SPEED_NUM_10G; 2764 break; 2765 } 2766 2767 return rte_eth_linkstatus_set(dev, &link); 2768 } 2769 2770 static int 2771 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 2772 { 2773 return txgbe_dev_link_update_share(dev, wait_to_complete); 2774 } 2775 2776 static int 2777 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 2778 { 2779 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2780 uint32_t fctrl; 2781 2782 fctrl = rd32(hw, TXGBE_PSRCTL); 2783 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP); 2784 wr32(hw, TXGBE_PSRCTL, fctrl); 2785 2786 return 0; 2787 } 2788 2789 static int 2790 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 2791 { 2792 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2793 uint32_t fctrl; 2794 2795 fctrl = rd32(hw, TXGBE_PSRCTL); 2796 fctrl &= (~TXGBE_PSRCTL_UCP); 2797 if (dev->data->all_multicast == 1) 2798 fctrl |= TXGBE_PSRCTL_MCP; 2799 else 2800 fctrl &= (~TXGBE_PSRCTL_MCP); 2801 wr32(hw, TXGBE_PSRCTL, fctrl); 2802 2803 return 0; 2804 } 2805 2806 static int 2807 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 2808 { 2809 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2810 uint32_t fctrl; 2811 2812 fctrl = rd32(hw, TXGBE_PSRCTL); 2813 fctrl |= TXGBE_PSRCTL_MCP; 2814 wr32(hw, TXGBE_PSRCTL, fctrl); 2815 2816 return 0; 2817 } 2818 2819 static int 2820 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 2821 { 2822 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2823 uint32_t fctrl; 2824 2825 if (dev->data->promiscuous == 1) 2826 return 0; /* must remain in all_multicast mode */ 2827 2828 fctrl = rd32(hw, TXGBE_PSRCTL); 2829 fctrl &= (~TXGBE_PSRCTL_MCP); 2830 wr32(hw, TXGBE_PSRCTL, fctrl); 2831 2832 return 0; 2833 } 2834 2835 /** 2836 * It clears the interrupt causes and enables the interrupt. 2837 * It will be called once only during nic initialized. 2838 * 2839 * @param dev 2840 * Pointer to struct rte_eth_dev. 2841 * @param on 2842 * Enable or Disable. 2843 * 2844 * @return 2845 * - On success, zero. 2846 * - On failure, a negative value. 2847 */ 2848 static int 2849 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 2850 { 2851 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2852 2853 txgbe_dev_link_status_print(dev); 2854 if (on) 2855 intr->mask_misc |= TXGBE_ICRMISC_LSC; 2856 else 2857 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 2858 2859 return 0; 2860 } 2861 2862 static int 2863 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev) 2864 { 2865 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2866 u64 mask; 2867 2868 mask = TXGBE_ICR_MASK; 2869 mask &= (1ULL << TXGBE_MISC_VEC_ID); 2870 intr->mask |= mask; 2871 intr->mask_misc |= TXGBE_ICRMISC_GPIO; 2872 intr->mask_misc |= TXGBE_ICRMISC_ANDONE; 2873 return 0; 2874 } 2875 2876 /** 2877 * It clears the interrupt causes and enables the interrupt. 2878 * It will be called once only during nic initialized. 2879 * 2880 * @param dev 2881 * Pointer to struct rte_eth_dev. 2882 * 2883 * @return 2884 * - On success, zero. 2885 * - On failure, a negative value. 2886 */ 2887 static int 2888 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 2889 { 2890 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2891 u64 mask; 2892 2893 mask = TXGBE_ICR_MASK; 2894 mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1); 2895 intr->mask |= mask; 2896 2897 return 0; 2898 } 2899 2900 /** 2901 * It clears the interrupt causes and enables the interrupt. 2902 * It will be called once only during nic initialized. 2903 * 2904 * @param dev 2905 * Pointer to struct rte_eth_dev. 2906 * 2907 * @return 2908 * - On success, zero. 2909 * - On failure, a negative value. 2910 */ 2911 static int 2912 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 2913 { 2914 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2915 2916 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC; 2917 2918 return 0; 2919 } 2920 2921 /* 2922 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update. 2923 * 2924 * @param dev 2925 * Pointer to struct rte_eth_dev. 2926 * 2927 * @return 2928 * - On success, zero. 2929 * - On failure, a negative value. 2930 */ 2931 static int 2932 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, 2933 struct rte_intr_handle *intr_handle) 2934 { 2935 uint32_t eicr; 2936 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 2937 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 2938 2939 if (intr_handle->type != RTE_INTR_HANDLE_UIO && 2940 intr_handle->type != RTE_INTR_HANDLE_VFIO_MSIX) 2941 wr32(hw, TXGBE_PX_INTA, 1); 2942 2943 /* clear all cause mask */ 2944 txgbe_disable_intr(hw); 2945 2946 /* read-on-clear nic registers here */ 2947 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 2948 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 2949 2950 intr->flags = 0; 2951 2952 /* set flag for async link update */ 2953 if (eicr & TXGBE_ICRMISC_LSC) 2954 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; 2955 2956 if (eicr & TXGBE_ICRMISC_ANDONE) 2957 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG; 2958 2959 if (eicr & TXGBE_ICRMISC_VFMBX) 2960 intr->flags |= TXGBE_FLAG_MAILBOX; 2961 2962 if (eicr & TXGBE_ICRMISC_LNKSEC) 2963 intr->flags |= TXGBE_FLAG_MACSEC; 2964 2965 if (eicr & TXGBE_ICRMISC_GPIO) 2966 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT; 2967 2968 return 0; 2969 } 2970 2971 /** 2972 * It gets and then prints the link status. 2973 * 2974 * @param dev 2975 * Pointer to struct rte_eth_dev. 2976 * 2977 * @return 2978 * - On success, zero. 2979 * - On failure, a negative value. 2980 */ 2981 static void 2982 txgbe_dev_link_status_print(struct rte_eth_dev *dev) 2983 { 2984 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2985 struct rte_eth_link link; 2986 2987 rte_eth_linkstatus_get(dev, &link); 2988 2989 if (link.link_status) { 2990 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 2991 (int)(dev->data->port_id), 2992 (unsigned int)link.link_speed, 2993 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 2994 "full-duplex" : "half-duplex"); 2995 } else { 2996 PMD_INIT_LOG(INFO, " Port %d: Link Down", 2997 (int)(dev->data->port_id)); 2998 } 2999 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 3000 pci_dev->addr.domain, 3001 pci_dev->addr.bus, 3002 pci_dev->addr.devid, 3003 pci_dev->addr.function); 3004 } 3005 3006 /* 3007 * It executes link_update after knowing an interrupt occurred. 3008 * 3009 * @param dev 3010 * Pointer to struct rte_eth_dev. 3011 * 3012 * @return 3013 * - On success, zero. 3014 * - On failure, a negative value. 3015 */ 3016 static int 3017 txgbe_dev_interrupt_action(struct rte_eth_dev *dev, 3018 struct rte_intr_handle *intr_handle) 3019 { 3020 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 3021 int64_t timeout; 3022 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3023 3024 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 3025 3026 if (intr->flags & TXGBE_FLAG_MAILBOX) { 3027 txgbe_pf_mbx_process(dev); 3028 intr->flags &= ~TXGBE_FLAG_MAILBOX; 3029 } 3030 3031 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 3032 hw->phy.handle_lasi(hw); 3033 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 3034 } 3035 3036 if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) { 3037 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) { 3038 hw->mac.kr_handle(hw); 3039 intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG; 3040 } 3041 } 3042 3043 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 3044 struct rte_eth_link link; 3045 3046 /*get the link status before link update, for predicting later*/ 3047 rte_eth_linkstatus_get(dev, &link); 3048 3049 txgbe_dev_link_update(dev, 0); 3050 3051 /* likely to up */ 3052 if (!link.link_status) 3053 /* handle it 1 sec later, wait it being stable */ 3054 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT; 3055 /* likely to down */ 3056 else if ((hw->subsystem_device_id & 0xFF) == 3057 TXGBE_DEV_ID_KR_KX_KX4 && 3058 hw->devarg.auto_neg == 1) 3059 /* handle it 2 sec later for backplane AN73 */ 3060 timeout = 2000; 3061 else 3062 /* handle it 4 sec later, wait it being stable */ 3063 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT; 3064 3065 txgbe_dev_link_status_print(dev); 3066 if (rte_eal_alarm_set(timeout * 1000, 3067 txgbe_dev_interrupt_delayed_handler, 3068 (void *)dev) < 0) { 3069 PMD_DRV_LOG(ERR, "Error setting alarm"); 3070 } else { 3071 /* only disable lsc interrupt */ 3072 intr->mask_misc &= ~TXGBE_ICRMISC_LSC; 3073 3074 intr->mask_orig = intr->mask; 3075 /* only disable all misc interrupts */ 3076 intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID); 3077 } 3078 } 3079 3080 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 3081 txgbe_enable_intr(dev); 3082 rte_intr_enable(intr_handle); 3083 3084 return 0; 3085 } 3086 3087 /** 3088 * Interrupt handler which shall be registered for alarm callback for delayed 3089 * handling specific interrupt to wait for the stable nic state. As the 3090 * NIC interrupt state is not stable for txgbe after link is just down, 3091 * it needs to wait 4 seconds to get the stable status. 3092 * 3093 * @param handle 3094 * Pointer to interrupt handle. 3095 * @param param 3096 * The address of parameter (struct rte_eth_dev *) registered before. 3097 * 3098 * @return 3099 * void 3100 */ 3101 static void 3102 txgbe_dev_interrupt_delayed_handler(void *param) 3103 { 3104 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3105 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3106 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3107 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); 3108 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3109 uint32_t eicr; 3110 3111 txgbe_disable_intr(hw); 3112 3113 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; 3114 if (eicr & TXGBE_ICRMISC_VFMBX) 3115 txgbe_pf_mbx_process(dev); 3116 3117 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { 3118 hw->phy.handle_lasi(hw); 3119 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; 3120 } 3121 3122 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) { 3123 txgbe_dev_link_update(dev, 0); 3124 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE; 3125 txgbe_dev_link_status_print(dev); 3126 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 3127 NULL); 3128 } 3129 3130 if (intr->flags & TXGBE_FLAG_MACSEC) { 3131 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 3132 NULL); 3133 intr->flags &= ~TXGBE_FLAG_MACSEC; 3134 } 3135 3136 /* restore original mask */ 3137 intr->mask_misc |= TXGBE_ICRMISC_LSC; 3138 3139 intr->mask = intr->mask_orig; 3140 intr->mask_orig = 0; 3141 3142 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 3143 txgbe_enable_intr(dev); 3144 rte_intr_enable(intr_handle); 3145 } 3146 3147 /** 3148 * Interrupt handler triggered by NIC for handling 3149 * specific interrupt. 3150 * 3151 * @param handle 3152 * Pointer to interrupt handle. 3153 * @param param 3154 * The address of parameter (struct rte_eth_dev *) registered before. 3155 * 3156 * @return 3157 * void 3158 */ 3159 static void 3160 txgbe_dev_interrupt_handler(void *param) 3161 { 3162 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3163 3164 txgbe_dev_interrupt_get_status(dev, dev->intr_handle); 3165 txgbe_dev_interrupt_action(dev, dev->intr_handle); 3166 } 3167 3168 static int 3169 txgbe_dev_led_on(struct rte_eth_dev *dev) 3170 { 3171 struct txgbe_hw *hw; 3172 3173 hw = TXGBE_DEV_HW(dev); 3174 return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP; 3175 } 3176 3177 static int 3178 txgbe_dev_led_off(struct rte_eth_dev *dev) 3179 { 3180 struct txgbe_hw *hw; 3181 3182 hw = TXGBE_DEV_HW(dev); 3183 return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP; 3184 } 3185 3186 static int 3187 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3188 { 3189 struct txgbe_hw *hw; 3190 uint32_t mflcn_reg; 3191 uint32_t fccfg_reg; 3192 int rx_pause; 3193 int tx_pause; 3194 3195 hw = TXGBE_DEV_HW(dev); 3196 3197 fc_conf->pause_time = hw->fc.pause_time; 3198 fc_conf->high_water = hw->fc.high_water[0]; 3199 fc_conf->low_water = hw->fc.low_water[0]; 3200 fc_conf->send_xon = hw->fc.send_xon; 3201 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 3202 3203 /* 3204 * Return rx_pause status according to actual setting of 3205 * RXFCCFG register. 3206 */ 3207 mflcn_reg = rd32(hw, TXGBE_RXFCCFG); 3208 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC)) 3209 rx_pause = 1; 3210 else 3211 rx_pause = 0; 3212 3213 /* 3214 * Return tx_pause status according to actual setting of 3215 * TXFCCFG register. 3216 */ 3217 fccfg_reg = rd32(hw, TXGBE_TXFCCFG); 3218 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC)) 3219 tx_pause = 1; 3220 else 3221 tx_pause = 0; 3222 3223 if (rx_pause && tx_pause) 3224 fc_conf->mode = RTE_FC_FULL; 3225 else if (rx_pause) 3226 fc_conf->mode = RTE_FC_RX_PAUSE; 3227 else if (tx_pause) 3228 fc_conf->mode = RTE_FC_TX_PAUSE; 3229 else 3230 fc_conf->mode = RTE_FC_NONE; 3231 3232 return 0; 3233 } 3234 3235 static int 3236 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 3237 { 3238 struct txgbe_hw *hw; 3239 int err; 3240 uint32_t rx_buf_size; 3241 uint32_t max_high_water; 3242 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3243 txgbe_fc_none, 3244 txgbe_fc_rx_pause, 3245 txgbe_fc_tx_pause, 3246 txgbe_fc_full 3247 }; 3248 3249 PMD_INIT_FUNC_TRACE(); 3250 3251 hw = TXGBE_DEV_HW(dev); 3252 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0)); 3253 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3254 3255 /* 3256 * At least reserve one Ethernet frame for watermark 3257 * high_water/low_water in kilo bytes for txgbe 3258 */ 3259 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3260 if (fc_conf->high_water > max_high_water || 3261 fc_conf->high_water < fc_conf->low_water) { 3262 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3263 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3264 return -EINVAL; 3265 } 3266 3267 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode]; 3268 hw->fc.pause_time = fc_conf->pause_time; 3269 hw->fc.high_water[0] = fc_conf->high_water; 3270 hw->fc.low_water[0] = fc_conf->low_water; 3271 hw->fc.send_xon = fc_conf->send_xon; 3272 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 3273 3274 err = txgbe_fc_enable(hw); 3275 3276 /* Not negotiated is not an error case */ 3277 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) { 3278 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK, 3279 (fc_conf->mac_ctrl_frame_fwd 3280 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP)); 3281 txgbe_flush(hw); 3282 3283 return 0; 3284 } 3285 3286 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err); 3287 return -EIO; 3288 } 3289 3290 static int 3291 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 3292 struct rte_eth_pfc_conf *pfc_conf) 3293 { 3294 int err; 3295 uint32_t rx_buf_size; 3296 uint32_t max_high_water; 3297 uint8_t tc_num; 3298 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 }; 3299 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3300 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 3301 3302 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = { 3303 txgbe_fc_none, 3304 txgbe_fc_rx_pause, 3305 txgbe_fc_tx_pause, 3306 txgbe_fc_full 3307 }; 3308 3309 PMD_INIT_FUNC_TRACE(); 3310 3311 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map); 3312 tc_num = map[pfc_conf->priority]; 3313 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num)); 3314 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 3315 /* 3316 * At least reserve one Ethernet frame for watermark 3317 * high_water/low_water in kilo bytes for txgbe 3318 */ 3319 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10; 3320 if (pfc_conf->fc.high_water > max_high_water || 3321 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) { 3322 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 3323 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 3324 return -EINVAL; 3325 } 3326 3327 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode]; 3328 hw->fc.pause_time = pfc_conf->fc.pause_time; 3329 hw->fc.send_xon = pfc_conf->fc.send_xon; 3330 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 3331 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 3332 3333 err = txgbe_dcb_pfc_enable(hw, tc_num); 3334 3335 /* Not negotiated is not an error case */ 3336 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) 3337 return 0; 3338 3339 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err); 3340 return -EIO; 3341 } 3342 3343 int 3344 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 3345 struct rte_eth_rss_reta_entry64 *reta_conf, 3346 uint16_t reta_size) 3347 { 3348 uint8_t i, j, mask; 3349 uint32_t reta; 3350 uint16_t idx, shift; 3351 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 3352 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3353 3354 PMD_INIT_FUNC_TRACE(); 3355 3356 if (!txgbe_rss_update_sp(hw->mac.type)) { 3357 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 3358 "NIC."); 3359 return -ENOTSUP; 3360 } 3361 3362 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3363 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3364 "(%d) doesn't match the number hardware can supported " 3365 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3366 return -EINVAL; 3367 } 3368 3369 for (i = 0; i < reta_size; i += 4) { 3370 idx = i / RTE_RETA_GROUP_SIZE; 3371 shift = i % RTE_RETA_GROUP_SIZE; 3372 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3373 if (!mask) 3374 continue; 3375 3376 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3377 for (j = 0; j < 4; j++) { 3378 if (RS8(mask, j, 0x1)) { 3379 reta &= ~(MS32(8 * j, 0xFF)); 3380 reta |= LS32(reta_conf[idx].reta[shift + j], 3381 8 * j, 0xFF); 3382 } 3383 } 3384 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta); 3385 } 3386 adapter->rss_reta_updated = 1; 3387 3388 return 0; 3389 } 3390 3391 int 3392 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 3393 struct rte_eth_rss_reta_entry64 *reta_conf, 3394 uint16_t reta_size) 3395 { 3396 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3397 uint8_t i, j, mask; 3398 uint32_t reta; 3399 uint16_t idx, shift; 3400 3401 PMD_INIT_FUNC_TRACE(); 3402 3403 if (reta_size != ETH_RSS_RETA_SIZE_128) { 3404 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 3405 "(%d) doesn't match the number hardware can supported " 3406 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128); 3407 return -EINVAL; 3408 } 3409 3410 for (i = 0; i < reta_size; i += 4) { 3411 idx = i / RTE_RETA_GROUP_SIZE; 3412 shift = i % RTE_RETA_GROUP_SIZE; 3413 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF); 3414 if (!mask) 3415 continue; 3416 3417 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2); 3418 for (j = 0; j < 4; j++) { 3419 if (RS8(mask, j, 0x1)) 3420 reta_conf[idx].reta[shift + j] = 3421 (uint16_t)RS32(reta, 8 * j, 0xFF); 3422 } 3423 } 3424 3425 return 0; 3426 } 3427 3428 static int 3429 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 3430 uint32_t index, uint32_t pool) 3431 { 3432 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3433 uint32_t enable_addr = 1; 3434 3435 return txgbe_set_rar(hw, index, mac_addr->addr_bytes, 3436 pool, enable_addr); 3437 } 3438 3439 static void 3440 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 3441 { 3442 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3443 3444 txgbe_clear_rar(hw, index); 3445 } 3446 3447 static int 3448 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 3449 { 3450 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3451 3452 txgbe_remove_rar(dev, 0); 3453 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 3454 3455 return 0; 3456 } 3457 3458 static int 3459 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 3460 { 3461 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3462 struct rte_eth_dev_info dev_info; 3463 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 3464 struct rte_eth_dev_data *dev_data = dev->data; 3465 int ret; 3466 3467 ret = txgbe_dev_info_get(dev, &dev_info); 3468 if (ret != 0) 3469 return ret; 3470 3471 /* check that mtu is within the allowed range */ 3472 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 3473 return -EINVAL; 3474 3475 /* If device is started, refuse mtu that requires the support of 3476 * scattered packets when this feature has not been enabled before. 3477 */ 3478 if (dev_data->dev_started && !dev_data->scattered_rx && 3479 (frame_size + 2 * TXGBE_VLAN_TAG_SIZE > 3480 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 3481 PMD_INIT_LOG(ERR, "Stop port first."); 3482 return -EINVAL; 3483 } 3484 3485 /* update max frame size */ 3486 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 3487 3488 if (hw->mode) 3489 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3490 TXGBE_FRAME_SIZE_MAX); 3491 else 3492 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK, 3493 TXGBE_FRMSZ_MAX(frame_size)); 3494 3495 return 0; 3496 } 3497 3498 static uint32_t 3499 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr) 3500 { 3501 uint32_t vector = 0; 3502 3503 switch (hw->mac.mc_filter_type) { 3504 case 0: /* use bits [47:36] of the address */ 3505 vector = ((uc_addr->addr_bytes[4] >> 4) | 3506 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 3507 break; 3508 case 1: /* use bits [46:35] of the address */ 3509 vector = ((uc_addr->addr_bytes[4] >> 3) | 3510 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 3511 break; 3512 case 2: /* use bits [45:34] of the address */ 3513 vector = ((uc_addr->addr_bytes[4] >> 2) | 3514 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 3515 break; 3516 case 3: /* use bits [43:32] of the address */ 3517 vector = ((uc_addr->addr_bytes[4]) | 3518 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 3519 break; 3520 default: /* Invalid mc_filter_type */ 3521 break; 3522 } 3523 3524 /* vector can only be 12-bits or boundary will be exceeded */ 3525 vector &= 0xFFF; 3526 return vector; 3527 } 3528 3529 static int 3530 txgbe_uc_hash_table_set(struct rte_eth_dev *dev, 3531 struct rte_ether_addr *mac_addr, uint8_t on) 3532 { 3533 uint32_t vector; 3534 uint32_t uta_idx; 3535 uint32_t reg_val; 3536 uint32_t uta_mask; 3537 uint32_t psrctl; 3538 3539 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3540 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3541 3542 /* The UTA table only exists on pf hardware */ 3543 if (hw->mac.type < txgbe_mac_raptor) 3544 return -ENOTSUP; 3545 3546 vector = txgbe_uta_vector(hw, mac_addr); 3547 uta_idx = (vector >> 5) & 0x7F; 3548 uta_mask = 0x1UL << (vector & 0x1F); 3549 3550 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask)) 3551 return 0; 3552 3553 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx)); 3554 if (on) { 3555 uta_info->uta_in_use++; 3556 reg_val |= uta_mask; 3557 uta_info->uta_shadow[uta_idx] |= uta_mask; 3558 } else { 3559 uta_info->uta_in_use--; 3560 reg_val &= ~uta_mask; 3561 uta_info->uta_shadow[uta_idx] &= ~uta_mask; 3562 } 3563 3564 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val); 3565 3566 psrctl = rd32(hw, TXGBE_PSRCTL); 3567 if (uta_info->uta_in_use > 0) 3568 psrctl |= TXGBE_PSRCTL_UCHFENA; 3569 else 3570 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3571 3572 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3573 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3574 wr32(hw, TXGBE_PSRCTL, psrctl); 3575 3576 return 0; 3577 } 3578 3579 static int 3580 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 3581 { 3582 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3583 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev); 3584 uint32_t psrctl; 3585 int i; 3586 3587 /* The UTA table only exists on pf hardware */ 3588 if (hw->mac.type < txgbe_mac_raptor) 3589 return -ENOTSUP; 3590 3591 if (on) { 3592 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3593 uta_info->uta_shadow[i] = ~0; 3594 wr32(hw, TXGBE_UCADDRTBL(i), ~0); 3595 } 3596 } else { 3597 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 3598 uta_info->uta_shadow[i] = 0; 3599 wr32(hw, TXGBE_UCADDRTBL(i), 0); 3600 } 3601 } 3602 3603 psrctl = rd32(hw, TXGBE_PSRCTL); 3604 if (on) 3605 psrctl |= TXGBE_PSRCTL_UCHFENA; 3606 else 3607 psrctl &= ~TXGBE_PSRCTL_UCHFENA; 3608 3609 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK; 3610 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 3611 wr32(hw, TXGBE_PSRCTL, psrctl); 3612 3613 return 0; 3614 } 3615 3616 uint32_t 3617 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 3618 { 3619 uint32_t new_val = orig_val; 3620 3621 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 3622 new_val |= TXGBE_POOLETHCTL_UTA; 3623 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 3624 new_val |= TXGBE_POOLETHCTL_MCHA; 3625 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 3626 new_val |= TXGBE_POOLETHCTL_UCHA; 3627 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 3628 new_val |= TXGBE_POOLETHCTL_BCA; 3629 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 3630 new_val |= TXGBE_POOLETHCTL_MCP; 3631 3632 return new_val; 3633 } 3634 3635 static int 3636 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 3637 { 3638 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3639 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3640 uint32_t mask; 3641 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3642 3643 if (queue_id < 32) { 3644 mask = rd32(hw, TXGBE_IMS(0)); 3645 mask &= (1 << queue_id); 3646 wr32(hw, TXGBE_IMS(0), mask); 3647 } else if (queue_id < 64) { 3648 mask = rd32(hw, TXGBE_IMS(1)); 3649 mask &= (1 << (queue_id - 32)); 3650 wr32(hw, TXGBE_IMS(1), mask); 3651 } 3652 rte_intr_enable(intr_handle); 3653 3654 return 0; 3655 } 3656 3657 static int 3658 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 3659 { 3660 uint32_t mask; 3661 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3662 3663 if (queue_id < 32) { 3664 mask = rd32(hw, TXGBE_IMS(0)); 3665 mask &= ~(1 << queue_id); 3666 wr32(hw, TXGBE_IMS(0), mask); 3667 } else if (queue_id < 64) { 3668 mask = rd32(hw, TXGBE_IMS(1)); 3669 mask &= ~(1 << (queue_id - 32)); 3670 wr32(hw, TXGBE_IMS(1), mask); 3671 } 3672 3673 return 0; 3674 } 3675 3676 /** 3677 * set the IVAR registers, mapping interrupt causes to vectors 3678 * @param hw 3679 * pointer to txgbe_hw struct 3680 * @direction 3681 * 0 for Rx, 1 for Tx, -1 for other causes 3682 * @queue 3683 * queue to map the corresponding interrupt to 3684 * @msix_vector 3685 * the vector to map to the corresponding queue 3686 */ 3687 void 3688 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction, 3689 uint8_t queue, uint8_t msix_vector) 3690 { 3691 uint32_t tmp, idx; 3692 3693 if (direction == -1) { 3694 /* other causes */ 3695 msix_vector |= TXGBE_IVARMISC_VLD; 3696 idx = 0; 3697 tmp = rd32(hw, TXGBE_IVARMISC); 3698 tmp &= ~(0xFF << idx); 3699 tmp |= (msix_vector << idx); 3700 wr32(hw, TXGBE_IVARMISC, tmp); 3701 } else { 3702 /* rx or tx causes */ 3703 /* Workround for ICR lost */ 3704 idx = ((16 * (queue & 1)) + (8 * direction)); 3705 tmp = rd32(hw, TXGBE_IVAR(queue >> 1)); 3706 tmp &= ~(0xFF << idx); 3707 tmp |= (msix_vector << idx); 3708 wr32(hw, TXGBE_IVAR(queue >> 1), tmp); 3709 } 3710 } 3711 3712 /** 3713 * Sets up the hardware to properly generate MSI-X interrupts 3714 * @hw 3715 * board private structure 3716 */ 3717 static void 3718 txgbe_configure_msix(struct rte_eth_dev *dev) 3719 { 3720 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3721 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 3722 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3723 uint32_t queue_id, base = TXGBE_MISC_VEC_ID; 3724 uint32_t vec = TXGBE_MISC_VEC_ID; 3725 uint32_t gpie; 3726 3727 /* won't configure msix register if no mapping is done 3728 * between intr vector and event fd 3729 * but if misx has been enabled already, need to configure 3730 * auto clean, auto mask and throttling. 3731 */ 3732 gpie = rd32(hw, TXGBE_GPIE); 3733 if (!rte_intr_dp_is_en(intr_handle) && 3734 !(gpie & TXGBE_GPIE_MSIX)) 3735 return; 3736 3737 if (rte_intr_allow_others(intr_handle)) { 3738 base = TXGBE_RX_VEC_START; 3739 vec = base; 3740 } 3741 3742 /* setup GPIE for MSI-x mode */ 3743 gpie = rd32(hw, TXGBE_GPIE); 3744 gpie |= TXGBE_GPIE_MSIX; 3745 wr32(hw, TXGBE_GPIE, gpie); 3746 3747 /* Populate the IVAR table and set the ITR values to the 3748 * corresponding register. 3749 */ 3750 if (rte_intr_dp_is_en(intr_handle)) { 3751 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 3752 queue_id++) { 3753 /* by default, 1:1 mapping */ 3754 txgbe_set_ivar_map(hw, 0, queue_id, vec); 3755 intr_handle->intr_vec[queue_id] = vec; 3756 if (vec < base + intr_handle->nb_efd - 1) 3757 vec++; 3758 } 3759 3760 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID); 3761 } 3762 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID), 3763 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 3764 | TXGBE_ITR_WRDSA); 3765 } 3766 3767 int 3768 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 3769 uint16_t queue_idx, uint16_t tx_rate) 3770 { 3771 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3772 uint32_t bcnrc_val; 3773 3774 if (queue_idx >= hw->mac.max_tx_queues) 3775 return -EINVAL; 3776 3777 if (tx_rate != 0) { 3778 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate); 3779 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2); 3780 } else { 3781 bcnrc_val = 0; 3782 } 3783 3784 /* 3785 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW 3786 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 3787 */ 3788 wr32(hw, TXGBE_ARBTXMMW, 0x14); 3789 3790 /* Set ARBTXRATE of queue X */ 3791 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx); 3792 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val); 3793 txgbe_flush(hw); 3794 3795 return 0; 3796 } 3797 3798 int 3799 txgbe_syn_filter_set(struct rte_eth_dev *dev, 3800 struct rte_eth_syn_filter *filter, 3801 bool add) 3802 { 3803 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3804 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3805 uint32_t syn_info; 3806 uint32_t synqf; 3807 3808 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 3809 return -EINVAL; 3810 3811 syn_info = filter_info->syn_info; 3812 3813 if (add) { 3814 if (syn_info & TXGBE_SYNCLS_ENA) 3815 return -EINVAL; 3816 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue); 3817 synqf |= TXGBE_SYNCLS_ENA; 3818 3819 if (filter->hig_pri) 3820 synqf |= TXGBE_SYNCLS_HIPRIO; 3821 else 3822 synqf &= ~TXGBE_SYNCLS_HIPRIO; 3823 } else { 3824 synqf = rd32(hw, TXGBE_SYNCLS); 3825 if (!(syn_info & TXGBE_SYNCLS_ENA)) 3826 return -ENOENT; 3827 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA); 3828 } 3829 3830 filter_info->syn_info = synqf; 3831 wr32(hw, TXGBE_SYNCLS, synqf); 3832 txgbe_flush(hw); 3833 return 0; 3834 } 3835 3836 static inline enum txgbe_5tuple_protocol 3837 convert_protocol_type(uint8_t protocol_value) 3838 { 3839 if (protocol_value == IPPROTO_TCP) 3840 return TXGBE_5TF_PROT_TCP; 3841 else if (protocol_value == IPPROTO_UDP) 3842 return TXGBE_5TF_PROT_UDP; 3843 else if (protocol_value == IPPROTO_SCTP) 3844 return TXGBE_5TF_PROT_SCTP; 3845 else 3846 return TXGBE_5TF_PROT_NONE; 3847 } 3848 3849 /* inject a 5-tuple filter to HW */ 3850 static inline void 3851 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 3852 struct txgbe_5tuple_filter *filter) 3853 { 3854 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3855 int i; 3856 uint32_t ftqf, sdpqf; 3857 uint32_t l34timir = 0; 3858 uint32_t mask = TXGBE_5TFCTL0_MASK; 3859 3860 i = filter->index; 3861 sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port)); 3862 sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port)); 3863 3864 ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto); 3865 ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority); 3866 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 3867 mask &= ~TXGBE_5TFCTL0_MSADDR; 3868 if (filter->filter_info.dst_ip_mask == 0) 3869 mask &= ~TXGBE_5TFCTL0_MDADDR; 3870 if (filter->filter_info.src_port_mask == 0) 3871 mask &= ~TXGBE_5TFCTL0_MSPORT; 3872 if (filter->filter_info.dst_port_mask == 0) 3873 mask &= ~TXGBE_5TFCTL0_MDPORT; 3874 if (filter->filter_info.proto_mask == 0) 3875 mask &= ~TXGBE_5TFCTL0_MPROTO; 3876 ftqf |= mask; 3877 ftqf |= TXGBE_5TFCTL0_MPOOL; 3878 ftqf |= TXGBE_5TFCTL0_ENA; 3879 3880 wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip)); 3881 wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip)); 3882 wr32(hw, TXGBE_5TFPORT(i), sdpqf); 3883 wr32(hw, TXGBE_5TFCTL0(i), ftqf); 3884 3885 l34timir |= TXGBE_5TFCTL1_QP(filter->queue); 3886 wr32(hw, TXGBE_5TFCTL1(i), l34timir); 3887 } 3888 3889 /* 3890 * add a 5tuple filter 3891 * 3892 * @param 3893 * dev: Pointer to struct rte_eth_dev. 3894 * index: the index the filter allocates. 3895 * filter: pointer to the filter that will be added. 3896 * rx_queue: the queue id the filter assigned to. 3897 * 3898 * @return 3899 * - On success, zero. 3900 * - On failure, a negative value. 3901 */ 3902 static int 3903 txgbe_add_5tuple_filter(struct rte_eth_dev *dev, 3904 struct txgbe_5tuple_filter *filter) 3905 { 3906 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3907 int i, idx, shift; 3908 3909 /* 3910 * look for an unused 5tuple filter index, 3911 * and insert the filter to list. 3912 */ 3913 for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) { 3914 idx = i / (sizeof(uint32_t) * NBBY); 3915 shift = i % (sizeof(uint32_t) * NBBY); 3916 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 3917 filter_info->fivetuple_mask[idx] |= 1 << shift; 3918 filter->index = i; 3919 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 3920 filter, 3921 entries); 3922 break; 3923 } 3924 } 3925 if (i >= TXGBE_MAX_FTQF_FILTERS) { 3926 PMD_DRV_LOG(ERR, "5tuple filters are full."); 3927 return -ENOSYS; 3928 } 3929 3930 txgbe_inject_5tuple_filter(dev, filter); 3931 3932 return 0; 3933 } 3934 3935 /* 3936 * remove a 5tuple filter 3937 * 3938 * @param 3939 * dev: Pointer to struct rte_eth_dev. 3940 * filter: the pointer of the filter will be removed. 3941 */ 3942 static void 3943 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 3944 struct txgbe_5tuple_filter *filter) 3945 { 3946 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 3947 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 3948 uint16_t index = filter->index; 3949 3950 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 3951 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 3952 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 3953 rte_free(filter); 3954 3955 wr32(hw, TXGBE_5TFDADDR(index), 0); 3956 wr32(hw, TXGBE_5TFSADDR(index), 0); 3957 wr32(hw, TXGBE_5TFPORT(index), 0); 3958 wr32(hw, TXGBE_5TFCTL0(index), 0); 3959 wr32(hw, TXGBE_5TFCTL1(index), 0); 3960 } 3961 3962 static inline struct txgbe_5tuple_filter * 3963 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list, 3964 struct txgbe_5tuple_filter_info *key) 3965 { 3966 struct txgbe_5tuple_filter *it; 3967 3968 TAILQ_FOREACH(it, filter_list, entries) { 3969 if (memcmp(key, &it->filter_info, 3970 sizeof(struct txgbe_5tuple_filter_info)) == 0) { 3971 return it; 3972 } 3973 } 3974 return NULL; 3975 } 3976 3977 /* translate elements in struct rte_eth_ntuple_filter 3978 * to struct txgbe_5tuple_filter_info 3979 */ 3980 static inline int 3981 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 3982 struct txgbe_5tuple_filter_info *filter_info) 3983 { 3984 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM || 3985 filter->priority > TXGBE_5TUPLE_MAX_PRI || 3986 filter->priority < TXGBE_5TUPLE_MIN_PRI) 3987 return -EINVAL; 3988 3989 switch (filter->dst_ip_mask) { 3990 case UINT32_MAX: 3991 filter_info->dst_ip_mask = 0; 3992 filter_info->dst_ip = filter->dst_ip; 3993 break; 3994 case 0: 3995 filter_info->dst_ip_mask = 1; 3996 break; 3997 default: 3998 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 3999 return -EINVAL; 4000 } 4001 4002 switch (filter->src_ip_mask) { 4003 case UINT32_MAX: 4004 filter_info->src_ip_mask = 0; 4005 filter_info->src_ip = filter->src_ip; 4006 break; 4007 case 0: 4008 filter_info->src_ip_mask = 1; 4009 break; 4010 default: 4011 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 4012 return -EINVAL; 4013 } 4014 4015 switch (filter->dst_port_mask) { 4016 case UINT16_MAX: 4017 filter_info->dst_port_mask = 0; 4018 filter_info->dst_port = filter->dst_port; 4019 break; 4020 case 0: 4021 filter_info->dst_port_mask = 1; 4022 break; 4023 default: 4024 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 4025 return -EINVAL; 4026 } 4027 4028 switch (filter->src_port_mask) { 4029 case UINT16_MAX: 4030 filter_info->src_port_mask = 0; 4031 filter_info->src_port = filter->src_port; 4032 break; 4033 case 0: 4034 filter_info->src_port_mask = 1; 4035 break; 4036 default: 4037 PMD_DRV_LOG(ERR, "invalid src_port mask."); 4038 return -EINVAL; 4039 } 4040 4041 switch (filter->proto_mask) { 4042 case UINT8_MAX: 4043 filter_info->proto_mask = 0; 4044 filter_info->proto = 4045 convert_protocol_type(filter->proto); 4046 break; 4047 case 0: 4048 filter_info->proto_mask = 1; 4049 break; 4050 default: 4051 PMD_DRV_LOG(ERR, "invalid protocol mask."); 4052 return -EINVAL; 4053 } 4054 4055 filter_info->priority = (uint8_t)filter->priority; 4056 return 0; 4057 } 4058 4059 /* 4060 * add or delete a ntuple filter 4061 * 4062 * @param 4063 * dev: Pointer to struct rte_eth_dev. 4064 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 4065 * add: if true, add filter, if false, remove filter 4066 * 4067 * @return 4068 * - On success, zero. 4069 * - On failure, a negative value. 4070 */ 4071 int 4072 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 4073 struct rte_eth_ntuple_filter *ntuple_filter, 4074 bool add) 4075 { 4076 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4077 struct txgbe_5tuple_filter_info filter_5tuple; 4078 struct txgbe_5tuple_filter *filter; 4079 int ret; 4080 4081 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 4082 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 4083 return -EINVAL; 4084 } 4085 4086 memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info)); 4087 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 4088 if (ret < 0) 4089 return ret; 4090 4091 filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 4092 &filter_5tuple); 4093 if (filter != NULL && add) { 4094 PMD_DRV_LOG(ERR, "filter exists."); 4095 return -EEXIST; 4096 } 4097 if (filter == NULL && !add) { 4098 PMD_DRV_LOG(ERR, "filter doesn't exist."); 4099 return -ENOENT; 4100 } 4101 4102 if (add) { 4103 filter = rte_zmalloc("txgbe_5tuple_filter", 4104 sizeof(struct txgbe_5tuple_filter), 0); 4105 if (filter == NULL) 4106 return -ENOMEM; 4107 rte_memcpy(&filter->filter_info, 4108 &filter_5tuple, 4109 sizeof(struct txgbe_5tuple_filter_info)); 4110 filter->queue = ntuple_filter->queue; 4111 ret = txgbe_add_5tuple_filter(dev, filter); 4112 if (ret < 0) { 4113 rte_free(filter); 4114 return ret; 4115 } 4116 } else { 4117 txgbe_remove_5tuple_filter(dev, filter); 4118 } 4119 4120 return 0; 4121 } 4122 4123 int 4124 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 4125 struct rte_eth_ethertype_filter *filter, 4126 bool add) 4127 { 4128 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4129 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 4130 uint32_t etqf = 0; 4131 uint32_t etqs = 0; 4132 int ret; 4133 struct txgbe_ethertype_filter ethertype_filter; 4134 4135 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM) 4136 return -EINVAL; 4137 4138 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 || 4139 filter->ether_type == RTE_ETHER_TYPE_IPV6) { 4140 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 4141 " ethertype filter.", filter->ether_type); 4142 return -EINVAL; 4143 } 4144 4145 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 4146 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 4147 return -EINVAL; 4148 } 4149 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 4150 PMD_DRV_LOG(ERR, "drop option is unsupported."); 4151 return -EINVAL; 4152 } 4153 4154 ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 4155 if (ret >= 0 && add) { 4156 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 4157 filter->ether_type); 4158 return -EEXIST; 4159 } 4160 if (ret < 0 && !add) { 4161 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 4162 filter->ether_type); 4163 return -ENOENT; 4164 } 4165 4166 if (add) { 4167 etqf = TXGBE_ETFLT_ENA; 4168 etqf |= TXGBE_ETFLT_ETID(filter->ether_type); 4169 etqs |= TXGBE_ETCLS_QPID(filter->queue); 4170 etqs |= TXGBE_ETCLS_QENA; 4171 4172 ethertype_filter.ethertype = filter->ether_type; 4173 ethertype_filter.etqf = etqf; 4174 ethertype_filter.etqs = etqs; 4175 ethertype_filter.conf = FALSE; 4176 ret = txgbe_ethertype_filter_insert(filter_info, 4177 ðertype_filter); 4178 if (ret < 0) { 4179 PMD_DRV_LOG(ERR, "ethertype filters are full."); 4180 return -ENOSPC; 4181 } 4182 } else { 4183 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 4184 if (ret < 0) 4185 return -ENOSYS; 4186 } 4187 wr32(hw, TXGBE_ETFLT(ret), etqf); 4188 wr32(hw, TXGBE_ETCLS(ret), etqs); 4189 txgbe_flush(hw); 4190 4191 return 0; 4192 } 4193 4194 static int 4195 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev, 4196 const struct rte_flow_ops **ops) 4197 { 4198 *ops = &txgbe_flow_ops; 4199 return 0; 4200 } 4201 4202 static u8 * 4203 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw, 4204 u8 **mc_addr_ptr, u32 *vmdq) 4205 { 4206 u8 *mc_addr; 4207 4208 *vmdq = 0; 4209 mc_addr = *mc_addr_ptr; 4210 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); 4211 return mc_addr; 4212 } 4213 4214 int 4215 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 4216 struct rte_ether_addr *mc_addr_set, 4217 uint32_t nb_mc_addr) 4218 { 4219 struct txgbe_hw *hw; 4220 u8 *mc_addr_list; 4221 4222 hw = TXGBE_DEV_HW(dev); 4223 mc_addr_list = (u8 *)mc_addr_set; 4224 return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 4225 txgbe_dev_addr_list_itr, TRUE); 4226 } 4227 4228 static uint64_t 4229 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 4230 { 4231 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4232 uint64_t systime_cycles; 4233 4234 systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL); 4235 systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32; 4236 4237 return systime_cycles; 4238 } 4239 4240 static uint64_t 4241 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4242 { 4243 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4244 uint64_t rx_tstamp_cycles; 4245 4246 /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */ 4247 rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL); 4248 rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32; 4249 4250 return rx_tstamp_cycles; 4251 } 4252 4253 static uint64_t 4254 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 4255 { 4256 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4257 uint64_t tx_tstamp_cycles; 4258 4259 /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */ 4260 tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL); 4261 tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32; 4262 4263 return tx_tstamp_cycles; 4264 } 4265 4266 static void 4267 txgbe_start_timecounters(struct rte_eth_dev *dev) 4268 { 4269 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4270 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4271 struct rte_eth_link link; 4272 uint32_t incval = 0; 4273 uint32_t shift = 0; 4274 4275 /* Get current link speed. */ 4276 txgbe_dev_link_update(dev, 1); 4277 rte_eth_linkstatus_get(dev, &link); 4278 4279 switch (link.link_speed) { 4280 case ETH_SPEED_NUM_100M: 4281 incval = TXGBE_INCVAL_100; 4282 shift = TXGBE_INCVAL_SHIFT_100; 4283 break; 4284 case ETH_SPEED_NUM_1G: 4285 incval = TXGBE_INCVAL_1GB; 4286 shift = TXGBE_INCVAL_SHIFT_1GB; 4287 break; 4288 case ETH_SPEED_NUM_10G: 4289 default: 4290 incval = TXGBE_INCVAL_10GB; 4291 shift = TXGBE_INCVAL_SHIFT_10GB; 4292 break; 4293 } 4294 4295 wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2)); 4296 4297 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 4298 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4299 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 4300 4301 adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4302 adapter->systime_tc.cc_shift = shift; 4303 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 4304 4305 adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4306 adapter->rx_tstamp_tc.cc_shift = shift; 4307 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4308 4309 adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK; 4310 adapter->tx_tstamp_tc.cc_shift = shift; 4311 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 4312 } 4313 4314 static int 4315 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 4316 { 4317 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4318 4319 adapter->systime_tc.nsec += delta; 4320 adapter->rx_tstamp_tc.nsec += delta; 4321 adapter->tx_tstamp_tc.nsec += delta; 4322 4323 return 0; 4324 } 4325 4326 static int 4327 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 4328 { 4329 uint64_t ns; 4330 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4331 4332 ns = rte_timespec_to_ns(ts); 4333 /* Set the timecounters to a new value. */ 4334 adapter->systime_tc.nsec = ns; 4335 adapter->rx_tstamp_tc.nsec = ns; 4336 adapter->tx_tstamp_tc.nsec = ns; 4337 4338 return 0; 4339 } 4340 4341 static int 4342 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 4343 { 4344 uint64_t ns, systime_cycles; 4345 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4346 4347 systime_cycles = txgbe_read_systime_cyclecounter(dev); 4348 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 4349 *ts = rte_ns_to_timespec(ns); 4350 4351 return 0; 4352 } 4353 4354 static int 4355 txgbe_timesync_enable(struct rte_eth_dev *dev) 4356 { 4357 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4358 uint32_t tsync_ctl; 4359 4360 /* Stop the timesync system time. */ 4361 wr32(hw, TXGBE_TSTIMEINC, 0x0); 4362 /* Reset the timesync system time value. */ 4363 wr32(hw, TXGBE_TSTIMEL, 0x0); 4364 wr32(hw, TXGBE_TSTIMEH, 0x0); 4365 4366 txgbe_start_timecounters(dev); 4367 4368 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4369 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 4370 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588); 4371 4372 /* Enable timestamping of received PTP packets. */ 4373 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4374 tsync_ctl |= TXGBE_TSRXCTL_ENA; 4375 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4376 4377 /* Enable timestamping of transmitted PTP packets. */ 4378 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4379 tsync_ctl |= TXGBE_TSTXCTL_ENA; 4380 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4381 4382 txgbe_flush(hw); 4383 4384 return 0; 4385 } 4386 4387 static int 4388 txgbe_timesync_disable(struct rte_eth_dev *dev) 4389 { 4390 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4391 uint32_t tsync_ctl; 4392 4393 /* Disable timestamping of transmitted PTP packets. */ 4394 tsync_ctl = rd32(hw, TXGBE_TSTXCTL); 4395 tsync_ctl &= ~TXGBE_TSTXCTL_ENA; 4396 wr32(hw, TXGBE_TSTXCTL, tsync_ctl); 4397 4398 /* Disable timestamping of received PTP packets. */ 4399 tsync_ctl = rd32(hw, TXGBE_TSRXCTL); 4400 tsync_ctl &= ~TXGBE_TSRXCTL_ENA; 4401 wr32(hw, TXGBE_TSRXCTL, tsync_ctl); 4402 4403 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 4404 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0); 4405 4406 /* Stop incrementating the System Time registers. */ 4407 wr32(hw, TXGBE_TSTIMEINC, 0); 4408 4409 return 0; 4410 } 4411 4412 static int 4413 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 4414 struct timespec *timestamp, 4415 uint32_t flags __rte_unused) 4416 { 4417 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4418 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4419 uint32_t tsync_rxctl; 4420 uint64_t rx_tstamp_cycles; 4421 uint64_t ns; 4422 4423 tsync_rxctl = rd32(hw, TXGBE_TSRXCTL); 4424 if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0) 4425 return -EINVAL; 4426 4427 rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev); 4428 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 4429 *timestamp = rte_ns_to_timespec(ns); 4430 4431 return 0; 4432 } 4433 4434 static int 4435 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 4436 struct timespec *timestamp) 4437 { 4438 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4439 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); 4440 uint32_t tsync_txctl; 4441 uint64_t tx_tstamp_cycles; 4442 uint64_t ns; 4443 4444 tsync_txctl = rd32(hw, TXGBE_TSTXCTL); 4445 if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0) 4446 return -EINVAL; 4447 4448 tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev); 4449 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 4450 *timestamp = rte_ns_to_timespec(ns); 4451 4452 return 0; 4453 } 4454 4455 static int 4456 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused) 4457 { 4458 int count = 0; 4459 int g_ind = 0; 4460 const struct reg_info *reg_group; 4461 const struct reg_info **reg_set = txgbe_regs_others; 4462 4463 while ((reg_group = reg_set[g_ind++])) 4464 count += txgbe_regs_group_count(reg_group); 4465 4466 return count; 4467 } 4468 4469 static int 4470 txgbe_get_regs(struct rte_eth_dev *dev, 4471 struct rte_dev_reg_info *regs) 4472 { 4473 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4474 uint32_t *data = regs->data; 4475 int g_ind = 0; 4476 int count = 0; 4477 const struct reg_info *reg_group; 4478 const struct reg_info **reg_set = txgbe_regs_others; 4479 4480 if (data == NULL) { 4481 regs->length = txgbe_get_reg_length(dev); 4482 regs->width = sizeof(uint32_t); 4483 return 0; 4484 } 4485 4486 /* Support only full register dump */ 4487 if (regs->length == 0 || 4488 regs->length == (uint32_t)txgbe_get_reg_length(dev)) { 4489 regs->version = hw->mac.type << 24 | 4490 hw->revision_id << 16 | 4491 hw->device_id; 4492 while ((reg_group = reg_set[g_ind++])) 4493 count += txgbe_read_regs_group(dev, &data[count], 4494 reg_group); 4495 return 0; 4496 } 4497 4498 return -ENOTSUP; 4499 } 4500 4501 static int 4502 txgbe_get_eeprom_length(struct rte_eth_dev *dev) 4503 { 4504 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4505 4506 /* Return unit is byte count */ 4507 return hw->rom.word_size * 2; 4508 } 4509 4510 static int 4511 txgbe_get_eeprom(struct rte_eth_dev *dev, 4512 struct rte_dev_eeprom_info *in_eeprom) 4513 { 4514 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4515 struct txgbe_rom_info *eeprom = &hw->rom; 4516 uint16_t *data = in_eeprom->data; 4517 int first, length; 4518 4519 first = in_eeprom->offset >> 1; 4520 length = in_eeprom->length >> 1; 4521 if (first > hw->rom.word_size || 4522 ((first + length) > hw->rom.word_size)) 4523 return -EINVAL; 4524 4525 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4526 4527 return eeprom->readw_buffer(hw, first, length, data); 4528 } 4529 4530 static int 4531 txgbe_set_eeprom(struct rte_eth_dev *dev, 4532 struct rte_dev_eeprom_info *in_eeprom) 4533 { 4534 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4535 struct txgbe_rom_info *eeprom = &hw->rom; 4536 uint16_t *data = in_eeprom->data; 4537 int first, length; 4538 4539 first = in_eeprom->offset >> 1; 4540 length = in_eeprom->length >> 1; 4541 if (first > hw->rom.word_size || 4542 ((first + length) > hw->rom.word_size)) 4543 return -EINVAL; 4544 4545 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 4546 4547 return eeprom->writew_buffer(hw, first, length, data); 4548 } 4549 4550 static int 4551 txgbe_get_module_info(struct rte_eth_dev *dev, 4552 struct rte_eth_dev_module_info *modinfo) 4553 { 4554 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4555 uint32_t status; 4556 uint8_t sff8472_rev, addr_mode; 4557 bool page_swap = false; 4558 4559 /* Check whether we support SFF-8472 or not */ 4560 status = hw->phy.read_i2c_eeprom(hw, 4561 TXGBE_SFF_SFF_8472_COMP, 4562 &sff8472_rev); 4563 if (status != 0) 4564 return -EIO; 4565 4566 /* addressing mode is not supported */ 4567 status = hw->phy.read_i2c_eeprom(hw, 4568 TXGBE_SFF_SFF_8472_SWAP, 4569 &addr_mode); 4570 if (status != 0) 4571 return -EIO; 4572 4573 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) { 4574 PMD_DRV_LOG(ERR, 4575 "Address change required to access page 0xA2, " 4576 "but not supported. Please report the module " 4577 "type to the driver maintainers."); 4578 page_swap = true; 4579 } 4580 4581 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) { 4582 /* We have a SFP, but it does not support SFF-8472 */ 4583 modinfo->type = RTE_ETH_MODULE_SFF_8079; 4584 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 4585 } else { 4586 /* We have a SFP which supports a revision of SFF-8472. */ 4587 modinfo->type = RTE_ETH_MODULE_SFF_8472; 4588 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 4589 } 4590 4591 return 0; 4592 } 4593 4594 static int 4595 txgbe_get_module_eeprom(struct rte_eth_dev *dev, 4596 struct rte_dev_eeprom_info *info) 4597 { 4598 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4599 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID; 4600 uint8_t databyte = 0xFF; 4601 uint8_t *data = info->data; 4602 uint32_t i = 0; 4603 4604 if (info->length == 0) 4605 return -EINVAL; 4606 4607 for (i = info->offset; i < info->offset + info->length; i++) { 4608 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 4609 status = hw->phy.read_i2c_eeprom(hw, i, &databyte); 4610 else 4611 status = hw->phy.read_i2c_sff8472(hw, i, &databyte); 4612 4613 if (status != 0) 4614 return -EIO; 4615 4616 data[i - info->offset] = databyte; 4617 } 4618 4619 return 0; 4620 } 4621 4622 bool 4623 txgbe_rss_update_sp(enum txgbe_mac_type mac_type) 4624 { 4625 switch (mac_type) { 4626 case txgbe_mac_raptor: 4627 case txgbe_mac_raptor_vf: 4628 return 1; 4629 default: 4630 return 0; 4631 } 4632 } 4633 4634 static int 4635 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 4636 struct rte_eth_dcb_info *dcb_info) 4637 { 4638 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev); 4639 struct txgbe_dcb_tc_config *tc; 4640 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 4641 uint8_t nb_tcs; 4642 uint8_t i, j; 4643 4644 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 4645 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 4646 else 4647 dcb_info->nb_tcs = 1; 4648 4649 tc_queue = &dcb_info->tc_queue; 4650 nb_tcs = dcb_info->nb_tcs; 4651 4652 if (dcb_config->vt_mode) { /* vt is enabled */ 4653 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 4654 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 4655 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 4656 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 4657 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 4658 for (j = 0; j < nb_tcs; j++) { 4659 tc_queue->tc_rxq[0][j].base = j; 4660 tc_queue->tc_rxq[0][j].nb_queue = 1; 4661 tc_queue->tc_txq[0][j].base = j; 4662 tc_queue->tc_txq[0][j].nb_queue = 1; 4663 } 4664 } else { 4665 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 4666 for (j = 0; j < nb_tcs; j++) { 4667 tc_queue->tc_rxq[i][j].base = 4668 i * nb_tcs + j; 4669 tc_queue->tc_rxq[i][j].nb_queue = 1; 4670 tc_queue->tc_txq[i][j].base = 4671 i * nb_tcs + j; 4672 tc_queue->tc_txq[i][j].nb_queue = 1; 4673 } 4674 } 4675 } 4676 } else { /* vt is disabled */ 4677 struct rte_eth_dcb_rx_conf *rx_conf = 4678 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 4679 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 4680 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 4681 if (dcb_info->nb_tcs == ETH_4_TCS) { 4682 for (i = 0; i < dcb_info->nb_tcs; i++) { 4683 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 4684 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4685 } 4686 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4687 dcb_info->tc_queue.tc_txq[0][1].base = 64; 4688 dcb_info->tc_queue.tc_txq[0][2].base = 96; 4689 dcb_info->tc_queue.tc_txq[0][3].base = 112; 4690 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 4691 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4692 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4693 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4694 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 4695 for (i = 0; i < dcb_info->nb_tcs; i++) { 4696 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 4697 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 4698 } 4699 dcb_info->tc_queue.tc_txq[0][0].base = 0; 4700 dcb_info->tc_queue.tc_txq[0][1].base = 32; 4701 dcb_info->tc_queue.tc_txq[0][2].base = 64; 4702 dcb_info->tc_queue.tc_txq[0][3].base = 80; 4703 dcb_info->tc_queue.tc_txq[0][4].base = 96; 4704 dcb_info->tc_queue.tc_txq[0][5].base = 104; 4705 dcb_info->tc_queue.tc_txq[0][6].base = 112; 4706 dcb_info->tc_queue.tc_txq[0][7].base = 120; 4707 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 4708 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 4709 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 4710 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 4711 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 4712 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 4713 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 4714 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 4715 } 4716 } 4717 for (i = 0; i < dcb_info->nb_tcs; i++) { 4718 tc = &dcb_config->tc_config[i]; 4719 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent; 4720 } 4721 return 0; 4722 } 4723 4724 /* Update e-tag ether type */ 4725 static int 4726 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw, 4727 uint16_t ether_type) 4728 { 4729 uint32_t etag_etype; 4730 4731 etag_etype = rd32(hw, TXGBE_EXTAG); 4732 etag_etype &= ~TXGBE_EXTAG_ETAG_MASK; 4733 etag_etype |= ether_type; 4734 wr32(hw, TXGBE_EXTAG, etag_etype); 4735 txgbe_flush(hw); 4736 4737 return 0; 4738 } 4739 4740 /* Enable e-tag tunnel */ 4741 static int 4742 txgbe_e_tag_enable(struct txgbe_hw *hw) 4743 { 4744 uint32_t etag_etype; 4745 4746 etag_etype = rd32(hw, TXGBE_PORTCTL); 4747 etag_etype |= TXGBE_PORTCTL_ETAG; 4748 wr32(hw, TXGBE_PORTCTL, etag_etype); 4749 txgbe_flush(hw); 4750 4751 return 0; 4752 } 4753 4754 static int 4755 txgbe_e_tag_filter_del(struct rte_eth_dev *dev, 4756 struct txgbe_l2_tunnel_conf *l2_tunnel) 4757 { 4758 int ret = 0; 4759 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4760 uint32_t i, rar_entries; 4761 uint32_t rar_low, rar_high; 4762 4763 rar_entries = hw->mac.num_rar_entries; 4764 4765 for (i = 1; i < rar_entries; i++) { 4766 wr32(hw, TXGBE_ETHADDRIDX, i); 4767 rar_high = rd32(hw, TXGBE_ETHADDRH); 4768 rar_low = rd32(hw, TXGBE_ETHADDRL); 4769 if ((rar_high & TXGBE_ETHADDRH_VLD) && 4770 (rar_high & TXGBE_ETHADDRH_ETAG) && 4771 (TXGBE_ETHADDRL_ETAG(rar_low) == 4772 l2_tunnel->tunnel_id)) { 4773 wr32(hw, TXGBE_ETHADDRL, 0); 4774 wr32(hw, TXGBE_ETHADDRH, 0); 4775 4776 txgbe_clear_vmdq(hw, i, BIT_MASK32); 4777 4778 return ret; 4779 } 4780 } 4781 4782 return ret; 4783 } 4784 4785 static int 4786 txgbe_e_tag_filter_add(struct rte_eth_dev *dev, 4787 struct txgbe_l2_tunnel_conf *l2_tunnel) 4788 { 4789 int ret = 0; 4790 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4791 uint32_t i, rar_entries; 4792 uint32_t rar_low, rar_high; 4793 4794 /* One entry for one tunnel. Try to remove potential existing entry. */ 4795 txgbe_e_tag_filter_del(dev, l2_tunnel); 4796 4797 rar_entries = hw->mac.num_rar_entries; 4798 4799 for (i = 1; i < rar_entries; i++) { 4800 wr32(hw, TXGBE_ETHADDRIDX, i); 4801 rar_high = rd32(hw, TXGBE_ETHADDRH); 4802 if (rar_high & TXGBE_ETHADDRH_VLD) { 4803 continue; 4804 } else { 4805 txgbe_set_vmdq(hw, i, l2_tunnel->pool); 4806 rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG; 4807 rar_low = l2_tunnel->tunnel_id; 4808 4809 wr32(hw, TXGBE_ETHADDRL, rar_low); 4810 wr32(hw, TXGBE_ETHADDRH, rar_high); 4811 4812 return ret; 4813 } 4814 } 4815 4816 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 4817 " Please remove a rule before adding a new one."); 4818 return -EINVAL; 4819 } 4820 4821 static inline struct txgbe_l2_tn_filter * 4822 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info, 4823 struct txgbe_l2_tn_key *key) 4824 { 4825 int ret; 4826 4827 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 4828 if (ret < 0) 4829 return NULL; 4830 4831 return l2_tn_info->hash_map[ret]; 4832 } 4833 4834 static inline int 4835 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4836 struct txgbe_l2_tn_filter *l2_tn_filter) 4837 { 4838 int ret; 4839 4840 ret = rte_hash_add_key(l2_tn_info->hash_handle, 4841 &l2_tn_filter->key); 4842 4843 if (ret < 0) { 4844 PMD_DRV_LOG(ERR, 4845 "Failed to insert L2 tunnel filter" 4846 " to hash table %d!", 4847 ret); 4848 return ret; 4849 } 4850 4851 l2_tn_info->hash_map[ret] = l2_tn_filter; 4852 4853 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4854 4855 return 0; 4856 } 4857 4858 static inline int 4859 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info, 4860 struct txgbe_l2_tn_key *key) 4861 { 4862 int ret; 4863 struct txgbe_l2_tn_filter *l2_tn_filter; 4864 4865 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 4866 4867 if (ret < 0) { 4868 PMD_DRV_LOG(ERR, 4869 "No such L2 tunnel filter to delete %d!", 4870 ret); 4871 return ret; 4872 } 4873 4874 l2_tn_filter = l2_tn_info->hash_map[ret]; 4875 l2_tn_info->hash_map[ret] = NULL; 4876 4877 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 4878 rte_free(l2_tn_filter); 4879 4880 return 0; 4881 } 4882 4883 /* Add l2 tunnel filter */ 4884 int 4885 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 4886 struct txgbe_l2_tunnel_conf *l2_tunnel, 4887 bool restore) 4888 { 4889 int ret; 4890 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4891 struct txgbe_l2_tn_key key; 4892 struct txgbe_l2_tn_filter *node; 4893 4894 if (!restore) { 4895 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4896 key.tn_id = l2_tunnel->tunnel_id; 4897 4898 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key); 4899 4900 if (node) { 4901 PMD_DRV_LOG(ERR, 4902 "The L2 tunnel filter already exists!"); 4903 return -EINVAL; 4904 } 4905 4906 node = rte_zmalloc("txgbe_l2_tn", 4907 sizeof(struct txgbe_l2_tn_filter), 4908 0); 4909 if (!node) 4910 return -ENOMEM; 4911 4912 rte_memcpy(&node->key, 4913 &key, 4914 sizeof(struct txgbe_l2_tn_key)); 4915 node->pool = l2_tunnel->pool; 4916 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node); 4917 if (ret < 0) { 4918 rte_free(node); 4919 return ret; 4920 } 4921 } 4922 4923 switch (l2_tunnel->l2_tunnel_type) { 4924 case RTE_L2_TUNNEL_TYPE_E_TAG: 4925 ret = txgbe_e_tag_filter_add(dev, l2_tunnel); 4926 break; 4927 default: 4928 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4929 ret = -EINVAL; 4930 break; 4931 } 4932 4933 if (!restore && ret < 0) 4934 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4935 4936 return ret; 4937 } 4938 4939 /* Delete l2 tunnel filter */ 4940 int 4941 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 4942 struct txgbe_l2_tunnel_conf *l2_tunnel) 4943 { 4944 int ret; 4945 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 4946 struct txgbe_l2_tn_key key; 4947 4948 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 4949 key.tn_id = l2_tunnel->tunnel_id; 4950 ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key); 4951 if (ret < 0) 4952 return ret; 4953 4954 switch (l2_tunnel->l2_tunnel_type) { 4955 case RTE_L2_TUNNEL_TYPE_E_TAG: 4956 ret = txgbe_e_tag_filter_del(dev, l2_tunnel); 4957 break; 4958 default: 4959 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 4960 ret = -EINVAL; 4961 break; 4962 } 4963 4964 return ret; 4965 } 4966 4967 static int 4968 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 4969 { 4970 int ret = 0; 4971 uint32_t ctrl; 4972 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4973 4974 ctrl = rd32(hw, TXGBE_POOLCTL); 4975 ctrl &= ~TXGBE_POOLCTL_MODE_MASK; 4976 if (en) 4977 ctrl |= TXGBE_PSRPOOL_MODE_ETAG; 4978 wr32(hw, TXGBE_POOLCTL, ctrl); 4979 4980 return ret; 4981 } 4982 4983 /* Add UDP tunneling port */ 4984 static int 4985 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 4986 struct rte_eth_udp_tunnel *udp_tunnel) 4987 { 4988 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 4989 int ret = 0; 4990 4991 if (udp_tunnel == NULL) 4992 return -EINVAL; 4993 4994 switch (udp_tunnel->prot_type) { 4995 case RTE_TUNNEL_TYPE_VXLAN: 4996 if (udp_tunnel->udp_port == 0) { 4997 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 4998 ret = -EINVAL; 4999 break; 5000 } 5001 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port); 5002 break; 5003 case RTE_TUNNEL_TYPE_GENEVE: 5004 if (udp_tunnel->udp_port == 0) { 5005 PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed."); 5006 ret = -EINVAL; 5007 break; 5008 } 5009 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port); 5010 break; 5011 case RTE_TUNNEL_TYPE_TEREDO: 5012 if (udp_tunnel->udp_port == 0) { 5013 PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed."); 5014 ret = -EINVAL; 5015 break; 5016 } 5017 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port); 5018 break; 5019 case RTE_TUNNEL_TYPE_VXLAN_GPE: 5020 if (udp_tunnel->udp_port == 0) { 5021 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 5022 ret = -EINVAL; 5023 break; 5024 } 5025 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port); 5026 break; 5027 default: 5028 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5029 ret = -EINVAL; 5030 break; 5031 } 5032 5033 txgbe_flush(hw); 5034 5035 return ret; 5036 } 5037 5038 /* Remove UDP tunneling port */ 5039 static int 5040 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 5041 struct rte_eth_udp_tunnel *udp_tunnel) 5042 { 5043 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5044 int ret = 0; 5045 uint16_t cur_port; 5046 5047 if (udp_tunnel == NULL) 5048 return -EINVAL; 5049 5050 switch (udp_tunnel->prot_type) { 5051 case RTE_TUNNEL_TYPE_VXLAN: 5052 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT); 5053 if (cur_port != udp_tunnel->udp_port) { 5054 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5055 udp_tunnel->udp_port); 5056 ret = -EINVAL; 5057 break; 5058 } 5059 wr32(hw, TXGBE_VXLANPORT, 0); 5060 break; 5061 case RTE_TUNNEL_TYPE_GENEVE: 5062 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT); 5063 if (cur_port != udp_tunnel->udp_port) { 5064 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5065 udp_tunnel->udp_port); 5066 ret = -EINVAL; 5067 break; 5068 } 5069 wr32(hw, TXGBE_GENEVEPORT, 0); 5070 break; 5071 case RTE_TUNNEL_TYPE_TEREDO: 5072 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT); 5073 if (cur_port != udp_tunnel->udp_port) { 5074 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5075 udp_tunnel->udp_port); 5076 ret = -EINVAL; 5077 break; 5078 } 5079 wr32(hw, TXGBE_TEREDOPORT, 0); 5080 break; 5081 case RTE_TUNNEL_TYPE_VXLAN_GPE: 5082 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORTGPE); 5083 if (cur_port != udp_tunnel->udp_port) { 5084 PMD_DRV_LOG(ERR, "Port %u does not exist.", 5085 udp_tunnel->udp_port); 5086 ret = -EINVAL; 5087 break; 5088 } 5089 wr32(hw, TXGBE_VXLANPORTGPE, 0); 5090 break; 5091 default: 5092 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 5093 ret = -EINVAL; 5094 break; 5095 } 5096 5097 txgbe_flush(hw); 5098 5099 return ret; 5100 } 5101 5102 /* restore n-tuple filter */ 5103 static inline void 5104 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 5105 { 5106 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5107 struct txgbe_5tuple_filter *node; 5108 5109 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 5110 txgbe_inject_5tuple_filter(dev, node); 5111 } 5112 } 5113 5114 /* restore ethernet type filter */ 5115 static inline void 5116 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 5117 { 5118 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5119 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5120 int i; 5121 5122 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5123 if (filter_info->ethertype_mask & (1 << i)) { 5124 wr32(hw, TXGBE_ETFLT(i), 5125 filter_info->ethertype_filters[i].etqf); 5126 wr32(hw, TXGBE_ETCLS(i), 5127 filter_info->ethertype_filters[i].etqs); 5128 txgbe_flush(hw); 5129 } 5130 } 5131 } 5132 5133 /* restore SYN filter */ 5134 static inline void 5135 txgbe_syn_filter_restore(struct rte_eth_dev *dev) 5136 { 5137 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5138 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5139 uint32_t synqf; 5140 5141 synqf = filter_info->syn_info; 5142 5143 if (synqf & TXGBE_SYNCLS_ENA) { 5144 wr32(hw, TXGBE_SYNCLS, synqf); 5145 txgbe_flush(hw); 5146 } 5147 } 5148 5149 /* restore L2 tunnel filter */ 5150 static inline void 5151 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 5152 { 5153 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5154 struct txgbe_l2_tn_filter *node; 5155 struct txgbe_l2_tunnel_conf l2_tn_conf; 5156 5157 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 5158 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 5159 l2_tn_conf.tunnel_id = node->key.tn_id; 5160 l2_tn_conf.pool = node->pool; 5161 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 5162 } 5163 } 5164 5165 /* restore rss filter */ 5166 static inline void 5167 txgbe_rss_filter_restore(struct rte_eth_dev *dev) 5168 { 5169 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5170 5171 if (filter_info->rss_info.conf.queue_num) 5172 txgbe_config_rss_filter(dev, 5173 &filter_info->rss_info, TRUE); 5174 } 5175 5176 static int 5177 txgbe_filter_restore(struct rte_eth_dev *dev) 5178 { 5179 txgbe_ntuple_filter_restore(dev); 5180 txgbe_ethertype_filter_restore(dev); 5181 txgbe_syn_filter_restore(dev); 5182 txgbe_fdir_filter_restore(dev); 5183 txgbe_l2_tn_filter_restore(dev); 5184 txgbe_rss_filter_restore(dev); 5185 5186 return 0; 5187 } 5188 5189 static void 5190 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 5191 { 5192 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5193 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5194 5195 if (l2_tn_info->e_tag_en) 5196 (void)txgbe_e_tag_enable(hw); 5197 5198 if (l2_tn_info->e_tag_fwd_en) 5199 (void)txgbe_e_tag_forwarding_en_dis(dev, 1); 5200 5201 (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 5202 } 5203 5204 /* remove all the n-tuple filters */ 5205 void 5206 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 5207 { 5208 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5209 struct txgbe_5tuple_filter *p_5tuple; 5210 5211 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 5212 txgbe_remove_5tuple_filter(dev, p_5tuple); 5213 } 5214 5215 /* remove all the ether type filters */ 5216 void 5217 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 5218 { 5219 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5220 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5221 int i; 5222 5223 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 5224 if (filter_info->ethertype_mask & (1 << i) && 5225 !filter_info->ethertype_filters[i].conf) { 5226 (void)txgbe_ethertype_filter_remove(filter_info, 5227 (uint8_t)i); 5228 wr32(hw, TXGBE_ETFLT(i), 0); 5229 wr32(hw, TXGBE_ETCLS(i), 0); 5230 txgbe_flush(hw); 5231 } 5232 } 5233 } 5234 5235 /* remove the SYN filter */ 5236 void 5237 txgbe_clear_syn_filter(struct rte_eth_dev *dev) 5238 { 5239 struct txgbe_hw *hw = TXGBE_DEV_HW(dev); 5240 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev); 5241 5242 if (filter_info->syn_info & TXGBE_SYNCLS_ENA) { 5243 filter_info->syn_info = 0; 5244 5245 wr32(hw, TXGBE_SYNCLS, 0); 5246 txgbe_flush(hw); 5247 } 5248 } 5249 5250 /* remove all the L2 tunnel filters */ 5251 int 5252 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 5253 { 5254 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev); 5255 struct txgbe_l2_tn_filter *l2_tn_filter; 5256 struct txgbe_l2_tunnel_conf l2_tn_conf; 5257 int ret = 0; 5258 5259 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 5260 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 5261 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 5262 l2_tn_conf.pool = l2_tn_filter->pool; 5263 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 5264 if (ret < 0) 5265 return ret; 5266 } 5267 5268 return 0; 5269 } 5270 5271 static const struct eth_dev_ops txgbe_eth_dev_ops = { 5272 .dev_configure = txgbe_dev_configure, 5273 .dev_infos_get = txgbe_dev_info_get, 5274 .dev_start = txgbe_dev_start, 5275 .dev_stop = txgbe_dev_stop, 5276 .dev_set_link_up = txgbe_dev_set_link_up, 5277 .dev_set_link_down = txgbe_dev_set_link_down, 5278 .dev_close = txgbe_dev_close, 5279 .dev_reset = txgbe_dev_reset, 5280 .promiscuous_enable = txgbe_dev_promiscuous_enable, 5281 .promiscuous_disable = txgbe_dev_promiscuous_disable, 5282 .allmulticast_enable = txgbe_dev_allmulticast_enable, 5283 .allmulticast_disable = txgbe_dev_allmulticast_disable, 5284 .link_update = txgbe_dev_link_update, 5285 .stats_get = txgbe_dev_stats_get, 5286 .xstats_get = txgbe_dev_xstats_get, 5287 .xstats_get_by_id = txgbe_dev_xstats_get_by_id, 5288 .stats_reset = txgbe_dev_stats_reset, 5289 .xstats_reset = txgbe_dev_xstats_reset, 5290 .xstats_get_names = txgbe_dev_xstats_get_names, 5291 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id, 5292 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set, 5293 .fw_version_get = txgbe_fw_version_get, 5294 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get, 5295 .mtu_set = txgbe_dev_mtu_set, 5296 .vlan_filter_set = txgbe_vlan_filter_set, 5297 .vlan_tpid_set = txgbe_vlan_tpid_set, 5298 .vlan_offload_set = txgbe_vlan_offload_set, 5299 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set, 5300 .rx_queue_start = txgbe_dev_rx_queue_start, 5301 .rx_queue_stop = txgbe_dev_rx_queue_stop, 5302 .tx_queue_start = txgbe_dev_tx_queue_start, 5303 .tx_queue_stop = txgbe_dev_tx_queue_stop, 5304 .rx_queue_setup = txgbe_dev_rx_queue_setup, 5305 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable, 5306 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable, 5307 .rx_queue_release = txgbe_dev_rx_queue_release, 5308 .tx_queue_setup = txgbe_dev_tx_queue_setup, 5309 .tx_queue_release = txgbe_dev_tx_queue_release, 5310 .dev_led_on = txgbe_dev_led_on, 5311 .dev_led_off = txgbe_dev_led_off, 5312 .flow_ctrl_get = txgbe_flow_ctrl_get, 5313 .flow_ctrl_set = txgbe_flow_ctrl_set, 5314 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set, 5315 .mac_addr_add = txgbe_add_rar, 5316 .mac_addr_remove = txgbe_remove_rar, 5317 .mac_addr_set = txgbe_set_default_mac_addr, 5318 .uc_hash_table_set = txgbe_uc_hash_table_set, 5319 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set, 5320 .set_queue_rate_limit = txgbe_set_queue_rate_limit, 5321 .reta_update = txgbe_dev_rss_reta_update, 5322 .reta_query = txgbe_dev_rss_reta_query, 5323 .rss_hash_update = txgbe_dev_rss_hash_update, 5324 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get, 5325 .flow_ops_get = txgbe_dev_flow_ops_get, 5326 .set_mc_addr_list = txgbe_dev_set_mc_addr_list, 5327 .rxq_info_get = txgbe_rxq_info_get, 5328 .txq_info_get = txgbe_txq_info_get, 5329 .timesync_enable = txgbe_timesync_enable, 5330 .timesync_disable = txgbe_timesync_disable, 5331 .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp, 5332 .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp, 5333 .get_reg = txgbe_get_regs, 5334 .get_eeprom_length = txgbe_get_eeprom_length, 5335 .get_eeprom = txgbe_get_eeprom, 5336 .set_eeprom = txgbe_set_eeprom, 5337 .get_module_info = txgbe_get_module_info, 5338 .get_module_eeprom = txgbe_get_module_eeprom, 5339 .get_dcb_info = txgbe_dev_get_dcb_info, 5340 .timesync_adjust_time = txgbe_timesync_adjust_time, 5341 .timesync_read_time = txgbe_timesync_read_time, 5342 .timesync_write_time = txgbe_timesync_write_time, 5343 .udp_tunnel_port_add = txgbe_dev_udp_tunnel_port_add, 5344 .udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del, 5345 .tm_ops_get = txgbe_tm_ops_get, 5346 .tx_done_cleanup = txgbe_dev_tx_done_cleanup, 5347 }; 5348 5349 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd); 5350 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map); 5351 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 5352 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe, 5353 TXGBE_DEVARG_BP_AUTO "=<0|1>" 5354 TXGBE_DEVARG_KR_POLL "=<0|1>" 5355 TXGBE_DEVARG_KR_PRESENT "=<0|1>" 5356 TXGBE_DEVARG_KX_SGMII "=<0|1>" 5357 TXGBE_DEVARG_FFE_SET "=<0-4>" 5358 TXGBE_DEVARG_FFE_MAIN "=<uint16>" 5359 TXGBE_DEVARG_FFE_PRE "=<uint16>" 5360 TXGBE_DEVARG_FFE_POST "=<uint16>"); 5361 5362 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE); 5363 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE); 5364 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_bp, bp, NOTICE); 5365 5366 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX 5367 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_rx, rx, DEBUG); 5368 #endif 5369 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX 5370 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx, tx, DEBUG); 5371 #endif 5372 5373 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE 5374 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx_free, tx_free, DEBUG); 5375 #endif 5376