1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #ifndef _TXGBE_REGS_H_ 7 #define _TXGBE_REGS_H_ 8 9 #define TXGBE_PVMBX_QSIZE (16) /* 16*4B */ 10 #define TXGBE_PVMBX_BSIZE (TXGBE_PVMBX_QSIZE * 4) 11 12 #define TXGBE_REMOVED(a) (0) 13 14 #define TXGBE_REG_DUMMY 0xFFFFFF 15 16 #define MS8(shift, mask) (((u8)(mask)) << (shift)) 17 #define LS8(val, shift, mask) (((u8)(val) & (u8)(mask)) << (shift)) 18 #define RS8(reg, shift, mask) (((u8)(reg) >> (shift)) & (u8)(mask)) 19 20 #define MS16(shift, mask) (((u16)(mask)) << (shift)) 21 #define LS16(val, shift, mask) (((u16)(val) & (u16)(mask)) << (shift)) 22 #define RS16(reg, shift, mask) (((u16)(reg) >> (shift)) & (u16)(mask)) 23 24 #define MS32(shift, mask) (((u32)(mask)) << (shift)) 25 #define LS32(val, shift, mask) (((u32)(val) & (u32)(mask)) << (shift)) 26 #define RS32(reg, shift, mask) (((u32)(reg) >> (shift)) & (u32)(mask)) 27 28 #define MS64(shift, mask) (((u64)(mask)) << (shift)) 29 #define LS64(val, shift, mask) (((u64)(val) & (u64)(mask)) << (shift)) 30 #define RS64(reg, shift, mask) (((u64)(reg) >> (shift)) & (u64)(mask)) 31 32 #define MS(shift, mask) MS32(shift, mask) 33 #define LS(val, shift, mask) LS32(val, shift, mask) 34 #define RS(reg, shift, mask) RS32(reg, shift, mask) 35 36 #define ROUND_UP(x, y) (((x) + (y) - 1) / (y) * (y)) 37 #define ROUND_DOWN(x, y) ((x) / (y) * (y)) 38 #define ROUND_OVER(x, maxbits, unitbits) \ 39 ((x) >= 1 << (maxbits) ? 0 : (x) >> (unitbits)) 40 41 /* autoc bits definition */ 42 #define TXGBE_AUTOC TXGBE_REG_DUMMY 43 #define TXGBE_AUTOC_FLU MS64(0, 0x1) 44 #define TXGBE_AUTOC_10G_PMA_PMD_MASK MS64(7, 0x3) /* parallel */ 45 #define TXGBE_AUTOC_10G_XAUI LS64(0, 7, 0x3) 46 #define TXGBE_AUTOC_10G_KX4 LS64(1, 7, 0x3) 47 #define TXGBE_AUTOC_10G_CX4 LS64(2, 7, 0x3) 48 #define TXGBE_AUTOC_10G_KR LS64(3, 7, 0x3) /* fixme */ 49 #define TXGBE_AUTOC_1G_PMA_PMD_MASK MS64(9, 0x7) 50 #define TXGBE_AUTOC_1G_BX LS64(0, 9, 0x7) 51 #define TXGBE_AUTOC_1G_KX LS64(1, 9, 0x7) 52 #define TXGBE_AUTOC_1G_SFI LS64(0, 9, 0x7) 53 #define TXGBE_AUTOC_1G_KX_BX LS64(1, 9, 0x7) 54 #define TXGBE_AUTOC_AN_RESTART MS64(12, 0x1) 55 #define TXGBE_AUTOC_LMS_MASK MS64(13, 0x7) 56 #define TXGBE_AUTOC_LMS_10G LS64(3, 13, 0x7) 57 #define TXGBE_AUTOC_LMS_KX4_KX_KR LS64(4, 13, 0x7) 58 #define TXGBE_AUTOC_LMS_SGMII_1G_100M LS64(5, 13, 0x7) 59 #define TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN LS64(6, 13, 0x7) 60 #define TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII LS64(7, 13, 0x7) 61 #define TXGBE_AUTOC_LMS_1G_LINK_NO_AN LS64(0, 13, 0x7) 62 #define TXGBE_AUTOC_LMS_10G_LINK_NO_AN LS64(1, 13, 0x7) 63 #define TXGBE_AUTOC_LMS_1G_AN LS64(2, 13, 0x7) 64 #define TXGBE_AUTOC_LMS_KX4_AN LS64(4, 13, 0x7) 65 #define TXGBE_AUTOC_LMS_KX4_AN_1G_AN LS64(6, 13, 0x7) 66 #define TXGBE_AUTOC_LMS_ATTACH_TYPE LS64(7, 13, 0x7) 67 #define TXGBE_AUTOC_LMS_AN MS64(15, 0x7) 68 69 #define TXGBE_AUTOC_KR_SUPP MS64(16, 0x1) 70 #define TXGBE_AUTOC_FECR MS64(17, 0x1) 71 #define TXGBE_AUTOC_FECA MS64(18, 0x1) 72 #define TXGBE_AUTOC_AN_RX_ALIGN MS64(18, 0x1F) /* fixme */ 73 #define TXGBE_AUTOC_AN_RX_DRIFT MS64(23, 0x3) 74 #define TXGBE_AUTOC_AN_RX_LOOSE MS64(24, 0x3) 75 #define TXGBE_AUTOC_PD_TMR MS64(25, 0x3) 76 #define TXGBE_AUTOC_RF MS64(27, 0x1) 77 #define TXGBE_AUTOC_ASM_PAUSE MS64(29, 0x1) 78 #define TXGBE_AUTOC_SYM_PAUSE MS64(28, 0x1) 79 #define TXGBE_AUTOC_PAUSE MS64(28, 0x3) 80 #define TXGBE_AUTOC_KX_SUPP MS64(30, 0x1) 81 #define TXGBE_AUTOC_KX4_SUPP MS64(31, 0x1) 82 83 #define TXGBE_AUTOC_10GS_PMA_PMD_MASK MS64(48, 0x3) /* serial */ 84 #define TXGBE_AUTOC_10GS_KR LS64(0, 48, 0x3) 85 #define TXGBE_AUTOC_10GS_XFI LS64(1, 48, 0x3) 86 #define TXGBE_AUTOC_10GS_SFI LS64(2, 48, 0x3) 87 #define TXGBE_AUTOC_LINK_DIA_MASK MS64(60, 0x7) 88 #define TXGBE_AUTOC_LINK_DIA_D3_MASK LS64(5, 60, 0x7) 89 90 #define TXGBE_AUTOC_SPEED_MASK MS64(32, 0xFFFF) 91 #define TXGBD_AUTOC_SPEED(r) RS64(r, 32, 0xFFFF) 92 #define TXGBE_AUTOC_SPEED(v) LS64(v, 32, 0xFFFF) 93 #define TXGBE_LINK_SPEED_UNKNOWN 0 94 #define TXGBE_LINK_SPEED_10M_FULL 0x0002 95 #define TXGBE_LINK_SPEED_100M_FULL 0x0008 96 #define TXGBE_LINK_SPEED_1GB_FULL 0x0020 97 #define TXGBE_LINK_SPEED_2_5GB_FULL 0x0400 98 #define TXGBE_LINK_SPEED_5GB_FULL 0x0800 99 #define TXGBE_LINK_SPEED_10GB_FULL 0x0080 100 #define TXGBE_LINK_SPEED_40GB_FULL 0x0100 101 #define TXGBE_AUTOC_AUTONEG MS64(63, 0x1) 102 103 104 105 /* Hardware Datapath: 106 * RX: / Queue <- Filter \ 107 * Host | TC <=> SEC <=> MAC <=> PHY 108 * TX: \ Queue -> Filter / 109 * 110 * Packet Filter: 111 * RX: RSS < FDIR < Filter < Encrypt 112 * 113 * Macro Argument Naming: 114 * rp = ring pair [0,127] 115 * tc = traffic class [0,7] 116 * up = user priority [0,7] 117 * pi = pool index [0,63] 118 * r = register 119 * v = value 120 * s = shift 121 * m = mask 122 * i,j,k = array index 123 * H,L = high/low bits 124 * HI,LO = high/low state 125 */ 126 127 #define TXGBE_ETHPHYIF TXGBE_REG_DUMMY 128 #define TXGBE_ETHPHYIF_MDIO_ACT MS(1, 0x1) 129 #define TXGBE_ETHPHYIF_MDIO_MODE MS(2, 0x1) 130 #define TXGBE_ETHPHYIF_MDIO_BASE(r) RS(r, 3, 0x1F) 131 #define TXGBE_ETHPHYIF_MDIO_SHARED MS(13, 0x1) 132 #define TXGBE_ETHPHYIF_SPEED_10M MS(17, 0x1) 133 #define TXGBE_ETHPHYIF_SPEED_100M MS(18, 0x1) 134 #define TXGBE_ETHPHYIF_SPEED_1G MS(19, 0x1) 135 #define TXGBE_ETHPHYIF_SPEED_2_5G MS(20, 0x1) 136 #define TXGBE_ETHPHYIF_SPEED_10G MS(21, 0x1) 137 #define TXGBE_ETHPHYIF_SGMII_ENABLE MS(25, 0x1) 138 #define TXGBE_ETHPHYIF_INT_PHY_MODE MS(24, 0x1) 139 #define TXGBE_ETHPHYIF_IO_XPCS MS(30, 0x1) 140 #define TXGBE_ETHPHYIF_IO_EPHY MS(31, 0x1) 141 142 /****************************************************************************** 143 * Chip Registers 144 ******************************************************************************/ 145 /** 146 * Chip Status 147 **/ 148 #define TXGBE_PWR 0x010000 149 #define TXGBE_PWR_LAN(r) RS(r, 30, 0x3) 150 #define TXGBE_PWR_LAN_0 (1) 151 #define TXGBE_PWR_LAN_1 (2) 152 #define TXGBE_PWR_LAN_A (3) 153 #define TXGBE_CTL 0x010004 154 #define TXGBE_LOCKPF 0x010008 155 #define TXGBE_RST 0x01000C 156 #define TXGBE_RST_SW MS(0, 0x1) 157 #define TXGBE_RST_LAN(i) MS(((i) + 1), 0x1) 158 #define TXGBE_RST_FW MS(3, 0x1) 159 #define TXGBE_RST_ETH(i) MS(((i) + 29), 0x1) 160 #define TXGBE_RST_GLB MS(31, 0x1) 161 #define TXGBE_RST_DEFAULT (TXGBE_RST_SW | \ 162 TXGBE_RST_LAN(0) | \ 163 TXGBE_RST_LAN(1)) 164 165 #define TXGBE_STAT 0x010028 166 #define TXGBE_STAT_MNGINIT MS(0, 0x1) 167 #define TXGBE_STAT_MNGVETO MS(8, 0x1) 168 #define TXGBE_STAT_ECCLAN0 MS(16, 0x1) 169 #define TXGBE_STAT_ECCLAN1 MS(17, 0x1) 170 #define TXGBE_STAT_ECCMNG MS(18, 0x1) 171 #define TXGBE_STAT_ECCPCIE MS(19, 0x1) 172 #define TXGBE_STAT_ECCPCIW MS(20, 0x1) 173 #define TXGBE_RSTSTAT 0x010030 174 #define TXGBE_RSTSTAT_PROG MS(20, 0x1) 175 #define TXGBE_RSTSTAT_PREP MS(19, 0x1) 176 #define TXGBE_RSTSTAT_TYPE_MASK MS(16, 0x7) 177 #define TXGBE_RSTSTAT_TYPE(r) RS(r, 16, 0x7) 178 #define TXGBE_RSTSTAT_TYPE_PE LS(0, 16, 0x7) 179 #define TXGBE_RSTSTAT_TYPE_PWR LS(1, 16, 0x7) 180 #define TXGBE_RSTSTAT_TYPE_HOT LS(2, 16, 0x7) 181 #define TXGBE_RSTSTAT_TYPE_SW LS(3, 16, 0x7) 182 #define TXGBE_RSTSTAT_TYPE_FW LS(4, 16, 0x7) 183 #define TXGBE_RSTSTAT_TMRINIT_MASK MS(8, 0xFF) 184 #define TXGBE_RSTSTAT_TMRINIT(v) LS(v, 8, 0xFF) 185 #define TXGBE_RSTSTAT_TMRCNT_MASK MS(0, 0xFF) 186 #define TXGBE_RSTSTAT_TMRCNT(v) LS(v, 0, 0xFF) 187 #define TXGBE_PWRTMR 0x010034 188 189 /** 190 * SPI(Flash) 191 **/ 192 #define TXGBE_SPICMD 0x010104 193 #define TXGBE_SPICMD_ADDR(v) LS(v, 0, 0xFFFFFF) 194 #define TXGBE_SPICMD_CLK(v) LS(v, 25, 0x7) 195 #define TXGBE_SPICMD_CMD(v) LS(v, 28, 0x7) 196 #define TXGBE_SPIDAT 0x010108 197 #define TXGBE_SPIDAT_BYPASS MS(31, 0x1) 198 #define TXGBE_SPIDAT_STATUS(v) LS(v, 16, 0xFF) 199 #define TXGBE_SPIDAT_OPDONE MS(0, 0x1) 200 #define TXGBE_SPISTATUS 0x01010C 201 #define TXGBE_SPISTATUS_OPDONE MS(0, 0x1) 202 #define TXGBE_SPISTATUS_BYPASS MS(31, 0x1) 203 #define TXGBE_SPIUSRCMD 0x010110 204 #define TXGBE_SPICFG0 0x010114 205 #define TXGBE_SPICFG1 0x010118 206 #define TXGBE_FLASH 0x010120 207 #define TXGBE_FLASH_PERSTD MS(0, 0x1) 208 #define TXGBE_FLASH_PWRRSTD MS(1, 0x1) 209 #define TXGBE_FLASH_SWRSTD MS(7, 0x1) 210 #define TXGBE_FLASH_LANRSTD(i) MS(((i) + 9), 0x1) 211 #define TXGBE_SRAM 0x010124 212 #define TXGBE_SRAM_SZ(v) LS(v, 28, 0x7) 213 #define TXGBE_SRAMCTLECC 0x010130 214 #define TXGBE_SRAMINJECC 0x010134 215 #define TXGBE_SRAMECC 0x010138 216 217 /** 218 * Thermel Sensor 219 **/ 220 #define TXGBE_TSCTL 0x010300 221 #define TXGBE_TSCTL_MODE MS(31, 0x1) 222 #define TXGBE_TSREVAL 0x010304 223 #define TXGBE_TSREVAL_EA MS(0, 0x1) 224 #define TXGBE_TSDAT 0x010308 225 #define TXGBE_TSDAT_TMP(r) ((r) & 0x3FF) 226 #define TXGBE_TSDAT_VLD MS(16, 0x1) 227 #define TXGBE_TSALMWTRHI 0x01030C 228 #define TXGBE_TSALMWTRHI_VAL(v) (((v) & 0x3FF)) 229 #define TXGBE_TSALMWTRLO 0x010310 230 #define TXGBE_TSALMWTRLO_VAL(v) (((v) & 0x3FF)) 231 #define TXGBE_TSINTWTR 0x010314 232 #define TXGBE_TSINTWTR_HI MS(0, 0x1) 233 #define TXGBE_TSINTWTR_LO MS(1, 0x1) 234 #define TXGBE_TSALM 0x010318 235 #define TXGBE_TSALM_LO MS(0, 0x1) 236 #define TXGBE_TSALM_HI MS(1, 0x1) 237 238 /** 239 * Management 240 **/ 241 #define TXGBE_MNGTC 0x01CD10 242 #define TXGBE_MNGFWSYNC 0x01E000 243 #define TXGBE_MNGFWSYNC_REQ MS(0, 0x1) 244 #define TXGBE_MNGSWSYNC 0x01E004 245 #define TXGBE_MNGSWSYNC_REQ MS(0, 0x1) 246 #define TXGBE_SWSEM 0x01002C 247 #define TXGBE_SWSEM_PF MS(0, 0x1) 248 #define TXGBE_MNGSEM 0x01E008 249 #define TXGBE_MNGSEM_SW(v) LS(v, 0, 0xFFFF) 250 #define TXGBE_MNGSEM_SWPHY MS(0, 0x1) 251 #define TXGBE_MNGSEM_SWMBX MS(2, 0x1) 252 #define TXGBE_MNGSEM_SWFLASH MS(3, 0x1) 253 #define TXGBE_MNGSEM_FW(v) LS(v, 16, 0xFFFF) 254 #define TXGBE_MNGSEM_FWPHY MS(16, 0x1) 255 #define TXGBE_MNGSEM_FWMBX MS(18, 0x1) 256 #define TXGBE_MNGSEM_FWFLASH MS(19, 0x1) 257 #define TXGBE_MNGMBXCTL 0x01E044 258 #define TXGBE_MNGMBXCTL_SWRDY MS(0, 0x1) 259 #define TXGBE_MNGMBXCTL_SWACK MS(1, 0x1) 260 #define TXGBE_MNGMBXCTL_FWRDY MS(2, 0x1) 261 #define TXGBE_MNGMBXCTL_FWACK MS(3, 0x1) 262 #define TXGBE_MNGMBX 0x01E100 263 264 /****************************************************************************** 265 * Port Registers 266 ******************************************************************************/ 267 /* Port Control */ 268 #define TXGBE_PORTCTL 0x014400 269 #define TXGBE_PORTCTL_VLANEXT MS(0, 0x1) 270 #define TXGBE_PORTCTL_ETAG MS(1, 0x1) 271 #define TXGBE_PORTCTL_QINQ MS(2, 0x1) 272 #define TXGBE_PORTCTL_DRVLOAD MS(3, 0x1) 273 #define TXGBE_PORTCTL_UPLNK MS(4, 0x1) 274 #define TXGBE_PORTCTL_DCB MS(10, 0x1) 275 #define TXGBE_PORTCTL_NUMTC_MASK MS(11, 0x1) 276 #define TXGBE_PORTCTL_NUMTC_4 LS(0, 11, 0x1) 277 #define TXGBE_PORTCTL_NUMTC_8 LS(1, 11, 0x1) 278 #define TXGBE_PORTCTL_NUMVT_MASK MS(12, 0x3) 279 #define TXGBE_PORTCTL_NUMVT_16 LS(1, 12, 0x3) 280 #define TXGBE_PORTCTL_NUMVT_32 LS(2, 12, 0x3) 281 #define TXGBE_PORTCTL_NUMVT_64 LS(3, 12, 0x3) 282 #define TXGBE_PORTCTL_RSTDONE MS(14, 0x1) 283 #define TXGBE_PORTCTL_TEREDODIA MS(27, 0x1) 284 #define TXGBE_PORTCTL_GENEVEDIA MS(28, 0x1) 285 #define TXGBE_PORTCTL_VXLANGPEDIA MS(30, 0x1) 286 #define TXGBE_PORTCTL_VXLANDIA MS(31, 0x1) 287 288 #define TXGBE_PORT 0x014404 289 #define TXGBE_PORT_LINKUP MS(0, 0x1) 290 #define TXGBE_PORT_LINK10G MS(1, 0x1) 291 #define TXGBE_PORT_LINK1000M MS(2, 0x1) 292 #define TXGBE_PORT_LINK100M MS(3, 0x1) 293 #define TXGBE_PORT_LANID(r) RS(r, 8, 0x1) 294 #define TXGBE_EXTAG 0x014408 295 #define TXGBE_EXTAG_ETAG_MASK MS(0, 0xFFFF) 296 #define TXGBE_EXTAG_ETAG(v) LS(v, 0, 0xFFFF) 297 #define TXGBE_EXTAG_VLAN_MASK MS(16, 0xFFFF) 298 #define TXGBE_EXTAG_VLAN(v) LS(v, 16, 0xFFFF) 299 #define TXGBE_VXLANPORT 0x014410 300 #define TXGBE_VXLANPORTGPE 0x014414 301 #define TXGBE_GENEVEPORT 0x014418 302 #define TXGBE_TEREDOPORT 0x01441C 303 #define TXGBE_LEDCTL 0x014424 304 #define TXGBE_LEDCTL_SEL_MASK MS(0, 0xFFFF) 305 #define TXGBE_LEDCTL_SEL(s) MS((s), 0x1) 306 #define TXGBE_LEDCTL_ORD_MASK MS(16, 0xFFFF) 307 #define TXGBE_LEDCTL_ORD(s) MS(((s)+16), 0x1) 308 /* s=UP(0),10G(1),1G(2),100M(3),BSY(4) */ 309 #define TXGBE_LEDCTL_ACTIVE (TXGBE_LEDCTL_SEL(4) | TXGBE_LEDCTL_ORD(4)) 310 #define TXGBE_TAGTPID(i) (0x014430 + (i) * 4) /* 0-3 */ 311 #define TXGBE_TAGTPID_LSB_MASK MS(0, 0xFFFF) 312 #define TXGBE_TAGTPID_LSB(v) LS(v, 0, 0xFFFF) 313 #define TXGBE_TAGTPID_MSB_MASK MS(16, 0xFFFF) 314 #define TXGBE_TAGTPID_MSB(v) LS(v, 16, 0xFFFF) 315 316 /** 317 * GPIO Control 318 * P0: link speed change 319 * P1: 320 * P2: 321 * P3: optical laser disable 322 * P4: 323 * P5: link speed selection 324 * P6: 325 * P7: external phy event 326 **/ 327 #define TXGBE_SDP 0x014800 328 #define TXGBE_SDP_0 MS(0, 0x1) 329 #define TXGBE_SDP_1 MS(1, 0x1) 330 #define TXGBE_SDP_2 MS(2, 0x1) 331 #define TXGBE_SDP_3 MS(3, 0x1) 332 #define TXGBE_SDP_4 MS(4, 0x1) 333 #define TXGBE_SDP_5 MS(5, 0x1) 334 #define TXGBE_SDP_6 MS(6, 0x1) 335 #define TXGBE_SDP_7 MS(7, 0x1) 336 #define TXGBE_SDPDIR 0x014804 337 #define TXGBE_SDPCTL 0x014808 338 #define TXGBE_SDPINTEA 0x014830 339 #define TXGBE_SDPINTMSK 0x014834 340 #define TXGBE_SDPINTTYP 0x014838 341 #define TXGBE_SDPINTPOL 0x01483C 342 #define TXGBE_SDPINT 0x014840 343 #define TXGBE_SDPINTDB 0x014848 344 #define TXGBE_SDPINTEND 0x01484C 345 #define TXGBE_SDPDAT 0x014850 346 #define TXGBE_SDPLVLSYN 0x014854 347 348 /** 349 * MDIO(PHY) 350 **/ 351 #define TXGBE_MDIOSCA 0x011200 352 #define TXGBE_MDIOSCA_REG(v) LS(v, 0, 0xFFFF) 353 #define TXGBE_MDIOSCA_PORT(v) LS(v, 16, 0x1F) 354 #define TXGBE_MDIOSCA_DEV(v) LS(v, 21, 0x1F) 355 #define TXGBE_MDIOSCD 0x011204 356 #define TXGBD_MDIOSCD_DAT(r) RS(r, 0, 0xFFFF) 357 #define TXGBE_MDIOSCD_DAT(v) LS(v, 0, 0xFFFF) 358 #define TXGBE_MDIOSCD_CMD_PREAD LS(1, 16, 0x3) 359 #define TXGBE_MDIOSCD_CMD_WRITE LS(2, 16, 0x3) 360 #define TXGBE_MDIOSCD_CMD_READ LS(3, 16, 0x3) 361 #define TXGBE_MDIOSCD_SADDR MS(18, 0x1) 362 #define TXGBE_MDIOSCD_CLOCK(v) LS(v, 19, 0x7) 363 #define TXGBE_MDIOSCD_BUSY MS(22, 0x1) 364 365 /** 366 * I2C (SFP) 367 **/ 368 #define TXGBE_I2CCTL 0x014900 369 #define TXGBE_I2CCTL_MAEA MS(0, 0x1) 370 #define TXGBE_I2CCTL_SPEED(v) LS(v, 1, 0x3) 371 #define TXGBE_I2CCTL_RESTART MS(5, 0x1) 372 #define TXGBE_I2CCTL_SLDA MS(6, 0x1) 373 #define TXGBE_I2CTGT 0x014904 374 #define TXGBE_I2CTGT_ADDR(v) LS(v, 0, 0x3FF) 375 #define TXGBE_I2CCMD 0x014910 376 #define TXGBE_I2CCMD_READ (MS(9, 0x1) | 0x100) 377 #define TXGBE_I2CCMD_WRITE (MS(9, 0x1)) 378 #define TXGBE_I2CSCLHITM 0x014914 379 #define TXGBE_I2CSCLLOTM 0x014918 380 #define TXGBE_I2CINT 0x014934 381 #define TXGBE_I2CINT_RXFULL MS(2, 0x1) 382 #define TXGBE_I2CINT_TXEMPTY MS(4, 0x1) 383 #define TXGBE_I2CINTMSK 0x014930 384 #define TXGBE_I2CRXFIFO 0x014938 385 #define TXGBE_I2CTXFIFO 0x01493C 386 #define TXGBE_I2CEA 0x01496C 387 #define TXGBE_I2CST 0x014970 388 #define TXGBE_I2CST_ACT MS(5, 0x1) 389 #define TXGBE_I2CSCLTM 0x0149AC 390 #define TXGBE_I2CSDATM 0x0149B0 391 392 /** 393 * TPH 394 **/ 395 #define TXGBE_TPHCFG 0x014F00 396 397 /****************************************************************************** 398 * Pool Registers 399 ******************************************************************************/ 400 #define TXGBE_POOLETHCTL(pl) (0x015600 + (pl) * 4) 401 #define TXGBE_POOLETHCTL_LBDIA MS(0, 0x1) 402 #define TXGBE_POOLETHCTL_LLBDIA MS(1, 0x1) 403 #define TXGBE_POOLETHCTL_LLB MS(2, 0x1) 404 #define TXGBE_POOLETHCTL_UCP MS(4, 0x1) 405 #define TXGBE_POOLETHCTL_ETP MS(5, 0x1) 406 #define TXGBE_POOLETHCTL_VLA MS(6, 0x1) 407 #define TXGBE_POOLETHCTL_VLP MS(7, 0x1) 408 #define TXGBE_POOLETHCTL_UTA MS(8, 0x1) 409 #define TXGBE_POOLETHCTL_MCHA MS(9, 0x1) 410 #define TXGBE_POOLETHCTL_UCHA MS(10, 0x1) 411 #define TXGBE_POOLETHCTL_BCA MS(11, 0x1) 412 #define TXGBE_POOLETHCTL_MCP MS(12, 0x1) 413 414 /* DMA Control */ 415 #define TXGBE_POOLRXENA(i) (0x012004 + (i) * 4) /* 0-1 */ 416 #define TXGBE_POOLRXDNA(i) (0x012060 + (i) * 4) /* 0-1 */ 417 #define TXGBE_POOLTXENA(i) (0x018004 + (i) * 4) /* 0-1 */ 418 #define TXGBE_POOLTXDSA(i) (0x0180A0 + (i) * 4) /* 0-1 */ 419 #define TXGBE_POOLTXLBET(i) (0x018050 + (i) * 4) /* 0-1 */ 420 #define TXGBE_POOLTXASET(i) (0x018058 + (i) * 4) /* 0-1 */ 421 #define TXGBE_POOLTXASMAC(i) (0x018060 + (i) * 4) /* 0-1 */ 422 #define TXGBE_POOLTXASVLAN(i) (0x018070 + (i) * 4) /* 0-1 */ 423 #define TXGBE_POOLDROPSWBK(i) (0x0151C8 + (i) * 4) /* 0-1 */ 424 425 #define TXGBE_POOLTAG(pl) (0x018100 + (pl) * 4) 426 #define TXGBE_POOLTAG_VTAG(v) LS(v, 0, 0xFFFF) 427 #define TXGBE_POOLTAG_VTAG_MASK MS(0, 0xFFFF) 428 #define TXGBD_POOLTAG_VTAG_UP(r) RS(r, 13, 0x7) 429 #define TXGBE_POOLTAG_TPIDSEL(v) LS(v, 24, 0x7) 430 #define TXGBE_POOLTAG_ETAG_MASK MS(27, 0x3) 431 #define TXGBE_POOLTAG_ETAG LS(2, 27, 0x3) 432 #define TXGBE_POOLTAG_ACT_MASK MS(30, 0x3) 433 #define TXGBE_POOLTAG_ACT_ALWAYS LS(1, 30, 0x3) 434 #define TXGBE_POOLTAG_ACT_NEVER LS(2, 30, 0x3) 435 #define TXGBE_POOLTXARB 0x018204 436 #define TXGBE_POOLTXARB_WRR MS(1, 0x1) 437 #define TXGBE_POOLETAG(pl) (0x018700 + (pl) * 4) 438 439 /* RSS Hash */ 440 #define TXGBE_POOLRSS(pl) (0x019300 + (pl) * 4) 441 #define TXGBE_POOLRSS_L4HDR MS(1, 0x1) 442 #define TXGBE_POOLRSS_L3HDR MS(2, 0x1) 443 #define TXGBE_POOLRSS_L2HDR MS(3, 0x1) 444 #define TXGBE_POOLRSS_L2TUN MS(4, 0x1) 445 #define TXGBE_POOLRSS_TUNHDR MS(5, 0x1) 446 #define TXGBE_POOLRSSKEY(pl, i) (0x01A000 + (pl) * 0x40 + (i) * 4) 447 #define TXGBE_POOLRSSMAP(pl, i) (0x01B000 + (pl) * 0x40 + (i) * 4) 448 449 /****************************************************************************** 450 * Packet Buffer 451 ******************************************************************************/ 452 /* Flow Control */ 453 #define TXGBE_FCXOFFTM(i) (0x019200 + (i) * 4) /* 0-3 */ 454 #define TXGBE_FCWTRLO(tc) (0x019220 + (tc) * 4) 455 #define TXGBE_FCWTRLO_TH(v) LS(v, 10, 0x1FF) /* KB */ 456 #define TXGBE_FCWTRLO_XON MS(31, 0x1) 457 #define TXGBE_FCWTRHI(tc) (0x019260 + (tc) * 4) 458 #define TXGBE_FCWTRHI_TH(v) LS(v, 10, 0x1FF) /* KB */ 459 #define TXGBE_FCWTRHI_XOFF MS(31, 0x1) 460 #define TXGBE_RXFCRFSH 0x0192A0 461 #define TXGBE_RXFCFSH_TIME(v) LS(v, 0, 0xFFFF) 462 #define TXGBE_FCSTAT 0x01CE00 463 #define TXGBE_FCSTAT_DLNK(tc) MS((tc), 0x1) 464 #define TXGBE_FCSTAT_ULNK(tc) MS((tc) + 8, 0x1) 465 466 #define TXGBE_RXFCCFG 0x011090 467 #define TXGBE_RXFCCFG_FC MS(0, 0x1) 468 #define TXGBE_RXFCCFG_PFC MS(8, 0x1) 469 #define TXGBE_TXFCCFG 0x0192A4 470 #define TXGBE_TXFCCFG_FC MS(3, 0x1) 471 #define TXGBE_TXFCCFG_PFC MS(4, 0x1) 472 473 /* Data Buffer */ 474 #define TXGBE_PBRXCTL 0x019000 475 #define TXGBE_PBRXCTL_ST MS(0, 0x1) 476 #define TXGBE_PBRXCTL_ENA MS(31, 0x1) 477 #define TXGBE_PBRXUP2TC 0x019008 478 #define TXGBE_PBTXUP2TC 0x01C800 479 #define TXGBE_DCBUP2TC_MAP(tc, v) LS(v, 3 * (tc), 0x7) 480 #define TXGBE_DCBUP2TC_DEC(tc, r) RS(r, 3 * (tc), 0x7) 481 #define TXGBE_PBRXSIZE(tc) (0x019020 + (tc) * 4) 482 #define TXGBE_PBRXSIZE_KB(v) LS(v, 10, 0x3FF) 483 484 #define TXGBE_PBRXOFTMR 0x019094 485 #define TXGBE_PBRXDBGCMD 0x019090 486 #define TXGBE_PBRXDBGDAT(tc) (0x0190A0 + (tc) * 4) 487 #define TXGBE_PBTXDMATH(tc) (0x018020 + (tc) * 4) 488 #define TXGBE_PBTXSIZE(tc) (0x01CC00 + (tc) * 4) 489 490 /* LLI */ 491 #define TXGBE_PBRXLLI 0x19080 492 #define TXGBE_PBRXLLI_SZLT(v) LS(v, 0, 0xFFF) 493 #define TXGBE_PBRXLLI_UPLT(v) LS(v, 16, 0x7) 494 #define TXGBE_PBRXLLI_UPEA MS(19, 0x1) 495 #define TXGBE_PBRXLLI_CNM MS(20, 0x1) 496 497 /* Port Arbiter(QoS) */ 498 #define TXGBE_PARBTXCTL 0x01CD00 499 #define TXGBE_PARBTXCTL_SP MS(5, 0x1) 500 #define TXGBE_PARBTXCTL_DA MS(6, 0x1) 501 #define TXGBE_PARBTXCTL_RECYC MS(8, 0x1) 502 #define TXGBE_PARBTXCFG(tc) (0x01CD20 + (tc) * 4) 503 #define TXGBE_PARBTXCFG_CRQ(v) LS(v, 0, 0x1FF) 504 #define TXGBE_PARBTXCFG_BWG(v) LS(v, 9, 0x7) 505 #define TXGBE_PARBTXCFG_MCL(v) LS(v, 12, 0xFFF) 506 #define TXGBE_PARBTXCFG_GSP MS(30, 0x1) 507 #define TXGBE_PARBTXCFG_LSP MS(31, 0x1) 508 509 /****************************************************************************** 510 * Queue Registers 511 ******************************************************************************/ 512 /* Queue Control */ 513 #define TXGBE_QPRXDROP(i) (0x012080 + (i) * 4) /* 0-3 */ 514 #define TXGBE_QPRXSTRPVLAN(i) (0x012090 + (i) * 4) /* 0-3 */ 515 #define TXGBE_QPTXLLI(i) (0x018040 + (i) * 4) /* 0-3 */ 516 517 /* Queue Arbiter(QoS) */ 518 #define TXGBE_QARBRXCTL 0x012000 519 #define TXGBE_QARBRXCTL_RC MS(1, 0x1) 520 #define TXGBE_QARBRXCTL_WSP MS(2, 0x1) 521 #define TXGBE_QARBRXCTL_DA MS(6, 0x1) 522 #define TXGBE_QARBRXCFG(tc) (0x012040 + (tc) * 4) 523 #define TXGBE_QARBRXCFG_CRQ(v) LS(v, 0, 0x1FF) 524 #define TXGBE_QARBRXCFG_BWG(v) LS(v, 9, 0x7) 525 #define TXGBE_QARBRXCFG_MCL(v) LS(v, 12, 0xFFF) 526 #define TXGBE_QARBRXCFG_GSP MS(30, 0x1) 527 #define TXGBE_QARBRXCFG_LSP MS(31, 0x1) 528 #define TXGBE_QARBRXTC 0x0194F8 529 #define TXGBE_QARBRXTC_RR MS(0, 0x1) 530 531 #define TXGBE_QARBTXCTL 0x018200 532 #define TXGBE_QARBTXCTL_WSP MS(1, 0x1) 533 #define TXGBE_QARBTXCTL_RECYC MS(4, 0x1) 534 #define TXGBE_QARBTXCTL_DA MS(6, 0x1) 535 #define TXGBE_QARBTXCFG(tc) (0x018220 + (tc) * 4) 536 #define TXGBE_QARBTXCFG_CRQ(v) LS(v, 0, 0x1FF) 537 #define TXGBE_QARBTXCFG_BWG(v) LS(v, 9, 0x7) 538 #define TXGBE_QARBTXCFG_MCL(v) LS(v, 12, 0xFFF) 539 #define TXGBE_QARBTXCFG_GSP MS(30, 0x1) 540 #define TXGBE_QARBTXCFG_LSP MS(31, 0x1) 541 #define TXGBE_QARBTXMMW 0x018208 542 #define TXGBE_QARBTXMMW_DEF (4) 543 #define TXGBE_QARBTXMMW_JF (20) 544 #define TXGBE_QARBTXRATEI 0x01820C 545 #define TXGBE_QARBTXRATE 0x018404 546 #define TXGBE_QARBTXRATE_MIN(v) LS(v, 0, 0x3FFF) 547 #define TXGBE_QARBTXRATE_MAX(v) LS(v, 16, 0x3FFF) 548 #define TXGBE_QARBTXCRED(rp) (0x018500 + (rp) * 4) 549 550 /* QCN */ 551 #define TXGBE_QCNADJ 0x018210 552 #define TXGBE_QCNRP 0x018400 553 #define TXGBE_QCNRPRATE 0x018404 554 #define TXGBE_QCNRPADJ 0x018408 555 #define TXGBE_QCNRPRLD 0x01840C 556 557 /* Misc Control */ 558 #define TXGBE_RSECCTL 0x01200C 559 #define TXGBE_RSECCTL_TSRSC MS(0, 0x1) 560 #define TXGBE_DMATXCTRL 0x018000 561 #define TXGBE_DMATXCTRL_ENA MS(0, 0x1) 562 #define TXGBE_DMATXCTRL_TPID_MASK MS(16, 0xFFFF) 563 #define TXGBE_DMATXCTRL_TPID(v) LS(v, 16, 0xFFFF) 564 565 /****************************************************************************** 566 * Packet Filter (L2-7) 567 ******************************************************************************/ 568 /** 569 * Receive Scaling 570 **/ 571 #define TXGBE_RSSTBL(i) (0x019400 + (i) * 4) /* 32 */ 572 #define TXGBE_RSSKEY(i) (0x019480 + (i) * 4) /* 10 */ 573 #define TXGBE_RSSPBHASH 0x0194F0 574 #define TXGBE_RSSPBHASH_BITS(tc, v) LS(v, 3 * (tc), 0x7) 575 #define TXGBE_RACTL 0x0194F4 576 #define TXGBE_RACTL_RSSMKEY MS(0, 0x1) 577 #define TXGBE_RACTL_RSSENA MS(2, 0x1) 578 #define TXGBE_RACTL_RSSMASK MS(16, 0xFFFF) 579 #define TXGBE_RACTL_RSSIPV4TCP MS(16, 0x1) 580 #define TXGBE_RACTL_RSSIPV4 MS(17, 0x1) 581 #define TXGBE_RACTL_RSSIPV6 MS(20, 0x1) 582 #define TXGBE_RACTL_RSSIPV6TCP MS(21, 0x1) 583 #define TXGBE_RACTL_RSSIPV4UDP MS(22, 0x1) 584 #define TXGBE_RACTL_RSSIPV6UDP MS(23, 0x1) 585 586 /** 587 * Flow Director 588 **/ 589 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */ 590 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */ 591 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */ 592 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */ 593 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */ 594 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */ 595 596 #define TXGBE_FDIRCTL 0x019500 597 #define TXGBE_FDIRCTL_BUF_MASK MS(0, 0x3) 598 #define TXGBE_FDIRCTL_BUF_64K LS(1, 0, 0x3) 599 #define TXGBE_FDIRCTL_BUF_128K LS(2, 0, 0x3) 600 #define TXGBE_FDIRCTL_BUF_256K LS(3, 0, 0x3) 601 #define TXGBD_FDIRCTL_BUF_BYTE(r) (1 << (15 + RS(r, 0, 0x3))) 602 #define TXGBE_FDIRCTL_INITDONE MS(3, 0x1) 603 #define TXGBE_FDIRCTL_PERFECT MS(4, 0x1) 604 #define TXGBE_FDIRCTL_REPORT_MASK MS(5, 0x7) 605 #define TXGBE_FDIRCTL_REPORT_MATCH LS(1, 5, 0x7) 606 #define TXGBE_FDIRCTL_REPORT_ALWAYS LS(5, 5, 0x7) 607 #define TXGBE_FDIRCTL_DROPQP_MASK MS(8, 0x7F) 608 #define TXGBE_FDIRCTL_DROPQP(v) LS(v, 8, 0x7F) 609 #define TXGBE_FDIRCTL_HASHBITS_MASK LS(20, 0xF) 610 #define TXGBE_FDIRCTL_HASHBITS(v) LS(v, 20, 0xF) 611 #define TXGBE_FDIRCTL_MAXLEN(v) LS(v, 24, 0xF) 612 #define TXGBE_FDIRCTL_FULLTHR(v) LS(v, 28, 0xF) 613 #define TXGBE_FDIRFLEXCFG(i) (0x019580 + (i) * 4) /* 0-15 */ 614 #define TXGBD_FDIRFLEXCFG_ALL(r, i) RS(0, (i) << 3, 0xFF) 615 #define TXGBE_FDIRFLEXCFG_ALL(v, i) LS(v, (i) << 3, 0xFF) 616 #define TXGBE_FDIRFLEXCFG_BASE_MAC LS(0, 0, 0x3) 617 #define TXGBE_FDIRFLEXCFG_BASE_L2 LS(1, 0, 0x3) 618 #define TXGBE_FDIRFLEXCFG_BASE_L3 LS(2, 0, 0x3) 619 #define TXGBE_FDIRFLEXCFG_BASE_PAY LS(3, 0, 0x3) 620 #define TXGBE_FDIRFLEXCFG_DIA MS(2, 0x1) 621 #define TXGBE_FDIRFLEXCFG_OFST_MASK MS(3, 0x1F) 622 #define TXGBD_FDIRFLEXCFG_OFST(r) RS(r, 3, 0x1F) 623 #define TXGBE_FDIRFLEXCFG_OFST(v) LS(v, 3, 0x1F) 624 #define TXGBE_FDIRBKTHKEY 0x019568 625 #define TXGBE_FDIRSIGHKEY 0x01956C 626 627 /* Common Mask */ 628 #define TXGBE_FDIRDIP4MSK 0x01953C 629 #define TXGBE_FDIRSIP4MSK 0x019540 630 #define TXGBE_FDIRIP6MSK 0x019574 631 #define TXGBE_FDIRIP6MSK_SRC(v) LS(v, 0, 0xFFFF) 632 #define TXGBE_FDIRIP6MSK_DST(v) LS(v, 16, 0xFFFF) 633 #define TXGBE_FDIRTCPMSK 0x019544 634 #define TXGBE_FDIRTCPMSK_SRC(v) LS(v, 0, 0xFFFF) 635 #define TXGBE_FDIRTCPMSK_DST(v) LS(v, 16, 0xFFFF) 636 #define TXGBE_FDIRUDPMSK 0x019548 637 #define TXGBE_FDIRUDPMSK_SRC(v) LS(v, 0, 0xFFFF) 638 #define TXGBE_FDIRUDPMSK_DST(v) LS(v, 16, 0xFFFF) 639 #define TXGBE_FDIRSCTPMSK 0x019560 640 #define TXGBE_FDIRSCTPMSK_SRC(v) LS(v, 0, 0xFFFF) 641 #define TXGBE_FDIRSCTPMSK_DST(v) LS(v, 16, 0xFFFF) 642 #define TXGBE_FDIRMSK 0x019570 643 #define TXGBE_FDIRMSK_POOL MS(2, 0x1) 644 #define TXGBE_FDIRMSK_L4P MS(3, 0x1) 645 #define TXGBE_FDIRMSK_L3P MS(4, 0x1) 646 #define TXGBE_FDIRMSK_TUNTYPE MS(5, 0x1) 647 #define TXGBE_FDIRMSK_TUNIP MS(6, 0x1) 648 #define TXGBE_FDIRMSK_TUNPKT MS(7, 0x1) 649 650 /* Programming Interface */ 651 #define TXGBE_FDIRPIPORT 0x019520 652 #define TXGBE_FDIRPIPORT_SRC(v) LS(v, 0, 0xFFFF) 653 #define TXGBE_FDIRPIPORT_DST(v) LS(v, 16, 0xFFFF) 654 #define TXGBE_FDIRPISIP6(i) (0x01950C + (i) * 4) /* [0,2] */ 655 #define TXGBE_FDIRPISIP4 0x019518 656 #define TXGBE_FDIRPIDIP4 0x01951C 657 #define TXGBE_FDIRPIFLEX 0x019524 658 #define TXGBE_FDIRPIFLEX_PTYPE(v) LS(v, 0, 0xFF) 659 #define TXGBE_FDIRPIFLEX_FLEX(v) LS(v, 16, 0xFFFF) 660 #define TXGBE_FDIRPIHASH 0x019528 661 #define TXGBE_FDIRPIHASH_BKT(v) LS(v, 0, 0x7FFF) 662 #define TXGBE_FDIRPIHASH_VLD MS(15, 0x1) 663 #define TXGBE_FDIRPIHASH_SIG(v) LS(v, 16, 0x7FFF) 664 #define TXGBE_FDIRPIHASH_IDX(v) LS(v, 16, 0xFFFF) 665 #define TXGBE_FDIRPICMD 0x01952C 666 #define TXGBE_FDIRPICMD_OP_MASK MS(0, 0x3) 667 #define TXGBE_FDIRPICMD_OP_ADD LS(1, 0, 0x3) 668 #define TXGBE_FDIRPICMD_OP_REM LS(2, 0, 0x3) 669 #define TXGBE_FDIRPICMD_OP_QRY LS(3, 0, 0x3) 670 #define TXGBE_FDIRPICMD_VLD MS(2, 0x1) 671 #define TXGBE_FDIRPICMD_UPD MS(3, 0x1) 672 #define TXGBE_FDIRPICMD_DIP6 MS(4, 0x1) 673 #define TXGBE_FDIRPICMD_FT(v) LS(v, 5, 0x3) 674 #define TXGBE_FDIRPICMD_FT_MASK MS(5, 0x3) 675 #define TXGBE_FDIRPICMD_FT_UDP LS(1, 5, 0x3) 676 #define TXGBE_FDIRPICMD_FT_TCP LS(2, 5, 0x3) 677 #define TXGBE_FDIRPICMD_FT_SCTP LS(3, 5, 0x3) 678 #define TXGBE_FDIRPICMD_IP6 MS(7, 0x1) 679 #define TXGBE_FDIRPICMD_CLR MS(8, 0x1) 680 #define TXGBE_FDIRPICMD_DROP MS(9, 0x1) 681 #define TXGBE_FDIRPICMD_LLI MS(10, 0x1) 682 #define TXGBE_FDIRPICMD_LAST MS(11, 0x1) 683 #define TXGBE_FDIRPICMD_COLLI MS(12, 0x1) 684 #define TXGBE_FDIRPICMD_QPENA MS(15, 0x1) 685 #define TXGBE_FDIRPICMD_QP(v) LS(v, 16, 0x7F) 686 #define TXGBE_FDIRPICMD_POOL(v) LS(v, 24, 0x3F) 687 688 /** 689 * 5-tuple Filter 690 **/ 691 #define TXGBE_5TFSADDR(i) (0x019600 + (i) * 4) /* 0-127 */ 692 #define TXGBE_5TFDADDR(i) (0x019800 + (i) * 4) /* 0-127 */ 693 #define TXGBE_5TFPORT(i) (0x019A00 + (i) * 4) /* 0-127 */ 694 #define TXGBE_5TFPORT_SRC(v) LS(v, 0, 0xFFFF) 695 #define TXGBE_5TFPORT_DST(v) LS(v, 16, 0xFFFF) 696 #define TXGBE_5TFCTL0(i) (0x019C00 + (i) * 4) /* 0-127 */ 697 #define TXGBE_5TFCTL0_PROTO(v) LS(v, 0, 0x3) 698 enum txgbe_5tuple_protocol { 699 TXGBE_5TF_PROT_TCP = 0, 700 TXGBE_5TF_PROT_UDP, 701 TXGBE_5TF_PROT_SCTP, 702 TXGBE_5TF_PROT_NONE, 703 }; 704 #define TXGBE_5TFCTL0_PRI(v) LS(v, 2, 0x7) 705 #define TXGBE_5TFCTL0_POOL(v) LS(v, 8, 0x3F) 706 #define TXGBE_5TFCTL0_MASK MS(25, 0x3F) 707 #define TXGBE_5TFCTL0_MSADDR MS(25, 0x1) 708 #define TXGBE_5TFCTL0_MDADDR MS(26, 0x1) 709 #define TXGBE_5TFCTL0_MSPORT MS(27, 0x1) 710 #define TXGBE_5TFCTL0_MDPORT MS(28, 0x1) 711 #define TXGBE_5TFCTL0_MPROTO MS(29, 0x1) 712 #define TXGBE_5TFCTL0_MPOOL MS(30, 0x1) 713 #define TXGBE_5TFCTL0_ENA MS(31, 0x1) 714 #define TXGBE_5TFCTL1(i) (0x019E00 + (i) * 4) /* 0-127 */ 715 #define TXGBE_5TFCTL1_CHKSZ MS(12, 0x1) 716 #define TXGBE_5TFCTL1_LLI MS(20, 0x1) 717 #define TXGBE_5TFCTL1_QP(v) LS(v, 21, 0x7F) 718 719 /** 720 * Storm Control 721 **/ 722 #define TXGBE_STRMCTL 0x015004 723 #define TXGBE_STRMCTL_MCPNSH MS(0, 0x1) 724 #define TXGBE_STRMCTL_MCDROP MS(1, 0x1) 725 #define TXGBE_STRMCTL_BCPNSH MS(2, 0x1) 726 #define TXGBE_STRMCTL_BCDROP MS(3, 0x1) 727 #define TXGBE_STRMCTL_DFTPOOL MS(4, 0x1) 728 #define TXGBE_STRMCTL_ITVL(v) LS(v, 8, 0x3FF) 729 #define TXGBE_STRMTH 0x015008 730 #define TXGBE_STRMTH_MC(v) LS(v, 0, 0xFFFF) 731 #define TXGBE_STRMTH_BC(v) LS(v, 16, 0xFFFF) 732 733 /****************************************************************************** 734 * Ether Flow 735 ******************************************************************************/ 736 #define TXGBE_PSRCTL 0x015000 737 #define TXGBE_PSRCTL_TPE MS(4, 0x1) 738 #define TXGBE_PSRCTL_ADHF12_MASK MS(5, 0x3) 739 #define TXGBE_PSRCTL_ADHF12(v) LS(v, 5, 0x3) 740 #define TXGBE_PSRCTL_UCHFENA MS(7, 0x1) 741 #define TXGBE_PSRCTL_MCHFENA MS(7, 0x1) 742 #define TXGBE_PSRCTL_MCP MS(8, 0x1) 743 #define TXGBE_PSRCTL_UCP MS(9, 0x1) 744 #define TXGBE_PSRCTL_BCA MS(10, 0x1) 745 #define TXGBE_PSRCTL_L4CSUM MS(12, 0x1) 746 #define TXGBE_PSRCTL_PCSD MS(13, 0x1) 747 #define TXGBE_PSRCTL_RSCPUSH MS(15, 0x1) 748 #define TXGBE_PSRCTL_RSCDIA MS(16, 0x1) 749 #define TXGBE_PSRCTL_RSCACK MS(17, 0x1) 750 #define TXGBE_PSRCTL_LBENA MS(18, 0x1) 751 #define TXGBE_FRMSZ 0x015020 752 #define TXGBE_FRMSZ_MAX_MASK MS(0, 0xFFFF) 753 #define TXGBE_FRMSZ_MAX(v) LS((v) + 4, 0, 0xFFFF) 754 #define TXGBE_VLANCTL 0x015088 755 #define TXGBE_VLANCTL_TPID_MASK MS(0, 0xFFFF) 756 #define TXGBE_VLANCTL_TPID(v) LS(v, 0, 0xFFFF) 757 #define TXGBE_VLANCTL_CFI MS(28, 0x1) 758 #define TXGBE_VLANCTL_CFIENA MS(29, 0x1) 759 #define TXGBE_VLANCTL_VFE MS(30, 0x1) 760 #define TXGBE_POOLCTL 0x0151B0 761 #define TXGBE_POOLCTL_DEFDSA MS(29, 0x1) 762 #define TXGBE_POOLCTL_RPLEN MS(30, 0x1) 763 #define TXGBE_POOLCTL_MODE_MASK MS(16, 0x3) 764 #define TXGBE_PSRPOOL_MODE_MAC LS(0, 16, 0x3) 765 #define TXGBE_PSRPOOL_MODE_ETAG LS(1, 16, 0x3) 766 #define TXGBE_POOLCTL_DEFPL(v) LS(v, 7, 0x3F) 767 #define TXGBE_POOLCTL_DEFPL_MASK MS(7, 0x3F) 768 769 #define TXGBE_ETFLT(i) (0x015128 + (i) * 4) /* 0-7 */ 770 #define TXGBE_ETFLT_ETID(v) LS(v, 0, 0xFFFF) 771 #define TXGBE_ETFLT_ETID_MASK MS(0, 0xFFFF) 772 #define TXGBE_ETFLT_POOL(v) LS(v, 20, 0x3FF) 773 #define TXGBE_ETFLT_POOLENA MS(26, 0x1) 774 #define TXGBE_ETFLT_FCOE MS(27, 0x1) 775 #define TXGBE_ETFLT_TXAS MS(29, 0x1) 776 #define TXGBE_ETFLT_1588 MS(30, 0x1) 777 #define TXGBE_ETFLT_ENA MS(31, 0x1) 778 #define TXGBE_ETCLS(i) (0x019100 + (i) * 4) /* 0-7 */ 779 #define TXGBE_ETCLS_QPID(v) LS(v, 16, 0x7F) 780 #define TXGBD_ETCLS_QPID(r) RS(r, 16, 0x7F) 781 #define TXGBE_ETCLS_LLI MS(29, 0x1) 782 #define TXGBE_ETCLS_QENA MS(31, 0x1) 783 #define TXGBE_SYNCLS 0x019130 784 #define TXGBE_SYNCLS_ENA MS(0, 0x1) 785 #define TXGBE_SYNCLS_QPID(v) LS(v, 1, 0x7F) 786 #define TXGBD_SYNCLS_QPID(r) RS(r, 1, 0x7F) 787 #define TXGBE_SYNCLS_QPID_MASK MS(1, 0x7F) 788 #define TXGBE_SYNCLS_HIPRIO MS(31, 0x1) 789 790 /* MAC & VLAN & NVE */ 791 #define TXGBE_PSRVLANIDX 0x016230 /* 0-63 */ 792 #define TXGBE_PSRVLAN 0x016220 793 #define TXGBE_PSRVLAN_VID(v) LS(v, 0, 0xFFF) 794 #define TXGBE_PSRVLAN_EA MS(31, 0x1) 795 #define TXGBE_PSRVLANPLM(i) (0x016224 + (i) * 4) /* 0-1 */ 796 797 #define TXGBE_PSRNVEI 0x016260 /* 256 */ 798 #define TXGBE_PSRNVEADDR(i) (0x016240 + (i) * 4) /* 0-3 */ 799 #define TXGBE_PSRNVE 0x016250 800 #define TXGBE_PSRNVE_KEY(v) LS(v, 0, 0xFFFFFF) 801 #define TXGBE_PSRNVE_TYPE(v) LS(v, 24, 0x3) 802 #define TXGBE_PSRNVECTL 0x016254 803 #define TXGBE_PSRNVECTL_MKEY MS(0, 0x1) 804 #define TXGBE_PSRNVECTL_MADDR MS(1, 0x1) 805 #define TXGBE_PSRNVECTL_SEL(v) LS(v, 8, 0x3) 806 #define TXGBE_PSRNVECTL_SEL_ODIP (0) 807 #define TXGBE_PSRNVECTL_SEL_IDMAC (1) 808 #define TXGBE_PSRNVECTL_SEL_IDIP (2) 809 #define TXGBE_PSRNVECTL_EA MS(31, 0x1) 810 #define TXGBE_PSRNVEPM(i) (0x016258 + (i) * 4) /* 0-1 */ 811 812 /** 813 * FCoE 814 **/ 815 #define TXGBE_FCCTL 0x015100 816 #define TXGBE_FCCTL_LLI MS(0, 0x1) 817 #define TXGBE_FCCTL_SAVBAD MS(1, 0x1) 818 #define TXGBE_FCCTL_FRSTRDH MS(2, 0x1) 819 #define TXGBE_FCCTL_LSEQH MS(3, 0x1) 820 #define TXGBE_FCCTL_ALLH MS(4, 0x1) 821 #define TXGBE_FCCTL_FSEQH MS(5, 0x1) 822 #define TXGBE_FCCTL_ICRC MS(6, 0x1) 823 #define TXGBE_FCCTL_CRCBO MS(7, 0x1) 824 #define TXGBE_FCCTL_VER(v) LS(v, 8, 0xF) 825 #define TXGBE_FCRSSCTL 0x019140 826 #define TXGBE_FCRSSCTL_EA MS(0, 0x1) 827 #define TXGBE_FCRSSTBL(i) (0x019160 + (i) * 4) /* 0-7 */ 828 #define TXGBE_FCRSSTBL_QUE(v) LS(v, 0, 0x7F) 829 830 #define TXGBE_FCRXEOF 0x015158 831 #define TXGBE_FCRXSOF 0x0151F8 832 #define TXGBE_FCTXEOF 0x018384 833 #define TXGBE_FCTXSOF 0x018380 834 #define TXGBE_FCRXFCDESC(i) (0x012410 + (i) * 4) /* 0-1 */ 835 #define TXGBE_FCRXFCBUF 0x012418 836 #define TXGBE_FCRXFCDDP 0x012420 837 #define TXGBE_FCRXCTXINVL(i) (0x0190C0 + (i) * 4) /* 0-15 */ 838 839 /* Programming Interface */ 840 #define TXGBE_FCCTXT 0x015110 841 #define TXGBE_FCCTXT_ID(v) (((v) & 0x1FF)) /* 512 */ 842 #define TXGBE_FCCTXT_REVA LS(0x1, 13, 0x1) 843 #define TXGBE_FCCTXT_WREA LS(0x1, 14, 0x1) 844 #define TXGBE_FCCTXT_RDEA LS(0x1, 15, 0x1) 845 #define TXGBE_FCCTXTCTL 0x015108 846 #define TXGBE_FCCTXTCTL_EA MS(0, 0x1) 847 #define TXGBE_FCCTXTCTL_FIRST MS(1, 0x1) 848 #define TXGBE_FCCTXTCTL_WR MS(2, 0x1) 849 #define TXGBE_FCCTXTCTL_SEQID(v) LS(v, 8, 0xFF) 850 #define TXGBE_FCCTXTCTL_SEQNR(v) LS(v, 16, 0xFFFF) 851 #define TXGBE_FCCTXTPARM 0x0151D8 852 853 /** 854 * Mirror Rules 855 **/ 856 #define TXGBE_MIRRCTL(i) (0x015B00 + (i) * 4) 857 #define TXGBE_MIRRCTL_POOL MS(0, 0x1) 858 #define TXGBE_MIRRCTL_UPLINK MS(1, 0x1) 859 #define TXGBE_MIRRCTL_DNLINK MS(2, 0x1) 860 #define TXGBE_MIRRCTL_VLAN MS(3, 0x1) 861 #define TXGBE_MIRRCTL_DESTP(v) LS(v, 8, 0x3F) 862 #define TXGBE_MIRRVLANL(i) (0x015B10 + (i) * 8) 863 #define TXGBE_MIRRVLANH(i) (0x015B14 + (i) * 8) 864 #define TXGBE_MIRRPOOLL(i) (0x015B30 + (i) * 8) 865 #define TXGBE_MIRRPOOLH(i) (0x015B34 + (i) * 8) 866 867 /** 868 * Time Stamp 869 **/ 870 #define TXGBE_TSRXCTL 0x015188 871 #define TXGBE_TSRXCTL_VLD MS(0, 0x1) 872 #define TXGBE_TSRXCTL_TYPE(v) LS(v, 1, 0x7) 873 #define TXGBE_TSRXCTL_TYPE_V2L2 (0) 874 #define TXGBE_TSRXCTL_TYPE_V1L4 (1) 875 #define TXGBE_TSRXCTL_TYPE_V2L24 (2) 876 #define TXGBE_TSRXCTL_TYPE_V2EVENT (5) 877 #define TXGBE_TSRXCTL_ENA MS(4, 0x1) 878 #define TXGBE_TSRXSTMPL 0x0151E8 879 #define TXGBE_TSRXSTMPH 0x0151A4 880 #define TXGBE_TSTXCTL 0x01D400 881 #define TXGBE_TSTXCTL_VLD MS(0, 0x1) 882 #define TXGBE_TSTXCTL_ENA MS(4, 0x1) 883 #define TXGBE_TSTXSTMPL 0x01D404 884 #define TXGBE_TSTXSTMPH 0x01D408 885 #define TXGBE_TSTIMEL 0x01D40C 886 #define TXGBE_TSTIMEH 0x01D410 887 #define TXGBE_TSTIMEINC 0x01D414 888 #define TXGBE_TSTIMEINC_IV(v) LS(v, 0, 0xFFFFFF) 889 #define TXGBE_TSTIMEINC_IP(v) LS(v, 24, 0xFF) 890 #define TXGBE_TSTIMEINC_VP(v, p) \ 891 (((v) & MS(0, 0xFFFFFF)) | TXGBE_TSTIMEINC_IP(p)) 892 893 /** 894 * Wake on Lan 895 **/ 896 #define TXGBE_WOLCTL 0x015B80 897 #define TXGBE_WOLIPCTL 0x015B84 898 #define TXGBE_WOLIP4(i) (0x015BC0 + (i) * 4) /* 0-3 */ 899 #define TXGBE_WOLIP6(i) (0x015BE0 + (i) * 4) /* 0-3 */ 900 901 #define TXGBE_WOLFLEXCTL 0x015CFC 902 #define TXGBE_WOLFLEXI 0x015B8C 903 #define TXGBE_WOLFLEXDAT(i) (0x015C00 + (i) * 16) /* 0-15 */ 904 #define TXGBE_WOLFLEXMSK(i) (0x015C08 + (i) * 16) /* 0-15 */ 905 906 /****************************************************************************** 907 * Security Registers 908 ******************************************************************************/ 909 #define TXGBE_SECRXCTL 0x017000 910 #define TXGBE_SECRXCTL_ODSA MS(0, 0x1) 911 #define TXGBE_SECRXCTL_XDSA MS(1, 0x1) 912 #define TXGBE_SECRXCTL_CRCSTRIP MS(2, 0x1) 913 #define TXGBE_SECRXCTL_SAVEBAD MS(6, 0x1) 914 #define TXGBE_SECRXSTAT 0x017004 915 #define TXGBE_SECRXSTAT_RDY MS(0, 0x1) 916 #define TXGBE_SECRXSTAT_ECC MS(1, 0x1) 917 918 #define TXGBE_SECTXCTL 0x01D000 919 #define TXGBE_SECTXCTL_ODSA MS(0, 0x1) 920 #define TXGBE_SECTXCTL_XDSA MS(1, 0x1) 921 #define TXGBE_SECTXCTL_STFWD MS(2, 0x1) 922 #define TXGBE_SECTXCTL_MSKIV MS(3, 0x1) 923 #define TXGBE_SECTXSTAT 0x01D004 924 #define TXGBE_SECTXSTAT_RDY MS(0, 0x1) 925 #define TXGBE_SECTXSTAT_ECC MS(1, 0x1) 926 #define TXGBE_SECTXBUFAF 0x01D008 927 #define TXGBE_SECTXBUFAE 0x01D00C 928 #define TXGBE_SECTXIFG 0x01D020 929 #define TXGBE_SECTXIFG_MIN(v) LS(v, 0, 0xF) 930 #define TXGBE_SECTXIFG_MIN_MASK MS(0, 0xF) 931 932 933 /** 934 * LinkSec 935 **/ 936 #define TXGBE_LSECRXCAP 0x017200 937 #define TXGBE_LSECRXCTL 0x017204 938 /* disabled(0),check(1),strict(2),drop(3) */ 939 #define TXGBE_LSECRXCTL_MODE_MASK MS(2, 0x3) 940 #define TXGBE_LSECRXCTL_MODE_STRICT LS(2, 2, 0x3) 941 #define TXGBE_LSECRXCTL_POSTHDR MS(6, 0x1) 942 #define TXGBE_LSECRXCTL_REPLAY MS(7, 0x1) 943 #define TXGBE_LSECRXSCIL 0x017208 944 #define TXGBE_LSECRXSCIH 0x01720C 945 #define TXGBE_LSECRXSA(i) (0x017210 + (i) * 4) /* 0-1 */ 946 #define TXGBE_LSECRXPN(i) (0x017218 + (i) * 4) /* 0-1 */ 947 #define TXGBE_LSECRXKEY(n, i) (0x017220 + 0x10 * (n) + 4 * (i)) /*0-3*/ 948 #define TXGBE_LSECTXCAP 0x01D200 949 #define TXGBE_LSECTXCTL 0x01D204 950 /* disabled(0), auth(1), auth+encrypt(2) */ 951 #define TXGBE_LSECTXCTL_MODE_MASK MS(0, 0x3) 952 #define TXGBE_LSECTXCTL_MODE_AUTH LS(1, 0, 0x3) 953 #define TXGBE_LSECTXCTL_MODE_AENC LS(2, 0, 0x3) 954 #define TXGBE_LSECTXCTL_PNTRH_MASK MS(8, 0xFFFFFF) 955 #define TXGBE_LSECTXCTL_PNTRH(v) LS(v, 8, 0xFFFFFF) 956 #define TXGBE_LSECTXSCIL 0x01D208 957 #define TXGBE_LSECTXSCIH 0x01D20C 958 #define TXGBE_LSECTXSA 0x01D210 959 #define TXGBE_LSECTXPN0 0x01D214 960 #define TXGBE_LSECTXPN1 0x01D218 961 #define TXGBE_LSECTXKEY0(i) (0x01D21C + (i) * 4) /* 0-3 */ 962 #define TXGBE_LSECTXKEY1(i) (0x01D22C + (i) * 4) /* 0-3 */ 963 964 #define TXGBE_LSECRX_UTPKT 0x017240 965 #define TXGBE_LSECRX_DECOCT 0x017244 966 #define TXGBE_LSECRX_VLDOCT 0x017248 967 #define TXGBE_LSECRX_BTPKT 0x01724C 968 #define TXGBE_LSECRX_NOSCIPKT 0x017250 969 #define TXGBE_LSECRX_UNSCIPKT 0x017254 970 #define TXGBE_LSECRX_UNCHKPKT 0x017258 971 #define TXGBE_LSECRX_DLYPKT 0x01725C 972 #define TXGBE_LSECRX_LATEPKT 0x017260 973 #define TXGBE_LSECRX_OKPKT(i) (0x017264 + (i) * 4) /* 0-1 */ 974 #define TXGBE_LSECRX_BADPKT(i) (0x01726C + (i) * 4) /* 0-1 */ 975 #define TXGBE_LSECRX_INVPKT(i) (0x017274 + (i) * 4) /* 0-1 */ 976 #define TXGBE_LSECRX_BADSAPKT 0x01727C 977 #define TXGBE_LSECRX_INVSAPKT 0x017280 978 #define TXGBE_LSECTX_UTPKT 0x01D23C 979 #define TXGBE_LSECTX_ENCPKT 0x01D240 980 #define TXGBE_LSECTX_PROTPKT 0x01D244 981 #define TXGBE_LSECTX_ENCOCT 0x01D248 982 #define TXGBE_LSECTX_PROTOCT 0x01D24C 983 984 /** 985 * IpSec 986 **/ 987 #define TXGBE_ISECRXIDX 0x017100 988 #define TXGBE_ISECRXADDR(i) (0x017104 + (i) * 4) /*0-3*/ 989 #define TXGBE_ISECRXSPI 0x017114 990 #define TXGBE_ISECRXIPIDX 0x017118 991 #define TXGBE_ISECRXKEY(i) (0x01711C + (i) * 4) /*0-3*/ 992 #define TXGBE_ISECRXSALT 0x01712C 993 #define TXGBE_ISECRXMODE 0x017130 994 995 #define TXGBE_ISECTXIDX 0x01D100 996 #define TXGBE_ISECTXIDX_WT 0x80000000U 997 #define TXGBE_ISECTXIDX_RD 0x40000000U 998 #define TXGBE_ISECTXIDX_SDIDX 0x0U 999 #define TXGBE_ISECTXIDX_ENA 0x00000001U 1000 1001 #define TXGBE_ISECTXSALT 0x01D104 1002 #define TXGBE_ISECTXKEY(i) (0x01D108 + (i) * 4) /* 0-3 */ 1003 1004 /****************************************************************************** 1005 * MAC Registers 1006 ******************************************************************************/ 1007 #define TXGBE_MACRXCFG 0x011004 1008 #define TXGBE_MACRXCFG_ENA MS(0, 0x1) 1009 #define TXGBE_MACRXCFG_JUMBO MS(8, 0x1) 1010 #define TXGBE_MACRXCFG_LB MS(10, 0x1) 1011 #define TXGBE_MACCNTCTL 0x011800 1012 #define TXGBE_MACCNTCTL_RC MS(2, 0x1) 1013 1014 #define TXGBE_MACRXFLT 0x011008 1015 #define TXGBE_MACRXFLT_PROMISC MS(0, 0x1) 1016 #define TXGBE_MACRXFLT_CTL_MASK MS(6, 0x3) 1017 #define TXGBE_MACRXFLT_CTL_DROP LS(0, 6, 0x3) 1018 #define TXGBE_MACRXFLT_CTL_NOPS LS(1, 6, 0x3) 1019 #define TXGBE_MACRXFLT_CTL_NOFT LS(2, 6, 0x3) 1020 #define TXGBE_MACRXFLT_CTL_PASS LS(3, 6, 0x3) 1021 #define TXGBE_MACRXFLT_RXALL MS(31, 0x1) 1022 1023 /****************************************************************************** 1024 * Statistic Registers 1025 ******************************************************************************/ 1026 /* Ring Counter */ 1027 #define TXGBE_QPRXPKT(rp) (0x001014 + 0x40 * (rp)) 1028 #define TXGBE_QPRXOCTL(rp) (0x001018 + 0x40 * (rp)) 1029 #define TXGBE_QPRXOCTH(rp) (0x00101C + 0x40 * (rp)) 1030 #define TXGBE_QPTXPKT(rp) (0x003014 + 0x40 * (rp)) 1031 #define TXGBE_QPTXOCTL(rp) (0x003018 + 0x40 * (rp)) 1032 #define TXGBE_QPTXOCTH(rp) (0x00301C + 0x40 * (rp)) 1033 #define TXGBE_QPRXMPKT(rp) (0x001020 + 0x40 * (rp)) 1034 1035 /* Host DMA Counter */ 1036 #define TXGBE_DMATXDROP 0x018300 1037 #define TXGBE_DMATXSECDROP 0x018304 1038 #define TXGBE_DMATXPKT 0x018308 1039 #define TXGBE_DMATXOCTL 0x01830C 1040 #define TXGBE_DMATXOCTH 0x018310 1041 #define TXGBE_DMATXMNG 0x018314 1042 #define TXGBE_DMARXDROP 0x012500 1043 #define TXGBE_DMARXPKT 0x012504 1044 #define TXGBE_DMARXOCTL 0x012508 1045 #define TXGBE_DMARXOCTH 0x01250C 1046 #define TXGBE_DMARXMNG 0x012510 1047 1048 /* Packet Buffer Counter */ 1049 #define TXGBE_PBRXMISS(tc) (0x019040 + (tc) * 4) 1050 #define TXGBE_PBRXPKT 0x019060 1051 #define TXGBE_PBRXREP 0x019064 1052 #define TXGBE_PBRXDROP 0x019068 1053 #define TXGBE_PBRXLNKXOFF 0x011988 1054 #define TXGBE_PBRXLNKXON 0x011E0C 1055 #define TXGBE_PBRXUPXON(up) (0x011E30 + (up) * 4) 1056 #define TXGBE_PBRXUPXOFF(up) (0x011E10 + (up) * 4) 1057 1058 #define TXGBE_PBTXLNKXOFF 0x019218 1059 #define TXGBE_PBTXLNKXON 0x01921C 1060 #define TXGBE_PBTXUPXON(up) (0x0192E0 + (up) * 4) 1061 #define TXGBE_PBTXUPXOFF(up) (0x0192C0 + (up) * 4) 1062 #define TXGBE_PBTXUPOFF(up) (0x019280 + (up) * 4) 1063 1064 #define TXGBE_PBLPBK 0x01CF08 1065 1066 /* Ether Flow Counter */ 1067 #define TXGBE_LANPKTDROP 0x0151C0 1068 #define TXGBE_MNGPKTDROP 0x0151C4 1069 1070 /* MAC Counter */ 1071 #define TXGBE_MACRXERRCRCL 0x011928 1072 #define TXGBE_MACRXERRCRCH 0x01192C 1073 #define TXGBE_MACRXERRLENL 0x011978 1074 #define TXGBE_MACRXERRLENH 0x01197C 1075 #define TXGBE_MACRX1TO64L 0x011940 1076 #define TXGBE_MACRX1TO64H 0x011944 1077 #define TXGBE_MACRX65TO127L 0x011948 1078 #define TXGBE_MACRX65TO127H 0x01194C 1079 #define TXGBE_MACRX128TO255L 0x011950 1080 #define TXGBE_MACRX128TO255H 0x011954 1081 #define TXGBE_MACRX256TO511L 0x011958 1082 #define TXGBE_MACRX256TO511H 0x01195C 1083 #define TXGBE_MACRX512TO1023L 0x011960 1084 #define TXGBE_MACRX512TO1023H 0x011964 1085 #define TXGBE_MACRX1024TOMAXL 0x011968 1086 #define TXGBE_MACRX1024TOMAXH 0x01196C 1087 #define TXGBE_MACTX1TO64L 0x011834 1088 #define TXGBE_MACTX1TO64H 0x011838 1089 #define TXGBE_MACTX65TO127L 0x01183C 1090 #define TXGBE_MACTX65TO127H 0x011840 1091 #define TXGBE_MACTX128TO255L 0x011844 1092 #define TXGBE_MACTX128TO255H 0x011848 1093 #define TXGBE_MACTX256TO511L 0x01184C 1094 #define TXGBE_MACTX256TO511H 0x011850 1095 #define TXGBE_MACTX512TO1023L 0x011854 1096 #define TXGBE_MACTX512TO1023H 0x011858 1097 #define TXGBE_MACTX1024TOMAXL 0x01185C 1098 #define TXGBE_MACTX1024TOMAXH 0x011860 1099 1100 #define TXGBE_MACRXUNDERSIZE 0x011938 1101 #define TXGBE_MACRXOVERSIZE 0x01193C 1102 #define TXGBE_MACRXJABBER 0x011934 1103 1104 #define TXGBE_MACRXPKTL 0x011900 1105 #define TXGBE_MACRXPKTH 0x011904 1106 #define TXGBE_MACTXPKTL 0x01181C 1107 #define TXGBE_MACTXPKTH 0x011820 1108 #define TXGBE_MACRXGBOCTL 0x011908 1109 #define TXGBE_MACRXGBOCTH 0x01190C 1110 #define TXGBE_MACTXGBOCTL 0x011814 1111 #define TXGBE_MACTXGBOCTH 0x011818 1112 1113 #define TXGBE_MACRXOCTL 0x011918 1114 #define TXGBE_MACRXOCTH 0x01191C 1115 #define TXGBE_MACRXMPKTL 0x011920 1116 #define TXGBE_MACRXMPKTH 0x011924 1117 #define TXGBE_MACTXOCTL 0x011824 1118 #define TXGBE_MACTXOCTH 0x011828 1119 #define TXGBE_MACTXMPKTL 0x01182C 1120 #define TXGBE_MACTXMPKTH 0x011830 1121 1122 /* Management Counter */ 1123 #define TXGBE_MNGOUT 0x01CF00 1124 #define TXGBE_MNGIN 0x01CF04 1125 1126 /* MAC SEC Counter */ 1127 #define TXGBE_LSECRXUNTAG 0x017240 1128 #define TXGBE_LSECRXDECOCT 0x017244 1129 #define TXGBE_LSECRXVLDOCT 0x017248 1130 #define TXGBE_LSECRXBADTAG 0x01724C 1131 #define TXGBE_LSECRXNOSCI 0x017250 1132 #define TXGBE_LSECRXUKSCI 0x017254 1133 #define TXGBE_LSECRXUNCHK 0x017258 1134 #define TXGBE_LSECRXDLY 0x01725C 1135 #define TXGBE_LSECRXLATE 0x017260 1136 #define TXGBE_LSECRXGOOD 0x017264 1137 #define TXGBE_LSECRXBAD 0x01726C 1138 #define TXGBE_LSECRXUK 0x017274 1139 #define TXGBE_LSECRXBADSA 0x01727C 1140 #define TXGBE_LSECRXUKSA 0x017280 1141 #define TXGBE_LSECTXUNTAG 0x01D23C 1142 #define TXGBE_LSECTXENC 0x01D240 1143 #define TXGBE_LSECTXPTT 0x01D244 1144 #define TXGBE_LSECTXENCOCT 0x01D248 1145 #define TXGBE_LSECTXPTTOCT 0x01D24C 1146 1147 /* IP SEC Counter */ 1148 1149 /* FDIR Counter */ 1150 #define TXGBE_FDIRFREE 0x019538 1151 #define TXGBE_FDIRFREE_FLT(r) RS(r, 0, 0xFFFF) 1152 #define TXGBE_FDIRLEN 0x01954C 1153 #define TXGBE_FDIRLEN_BKTLEN(r) RS(r, 0, 0x3F) 1154 #define TXGBE_FDIRLEN_MAXLEN(r) RS(r, 8, 0x3F) 1155 #define TXGBE_FDIRUSED 0x019550 1156 #define TXGBE_FDIRUSED_ADD(r) RS(r, 0, 0xFFFF) 1157 #define TXGBE_FDIRUSED_REM(r) RS(r, 16, 0xFFFF) 1158 #define TXGBE_FDIRFAIL 0x019554 1159 #define TXGBE_FDIRFAIL_ADD(r) RS(r, 0, 0xFF) 1160 #define TXGBE_FDIRFAIL_REM(r) RS(r, 8, 0xFF) 1161 #define TXGBE_FDIRMATCH 0x019558 1162 #define TXGBE_FDIRMISS 0x01955C 1163 1164 /* FCOE Counter */ 1165 #define TXGBE_FCOECRC 0x015160 1166 #define TXGBE_FCOERPDC 0x012514 1167 #define TXGBE_FCOELAST 0x012518 1168 #define TXGBE_FCOEPRC 0x015164 1169 #define TXGBE_FCOEDWRC 0x015168 1170 #define TXGBE_FCOEPTC 0x018318 1171 #define TXGBE_FCOEDWTC 0x01831C 1172 1173 /* Management Counter */ 1174 #define TXGBE_MNGOS2BMC 0x01E094 1175 #define TXGBE_MNGBMC2OS 0x01E090 1176 1177 /****************************************************************************** 1178 * PF(Physical Function) Registers 1179 ******************************************************************************/ 1180 /* Interrupt */ 1181 #define TXGBE_ICRMISC 0x000100 1182 #define TXGBE_ICRMISC_MASK MS(8, 0xFFFFFF) 1183 #define TXGBE_ICRMISC_LNKDN MS(8, 0x1) /* eth link down */ 1184 #define TXGBE_ICRMISC_RST MS(10, 0x1) /* device reset event */ 1185 #define TXGBE_ICRMISC_TS MS(11, 0x1) /* time sync */ 1186 #define TXGBE_ICRMISC_STALL MS(12, 0x1) /* trans or recv path is stalled */ 1187 #define TXGBE_ICRMISC_LNKSEC MS(13, 0x1) /* Tx LinkSec require key exchange */ 1188 #define TXGBE_ICRMISC_ERRBUF MS(14, 0x1) /* Packet Buffer Overrun */ 1189 #define TXGBE_ICRMISC_FDIR MS(15, 0x1) /* FDir Exception */ 1190 #define TXGBE_ICRMISC_I2C MS(16, 0x1) /* I2C interrupt */ 1191 #define TXGBE_ICRMISC_ERRMAC MS(17, 0x1) /* err reported by MAC */ 1192 #define TXGBE_ICRMISC_LNKUP MS(18, 0x1) /* link up */ 1193 #define TXGBE_ICRMISC_ANDONE MS(19, 0x1) /* link auto-nego done */ 1194 #define TXGBE_ICRMISC_ERRIG MS(20, 0x1) /* integrity error */ 1195 #define TXGBE_ICRMISC_SPI MS(21, 0x1) /* SPI interface */ 1196 #define TXGBE_ICRMISC_VFMBX MS(22, 0x1) /* VF-PF message box */ 1197 #define TXGBE_ICRMISC_GPIO MS(26, 0x1) /* GPIO interrupt */ 1198 #define TXGBE_ICRMISC_ERRPCI MS(27, 0x1) /* pcie request error */ 1199 #define TXGBE_ICRMISC_HEAT MS(28, 0x1) /* overheat detection */ 1200 #define TXGBE_ICRMISC_PROBE MS(29, 0x1) /* probe match */ 1201 #define TXGBE_ICRMISC_MNGMBX MS(30, 0x1) /* mng mailbox */ 1202 #define TXGBE_ICRMISC_TIMER MS(31, 0x1) /* tcp timer */ 1203 #define TXGBE_ICRMISC_DEFAULT ( \ 1204 TXGBE_ICRMISC_LNKDN | \ 1205 TXGBE_ICRMISC_RST | \ 1206 TXGBE_ICRMISC_ERRMAC | \ 1207 TXGBE_ICRMISC_LNKUP | \ 1208 TXGBE_ICRMISC_ANDONE | \ 1209 TXGBE_ICRMISC_ERRIG | \ 1210 TXGBE_ICRMISC_VFMBX | \ 1211 TXGBE_ICRMISC_MNGMBX | \ 1212 TXGBE_ICRMISC_STALL | \ 1213 TXGBE_ICRMISC_TIMER) 1214 #define TXGBE_ICRMISC_LSC ( \ 1215 TXGBE_ICRMISC_LNKDN | \ 1216 TXGBE_ICRMISC_LNKUP) 1217 #define TXGBE_ICSMISC 0x000104 1218 #define TXGBE_IENMISC 0x000108 1219 #define TXGBE_IVARMISC 0x0004FC 1220 #define TXGBE_IVARMISC_VEC(v) LS(v, 0, 0x7) 1221 #define TXGBE_IVARMISC_VLD MS(7, 0x1) 1222 #define TXGBE_PX_INTA 0x000110 1223 #define TXGBE_ICR(i) (0x000120 + (i) * 4) /* 0-1 */ 1224 #define TXGBE_ICR_MASK MS(0, 0xFFFFFFFF) 1225 #define TXGBE_ICS(i) (0x000130 + (i) * 4) /* 0-1 */ 1226 #define TXGBE_ICS_MASK TXGBE_ICR_MASK 1227 #define TXGBE_IMS(i) (0x000140 + (i) * 4) /* 0-1 */ 1228 #define TXGBE_IMS_MASK TXGBE_ICR_MASK 1229 #define TXGBE_IMC(i) (0x000150 + (i) * 4) /* 0-1 */ 1230 #define TXGBE_IMC_MASK TXGBE_ICR_MASK 1231 #define TXGBE_IVAR(i) (0x000500 + (i) * 4) /* 0-3 */ 1232 #define TXGBE_IVAR_VEC(v) LS(v, 0, 0x7) 1233 #define TXGBE_IVAR_VLD MS(7, 0x1) 1234 #define TXGBE_TCPTMR 0x000170 1235 #define TXGBE_ITRSEL 0x000180 1236 1237 /* P2V Mailbox */ 1238 #define TXGBE_MBMEM(i) (0x005000 + 0x40 * (i)) /* 0-63 */ 1239 #define TXGBE_MBCTL(i) (0x000600 + 4 * (i)) /* 0-63 */ 1240 #define TXGBE_MBCTL_STS MS(0, 0x1) /* Initiate message send to VF */ 1241 #define TXGBE_MBCTL_ACK MS(1, 0x1) /* Ack message recv'd from VF */ 1242 #define TXGBE_MBCTL_VFU MS(2, 0x1) /* VF owns the mailbox buffer */ 1243 #define TXGBE_MBCTL_PFU MS(3, 0x1) /* PF owns the mailbox buffer */ 1244 #define TXGBE_MBCTL_RVFU MS(4, 0x1) /* Reset VFU - used when VF stuck */ 1245 #define TXGBE_MBVFICR(i) (0x000480 + 4 * (i)) /* 0-3 */ 1246 #define TXGBE_MBVFICR_INDEX(vf) ((vf) >> 4) 1247 #define TXGBE_MBVFICR_VFREQ_MASK (0x0000FFFF) /* bits for VF messages */ 1248 #define TXGBE_MBVFICR_VFREQ_VF1 (0x00000001) /* bit for VF 1 message */ 1249 #define TXGBE_MBVFICR_VFACK_MASK (0xFFFF0000) /* bits for VF acks */ 1250 #define TXGBE_MBVFICR_VFACK_VF1 (0x00010000) /* bit for VF 1 ack */ 1251 #define TXGBE_FLRVFP(i) (0x000490 + 4 * (i)) /* 0-1 */ 1252 #define TXGBE_FLRVFE(i) (0x0004A0 + 4 * (i)) /* 0-1 */ 1253 #define TXGBE_FLRVFEC(i) (0x0004A8 + 4 * (i)) /* 0-1 */ 1254 1255 /****************************************************************************** 1256 * VF(Virtual Function) Registers 1257 ******************************************************************************/ 1258 #define TXGBE_VFPBWRAP 0x000000 1259 #define TXGBE_VFPBWRAP_WRAP(r, tc) ((0x7 << 4 * (tc) & (r)) >> 4 * (tc)) 1260 #define TXGBE_VFPBWRAP_EMPT(r, tc) ((0x8 << 4 * (tc) & (r)) >> 4 * (tc)) 1261 #define TXGBE_VFSTATUS 0x000004 1262 #define TXGBE_VFSTATUS_UP MS(0, 0x1) 1263 #define TXGBE_VFSTATUS_BW_MASK MS(1, 0x7) 1264 #define TXGBE_VFSTATUS_BW_10G LS(0x1, 1, 0x7) 1265 #define TXGBE_VFSTATUS_BW_1G LS(0x2, 1, 0x7) 1266 #define TXGBE_VFSTATUS_BW_100M LS(0x4, 1, 0x7) 1267 #define TXGBE_VFSTATUS_BUSY MS(4, 0x1) 1268 #define TXGBE_VFSTATUS_LANID MS(8, 0x1) 1269 #define TXGBE_VFRST 0x000008 1270 #define TXGBE_VFRST_SET MS(0, 0x1) 1271 #define TXGBE_VFPLCFG 0x000078 1272 #define TXGBE_VFPLCFG_RSV MS(0, 0x1) 1273 #define TXGBE_VFPLCFG_PSR(v) LS(v, 1, 0x1F) 1274 #define TXGBE_VFPLCFG_PSRL4HDR (0x1) 1275 #define TXGBE_VFPLCFG_PSRL3HDR (0x2) 1276 #define TXGBE_VFPLCFG_PSRL2HDR (0x4) 1277 #define TXGBE_VFPLCFG_PSRTUNHDR (0x8) 1278 #define TXGBE_VFPLCFG_PSRTUNMAC (0x10) 1279 #define TXGBE_VFPLCFG_RSSMASK MS(16, 0xFF) 1280 #define TXGBE_VFPLCFG_RSSIPV4TCP MS(16, 0x1) 1281 #define TXGBE_VFPLCFG_RSSIPV4 MS(17, 0x1) 1282 #define TXGBE_VFPLCFG_RSSIPV6 MS(20, 0x1) 1283 #define TXGBE_VFPLCFG_RSSIPV6TCP MS(21, 0x1) 1284 #define TXGBE_VFPLCFG_RSSIPV4UDP MS(22, 0x1) 1285 #define TXGBE_VFPLCFG_RSSIPV6UDP MS(23, 0x1) 1286 #define TXGBE_VFPLCFG_RSSENA MS(24, 0x1) 1287 #define TXGBE_VFPLCFG_RSSHASH(v) LS(v, 29, 0x7) 1288 #define TXGBE_VFRSSKEY(i) (0x000080 + (i) * 4) /* 0-9 */ 1289 #define TXGBE_VFRSSTBL(i) (0x0000C0 + (i) * 4) /* 0-15 */ 1290 #define TXGBE_VFICR 0x000100 1291 #define TXGBE_VFICR_MASK LS(7, 0, 0x7) 1292 #define TXGBE_VFICR_MBX MS(0, 0x1) 1293 #define TXGBE_VFICR_DONE1 MS(1, 0x1) 1294 #define TXGBE_VFICR_DONE2 MS(2, 0x1) 1295 #define TXGBE_VFICS 0x000104 1296 #define TXGBE_VFICS_MASK TXGBE_VFICR_MASK 1297 #define TXGBE_VFIMS 0x000108 1298 #define TXGBE_VFIMS_MASK TXGBE_VFICR_MASK 1299 #define TXGBE_VFIMC 0x00010C 1300 #define TXGBE_VFIMC_MASK TXGBE_VFICR_MASK 1301 #define TXGBE_VFGPIE 0x000118 1302 #define TXGBE_VFIVAR(i) (0x000240 + 4 * (i)) /* 0-3 */ 1303 #define TXGBE_VFIVARMISC 0x000260 1304 #define TXGBE_VFIVAR_ALLOC(v) LS(v, 0, 0x3) 1305 #define TXGBE_VFIVAR_VLD MS(7, 0x1) 1306 1307 #define TXGBE_VFMBCTL 0x000600 1308 #define TXGBE_VFMBCTL_REQ MS(0, 0x1) /* Request for PF Ready bit */ 1309 #define TXGBE_VFMBCTL_ACK MS(1, 0x1) /* Ack PF message received */ 1310 #define TXGBE_VFMBCTL_VFU MS(2, 0x1) /* VF owns the mailbox buffer */ 1311 #define TXGBE_VFMBCTL_PFU MS(3, 0x1) /* PF owns the mailbox buffer */ 1312 #define TXGBE_VFMBCTL_PFSTS MS(4, 0x1) /* PF wrote a message in the MB */ 1313 #define TXGBE_VFMBCTL_PFACK MS(5, 0x1) /* PF ack the previous VF msg */ 1314 #define TXGBE_VFMBCTL_RSTI MS(6, 0x1) /* PF has reset indication */ 1315 #define TXGBE_VFMBCTL_RSTD MS(7, 0x1) /* PF has indicated reset done */ 1316 #define TXGBE_VFMBCTL_R2C_BITS (TXGBE_VFMBCTL_RSTD | \ 1317 TXGBE_VFMBCTL_PFSTS | \ 1318 TXGBE_VFMBCTL_PFACK) 1319 #define TXGBE_VFMBX 0x000C00 /* 0-15 */ 1320 #define TXGBE_VFTPHCTL(i) (0x000D00 + 4 * (i)) /* 0-7 */ 1321 1322 /****************************************************************************** 1323 * PF&VF TxRx Interface 1324 ******************************************************************************/ 1325 #define RNGLEN(v) ROUND_OVER(v, 13, 7) 1326 #define HDRLEN(v) ROUND_OVER(v, 10, 6) 1327 #define PKTLEN(v) ROUND_OVER(v, 14, 10) 1328 #define INTTHR(v) ROUND_OVER(v, 4, 0) 1329 1330 #define TXGBE_RING_DESC_ALIGN 128 1331 #define TXGBE_RING_DESC_MIN 128 1332 #define TXGBE_RING_DESC_MAX 8192 1333 #define TXGBE_RXD_ALIGN TXGBE_RING_DESC_ALIGN 1334 #define TXGBE_TXD_ALIGN TXGBE_RING_DESC_ALIGN 1335 1336 /* receive ring */ 1337 #define TXGBE_RXBAL(rp) (0x001000 + 0x40 * (rp)) 1338 #define TXGBE_RXBAH(rp) (0x001004 + 0x40 * (rp)) 1339 #define TXGBE_RXRP(rp) (0x00100C + 0x40 * (rp)) 1340 #define TXGBE_RXWP(rp) (0x001008 + 0x40 * (rp)) 1341 #define TXGBE_RXCFG(rp) (0x001010 + 0x40 * (rp)) 1342 #define TXGBE_RXCFG_ENA MS(0, 0x1) 1343 #define TXGBE_RXCFG_RNGLEN(v) LS(RNGLEN(v), 1, 0x3F) 1344 #define TXGBE_RXCFG_PKTLEN(v) LS(PKTLEN(v), 8, 0xF) 1345 #define TXGBE_RXCFG_PKTLEN_MASK MS(8, 0xF) 1346 #define TXGBE_RXCFG_HDRLEN(v) LS(HDRLEN(v), 12, 0xF) 1347 #define TXGBE_RXCFG_HDRLEN_MASK MS(12, 0xF) 1348 #define TXGBE_RXCFG_WTHRESH(v) LS(v, 16, 0x7) 1349 #define TXGBE_RXCFG_ETAG MS(22, 0x1) 1350 #define TXGBE_RXCFG_RSCMAX_MASK MS(23, 0x3) 1351 #define TXGBE_RXCFG_RSCMAX_1 LS(0, 23, 0x3) 1352 #define TXGBE_RXCFG_RSCMAX_4 LS(1, 23, 0x3) 1353 #define TXGBE_RXCFG_RSCMAX_8 LS(2, 23, 0x3) 1354 #define TXGBE_RXCFG_RSCMAX_16 LS(3, 23, 0x3) 1355 #define TXGBE_RXCFG_STALL MS(25, 0x1) 1356 #define TXGBE_RXCFG_SPLIT MS(26, 0x1) 1357 #define TXGBE_RXCFG_RSCMODE MS(27, 0x1) 1358 #define TXGBE_RXCFG_CNTAG MS(28, 0x1) 1359 #define TXGBE_RXCFG_RSCENA MS(29, 0x1) 1360 #define TXGBE_RXCFG_DROP MS(30, 0x1) 1361 #define TXGBE_RXCFG_VLAN MS(31, 0x1) 1362 1363 /* transmit ring */ 1364 #define TXGBE_TXBAL(rp) (0x003000 + 0x40 * (rp)) 1365 #define TXGBE_TXBAH(rp) (0x003004 + 0x40 * (rp)) 1366 #define TXGBE_TXWP(rp) (0x003008 + 0x40 * (rp)) 1367 #define TXGBE_TXRP(rp) (0x00300C + 0x40 * (rp)) 1368 #define TXGBE_TXCFG(rp) (0x003010 + 0x40 * (rp)) 1369 #define TXGBE_TXCFG_ENA MS(0, 0x1) 1370 #define TXGBE_TXCFG_BUFLEN_MASK MS(1, 0x3F) 1371 #define TXGBE_TXCFG_BUFLEN(v) LS(RNGLEN(v), 1, 0x3F) 1372 #define TXGBE_TXCFG_HTHRESH_MASK MS(8, 0xF) 1373 #define TXGBE_TXCFG_HTHRESH(v) LS(v, 8, 0xF) 1374 #define TXGBE_TXCFG_WTHRESH_MASK MS(16, 0x7F) 1375 #define TXGBE_TXCFG_WTHRESH(v) LS(v, 16, 0x7F) 1376 #define TXGBE_TXCFG_FLUSH MS(26, 0x1) 1377 1378 /* interrupt registers */ 1379 #define TXGBE_ITRI 0x000180 1380 #define TXGBE_ITR(i) (0x000200 + 4 * (i)) 1381 #define TXGBE_ITR_IVAL_MASK MS(2, 0x3FE) 1382 #define TXGBE_ITR_IVAL(v) LS(v, 2, 0x3FE) 1383 #define TXGBE_ITR_IVAL_1G(us) TXGBE_ITR_IVAL((us) / 2) 1384 #define TXGBE_ITR_IVAL_10G(us) TXGBE_ITR_IVAL((us) / 20) 1385 #define TXGBE_ITR_LLIEA MS(15, 0x1) 1386 #define TXGBE_ITR_LLICREDIT(v) LS(v, 16, 0x1F) 1387 #define TXGBE_ITR_CNT(v) LS(v, 21, 0x7F) 1388 #define TXGBE_ITR_WRDSA MS(31, 0x1) 1389 #define TXGBE_GPIE 0x000118 1390 #define TXGBE_GPIE_MSIX MS(0, 0x1) 1391 #define TXGBE_GPIE_LLIEA MS(1, 0x1) 1392 #define TXGBE_GPIE_LLIVAL(v) LS(v, 4, 0xF) 1393 #define TXGBE_GPIE_RSCDLY(v) LS(v, 8, 0x7) 1394 1395 /****************************************************************************** 1396 * Debug Registers 1397 ******************************************************************************/ 1398 /** 1399 * Probe 1400 **/ 1401 #define TXGBE_PROB 0x010010 1402 #define TXGBE_IODRV 0x010024 1403 1404 #define TXGBE_PRBCTL 0x010200 1405 #define TXGBE_PRBSTA 0x010204 1406 #define TXGBE_PRBDAT 0x010220 1407 #define TXGBE_PRBPTN 0x010224 1408 #define TXGBE_PRBCNT 0x010228 1409 #define TXGBE_PRBMSK 0x01022C 1410 1411 #define TXGBE_PRBPCI 0x01F010 1412 #define TXGBE_PRBRDMA 0x012010 1413 #define TXGBE_PRBTDMA 0x018010 1414 #define TXGBE_PRBPSR 0x015010 1415 #define TXGBE_PRBRDB 0x019010 1416 #define TXGBE_PRBTDB 0x01C010 1417 #define TXGBE_PRBRSEC 0x017010 1418 #define TXGBE_PRBTSEC 0x01D010 1419 #define TXGBE_PRBMNG 0x01E010 1420 #define TXGBE_PRBRMAC 0x011014 1421 #define TXGBE_PRBTMAC 0x011010 1422 #define TXGBE_PRBREMAC 0x011E04 1423 #define TXGBE_PRBTEMAC 0x011E00 1424 1425 /** 1426 * ECC 1427 **/ 1428 #define TXGBE_ECCRXDMACTL 0x012014 1429 #define TXGBE_ECCRXDMAINJ 0x012018 1430 #define TXGBE_ECCRXDMA 0x01201C 1431 #define TXGBE_ECCTXDMACTL 0x018014 1432 #define TXGBE_ECCTXDMAINJ 0x018018 1433 #define TXGBE_ECCTXDMA 0x01801C 1434 1435 #define TXGBE_ECCRXPBCTL 0x019014 1436 #define TXGBE_ECCRXPBINJ 0x019018 1437 #define TXGBE_ECCRXPB 0x01901C 1438 #define TXGBE_ECCTXPBCTL 0x01C014 1439 #define TXGBE_ECCTXPBINJ 0x01C018 1440 #define TXGBE_ECCTXPB 0x01C01C 1441 1442 #define TXGBE_ECCRXETHCTL 0x015014 1443 #define TXGBE_ECCRXETHINJ 0x015018 1444 #define TXGBE_ECCRXETH 0x01401C 1445 1446 #define TXGBE_ECCRXSECCTL 0x017014 1447 #define TXGBE_ECCRXSECINJ 0x017018 1448 #define TXGBE_ECCRXSEC 0x01701C 1449 #define TXGBE_ECCTXSECCTL 0x01D014 1450 #define TXGBE_ECCTXSECINJ 0x01D018 1451 #define TXGBE_ECCTXSEC 0x01D01C 1452 1453 /** 1454 * Inspection 1455 **/ 1456 #define TXGBE_PBLBSTAT 0x01906C 1457 #define TXGBE_PBLBSTAT_FREE(r) RS(r, 0, 0x3FF) 1458 #define TXGBE_PBLBSTAT_FULL MS(11, 0x1) 1459 #define TXGBE_PBRXSTAT 0x019004 1460 #define TXGBE_PBRXSTAT_WRAP(tc, r) ((7u << 4 * (tc) & (r)) >> 4 * (tc)) 1461 #define TXGBE_PBRXSTAT_EMPT(tc, r) ((8u << 4 * (tc) & (r)) >> 4 * (tc)) 1462 #define TXGBE_PBRXSTAT2(tc) (0x019180 + (tc) * 4) 1463 #define TXGBE_PBRXSTAT2_USED(r) RS(r, 0, 0xFFFF) 1464 #define TXGBE_PBRXWRPTR(tc) (0x019180 + (tc) * 4) 1465 #define TXGBE_PBRXWRPTR_HEAD(r) RS(r, 0, 0xFFFF) 1466 #define TXGBE_PBRXWRPTR_TAIL(r) RS(r, 16, 0xFFFF) 1467 #define TXGBE_PBRXRDPTR(tc) (0x0191A0 + (tc) * 4) 1468 #define TXGBE_PBRXRDPTR_HEAD(r) RS(r, 0, 0xFFFF) 1469 #define TXGBE_PBRXRDPTR_TAIL(r) RS(r, 16, 0xFFFF) 1470 #define TXGBE_PBRXDATA(tc) (0x0191C0 + (tc) * 4) 1471 #define TXGBE_PBRXDATA_RDPTR(r) RS(r, 0, 0xFFFF) 1472 #define TXGBE_PBRXDATA_WRPTR(r) RS(r, 16, 0xFFFF) 1473 #define TXGBE_PBTXSTAT 0x01C004 1474 #define TXGBE_PBTXSTAT_EMPT(tc, r) ((1 << (tc) & (r)) >> (tc)) 1475 1476 #define TXGBE_RXPBPFCDMACL 0x019210 1477 #define TXGBE_RXPBPFCDMACH 0x019214 1478 1479 #define TXGBE_PSRLANPKTCNT 0x0151B8 1480 #define TXGBE_PSRMNGPKTCNT 0x0151BC 1481 1482 #define TXGBE_P2VMBX_SIZE (16) /* 16*4B */ 1483 #define TXGBE_P2MMBX_SIZE (64) /* 64*4B */ 1484 1485 /**************** Global Registers ****************************/ 1486 /* chip control Registers */ 1487 #define TXGBE_PWR 0x010000 1488 #define TXGBE_PWR_LANID(r) RS(r, 30, 0x3) 1489 #define TXGBE_PWR_LANID_SWAP LS(2, 30, 0x3) 1490 1491 /* Sensors for PVT(Process Voltage Temperature) */ 1492 #define TXGBE_TSCTRL 0x010300 1493 #define TXGBE_TSCTRL_EVALMD MS(31, 0x1) 1494 #define TXGBE_TSEN 0x010304 1495 #define TXGBE_TSEN_ENA MS(0, 0x1) 1496 #define TXGBE_TSSTAT 0x010308 1497 #define TXGBE_TSSTAT_VLD MS(16, 0x1) 1498 #define TXGBE_TSSTAT_DATA(r) RS(r, 0, 0x3FF) 1499 1500 #define TXGBE_TSATHRE 0x01030C 1501 #define TXGBE_TSDTHRE 0x010310 1502 #define TXGBE_TSINTR 0x010314 1503 #define TXGBE_TSINTR_AEN MS(0, 0x1) 1504 #define TXGBE_TSINTR_DEN MS(1, 0x1) 1505 #define TXGBE_TS_ALARM_ST 0x10318 1506 #define TXGBE_TS_ALARM_ST_DALARM 0x00000002U 1507 #define TXGBE_TS_ALARM_ST_ALARM 0x00000001U 1508 1509 /* FMGR Registers */ 1510 #define TXGBE_ILDRSTAT 0x010120 1511 #define TXGBE_ILDRSTAT_PCIRST MS(0, 0x1) 1512 #define TXGBE_ILDRSTAT_PWRRST MS(1, 0x1) 1513 #define TXGBE_ILDRSTAT_SWRST MS(7, 0x1) 1514 #define TXGBE_ILDRSTAT_SWRST_LAN0 MS(9, 0x1) 1515 #define TXGBE_ILDRSTAT_SWRST_LAN1 MS(10, 0x1) 1516 1517 #define TXGBE_SPISTAT 0x01010C 1518 #define TXGBE_SPISTAT_OPDONE MS(0, 0x1) 1519 #define TXGBE_SPISTAT_BPFLASH MS(31, 0x1) 1520 1521 /************************* Port Registers ************************************/ 1522 /* I2C registers */ 1523 #define TXGBE_I2CCON 0x014900 /* I2C Control */ 1524 #define TXGBE_I2CCON_SDIA ((1 << 6)) 1525 #define TXGBE_I2CCON_RESTART ((1 << 5)) 1526 #define TXGBE_I2CCON_M10BITADDR ((1 << 4)) 1527 #define TXGBE_I2CCON_S10BITADDR ((1 << 3)) 1528 #define TXGBE_I2CCON_SPEED(v) (((v) & 0x3) << 1) 1529 #define TXGBE_I2CCON_MENA ((1 << 0)) 1530 #define TXGBE_I2CTAR 0x014904 /* I2C Target Address */ 1531 #define TXGBE_I2CDATA 0x014910 /* I2C Rx/Tx Data Buf and Cmd */ 1532 #define TXGBE_I2CDATA_STOP ((1 << 9)) 1533 #define TXGBE_I2CDATA_READ ((1 << 8) | TXGBE_I2CDATA_STOP) 1534 #define TXGBE_I2CDATA_WRITE ((0 << 8) | TXGBE_I2CDATA_STOP) 1535 #define TXGBE_I2CSSSCLHCNT 0x014914 1536 #define TXGBE_I2CSSSCLLCNT 0x014918 1537 #define TXGBE_I2CICR 0x014934 /* I2C Raw Interrupt Status */ 1538 #define TXGBE_I2CICR_RXFULL ((0x1) << 2) 1539 #define TXGBE_I2CICR_TXEMPTY ((0x1) << 4) 1540 #define TXGBE_I2CICM 0x014930 /* I2C Interrupt Mask */ 1541 #define TXGBE_I2CRXTL 0x014938 /* I2C Receive FIFO Threshold */ 1542 #define TXGBE_I2CTXTL 0x01493C /* I2C TX FIFO Threshold */ 1543 #define TXGBE_I2CENA 0x01496C /* I2C Enable */ 1544 #define TXGBE_I2CSTAT 0x014970 /* I2C Status register */ 1545 #define TXGBE_I2CSTAT_MST ((1U << 5)) 1546 #define TXGBE_I2CSCLTMOUT 0x0149AC 1547 #define TXGBE_I2CSDATMOUT 0x0149B0 /*I2C SDA Stuck at Low Timeout*/ 1548 1549 /* port cfg Registers */ 1550 #define TXGBE_PORTSTAT 0x014404 1551 #define TXGBE_PORTSTAT_UP MS(0, 0x1) 1552 #define TXGBE_PORTSTAT_BW_MASK MS(1, 0x7) 1553 #define TXGBE_PORTSTAT_BW_10G MS(1, 0x1) 1554 #define TXGBE_PORTSTAT_BW_1G MS(2, 0x1) 1555 #define TXGBE_PORTSTAT_BW_100M MS(3, 0x1) 1556 #define TXGBE_PORTSTAT_ID(r) RS(r, 8, 0x1) 1557 1558 #define TXGBE_VXLAN 0x014410 1559 #define TXGBE_VXLAN_GPE 0x014414 1560 #define TXGBE_GENEVE 0x014418 1561 #define TXGBE_TEREDO 0x01441C 1562 #define TXGBE_TCPTIME 0x014420 1563 1564 /* GPIO Registers */ 1565 #define TXGBE_GPIODATA 0x014800 1566 #define TXGBE_GPIOBIT_0 MS(0, 0x1) /* O:tx fault */ 1567 #define TXGBE_GPIOBIT_1 MS(1, 0x1) /* O:tx disabled */ 1568 #define TXGBE_GPIOBIT_2 MS(2, 0x1) /* I:sfp module absent */ 1569 #define TXGBE_GPIOBIT_3 MS(3, 0x1) /* I:rx signal lost */ 1570 #define TXGBE_GPIOBIT_4 MS(4, 0x1) /* O:rate select, 1G(0) 10G(1) */ 1571 #define TXGBE_GPIOBIT_5 MS(5, 0x1) /* O:rate select, 1G(0) 10G(1) */ 1572 #define TXGBE_GPIOBIT_6 MS(6, 0x1) /* I:ext phy interrupt */ 1573 #define TXGBE_GPIOBIT_7 MS(7, 0x1) /* I:fan speed alarm */ 1574 #define TXGBE_GPIODIR 0x014804 1575 #define TXGBE_GPIOCTL 0x014808 1576 #define TXGBE_GPIOINTEN 0x014830 1577 #define TXGBE_GPIOINTMASK 0x014834 1578 #define TXGBE_GPIOINTTYPE 0x014838 1579 #define TXGBE_GPIOINTSTAT 0x014840 1580 #define TXGBE_GPIOEOI 0x01484C 1581 1582 1583 #define TXGBE_ARBPOOLIDX 0x01820C 1584 #define TXGBE_ARBTXRATE 0x018404 1585 #define TXGBE_ARBTXRATE_MIN(v) LS(v, 0, 0x3FFF) 1586 #define TXGBE_ARBTXRATE_MAX(v) LS(v, 16, 0x3FFF) 1587 1588 /* qos */ 1589 #define TXGBE_ARBTXCTL 0x018200 1590 #define TXGBE_ARBTXCTL_RRM MS(1, 0x1) 1591 #define TXGBE_ARBTXCTL_WSP MS(2, 0x1) 1592 #define TXGBE_ARBTXCTL_DIA MS(6, 0x1) 1593 #define TXGBE_ARBTXMMW 0x018208 1594 1595 /**************************** Receive DMA registers **************************/ 1596 /* receive control */ 1597 #define TXGBE_ARBRXCTL 0x012000 1598 #define TXGBE_ARBRXCTL_RRM MS(1, 0x1) 1599 #define TXGBE_ARBRXCTL_WSP MS(2, 0x1) 1600 #define TXGBE_ARBRXCTL_DIA MS(6, 0x1) 1601 1602 #define TXGBE_RPUP2TC 0x019008 1603 #define TXGBE_RPUP2TC_UP_SHIFT 3 1604 #define TXGBE_RPUP2TC_UP_MASK 0x7 1605 1606 /* mac switcher */ 1607 #define TXGBE_ETHADDRL 0x016200 1608 #define TXGBE_ETHADDRL_AD0(v) LS(v, 0, 0xFF) 1609 #define TXGBE_ETHADDRL_AD1(v) LS(v, 8, 0xFF) 1610 #define TXGBE_ETHADDRL_AD2(v) LS(v, 16, 0xFF) 1611 #define TXGBE_ETHADDRL_AD3(v) LS(v, 24, 0xFF) 1612 #define TXGBE_ETHADDRL_ETAG(r) RS(r, 0, 0x3FFF) 1613 #define TXGBE_ETHADDRH 0x016204 1614 #define TXGBE_ETHADDRH_AD4(v) LS(v, 0, 0xFF) 1615 #define TXGBE_ETHADDRH_AD5(v) LS(v, 8, 0xFF) 1616 #define TXGBE_ETHADDRH_AD_MASK MS(0, 0xFFFF) 1617 #define TXGBE_ETHADDRH_ETAG MS(30, 0x1) 1618 #define TXGBE_ETHADDRH_VLD MS(31, 0x1) 1619 #define TXGBE_ETHADDRASSL 0x016208 1620 #define TXGBE_ETHADDRASSH 0x01620C 1621 #define TXGBE_ETHADDRIDX 0x016210 1622 1623 /* Outmost Barrier Filters */ 1624 #define TXGBE_MCADDRTBL(i) (0x015200 + (i) * 4) /* 0-127 */ 1625 #define TXGBE_UCADDRTBL(i) (0x015400 + (i) * 4) /* 0-127 */ 1626 #define TXGBE_VLANTBL(i) (0x016000 + (i) * 4) /* 0-127 */ 1627 1628 #define TXGBE_MNGFLEXSEL 0x1582C 1629 #define TXGBE_MNGFLEXDWL(i) (0x15A00 + ((i) * 16)) 1630 #define TXGBE_MNGFLEXDWH(i) (0x15A04 + ((i) * 16)) 1631 #define TXGBE_MNGFLEXMSK(i) (0x15A08 + ((i) * 16)) 1632 1633 #define TXGBE_LANFLEXSEL 0x15B8C 1634 #define TXGBE_LANFLEXDWL(i) (0x15C00 + ((i) * 16)) 1635 #define TXGBE_LANFLEXDWH(i) (0x15C04 + ((i) * 16)) 1636 #define TXGBE_LANFLEXMSK(i) (0x15C08 + ((i) * 16)) 1637 #define TXGBE_LANFLEXCTL 0x15CFC 1638 1639 /* ipsec */ 1640 #define TXGBE_IPSRXIDX 0x017100 1641 #define TXGBE_IPSRXIDX_ENA MS(0, 0x1) 1642 #define TXGBE_IPSRXIDX_TB_MASK MS(1, 0x3) 1643 #define TXGBE_IPSRXIDX_TB_IP LS(1, 1, 0x3) 1644 #define TXGBE_IPSRXIDX_TB_SPI LS(2, 1, 0x3) 1645 #define TXGBE_IPSRXIDX_TB_KEY LS(3, 1, 0x3) 1646 #define TXGBE_IPSRXIDX_TBIDX(v) LS(v, 3, 0x3FF) 1647 #define TXGBE_IPSRXIDX_READ MS(30, 0x1) 1648 #define TXGBE_IPSRXIDX_WRITE MS(31, 0x1) 1649 #define TXGBE_IPSRXADDR(i) (0x017104 + (i) * 4) 1650 1651 #define TXGBE_IPSRXSPI 0x017114 1652 #define TXGBE_IPSRXADDRIDX 0x017118 1653 #define TXGBE_IPSRXKEY(i) (0x01711C + (i) * 4) 1654 #define TXGBE_IPSRXSALT 0x01712C 1655 #define TXGBE_IPSRXMODE 0x017130 1656 #define TXGBE_IPSRXMODE_IPV6 0x00000010 1657 #define TXGBE_IPSRXMODE_DEC 0x00000008 1658 #define TXGBE_IPSRXMODE_ESP 0x00000004 1659 #define TXGBE_IPSRXMODE_AH 0x00000002 1660 #define TXGBE_IPSRXMODE_VLD 0x00000001 1661 #define TXGBE_IPSTXIDX 0x01D100 1662 #define TXGBE_IPSTXIDX_ENA MS(0, 0x1) 1663 #define TXGBE_IPSTXIDX_SAIDX(v) LS(v, 3, 0x3FF) 1664 #define TXGBE_IPSTXIDX_READ MS(30, 0x1) 1665 #define TXGBE_IPSTXIDX_WRITE MS(31, 0x1) 1666 #define TXGBE_IPSTXSALT 0x01D104 1667 #define TXGBE_IPSTXKEY(i) (0x01D108 + (i) * 4) 1668 1669 #define TXGBE_MACTXCFG 0x011000 1670 #define TXGBE_MACTXCFG_TXE MS(0, 0x1) 1671 #define TXGBE_MACTXCFG_SPEED_MASK MS(29, 0x3) 1672 #define TXGBE_MACTXCFG_SPEED(v) LS(v, 29, 0x3) 1673 #define TXGBE_MACTXCFG_SPEED_10G LS(0, 29, 0x3) 1674 #define TXGBE_MACTXCFG_SPEED_1G LS(3, 29, 0x3) 1675 1676 #define TXGBE_ISBADDRL 0x000160 1677 #define TXGBE_ISBADDRH 0x000164 1678 1679 #define NVM_OROM_OFFSET 0x17 1680 #define NVM_OROM_BLK_LOW 0x83 1681 #define NVM_OROM_BLK_HI 0x84 1682 #define NVM_OROM_PATCH_MASK 0xFF 1683 #define NVM_OROM_SHIFT 8 1684 #define NVM_VER_MASK 0x00FF /* version mask */ 1685 #define NVM_VER_SHIFT 8 /* version bit shift */ 1686 #define NVM_OEM_PROD_VER_PTR 0x1B /* OEM Product version block pointer */ 1687 #define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */ 1688 #define NVM_OEM_PROD_VER_OFF_L 0x2 /* OEM Product version offset low */ 1689 #define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */ 1690 #define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */ 1691 #define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */ 1692 #define NVM_ETK_OFF_LOW 0x2D /* version low order word */ 1693 #define NVM_ETK_OFF_HI 0x2E /* version high order word */ 1694 #define NVM_ETK_SHIFT 16 /* high version word shift */ 1695 #define NVM_VER_INVALID 0xFFFF 1696 #define NVM_ETK_VALID 0x8000 1697 #define NVM_INVALID_PTR 0xFFFF 1698 #define NVM_VER_SIZE 32 /* version sting size */ 1699 1700 #define TXGBE_REG_RSSTBL TXGBE_RSSTBL(0) 1701 #define TXGBE_REG_RSSKEY TXGBE_RSSKEY(0) 1702 1703 static inline u32 1704 txgbe_map_reg(struct txgbe_hw *hw, u32 reg) 1705 { 1706 switch (reg) { 1707 case TXGBE_REG_RSSTBL: 1708 if (hw->mac.type == txgbe_mac_raptor_vf) 1709 reg = TXGBE_VFRSSTBL(0); 1710 break; 1711 case TXGBE_REG_RSSKEY: 1712 if (hw->mac.type == txgbe_mac_raptor_vf) 1713 reg = TXGBE_VFRSSKEY(0); 1714 break; 1715 default: 1716 /* you should never reach here */ 1717 reg = TXGBE_REG_DUMMY; 1718 break; 1719 } 1720 1721 return reg; 1722 } 1723 1724 /* 1725 * read non-rc counters 1726 */ 1727 #define TXGBE_UPDCNT32(reg, last, cur) \ 1728 do { \ 1729 uint32_t latest = rd32(hw, reg); \ 1730 if (hw->offset_loaded || hw->rx_loaded) \ 1731 last = 0; \ 1732 cur += (latest - last) & UINT_MAX; \ 1733 last = latest; \ 1734 } while (0) 1735 1736 #define TXGBE_UPDCNT36(regl, last, cur) \ 1737 do { \ 1738 uint64_t new_lsb = rd32(hw, regl); \ 1739 uint64_t new_msb = rd32(hw, regl + 4); \ 1740 uint64_t latest = ((new_msb << 32) | new_lsb); \ 1741 if (hw->offset_loaded || hw->rx_loaded) \ 1742 last = 0; \ 1743 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 1744 last = latest; \ 1745 } while (0) 1746 1747 /** 1748 * register operations 1749 **/ 1750 #define TXGBE_REG_READ32(addr) rte_read32(addr) 1751 #define TXGBE_REG_READ32_RELAXED(addr) rte_read32_relaxed(addr) 1752 #define TXGBE_REG_WRITE32(addr, val) rte_write32(val, addr) 1753 #define TXGBE_REG_WRITE32_RELAXED(addr, val) rte_write32_relaxed(val, addr) 1754 1755 #define TXGBE_DEAD_READ_REG 0xdeadbeefU 1756 #define TXGBE_FAILED_READ_REG 0xffffffffU 1757 #define TXGBE_REG_ADDR(hw, reg) \ 1758 ((volatile u32 *)((char *)(hw)->hw_addr + (reg))) 1759 1760 static inline u32 1761 txgbe_get32(volatile u32 *addr) 1762 { 1763 u32 val = TXGBE_REG_READ32(addr); 1764 return rte_le_to_cpu_32(val); 1765 } 1766 1767 static inline void 1768 txgbe_set32(volatile u32 *addr, u32 val) 1769 { 1770 val = rte_cpu_to_le_32(val); 1771 TXGBE_REG_WRITE32(addr, val); 1772 } 1773 1774 static inline u32 1775 txgbe_get32_masked(volatile u32 *addr, u32 mask) 1776 { 1777 u32 val = txgbe_get32(addr); 1778 val &= mask; 1779 return val; 1780 } 1781 1782 static inline void 1783 txgbe_set32_masked(volatile u32 *addr, u32 mask, u32 field) 1784 { 1785 u32 val = txgbe_get32(addr); 1786 val = ((val & ~mask) | (field & mask)); 1787 txgbe_set32(addr, val); 1788 } 1789 1790 static inline u32 1791 txgbe_get32_relaxed(volatile u32 *addr) 1792 { 1793 u32 val = TXGBE_REG_READ32_RELAXED(addr); 1794 return rte_le_to_cpu_32(val); 1795 } 1796 1797 static inline void 1798 txgbe_set32_relaxed(volatile u32 *addr, u32 val) 1799 { 1800 val = rte_cpu_to_le_32(val); 1801 TXGBE_REG_WRITE32_RELAXED(addr, val); 1802 } 1803 1804 static inline u32 1805 rd32(struct txgbe_hw *hw, u32 reg) 1806 { 1807 if (reg == TXGBE_REG_DUMMY) 1808 return 0; 1809 return txgbe_get32(TXGBE_REG_ADDR(hw, reg)); 1810 } 1811 1812 static inline void 1813 wr32(struct txgbe_hw *hw, u32 reg, u32 val) 1814 { 1815 if (reg == TXGBE_REG_DUMMY) 1816 return; 1817 txgbe_set32(TXGBE_REG_ADDR(hw, reg), val); 1818 } 1819 1820 static inline u32 1821 rd32m(struct txgbe_hw *hw, u32 reg, u32 mask) 1822 { 1823 u32 val = rd32(hw, reg); 1824 val &= mask; 1825 return val; 1826 } 1827 1828 static inline void 1829 wr32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 field) 1830 { 1831 u32 val = rd32(hw, reg); 1832 val = ((val & ~mask) | (field & mask)); 1833 wr32(hw, reg, val); 1834 } 1835 1836 static inline u64 1837 rd64(struct txgbe_hw *hw, u32 reg) 1838 { 1839 u64 lsb = rd32(hw, reg); 1840 u64 msb = rd32(hw, reg + 4); 1841 return (lsb | msb << 32); 1842 } 1843 1844 static inline void 1845 wr64(struct txgbe_hw *hw, u32 reg, u64 val) 1846 { 1847 wr32(hw, reg, (u32)val); 1848 wr32(hw, reg + 4, (u32)(val >> 32)); 1849 } 1850 1851 /* poll register */ 1852 static inline u32 1853 po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, 1854 u32 loop, u32 slice) 1855 { 1856 bool usec = true; 1857 u32 value = 0, all = 0; 1858 1859 if (slice > 1000 * MAX_UDELAY_MS) { 1860 usec = false; 1861 slice = (slice + 500) / 1000; 1862 } 1863 1864 do { 1865 all |= rd32(hw, reg); 1866 value |= mask & all; 1867 if (value == expect) 1868 break; 1869 1870 usec ? usec_delay(slice) : msec_delay(slice); 1871 } while (--loop > 0); 1872 1873 if (actual) 1874 *actual = all; 1875 1876 return loop; 1877 } 1878 1879 /* flush all write operations */ 1880 #define txgbe_flush(hw) rd32(hw, 0x00100C) 1881 1882 #define rd32a(hw, reg, idx) ( \ 1883 rd32((hw), (reg) + ((idx) << 2))) 1884 #define wr32a(hw, reg, idx, val) \ 1885 wr32((hw), (reg) + ((idx) << 2), (val)) 1886 1887 #define rd32at(hw, reg, idx) \ 1888 rd32a(hw, txgbe_map_reg(hw, reg), idx) 1889 #define wr32at(hw, reg, idx, val) \ 1890 wr32a(hw, txgbe_map_reg(hw, reg), idx, val) 1891 1892 #define rd32w(hw, reg, mask, slice) do { \ 1893 rd32((hw), reg); \ 1894 po32m((hw), reg, mask, mask, NULL, 5, slice); \ 1895 } while (0) 1896 1897 #define wr32w(hw, reg, val, mask, slice) do { \ 1898 wr32((hw), reg, val); \ 1899 po32m((hw), reg, mask, mask, NULL, 5, slice); \ 1900 } while (0) 1901 1902 #define TXGBE_XPCS_IDAADDR 0x13000 1903 #define TXGBE_XPCS_IDADATA 0x13004 1904 #define TXGBE_EPHY_IDAADDR 0x13008 1905 #define TXGBE_EPHY_IDADATA 0x1300C 1906 static inline u32 1907 rd32_epcs(struct txgbe_hw *hw, u32 addr) 1908 { 1909 u32 data; 1910 wr32(hw, TXGBE_XPCS_IDAADDR, addr); 1911 data = rd32(hw, TXGBE_XPCS_IDADATA); 1912 return data; 1913 } 1914 1915 static inline void 1916 wr32_epcs(struct txgbe_hw *hw, u32 addr, u32 data) 1917 { 1918 wr32(hw, TXGBE_XPCS_IDAADDR, addr); 1919 wr32(hw, TXGBE_XPCS_IDADATA, data); 1920 } 1921 1922 static inline u32 1923 rd32_ephy(struct txgbe_hw *hw, u32 addr) 1924 { 1925 u32 data; 1926 wr32(hw, TXGBE_EPHY_IDAADDR, addr); 1927 data = rd32(hw, TXGBE_EPHY_IDADATA); 1928 return data; 1929 } 1930 1931 static inline void 1932 wr32_ephy(struct txgbe_hw *hw, u32 addr, u32 data) 1933 { 1934 wr32(hw, TXGBE_EPHY_IDAADDR, addr); 1935 wr32(hw, TXGBE_EPHY_IDADATA, data); 1936 } 1937 1938 #endif /* _TXGBE_REGS_H_ */ 1939