1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #include "txgbe_type.h" 7 8 #include "txgbe_dcb.h" 9 10 /** 11 * txgbe_dcb_config_rx_arbiter_raptor - Config Rx Data arbiter 12 * @hw: pointer to hardware structure 13 * @refill: refill credits index by traffic class 14 * @max: max credits index by traffic class 15 * @bwg_id: bandwidth grouping indexed by traffic class 16 * @tsa: transmission selection algorithm indexed by traffic class 17 * @map: priority to tc assignments indexed by priority 18 * 19 * Configure Rx Packet Arbiter and credits for each traffic class. 20 */ 21 s32 txgbe_dcb_config_rx_arbiter_raptor(struct txgbe_hw *hw, u16 *refill, 22 u16 *max, u8 *bwg_id, u8 *tsa, 23 u8 *map) 24 { 25 u32 reg = 0; 26 u32 credit_refill = 0; 27 u32 credit_max = 0; 28 u8 i = 0; 29 30 /* 31 * Disable the arbiter before changing parameters 32 * (always enable recycle mode; WSP) 33 */ 34 reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP | 35 TXGBE_ARBRXCTL_DIA; 36 wr32(hw, TXGBE_ARBRXCTL, reg); 37 38 /* 39 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding 40 * bits sets for the UPs that needs to be mappped to that TC. 41 * e.g if priorities 6 and 7 are to be mapped to a TC then the 42 * up_to_tc_bitmap value for that TC will be 11000000 in binary. 43 */ 44 reg = 0; 45 for (i = 0; i < TXGBE_DCB_UP_MAX; i++) 46 reg |= (map[i] << (i * TXGBE_RPUP2TC_UP_SHIFT)); 47 48 wr32(hw, TXGBE_RPUP2TC, reg); 49 50 /* Configure traffic class credits and priority */ 51 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 52 credit_refill = refill[i]; 53 credit_max = max[i]; 54 reg = TXGBE_QARBRXCFG_CRQ(credit_refill) | 55 TXGBE_QARBRXCFG_MCL(credit_max) | 56 TXGBE_QARBRXCFG_BWG(bwg_id[i]); 57 58 if (tsa[i] == txgbe_dcb_tsa_strict) 59 reg |= TXGBE_QARBRXCFG_LSP; 60 61 wr32(hw, TXGBE_QARBRXCFG(i), reg); 62 } 63 64 /* 65 * Configure Rx packet plane (recycle mode; WSP) and 66 * enable arbiter 67 */ 68 reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP; 69 wr32(hw, TXGBE_ARBRXCTL, reg); 70 71 return 0; 72 } 73 74 /** 75 * txgbe_dcb_config_tx_desc_arbiter_raptor - Config Tx Desc. arbiter 76 * @hw: pointer to hardware structure 77 * @refill: refill credits index by traffic class 78 * @max: max credits index by traffic class 79 * @bwg_id: bandwidth grouping indexed by traffic class 80 * @tsa: transmission selection algorithm indexed by traffic class 81 * 82 * Configure Tx Descriptor Arbiter and credits for each traffic class. 83 */ 84 s32 txgbe_dcb_config_tx_desc_arbiter_raptor(struct txgbe_hw *hw, u16 *refill, 85 u16 *max, u8 *bwg_id, u8 *tsa) 86 { 87 u32 reg, max_credits; 88 u8 i; 89 90 /* Clear the per-Tx queue credits; we use per-TC instead */ 91 for (i = 0; i < 128; i++) 92 wr32(hw, TXGBE_QARBTXCRED(i), 0); 93 94 /* Configure traffic class credits and priority */ 95 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 96 max_credits = max[i]; 97 reg = TXGBE_QARBTXCFG_MCL(max_credits) | 98 TXGBE_QARBTXCFG_CRQ(refill[i]) | 99 TXGBE_QARBTXCFG_BWG(bwg_id[i]); 100 101 if (tsa[i] == txgbe_dcb_tsa_group_strict_cee) 102 reg |= TXGBE_QARBTXCFG_GSP; 103 104 if (tsa[i] == txgbe_dcb_tsa_strict) 105 reg |= TXGBE_QARBTXCFG_LSP; 106 107 wr32(hw, TXGBE_QARBTXCFG(i), reg); 108 } 109 110 /* 111 * Configure Tx descriptor plane (recycle mode; WSP) and 112 * enable arbiter 113 */ 114 reg = TXGBE_ARBTXCTL_WSP | TXGBE_ARBTXCTL_RRM; 115 wr32(hw, TXGBE_ARBTXCTL, reg); 116 117 return 0; 118 } 119 120 /** 121 * txgbe_dcb_config_tx_data_arbiter_raptor - Config Tx Data arbiter 122 * @hw: pointer to hardware structure 123 * @refill: refill credits index by traffic class 124 * @max: max credits index by traffic class 125 * @bwg_id: bandwidth grouping indexed by traffic class 126 * @tsa: transmission selection algorithm indexed by traffic class 127 * @map: priority to tc assignments indexed by priority 128 * 129 * Configure Tx Packet Arbiter and credits for each traffic class. 130 */ 131 s32 txgbe_dcb_config_tx_data_arbiter_raptor(struct txgbe_hw *hw, u16 *refill, 132 u16 *max, u8 *bwg_id, u8 *tsa, 133 u8 *map) 134 { 135 u32 reg; 136 u8 i; 137 138 /* 139 * Disable the arbiter before changing parameters 140 * (always enable recycle mode; SP; arb delay) 141 */ 142 reg = TXGBE_PARBTXCTL_SP | 143 TXGBE_PARBTXCTL_RECYC | 144 TXGBE_PARBTXCTL_DA; 145 wr32(hw, TXGBE_PARBTXCTL, reg); 146 147 /* 148 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding 149 * bits sets for the UPs that needs to be mappped to that TC. 150 * e.g if priorities 6 and 7 are to be mapped to a TC then the 151 * up_to_tc_bitmap value for that TC will be 11000000 in binary. 152 */ 153 reg = 0; 154 for (i = 0; i < TXGBE_DCB_UP_MAX; i++) 155 reg |= TXGBE_DCBUP2TC_MAP(i, map[i]); 156 157 wr32(hw, TXGBE_PBRXUP2TC, reg); 158 159 /* Configure traffic class credits and priority */ 160 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) { 161 reg = TXGBE_PARBTXCFG_CRQ(refill[i]) | 162 TXGBE_PARBTXCFG_MCL(max[i]) | 163 TXGBE_PARBTXCFG_BWG(bwg_id[i]); 164 165 if (tsa[i] == txgbe_dcb_tsa_group_strict_cee) 166 reg |= TXGBE_PARBTXCFG_GSP; 167 168 if (tsa[i] == txgbe_dcb_tsa_strict) 169 reg |= TXGBE_PARBTXCFG_LSP; 170 171 wr32(hw, TXGBE_PARBTXCFG(i), reg); 172 } 173 174 /* 175 * Configure Tx packet plane (recycle mode; SP; arb delay) and 176 * enable arbiter 177 */ 178 reg = TXGBE_PARBTXCTL_SP | TXGBE_PARBTXCTL_RECYC; 179 wr32(hw, TXGBE_PARBTXCTL, reg); 180 181 return 0; 182 } 183 184 /** 185 * txgbe_dcb_config_pfc_raptor - Configure priority flow control 186 * @hw: pointer to hardware structure 187 * @pfc_en: enabled pfc bitmask 188 * @map: priority to tc assignments indexed by priority 189 * 190 * Configure Priority Flow Control (PFC) for each traffic class. 191 */ 192 s32 txgbe_dcb_config_pfc_raptor(struct txgbe_hw *hw, u8 pfc_en, u8 *map) 193 { 194 u32 i, j, fcrtl, reg; 195 u8 max_tc = 0; 196 197 /* Enable Transmit Priority Flow Control */ 198 wr32(hw, TXGBE_TXFCCFG, TXGBE_TXFCCFG_PFC); 199 200 /* Enable Receive Priority Flow Control */ 201 wr32m(hw, TXGBE_RXFCCFG, TXGBE_RXFCCFG_PFC, 202 pfc_en ? TXGBE_RXFCCFG_PFC : 0); 203 204 for (i = 0; i < TXGBE_DCB_UP_MAX; i++) { 205 if (map[i] > max_tc) 206 max_tc = map[i]; 207 } 208 209 /* Configure PFC Tx thresholds per TC */ 210 for (i = 0; i <= max_tc; i++) { 211 int enabled = 0; 212 213 for (j = 0; j < TXGBE_DCB_UP_MAX; j++) { 214 if (map[j] == i && (pfc_en & (1 << j))) { 215 enabled = 1; 216 break; 217 } 218 } 219 220 if (enabled) { 221 reg = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) | 222 TXGBE_FCWTRHI_XOFF; 223 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) | 224 TXGBE_FCWTRLO_XON; 225 wr32(hw, TXGBE_FCWTRLO(i), fcrtl); 226 } else { 227 /* 228 * In order to prevent Tx hangs when the internal Tx 229 * switch is enabled we must set the high water mark 230 * to the Rx packet buffer size - 24KB. This allows 231 * the Tx switch to function even under heavy Rx 232 * workloads. 233 */ 234 reg = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576; 235 wr32(hw, TXGBE_FCWTRLO(i), 0); 236 } 237 238 wr32(hw, TXGBE_FCWTRHI(i), reg); 239 } 240 241 for (; i < TXGBE_DCB_TC_MAX; i++) { 242 wr32(hw, TXGBE_FCWTRLO(i), 0); 243 wr32(hw, TXGBE_FCWTRHI(i), 0); 244 } 245 246 /* Configure pause time (2 TCs per register) */ 247 reg = hw->fc.pause_time | (hw->fc.pause_time << 16); 248 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++) 249 wr32(hw, TXGBE_FCXOFFTM(i), reg); 250 251 /* Configure flow control refresh threshold value */ 252 wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2); 253 254 return 0; 255 } 256 257 /** 258 * txgbe_dcb_config_tc_stats_raptor - Config traffic class statistics 259 * @hw: pointer to hardware structure 260 * @dcb_config: pointer to txgbe_dcb_config structure 261 * 262 * Configure queue statistics registers, all queues belonging to same traffic 263 * class uses a single set of queue statistics counters. 264 */ 265 s32 txgbe_dcb_config_tc_stats_raptor(struct txgbe_hw *hw, 266 struct txgbe_dcb_config *dcb_config) 267 { 268 u8 tc_count = 8; 269 bool vt_mode = false; 270 271 UNREFERENCED_PARAMETER(hw); 272 273 if (dcb_config != NULL) { 274 tc_count = dcb_config->num_tcs.pg_tcs; 275 vt_mode = dcb_config->vt_mode; 276 } 277 278 if (!((tc_count == 8 && !vt_mode) || tc_count == 4)) 279 return TXGBE_ERR_PARAM; 280 281 return 0; 282 } 283 284