1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 8 #ifndef _QEDE_ETHDEV_H_ 9 #define _QEDE_ETHDEV_H_ 10 11 #include <sys/queue.h> 12 13 #include <rte_ether.h> 14 #include <rte_ethdev_driver.h> 15 #include <rte_ethdev_pci.h> 16 #include <rte_dev.h> 17 #include <rte_ip.h> 18 19 /* ecore includes */ 20 #include "base/bcm_osal.h" 21 #include "base/ecore.h" 22 #include "base/ecore_dev_api.h" 23 #include "base/ecore_l2_api.h" 24 #include "base/ecore_vf_api.h" 25 #include "base/ecore_hsi_common.h" 26 #include "base/ecore_int_api.h" 27 #include "base/ecore_chain.h" 28 #include "base/ecore_status.h" 29 #include "base/ecore_hsi_eth.h" 30 #include "base/ecore_iov_api.h" 31 #include "base/ecore_cxt.h" 32 #include "base/nvm_cfg.h" 33 #include "base/ecore_sp_commands.h" 34 #include "base/ecore_l2.h" 35 #include "base/ecore_vf.h" 36 37 #include "qede_logs.h" 38 #include "qede_if.h" 39 #include "qede_rxtx.h" 40 41 #define qede_stringify1(x...) #x 42 #define qede_stringify(x...) qede_stringify1(x) 43 44 /* Driver versions */ 45 #define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE /* 128 */ 46 #define QEDE_PMD_VER_PREFIX "QEDE PMD" 47 #define QEDE_PMD_VERSION_MAJOR 2 48 #define QEDE_PMD_VERSION_MINOR 11 49 #define QEDE_PMD_VERSION_REVISION 3 50 #define QEDE_PMD_VERSION_PATCH 1 51 52 #define QEDE_PMD_DRV_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "." \ 53 qede_stringify(QEDE_PMD_VERSION_MINOR) "." \ 54 qede_stringify(QEDE_PMD_VERSION_REVISION) "." \ 55 qede_stringify(QEDE_PMD_VERSION_PATCH) 56 57 #define QEDE_PMD_BASE_VERSION qede_stringify(ECORE_MAJOR_VERSION) "." \ 58 qede_stringify(ECORE_MINOR_VERSION) "." \ 59 qede_stringify(ECORE_REVISION_VERSION) "." \ 60 qede_stringify(ECORE_ENGINEERING_VERSION) 61 62 #define QEDE_PMD_FW_VERSION qede_stringify(FW_MAJOR_VERSION) "." \ 63 qede_stringify(FW_MINOR_VERSION) "." \ 64 qede_stringify(FW_REVISION_VERSION) "." \ 65 qede_stringify(FW_ENGINEERING_VERSION) 66 67 #define QEDE_RSS_INDIR_INITED (1 << 0) 68 #define QEDE_RSS_KEY_INITED (1 << 1) 69 #define QEDE_RSS_CAPS_INITED (1 << 2) 70 71 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues) 72 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \ 73 (edev)->dev_info.num_tc) 74 75 #define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues) 76 #define QEDE_RSS_COUNT(dev) ((dev)->data->nb_rx_queues) 77 #define QEDE_TSS_COUNT(dev) ((dev)->data->nb_tx_queues) 78 79 #define QEDE_DUPLEX_FULL 1 80 #define QEDE_DUPLEX_HALF 2 81 #define QEDE_DUPLEX_UNKNOWN 0xff 82 83 #define QEDE_SUPPORTED_AUTONEG (1 << 6) 84 #define QEDE_SUPPORTED_PAUSE (1 << 13) 85 86 #define QEDE_INIT_QDEV(eth_dev) (eth_dev->data->dev_private) 87 88 #define QEDE_INIT_EDEV(adapter) (&((struct qede_dev *)adapter)->edev) 89 90 #define QEDE_INIT(eth_dev) { \ 91 struct qede_dev *qdev = eth_dev->data->dev_private; \ 92 struct ecore_dev *edev = &qdev->edev; \ 93 } 94 95 /************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/ 96 #define PCI_VENDOR_ID_QLOGIC 0x1077 97 98 #define CHIP_NUM_57980E 0x1634 99 #define CHIP_NUM_57980S 0x1629 100 #define CHIP_NUM_VF 0x1630 101 #define CHIP_NUM_57980S_40 0x1634 102 #define CHIP_NUM_57980S_25 0x1656 103 #define CHIP_NUM_57980S_IOV 0x1664 104 #define CHIP_NUM_57980S_100 0x1644 105 #define CHIP_NUM_57980S_50 0x1654 106 #define CHIP_NUM_AH_50G 0x8070 107 #define CHIP_NUM_AH_10G 0x8071 108 #define CHIP_NUM_AH_40G 0x8072 109 #define CHIP_NUM_AH_25G 0x8073 110 #define CHIP_NUM_AH_IOV 0x8090 111 112 #define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E 113 #define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S 114 #define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF 115 #define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40 116 #define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25 117 #define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV 118 #define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100 119 #define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50 120 #define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G 121 #define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G 122 #define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G 123 #define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G 124 #define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV 125 126 127 128 extern char qede_fw_file[]; 129 130 /* Number of PF connections - 32 RX + 32 TX */ 131 #define QEDE_PF_NUM_CONNS (64) 132 133 /* Maximum number of flowdir filters */ 134 #define QEDE_RFS_MAX_FLTR (256) 135 136 #define QEDE_MAX_MCAST_FILTERS (64) 137 138 enum qed_filter_rx_mode_type { 139 QED_FILTER_RX_MODE_TYPE_REGULAR, 140 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC, 141 QED_FILTER_RX_MODE_TYPE_PROMISC, 142 }; 143 144 struct qede_vlan_entry { 145 SLIST_ENTRY(qede_vlan_entry) list; 146 uint16_t vid; 147 }; 148 149 struct qede_mcast_entry { 150 struct rte_ether_addr mac; 151 SLIST_ENTRY(qede_mcast_entry) list; 152 }; 153 154 struct qede_ucast_entry { 155 struct rte_ether_addr mac; 156 uint16_t vlan; 157 uint16_t vni; 158 SLIST_ENTRY(qede_ucast_entry) list; 159 }; 160 161 #ifndef IPV6_ADDR_LEN 162 #define IPV6_ADDR_LEN (16) 163 #endif 164 165 struct qede_arfs_tuple { 166 union { 167 uint32_t src_ipv4; 168 uint8_t src_ipv6[IPV6_ADDR_LEN]; 169 }; 170 171 union { 172 uint32_t dst_ipv4; 173 uint8_t dst_ipv6[IPV6_ADDR_LEN]; 174 }; 175 176 uint16_t src_port; 177 uint16_t dst_port; 178 uint16_t eth_proto; 179 uint8_t ip_proto; 180 181 /* Describe filtering mode needed for this kind of filter */ 182 enum ecore_filter_config_mode mode; 183 }; 184 185 struct qede_arfs_entry { 186 uint32_t soft_id; /* unused for now */ 187 uint16_t pkt_len; /* actual packet length to match */ 188 uint16_t rx_queue; /* queue to be steered to */ 189 bool is_drop; /* drop action */ 190 const struct rte_memzone *mz; /* mz used to hold L2 frame */ 191 struct qede_arfs_tuple tuple; 192 SLIST_ENTRY(qede_arfs_entry) list; 193 }; 194 195 /* Opaque handle for rte flow managed by PMD */ 196 struct rte_flow { 197 struct qede_arfs_entry entry; 198 }; 199 200 struct qede_arfs_info { 201 struct ecore_arfs_config_params arfs; 202 uint16_t filter_count; 203 SLIST_HEAD(arfs_list_head, qede_arfs_entry)arfs_list_head; 204 }; 205 206 /* IANA assigned default UDP ports for encapsulation protocols */ 207 #define QEDE_VXLAN_DEF_PORT (4789) 208 #define QEDE_GENEVE_DEF_PORT (6081) 209 210 struct qede_tunn_params { 211 bool enable; 212 uint16_t num_filters; 213 uint16_t filter_type; 214 uint16_t udp_port; 215 }; 216 217 #define QEDE_FW_DUMP_FILE_SIZE 128 218 219 /* 220 * Structure to store private data for each port. 221 */ 222 struct qede_dev { 223 struct ecore_dev edev; 224 const struct qed_eth_ops *ops; 225 struct qed_dev_eth_info dev_info; 226 struct ecore_sb_info *sb_array; 227 struct qede_fastpath *fp_array; 228 struct qede_fastpath_cmt *fp_array_cmt; 229 uint16_t mtu; 230 uint16_t new_mtu; 231 bool enable_tx_switching; 232 bool rss_enable; 233 struct rte_eth_rss_conf rss_conf; 234 uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE]; 235 uint64_t rss_hf; 236 uint8_t rss_key_len; 237 bool enable_lro; 238 uint8_t num_rx_queues; 239 uint8_t num_tx_queues; 240 SLIST_HEAD(vlan_list_head, qede_vlan_entry)vlan_list_head; 241 uint16_t configured_vlans; 242 bool accept_any_vlan; 243 struct rte_ether_addr primary_mac; 244 SLIST_HEAD(mc_list_head, qede_mcast_entry) mc_list_head; 245 uint16_t num_mc_addr; 246 SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head; 247 uint16_t num_uc_addr; 248 bool handle_hw_err; 249 struct qede_tunn_params vxlan; 250 struct qede_tunn_params geneve; 251 struct qede_tunn_params ipgre; 252 struct qede_arfs_info arfs_info; 253 bool vlan_strip_flg; 254 char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 255 bool vport_started; 256 int vlan_offload_mask; 257 char dump_file[QEDE_FW_DUMP_FILE_SIZE]; 258 void *ethdev; 259 }; 260 261 static inline void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast) 262 { 263 memset(ucast, 0, sizeof(struct ecore_filter_ucast)); 264 ucast->is_rx_filter = true; 265 ucast->is_tx_filter = true; 266 /* ucast->assert_on_error = true; - For debug */ 267 } 268 269 270 /* Non-static functions */ 271 int qede_config_rss(struct rte_eth_dev *eth_dev); 272 273 int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 274 struct rte_eth_rss_conf *rss_conf); 275 276 int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 277 struct rte_eth_rss_reta_entry64 *reta_conf, 278 uint16_t reta_size); 279 280 int qed_fill_eth_dev_info(struct ecore_dev *edev, 281 struct qed_dev_eth_info *info); 282 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up); 283 284 int qede_link_update(struct rte_eth_dev *eth_dev, 285 __rte_unused int wait_to_complete); 286 287 int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type, 288 enum rte_filter_op op, void *arg); 289 290 int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev, 291 enum rte_filter_op filter_op, void *arg); 292 293 int qede_check_fdir_support(struct rte_eth_dev *eth_dev); 294 295 uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev, 296 struct rte_eth_fdir_filter *fdir, 297 void *buff, 298 struct ecore_arfs_config_params *params); 299 300 void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev); 301 302 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg); 303 304 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu); 305 306 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg); 307 int qede_udp_dst_port_del(struct rte_eth_dev *eth_dev, 308 struct rte_eth_udp_tunnel *tunnel_udp); 309 int qede_udp_dst_port_add(struct rte_eth_dev *eth_dev, 310 struct rte_eth_udp_tunnel *tunnel_udp); 311 312 enum _ecore_status_t 313 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 314 bool add); 315 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg); 316 int qede_ucast_filter(struct rte_eth_dev *eth_dev, 317 struct ecore_filter_ucast *ucast, 318 bool add); 319 320 #define REGDUMP_HEADER_SIZE sizeof(u32) 321 #define REGDUMP_HEADER_FEATURE_SHIFT 24 322 #define REGDUMP_HEADER_ENGINE_SHIFT 31 323 #define REGDUMP_HEADER_OMIT_ENGINE_SHIFT 30 324 325 enum debug_print_features { 326 OLD_MODE = 0, 327 IDLE_CHK = 1, 328 GRC_DUMP = 2, 329 MCP_TRACE = 3, 330 REG_FIFO = 4, 331 PROTECTION_OVERRIDE = 5, 332 IGU_FIFO = 6, 333 PHY = 7, 334 FW_ASSERTS = 8, 335 }; 336 337 int qede_get_regs_len(struct qede_dev *qdev); 338 int qede_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs); 339 void qede_config_rx_mode(struct rte_eth_dev *eth_dev); 340 void qed_dbg_dump(struct rte_eth_dev *eth_dev); 341 #endif /* _QEDE_ETHDEV_H_ */ 342