1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #include "qede_ethdev.h" 8 #include <rte_string_fns.h> 9 #include <rte_alarm.h> 10 #include <rte_version.h> 11 #include <rte_kvargs.h> 12 13 /* Globals */ 14 int qede_logtype_init; 15 int qede_logtype_driver; 16 17 static const struct qed_eth_ops *qed_ops; 18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev); 19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev); 20 21 #define QEDE_SP_TIMER_PERIOD 10000 /* 100ms */ 22 23 struct rte_qede_xstats_name_off { 24 char name[RTE_ETH_XSTATS_NAME_SIZE]; 25 uint64_t offset; 26 }; 27 28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 29 {"rx_unicast_bytes", 30 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)}, 31 {"rx_multicast_bytes", 32 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)}, 33 {"rx_broadcast_bytes", 34 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)}, 35 {"rx_unicast_packets", 36 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)}, 37 {"rx_multicast_packets", 38 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)}, 39 {"rx_broadcast_packets", 40 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)}, 41 42 {"tx_unicast_bytes", 43 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)}, 44 {"tx_multicast_bytes", 45 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)}, 46 {"tx_broadcast_bytes", 47 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)}, 48 {"tx_unicast_packets", 49 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)}, 50 {"tx_multicast_packets", 51 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)}, 52 {"tx_broadcast_packets", 53 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)}, 54 55 {"rx_64_byte_packets", 56 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)}, 57 {"rx_65_to_127_byte_packets", 58 offsetof(struct ecore_eth_stats_common, 59 rx_65_to_127_byte_packets)}, 60 {"rx_128_to_255_byte_packets", 61 offsetof(struct ecore_eth_stats_common, 62 rx_128_to_255_byte_packets)}, 63 {"rx_256_to_511_byte_packets", 64 offsetof(struct ecore_eth_stats_common, 65 rx_256_to_511_byte_packets)}, 66 {"rx_512_to_1023_byte_packets", 67 offsetof(struct ecore_eth_stats_common, 68 rx_512_to_1023_byte_packets)}, 69 {"rx_1024_to_1518_byte_packets", 70 offsetof(struct ecore_eth_stats_common, 71 rx_1024_to_1518_byte_packets)}, 72 {"tx_64_byte_packets", 73 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)}, 74 {"tx_65_to_127_byte_packets", 75 offsetof(struct ecore_eth_stats_common, 76 tx_65_to_127_byte_packets)}, 77 {"tx_128_to_255_byte_packets", 78 offsetof(struct ecore_eth_stats_common, 79 tx_128_to_255_byte_packets)}, 80 {"tx_256_to_511_byte_packets", 81 offsetof(struct ecore_eth_stats_common, 82 tx_256_to_511_byte_packets)}, 83 {"tx_512_to_1023_byte_packets", 84 offsetof(struct ecore_eth_stats_common, 85 tx_512_to_1023_byte_packets)}, 86 {"tx_1024_to_1518_byte_packets", 87 offsetof(struct ecore_eth_stats_common, 88 tx_1024_to_1518_byte_packets)}, 89 90 {"rx_mac_crtl_frames", 91 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)}, 92 {"tx_mac_control_frames", 93 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)}, 94 {"rx_pause_frames", 95 offsetof(struct ecore_eth_stats_common, rx_pause_frames)}, 96 {"tx_pause_frames", 97 offsetof(struct ecore_eth_stats_common, tx_pause_frames)}, 98 {"rx_priority_flow_control_frames", 99 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)}, 100 {"tx_priority_flow_control_frames", 101 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)}, 102 103 {"rx_crc_errors", 104 offsetof(struct ecore_eth_stats_common, rx_crc_errors)}, 105 {"rx_align_errors", 106 offsetof(struct ecore_eth_stats_common, rx_align_errors)}, 107 {"rx_carrier_errors", 108 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)}, 109 {"rx_oversize_packet_errors", 110 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)}, 111 {"rx_jabber_errors", 112 offsetof(struct ecore_eth_stats_common, rx_jabbers)}, 113 {"rx_undersize_packet_errors", 114 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)}, 115 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)}, 116 {"rx_host_buffer_not_available", 117 offsetof(struct ecore_eth_stats_common, no_buff_discards)}, 118 /* Number of packets discarded because they are bigger than MTU */ 119 {"rx_packet_too_big_discards", 120 offsetof(struct ecore_eth_stats_common, 121 packet_too_big_discard)}, 122 {"rx_ttl_zero_discards", 123 offsetof(struct ecore_eth_stats_common, ttl0_discard)}, 124 {"rx_multi_function_tag_filter_discards", 125 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)}, 126 {"rx_mac_filter_discards", 127 offsetof(struct ecore_eth_stats_common, mac_filter_discards)}, 128 {"rx_gft_filter_drop", 129 offsetof(struct ecore_eth_stats_common, gft_filter_drop)}, 130 {"rx_hw_buffer_truncates", 131 offsetof(struct ecore_eth_stats_common, brb_truncates)}, 132 {"rx_hw_buffer_discards", 133 offsetof(struct ecore_eth_stats_common, brb_discards)}, 134 {"tx_error_drop_packets", 135 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)}, 136 137 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)}, 138 {"rx_mac_unicast_packets", 139 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)}, 140 {"rx_mac_multicast_packets", 141 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)}, 142 {"rx_mac_broadcast_packets", 143 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)}, 144 {"rx_mac_frames_ok", 145 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)}, 146 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)}, 147 {"tx_mac_unicast_packets", 148 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)}, 149 {"tx_mac_multicast_packets", 150 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)}, 151 {"tx_mac_broadcast_packets", 152 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)}, 153 154 {"lro_coalesced_packets", 155 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)}, 156 {"lro_coalesced_events", 157 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)}, 158 {"lro_aborts_num", 159 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)}, 160 {"lro_not_coalesced_packets", 161 offsetof(struct ecore_eth_stats_common, 162 tpa_not_coalesced_pkts)}, 163 {"lro_coalesced_bytes", 164 offsetof(struct ecore_eth_stats_common, 165 tpa_coalesced_bytes)}, 166 }; 167 168 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = { 169 {"rx_1519_to_1522_byte_packets", 170 offsetof(struct ecore_eth_stats, bb) + 171 offsetof(struct ecore_eth_stats_bb, 172 rx_1519_to_1522_byte_packets)}, 173 {"rx_1519_to_2047_byte_packets", 174 offsetof(struct ecore_eth_stats, bb) + 175 offsetof(struct ecore_eth_stats_bb, 176 rx_1519_to_2047_byte_packets)}, 177 {"rx_2048_to_4095_byte_packets", 178 offsetof(struct ecore_eth_stats, bb) + 179 offsetof(struct ecore_eth_stats_bb, 180 rx_2048_to_4095_byte_packets)}, 181 {"rx_4096_to_9216_byte_packets", 182 offsetof(struct ecore_eth_stats, bb) + 183 offsetof(struct ecore_eth_stats_bb, 184 rx_4096_to_9216_byte_packets)}, 185 {"rx_9217_to_16383_byte_packets", 186 offsetof(struct ecore_eth_stats, bb) + 187 offsetof(struct ecore_eth_stats_bb, 188 rx_9217_to_16383_byte_packets)}, 189 190 {"tx_1519_to_2047_byte_packets", 191 offsetof(struct ecore_eth_stats, bb) + 192 offsetof(struct ecore_eth_stats_bb, 193 tx_1519_to_2047_byte_packets)}, 194 {"tx_2048_to_4095_byte_packets", 195 offsetof(struct ecore_eth_stats, bb) + 196 offsetof(struct ecore_eth_stats_bb, 197 tx_2048_to_4095_byte_packets)}, 198 {"tx_4096_to_9216_byte_packets", 199 offsetof(struct ecore_eth_stats, bb) + 200 offsetof(struct ecore_eth_stats_bb, 201 tx_4096_to_9216_byte_packets)}, 202 {"tx_9217_to_16383_byte_packets", 203 offsetof(struct ecore_eth_stats, bb) + 204 offsetof(struct ecore_eth_stats_bb, 205 tx_9217_to_16383_byte_packets)}, 206 207 {"tx_lpi_entry_count", 208 offsetof(struct ecore_eth_stats, bb) + 209 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)}, 210 {"tx_total_collisions", 211 offsetof(struct ecore_eth_stats, bb) + 212 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)}, 213 }; 214 215 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = { 216 {"rx_1519_to_max_byte_packets", 217 offsetof(struct ecore_eth_stats, ah) + 218 offsetof(struct ecore_eth_stats_ah, 219 rx_1519_to_max_byte_packets)}, 220 {"tx_1519_to_max_byte_packets", 221 offsetof(struct ecore_eth_stats, ah) + 222 offsetof(struct ecore_eth_stats_ah, 223 tx_1519_to_max_byte_packets)}, 224 }; 225 226 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 227 {"rx_q_segments", 228 offsetof(struct qede_rx_queue, rx_segs)}, 229 {"rx_q_hw_errors", 230 offsetof(struct qede_rx_queue, rx_hw_errors)}, 231 {"rx_q_allocation_errors", 232 offsetof(struct qede_rx_queue, rx_alloc_errors)} 233 }; 234 235 /* Get FW version string based on fw_size */ 236 static int 237 qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size) 238 { 239 struct qede_dev *qdev = dev->data->dev_private; 240 struct ecore_dev *edev = &qdev->edev; 241 struct qed_dev_info *info = &qdev->dev_info.common; 242 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 243 size_t size; 244 245 if (fw_ver == NULL) 246 return 0; 247 248 if (IS_PF(edev)) 249 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s", 250 QEDE_PMD_FW_VERSION); 251 else 252 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 253 info->fw_major, info->fw_minor, 254 info->fw_rev, info->fw_eng); 255 size = strlen(ver_str); 256 if (size + 1 <= fw_size) /* Add 1 byte for "\0" */ 257 strlcpy(fw_ver, ver_str, fw_size); 258 else 259 return (size + 1); 260 261 snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size), 262 " MFW: %d.%d.%d.%d", 263 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_3), 264 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_2), 265 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_1), 266 GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_0)); 267 size = strlen(ver_str); 268 if (size + 1 <= fw_size) 269 strlcpy(fw_ver, ver_str, fw_size); 270 271 if (fw_size <= 32) 272 goto out; 273 274 snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size), 275 " MBI: %d.%d.%d", 276 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_2), 277 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_1), 278 GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_0)); 279 size = strlen(ver_str); 280 if (size + 1 <= fw_size) 281 strlcpy(fw_ver, ver_str, fw_size); 282 283 out: 284 return 0; 285 } 286 287 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 288 { 289 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 290 } 291 292 static void 293 qede_interrupt_handler_intx(void *param) 294 { 295 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 296 struct qede_dev *qdev = eth_dev->data->dev_private; 297 struct ecore_dev *edev = &qdev->edev; 298 u64 status; 299 300 /* Check if our device actually raised an interrupt */ 301 status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev)); 302 if (status & 0x1) { 303 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 304 305 if (rte_intr_ack(eth_dev->intr_handle)) 306 DP_ERR(edev, "rte_intr_ack failed\n"); 307 } 308 } 309 310 static void 311 qede_interrupt_handler(void *param) 312 { 313 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 314 struct qede_dev *qdev = eth_dev->data->dev_private; 315 struct ecore_dev *edev = &qdev->edev; 316 317 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 318 if (rte_intr_ack(eth_dev->intr_handle)) 319 DP_ERR(edev, "rte_intr_ack failed\n"); 320 } 321 322 static void 323 qede_assign_rxtx_handlers(struct rte_eth_dev *dev, bool is_dummy) 324 { 325 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads; 326 struct qede_dev *qdev = dev->data->dev_private; 327 struct ecore_dev *edev = &qdev->edev; 328 bool use_tx_offload = false; 329 330 if (is_dummy) { 331 dev->rx_pkt_burst = qede_rxtx_pkts_dummy; 332 dev->tx_pkt_burst = qede_rxtx_pkts_dummy; 333 return; 334 } 335 336 if (ECORE_IS_CMT(edev)) { 337 dev->rx_pkt_burst = qede_recv_pkts_cmt; 338 dev->tx_pkt_burst = qede_xmit_pkts_cmt; 339 return; 340 } 341 342 if (dev->data->lro || dev->data->scattered_rx) { 343 DP_INFO(edev, "Assigning qede_recv_pkts\n"); 344 dev->rx_pkt_burst = qede_recv_pkts; 345 } else { 346 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n"); 347 dev->rx_pkt_burst = qede_recv_pkts_regular; 348 } 349 350 use_tx_offload = !!(tx_offloads & 351 (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */ 352 DEV_TX_OFFLOAD_TCP_TSO | /* tso */ 353 DEV_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */ 354 355 if (use_tx_offload) { 356 DP_INFO(edev, "Assigning qede_xmit_pkts\n"); 357 dev->tx_pkt_burst = qede_xmit_pkts; 358 } else { 359 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n"); 360 dev->tx_pkt_burst = qede_xmit_pkts_regular; 361 } 362 } 363 364 static void 365 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 366 { 367 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 368 qdev->ops = qed_ops; 369 } 370 371 static void qede_print_adapter_info(struct rte_eth_dev *dev) 372 { 373 struct qede_dev *qdev = dev->data->dev_private; 374 struct ecore_dev *edev = &qdev->edev; 375 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 376 377 DP_INFO(edev, "**************************************************\n"); 378 DP_INFO(edev, " %-20s: %s\n", "DPDK version", rte_version()); 379 DP_INFO(edev, " %-20s: %s %c%d\n", "Chip details", 380 ECORE_IS_BB(edev) ? "BB" : "AH", 381 'A' + edev->chip_rev, 382 (int)edev->chip_metal); 383 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s", 384 QEDE_PMD_DRV_VERSION); 385 DP_INFO(edev, " %-20s: %s\n", "Driver version", ver_str); 386 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s", 387 QEDE_PMD_BASE_VERSION); 388 DP_INFO(edev, " %-20s: %s\n", "Base version", ver_str); 389 qede_fw_version_get(dev, ver_str, sizeof(ver_str)); 390 DP_INFO(edev, " %-20s: %s\n", "Firmware version", ver_str); 391 DP_INFO(edev, " %-20s: %s\n", "Firmware file", qede_fw_file); 392 DP_INFO(edev, "**************************************************\n"); 393 } 394 395 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats) 396 { 397 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev; 398 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 399 unsigned int i = 0, j = 0, qid; 400 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 401 struct qede_tx_queue *txq; 402 403 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n"); 404 405 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev), 406 RTE_ETHDEV_QUEUE_STAT_CNTRS); 407 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev), 408 RTE_ETHDEV_QUEUE_STAT_CNTRS); 409 410 for (qid = 0; qid < qdev->num_rx_queues; qid++) { 411 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 412 offsetof(struct qede_rx_queue, rcv_pkts), 0, 413 sizeof(uint64_t)); 414 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 415 offsetof(struct qede_rx_queue, rx_hw_errors), 0, 416 sizeof(uint64_t)); 417 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 418 offsetof(struct qede_rx_queue, rx_alloc_errors), 0, 419 sizeof(uint64_t)); 420 421 if (xstats) 422 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++) 423 OSAL_MEMSET((((char *) 424 (qdev->fp_array[qid].rxq)) + 425 qede_rxq_xstats_strings[j].offset), 426 0, 427 sizeof(uint64_t)); 428 429 i++; 430 if (i == rxq_stat_cntrs) 431 break; 432 } 433 434 i = 0; 435 436 for (qid = 0; qid < qdev->num_tx_queues; qid++) { 437 txq = qdev->fp_array[qid].txq; 438 439 OSAL_MEMSET((uint64_t *)(uintptr_t) 440 (((uint64_t)(uintptr_t)(txq)) + 441 offsetof(struct qede_tx_queue, xmit_pkts)), 0, 442 sizeof(uint64_t)); 443 444 i++; 445 if (i == txq_stat_cntrs) 446 break; 447 } 448 } 449 450 static int 451 qede_stop_vport(struct ecore_dev *edev) 452 { 453 struct ecore_hwfn *p_hwfn; 454 uint8_t vport_id; 455 int rc; 456 int i; 457 458 vport_id = 0; 459 for_each_hwfn(edev, i) { 460 p_hwfn = &edev->hwfns[i]; 461 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid, 462 vport_id); 463 if (rc != ECORE_SUCCESS) { 464 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc); 465 return rc; 466 } 467 } 468 469 DP_INFO(edev, "vport stopped\n"); 470 471 return 0; 472 } 473 474 static int 475 qede_start_vport(struct qede_dev *qdev, uint16_t mtu) 476 { 477 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 478 struct ecore_sp_vport_start_params params; 479 struct ecore_hwfn *p_hwfn; 480 int rc; 481 int i; 482 483 if (qdev->vport_started) 484 qede_stop_vport(edev); 485 486 memset(¶ms, 0, sizeof(params)); 487 params.vport_id = 0; 488 params.mtu = mtu; 489 /* @DPDK - Disable FW placement */ 490 params.zero_placement_offset = 1; 491 for_each_hwfn(edev, i) { 492 p_hwfn = &edev->hwfns[i]; 493 params.concrete_fid = p_hwfn->hw_info.concrete_fid; 494 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 495 rc = ecore_sp_vport_start(p_hwfn, ¶ms); 496 if (rc != ECORE_SUCCESS) { 497 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 498 return rc; 499 } 500 } 501 ecore_reset_vport_stats(edev); 502 qdev->vport_started = true; 503 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu); 504 505 return 0; 506 } 507 508 #define QEDE_NPAR_TX_SWITCHING "npar_tx_switching" 509 #define QEDE_VF_TX_SWITCHING "vf_tx_switching" 510 511 /* Activate or deactivate vport via vport-update */ 512 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg) 513 { 514 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 515 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 516 struct ecore_sp_vport_update_params params; 517 struct ecore_hwfn *p_hwfn; 518 uint8_t i; 519 int rc = -1; 520 521 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 522 params.vport_id = 0; 523 params.update_vport_active_rx_flg = 1; 524 params.update_vport_active_tx_flg = 1; 525 params.vport_active_rx_flg = flg; 526 params.vport_active_tx_flg = flg; 527 if ((qdev->enable_tx_switching == false) && (flg == true)) { 528 params.update_tx_switching_flg = 1; 529 params.tx_switching_flg = !flg; 530 } 531 for_each_hwfn(edev, i) { 532 p_hwfn = &edev->hwfns[i]; 533 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 534 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 535 ECORE_SPQ_MODE_EBLOCK, NULL); 536 if (rc != ECORE_SUCCESS) { 537 DP_ERR(edev, "Failed to update vport\n"); 538 break; 539 } 540 } 541 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated"); 542 543 return rc; 544 } 545 546 static void 547 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params, 548 uint16_t mtu, bool enable) 549 { 550 /* Enable LRO in split mode */ 551 sge_tpa_params->tpa_ipv4_en_flg = enable; 552 sge_tpa_params->tpa_ipv6_en_flg = enable; 553 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable; 554 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable; 555 /* set if tpa enable changes */ 556 sge_tpa_params->update_tpa_en_flg = 1; 557 /* set if tpa parameters should be handled */ 558 sge_tpa_params->update_tpa_param_flg = enable; 559 560 sge_tpa_params->max_buffers_per_cqe = 20; 561 /* Enable TPA in split mode. In this mode each TPA segment 562 * starts on the new BD, so there is one BD per segment. 563 */ 564 sge_tpa_params->tpa_pkt_split_flg = 1; 565 sge_tpa_params->tpa_hdr_data_split_flg = 0; 566 sge_tpa_params->tpa_gro_consistent_flg = 0; 567 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 568 sge_tpa_params->tpa_max_size = 0x7FFF; 569 sge_tpa_params->tpa_min_size_to_start = mtu / 2; 570 sge_tpa_params->tpa_min_size_to_cont = mtu / 2; 571 } 572 573 /* Enable/disable LRO via vport-update */ 574 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg) 575 { 576 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 577 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 578 struct ecore_sp_vport_update_params params; 579 struct ecore_sge_tpa_params tpa_params; 580 struct ecore_hwfn *p_hwfn; 581 int rc; 582 int i; 583 584 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 585 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params)); 586 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg); 587 params.vport_id = 0; 588 params.sge_tpa_params = &tpa_params; 589 for_each_hwfn(edev, i) { 590 p_hwfn = &edev->hwfns[i]; 591 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 592 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 593 ECORE_SPQ_MODE_EBLOCK, NULL); 594 if (rc != ECORE_SUCCESS) { 595 DP_ERR(edev, "Failed to update LRO\n"); 596 return -1; 597 } 598 } 599 qdev->enable_lro = flg; 600 eth_dev->data->lro = flg; 601 602 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled"); 603 604 return 0; 605 } 606 607 static int 608 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev, 609 enum qed_filter_rx_mode_type type) 610 { 611 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 612 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 613 struct ecore_filter_accept_flags flags; 614 615 memset(&flags, 0, sizeof(flags)); 616 617 flags.update_rx_mode_config = 1; 618 flags.update_tx_mode_config = 1; 619 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 620 ECORE_ACCEPT_MCAST_MATCHED | 621 ECORE_ACCEPT_BCAST; 622 623 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 624 ECORE_ACCEPT_MCAST_MATCHED | 625 ECORE_ACCEPT_BCAST; 626 627 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 628 flags.rx_accept_filter |= (ECORE_ACCEPT_UCAST_UNMATCHED | 629 ECORE_ACCEPT_MCAST_UNMATCHED); 630 if (IS_VF(edev)) { 631 flags.tx_accept_filter |= 632 (ECORE_ACCEPT_UCAST_UNMATCHED | 633 ECORE_ACCEPT_MCAST_UNMATCHED); 634 DP_INFO(edev, "Enabling Tx unmatched flags for VF\n"); 635 } 636 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 637 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED; 638 } 639 640 return ecore_filter_accept_cmd(edev, 0, flags, false, false, 641 ECORE_SPQ_MODE_CB, NULL); 642 } 643 644 int 645 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 646 bool add) 647 { 648 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 649 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 650 struct qede_ucast_entry *tmp = NULL; 651 struct qede_ucast_entry *u; 652 struct rte_ether_addr *mac_addr; 653 654 mac_addr = (struct rte_ether_addr *)ucast->mac; 655 if (add) { 656 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 657 if ((memcmp(mac_addr, &tmp->mac, 658 RTE_ETHER_ADDR_LEN) == 0) && 659 ucast->vni == tmp->vni && 660 ucast->vlan == tmp->vlan) { 661 DP_INFO(edev, "Unicast MAC is already added" 662 " with vlan = %u, vni = %u\n", 663 ucast->vlan, ucast->vni); 664 return 0; 665 } 666 } 667 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry), 668 RTE_CACHE_LINE_SIZE); 669 if (!u) { 670 DP_ERR(edev, "Did not allocate memory for ucast\n"); 671 return -ENOMEM; 672 } 673 rte_ether_addr_copy(mac_addr, &u->mac); 674 u->vlan = ucast->vlan; 675 u->vni = ucast->vni; 676 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list); 677 qdev->num_uc_addr++; 678 } else { 679 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 680 if ((memcmp(mac_addr, &tmp->mac, 681 RTE_ETHER_ADDR_LEN) == 0) && 682 ucast->vlan == tmp->vlan && 683 ucast->vni == tmp->vni) 684 break; 685 } 686 if (tmp == NULL) { 687 DP_INFO(edev, "Unicast MAC is not found\n"); 688 return -EINVAL; 689 } 690 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list); 691 qdev->num_uc_addr--; 692 } 693 694 return 0; 695 } 696 697 static int 698 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, 699 struct rte_ether_addr *mc_addrs, 700 uint32_t mc_addrs_num) 701 { 702 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 703 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 704 struct ecore_filter_mcast mcast; 705 struct qede_mcast_entry *m = NULL; 706 uint8_t i; 707 int rc; 708 709 for (i = 0; i < mc_addrs_num; i++) { 710 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry), 711 RTE_CACHE_LINE_SIZE); 712 if (!m) { 713 DP_ERR(edev, "Did not allocate memory for mcast\n"); 714 return -ENOMEM; 715 } 716 rte_ether_addr_copy(&mc_addrs[i], &m->mac); 717 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list); 718 } 719 memset(&mcast, 0, sizeof(mcast)); 720 mcast.num_mc_addrs = mc_addrs_num; 721 mcast.opcode = ECORE_FILTER_ADD; 722 for (i = 0; i < mc_addrs_num; i++) 723 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *) 724 &mcast.mac[i]); 725 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL); 726 if (rc != ECORE_SUCCESS) { 727 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc); 728 return -1; 729 } 730 731 return 0; 732 } 733 734 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev) 735 { 736 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 737 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 738 struct qede_mcast_entry *tmp = NULL; 739 struct ecore_filter_mcast mcast; 740 int j; 741 int rc; 742 743 memset(&mcast, 0, sizeof(mcast)); 744 mcast.num_mc_addrs = qdev->num_mc_addr; 745 mcast.opcode = ECORE_FILTER_REMOVE; 746 j = 0; 747 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 748 rte_ether_addr_copy(&tmp->mac, 749 (struct rte_ether_addr *)&mcast.mac[j]); 750 j++; 751 } 752 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL); 753 if (rc != ECORE_SUCCESS) { 754 DP_ERR(edev, "Failed to delete multicast filter\n"); 755 return -1; 756 } 757 /* Init the list */ 758 while (!SLIST_EMPTY(&qdev->mc_list_head)) { 759 tmp = SLIST_FIRST(&qdev->mc_list_head); 760 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list); 761 } 762 SLIST_INIT(&qdev->mc_list_head); 763 764 return 0; 765 } 766 767 enum _ecore_status_t 768 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 769 bool add) 770 { 771 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 772 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 773 enum _ecore_status_t rc = ECORE_INVAL; 774 775 if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) { 776 DP_ERR(edev, "Ucast filter table limit exceeded," 777 " Please enable promisc mode\n"); 778 return ECORE_INVAL; 779 } 780 781 rc = qede_ucast_filter(eth_dev, ucast, add); 782 if (rc == 0) 783 rc = ecore_filter_ucast_cmd(edev, ucast, 784 ECORE_SPQ_MODE_CB, NULL); 785 /* Indicate error only for add filter operation. 786 * Delete filter operations are not severe. 787 */ 788 if ((rc != ECORE_SUCCESS) && add) 789 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n", 790 rc, add); 791 792 return rc; 793 } 794 795 static int 796 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr, 797 __rte_unused uint32_t index, __rte_unused uint32_t pool) 798 { 799 struct ecore_filter_ucast ucast; 800 int re; 801 802 if (!rte_is_valid_assigned_ether_addr(mac_addr)) 803 return -EINVAL; 804 805 qede_set_ucast_cmn_params(&ucast); 806 ucast.opcode = ECORE_FILTER_ADD; 807 ucast.type = ECORE_FILTER_MAC; 808 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac); 809 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1); 810 return re; 811 } 812 813 static void 814 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 815 { 816 struct qede_dev *qdev = eth_dev->data->dev_private; 817 struct ecore_dev *edev = &qdev->edev; 818 struct ecore_filter_ucast ucast; 819 820 PMD_INIT_FUNC_TRACE(edev); 821 822 if (index >= qdev->dev_info.num_mac_filters) { 823 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 824 index, qdev->dev_info.num_mac_filters); 825 return; 826 } 827 828 if (!rte_is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index])) 829 return; 830 831 qede_set_ucast_cmn_params(&ucast); 832 ucast.opcode = ECORE_FILTER_REMOVE; 833 ucast.type = ECORE_FILTER_MAC; 834 835 /* Use the index maintained by rte */ 836 rte_ether_addr_copy(ð_dev->data->mac_addrs[index], 837 (struct rte_ether_addr *)&ucast.mac); 838 839 qede_mac_int_ops(eth_dev, &ucast, false); 840 } 841 842 static int 843 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr) 844 { 845 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 846 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 847 848 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 849 mac_addr->addr_bytes)) { 850 DP_ERR(edev, "Setting MAC address is not allowed\n"); 851 return -EPERM; 852 } 853 854 qede_mac_addr_remove(eth_dev, 0); 855 856 return qede_mac_addr_add(eth_dev, mac_addr, 0, 0); 857 } 858 859 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg) 860 { 861 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 862 struct ecore_sp_vport_update_params params; 863 struct ecore_hwfn *p_hwfn; 864 uint8_t i; 865 int rc; 866 867 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 868 params.vport_id = 0; 869 params.update_accept_any_vlan_flg = 1; 870 params.accept_any_vlan = flg; 871 for_each_hwfn(edev, i) { 872 p_hwfn = &edev->hwfns[i]; 873 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 874 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 875 ECORE_SPQ_MODE_EBLOCK, NULL); 876 if (rc != ECORE_SUCCESS) { 877 DP_ERR(edev, "Failed to configure accept-any-vlan\n"); 878 return; 879 } 880 } 881 882 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled"); 883 } 884 885 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg) 886 { 887 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 888 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 889 struct ecore_sp_vport_update_params params; 890 struct ecore_hwfn *p_hwfn; 891 uint8_t i; 892 int rc; 893 894 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 895 params.vport_id = 0; 896 params.update_inner_vlan_removal_flg = 1; 897 params.inner_vlan_removal_flg = flg; 898 for_each_hwfn(edev, i) { 899 p_hwfn = &edev->hwfns[i]; 900 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 901 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 902 ECORE_SPQ_MODE_EBLOCK, NULL); 903 if (rc != ECORE_SUCCESS) { 904 DP_ERR(edev, "Failed to update vport\n"); 905 return -1; 906 } 907 } 908 909 qdev->vlan_strip_flg = flg; 910 911 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled"); 912 return 0; 913 } 914 915 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 916 uint16_t vlan_id, int on) 917 { 918 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 919 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 920 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 921 struct qede_vlan_entry *tmp = NULL; 922 struct qede_vlan_entry *vlan; 923 struct ecore_filter_ucast ucast; 924 int rc; 925 926 if (on) { 927 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 928 DP_ERR(edev, "Reached max VLAN filter limit" 929 " enabling accept_any_vlan\n"); 930 qede_config_accept_any_vlan(qdev, true); 931 return 0; 932 } 933 934 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 935 if (tmp->vid == vlan_id) { 936 DP_INFO(edev, "VLAN %u already configured\n", 937 vlan_id); 938 return 0; 939 } 940 } 941 942 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 943 RTE_CACHE_LINE_SIZE); 944 945 if (!vlan) { 946 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 947 return -ENOMEM; 948 } 949 950 qede_set_ucast_cmn_params(&ucast); 951 ucast.opcode = ECORE_FILTER_ADD; 952 ucast.type = ECORE_FILTER_VLAN; 953 ucast.vlan = vlan_id; 954 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 955 NULL); 956 if (rc != 0) { 957 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 958 rc); 959 rte_free(vlan); 960 } else { 961 vlan->vid = vlan_id; 962 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 963 qdev->configured_vlans++; 964 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 965 vlan_id, qdev->configured_vlans); 966 } 967 } else { 968 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 969 if (tmp->vid == vlan_id) 970 break; 971 } 972 973 if (!tmp) { 974 if (qdev->configured_vlans == 0) { 975 DP_INFO(edev, 976 "No VLAN filters configured yet\n"); 977 return 0; 978 } 979 980 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 981 return -EINVAL; 982 } 983 984 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 985 986 qede_set_ucast_cmn_params(&ucast); 987 ucast.opcode = ECORE_FILTER_REMOVE; 988 ucast.type = ECORE_FILTER_VLAN; 989 ucast.vlan = vlan_id; 990 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 991 NULL); 992 if (rc != 0) { 993 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 994 vlan_id, rc); 995 } else { 996 qdev->configured_vlans--; 997 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 998 vlan_id, qdev->configured_vlans); 999 } 1000 } 1001 1002 return rc; 1003 } 1004 1005 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 1006 { 1007 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1008 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1009 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1010 1011 if (mask & ETH_VLAN_STRIP_MASK) { 1012 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1013 (void)qede_vlan_stripping(eth_dev, 1); 1014 else 1015 (void)qede_vlan_stripping(eth_dev, 0); 1016 } 1017 1018 if (mask & ETH_VLAN_FILTER_MASK) { 1019 /* VLAN filtering kicks in when a VLAN is added */ 1020 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 1021 qede_vlan_filter_set(eth_dev, 0, 1); 1022 } else { 1023 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 1024 DP_ERR(edev, 1025 " Please remove existing VLAN filters" 1026 " before disabling VLAN filtering\n"); 1027 /* Signal app that VLAN filtering is still 1028 * enabled 1029 */ 1030 eth_dev->data->dev_conf.rxmode.offloads |= 1031 DEV_RX_OFFLOAD_VLAN_FILTER; 1032 } else { 1033 qede_vlan_filter_set(eth_dev, 0, 0); 1034 } 1035 } 1036 } 1037 1038 if (mask & ETH_VLAN_EXTEND_MASK) 1039 DP_ERR(edev, "Extend VLAN not supported\n"); 1040 1041 qdev->vlan_offload_mask = mask; 1042 1043 DP_INFO(edev, "VLAN offload mask %d\n", mask); 1044 1045 return 0; 1046 } 1047 1048 static void qede_prandom_bytes(uint32_t *buff) 1049 { 1050 uint8_t i; 1051 1052 srand((unsigned int)time(NULL)); 1053 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++) 1054 buff[i] = rand(); 1055 } 1056 1057 int qede_config_rss(struct rte_eth_dev *eth_dev) 1058 { 1059 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1060 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1061 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE]; 1062 struct rte_eth_rss_reta_entry64 reta_conf[2]; 1063 struct rte_eth_rss_conf rss_conf; 1064 uint32_t i, id, pos, q; 1065 1066 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf; 1067 if (!rss_conf.rss_key) { 1068 DP_INFO(edev, "Applying driver default key\n"); 1069 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1070 qede_prandom_bytes(&def_rss_key[0]); 1071 rss_conf.rss_key = (uint8_t *)&def_rss_key[0]; 1072 } 1073 1074 /* Configure RSS hash */ 1075 if (qede_rss_hash_update(eth_dev, &rss_conf)) 1076 return -EINVAL; 1077 1078 /* Configure default RETA */ 1079 memset(reta_conf, 0, sizeof(reta_conf)); 1080 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) 1081 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX; 1082 1083 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 1084 id = i / RTE_RETA_GROUP_SIZE; 1085 pos = i % RTE_RETA_GROUP_SIZE; 1086 q = i % QEDE_RSS_COUNT(eth_dev); 1087 reta_conf[id].reta[pos] = q; 1088 } 1089 if (qede_rss_reta_update(eth_dev, &reta_conf[0], 1090 ECORE_RSS_IND_TABLE_SIZE)) 1091 return -EINVAL; 1092 1093 return 0; 1094 } 1095 1096 static void qede_fastpath_start(struct ecore_dev *edev) 1097 { 1098 struct ecore_hwfn *p_hwfn; 1099 int i; 1100 1101 for_each_hwfn(edev, i) { 1102 p_hwfn = &edev->hwfns[i]; 1103 ecore_hw_start_fastpath(p_hwfn); 1104 } 1105 } 1106 1107 static int qede_dev_start(struct rte_eth_dev *eth_dev) 1108 { 1109 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1110 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1111 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1112 1113 PMD_INIT_FUNC_TRACE(edev); 1114 1115 /* Update MTU only if it has changed */ 1116 if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) { 1117 if (qede_update_mtu(eth_dev, qdev->new_mtu)) 1118 goto err; 1119 qdev->mtu = qdev->new_mtu; 1120 qdev->new_mtu = 0; 1121 } 1122 1123 /* Configure TPA parameters */ 1124 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) { 1125 if (qede_enable_tpa(eth_dev, true)) 1126 return -EINVAL; 1127 /* Enable scatter mode for LRO */ 1128 if (!eth_dev->data->scattered_rx) 1129 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER; 1130 } 1131 1132 /* Start queues */ 1133 if (qede_start_queues(eth_dev)) 1134 goto err; 1135 1136 if (IS_PF(edev)) 1137 qede_reset_queue_stats(qdev, true); 1138 1139 /* Newer SR-IOV PF driver expects RX/TX queues to be started before 1140 * enabling RSS. Hence RSS configuration is deferred up to this point. 1141 * Also, we would like to retain similar behavior in PF case, so we 1142 * don't do PF/VF specific check here. 1143 */ 1144 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 1145 if (qede_config_rss(eth_dev)) 1146 goto err; 1147 1148 /* Enable vport*/ 1149 if (qede_activate_vport(eth_dev, true)) 1150 goto err; 1151 1152 /* Bring-up the link */ 1153 qede_dev_set_link_state(eth_dev, true); 1154 1155 /* Update link status */ 1156 qede_link_update(eth_dev, 0); 1157 1158 /* Start/resume traffic */ 1159 qede_fastpath_start(edev); 1160 1161 /* Assign I/O handlers */ 1162 qede_assign_rxtx_handlers(eth_dev, false); 1163 1164 DP_INFO(edev, "Device started\n"); 1165 1166 return 0; 1167 err: 1168 DP_ERR(edev, "Device start fails\n"); 1169 return -1; /* common error code is < 0 */ 1170 } 1171 1172 static void qede_dev_stop(struct rte_eth_dev *eth_dev) 1173 { 1174 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1175 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1176 1177 PMD_INIT_FUNC_TRACE(edev); 1178 1179 /* Bring the link down */ 1180 qede_dev_set_link_state(eth_dev, false); 1181 1182 /* Update link status */ 1183 qede_link_update(eth_dev, 0); 1184 1185 /* Replace I/O functions with dummy ones. It cannot 1186 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL. 1187 */ 1188 qede_assign_rxtx_handlers(eth_dev, true); 1189 1190 /* Disable vport */ 1191 if (qede_activate_vport(eth_dev, false)) 1192 return; 1193 1194 if (qdev->enable_lro) 1195 qede_enable_tpa(eth_dev, false); 1196 1197 /* Stop queues */ 1198 qede_stop_queues(eth_dev); 1199 1200 /* Disable traffic */ 1201 ecore_hw_stop_fastpath(edev); /* TBD - loop */ 1202 1203 DP_INFO(edev, "Device is stopped\n"); 1204 } 1205 1206 static const char * const valid_args[] = { 1207 QEDE_NPAR_TX_SWITCHING, 1208 QEDE_VF_TX_SWITCHING, 1209 NULL, 1210 }; 1211 1212 static int qede_args_check(const char *key, const char *val, void *opaque) 1213 { 1214 unsigned long tmp; 1215 int ret = 0; 1216 struct rte_eth_dev *eth_dev = opaque; 1217 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1218 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1219 1220 errno = 0; 1221 tmp = strtoul(val, NULL, 0); 1222 if (errno) { 1223 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val); 1224 return errno; 1225 } 1226 1227 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) || 1228 ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) { 1229 qdev->enable_tx_switching = !!tmp; 1230 DP_INFO(edev, "Disabling %s tx-switching\n", 1231 strcmp(QEDE_NPAR_TX_SWITCHING, key) ? 1232 "VF" : "NPAR"); 1233 } 1234 1235 return ret; 1236 } 1237 1238 static int qede_args(struct rte_eth_dev *eth_dev) 1239 { 1240 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 1241 struct rte_kvargs *kvlist; 1242 struct rte_devargs *devargs; 1243 int ret; 1244 int i; 1245 1246 devargs = pci_dev->device.devargs; 1247 if (!devargs) 1248 return 0; /* return success */ 1249 1250 kvlist = rte_kvargs_parse(devargs->args, valid_args); 1251 if (kvlist == NULL) 1252 return -EINVAL; 1253 1254 /* Process parameters. */ 1255 for (i = 0; (valid_args[i] != NULL); ++i) { 1256 if (rte_kvargs_count(kvlist, valid_args[i])) { 1257 ret = rte_kvargs_process(kvlist, valid_args[i], 1258 qede_args_check, eth_dev); 1259 if (ret != ECORE_SUCCESS) { 1260 rte_kvargs_free(kvlist); 1261 return ret; 1262 } 1263 } 1264 } 1265 rte_kvargs_free(kvlist); 1266 1267 return 0; 1268 } 1269 1270 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 1271 { 1272 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1273 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1274 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1275 uint8_t num_rxqs; 1276 uint8_t num_txqs; 1277 int ret; 1278 1279 PMD_INIT_FUNC_TRACE(edev); 1280 1281 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG) 1282 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1283 1284 /* We need to have min 1 RX queue.There is no min check in 1285 * rte_eth_dev_configure(), so we are checking it here. 1286 */ 1287 if (eth_dev->data->nb_rx_queues == 0) { 1288 DP_ERR(edev, "Minimum one RX queue is required\n"); 1289 return -EINVAL; 1290 } 1291 1292 /* Enable Tx switching by default */ 1293 qdev->enable_tx_switching = 1; 1294 1295 /* Parse devargs and fix up rxmode */ 1296 if (qede_args(eth_dev)) 1297 DP_NOTICE(edev, false, 1298 "Invalid devargs supplied, requested change will not take effect\n"); 1299 1300 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || 1301 rxmode->mq_mode == ETH_MQ_RX_RSS)) { 1302 DP_ERR(edev, "Unsupported multi-queue mode\n"); 1303 return -ENOTSUP; 1304 } 1305 /* Flow director mode check */ 1306 if (qede_check_fdir_support(eth_dev)) 1307 return -ENOTSUP; 1308 1309 /* Allocate/reallocate fastpath resources only for new queue config */ 1310 num_txqs = eth_dev->data->nb_tx_queues * edev->num_hwfns; 1311 num_rxqs = eth_dev->data->nb_rx_queues * edev->num_hwfns; 1312 if (qdev->num_tx_queues != num_txqs || 1313 qdev->num_rx_queues != num_rxqs) { 1314 qede_dealloc_fp_resc(eth_dev); 1315 qdev->num_tx_queues = num_txqs; 1316 qdev->num_rx_queues = num_rxqs; 1317 if (qede_alloc_fp_resc(qdev)) 1318 return -ENOMEM; 1319 } 1320 1321 /* If jumbo enabled adjust MTU */ 1322 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 1323 eth_dev->data->mtu = 1324 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1325 RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD; 1326 1327 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) 1328 eth_dev->data->scattered_rx = 1; 1329 1330 if (qede_start_vport(qdev, eth_dev->data->mtu)) 1331 return -1; 1332 1333 qdev->mtu = eth_dev->data->mtu; 1334 1335 /* Enable VLAN offloads by default */ 1336 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 1337 ETH_VLAN_FILTER_MASK); 1338 if (ret) 1339 return ret; 1340 1341 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n", 1342 QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev)); 1343 1344 if (ECORE_IS_CMT(edev)) 1345 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n", 1346 qdev->num_rx_queues, qdev->num_tx_queues); 1347 1348 1349 return 0; 1350 } 1351 1352 /* Info about HW descriptor ring limitations */ 1353 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 1354 .nb_max = 0x8000, /* 32K */ 1355 .nb_min = 128, 1356 .nb_align = 128 /* lowest common multiple */ 1357 }; 1358 1359 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 1360 .nb_max = 0x8000, /* 32K */ 1361 .nb_min = 256, 1362 .nb_align = 256, 1363 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET, 1364 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 1365 }; 1366 1367 static int 1368 qede_dev_info_get(struct rte_eth_dev *eth_dev, 1369 struct rte_eth_dev_info *dev_info) 1370 { 1371 struct qede_dev *qdev = eth_dev->data->dev_private; 1372 struct ecore_dev *edev = &qdev->edev; 1373 struct qed_link_output link; 1374 uint32_t speed_cap = 0; 1375 1376 PMD_INIT_FUNC_TRACE(edev); 1377 1378 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE; 1379 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 1380 dev_info->rx_desc_lim = qede_rx_desc_lim; 1381 dev_info->tx_desc_lim = qede_tx_desc_lim; 1382 1383 if (IS_PF(edev)) 1384 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1385 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2); 1386 else 1387 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1388 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); 1389 /* Since CMT mode internally doubles the number of queues */ 1390 if (ECORE_IS_CMT(edev)) 1391 dev_info->max_rx_queues = dev_info->max_rx_queues / 2; 1392 1393 dev_info->max_tx_queues = dev_info->max_rx_queues; 1394 1395 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters; 1396 dev_info->max_vfs = 0; 1397 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 1398 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1399 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 1400 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 1401 DEV_RX_OFFLOAD_UDP_CKSUM | 1402 DEV_RX_OFFLOAD_TCP_CKSUM | 1403 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1404 DEV_RX_OFFLOAD_TCP_LRO | 1405 DEV_RX_OFFLOAD_KEEP_CRC | 1406 DEV_RX_OFFLOAD_SCATTER | 1407 DEV_RX_OFFLOAD_JUMBO_FRAME | 1408 DEV_RX_OFFLOAD_VLAN_FILTER | 1409 DEV_RX_OFFLOAD_VLAN_STRIP | 1410 DEV_RX_OFFLOAD_RSS_HASH); 1411 dev_info->rx_queue_offload_capa = 0; 1412 1413 /* TX offloads are on a per-packet basis, so it is applicable 1414 * to both at port and queue levels. 1415 */ 1416 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 1417 DEV_TX_OFFLOAD_IPV4_CKSUM | 1418 DEV_TX_OFFLOAD_UDP_CKSUM | 1419 DEV_TX_OFFLOAD_TCP_CKSUM | 1420 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1421 DEV_TX_OFFLOAD_MULTI_SEGS | 1422 DEV_TX_OFFLOAD_TCP_TSO | 1423 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 1424 DEV_TX_OFFLOAD_GENEVE_TNL_TSO); 1425 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa; 1426 1427 dev_info->default_txconf = (struct rte_eth_txconf) { 1428 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS, 1429 }; 1430 1431 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1432 /* Packets are always dropped if no descriptors are available */ 1433 .rx_drop_en = 1, 1434 .offloads = 0, 1435 }; 1436 1437 memset(&link, 0, sizeof(struct qed_link_output)); 1438 qdev->ops->common->get_link(edev, &link); 1439 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1440 speed_cap |= ETH_LINK_SPEED_1G; 1441 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1442 speed_cap |= ETH_LINK_SPEED_10G; 1443 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1444 speed_cap |= ETH_LINK_SPEED_25G; 1445 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1446 speed_cap |= ETH_LINK_SPEED_40G; 1447 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1448 speed_cap |= ETH_LINK_SPEED_50G; 1449 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1450 speed_cap |= ETH_LINK_SPEED_100G; 1451 dev_info->speed_capa = speed_cap; 1452 1453 return 0; 1454 } 1455 1456 /* return 0 means link status changed, -1 means not changed */ 1457 int 1458 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 1459 { 1460 struct qede_dev *qdev = eth_dev->data->dev_private; 1461 struct ecore_dev *edev = &qdev->edev; 1462 struct qed_link_output q_link; 1463 struct rte_eth_link link; 1464 uint16_t link_duplex; 1465 1466 memset(&q_link, 0, sizeof(q_link)); 1467 memset(&link, 0, sizeof(link)); 1468 1469 qdev->ops->common->get_link(edev, &q_link); 1470 1471 /* Link Speed */ 1472 link.link_speed = q_link.speed; 1473 1474 /* Link Mode */ 1475 switch (q_link.duplex) { 1476 case QEDE_DUPLEX_HALF: 1477 link_duplex = ETH_LINK_HALF_DUPLEX; 1478 break; 1479 case QEDE_DUPLEX_FULL: 1480 link_duplex = ETH_LINK_FULL_DUPLEX; 1481 break; 1482 case QEDE_DUPLEX_UNKNOWN: 1483 default: 1484 link_duplex = -1; 1485 } 1486 link.link_duplex = link_duplex; 1487 1488 /* Link Status */ 1489 link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 1490 1491 /* AN */ 1492 link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 1493 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 1494 1495 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 1496 link.link_speed, link.link_duplex, 1497 link.link_autoneg, link.link_status); 1498 1499 return rte_eth_linkstatus_set(eth_dev, &link); 1500 } 1501 1502 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 1503 { 1504 enum _ecore_status_t ecore_status; 1505 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1506 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1507 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 1508 1509 PMD_INIT_FUNC_TRACE(edev); 1510 1511 ecore_status = qed_configure_filter_rx_mode(eth_dev, type); 1512 1513 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN; 1514 } 1515 1516 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 1517 { 1518 struct qede_dev *qdev = eth_dev->data->dev_private; 1519 struct ecore_dev *edev = &qdev->edev; 1520 enum _ecore_status_t ecore_status; 1521 1522 PMD_INIT_FUNC_TRACE(edev); 1523 1524 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1525 ecore_status = qed_configure_filter_rx_mode(eth_dev, 1526 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 1527 else 1528 ecore_status = qed_configure_filter_rx_mode(eth_dev, 1529 QED_FILTER_RX_MODE_TYPE_REGULAR); 1530 1531 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN; 1532 } 1533 1534 static void qede_poll_sp_sb_cb(void *param) 1535 { 1536 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1537 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1538 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1539 int rc; 1540 1541 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 1542 qede_interrupt_action(&edev->hwfns[1]); 1543 1544 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD, 1545 qede_poll_sp_sb_cb, 1546 (void *)eth_dev); 1547 if (rc != 0) { 1548 DP_ERR(edev, "Unable to start periodic" 1549 " timer rc %d\n", rc); 1550 } 1551 } 1552 1553 static void qede_dev_close(struct rte_eth_dev *eth_dev) 1554 { 1555 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1556 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1557 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1558 1559 PMD_INIT_FUNC_TRACE(edev); 1560 1561 /* dev_stop() shall cleanup fp resources in hw but without releasing 1562 * dma memories and sw structures so that dev_start() can be called 1563 * by the app without reconfiguration. However, in dev_close() we 1564 * can release all the resources and device can be brought up newly 1565 */ 1566 if (eth_dev->data->dev_started) 1567 qede_dev_stop(eth_dev); 1568 1569 if (qdev->vport_started) 1570 qede_stop_vport(edev); 1571 qdev->vport_started = false; 1572 qede_fdir_dealloc_resc(eth_dev); 1573 qede_dealloc_fp_resc(eth_dev); 1574 1575 eth_dev->data->nb_rx_queues = 0; 1576 eth_dev->data->nb_tx_queues = 0; 1577 1578 qdev->ops->common->slowpath_stop(edev); 1579 qdev->ops->common->remove(edev); 1580 rte_intr_disable(&pci_dev->intr_handle); 1581 1582 switch (pci_dev->intr_handle.type) { 1583 case RTE_INTR_HANDLE_UIO_INTX: 1584 case RTE_INTR_HANDLE_VFIO_LEGACY: 1585 rte_intr_callback_unregister(&pci_dev->intr_handle, 1586 qede_interrupt_handler_intx, 1587 (void *)eth_dev); 1588 break; 1589 default: 1590 rte_intr_callback_unregister(&pci_dev->intr_handle, 1591 qede_interrupt_handler, 1592 (void *)eth_dev); 1593 } 1594 1595 if (ECORE_IS_CMT(edev)) 1596 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 1597 } 1598 1599 static int 1600 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 1601 { 1602 struct qede_dev *qdev = eth_dev->data->dev_private; 1603 struct ecore_dev *edev = &qdev->edev; 1604 struct ecore_eth_stats stats; 1605 unsigned int i = 0, j = 0, qid, idx, hw_fn; 1606 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 1607 struct qede_tx_queue *txq; 1608 1609 ecore_get_vport_stats(edev, &stats); 1610 1611 /* RX Stats */ 1612 eth_stats->ipackets = stats.common.rx_ucast_pkts + 1613 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts; 1614 1615 eth_stats->ibytes = stats.common.rx_ucast_bytes + 1616 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes; 1617 1618 eth_stats->ierrors = stats.common.rx_crc_errors + 1619 stats.common.rx_align_errors + 1620 stats.common.rx_carrier_errors + 1621 stats.common.rx_oversize_packets + 1622 stats.common.rx_jabbers + stats.common.rx_undersize_packets; 1623 1624 eth_stats->rx_nombuf = stats.common.no_buff_discards; 1625 1626 eth_stats->imissed = stats.common.mftag_filter_discards + 1627 stats.common.mac_filter_discards + 1628 stats.common.no_buff_discards + 1629 stats.common.brb_truncates + stats.common.brb_discards; 1630 1631 /* TX stats */ 1632 eth_stats->opackets = stats.common.tx_ucast_pkts + 1633 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts; 1634 1635 eth_stats->obytes = stats.common.tx_ucast_bytes + 1636 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes; 1637 1638 eth_stats->oerrors = stats.common.tx_err_drop_pkts; 1639 1640 /* Queue stats */ 1641 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev), 1642 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1643 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev), 1644 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1645 if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) || 1646 txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev)) 1647 DP_VERBOSE(edev, ECORE_MSG_DEBUG, 1648 "Not all the queue stats will be displayed. Set" 1649 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param" 1650 " appropriately and retry.\n"); 1651 1652 for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) { 1653 eth_stats->q_ipackets[i] = 0; 1654 eth_stats->q_errors[i] = 0; 1655 1656 for_each_hwfn(edev, hw_fn) { 1657 idx = qid * edev->num_hwfns + hw_fn; 1658 1659 eth_stats->q_ipackets[i] += 1660 *(uint64_t *) 1661 (((char *)(qdev->fp_array[idx].rxq)) + 1662 offsetof(struct qede_rx_queue, 1663 rcv_pkts)); 1664 eth_stats->q_errors[i] += 1665 *(uint64_t *) 1666 (((char *)(qdev->fp_array[idx].rxq)) + 1667 offsetof(struct qede_rx_queue, 1668 rx_hw_errors)) + 1669 *(uint64_t *) 1670 (((char *)(qdev->fp_array[idx].rxq)) + 1671 offsetof(struct qede_rx_queue, 1672 rx_alloc_errors)); 1673 } 1674 1675 i++; 1676 if (i == rxq_stat_cntrs) 1677 break; 1678 } 1679 1680 for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) { 1681 eth_stats->q_opackets[j] = 0; 1682 1683 for_each_hwfn(edev, hw_fn) { 1684 idx = qid * edev->num_hwfns + hw_fn; 1685 1686 txq = qdev->fp_array[idx].txq; 1687 eth_stats->q_opackets[j] += 1688 *((uint64_t *)(uintptr_t) 1689 (((uint64_t)(uintptr_t)(txq)) + 1690 offsetof(struct qede_tx_queue, 1691 xmit_pkts))); 1692 } 1693 1694 j++; 1695 if (j == txq_stat_cntrs) 1696 break; 1697 } 1698 1699 return 0; 1700 } 1701 1702 static unsigned 1703 qede_get_xstats_count(struct qede_dev *qdev) { 1704 struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev; 1705 1706 if (ECORE_IS_BB(&qdev->edev)) 1707 return RTE_DIM(qede_xstats_strings) + 1708 RTE_DIM(qede_bb_xstats_strings) + 1709 (RTE_DIM(qede_rxq_xstats_strings) * 1710 QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns); 1711 else 1712 return RTE_DIM(qede_xstats_strings) + 1713 RTE_DIM(qede_ah_xstats_strings) + 1714 (RTE_DIM(qede_rxq_xstats_strings) * 1715 QEDE_RSS_COUNT(dev)); 1716 } 1717 1718 static int 1719 qede_get_xstats_names(struct rte_eth_dev *dev, 1720 struct rte_eth_xstat_name *xstats_names, 1721 __rte_unused unsigned int limit) 1722 { 1723 struct qede_dev *qdev = dev->data->dev_private; 1724 struct ecore_dev *edev = &qdev->edev; 1725 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 1726 unsigned int i, qid, hw_fn, stat_idx = 0; 1727 1728 if (xstats_names == NULL) 1729 return stat_cnt; 1730 1731 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1732 strlcpy(xstats_names[stat_idx].name, 1733 qede_xstats_strings[i].name, 1734 sizeof(xstats_names[stat_idx].name)); 1735 stat_idx++; 1736 } 1737 1738 if (ECORE_IS_BB(edev)) { 1739 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1740 strlcpy(xstats_names[stat_idx].name, 1741 qede_bb_xstats_strings[i].name, 1742 sizeof(xstats_names[stat_idx].name)); 1743 stat_idx++; 1744 } 1745 } else { 1746 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1747 strlcpy(xstats_names[stat_idx].name, 1748 qede_ah_xstats_strings[i].name, 1749 sizeof(xstats_names[stat_idx].name)); 1750 stat_idx++; 1751 } 1752 } 1753 1754 for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) { 1755 for_each_hwfn(edev, hw_fn) { 1756 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1757 snprintf(xstats_names[stat_idx].name, 1758 RTE_ETH_XSTATS_NAME_SIZE, 1759 "%.4s%d.%d%s", 1760 qede_rxq_xstats_strings[i].name, 1761 hw_fn, qid, 1762 qede_rxq_xstats_strings[i].name + 4); 1763 stat_idx++; 1764 } 1765 } 1766 } 1767 1768 return stat_cnt; 1769 } 1770 1771 static int 1772 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1773 unsigned int n) 1774 { 1775 struct qede_dev *qdev = dev->data->dev_private; 1776 struct ecore_dev *edev = &qdev->edev; 1777 struct ecore_eth_stats stats; 1778 const unsigned int num = qede_get_xstats_count(qdev); 1779 unsigned int i, qid, hw_fn, fpidx, stat_idx = 0; 1780 1781 if (n < num) 1782 return num; 1783 1784 ecore_get_vport_stats(edev, &stats); 1785 1786 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1787 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 1788 qede_xstats_strings[i].offset); 1789 xstats[stat_idx].id = stat_idx; 1790 stat_idx++; 1791 } 1792 1793 if (ECORE_IS_BB(edev)) { 1794 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1795 xstats[stat_idx].value = 1796 *(uint64_t *)(((char *)&stats) + 1797 qede_bb_xstats_strings[i].offset); 1798 xstats[stat_idx].id = stat_idx; 1799 stat_idx++; 1800 } 1801 } else { 1802 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1803 xstats[stat_idx].value = 1804 *(uint64_t *)(((char *)&stats) + 1805 qede_ah_xstats_strings[i].offset); 1806 xstats[stat_idx].id = stat_idx; 1807 stat_idx++; 1808 } 1809 } 1810 1811 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) { 1812 for_each_hwfn(edev, hw_fn) { 1813 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1814 fpidx = qid * edev->num_hwfns + hw_fn; 1815 xstats[stat_idx].value = *(uint64_t *) 1816 (((char *)(qdev->fp_array[fpidx].rxq)) + 1817 qede_rxq_xstats_strings[i].offset); 1818 xstats[stat_idx].id = stat_idx; 1819 stat_idx++; 1820 } 1821 1822 } 1823 } 1824 1825 return stat_idx; 1826 } 1827 1828 static int 1829 qede_reset_xstats(struct rte_eth_dev *dev) 1830 { 1831 struct qede_dev *qdev = dev->data->dev_private; 1832 struct ecore_dev *edev = &qdev->edev; 1833 1834 ecore_reset_vport_stats(edev); 1835 qede_reset_queue_stats(qdev, true); 1836 1837 return 0; 1838 } 1839 1840 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 1841 { 1842 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1843 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1844 struct qed_link_params link_params; 1845 int rc; 1846 1847 DP_INFO(edev, "setting link state %d\n", link_up); 1848 memset(&link_params, 0, sizeof(link_params)); 1849 link_params.link_up = link_up; 1850 rc = qdev->ops->common->set_link(edev, &link_params); 1851 if (rc != ECORE_SUCCESS) 1852 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1853 1854 return rc; 1855 } 1856 1857 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1858 { 1859 return qede_dev_set_link_state(eth_dev, true); 1860 } 1861 1862 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1863 { 1864 return qede_dev_set_link_state(eth_dev, false); 1865 } 1866 1867 static int qede_reset_stats(struct rte_eth_dev *eth_dev) 1868 { 1869 struct qede_dev *qdev = eth_dev->data->dev_private; 1870 struct ecore_dev *edev = &qdev->edev; 1871 1872 ecore_reset_vport_stats(edev); 1873 qede_reset_queue_stats(qdev, false); 1874 1875 return 0; 1876 } 1877 1878 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 1879 { 1880 enum qed_filter_rx_mode_type type = 1881 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1882 enum _ecore_status_t ecore_status; 1883 1884 ecore_status = qed_configure_filter_rx_mode(eth_dev, type); 1885 1886 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN; 1887 } 1888 1889 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 1890 { 1891 enum _ecore_status_t ecore_status; 1892 1893 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1894 ecore_status = qed_configure_filter_rx_mode(eth_dev, 1895 QED_FILTER_RX_MODE_TYPE_PROMISC); 1896 else 1897 ecore_status = qed_configure_filter_rx_mode(eth_dev, 1898 QED_FILTER_RX_MODE_TYPE_REGULAR); 1899 1900 return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN; 1901 } 1902 1903 static int 1904 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, 1905 struct rte_ether_addr *mc_addrs, 1906 uint32_t mc_addrs_num) 1907 { 1908 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1909 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1910 uint8_t i; 1911 1912 if (mc_addrs_num > ECORE_MAX_MC_ADDRS) { 1913 DP_ERR(edev, "Reached max multicast filters limit," 1914 "Please enable multicast promisc mode\n"); 1915 return -ENOSPC; 1916 } 1917 1918 for (i = 0; i < mc_addrs_num; i++) { 1919 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) { 1920 DP_ERR(edev, "Not a valid multicast MAC\n"); 1921 return -EINVAL; 1922 } 1923 } 1924 1925 /* Flush all existing entries */ 1926 if (qede_del_mcast_filters(eth_dev)) 1927 return -1; 1928 1929 /* Set new mcast list */ 1930 return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num); 1931 } 1932 1933 /* Update MTU via vport-update without doing port restart. 1934 * The vport must be deactivated before calling this API. 1935 */ 1936 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu) 1937 { 1938 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1939 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1940 struct ecore_hwfn *p_hwfn; 1941 int rc; 1942 int i; 1943 1944 if (IS_PF(edev)) { 1945 struct ecore_sp_vport_update_params params; 1946 1947 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 1948 params.vport_id = 0; 1949 params.mtu = mtu; 1950 params.vport_id = 0; 1951 for_each_hwfn(edev, i) { 1952 p_hwfn = &edev->hwfns[i]; 1953 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1954 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 1955 ECORE_SPQ_MODE_EBLOCK, NULL); 1956 if (rc != ECORE_SUCCESS) 1957 goto err; 1958 } 1959 } else { 1960 for_each_hwfn(edev, i) { 1961 p_hwfn = &edev->hwfns[i]; 1962 rc = ecore_vf_pf_update_mtu(p_hwfn, mtu); 1963 if (rc == ECORE_INVAL) { 1964 DP_INFO(edev, "VF MTU Update TLV not supported\n"); 1965 /* Recreate vport */ 1966 rc = qede_start_vport(qdev, mtu); 1967 if (rc != ECORE_SUCCESS) 1968 goto err; 1969 1970 /* Restore config lost due to vport stop */ 1971 if (eth_dev->data->promiscuous) 1972 qede_promiscuous_enable(eth_dev); 1973 else 1974 qede_promiscuous_disable(eth_dev); 1975 1976 if (eth_dev->data->all_multicast) 1977 qede_allmulticast_enable(eth_dev); 1978 else 1979 qede_allmulticast_disable(eth_dev); 1980 1981 qede_vlan_offload_set(eth_dev, 1982 qdev->vlan_offload_mask); 1983 } else if (rc != ECORE_SUCCESS) { 1984 goto err; 1985 } 1986 } 1987 } 1988 DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu); 1989 1990 return 0; 1991 1992 err: 1993 DP_ERR(edev, "Failed to update MTU\n"); 1994 return -1; 1995 } 1996 1997 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1998 struct rte_eth_fc_conf *fc_conf) 1999 { 2000 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2001 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2002 struct qed_link_output current_link; 2003 struct qed_link_params params; 2004 2005 memset(¤t_link, 0, sizeof(current_link)); 2006 qdev->ops->common->get_link(edev, ¤t_link); 2007 2008 memset(¶ms, 0, sizeof(params)); 2009 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 2010 if (fc_conf->autoneg) { 2011 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 2012 DP_ERR(edev, "Autoneg not supported\n"); 2013 return -EINVAL; 2014 } 2015 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 2016 } 2017 2018 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 2019 if (fc_conf->mode == RTE_FC_FULL) 2020 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 2021 QED_LINK_PAUSE_RX_ENABLE); 2022 if (fc_conf->mode == RTE_FC_TX_PAUSE) 2023 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 2024 if (fc_conf->mode == RTE_FC_RX_PAUSE) 2025 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 2026 2027 params.link_up = true; 2028 (void)qdev->ops->common->set_link(edev, ¶ms); 2029 2030 return 0; 2031 } 2032 2033 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 2034 struct rte_eth_fc_conf *fc_conf) 2035 { 2036 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2037 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2038 struct qed_link_output current_link; 2039 2040 memset(¤t_link, 0, sizeof(current_link)); 2041 qdev->ops->common->get_link(edev, ¤t_link); 2042 2043 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 2044 fc_conf->autoneg = true; 2045 2046 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 2047 QED_LINK_PAUSE_TX_ENABLE)) 2048 fc_conf->mode = RTE_FC_FULL; 2049 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 2050 fc_conf->mode = RTE_FC_RX_PAUSE; 2051 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 2052 fc_conf->mode = RTE_FC_TX_PAUSE; 2053 else 2054 fc_conf->mode = RTE_FC_NONE; 2055 2056 return 0; 2057 } 2058 2059 static const uint32_t * 2060 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 2061 { 2062 static const uint32_t ptypes[] = { 2063 RTE_PTYPE_L2_ETHER, 2064 RTE_PTYPE_L2_ETHER_VLAN, 2065 RTE_PTYPE_L3_IPV4, 2066 RTE_PTYPE_L3_IPV6, 2067 RTE_PTYPE_L4_TCP, 2068 RTE_PTYPE_L4_UDP, 2069 RTE_PTYPE_TUNNEL_VXLAN, 2070 RTE_PTYPE_L4_FRAG, 2071 RTE_PTYPE_TUNNEL_GENEVE, 2072 RTE_PTYPE_TUNNEL_GRE, 2073 /* Inner */ 2074 RTE_PTYPE_INNER_L2_ETHER, 2075 RTE_PTYPE_INNER_L2_ETHER_VLAN, 2076 RTE_PTYPE_INNER_L3_IPV4, 2077 RTE_PTYPE_INNER_L3_IPV6, 2078 RTE_PTYPE_INNER_L4_TCP, 2079 RTE_PTYPE_INNER_L4_UDP, 2080 RTE_PTYPE_INNER_L4_FRAG, 2081 RTE_PTYPE_UNKNOWN 2082 }; 2083 2084 if (eth_dev->rx_pkt_burst == qede_recv_pkts || 2085 eth_dev->rx_pkt_burst == qede_recv_pkts_regular || 2086 eth_dev->rx_pkt_burst == qede_recv_pkts_cmt) 2087 return ptypes; 2088 2089 return NULL; 2090 } 2091 2092 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 2093 { 2094 *rss_caps = 0; 2095 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 2096 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 2097 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 2098 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 2099 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 2100 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 2101 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0; 2102 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0; 2103 } 2104 2105 int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 2106 struct rte_eth_rss_conf *rss_conf) 2107 { 2108 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2109 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2110 struct ecore_sp_vport_update_params vport_update_params; 2111 struct ecore_rss_params rss_params; 2112 struct ecore_hwfn *p_hwfn; 2113 uint32_t *key = (uint32_t *)rss_conf->rss_key; 2114 uint64_t hf = rss_conf->rss_hf; 2115 uint8_t len = rss_conf->rss_key_len; 2116 uint8_t idx, i, j, fpidx; 2117 int rc; 2118 2119 memset(&vport_update_params, 0, sizeof(vport_update_params)); 2120 memset(&rss_params, 0, sizeof(rss_params)); 2121 2122 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n", 2123 (unsigned long)hf, len, key); 2124 2125 if (hf != 0) { 2126 /* Enabling RSS */ 2127 DP_INFO(edev, "Enabling rss\n"); 2128 2129 /* RSS caps */ 2130 qede_init_rss_caps(&rss_params.rss_caps, hf); 2131 rss_params.update_rss_capabilities = 1; 2132 2133 /* RSS hash key */ 2134 if (key) { 2135 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) { 2136 DP_ERR(edev, "RSS key length exceeds limit\n"); 2137 return -EINVAL; 2138 } 2139 DP_INFO(edev, "Applying user supplied hash key\n"); 2140 rss_params.update_rss_key = 1; 2141 memcpy(&rss_params.rss_key, key, len); 2142 } 2143 rss_params.rss_enable = 1; 2144 } 2145 2146 rss_params.update_rss_config = 1; 2147 /* tbl_size has to be set with capabilities */ 2148 rss_params.rss_table_size_log = 7; 2149 vport_update_params.vport_id = 0; 2150 2151 for_each_hwfn(edev, i) { 2152 /* pass the L2 handles instead of qids */ 2153 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) { 2154 idx = j % QEDE_RSS_COUNT(eth_dev); 2155 fpidx = idx * edev->num_hwfns + i; 2156 rss_params.rss_ind_table[j] = 2157 qdev->fp_array[fpidx].rxq->handle; 2158 } 2159 2160 vport_update_params.rss_params = &rss_params; 2161 2162 p_hwfn = &edev->hwfns[i]; 2163 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2164 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 2165 ECORE_SPQ_MODE_EBLOCK, NULL); 2166 if (rc) { 2167 DP_ERR(edev, "vport-update for RSS failed\n"); 2168 return rc; 2169 } 2170 } 2171 qdev->rss_enable = rss_params.rss_enable; 2172 2173 /* Update local structure for hash query */ 2174 qdev->rss_conf.rss_hf = hf; 2175 qdev->rss_conf.rss_key_len = len; 2176 if (qdev->rss_enable) { 2177 if (qdev->rss_conf.rss_key == NULL) { 2178 qdev->rss_conf.rss_key = (uint8_t *)malloc(len); 2179 if (qdev->rss_conf.rss_key == NULL) { 2180 DP_ERR(edev, "No memory to store RSS key\n"); 2181 return -ENOMEM; 2182 } 2183 } 2184 if (key && len) { 2185 DP_INFO(edev, "Storing RSS key\n"); 2186 memcpy(qdev->rss_conf.rss_key, key, len); 2187 } 2188 } else if (!qdev->rss_enable && len == 0) { 2189 if (qdev->rss_conf.rss_key) { 2190 free(qdev->rss_conf.rss_key); 2191 qdev->rss_conf.rss_key = NULL; 2192 DP_INFO(edev, "Free RSS key\n"); 2193 } 2194 } 2195 2196 return 0; 2197 } 2198 2199 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 2200 struct rte_eth_rss_conf *rss_conf) 2201 { 2202 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2203 2204 rss_conf->rss_hf = qdev->rss_conf.rss_hf; 2205 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len; 2206 2207 if (rss_conf->rss_key && qdev->rss_conf.rss_key) 2208 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key, 2209 rss_conf->rss_key_len); 2210 return 0; 2211 } 2212 2213 int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 2214 struct rte_eth_rss_reta_entry64 *reta_conf, 2215 uint16_t reta_size) 2216 { 2217 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2218 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2219 struct ecore_sp_vport_update_params vport_update_params; 2220 struct ecore_rss_params *params; 2221 uint16_t i, j, idx, fid, shift; 2222 struct ecore_hwfn *p_hwfn; 2223 uint8_t entry; 2224 int rc = 0; 2225 2226 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2227 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 2228 reta_size); 2229 return -EINVAL; 2230 } 2231 2232 memset(&vport_update_params, 0, sizeof(vport_update_params)); 2233 params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE); 2234 if (params == NULL) { 2235 DP_ERR(edev, "failed to allocate memory\n"); 2236 return -ENOMEM; 2237 } 2238 2239 params->update_rss_ind_table = 1; 2240 params->rss_table_size_log = 7; 2241 params->update_rss_config = 1; 2242 2243 vport_update_params.vport_id = 0; 2244 /* Use the current value of rss_enable */ 2245 params->rss_enable = qdev->rss_enable; 2246 vport_update_params.rss_params = params; 2247 2248 for_each_hwfn(edev, i) { 2249 for (j = 0; j < reta_size; j++) { 2250 idx = j / RTE_RETA_GROUP_SIZE; 2251 shift = j % RTE_RETA_GROUP_SIZE; 2252 if (reta_conf[idx].mask & (1ULL << shift)) { 2253 entry = reta_conf[idx].reta[shift]; 2254 fid = entry * edev->num_hwfns + i; 2255 /* Pass rxq handles to ecore */ 2256 params->rss_ind_table[j] = 2257 qdev->fp_array[fid].rxq->handle; 2258 /* Update the local copy for RETA query cmd */ 2259 qdev->rss_ind_table[j] = entry; 2260 } 2261 } 2262 2263 p_hwfn = &edev->hwfns[i]; 2264 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2265 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 2266 ECORE_SPQ_MODE_EBLOCK, NULL); 2267 if (rc) { 2268 DP_ERR(edev, "vport-update for RSS failed\n"); 2269 goto out; 2270 } 2271 } 2272 2273 out: 2274 rte_free(params); 2275 return rc; 2276 } 2277 2278 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 2279 struct rte_eth_rss_reta_entry64 *reta_conf, 2280 uint16_t reta_size) 2281 { 2282 struct qede_dev *qdev = eth_dev->data->dev_private; 2283 struct ecore_dev *edev = &qdev->edev; 2284 uint16_t i, idx, shift; 2285 uint8_t entry; 2286 2287 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2288 DP_ERR(edev, "reta_size %d is not supported\n", 2289 reta_size); 2290 return -EINVAL; 2291 } 2292 2293 for (i = 0; i < reta_size; i++) { 2294 idx = i / RTE_RETA_GROUP_SIZE; 2295 shift = i % RTE_RETA_GROUP_SIZE; 2296 if (reta_conf[idx].mask & (1ULL << shift)) { 2297 entry = qdev->rss_ind_table[i]; 2298 reta_conf[idx].reta[shift] = entry; 2299 } 2300 } 2301 2302 return 0; 2303 } 2304 2305 2306 2307 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 2308 { 2309 struct qede_dev *qdev = QEDE_INIT_QDEV(dev); 2310 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2311 struct rte_eth_dev_info dev_info = {0}; 2312 struct qede_fastpath *fp; 2313 uint32_t max_rx_pkt_len; 2314 uint32_t frame_size; 2315 uint16_t bufsz; 2316 bool restart = false; 2317 int i, rc; 2318 2319 PMD_INIT_FUNC_TRACE(edev); 2320 rc = qede_dev_info_get(dev, &dev_info); 2321 if (rc != 0) { 2322 DP_ERR(edev, "Error during getting ethernet device info\n"); 2323 return rc; 2324 } 2325 max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN; 2326 frame_size = max_rx_pkt_len; 2327 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) { 2328 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n", 2329 mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN - 2330 QEDE_ETH_OVERHEAD); 2331 return -EINVAL; 2332 } 2333 if (!dev->data->scattered_rx && 2334 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 2335 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n", 2336 dev->data->min_rx_buf_size); 2337 return -EINVAL; 2338 } 2339 if (dev->data->dev_started) { 2340 dev->data->dev_started = 0; 2341 qede_dev_stop(dev); 2342 restart = true; 2343 } 2344 rte_delay_ms(1000); 2345 qdev->new_mtu = mtu; 2346 2347 /* Fix up RX buf size for all queues of the port */ 2348 for (i = 0; i < qdev->num_rx_queues; i++) { 2349 fp = &qdev->fp_array[i]; 2350 if (fp->rxq != NULL) { 2351 bufsz = (uint16_t)rte_pktmbuf_data_room_size( 2352 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM; 2353 /* cache align the mbuf size to simplfy rx_buf_size 2354 * calculation 2355 */ 2356 bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz); 2357 rc = qede_calc_rx_buf_size(dev, bufsz, frame_size); 2358 if (rc < 0) 2359 return rc; 2360 2361 fp->rxq->rx_buf_size = rc; 2362 } 2363 } 2364 if (max_rx_pkt_len > RTE_ETHER_MAX_LEN) 2365 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; 2366 else 2367 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2368 2369 if (!dev->data->dev_started && restart) { 2370 qede_dev_start(dev); 2371 dev->data->dev_started = 1; 2372 } 2373 2374 /* update max frame size */ 2375 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len; 2376 2377 return 0; 2378 } 2379 2380 static int 2381 qede_dev_reset(struct rte_eth_dev *dev) 2382 { 2383 int ret; 2384 2385 ret = qede_eth_dev_uninit(dev); 2386 if (ret) 2387 return ret; 2388 2389 return qede_eth_dev_init(dev); 2390 } 2391 2392 static const struct eth_dev_ops qede_eth_dev_ops = { 2393 .dev_configure = qede_dev_configure, 2394 .dev_infos_get = qede_dev_info_get, 2395 .rx_queue_setup = qede_rx_queue_setup, 2396 .rx_queue_release = qede_rx_queue_release, 2397 .rx_descriptor_status = qede_rx_descriptor_status, 2398 .tx_queue_setup = qede_tx_queue_setup, 2399 .tx_queue_release = qede_tx_queue_release, 2400 .dev_start = qede_dev_start, 2401 .dev_reset = qede_dev_reset, 2402 .dev_set_link_up = qede_dev_set_link_up, 2403 .dev_set_link_down = qede_dev_set_link_down, 2404 .link_update = qede_link_update, 2405 .promiscuous_enable = qede_promiscuous_enable, 2406 .promiscuous_disable = qede_promiscuous_disable, 2407 .allmulticast_enable = qede_allmulticast_enable, 2408 .allmulticast_disable = qede_allmulticast_disable, 2409 .set_mc_addr_list = qede_set_mc_addr_list, 2410 .dev_stop = qede_dev_stop, 2411 .dev_close = qede_dev_close, 2412 .stats_get = qede_get_stats, 2413 .stats_reset = qede_reset_stats, 2414 .xstats_get = qede_get_xstats, 2415 .xstats_reset = qede_reset_xstats, 2416 .xstats_get_names = qede_get_xstats_names, 2417 .mac_addr_add = qede_mac_addr_add, 2418 .mac_addr_remove = qede_mac_addr_remove, 2419 .mac_addr_set = qede_mac_addr_set, 2420 .vlan_offload_set = qede_vlan_offload_set, 2421 .vlan_filter_set = qede_vlan_filter_set, 2422 .flow_ctrl_set = qede_flow_ctrl_set, 2423 .flow_ctrl_get = qede_flow_ctrl_get, 2424 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2425 .rss_hash_update = qede_rss_hash_update, 2426 .rss_hash_conf_get = qede_rss_hash_conf_get, 2427 .reta_update = qede_rss_reta_update, 2428 .reta_query = qede_rss_reta_query, 2429 .mtu_set = qede_set_mtu, 2430 .filter_ctrl = qede_dev_filter_ctrl, 2431 .udp_tunnel_port_add = qede_udp_dst_port_add, 2432 .udp_tunnel_port_del = qede_udp_dst_port_del, 2433 .fw_version_get = qede_fw_version_get, 2434 }; 2435 2436 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 2437 .dev_configure = qede_dev_configure, 2438 .dev_infos_get = qede_dev_info_get, 2439 .rx_queue_setup = qede_rx_queue_setup, 2440 .rx_queue_release = qede_rx_queue_release, 2441 .rx_descriptor_status = qede_rx_descriptor_status, 2442 .tx_queue_setup = qede_tx_queue_setup, 2443 .tx_queue_release = qede_tx_queue_release, 2444 .dev_start = qede_dev_start, 2445 .dev_reset = qede_dev_reset, 2446 .dev_set_link_up = qede_dev_set_link_up, 2447 .dev_set_link_down = qede_dev_set_link_down, 2448 .link_update = qede_link_update, 2449 .promiscuous_enable = qede_promiscuous_enable, 2450 .promiscuous_disable = qede_promiscuous_disable, 2451 .allmulticast_enable = qede_allmulticast_enable, 2452 .allmulticast_disable = qede_allmulticast_disable, 2453 .set_mc_addr_list = qede_set_mc_addr_list, 2454 .dev_stop = qede_dev_stop, 2455 .dev_close = qede_dev_close, 2456 .stats_get = qede_get_stats, 2457 .stats_reset = qede_reset_stats, 2458 .xstats_get = qede_get_xstats, 2459 .xstats_reset = qede_reset_xstats, 2460 .xstats_get_names = qede_get_xstats_names, 2461 .vlan_offload_set = qede_vlan_offload_set, 2462 .vlan_filter_set = qede_vlan_filter_set, 2463 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2464 .rss_hash_update = qede_rss_hash_update, 2465 .rss_hash_conf_get = qede_rss_hash_conf_get, 2466 .reta_update = qede_rss_reta_update, 2467 .reta_query = qede_rss_reta_query, 2468 .mtu_set = qede_set_mtu, 2469 .udp_tunnel_port_add = qede_udp_dst_port_add, 2470 .udp_tunnel_port_del = qede_udp_dst_port_del, 2471 .mac_addr_add = qede_mac_addr_add, 2472 .mac_addr_remove = qede_mac_addr_remove, 2473 .mac_addr_set = qede_mac_addr_set, 2474 .fw_version_get = qede_fw_version_get, 2475 }; 2476 2477 static void qede_update_pf_params(struct ecore_dev *edev) 2478 { 2479 struct ecore_pf_params pf_params; 2480 2481 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 2482 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS; 2483 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR; 2484 qed_ops->common->update_pf_params(edev, &pf_params); 2485 } 2486 2487 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 2488 { 2489 struct rte_pci_device *pci_dev; 2490 struct rte_pci_addr pci_addr; 2491 struct qede_dev *adapter; 2492 struct ecore_dev *edev; 2493 struct qed_dev_eth_info dev_info; 2494 struct qed_slowpath_params params; 2495 static bool do_once = true; 2496 uint8_t bulletin_change; 2497 uint8_t vf_mac[RTE_ETHER_ADDR_LEN]; 2498 uint8_t is_mac_forced; 2499 bool is_mac_exist; 2500 /* Fix up ecore debug level */ 2501 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 2502 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 2503 uint32_t int_mode; 2504 int rc; 2505 2506 /* Extract key data structures */ 2507 adapter = eth_dev->data->dev_private; 2508 adapter->ethdev = eth_dev; 2509 edev = &adapter->edev; 2510 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2511 pci_addr = pci_dev->addr; 2512 2513 PMD_INIT_FUNC_TRACE(edev); 2514 2515 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 2516 pci_addr.bus, pci_addr.devid, pci_addr.function, 2517 eth_dev->data->port_id); 2518 2519 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2520 DP_ERR(edev, "Skipping device init from secondary process\n"); 2521 return 0; 2522 } 2523 2524 rte_eth_copy_pci_info(eth_dev, pci_dev); 2525 2526 /* @DPDK */ 2527 edev->vendor_id = pci_dev->id.vendor_id; 2528 edev->device_id = pci_dev->id.device_id; 2529 2530 qed_ops = qed_get_eth_ops(); 2531 if (!qed_ops) { 2532 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 2533 rc = -EINVAL; 2534 goto err; 2535 } 2536 2537 DP_INFO(edev, "Starting qede probe\n"); 2538 rc = qed_ops->common->probe(edev, pci_dev, dp_module, 2539 dp_level, is_vf); 2540 if (rc != 0) { 2541 DP_ERR(edev, "qede probe failed rc %d\n", rc); 2542 rc = -ENODEV; 2543 goto err; 2544 } 2545 qede_update_pf_params(edev); 2546 2547 switch (pci_dev->intr_handle.type) { 2548 case RTE_INTR_HANDLE_UIO_INTX: 2549 case RTE_INTR_HANDLE_VFIO_LEGACY: 2550 int_mode = ECORE_INT_MODE_INTA; 2551 rte_intr_callback_register(&pci_dev->intr_handle, 2552 qede_interrupt_handler_intx, 2553 (void *)eth_dev); 2554 break; 2555 default: 2556 int_mode = ECORE_INT_MODE_MSIX; 2557 rte_intr_callback_register(&pci_dev->intr_handle, 2558 qede_interrupt_handler, 2559 (void *)eth_dev); 2560 } 2561 2562 if (rte_intr_enable(&pci_dev->intr_handle)) { 2563 DP_ERR(edev, "rte_intr_enable() failed\n"); 2564 rc = -ENODEV; 2565 goto err; 2566 } 2567 2568 /* Start the Slowpath-process */ 2569 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 2570 2571 params.int_mode = int_mode; 2572 params.drv_major = QEDE_PMD_VERSION_MAJOR; 2573 params.drv_minor = QEDE_PMD_VERSION_MINOR; 2574 params.drv_rev = QEDE_PMD_VERSION_REVISION; 2575 params.drv_eng = QEDE_PMD_VERSION_PATCH; 2576 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 2577 QEDE_PMD_DRV_VER_STR_SIZE); 2578 2579 qede_assign_rxtx_handlers(eth_dev, true); 2580 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts; 2581 2582 /* For CMT mode device do periodic polling for slowpath events. 2583 * This is required since uio device uses only one MSI-x 2584 * interrupt vector but we need one for each engine. 2585 */ 2586 if (ECORE_IS_CMT(edev) && IS_PF(edev)) { 2587 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD, 2588 qede_poll_sp_sb_cb, 2589 (void *)eth_dev); 2590 if (rc != 0) { 2591 DP_ERR(edev, "Unable to start periodic" 2592 " timer rc %d\n", rc); 2593 rc = -EINVAL; 2594 goto err; 2595 } 2596 } 2597 2598 rc = qed_ops->common->slowpath_start(edev, ¶ms); 2599 if (rc) { 2600 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 2601 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2602 (void *)eth_dev); 2603 rc = -ENODEV; 2604 goto err; 2605 } 2606 2607 rc = qed_ops->fill_dev_info(edev, &dev_info); 2608 if (rc) { 2609 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 2610 qed_ops->common->slowpath_stop(edev); 2611 qed_ops->common->remove(edev); 2612 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2613 (void *)eth_dev); 2614 rc = -ENODEV; 2615 goto err; 2616 } 2617 2618 qede_alloc_etherdev(adapter, &dev_info); 2619 2620 if (do_once) { 2621 qede_print_adapter_info(eth_dev); 2622 do_once = false; 2623 } 2624 2625 adapter->ops->common->set_name(edev, edev->name); 2626 2627 if (!is_vf) 2628 adapter->dev_info.num_mac_filters = 2629 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 2630 ECORE_MAC); 2631 else 2632 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 2633 (uint32_t *)&adapter->dev_info.num_mac_filters); 2634 2635 /* Allocate memory for storing MAC addr */ 2636 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 2637 (RTE_ETHER_ADDR_LEN * 2638 adapter->dev_info.num_mac_filters), 2639 RTE_CACHE_LINE_SIZE); 2640 2641 if (eth_dev->data->mac_addrs == NULL) { 2642 DP_ERR(edev, "Failed to allocate MAC address\n"); 2643 qed_ops->common->slowpath_stop(edev); 2644 qed_ops->common->remove(edev); 2645 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2646 (void *)eth_dev); 2647 return -ENOMEM; 2648 } 2649 2650 if (!is_vf) { 2651 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0]. 2652 hw_info.hw_mac_addr, 2653 ð_dev->data->mac_addrs[0]); 2654 rte_ether_addr_copy(ð_dev->data->mac_addrs[0], 2655 &adapter->primary_mac); 2656 } else { 2657 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 2658 &bulletin_change); 2659 if (bulletin_change) { 2660 is_mac_exist = 2661 ecore_vf_bulletin_get_forced_mac( 2662 ECORE_LEADING_HWFN(edev), 2663 vf_mac, 2664 &is_mac_forced); 2665 if (is_mac_exist) { 2666 DP_INFO(edev, "VF macaddr received from PF\n"); 2667 rte_ether_addr_copy( 2668 (struct rte_ether_addr *)&vf_mac, 2669 ð_dev->data->mac_addrs[0]); 2670 rte_ether_addr_copy( 2671 ð_dev->data->mac_addrs[0], 2672 &adapter->primary_mac); 2673 } else { 2674 DP_ERR(edev, "No VF macaddr assigned\n"); 2675 } 2676 } 2677 } 2678 2679 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 2680 2681 adapter->num_tx_queues = 0; 2682 adapter->num_rx_queues = 0; 2683 SLIST_INIT(&adapter->arfs_info.arfs_list_head); 2684 SLIST_INIT(&adapter->vlan_list_head); 2685 SLIST_INIT(&adapter->uc_list_head); 2686 SLIST_INIT(&adapter->mc_list_head); 2687 adapter->mtu = RTE_ETHER_MTU; 2688 adapter->vport_started = false; 2689 2690 /* VF tunnel offloads is enabled by default in PF driver */ 2691 adapter->vxlan.num_filters = 0; 2692 adapter->geneve.num_filters = 0; 2693 adapter->ipgre.num_filters = 0; 2694 if (is_vf) { 2695 adapter->vxlan.enable = true; 2696 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC | 2697 ETH_TUNNEL_FILTER_IVLAN; 2698 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT; 2699 adapter->geneve.enable = true; 2700 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC | 2701 ETH_TUNNEL_FILTER_IVLAN; 2702 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT; 2703 adapter->ipgre.enable = true; 2704 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC | 2705 ETH_TUNNEL_FILTER_IVLAN; 2706 } else { 2707 adapter->vxlan.enable = false; 2708 adapter->geneve.enable = false; 2709 adapter->ipgre.enable = false; 2710 } 2711 2712 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 2713 adapter->primary_mac.addr_bytes[0], 2714 adapter->primary_mac.addr_bytes[1], 2715 adapter->primary_mac.addr_bytes[2], 2716 adapter->primary_mac.addr_bytes[3], 2717 adapter->primary_mac.addr_bytes[4], 2718 adapter->primary_mac.addr_bytes[5]); 2719 2720 DP_INFO(edev, "Device initialized\n"); 2721 2722 return 0; 2723 2724 err: 2725 if (do_once) { 2726 qede_print_adapter_info(eth_dev); 2727 do_once = false; 2728 } 2729 return rc; 2730 } 2731 2732 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 2733 { 2734 return qede_common_dev_init(eth_dev, 1); 2735 } 2736 2737 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 2738 { 2739 return qede_common_dev_init(eth_dev, 0); 2740 } 2741 2742 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 2743 { 2744 struct qede_dev *qdev = eth_dev->data->dev_private; 2745 struct ecore_dev *edev = &qdev->edev; 2746 2747 PMD_INIT_FUNC_TRACE(edev); 2748 2749 /* only uninitialize in the primary process */ 2750 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2751 return 0; 2752 2753 /* safe to close dev here */ 2754 qede_dev_close(eth_dev); 2755 2756 eth_dev->dev_ops = NULL; 2757 eth_dev->rx_pkt_burst = NULL; 2758 eth_dev->tx_pkt_burst = NULL; 2759 2760 return 0; 2761 } 2762 2763 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2764 { 2765 return qede_dev_common_uninit(eth_dev); 2766 } 2767 2768 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2769 { 2770 return qede_dev_common_uninit(eth_dev); 2771 } 2772 2773 static const struct rte_pci_id pci_id_qedevf_map[] = { 2774 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2775 { 2776 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF) 2777 }, 2778 { 2779 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV) 2780 }, 2781 { 2782 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) 2783 }, 2784 {.vendor_id = 0,} 2785 }; 2786 2787 static const struct rte_pci_id pci_id_qede_map[] = { 2788 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2789 { 2790 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E) 2791 }, 2792 { 2793 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S) 2794 }, 2795 { 2796 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40) 2797 }, 2798 { 2799 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25) 2800 }, 2801 { 2802 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100) 2803 }, 2804 { 2805 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50) 2806 }, 2807 { 2808 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G) 2809 }, 2810 { 2811 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G) 2812 }, 2813 { 2814 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G) 2815 }, 2816 { 2817 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) 2818 }, 2819 {.vendor_id = 0,} 2820 }; 2821 2822 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2823 struct rte_pci_device *pci_dev) 2824 { 2825 return rte_eth_dev_pci_generic_probe(pci_dev, 2826 sizeof(struct qede_dev), qedevf_eth_dev_init); 2827 } 2828 2829 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 2830 { 2831 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit); 2832 } 2833 2834 static struct rte_pci_driver rte_qedevf_pmd = { 2835 .id_table = pci_id_qedevf_map, 2836 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2837 .probe = qedevf_eth_dev_pci_probe, 2838 .remove = qedevf_eth_dev_pci_remove, 2839 }; 2840 2841 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2842 struct rte_pci_device *pci_dev) 2843 { 2844 return rte_eth_dev_pci_generic_probe(pci_dev, 2845 sizeof(struct qede_dev), qede_eth_dev_init); 2846 } 2847 2848 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 2849 { 2850 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit); 2851 } 2852 2853 static struct rte_pci_driver rte_qede_pmd = { 2854 .id_table = pci_id_qede_map, 2855 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2856 .probe = qede_eth_dev_pci_probe, 2857 .remove = qede_eth_dev_pci_remove, 2858 }; 2859 2860 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd); 2861 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 2862 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci"); 2863 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd); 2864 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 2865 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci"); 2866 2867 RTE_INIT(qede_init_log) 2868 { 2869 qede_logtype_init = rte_log_register("pmd.net.qede.init"); 2870 if (qede_logtype_init >= 0) 2871 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE); 2872 qede_logtype_driver = rte_log_register("pmd.net.qede.driver"); 2873 if (qede_logtype_driver >= 0) 2874 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE); 2875 } 2876