1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #include "bcm_osal.h" 8 #include "reg_addr.h" 9 #include "ecore_gtt_reg_addr.h" 10 #include "ecore.h" 11 #include "ecore_chain.h" 12 #include "ecore_status.h" 13 #include "ecore_hw.h" 14 #include "ecore_rt_defs.h" 15 #include "ecore_init_ops.h" 16 #include "ecore_int.h" 17 #include "ecore_cxt.h" 18 #include "ecore_spq.h" 19 #include "ecore_init_fw_funcs.h" 20 #include "ecore_sp_commands.h" 21 #include "ecore_dev_api.h" 22 #include "ecore_sriov.h" 23 #include "ecore_vf.h" 24 #include "ecore_mcp.h" 25 #include "ecore_hw_defs.h" 26 #include "mcp_public.h" 27 #include "ecore_iro.h" 28 #include "nvm_cfg.h" 29 #include "ecore_dcbx.h" 30 #include "ecore_l2.h" 31 32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM 33 * registers involved are not split and thus configuration is a race where 34 * some of the PFs configuration might be lost. 35 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration 36 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where 37 * there's more than a single compiled ecore component in system]. 38 */ 39 static osal_spinlock_t qm_lock; 40 static u32 qm_lock_ref_cnt; 41 42 /******************** Doorbell Recovery *******************/ 43 /* The doorbell recovery mechanism consists of a list of entries which represent 44 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each 45 * entity needs to register with the mechanism and provide the parameters 46 * describing it's doorbell, including a location where last used doorbell data 47 * can be found. The doorbell execute function will traverse the list and 48 * doorbell all of the registered entries. 49 */ 50 struct ecore_db_recovery_entry { 51 osal_list_entry_t list_entry; 52 void OSAL_IOMEM *db_addr; 53 void *db_data; 54 enum ecore_db_rec_width db_width; 55 enum ecore_db_rec_space db_space; 56 u8 hwfn_idx; 57 }; 58 59 /* display a single doorbell recovery entry */ 60 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn, 61 struct ecore_db_recovery_entry *db_entry, 62 const char *action) 63 { 64 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n", 65 action, db_entry, db_entry->db_addr, db_entry->db_data, 66 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b", 67 db_entry->db_space == DB_REC_USER ? "user" : "kernel", 68 db_entry->hwfn_idx); 69 } 70 71 /* doorbell address sanity (address within doorbell bar range) */ 72 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr, 73 void *db_data) 74 { 75 /* make sure doorbell address is within the doorbell bar */ 76 if (db_addr < p_dev->doorbells || (u8 *)db_addr > 77 (u8 *)p_dev->doorbells + p_dev->db_size) { 78 OSAL_WARN(true, 79 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n", 80 db_addr, p_dev->doorbells, 81 (u8 *)p_dev->doorbells + p_dev->db_size); 82 return false; 83 } 84 85 /* make sure doorbell data pointer is not null */ 86 if (!db_data) { 87 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data); 88 return false; 89 } 90 91 return true; 92 } 93 94 /* find hwfn according to the doorbell address */ 95 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev, 96 void OSAL_IOMEM *db_addr) 97 { 98 struct ecore_hwfn *p_hwfn; 99 100 /* In CMT doorbell bar is split down the middle between engine 0 and 101 * enigne 1 102 */ 103 if (ECORE_IS_CMT(p_dev)) 104 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ? 105 &p_dev->hwfns[0] : &p_dev->hwfns[1]; 106 else 107 p_hwfn = ECORE_LEADING_HWFN(p_dev); 108 109 return p_hwfn; 110 } 111 112 /* add a new entry to the doorbell recovery mechanism */ 113 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev, 114 void OSAL_IOMEM *db_addr, 115 void *db_data, 116 enum ecore_db_rec_width db_width, 117 enum ecore_db_rec_space db_space) 118 { 119 struct ecore_db_recovery_entry *db_entry; 120 struct ecore_hwfn *p_hwfn; 121 122 /* shortcircuit VFs, for now */ 123 if (IS_VF(p_dev)) { 124 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n"); 125 return ECORE_SUCCESS; 126 } 127 128 /* sanitize doorbell address */ 129 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data)) 130 return ECORE_INVAL; 131 132 /* obtain hwfn from doorbell address */ 133 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr); 134 135 /* create entry */ 136 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry)); 137 if (!db_entry) { 138 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n"); 139 return ECORE_NOMEM; 140 } 141 142 /* populate entry */ 143 db_entry->db_addr = db_addr; 144 db_entry->db_data = db_data; 145 db_entry->db_width = db_width; 146 db_entry->db_space = db_space; 147 db_entry->hwfn_idx = p_hwfn->my_id; 148 149 /* display */ 150 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding"); 151 152 /* protect the list */ 153 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock); 154 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry, 155 &p_hwfn->db_recovery_info.list); 156 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock); 157 158 return ECORE_SUCCESS; 159 } 160 161 /* remove an entry from the doorbell recovery mechanism */ 162 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev, 163 void OSAL_IOMEM *db_addr, 164 void *db_data) 165 { 166 struct ecore_db_recovery_entry *db_entry = OSAL_NULL; 167 enum _ecore_status_t rc = ECORE_INVAL; 168 struct ecore_hwfn *p_hwfn; 169 170 /* shortcircuit VFs, for now */ 171 if (IS_VF(p_dev)) { 172 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n"); 173 return ECORE_SUCCESS; 174 } 175 176 /* sanitize doorbell address */ 177 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data)) 178 return ECORE_INVAL; 179 180 /* obtain hwfn from doorbell address */ 181 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr); 182 183 /* protect the list */ 184 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock); 185 OSAL_LIST_FOR_EACH_ENTRY(db_entry, 186 &p_hwfn->db_recovery_info.list, 187 list_entry, 188 struct ecore_db_recovery_entry) { 189 /* search according to db_data addr since db_addr is not unique 190 * (roce) 191 */ 192 if (db_entry->db_data == db_data) { 193 ecore_db_recovery_dp_entry(p_hwfn, db_entry, 194 "Deleting"); 195 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry, 196 &p_hwfn->db_recovery_info.list); 197 rc = ECORE_SUCCESS; 198 break; 199 } 200 } 201 202 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock); 203 204 if (rc == ECORE_INVAL) 205 /*OSAL_WARN(true,*/ 206 DP_NOTICE(p_hwfn, false, 207 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n", 208 db_data, db_addr); 209 else 210 OSAL_FREE(p_dev, db_entry); 211 212 return rc; 213 } 214 215 /* initialize the doorbell recovery mechanism */ 216 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn) 217 { 218 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n"); 219 220 /* make sure db_size was set in p_dev */ 221 if (!p_hwfn->p_dev->db_size) { 222 DP_ERR(p_hwfn->p_dev, "db_size not set\n"); 223 return ECORE_INVAL; 224 } 225 226 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list); 227 #ifdef CONFIG_ECORE_LOCK_ALLOC 228 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock)) 229 return ECORE_NOMEM; 230 #endif 231 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock); 232 p_hwfn->db_recovery_info.db_recovery_counter = 0; 233 234 return ECORE_SUCCESS; 235 } 236 237 /* destroy the doorbell recovery mechanism */ 238 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn) 239 { 240 struct ecore_db_recovery_entry *db_entry = OSAL_NULL; 241 242 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n"); 243 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) { 244 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n"); 245 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) { 246 db_entry = OSAL_LIST_FIRST_ENTRY( 247 &p_hwfn->db_recovery_info.list, 248 struct ecore_db_recovery_entry, 249 list_entry); 250 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging"); 251 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry, 252 &p_hwfn->db_recovery_info.list); 253 OSAL_FREE(p_hwfn->p_dev, db_entry); 254 } 255 } 256 #ifdef CONFIG_ECORE_LOCK_ALLOC 257 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock); 258 #endif 259 p_hwfn->db_recovery_info.db_recovery_counter = 0; 260 } 261 262 /* print the content of the doorbell recovery mechanism */ 263 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn) 264 { 265 struct ecore_db_recovery_entry *db_entry = OSAL_NULL; 266 267 DP_NOTICE(p_hwfn, false, 268 "Dispalying doorbell recovery database. Counter was %d\n", 269 p_hwfn->db_recovery_info.db_recovery_counter); 270 271 /* protect the list */ 272 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock); 273 OSAL_LIST_FOR_EACH_ENTRY(db_entry, 274 &p_hwfn->db_recovery_info.list, 275 list_entry, 276 struct ecore_db_recovery_entry) { 277 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing"); 278 } 279 280 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock); 281 } 282 283 /* ring the doorbell of a single doorbell recovery entry */ 284 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn, 285 struct ecore_db_recovery_entry *db_entry, 286 enum ecore_db_rec_exec db_exec) 287 { 288 /* Print according to width */ 289 if (db_entry->db_width == DB_REC_WIDTH_32B) 290 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n", 291 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing", 292 db_entry->db_addr, *(u32 *)db_entry->db_data); 293 else 294 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n", 295 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing", 296 db_entry->db_addr, 297 *(unsigned long *)(db_entry->db_data)); 298 299 /* Sanity */ 300 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr, 301 db_entry->db_data)) 302 return; 303 304 /* Flush the write combined buffer. Since there are multiple doorbelling 305 * entities using the same address, if we don't flush, a transaction 306 * could be lost. 307 */ 308 OSAL_WMB(p_hwfn->p_dev); 309 310 /* Ring the doorbell */ 311 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) { 312 if (db_entry->db_width == DB_REC_WIDTH_32B) 313 DIRECT_REG_WR(p_hwfn, db_entry->db_addr, 314 *(u32 *)(db_entry->db_data)); 315 else 316 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr, 317 *(u64 *)(db_entry->db_data)); 318 } 319 320 /* Flush the write combined buffer. Next doorbell may come from a 321 * different entity to the same address... 322 */ 323 OSAL_WMB(p_hwfn->p_dev); 324 } 325 326 /* traverse the doorbell recovery entry list and ring all the doorbells */ 327 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn, 328 enum ecore_db_rec_exec db_exec) 329 { 330 struct ecore_db_recovery_entry *db_entry = OSAL_NULL; 331 332 if (db_exec != DB_REC_ONCE) { 333 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n", 334 p_hwfn->db_recovery_info.db_recovery_counter); 335 336 /* track amount of times recovery was executed */ 337 p_hwfn->db_recovery_info.db_recovery_counter++; 338 } 339 340 /* protect the list */ 341 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock); 342 OSAL_LIST_FOR_EACH_ENTRY(db_entry, 343 &p_hwfn->db_recovery_info.list, 344 list_entry, 345 struct ecore_db_recovery_entry) { 346 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec); 347 if (db_exec == DB_REC_ONCE) 348 break; 349 } 350 351 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock); 352 } 353 /******************** Doorbell Recovery end ****************/ 354 355 /* Configurable */ 356 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to 357 * load the driver. The number was 358 * arbitrarily set. 359 */ 360 361 /* Derived */ 362 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS) 363 364 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, 365 struct ecore_ptt *p_ptt, 366 enum BAR_ID bar_id) 367 { 368 u32 bar_reg = (bar_id == BAR_ID_0 ? 369 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 370 u32 val; 371 372 if (IS_VF(p_hwfn->p_dev)) 373 return ecore_vf_hw_bar_size(p_hwfn, bar_id); 374 375 val = ecore_rd(p_hwfn, p_ptt, bar_reg); 376 if (val) 377 return 1 << (val + 15); 378 379 /* The above registers were updated in the past only in CMT mode. Since 380 * they were found to be useful MFW started updating them from 8.7.7.0. 381 * In older MFW versions they are set to 0 which means disabled. 382 */ 383 if (ECORE_IS_CMT(p_hwfn->p_dev)) { 384 DP_INFO(p_hwfn, 385 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 386 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024; 387 } else { 388 DP_INFO(p_hwfn, 389 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 390 val = 512 * 1024; 391 } 392 393 return val; 394 } 395 396 void ecore_init_dp(struct ecore_dev *p_dev, 397 u32 dp_module, u8 dp_level, void *dp_ctx) 398 { 399 u32 i; 400 401 p_dev->dp_level = dp_level; 402 p_dev->dp_module = dp_module; 403 p_dev->dp_ctx = dp_ctx; 404 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 405 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 406 407 p_hwfn->dp_level = dp_level; 408 p_hwfn->dp_module = dp_module; 409 p_hwfn->dp_ctx = dp_ctx; 410 } 411 } 412 413 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev) 414 { 415 u8 i; 416 417 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 418 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 419 420 p_hwfn->p_dev = p_dev; 421 p_hwfn->my_id = i; 422 p_hwfn->b_active = false; 423 424 #ifdef CONFIG_ECORE_LOCK_ALLOC 425 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock)) 426 goto handle_err; 427 #endif 428 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock); 429 } 430 431 /* hwfn 0 is always active */ 432 p_dev->hwfns[0].b_active = true; 433 434 /* set the default cache alignment to 128 (may be overridden later) */ 435 p_dev->cache_shift = 7; 436 return ECORE_SUCCESS; 437 #ifdef CONFIG_ECORE_LOCK_ALLOC 438 handle_err: 439 while (--i) { 440 struct ecore_hwfn *p_hwfn = OSAL_NULL; 441 442 p_hwfn = &p_dev->hwfns[i]; 443 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock); 444 } 445 return ECORE_NOMEM; 446 #endif 447 } 448 449 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn) 450 { 451 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 452 453 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params); 454 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params); 455 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params); 456 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data); 457 } 458 459 void ecore_resc_free(struct ecore_dev *p_dev) 460 { 461 int i; 462 463 if (IS_VF(p_dev)) { 464 for_each_hwfn(p_dev, i) 465 ecore_l2_free(&p_dev->hwfns[i]); 466 return; 467 } 468 469 OSAL_FREE(p_dev, p_dev->fw_data); 470 471 OSAL_FREE(p_dev, p_dev->reset_stats); 472 473 for_each_hwfn(p_dev, i) { 474 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 475 476 ecore_cxt_mngr_free(p_hwfn); 477 ecore_qm_info_free(p_hwfn); 478 ecore_spq_free(p_hwfn); 479 ecore_eq_free(p_hwfn); 480 ecore_consq_free(p_hwfn); 481 ecore_int_free(p_hwfn); 482 ecore_iov_free(p_hwfn); 483 ecore_l2_free(p_hwfn); 484 ecore_dmae_info_free(p_hwfn); 485 ecore_dcbx_info_free(p_hwfn); 486 /* @@@TBD Flush work-queue ? */ 487 488 /* destroy doorbell recovery mechanism */ 489 ecore_db_recovery_teardown(p_hwfn); 490 } 491 } 492 493 /******************** QM initialization *******************/ 494 495 /* bitmaps for indicating active traffic classes. 496 * Special case for Arrowhead 4 port 497 */ 498 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */ 499 #define ACTIVE_TCS_BMAP 0x9f 500 /* 0..3 actually used, OOO and high priority stuff all use 3 */ 501 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 502 503 /* determines the physical queue flags for a given PF. */ 504 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn) 505 { 506 u32 flags; 507 508 /* common flags */ 509 flags = PQ_FLAGS_LB; 510 511 /* feature flags */ 512 if (IS_ECORE_SRIOV(p_hwfn->p_dev)) 513 flags |= PQ_FLAGS_VFS; 514 if (IS_ECORE_PACING(p_hwfn)) 515 flags |= PQ_FLAGS_RLS; 516 517 /* protocol flags */ 518 switch (p_hwfn->hw_info.personality) { 519 case ECORE_PCI_ETH: 520 if (!IS_ECORE_PACING(p_hwfn)) 521 flags |= PQ_FLAGS_MCOS; 522 break; 523 case ECORE_PCI_FCOE: 524 flags |= PQ_FLAGS_OFLD; 525 break; 526 case ECORE_PCI_ISCSI: 527 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 528 break; 529 case ECORE_PCI_ETH_ROCE: 530 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 531 if (!IS_ECORE_PACING(p_hwfn)) 532 flags |= PQ_FLAGS_MCOS; 533 break; 534 case ECORE_PCI_ETH_IWARP: 535 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 536 if (!IS_ECORE_PACING(p_hwfn)) 537 flags |= PQ_FLAGS_MCOS; 538 break; 539 default: 540 DP_ERR(p_hwfn, "unknown personality %d\n", 541 p_hwfn->hw_info.personality); 542 return 0; 543 } 544 return flags; 545 } 546 547 /* Getters for resource amounts necessary for qm initialization */ 548 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn) 549 { 550 return p_hwfn->hw_info.num_hw_tc; 551 } 552 553 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn) 554 { 555 return IS_ECORE_SRIOV(p_hwfn->p_dev) ? 556 p_hwfn->p_dev->p_iov_info->total_vfs : 0; 557 } 558 559 #define NUM_DEFAULT_RLS 1 560 561 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn) 562 { 563 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn); 564 565 /* @DPDK */ 566 /* num RLs can't exceed resource amount of rls or vports or the 567 * dcqcn qps 568 */ 569 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL), 570 (u16)RESC_NUM(p_hwfn, ECORE_VPORT)); 571 572 /* make sure after we reserve the default and VF rls we'll have 573 * something left 574 */ 575 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) { 576 DP_NOTICE(p_hwfn, false, 577 "no rate limiters left for PF rate limiting" 578 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs); 579 return 0; 580 } 581 582 /* subtract rls necessary for VFs and one default one for the PF */ 583 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 584 585 return num_pf_rls; 586 } 587 588 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn) 589 { 590 u32 pq_flags = ecore_get_pq_flags(p_hwfn); 591 592 /* all pqs share the same vport (hence the 1 below), except for vfs 593 * and pf_rl pqs 594 */ 595 return (!!(PQ_FLAGS_RLS & pq_flags)) * 596 ecore_init_qm_get_num_pf_rls(p_hwfn) + 597 (!!(PQ_FLAGS_VFS & pq_flags)) * 598 ecore_init_qm_get_num_vfs(p_hwfn) + 1; 599 } 600 601 /* calc amount of PQs according to the requested flags */ 602 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn) 603 { 604 u32 pq_flags = ecore_get_pq_flags(p_hwfn); 605 606 return (!!(PQ_FLAGS_RLS & pq_flags)) * 607 ecore_init_qm_get_num_pf_rls(p_hwfn) + 608 (!!(PQ_FLAGS_MCOS & pq_flags)) * 609 ecore_init_qm_get_num_tcs(p_hwfn) + 610 (!!(PQ_FLAGS_LB & pq_flags)) + 611 (!!(PQ_FLAGS_OOO & pq_flags)) + 612 (!!(PQ_FLAGS_ACK & pq_flags)) + 613 (!!(PQ_FLAGS_OFLD & pq_flags)) + 614 (!!(PQ_FLAGS_VFS & pq_flags)) * 615 ecore_init_qm_get_num_vfs(p_hwfn); 616 } 617 618 /* initialize the top level QM params */ 619 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn) 620 { 621 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 622 bool four_port; 623 624 /* pq and vport bases for this PF */ 625 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ); 626 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT); 627 628 /* rate limiting and weighted fair queueing are always enabled */ 629 qm_info->vport_rl_en = 1; 630 qm_info->vport_wfq_en = 1; 631 632 /* TC config is different for AH 4 port */ 633 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2; 634 635 /* in AH 4 port we have fewer TCs per port */ 636 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 637 NUM_OF_PHYS_TCS; 638 639 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and 640 * 4 otherwise 641 */ 642 if (!qm_info->ooo_tc) 643 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 644 DCBX_TCP_OOO_TC; 645 } 646 647 /* initialize qm vport params */ 648 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn) 649 { 650 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 651 u8 i; 652 653 /* all vports participate in weighted fair queueing */ 654 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++) 655 qm_info->qm_vport_params[i].vport_wfq = 1; 656 } 657 658 /* initialize qm port params */ 659 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn) 660 { 661 /* Initialize qm port parameters */ 662 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine; 663 664 /* indicate how ooo and high pri traffic is dealt with */ 665 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 666 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP; 667 668 for (i = 0; i < num_ports; i++) { 669 struct init_qm_port_params *p_qm_port = 670 &p_hwfn->qm_info.qm_port_params[i]; 671 672 p_qm_port->active = 1; 673 p_qm_port->active_phys_tcs = active_phys_tcs; 674 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports; 675 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 676 } 677 } 678 679 /* Reset the params which must be reset for qm init. QM init may be called as 680 * a result of flows other than driver load (e.g. dcbx renegotiation). Other 681 * params may be affected by the init but would simply recalculate to the same 682 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 683 * affected as these amounts stay the same. 684 */ 685 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn) 686 { 687 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 688 689 qm_info->num_pqs = 0; 690 qm_info->num_vports = 0; 691 qm_info->num_pf_rls = 0; 692 qm_info->num_vf_pqs = 0; 693 qm_info->first_vf_pq = 0; 694 qm_info->first_mcos_pq = 0; 695 qm_info->first_rl_pq = 0; 696 } 697 698 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn) 699 { 700 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 701 702 qm_info->num_vports++; 703 704 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn)) 705 DP_ERR(p_hwfn, 706 "vport overflow! qm_info->num_vports %d," 707 " qm_init_get_num_vports() %d\n", 708 qm_info->num_vports, 709 ecore_init_qm_get_num_vports(p_hwfn)); 710 } 711 712 /* initialize a single pq and manage qm_info resources accounting. 713 * The pq_init_flags param determines whether the PQ is rate limited 714 * (for VF or PF) 715 * and whether a new vport is allocated to the pq or not (i.e. vport will be 716 * shared) 717 */ 718 719 /* flags for pq init */ 720 #define PQ_INIT_SHARE_VPORT (1 << 0) 721 #define PQ_INIT_PF_RL (1 << 1) 722 #define PQ_INIT_VF_RL (1 << 2) 723 724 /* defines for pq init */ 725 #define PQ_INIT_DEFAULT_WRR_GROUP 1 726 #define PQ_INIT_DEFAULT_TC 0 727 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc) 728 729 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn, 730 struct ecore_qm_info *qm_info, 731 u8 tc, u32 pq_init_flags) 732 { 733 u16 pq_idx = qm_info->num_pqs, max_pq = 734 ecore_init_qm_get_num_pqs(p_hwfn); 735 736 if (pq_idx > max_pq) 737 DP_ERR(p_hwfn, 738 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 739 740 /* init pq params */ 741 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; 742 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 743 qm_info->num_vports; 744 qm_info->qm_pq_params[pq_idx].tc_id = tc; 745 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 746 qm_info->qm_pq_params[pq_idx].rl_valid = 747 (pq_init_flags & PQ_INIT_PF_RL || 748 pq_init_flags & PQ_INIT_VF_RL); 749 750 /* qm params accounting */ 751 qm_info->num_pqs++; 752 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 753 qm_info->num_vports++; 754 755 if (pq_init_flags & PQ_INIT_PF_RL) 756 qm_info->num_pf_rls++; 757 758 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn)) 759 DP_ERR(p_hwfn, 760 "vport overflow! qm_info->num_vports %d," 761 " qm_init_get_num_vports() %d\n", 762 qm_info->num_vports, 763 ecore_init_qm_get_num_vports(p_hwfn)); 764 765 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn)) 766 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d," 767 " qm_init_get_num_pf_rls() %d\n", 768 qm_info->num_pf_rls, 769 ecore_init_qm_get_num_pf_rls(p_hwfn)); 770 } 771 772 /* get pq index according to PQ_FLAGS */ 773 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn, 774 u32 pq_flags) 775 { 776 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 777 778 /* Can't have multiple flags set here */ 779 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags, 780 sizeof(pq_flags)) > 1) 781 goto err; 782 783 switch (pq_flags) { 784 case PQ_FLAGS_RLS: 785 return &qm_info->first_rl_pq; 786 case PQ_FLAGS_MCOS: 787 return &qm_info->first_mcos_pq; 788 case PQ_FLAGS_LB: 789 return &qm_info->pure_lb_pq; 790 case PQ_FLAGS_OOO: 791 return &qm_info->ooo_pq; 792 case PQ_FLAGS_ACK: 793 return &qm_info->pure_ack_pq; 794 case PQ_FLAGS_OFLD: 795 return &qm_info->offload_pq; 796 case PQ_FLAGS_VFS: 797 return &qm_info->first_vf_pq; 798 default: 799 goto err; 800 } 801 802 err: 803 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags); 804 return OSAL_NULL; 805 } 806 807 /* save pq index in qm info */ 808 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn, 809 u32 pq_flags, u16 pq_val) 810 { 811 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 812 813 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 814 } 815 816 /* get tx pq index, with the PQ TX base already set (ready for context init) */ 817 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags) 818 { 819 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 820 821 return *base_pq_idx + CM_TX_PQ_BASE; 822 } 823 824 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc) 825 { 826 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn); 827 828 if (tc > max_tc) 829 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 830 831 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc; 832 } 833 834 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf) 835 { 836 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn); 837 838 if (vf > max_vf) 839 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 840 841 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf; 842 } 843 844 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl) 845 { 846 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn); 847 848 if (rl > max_rl) 849 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl); 850 851 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl; 852 } 853 854 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl) 855 { 856 u16 start_pq, pq, qm_pq_idx; 857 858 pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl); 859 start_pq = p_hwfn->qm_info.start_pq; 860 qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE; 861 862 if (qm_pq_idx > p_hwfn->qm_info.num_pqs) { 863 DP_ERR(p_hwfn, 864 "qm_pq_idx %d must be smaller than %d\n", 865 qm_pq_idx, p_hwfn->qm_info.num_pqs); 866 } 867 868 return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id; 869 } 870 871 /* Functions for creating specific types of pqs */ 872 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn) 873 { 874 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 875 876 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 877 return; 878 879 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 880 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 881 } 882 883 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn) 884 { 885 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 886 887 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 888 return; 889 890 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 891 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 892 } 893 894 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn) 895 { 896 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 897 898 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 899 return; 900 901 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 902 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 903 } 904 905 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn) 906 { 907 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 908 909 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 910 return; 911 912 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 913 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 914 } 915 916 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn) 917 { 918 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 919 u8 tc_idx; 920 921 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 922 return; 923 924 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 925 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++) 926 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 927 } 928 929 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn) 930 { 931 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 932 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn); 933 934 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 935 return; 936 937 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 938 939 qm_info->num_vf_pqs = num_vfs; 940 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 941 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC, 942 PQ_INIT_VF_RL); 943 } 944 945 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn) 946 { 947 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn); 948 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 949 950 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 951 return; 952 953 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 954 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 955 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, 956 PQ_INIT_PF_RL); 957 } 958 959 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn) 960 { 961 /* rate limited pqs, must come first (FW assumption) */ 962 ecore_init_qm_rl_pqs(p_hwfn); 963 964 /* pqs for multi cos */ 965 ecore_init_qm_mcos_pqs(p_hwfn); 966 967 /* pure loopback pq */ 968 ecore_init_qm_lb_pq(p_hwfn); 969 970 /* out of order pq */ 971 ecore_init_qm_ooo_pq(p_hwfn); 972 973 /* pure ack pq */ 974 ecore_init_qm_pure_ack_pq(p_hwfn); 975 976 /* pq for offloaded protocol */ 977 ecore_init_qm_offload_pq(p_hwfn); 978 979 /* done sharing vports */ 980 ecore_init_qm_advance_vport(p_hwfn); 981 982 /* pqs for vfs */ 983 ecore_init_qm_vf_pqs(p_hwfn); 984 } 985 986 /* compare values of getters against resources amounts */ 987 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn) 988 { 989 if (ecore_init_qm_get_num_vports(p_hwfn) > 990 RESC_NUM(p_hwfn, ECORE_VPORT)) { 991 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 992 return ECORE_INVAL; 993 } 994 995 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) { 996 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 997 return ECORE_INVAL; 998 } 999 1000 return ECORE_SUCCESS; 1001 } 1002 1003 /* 1004 * Function for verbose printing of the qm initialization results 1005 */ 1006 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn) 1007 { 1008 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1009 struct init_qm_vport_params *vport; 1010 struct init_qm_port_params *port; 1011 struct init_qm_pq_params *pq; 1012 int i, tc; 1013 1014 /* top level params */ 1015 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 1016 "qm init top level params: start_pq %d, start_vport %d," 1017 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n", 1018 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq, 1019 qm_info->offload_pq, qm_info->pure_ack_pq); 1020 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 1021 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d," 1022 " num_vports %d, max_phys_tcs_per_port %d\n", 1023 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs, 1024 qm_info->num_vf_pqs, qm_info->num_vports, 1025 qm_info->max_phys_tcs_per_port); 1026 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 1027 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d," 1028 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 1029 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en, 1030 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl, 1031 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn)); 1032 1033 /* port table */ 1034 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) { 1035 port = &qm_info->qm_port_params[i]; 1036 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 1037 "port idx %d, active %d, active_phys_tcs %d," 1038 " num_pbf_cmd_lines %d, num_btb_blocks %d," 1039 " reserved %d\n", 1040 i, port->active, port->active_phys_tcs, 1041 port->num_pbf_cmd_lines, port->num_btb_blocks, 1042 port->reserved); 1043 } 1044 1045 /* vport table */ 1046 for (i = 0; i < qm_info->num_vports; i++) { 1047 vport = &qm_info->qm_vport_params[i]; 1048 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 1049 "vport idx %d, vport_rl %d, wfq %d," 1050 " first_tx_pq_id [ ", 1051 qm_info->start_vport + i, vport->vport_rl, 1052 vport->vport_wfq); 1053 for (tc = 0; tc < NUM_OF_TCS; tc++) 1054 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ", 1055 vport->first_tx_pq_id[tc]); 1056 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n"); 1057 } 1058 1059 /* pq table */ 1060 for (i = 0; i < qm_info->num_pqs; i++) { 1061 pq = &qm_info->qm_pq_params[i]; 1062 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 1063 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", 1064 qm_info->start_pq + i, pq->port_id, pq->vport_id, 1065 pq->tc_id, pq->wrr_group, pq->rl_valid); 1066 } 1067 } 1068 1069 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn) 1070 { 1071 /* reset params required for init run */ 1072 ecore_init_qm_reset_params(p_hwfn); 1073 1074 /* init QM top level params */ 1075 ecore_init_qm_params(p_hwfn); 1076 1077 /* init QM port params */ 1078 ecore_init_qm_port_params(p_hwfn); 1079 1080 /* init QM vport params */ 1081 ecore_init_qm_vport_params(p_hwfn); 1082 1083 /* init QM physical queue params */ 1084 ecore_init_qm_pq_params(p_hwfn); 1085 1086 /* display all that init */ 1087 ecore_dp_init_qm_params(p_hwfn); 1088 } 1089 1090 /* This function reconfigures the QM pf on the fly. 1091 * For this purpose we: 1092 * 1. reconfigure the QM database 1093 * 2. set new values to runtime array 1094 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 1095 * 4. activate init tool in QM_PF stage 1096 * 5. send an sdm_qm_cmd through rbc interface to release the QM 1097 */ 1098 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn, 1099 struct ecore_ptt *p_ptt) 1100 { 1101 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1102 bool b_rc; 1103 enum _ecore_status_t rc; 1104 1105 /* initialize ecore's qm data structure */ 1106 ecore_init_qm_info(p_hwfn); 1107 1108 /* stop PF's qm queues */ 1109 OSAL_SPIN_LOCK(&qm_lock); 1110 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 1111 qm_info->start_pq, qm_info->num_pqs); 1112 OSAL_SPIN_UNLOCK(&qm_lock); 1113 if (!b_rc) 1114 return ECORE_INVAL; 1115 1116 /* clear the QM_PF runtime phase leftovers from previous init */ 1117 ecore_init_clear_rt_data(p_hwfn); 1118 1119 /* prepare QM portion of runtime array */ 1120 ecore_qm_init_pf(p_hwfn, p_ptt, false); 1121 1122 /* activate init tool on runtime array */ 1123 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 1124 p_hwfn->hw_info.hw_mode); 1125 if (rc != ECORE_SUCCESS) 1126 return rc; 1127 1128 /* start PF's qm queues */ 1129 OSAL_SPIN_LOCK(&qm_lock); 1130 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 1131 qm_info->start_pq, qm_info->num_pqs); 1132 OSAL_SPIN_UNLOCK(&qm_lock); 1133 if (!b_rc) 1134 return ECORE_INVAL; 1135 1136 return ECORE_SUCCESS; 1137 } 1138 1139 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn) 1140 { 1141 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1142 enum _ecore_status_t rc; 1143 1144 rc = ecore_init_qm_sanity(p_hwfn); 1145 if (rc != ECORE_SUCCESS) 1146 goto alloc_err; 1147 1148 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 1149 sizeof(struct init_qm_pq_params) * 1150 ecore_init_qm_get_num_pqs(p_hwfn)); 1151 if (!qm_info->qm_pq_params) 1152 goto alloc_err; 1153 1154 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 1155 sizeof(struct init_qm_vport_params) * 1156 ecore_init_qm_get_num_vports(p_hwfn)); 1157 if (!qm_info->qm_vport_params) 1158 goto alloc_err; 1159 1160 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 1161 sizeof(struct init_qm_port_params) * 1162 p_hwfn->p_dev->num_ports_in_engine); 1163 if (!qm_info->qm_port_params) 1164 goto alloc_err; 1165 1166 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 1167 sizeof(struct ecore_wfq_data) * 1168 ecore_init_qm_get_num_vports(p_hwfn)); 1169 if (!qm_info->wfq_data) 1170 goto alloc_err; 1171 1172 return ECORE_SUCCESS; 1173 1174 alloc_err: 1175 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n"); 1176 ecore_qm_info_free(p_hwfn); 1177 return ECORE_NOMEM; 1178 } 1179 /******************** End QM initialization ***************/ 1180 1181 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev) 1182 { 1183 enum _ecore_status_t rc = ECORE_SUCCESS; 1184 int i; 1185 1186 if (IS_VF(p_dev)) { 1187 for_each_hwfn(p_dev, i) { 1188 rc = ecore_l2_alloc(&p_dev->hwfns[i]); 1189 if (rc != ECORE_SUCCESS) 1190 return rc; 1191 } 1192 return rc; 1193 } 1194 1195 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL, 1196 sizeof(*p_dev->fw_data)); 1197 if (!p_dev->fw_data) 1198 return ECORE_NOMEM; 1199 1200 for_each_hwfn(p_dev, i) { 1201 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1202 u32 n_eqes, num_cons; 1203 1204 /* initialize the doorbell recovery mechanism */ 1205 rc = ecore_db_recovery_setup(p_hwfn); 1206 if (rc) 1207 goto alloc_err; 1208 1209 /* First allocate the context manager structure */ 1210 rc = ecore_cxt_mngr_alloc(p_hwfn); 1211 if (rc) 1212 goto alloc_err; 1213 1214 /* Set the HW cid/tid numbers (in the context manager) 1215 * Must be done prior to any further computations. 1216 */ 1217 rc = ecore_cxt_set_pf_params(p_hwfn); 1218 if (rc) 1219 goto alloc_err; 1220 1221 rc = ecore_alloc_qm_data(p_hwfn); 1222 if (rc) 1223 goto alloc_err; 1224 1225 /* init qm info */ 1226 ecore_init_qm_info(p_hwfn); 1227 1228 /* Compute the ILT client partition */ 1229 rc = ecore_cxt_cfg_ilt_compute(p_hwfn); 1230 if (rc) 1231 goto alloc_err; 1232 1233 /* CID map / ILT shadow table / T2 1234 * The talbes sizes are determined by the computations above 1235 */ 1236 rc = ecore_cxt_tables_alloc(p_hwfn); 1237 if (rc) 1238 goto alloc_err; 1239 1240 /* SPQ, must follow ILT because initializes SPQ context */ 1241 rc = ecore_spq_alloc(p_hwfn); 1242 if (rc) 1243 goto alloc_err; 1244 1245 /* SP status block allocation */ 1246 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn, 1247 RESERVED_PTT_DPC); 1248 1249 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 1250 if (rc) 1251 goto alloc_err; 1252 1253 rc = ecore_iov_alloc(p_hwfn); 1254 if (rc) 1255 goto alloc_err; 1256 1257 /* EQ */ 1258 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain); 1259 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) { 1260 /* Calculate the EQ size 1261 * --------------------- 1262 * Each ICID may generate up to one event at a time i.e. 1263 * the event must be handled/cleared before a new one 1264 * can be generated. We calculate the sum of events per 1265 * protocol and create an EQ deep enough to handle the 1266 * worst case: 1267 * - Core - according to SPQ. 1268 * - RoCE - per QP there are a couple of ICIDs, one 1269 * responder and one requester, each can 1270 * generate an EQE => n_eqes_qp = 2 * n_qp. 1271 * Each CQ can generate an EQE. There are 2 CQs 1272 * per QP => n_eqes_cq = 2 * n_qp. 1273 * Hence the RoCE total is 4 * n_qp or 1274 * 2 * num_cons. 1275 * - ENet - There can be up to two events per VF. One 1276 * for VF-PF channel and another for VF FLR 1277 * initial cleanup. The number of VFs is 1278 * bounded by MAX_NUM_VFS_BB, and is much 1279 * smaller than RoCE's so we avoid exact 1280 * calculation. 1281 */ 1282 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) { 1283 num_cons = 1284 ecore_cxt_get_proto_cid_count( 1285 p_hwfn, 1286 PROTOCOLID_ROCE, 1287 OSAL_NULL); 1288 num_cons *= 2; 1289 } else { 1290 num_cons = ecore_cxt_get_proto_cid_count( 1291 p_hwfn, 1292 PROTOCOLID_IWARP, 1293 OSAL_NULL); 1294 } 1295 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 1296 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) { 1297 num_cons = 1298 ecore_cxt_get_proto_cid_count(p_hwfn, 1299 PROTOCOLID_ISCSI, 1300 OSAL_NULL); 1301 n_eqes += 2 * num_cons; 1302 } 1303 1304 if (n_eqes > 0xFFFF) { 1305 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements." 1306 "The maximum of a u16 chain is 0x%x\n", 1307 n_eqes, 0xFFFF); 1308 goto alloc_no_mem; 1309 } 1310 1311 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes); 1312 if (rc) 1313 goto alloc_err; 1314 1315 rc = ecore_consq_alloc(p_hwfn); 1316 if (rc) 1317 goto alloc_err; 1318 1319 rc = ecore_l2_alloc(p_hwfn); 1320 if (rc != ECORE_SUCCESS) 1321 goto alloc_err; 1322 1323 /* DMA info initialization */ 1324 rc = ecore_dmae_info_alloc(p_hwfn); 1325 if (rc) { 1326 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n"); 1327 goto alloc_err; 1328 } 1329 1330 /* DCBX initialization */ 1331 rc = ecore_dcbx_info_alloc(p_hwfn); 1332 if (rc) { 1333 DP_NOTICE(p_hwfn, false, 1334 "Failed to allocate memory for dcbx structure\n"); 1335 goto alloc_err; 1336 } 1337 } 1338 1339 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL, 1340 sizeof(*p_dev->reset_stats)); 1341 if (!p_dev->reset_stats) { 1342 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n"); 1343 goto alloc_no_mem; 1344 } 1345 1346 return ECORE_SUCCESS; 1347 1348 alloc_no_mem: 1349 rc = ECORE_NOMEM; 1350 alloc_err: 1351 ecore_resc_free(p_dev); 1352 return rc; 1353 } 1354 1355 void ecore_resc_setup(struct ecore_dev *p_dev) 1356 { 1357 int i; 1358 1359 if (IS_VF(p_dev)) { 1360 for_each_hwfn(p_dev, i) 1361 ecore_l2_setup(&p_dev->hwfns[i]); 1362 return; 1363 } 1364 1365 for_each_hwfn(p_dev, i) { 1366 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1367 1368 ecore_cxt_mngr_setup(p_hwfn); 1369 ecore_spq_setup(p_hwfn); 1370 ecore_eq_setup(p_hwfn); 1371 ecore_consq_setup(p_hwfn); 1372 1373 /* Read shadow of current MFW mailbox */ 1374 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 1375 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow, 1376 p_hwfn->mcp_info->mfw_mb_cur, 1377 p_hwfn->mcp_info->mfw_mb_length); 1378 1379 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt); 1380 1381 ecore_l2_setup(p_hwfn); 1382 ecore_iov_setup(p_hwfn); 1383 } 1384 } 1385 1386 #define FINAL_CLEANUP_POLL_CNT (100) 1387 #define FINAL_CLEANUP_POLL_TIME (10) 1388 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn, 1389 struct ecore_ptt *p_ptt, 1390 u16 id, bool is_vf) 1391 { 1392 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 1393 enum _ecore_status_t rc = ECORE_TIMEOUT; 1394 1395 #ifndef ASIC_ONLY 1396 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) || 1397 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 1398 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n"); 1399 return ECORE_SUCCESS; 1400 } 1401 #endif 1402 1403 addr = GTT_BAR0_MAP_REG_USDM_RAM + 1404 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 1405 1406 if (is_vf) 1407 id += 0x10; 1408 1409 command |= X_FINAL_CLEANUP_AGG_INT << 1410 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 1411 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 1412 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 1413 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 1414 1415 /* Make sure notification is not set before initiating final cleanup */ 1416 1417 if (REG_RD(p_hwfn, addr)) { 1418 DP_NOTICE(p_hwfn, false, 1419 "Unexpected; Found final cleanup notification"); 1420 DP_NOTICE(p_hwfn, false, 1421 " before initiating final cleanup\n"); 1422 REG_WR(p_hwfn, addr, 0); 1423 } 1424 1425 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, 1426 "Sending final cleanup for PFVF[%d] [Command %08x]\n", 1427 id, command); 1428 1429 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 1430 1431 /* Poll until completion */ 1432 while (!REG_RD(p_hwfn, addr) && count--) 1433 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME); 1434 1435 if (REG_RD(p_hwfn, addr)) 1436 rc = ECORE_SUCCESS; 1437 else 1438 DP_NOTICE(p_hwfn, true, 1439 "Failed to receive FW final cleanup notification\n"); 1440 1441 /* Cleanup afterwards */ 1442 REG_WR(p_hwfn, addr, 0); 1443 1444 return rc; 1445 } 1446 1447 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn) 1448 { 1449 int hw_mode = 0; 1450 1451 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) { 1452 hw_mode |= 1 << MODE_BB; 1453 } else if (ECORE_IS_AH(p_hwfn->p_dev)) { 1454 hw_mode |= 1 << MODE_K2; 1455 } else { 1456 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n", 1457 p_hwfn->p_dev->type); 1458 return ECORE_INVAL; 1459 } 1460 1461 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */ 1462 switch (p_hwfn->p_dev->num_ports_in_engine) { 1463 case 1: 1464 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 1465 break; 1466 case 2: 1467 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 1468 break; 1469 case 4: 1470 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 1471 break; 1472 default: 1473 DP_NOTICE(p_hwfn, true, 1474 "num_ports_in_engine = %d not supported\n", 1475 p_hwfn->p_dev->num_ports_in_engine); 1476 return ECORE_INVAL; 1477 } 1478 1479 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, 1480 &p_hwfn->p_dev->mf_bits)) 1481 hw_mode |= 1 << MODE_MF_SD; 1482 else 1483 hw_mode |= 1 << MODE_MF_SI; 1484 1485 #ifndef ASIC_ONLY 1486 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 1487 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 1488 hw_mode |= 1 << MODE_FPGA; 1489 } else { 1490 if (p_hwfn->p_dev->b_is_emul_full) 1491 hw_mode |= 1 << MODE_EMUL_FULL; 1492 else 1493 hw_mode |= 1 << MODE_EMUL_REDUCED; 1494 } 1495 } else 1496 #endif 1497 hw_mode |= 1 << MODE_ASIC; 1498 1499 if (ECORE_IS_CMT(p_hwfn->p_dev)) 1500 hw_mode |= 1 << MODE_100G; 1501 1502 p_hwfn->hw_info.hw_mode = hw_mode; 1503 1504 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP), 1505 "Configuring function for hw_mode: 0x%08x\n", 1506 p_hwfn->hw_info.hw_mode); 1507 1508 return ECORE_SUCCESS; 1509 } 1510 1511 #ifndef ASIC_ONLY 1512 /* MFW-replacement initializations for non-ASIC */ 1513 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn, 1514 struct ecore_ptt *p_ptt) 1515 { 1516 struct ecore_dev *p_dev = p_hwfn->p_dev; 1517 u32 pl_hv = 1; 1518 int i; 1519 1520 if (CHIP_REV_IS_EMUL(p_dev)) { 1521 if (ECORE_IS_AH(p_dev)) 1522 pl_hv |= 0x600; 1523 } 1524 1525 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv); 1526 1527 if (CHIP_REV_IS_EMUL(p_dev) && 1528 (ECORE_IS_AH(p_dev))) 1529 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5, 1530 0x3ffffff); 1531 1532 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */ 1533 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */ 1534 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev)) 1535 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4); 1536 1537 if (CHIP_REV_IS_EMUL(p_dev)) { 1538 if (ECORE_IS_AH(p_dev)) { 1539 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */ 1540 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE, 1541 (p_dev->num_ports_in_engine >> 1)); 1542 1543 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN, 1544 p_dev->num_ports_in_engine == 4 ? 0 : 3); 1545 } 1546 } 1547 1548 /* Poll on RBC */ 1549 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1); 1550 for (i = 0; i < 100; i++) { 1551 OSAL_UDELAY(50); 1552 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1) 1553 break; 1554 } 1555 if (i == 100) 1556 DP_NOTICE(p_hwfn, true, 1557 "RBC done failed to complete in PSWRQ2\n"); 1558 1559 return ECORE_SUCCESS; 1560 } 1561 #endif 1562 1563 /* Init run time data for all PFs and their VFs on an engine. 1564 * TBD - for VFs - Once we have parent PF info for each VF in 1565 * shmem available as CAU requires knowledge of parent PF for each VF. 1566 */ 1567 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev) 1568 { 1569 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 1570 int i, igu_sb_id; 1571 1572 for_each_hwfn(p_dev, i) { 1573 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1574 struct ecore_igu_info *p_igu_info; 1575 struct ecore_igu_block *p_block; 1576 struct cau_sb_entry sb_entry; 1577 1578 p_igu_info = p_hwfn->hw_info.p_igu_info; 1579 1580 for (igu_sb_id = 0; 1581 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev); 1582 igu_sb_id++) { 1583 p_block = &p_igu_info->entry[igu_sb_id]; 1584 1585 if (!p_block->is_pf) 1586 continue; 1587 1588 ecore_init_cau_sb_entry(p_hwfn, &sb_entry, 1589 p_block->function_id, 0, 0); 1590 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 1591 sb_entry); 1592 } 1593 } 1594 } 1595 1596 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn, 1597 struct ecore_ptt *p_ptt) 1598 { 1599 u32 val, wr_mbs, cache_line_size; 1600 1601 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 1602 switch (val) { 1603 case 0: 1604 wr_mbs = 128; 1605 break; 1606 case 1: 1607 wr_mbs = 256; 1608 break; 1609 case 2: 1610 wr_mbs = 512; 1611 break; 1612 default: 1613 DP_INFO(p_hwfn, 1614 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 1615 val); 1616 return; 1617 } 1618 1619 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs); 1620 switch (cache_line_size) { 1621 case 32: 1622 val = 0; 1623 break; 1624 case 64: 1625 val = 1; 1626 break; 1627 case 128: 1628 val = 2; 1629 break; 1630 case 256: 1631 val = 3; 1632 break; 1633 default: 1634 DP_INFO(p_hwfn, 1635 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 1636 cache_line_size); 1637 } 1638 1639 if (wr_mbs < OSAL_CACHE_LINE_SIZE) 1640 DP_INFO(p_hwfn, 1641 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 1642 OSAL_CACHE_LINE_SIZE, wr_mbs); 1643 1644 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 1645 if (val > 0) { 1646 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 1647 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 1648 } 1649 } 1650 1651 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn, 1652 struct ecore_ptt *p_ptt, 1653 int hw_mode) 1654 { 1655 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1656 struct ecore_dev *p_dev = p_hwfn->p_dev; 1657 u8 vf_id, max_num_vfs; 1658 u16 num_pfs, pf_id; 1659 u32 concrete_fid; 1660 enum _ecore_status_t rc = ECORE_SUCCESS; 1661 1662 ecore_init_cau_rt_data(p_dev); 1663 1664 /* Program GTT windows */ 1665 ecore_gtt_init(p_hwfn, p_ptt); 1666 1667 #ifndef ASIC_ONLY 1668 if (CHIP_REV_IS_EMUL(p_dev)) { 1669 rc = ecore_hw_init_chip(p_hwfn, p_ptt); 1670 if (rc != ECORE_SUCCESS) 1671 return rc; 1672 } 1673 #endif 1674 1675 if (p_hwfn->mcp_info) { 1676 if (p_hwfn->mcp_info->func_info.bandwidth_max) 1677 qm_info->pf_rl_en = 1; 1678 if (p_hwfn->mcp_info->func_info.bandwidth_min) 1679 qm_info->pf_wfq_en = 1; 1680 } 1681 1682 ecore_qm_common_rt_init(p_hwfn, 1683 p_dev->num_ports_in_engine, 1684 qm_info->max_phys_tcs_per_port, 1685 qm_info->pf_rl_en, qm_info->pf_wfq_en, 1686 qm_info->vport_rl_en, qm_info->vport_wfq_en, 1687 qm_info->qm_port_params); 1688 1689 ecore_cxt_hw_init_common(p_hwfn); 1690 1691 ecore_init_cache_line_size(p_hwfn, p_ptt); 1692 1693 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn), 1694 hw_mode); 1695 if (rc != ECORE_SUCCESS) 1696 return rc; 1697 1698 /* @@TBD MichalK - should add VALIDATE_VFID to init tool... 1699 * need to decide with which value, maybe runtime 1700 */ 1701 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 1702 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 1703 1704 if (ECORE_IS_BB(p_dev)) { 1705 /* Workaround clears ROCE search for all functions to prevent 1706 * involving non initialized function in processing ROCE packet. 1707 */ 1708 num_pfs = NUM_OF_ENG_PFS(p_dev); 1709 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 1710 ecore_fid_pretend(p_hwfn, p_ptt, pf_id); 1711 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1712 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1713 } 1714 /* pretend to original PF */ 1715 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1716 } 1717 1718 /* Workaround for avoiding CCFC execution error when getting packets 1719 * with CRC errors, and allowing instead the invoking of the FW error 1720 * handler. 1721 * This is not done inside the init tool since it currently can't 1722 * perform a pretending to VFs. 1723 */ 1724 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 1725 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 1726 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id); 1727 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid); 1728 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 1729 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 1730 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 1731 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 1732 } 1733 /* pretend to original PF */ 1734 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1735 1736 return rc; 1737 } 1738 1739 #ifndef ASIC_ONLY 1740 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4) 1741 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5) 1742 1743 #define PMEG_IF_BYTE_COUNT 8 1744 1745 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn, 1746 struct ecore_ptt *p_ptt, 1747 u32 addr, u64 data, u8 reg_type, u8 port) 1748 { 1749 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 1750 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n", 1751 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) | 1752 (8 << PMEG_IF_BYTE_COUNT), 1753 (reg_type << 25) | (addr << 8) | port, 1754 (u32)((data >> 32) & 0xffffffff), 1755 (u32)(data & 0xffffffff)); 1756 1757 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB, 1758 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) & 1759 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT)); 1760 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB, 1761 (reg_type << 25) | (addr << 8) | port); 1762 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff); 1763 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, 1764 (data >> 32) & 0xffffffff); 1765 } 1766 1767 #define XLPORT_MODE_REG (0x20a) 1768 #define XLPORT_MAC_CONTROL (0x210) 1769 #define XLPORT_FLOW_CONTROL_CONFIG (0x207) 1770 #define XLPORT_ENABLE_REG (0x20b) 1771 1772 #define XLMAC_CTRL (0x600) 1773 #define XLMAC_MODE (0x601) 1774 #define XLMAC_RX_MAX_SIZE (0x608) 1775 #define XLMAC_TX_CTRL (0x604) 1776 #define XLMAC_PAUSE_CTRL (0x60d) 1777 #define XLMAC_PFC_CTRL (0x60e) 1778 1779 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn, 1780 struct ecore_ptt *p_ptt) 1781 { 1782 u8 loopback = 0, port = p_hwfn->port_id * 2; 1783 1784 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port); 1785 1786 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */ 1787 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1, 1788 port); 1789 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port); 1790 /* XLMAC: SOFT RESET */ 1791 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port); 1792 /* XLMAC: Port Speed >= 10Gbps */ 1793 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port); 1794 /* XLMAC: Max Size */ 1795 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port); 1796 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL, 1797 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38), 1798 0, port); 1799 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port); 1800 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL, 1801 0x30ffffc000ULL, 0, port); 1802 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0, 1803 port); /* XLMAC: TX_EN, RX_EN */ 1804 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */ 1805 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 1806 0x1003 | (loopback << 2), 0, port); 1807 /* Enabled Parallel PFC interface */ 1808 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port); 1809 1810 /* XLPORT port enable */ 1811 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port); 1812 } 1813 1814 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn, 1815 struct ecore_ptt *p_ptt) 1816 { 1817 u8 port = p_hwfn->port_id; 1818 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE; 1819 1820 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port); 1821 1822 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2), 1823 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) | 1824 (port << 1825 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) | 1826 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT)); 1827 1828 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5, 1829 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT); 1830 1831 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5, 1832 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT); 1833 1834 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5, 1835 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT); 1836 1837 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5, 1838 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT); 1839 1840 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5, 1841 (0xA << 1842 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) | 1843 (8 << 1844 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT)); 1845 1846 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5, 1847 0xa853); 1848 } 1849 1850 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn, 1851 struct ecore_ptt *p_ptt) 1852 { 1853 if (ECORE_IS_AH(p_hwfn->p_dev)) 1854 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt); 1855 else /* BB */ 1856 ecore_emul_link_init_bb(p_hwfn, p_ptt); 1857 } 1858 1859 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn, 1860 struct ecore_ptt *p_ptt, u8 port) 1861 { 1862 int port_offset = port ? 0x800 : 0; 1863 u32 xmac_rxctrl = 0; 1864 1865 /* Reset of XMAC */ 1866 /* FIXME: move to common start */ 1867 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32), 1868 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */ 1869 OSAL_MSLEEP(1); 1870 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32), 1871 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */ 1872 1873 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1); 1874 1875 /* Set the number of ports on the Warp Core to 10G */ 1876 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3); 1877 1878 /* Soft reset of XMAC */ 1879 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32), 1880 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT); 1881 OSAL_MSLEEP(1); 1882 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32), 1883 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT); 1884 1885 /* FIXME: move to common end */ 1886 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) 1887 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20); 1888 1889 /* Set Max packet size: initialize XMAC block register for port 0 */ 1890 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710); 1891 1892 /* CRC append for Tx packets: init XMAC block register for port 1 */ 1893 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800); 1894 1895 /* Enable TX and RX: initialize XMAC block register for port 1 */ 1896 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset, 1897 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB); 1898 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, 1899 XMAC_REG_RX_CTRL_BB + port_offset); 1900 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB; 1901 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl); 1902 } 1903 #endif 1904 1905 static enum _ecore_status_t 1906 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn, 1907 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 1908 { 1909 u32 dpi_bit_shift, dpi_count, dpi_page_size; 1910 u32 min_dpis; 1911 u32 n_wids; 1912 1913 /* Calculate DPI size 1914 * ------------------ 1915 * The PWM region contains Doorbell Pages. The first is reserverd for 1916 * the kernel for, e.g, L2. The others are free to be used by non- 1917 * trusted applications, typically from user space. Each page, called a 1918 * doorbell page is sectioned into windows that allow doorbells to be 1919 * issued in parallel by the kernel/application. The size of such a 1920 * window (a.k.a. WID) is 1kB. 1921 * Summary: 1922 * 1kB WID x N WIDS = DPI page size 1923 * DPI page size x N DPIs = PWM region size 1924 * Notes: 1925 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE 1926 * in order to ensure that two applications won't share the same page. 1927 * It also must contain at least one WID per CPU to allow parallelism. 1928 * It also must be a power of 2, since it is stored as a bit shift. 1929 * 1930 * The DPI page size is stored in a register as 'dpi_bit_shift' so that 1931 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096 1932 * containing 4 WIDs. 1933 */ 1934 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus); 1935 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids); 1936 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) & 1937 ~(OSAL_PAGE_SIZE - 1); 1938 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096); 1939 dpi_count = pwm_region_size / dpi_page_size; 1940 1941 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 1942 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis); 1943 1944 /* Update hwfn */ 1945 p_hwfn->dpi_size = dpi_page_size; 1946 p_hwfn->dpi_count = dpi_count; 1947 1948 /* Update registers */ 1949 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 1950 1951 if (dpi_count < min_dpis) 1952 return ECORE_NORESOURCES; 1953 1954 return ECORE_SUCCESS; 1955 } 1956 1957 enum ECORE_ROCE_EDPM_MODE { 1958 ECORE_ROCE_EDPM_MODE_ENABLE = 0, 1959 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1, 1960 ECORE_ROCE_EDPM_MODE_DISABLE = 2, 1961 }; 1962 1963 static enum _ecore_status_t 1964 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn, 1965 struct ecore_ptt *p_ptt) 1966 { 1967 u32 pwm_regsize, norm_regsize; 1968 u32 non_pwm_conn, min_addr_reg1; 1969 u32 db_bar_size, n_cpus; 1970 u32 roce_edpm_mode; 1971 u32 pf_dems_shift; 1972 enum _ecore_status_t rc = ECORE_SUCCESS; 1973 u8 cond; 1974 1975 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 1976 if (ECORE_IS_CMT(p_hwfn->p_dev)) 1977 db_bar_size /= 2; 1978 1979 /* Calculate doorbell regions 1980 * ----------------------------------- 1981 * The doorbell BAR is made of two regions. The first is called normal 1982 * region and the second is called PWM region. In the normal region 1983 * each ICID has its own set of addresses so that writing to that 1984 * specific address identifies the ICID. In the Process Window Mode 1985 * region the ICID is given in the data written to the doorbell. The 1986 * above per PF register denotes the offset in the doorbell BAR in which 1987 * the PWM region begins. 1988 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per 1989 * non-PWM connection. The calculation below computes the total non-PWM 1990 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is 1991 * in units of 4,096 bytes. 1992 */ 1993 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 1994 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 1995 OSAL_NULL) + 1996 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL); 1997 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 1998 OSAL_PAGE_SIZE); 1999 min_addr_reg1 = norm_regsize / 4096; 2000 pwm_regsize = db_bar_size - norm_regsize; 2001 2002 /* Check that the normal and PWM sizes are valid */ 2003 if (db_bar_size < norm_regsize) { 2004 DP_ERR(p_hwfn->p_dev, 2005 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 2006 db_bar_size, norm_regsize); 2007 return ECORE_NORESOURCES; 2008 } 2009 if (pwm_regsize < ECORE_MIN_PWM_REGION) { 2010 DP_ERR(p_hwfn->p_dev, 2011 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 2012 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size, 2013 norm_regsize); 2014 return ECORE_NORESOURCES; 2015 } 2016 2017 /* Calculate number of DPIs */ 2018 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 2019 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) || 2020 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) { 2021 /* Either EDPM is mandatory, or we are attempting to allocate a 2022 * WID per CPU. 2023 */ 2024 n_cpus = OSAL_NUM_CPUS(); 2025 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 2026 } 2027 2028 cond = ((rc != ECORE_SUCCESS) && 2029 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) || 2030 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE); 2031 if (cond || p_hwfn->dcbx_no_edpm) { 2032 /* Either EDPM is disabled from user configuration, or it is 2033 * disabled via DCBx, or it is not mandatory and we failed to 2034 * allocated a WID per CPU. 2035 */ 2036 n_cpus = 1; 2037 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 2038 2039 /* If we entered this flow due to DCBX then the DPM register is 2040 * already configured. 2041 */ 2042 } 2043 2044 DP_INFO(p_hwfn, 2045 "doorbell bar: normal_region_size=%d, pwm_region_size=%d", 2046 norm_regsize, pwm_regsize); 2047 DP_INFO(p_hwfn, 2048 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 2049 p_hwfn->dpi_size, p_hwfn->dpi_count, 2050 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 2051 "disabled" : "enabled"); 2052 2053 /* Check return codes from above calls */ 2054 if (rc != ECORE_SUCCESS) { 2055 DP_ERR(p_hwfn, 2056 "Failed to allocate enough DPIs\n"); 2057 return ECORE_NORESOURCES; 2058 } 2059 2060 /* Update hwfn */ 2061 p_hwfn->dpi_start_offset = norm_regsize; 2062 2063 /* Update registers */ 2064 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 2065 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4); 2066 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 2067 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 2068 2069 return ECORE_SUCCESS; 2070 } 2071 2072 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn, 2073 struct ecore_ptt *p_ptt, 2074 int hw_mode) 2075 { 2076 u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE]; 2077 u32 val; 2078 enum _ecore_status_t rc = ECORE_SUCCESS; 2079 u8 i; 2080 2081 /* In CMT for non-RoCE packets - use connection based classification */ 2082 val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0; 2083 for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++) 2084 ppf_to_eng_sel[i] = val; 2085 STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET, 2086 ppf_to_eng_sel); 2087 2088 /* In CMT the gate should be cleared by the 2nd hwfn */ 2089 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn)) 2090 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0); 2091 2092 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, 2093 hw_mode); 2094 if (rc != ECORE_SUCCESS) 2095 return rc; 2096 2097 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 2098 2099 #ifndef ASIC_ONLY 2100 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) 2101 return ECORE_SUCCESS; 2102 2103 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 2104 if (ECORE_IS_AH(p_hwfn->p_dev)) 2105 return ECORE_SUCCESS; 2106 else if (ECORE_IS_BB(p_hwfn->p_dev)) 2107 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id); 2108 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 2109 if (ECORE_IS_CMT(p_hwfn->p_dev)) { 2110 /* Activate OPTE in CMT */ 2111 u32 val; 2112 2113 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV); 2114 val |= 0x10; 2115 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val); 2116 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1); 2117 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1); 2118 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1); 2119 ecore_wr(p_hwfn, p_ptt, 2120 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1); 2121 ecore_wr(p_hwfn, p_ptt, 2122 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555); 2123 ecore_wr(p_hwfn, p_ptt, 2124 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4, 2125 0x55555555); 2126 } 2127 2128 ecore_emul_link_init(p_hwfn, p_ptt); 2129 } else { 2130 DP_INFO(p_hwfn->p_dev, "link is not being configured\n"); 2131 } 2132 #endif 2133 2134 return rc; 2135 } 2136 2137 static enum _ecore_status_t 2138 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, 2139 struct ecore_ptt *p_ptt, 2140 struct ecore_tunnel_info *p_tunn, 2141 int hw_mode, 2142 bool b_hw_start, 2143 enum ecore_int_mode int_mode, bool allow_npar_tx_switch) 2144 { 2145 u8 rel_pf_id = p_hwfn->rel_pf_id; 2146 u32 prs_reg; 2147 enum _ecore_status_t rc = ECORE_SUCCESS; 2148 u16 ctrl; 2149 int pos; 2150 2151 if (p_hwfn->mcp_info) { 2152 struct ecore_mcp_function_info *p_info; 2153 2154 p_info = &p_hwfn->mcp_info->func_info; 2155 if (p_info->bandwidth_min) 2156 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 2157 2158 /* Update rate limit once we'll actually have a link */ 2159 p_hwfn->qm_info.pf_rl = 100000; 2160 } 2161 ecore_cxt_hw_init_pf(p_hwfn, p_ptt); 2162 2163 ecore_int_igu_init_rt(p_hwfn); 2164 2165 /* Set VLAN in NIG if needed */ 2166 if (hw_mode & (1 << MODE_MF_SD)) { 2167 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 2168 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 2169 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 2170 p_hwfn->hw_info.ovlan); 2171 2172 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 2173 "Configuring LLH_FUNC_FILTER_HDR_SEL\n"); 2174 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET, 2175 1); 2176 } 2177 2178 /* Enable classification by MAC if needed */ 2179 if (hw_mode & (1 << MODE_MF_SI)) { 2180 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 2181 "Configuring TAGMAC_CLS_TYPE\n"); 2182 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 2183 1); 2184 } 2185 2186 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */ 2187 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 2188 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0); 2189 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 2190 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0); 2191 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 2192 2193 /* perform debug configuration when chip is out of reset */ 2194 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id); 2195 2196 /* Sanity check before the PF init sequence that uses DMAE */ 2197 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase"); 2198 if (rc) 2199 return rc; 2200 2201 /* PF Init sequence */ 2202 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 2203 if (rc) 2204 return rc; 2205 2206 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 2207 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 2208 if (rc) 2209 return rc; 2210 2211 /* Pure runtime initializations - directly to the HW */ 2212 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 2213 2214 /* PCI relaxed ordering causes a decrease in the performance on some 2215 * systems. Till a root cause is found, disable this attribute in the 2216 * PCI config space. 2217 */ 2218 /* Not in use @DPDK 2219 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP); 2220 * if (!pos) { 2221 * DP_NOTICE(p_hwfn, true, 2222 * "Failed to find the PCIe Cap\n"); 2223 * return ECORE_IO; 2224 * } 2225 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl); 2226 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN; 2227 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl); 2228 */ 2229 2230 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 2231 if (rc) 2232 return rc; 2233 if (b_hw_start) { 2234 /* enable interrupts */ 2235 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode); 2236 if (rc != ECORE_SUCCESS) 2237 return rc; 2238 2239 /* send function start command */ 2240 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn, 2241 allow_npar_tx_switch); 2242 if (rc) { 2243 DP_NOTICE(p_hwfn, true, 2244 "Function start ramrod failed\n"); 2245 } else { 2246 return rc; 2247 } 2248 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1); 2249 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 2250 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg); 2251 2252 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) { 2253 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, 2254 (1 << 2)); 2255 ecore_wr(p_hwfn, p_ptt, 2256 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 2257 0x100); 2258 } 2259 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 2260 "PRS_REG_SEARCH registers after start PFn\n"); 2261 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP); 2262 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 2263 "PRS_REG_SEARCH_TCP: %x\n", prs_reg); 2264 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP); 2265 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 2266 "PRS_REG_SEARCH_UDP: %x\n", prs_reg); 2267 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE); 2268 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 2269 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg); 2270 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE); 2271 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 2272 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg); 2273 prs_reg = ecore_rd(p_hwfn, p_ptt, 2274 PRS_REG_SEARCH_TCP_FIRST_FRAG); 2275 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 2276 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n", 2277 prs_reg); 2278 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1); 2279 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 2280 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg); 2281 } 2282 return ECORE_SUCCESS; 2283 } 2284 2285 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn, 2286 struct ecore_ptt *p_ptt, 2287 bool b_enable) 2288 { 2289 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0; 2290 2291 /* Configure the PF's internal FID_enable for master transactions */ 2292 ecore_wr(p_hwfn, p_ptt, 2293 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 2294 2295 /* Wait until value is set - try for 1 second every 50us */ 2296 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 2297 val = ecore_rd(p_hwfn, p_ptt, 2298 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 2299 if (val == set_val) 2300 break; 2301 2302 OSAL_UDELAY(50); 2303 } 2304 2305 if (val != set_val) { 2306 DP_NOTICE(p_hwfn, true, 2307 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 2308 return ECORE_UNKNOWN_ERROR; 2309 } 2310 2311 return ECORE_SUCCESS; 2312 } 2313 2314 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn, 2315 struct ecore_ptt *p_main_ptt) 2316 { 2317 /* Read shadow of current MFW mailbox */ 2318 ecore_mcp_read_mb(p_hwfn, p_main_ptt); 2319 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow, 2320 p_hwfn->mcp_info->mfw_mb_cur, 2321 p_hwfn->mcp_info->mfw_mb_length); 2322 } 2323 2324 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn, 2325 struct ecore_ptt *p_ptt) 2326 { 2327 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 2328 1 << p_hwfn->abs_pf_id); 2329 } 2330 2331 static enum _ecore_status_t 2332 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn, 2333 struct ecore_load_req_params *p_load_req, 2334 struct ecore_drv_load_params *p_drv_load) 2335 { 2336 /* Make sure that if ecore-client didn't provide inputs, all the 2337 * expected defaults are indeed zero. 2338 */ 2339 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0); 2340 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0); 2341 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0); 2342 2343 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req)); 2344 2345 if (p_drv_load == OSAL_NULL) 2346 goto out; 2347 2348 p_load_req->drv_role = p_drv_load->is_crash_kernel ? 2349 ECORE_DRV_ROLE_KDUMP : 2350 ECORE_DRV_ROLE_OS; 2351 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 2352 p_load_req->override_force_load = p_drv_load->override_force_load; 2353 2354 /* Old MFW versions don't support timeout values other than default and 2355 * none, so these values are replaced according to the fall-back action. 2356 */ 2357 2358 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT || 2359 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE || 2360 (p_hwfn->mcp_info->capabilities & 2361 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) { 2362 p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 2363 goto out; 2364 } 2365 2366 switch (p_drv_load->mfw_timeout_fallback) { 2367 case ECORE_TO_FALLBACK_TO_NONE: 2368 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE; 2369 break; 2370 case ECORE_TO_FALLBACK_TO_DEFAULT: 2371 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT; 2372 break; 2373 case ECORE_TO_FALLBACK_FAIL_LOAD: 2374 DP_NOTICE(p_hwfn, false, 2375 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n", 2376 p_drv_load->mfw_timeout_val, 2377 ECORE_LOAD_REQ_LOCK_TO_DEFAULT, 2378 ECORE_LOAD_REQ_LOCK_TO_NONE); 2379 return ECORE_ABORTED; 2380 } 2381 2382 DP_INFO(p_hwfn, 2383 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n", 2384 p_drv_load->mfw_timeout_val, 2385 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ? 2386 "default" : "none", 2387 p_load_req->timeout_val); 2388 out: 2389 return ECORE_SUCCESS; 2390 } 2391 2392 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn, 2393 struct ecore_hw_init_params *p_params) 2394 { 2395 if (p_params->p_tunn) { 2396 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 2397 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 2398 } 2399 2400 p_hwfn->b_int_enabled = 1; 2401 2402 return ECORE_SUCCESS; 2403 } 2404 2405 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, 2406 struct ecore_hw_init_params *p_params) 2407 { 2408 struct ecore_load_req_params load_req_params; 2409 u32 load_code, resp, param, drv_mb_param; 2410 bool b_default_mtu = true; 2411 struct ecore_hwfn *p_hwfn; 2412 enum _ecore_status_t rc = ECORE_SUCCESS; 2413 u16 ether_type; 2414 int i; 2415 2416 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) { 2417 DP_NOTICE(p_dev, false, 2418 "MSI mode is not supported for CMT devices\n"); 2419 return ECORE_INVAL; 2420 } 2421 2422 if (IS_PF(p_dev)) { 2423 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data); 2424 if (rc != ECORE_SUCCESS) 2425 return rc; 2426 } 2427 2428 for_each_hwfn(p_dev, i) { 2429 p_hwfn = &p_dev->hwfns[i]; 2430 2431 /* If management didn't provide a default, set one of our own */ 2432 if (!p_hwfn->hw_info.mtu) { 2433 p_hwfn->hw_info.mtu = 1500; 2434 b_default_mtu = false; 2435 } 2436 2437 if (IS_VF(p_dev)) { 2438 ecore_vf_start(p_hwfn, p_params); 2439 continue; 2440 } 2441 2442 rc = ecore_calc_hw_mode(p_hwfn); 2443 if (rc != ECORE_SUCCESS) 2444 return rc; 2445 2446 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, 2447 &p_dev->mf_bits) || 2448 OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING, 2449 &p_dev->mf_bits))) { 2450 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, 2451 &p_dev->mf_bits)) 2452 ether_type = ETHER_TYPE_VLAN; 2453 else 2454 ether_type = ETHER_TYPE_QINQ; 2455 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, 2456 ether_type); 2457 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, 2458 ether_type); 2459 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, 2460 ether_type); 2461 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, 2462 ether_type); 2463 } 2464 2465 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms); 2466 2467 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params, 2468 p_params->p_drv_load_params); 2469 if (rc != ECORE_SUCCESS) 2470 return rc; 2471 2472 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 2473 &load_req_params); 2474 if (rc != ECORE_SUCCESS) { 2475 DP_NOTICE(p_hwfn, false, 2476 "Failed sending a LOAD_REQ command\n"); 2477 return rc; 2478 } 2479 2480 load_code = load_req_params.load_code; 2481 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 2482 "Load request was sent. Load code: 0x%x\n", 2483 load_code); 2484 2485 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt); 2486 2487 /* CQ75580: 2488 * When coming back from hiberbate state, the registers from 2489 * which shadow is read initially are not initialized. It turns 2490 * out that these registers get initialized during the call to 2491 * ecore_mcp_load_req request. So we need to reread them here 2492 * to get the proper shadow register value. 2493 * Note: This is a workaround for the missing MFW 2494 * initialization. It may be removed once the implementation 2495 * is done. 2496 */ 2497 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 2498 2499 /* Only relevant for recovery: 2500 * Clear the indication after the LOAD_REQ command is responded 2501 * by the MFW. 2502 */ 2503 p_dev->recov_in_prog = false; 2504 2505 p_hwfn->first_on_engine = (load_code == 2506 FW_MSG_CODE_DRV_LOAD_ENGINE); 2507 2508 if (!qm_lock_ref_cnt) { 2509 #ifdef CONFIG_ECORE_LOCK_ALLOC 2510 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock); 2511 if (rc) { 2512 DP_ERR(p_hwfn, "qm_lock allocation failed\n"); 2513 goto qm_lock_fail; 2514 } 2515 #endif 2516 OSAL_SPIN_LOCK_INIT(&qm_lock); 2517 } 2518 ++qm_lock_ref_cnt; 2519 2520 /* Clean up chip from previous driver if such remains exist. 2521 * This is not needed when the PF is the first one on the 2522 * engine, since afterwards we are going to init the FW. 2523 */ 2524 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) { 2525 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt, 2526 p_hwfn->rel_pf_id, false); 2527 if (rc != ECORE_SUCCESS) { 2528 ecore_hw_err_notify(p_hwfn, 2529 ECORE_HW_ERR_RAMROD_FAIL); 2530 goto load_err; 2531 } 2532 } 2533 2534 /* Log and clear previous pglue_b errors if such exist */ 2535 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true); 2536 2537 /* Enable the PF's internal FID_enable in the PXP */ 2538 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, 2539 true); 2540 if (rc != ECORE_SUCCESS) 2541 goto load_err; 2542 2543 /* Clear the pglue_b was_error indication. 2544 * In E4 it must be done after the BME and the internal 2545 * FID_enable for the PF are set, since VDMs may cause the 2546 * indication to be set again. 2547 */ 2548 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 2549 2550 switch (load_code) { 2551 case FW_MSG_CODE_DRV_LOAD_ENGINE: 2552 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 2553 p_hwfn->hw_info.hw_mode); 2554 if (rc != ECORE_SUCCESS) 2555 break; 2556 /* Fall into */ 2557 case FW_MSG_CODE_DRV_LOAD_PORT: 2558 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 2559 p_hwfn->hw_info.hw_mode); 2560 if (rc != ECORE_SUCCESS) 2561 break; 2562 /* Fall into */ 2563 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 2564 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 2565 p_params->p_tunn, 2566 p_hwfn->hw_info.hw_mode, 2567 p_params->b_hw_start, 2568 p_params->int_mode, 2569 p_params->allow_npar_tx_switch); 2570 break; 2571 default: 2572 DP_NOTICE(p_hwfn, false, 2573 "Unexpected load code [0x%08x]", load_code); 2574 rc = ECORE_NOTIMPL; 2575 break; 2576 } 2577 2578 if (rc != ECORE_SUCCESS) { 2579 DP_NOTICE(p_hwfn, false, 2580 "init phase failed for loadcode 0x%x (rc %d)\n", 2581 load_code, rc); 2582 goto load_err; 2583 } 2584 2585 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 2586 if (rc != ECORE_SUCCESS) { 2587 DP_NOTICE(p_hwfn, false, 2588 "Sending load done failed, rc = %d\n", rc); 2589 if (rc == ECORE_NOMEM) { 2590 DP_NOTICE(p_hwfn, false, 2591 "Sending load done was failed due to memory allocation failure\n"); 2592 goto load_err; 2593 } 2594 return rc; 2595 } 2596 2597 /* send DCBX attention request command */ 2598 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 2599 "sending phony dcbx set command to trigger DCBx attention handling\n"); 2600 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 2601 DRV_MSG_CODE_SET_DCBX, 2602 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp, 2603 ¶m); 2604 if (rc != ECORE_SUCCESS) { 2605 DP_NOTICE(p_hwfn, false, 2606 "Failed to send DCBX attention request\n"); 2607 return rc; 2608 } 2609 2610 p_hwfn->hw_init_done = true; 2611 } 2612 2613 if (IS_PF(p_dev)) { 2614 /* Get pre-negotiated values for stag, bandwidth etc. */ 2615 p_hwfn = ECORE_LEADING_HWFN(p_dev); 2616 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, 2617 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n"); 2618 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 2619 DRV_MSG_CODE_GET_OEM_UPDATES, 2620 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET, 2621 &resp, ¶m); 2622 if (rc != ECORE_SUCCESS) 2623 DP_NOTICE(p_hwfn, false, 2624 "Failed to send GET_OEM_UPDATES attention request\n"); 2625 } 2626 2627 if (IS_PF(p_dev)) { 2628 p_hwfn = ECORE_LEADING_HWFN(p_dev); 2629 drv_mb_param = STORM_FW_VERSION; 2630 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 2631 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 2632 drv_mb_param, &resp, ¶m); 2633 if (rc != ECORE_SUCCESS) 2634 DP_INFO(p_hwfn, "Failed to update firmware version\n"); 2635 2636 if (!b_default_mtu) { 2637 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 2638 p_hwfn->hw_info.mtu); 2639 if (rc != ECORE_SUCCESS) 2640 DP_INFO(p_hwfn, "Failed to update default mtu\n"); 2641 } 2642 2643 rc = ecore_mcp_ov_update_driver_state(p_hwfn, 2644 p_hwfn->p_main_ptt, 2645 ECORE_OV_DRIVER_STATE_DISABLED); 2646 if (rc != ECORE_SUCCESS) 2647 DP_INFO(p_hwfn, "Failed to update driver state\n"); 2648 2649 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 2650 ECORE_OV_ESWITCH_NONE); 2651 if (rc != ECORE_SUCCESS) 2652 DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 2653 } 2654 2655 return rc; 2656 2657 load_err: 2658 --qm_lock_ref_cnt; 2659 #ifdef CONFIG_ECORE_LOCK_ALLOC 2660 if (!qm_lock_ref_cnt) 2661 OSAL_SPIN_LOCK_DEALLOC(&qm_lock); 2662 qm_lock_fail: 2663 #endif 2664 /* The MFW load lock should be released regardless of success or failure 2665 * of initialization. 2666 * TODO: replace this with an attempt to send cancel_load. 2667 */ 2668 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 2669 return rc; 2670 } 2671 2672 #define ECORE_HW_STOP_RETRY_LIMIT (10) 2673 static void ecore_hw_timers_stop(struct ecore_dev *p_dev, 2674 struct ecore_hwfn *p_hwfn, 2675 struct ecore_ptt *p_ptt) 2676 { 2677 int i; 2678 2679 /* close timers */ 2680 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 2681 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 2682 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog; 2683 i++) { 2684 if ((!ecore_rd(p_hwfn, p_ptt, 2685 TM_REG_PF_SCAN_ACTIVE_CONN)) && 2686 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 2687 break; 2688 2689 /* Dependent on number of connection/tasks, possibly 2690 * 1ms sleep is required between polls 2691 */ 2692 OSAL_MSLEEP(1); 2693 } 2694 2695 if (i < ECORE_HW_STOP_RETRY_LIMIT) 2696 return; 2697 2698 DP_NOTICE(p_hwfn, false, 2699 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 2700 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 2701 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 2702 } 2703 2704 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev) 2705 { 2706 int j; 2707 2708 for_each_hwfn(p_dev, j) { 2709 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 2710 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 2711 2712 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt); 2713 } 2714 } 2715 2716 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn, 2717 struct ecore_ptt *p_ptt, 2718 u32 addr, u32 expected_val) 2719 { 2720 u32 val = ecore_rd(p_hwfn, p_ptt, addr); 2721 2722 if (val != expected_val) { 2723 DP_NOTICE(p_hwfn, true, 2724 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n", 2725 addr, val, expected_val); 2726 return ECORE_UNKNOWN_ERROR; 2727 } 2728 2729 return ECORE_SUCCESS; 2730 } 2731 2732 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev) 2733 { 2734 struct ecore_hwfn *p_hwfn; 2735 struct ecore_ptt *p_ptt; 2736 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS; 2737 int j; 2738 2739 for_each_hwfn(p_dev, j) { 2740 p_hwfn = &p_dev->hwfns[j]; 2741 p_ptt = p_hwfn->p_main_ptt; 2742 2743 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n"); 2744 2745 if (IS_VF(p_dev)) { 2746 ecore_vf_pf_int_cleanup(p_hwfn); 2747 rc = ecore_vf_pf_reset(p_hwfn); 2748 if (rc != ECORE_SUCCESS) { 2749 DP_NOTICE(p_hwfn, true, 2750 "ecore_vf_pf_reset failed. rc = %d.\n", 2751 rc); 2752 rc2 = ECORE_UNKNOWN_ERROR; 2753 } 2754 continue; 2755 } 2756 2757 /* mark the hw as uninitialized... */ 2758 p_hwfn->hw_init_done = false; 2759 2760 /* Send unload command to MCP */ 2761 if (!p_dev->recov_in_prog) { 2762 rc = ecore_mcp_unload_req(p_hwfn, p_ptt); 2763 if (rc != ECORE_SUCCESS) { 2764 DP_NOTICE(p_hwfn, false, 2765 "Failed sending a UNLOAD_REQ command. rc = %d.\n", 2766 rc); 2767 rc2 = ECORE_UNKNOWN_ERROR; 2768 } 2769 } 2770 2771 OSAL_DPC_SYNC(p_hwfn); 2772 2773 /* After this point no MFW attentions are expected, e.g. prevent 2774 * race between pf stop and dcbx pf update. 2775 */ 2776 2777 rc = ecore_sp_pf_stop(p_hwfn); 2778 if (rc != ECORE_SUCCESS) { 2779 DP_NOTICE(p_hwfn, false, 2780 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 2781 rc); 2782 rc2 = ECORE_UNKNOWN_ERROR; 2783 } 2784 2785 /* perform debug action after PF stop was sent */ 2786 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id); 2787 2788 /* close NIG to BRB gate */ 2789 ecore_wr(p_hwfn, p_ptt, 2790 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 2791 2792 /* close parser */ 2793 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 2794 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 2795 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 2796 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 2797 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 2798 2799 /* @@@TBD - clean transmission queues (5.b) */ 2800 /* @@@TBD - clean BTB (5.c) */ 2801 2802 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt); 2803 2804 /* @@@TBD - verify DMAE requests are done (8) */ 2805 2806 /* Disable Attention Generation */ 2807 ecore_int_igu_disable_int(p_hwfn, p_ptt); 2808 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 2809 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 2810 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 2811 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt); 2812 if (rc != ECORE_SUCCESS) { 2813 DP_NOTICE(p_hwfn, true, 2814 "Failed to return IGU CAM to default\n"); 2815 rc2 = ECORE_UNKNOWN_ERROR; 2816 } 2817 2818 /* Need to wait 1ms to guarantee SBs are cleared */ 2819 OSAL_MSLEEP(1); 2820 2821 if (!p_dev->recov_in_prog) { 2822 ecore_verify_reg_val(p_hwfn, p_ptt, 2823 QM_REG_USG_CNT_PF_TX, 0); 2824 ecore_verify_reg_val(p_hwfn, p_ptt, 2825 QM_REG_USG_CNT_PF_OTHER, 0); 2826 /* @@@TBD - assert on incorrect xCFC values (10.b) */ 2827 } 2828 2829 /* Disable PF in HW blocks */ 2830 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 2831 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 2832 2833 --qm_lock_ref_cnt; 2834 #ifdef CONFIG_ECORE_LOCK_ALLOC 2835 if (!qm_lock_ref_cnt) 2836 OSAL_SPIN_LOCK_DEALLOC(&qm_lock); 2837 #endif 2838 2839 if (!p_dev->recov_in_prog) { 2840 rc = ecore_mcp_unload_done(p_hwfn, p_ptt); 2841 if (rc == ECORE_NOMEM) { 2842 DP_NOTICE(p_hwfn, false, 2843 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n"); 2844 rc = ecore_mcp_unload_done(p_hwfn, p_ptt); 2845 } 2846 if (rc != ECORE_SUCCESS) { 2847 DP_NOTICE(p_hwfn, false, 2848 "Failed sending a UNLOAD_DONE command. rc = %d.\n", 2849 rc); 2850 rc2 = ECORE_UNKNOWN_ERROR; 2851 } 2852 } 2853 } /* hwfn loop */ 2854 2855 if (IS_PF(p_dev) && !p_dev->recov_in_prog) { 2856 p_hwfn = ECORE_LEADING_HWFN(p_dev); 2857 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt; 2858 2859 /* Clear the PF's internal FID_enable in the PXP. 2860 * In CMT this should only be done for first hw-function, and 2861 * only after all transactions have stopped for all active 2862 * hw-functions. 2863 */ 2864 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, 2865 false); 2866 if (rc != ECORE_SUCCESS) { 2867 DP_NOTICE(p_hwfn, true, 2868 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n", 2869 rc); 2870 rc2 = ECORE_UNKNOWN_ERROR; 2871 } 2872 } 2873 2874 return rc2; 2875 } 2876 2877 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev) 2878 { 2879 int j; 2880 2881 for_each_hwfn(p_dev, j) { 2882 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 2883 struct ecore_ptt *p_ptt; 2884 2885 if (IS_VF(p_dev)) { 2886 ecore_vf_pf_int_cleanup(p_hwfn); 2887 continue; 2888 } 2889 p_ptt = ecore_ptt_acquire(p_hwfn); 2890 if (!p_ptt) 2891 return ECORE_AGAIN; 2892 2893 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 2894 "Shutting down the fastpath\n"); 2895 2896 ecore_wr(p_hwfn, p_ptt, 2897 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 2898 2899 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 2900 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 2901 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 2902 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 2903 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 2904 2905 /* @@@TBD - clean transmission queues (5.b) */ 2906 /* @@@TBD - clean BTB (5.c) */ 2907 2908 /* @@@TBD - verify DMAE requests are done (8) */ 2909 2910 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 2911 /* Need to wait 1ms to guarantee SBs are cleared */ 2912 OSAL_MSLEEP(1); 2913 ecore_ptt_release(p_hwfn, p_ptt); 2914 } 2915 2916 return ECORE_SUCCESS; 2917 } 2918 2919 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn) 2920 { 2921 struct ecore_ptt *p_ptt; 2922 2923 if (IS_VF(p_hwfn->p_dev)) 2924 return ECORE_SUCCESS; 2925 2926 p_ptt = ecore_ptt_acquire(p_hwfn); 2927 if (!p_ptt) 2928 return ECORE_AGAIN; 2929 2930 /* If roce info is allocated it means roce is initialized and should 2931 * be enabled in searcher. 2932 */ 2933 if (p_hwfn->p_rdma_info) { 2934 if (p_hwfn->b_rdma_enabled_in_prs) 2935 ecore_wr(p_hwfn, p_ptt, 2936 p_hwfn->rdma_prs_search_reg, 0x1); 2937 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1); 2938 } 2939 2940 /* Re-open incoming traffic */ 2941 ecore_wr(p_hwfn, p_ptt, 2942 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 2943 ecore_ptt_release(p_hwfn, p_ptt); 2944 2945 return ECORE_SUCCESS; 2946 } 2947 2948 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 2949 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn) 2950 { 2951 ecore_ptt_pool_free(p_hwfn); 2952 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info); 2953 } 2954 2955 /* Setup bar access */ 2956 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn) 2957 { 2958 /* clear indirect access */ 2959 if (ECORE_IS_AH(p_hwfn->p_dev)) { 2960 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2961 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0); 2962 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2963 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0); 2964 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2965 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0); 2966 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2967 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0); 2968 } else { 2969 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2970 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 2971 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2972 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 2973 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2974 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 2975 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2976 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 2977 } 2978 2979 /* Clean previous pglue_b errors if such exist */ 2980 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 2981 2982 /* enable internal target-read */ 2983 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2984 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 2985 } 2986 2987 static void get_function_id(struct ecore_hwfn *p_hwfn) 2988 { 2989 /* ME Register */ 2990 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, 2991 PXP_PF_ME_OPAQUE_ADDR); 2992 2993 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 2994 2995 /* Bits 16-19 from the ME registers are the pf_num */ 2996 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 2997 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2998 PXP_CONCRETE_FID_PFID); 2999 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 3000 PXP_CONCRETE_FID_PORT); 3001 3002 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 3003 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 3004 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 3005 } 3006 3007 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn) 3008 { 3009 u32 *feat_num = p_hwfn->hw_info.feat_num; 3010 struct ecore_sb_cnt_info sb_cnt; 3011 u32 non_l2_sbs = 0; 3012 3013 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt)); 3014 ecore_int_get_num_sbs(p_hwfn, &sb_cnt); 3015 3016 /* L2 Queues require each: 1 status block. 1 L2 queue */ 3017 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) { 3018 /* Start by allocating VF queues, then PF's */ 3019 feat_num[ECORE_VF_L2_QUE] = 3020 OSAL_MIN_T(u32, 3021 RESC_NUM(p_hwfn, ECORE_L2_QUEUE), 3022 sb_cnt.iov_cnt); 3023 feat_num[ECORE_PF_L2_QUE] = 3024 OSAL_MIN_T(u32, 3025 sb_cnt.cnt - non_l2_sbs, 3026 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) - 3027 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE)); 3028 } 3029 3030 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) || 3031 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) { 3032 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ? 3033 &feat_num[ECORE_FCOE_CQ] : 3034 &feat_num[ECORE_ISCSI_CQ]; 3035 u32 limit = sb_cnt.cnt; 3036 3037 /* The number of queues should not exceed the number of FP SBs. 3038 * In storage target, the queues are divided into pairs of a CQ 3039 * and a CmdQ, and each pair uses a single SB. The limit in 3040 * this case should allow a max ratio of 2:1 instead of 1:1. 3041 */ 3042 if (p_hwfn->p_dev->b_is_target) 3043 limit *= 2; 3044 *p_storage_feat = OSAL_MIN_T(u32, limit, 3045 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS)); 3046 3047 /* @DPDK */ 3048 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init 3049 * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2". 3050 */ 3051 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat, 3052 (NUM_OF_GLOBAL_QUEUES / 2)); 3053 } 3054 3055 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 3056 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n", 3057 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE), 3058 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE), 3059 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ), 3060 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ), 3061 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ), 3062 (int)sb_cnt.cnt); 3063 } 3064 3065 const char *ecore_hw_get_resc_name(enum ecore_resources res_id) 3066 { 3067 switch (res_id) { 3068 case ECORE_L2_QUEUE: 3069 return "L2_QUEUE"; 3070 case ECORE_VPORT: 3071 return "VPORT"; 3072 case ECORE_RSS_ENG: 3073 return "RSS_ENG"; 3074 case ECORE_PQ: 3075 return "PQ"; 3076 case ECORE_RL: 3077 return "RL"; 3078 case ECORE_MAC: 3079 return "MAC"; 3080 case ECORE_VLAN: 3081 return "VLAN"; 3082 case ECORE_RDMA_CNQ_RAM: 3083 return "RDMA_CNQ_RAM"; 3084 case ECORE_ILT: 3085 return "ILT"; 3086 case ECORE_LL2_QUEUE: 3087 return "LL2_QUEUE"; 3088 case ECORE_CMDQS_CQS: 3089 return "CMDQS_CQS"; 3090 case ECORE_RDMA_STATS_QUEUE: 3091 return "RDMA_STATS_QUEUE"; 3092 case ECORE_BDQ: 3093 return "BDQ"; 3094 case ECORE_SB: 3095 return "SB"; 3096 default: 3097 return "UNKNOWN_RESOURCE"; 3098 } 3099 } 3100 3101 static enum _ecore_status_t 3102 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn, 3103 struct ecore_ptt *p_ptt, 3104 enum ecore_resources res_id, 3105 u32 resc_max_val, 3106 u32 *p_mcp_resp) 3107 { 3108 enum _ecore_status_t rc; 3109 3110 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 3111 resc_max_val, p_mcp_resp); 3112 if (rc != ECORE_SUCCESS) { 3113 DP_NOTICE(p_hwfn, false, 3114 "MFW response failure for a max value setting of resource %d [%s]\n", 3115 res_id, ecore_hw_get_resc_name(res_id)); 3116 return rc; 3117 } 3118 3119 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 3120 DP_INFO(p_hwfn, 3121 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 3122 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp); 3123 3124 return ECORE_SUCCESS; 3125 } 3126 3127 static enum _ecore_status_t 3128 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn, 3129 struct ecore_ptt *p_ptt) 3130 { 3131 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 3132 u32 resc_max_val, mcp_resp; 3133 u8 res_id; 3134 enum _ecore_status_t rc; 3135 3136 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) { 3137 /* @DPDK */ 3138 switch (res_id) { 3139 case ECORE_LL2_QUEUE: 3140 case ECORE_RDMA_CNQ_RAM: 3141 case ECORE_RDMA_STATS_QUEUE: 3142 case ECORE_BDQ: 3143 resc_max_val = 0; 3144 break; 3145 default: 3146 continue; 3147 } 3148 3149 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 3150 resc_max_val, &mcp_resp); 3151 if (rc != ECORE_SUCCESS) 3152 return rc; 3153 3154 /* There's no point to continue to the next resource if the 3155 * command is not supported by the MFW. 3156 * We do continue if the command is supported but the resource 3157 * is unknown to the MFW. Such a resource will be later 3158 * configured with the default allocation values. 3159 */ 3160 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 3161 return ECORE_NOTIMPL; 3162 } 3163 3164 return ECORE_SUCCESS; 3165 } 3166 3167 static 3168 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn, 3169 enum ecore_resources res_id, 3170 u32 *p_resc_num, u32 *p_resc_start) 3171 { 3172 u8 num_funcs = p_hwfn->num_funcs_on_engine; 3173 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 3174 3175 switch (res_id) { 3176 case ECORE_L2_QUEUE: 3177 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : 3178 MAX_NUM_L2_QUEUES_BB) / num_funcs; 3179 break; 3180 case ECORE_VPORT: 3181 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 3182 MAX_NUM_VPORTS_BB) / num_funcs; 3183 break; 3184 case ECORE_RSS_ENG: 3185 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : 3186 ETH_RSS_ENGINE_NUM_BB) / num_funcs; 3187 break; 3188 case ECORE_PQ: 3189 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : 3190 MAX_QM_TX_QUEUES_BB) / num_funcs; 3191 break; 3192 case ECORE_RL: 3193 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 3194 break; 3195 case ECORE_MAC: 3196 case ECORE_VLAN: 3197 /* Each VFC resource can accommodate both a MAC and a VLAN */ 3198 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 3199 break; 3200 case ECORE_ILT: 3201 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : 3202 PXP_NUM_ILT_RECORDS_BB) / num_funcs; 3203 break; 3204 case ECORE_LL2_QUEUE: 3205 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 3206 break; 3207 case ECORE_RDMA_CNQ_RAM: 3208 case ECORE_CMDQS_CQS: 3209 /* CNQ/CMDQS are the same resource */ 3210 /* @DPDK */ 3211 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs; 3212 break; 3213 case ECORE_RDMA_STATS_QUEUE: 3214 /* @DPDK */ 3215 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 3216 MAX_NUM_VPORTS_BB) / num_funcs; 3217 break; 3218 case ECORE_BDQ: 3219 /* @DPDK */ 3220 *p_resc_num = 0; 3221 break; 3222 default: 3223 break; 3224 } 3225 3226 3227 switch (res_id) { 3228 case ECORE_BDQ: 3229 if (!*p_resc_num) 3230 *p_resc_start = 0; 3231 break; 3232 case ECORE_SB: 3233 /* Since we want its value to reflect whether MFW supports 3234 * the new scheme, have a default of 0. 3235 */ 3236 *p_resc_num = 0; 3237 break; 3238 default: 3239 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 3240 break; 3241 } 3242 3243 return ECORE_SUCCESS; 3244 } 3245 3246 static enum _ecore_status_t 3247 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id, 3248 bool drv_resc_alloc) 3249 { 3250 u32 dflt_resc_num = 0, dflt_resc_start = 0; 3251 u32 mcp_resp, *p_resc_num, *p_resc_start; 3252 enum _ecore_status_t rc; 3253 3254 p_resc_num = &RESC_NUM(p_hwfn, res_id); 3255 p_resc_start = &RESC_START(p_hwfn, res_id); 3256 3257 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 3258 &dflt_resc_start); 3259 if (rc != ECORE_SUCCESS) { 3260 DP_ERR(p_hwfn, 3261 "Failed to get default amount for resource %d [%s]\n", 3262 res_id, ecore_hw_get_resc_name(res_id)); 3263 return rc; 3264 } 3265 3266 #ifndef ASIC_ONLY 3267 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 3268 *p_resc_num = dflt_resc_num; 3269 *p_resc_start = dflt_resc_start; 3270 goto out; 3271 } 3272 #endif 3273 3274 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 3275 &mcp_resp, p_resc_num, p_resc_start); 3276 if (rc != ECORE_SUCCESS) { 3277 DP_NOTICE(p_hwfn, true, 3278 "MFW response failure for an allocation request for" 3279 " resource %d [%s]\n", 3280 res_id, ecore_hw_get_resc_name(res_id)); 3281 return rc; 3282 } 3283 3284 /* Default driver values are applied in the following cases: 3285 * - The resource allocation MB command is not supported by the MFW 3286 * - There is an internal error in the MFW while processing the request 3287 * - The resource ID is unknown to the MFW 3288 */ 3289 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 3290 DP_INFO(p_hwfn, 3291 "Failed to receive allocation info for resource %d [%s]." 3292 " mcp_resp = 0x%x. Applying default values" 3293 " [%d,%d].\n", 3294 res_id, ecore_hw_get_resc_name(res_id), mcp_resp, 3295 dflt_resc_num, dflt_resc_start); 3296 3297 *p_resc_num = dflt_resc_num; 3298 *p_resc_start = dflt_resc_start; 3299 goto out; 3300 } 3301 3302 if ((*p_resc_num != dflt_resc_num || 3303 *p_resc_start != dflt_resc_start) && 3304 res_id != ECORE_SB) { 3305 DP_INFO(p_hwfn, 3306 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n", 3307 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num, 3308 *p_resc_start, dflt_resc_num, dflt_resc_start, 3309 drv_resc_alloc ? " - Applying default values" : ""); 3310 if (drv_resc_alloc) { 3311 *p_resc_num = dflt_resc_num; 3312 *p_resc_start = dflt_resc_start; 3313 } 3314 } 3315 out: 3316 return ECORE_SUCCESS; 3317 } 3318 3319 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, 3320 bool drv_resc_alloc) 3321 { 3322 enum _ecore_status_t rc; 3323 u8 res_id; 3324 3325 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) { 3326 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc); 3327 if (rc != ECORE_SUCCESS) 3328 return rc; 3329 } 3330 3331 return ECORE_SUCCESS; 3332 } 3333 3334 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn, 3335 struct ecore_ptt *p_ptt, 3336 bool drv_resc_alloc) 3337 { 3338 struct ecore_resc_unlock_params resc_unlock_params; 3339 struct ecore_resc_lock_params resc_lock_params; 3340 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 3341 u8 res_id; 3342 enum _ecore_status_t rc; 3343 #ifndef ASIC_ONLY 3344 u32 *resc_start = p_hwfn->hw_info.resc_start; 3345 u32 *resc_num = p_hwfn->hw_info.resc_num; 3346 /* For AH, an equal share of the ILT lines between the maximal number of 3347 * PFs is not enough for RoCE. This would be solved by the future 3348 * resource allocation scheme, but isn't currently present for 3349 * FPGA/emulation. For now we keep a number that is sufficient for RoCE 3350 * to work - the BB number of ILT lines divided by its max PFs number. 3351 */ 3352 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB; 3353 #endif 3354 3355 /* Setting the max values of the soft resources and the following 3356 * resources allocation queries should be atomic. Since several PFs can 3357 * run in parallel - a resource lock is needed. 3358 * If either the resource lock or resource set value commands are not 3359 * supported - skip the max values setting, release the lock if 3360 * needed, and proceed to the queries. Other failures, including a 3361 * failure to acquire the lock, will cause this function to fail. 3362 * Old drivers that don't acquire the lock can run in parallel, and 3363 * their allocation values won't be affected by the updated max values. 3364 */ 3365 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 3366 ECORE_RESC_LOCK_RESC_ALLOC, false); 3367 3368 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 3369 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) { 3370 return rc; 3371 } else if (rc == ECORE_NOTIMPL) { 3372 DP_INFO(p_hwfn, 3373 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 3374 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) { 3375 DP_NOTICE(p_hwfn, false, 3376 "Failed to acquire the resource lock for the resource allocation commands\n"); 3377 rc = ECORE_BUSY; 3378 goto unlock_and_exit; 3379 } else { 3380 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt); 3381 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) { 3382 DP_NOTICE(p_hwfn, false, 3383 "Failed to set the max values of the soft resources\n"); 3384 goto unlock_and_exit; 3385 } else if (rc == ECORE_NOTIMPL) { 3386 DP_INFO(p_hwfn, 3387 "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 3388 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt, 3389 &resc_unlock_params); 3390 if (rc != ECORE_SUCCESS) 3391 DP_INFO(p_hwfn, 3392 "Failed to release the resource lock for the resource allocation commands\n"); 3393 } 3394 } 3395 3396 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc); 3397 if (rc != ECORE_SUCCESS) 3398 goto unlock_and_exit; 3399 3400 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 3401 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt, 3402 &resc_unlock_params); 3403 if (rc != ECORE_SUCCESS) 3404 DP_INFO(p_hwfn, 3405 "Failed to release the resource lock for the resource allocation commands\n"); 3406 } 3407 3408 #ifndef ASIC_ONLY 3409 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 3410 /* Reduced build contains less PQs */ 3411 if (!(p_hwfn->p_dev->b_is_emul_full)) { 3412 resc_num[ECORE_PQ] = 32; 3413 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] * 3414 p_hwfn->enabled_func_idx; 3415 } 3416 3417 /* For AH emulation, since we have a possible maximal number of 3418 * 16 enabled PFs, in case there are not enough ILT lines - 3419 * allocate only first PF as RoCE and have all the other ETH 3420 * only with less ILT lines. 3421 */ 3422 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full) 3423 resc_num[ECORE_ILT] = OSAL_MAX_T(u32, 3424 resc_num[ECORE_ILT], 3425 roce_min_ilt_lines); 3426 } 3427 3428 /* Correct the common ILT calculation if PF0 has more */ 3429 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) && 3430 p_hwfn->p_dev->b_is_emul_full && 3431 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines) 3432 resc_start[ECORE_ILT] += roce_min_ilt_lines - 3433 resc_num[ECORE_ILT]; 3434 #endif 3435 3436 /* Sanity for ILT */ 3437 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 3438 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 3439 DP_NOTICE(p_hwfn, true, 3440 "Can't assign ILT pages [%08x,...,%08x]\n", 3441 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn, 3442 ECORE_ILT) - 3443 1); 3444 return ECORE_INVAL; 3445 } 3446 3447 /* This will also learn the number of SBs from MFW */ 3448 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt)) 3449 return ECORE_INVAL; 3450 3451 ecore_hw_set_feat(p_hwfn); 3452 3453 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 3454 "The numbers for each resource are:\n"); 3455 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) 3456 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n", 3457 ecore_hw_get_resc_name(res_id), 3458 RESC_NUM(p_hwfn, res_id), 3459 RESC_START(p_hwfn, res_id)); 3460 3461 return ECORE_SUCCESS; 3462 3463 unlock_and_exit: 3464 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 3465 ecore_mcp_resc_unlock(p_hwfn, p_ptt, 3466 &resc_unlock_params); 3467 return rc; 3468 } 3469 3470 static enum _ecore_status_t 3471 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn, 3472 struct ecore_ptt *p_ptt, 3473 struct ecore_hw_prepare_params *p_params) 3474 { 3475 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode; 3476 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 3477 struct ecore_mcp_link_capabilities *p_caps; 3478 struct ecore_mcp_link_params *link; 3479 enum _ecore_status_t rc; 3480 3481 /* Read global nvm_cfg address */ 3482 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 3483 3484 /* Verify MCP has initialized it */ 3485 if (!nvm_cfg_addr) { 3486 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n"); 3487 if (p_params->b_relaxed_probe) 3488 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM; 3489 return ECORE_INVAL; 3490 } 3491 3492 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 3493 3494 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 3495 3496 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 3497 OFFSETOF(struct nvm_cfg1, glob) + 3498 OFFSETOF(struct nvm_cfg1_glob, core_cfg); 3499 3500 core_cfg = ecore_rd(p_hwfn, p_ptt, addr); 3501 3502 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 3503 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 3504 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 3505 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G; 3506 break; 3507 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 3508 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G; 3509 break; 3510 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 3511 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G; 3512 break; 3513 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 3514 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F; 3515 break; 3516 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 3517 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E; 3518 break; 3519 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 3520 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G; 3521 break; 3522 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 3523 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G; 3524 break; 3525 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 3526 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G; 3527 break; 3528 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 3529 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G; 3530 break; 3531 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 3532 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G; 3533 break; 3534 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 3535 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G; 3536 break; 3537 default: 3538 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n", 3539 core_cfg); 3540 break; 3541 } 3542 3543 /* Read DCBX configuration */ 3544 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 3545 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 3546 dcbx_mode = ecore_rd(p_hwfn, p_ptt, 3547 port_cfg_addr + 3548 OFFSETOF(struct nvm_cfg1_port, generic_cont0)); 3549 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK) 3550 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET; 3551 switch (dcbx_mode) { 3552 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC: 3553 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC; 3554 break; 3555 case NVM_CFG1_PORT_DCBX_MODE_CEE: 3556 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE; 3557 break; 3558 case NVM_CFG1_PORT_DCBX_MODE_IEEE: 3559 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE; 3560 break; 3561 default: 3562 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED; 3563 } 3564 3565 /* Read default link configuration */ 3566 link = &p_hwfn->mcp_info->link_input; 3567 p_caps = &p_hwfn->mcp_info->link_capabilities; 3568 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 3569 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 3570 link_temp = ecore_rd(p_hwfn, p_ptt, 3571 port_cfg_addr + 3572 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask)); 3573 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 3574 link->speed.advertised_speeds = link_temp; 3575 p_caps->speed_capabilities = link->speed.advertised_speeds; 3576 3577 link_temp = ecore_rd(p_hwfn, p_ptt, 3578 port_cfg_addr + 3579 OFFSETOF(struct nvm_cfg1_port, link_settings)); 3580 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 3581 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 3582 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 3583 link->speed.autoneg = true; 3584 break; 3585 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 3586 link->speed.forced_speed = 1000; 3587 break; 3588 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 3589 link->speed.forced_speed = 10000; 3590 break; 3591 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 3592 link->speed.forced_speed = 25000; 3593 break; 3594 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 3595 link->speed.forced_speed = 40000; 3596 break; 3597 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 3598 link->speed.forced_speed = 50000; 3599 break; 3600 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 3601 link->speed.forced_speed = 100000; 3602 break; 3603 default: 3604 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp); 3605 } 3606 3607 p_caps->default_speed = link->speed.forced_speed; 3608 p_caps->default_speed_autoneg = link->speed.autoneg; 3609 3610 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 3611 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 3612 link->pause.autoneg = !!(link_temp & 3613 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 3614 link->pause.forced_rx = !!(link_temp & 3615 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 3616 link->pause.forced_tx = !!(link_temp & 3617 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 3618 link->loopback_mode = 0; 3619 3620 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 3621 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr + 3622 OFFSETOF(struct nvm_cfg1_port, ext_phy)); 3623 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK; 3624 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET; 3625 p_caps->default_eee = ECORE_MCP_EEE_ENABLED; 3626 link->eee.enable = true; 3627 switch (link_temp) { 3628 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED: 3629 p_caps->default_eee = ECORE_MCP_EEE_DISABLED; 3630 link->eee.enable = false; 3631 break; 3632 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED: 3633 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME; 3634 break; 3635 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE: 3636 p_caps->eee_lpi_timer = 3637 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME; 3638 break; 3639 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY: 3640 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME; 3641 break; 3642 } 3643 3644 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer; 3645 link->eee.tx_lpi_enable = link->eee.enable; 3646 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV; 3647 } else { 3648 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED; 3649 } 3650 3651 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 3652 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]", 3653 link->speed.forced_speed, link->speed.advertised_speeds, 3654 link->speed.autoneg, link->pause.autoneg, 3655 p_caps->default_eee, p_caps->eee_lpi_timer); 3656 3657 /* Read Multi-function information from shmem */ 3658 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 3659 OFFSETOF(struct nvm_cfg1, glob) + 3660 OFFSETOF(struct nvm_cfg1_glob, generic_cont0); 3661 3662 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr); 3663 3664 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 3665 NVM_CFG1_GLOB_MF_MODE_OFFSET; 3666 3667 switch (mf_mode) { 3668 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 3669 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS; 3670 break; 3671 case NVM_CFG1_GLOB_MF_MODE_UFP: 3672 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS | 3673 1 << ECORE_MF_UFP_SPECIFIC | 3674 1 << ECORE_MF_8021Q_TAGGING; 3675 break; 3676 case NVM_CFG1_GLOB_MF_MODE_BD: 3677 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS | 3678 1 << ECORE_MF_LLH_PROTO_CLSS | 3679 1 << ECORE_MF_8021AD_TAGGING; 3680 break; 3681 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 3682 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS | 3683 1 << ECORE_MF_LLH_PROTO_CLSS | 3684 1 << ECORE_MF_LL2_NON_UNICAST | 3685 1 << ECORE_MF_INTER_PF_SWITCH | 3686 1 << ECORE_MF_DISABLE_ARFS; 3687 break; 3688 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 3689 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS | 3690 1 << ECORE_MF_LLH_PROTO_CLSS | 3691 1 << ECORE_MF_LL2_NON_UNICAST; 3692 if (ECORE_IS_BB(p_hwfn->p_dev)) 3693 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF; 3694 break; 3695 } 3696 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 3697 p_hwfn->p_dev->mf_bits); 3698 3699 if (ECORE_IS_CMT(p_hwfn->p_dev)) 3700 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS); 3701 3702 /* It's funny since we have another switch, but it's easier 3703 * to throw this away in linux this way. Long term, it might be 3704 * better to have have getters for needed ECORE_MF_* fields, 3705 * convert client code and eliminate this. 3706 */ 3707 switch (mf_mode) { 3708 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 3709 case NVM_CFG1_GLOB_MF_MODE_BD: 3710 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN; 3711 break; 3712 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 3713 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR; 3714 break; 3715 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 3716 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT; 3717 break; 3718 case NVM_CFG1_GLOB_MF_MODE_UFP: 3719 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP; 3720 break; 3721 } 3722 3723 /* Read Multi-function information from shmem */ 3724 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 3725 OFFSETOF(struct nvm_cfg1, glob) + 3726 OFFSETOF(struct nvm_cfg1_glob, device_capabilities); 3727 3728 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr); 3729 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 3730 OSAL_SET_BIT(ECORE_DEV_CAP_ETH, 3731 &p_hwfn->hw_info.device_capabilities); 3732 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 3733 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE, 3734 &p_hwfn->hw_info.device_capabilities); 3735 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 3736 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI, 3737 &p_hwfn->hw_info.device_capabilities); 3738 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 3739 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE, 3740 &p_hwfn->hw_info.device_capabilities); 3741 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP) 3742 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP, 3743 &p_hwfn->hw_info.device_capabilities); 3744 3745 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 3746 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) { 3747 rc = ECORE_SUCCESS; 3748 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP; 3749 } 3750 3751 return rc; 3752 } 3753 3754 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn, 3755 struct ecore_ptt *p_ptt) 3756 { 3757 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 3758 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 3759 struct ecore_dev *p_dev = p_hwfn->p_dev; 3760 3761 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 3762 3763 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 3764 * in the other bits are selected. 3765 * Bits 1-15 are for functions 1-15, respectively, and their value is 3766 * '0' only for enabled functions (function 0 always exists and 3767 * enabled). 3768 * In case of CMT in BB, only the "even" functions are enabled, and thus 3769 * the number of functions for both hwfns is learnt from the same bits. 3770 */ 3771 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) { 3772 reg_function_hide = ecore_rd(p_hwfn, p_ptt, 3773 MISCS_REG_FUNCTION_HIDE_BB_K2); 3774 } else { /* E5 */ 3775 reg_function_hide = 0; 3776 } 3777 3778 if (reg_function_hide & 0x1) { 3779 if (ECORE_IS_BB(p_dev)) { 3780 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) { 3781 num_funcs = 0; 3782 eng_mask = 0xaaaa; 3783 } else { 3784 num_funcs = 1; 3785 eng_mask = 0x5554; 3786 } 3787 } else { 3788 num_funcs = 1; 3789 eng_mask = 0xfffe; 3790 } 3791 3792 /* Get the number of the enabled functions on the engine */ 3793 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 3794 while (tmp) { 3795 if (tmp & 0x1) 3796 num_funcs++; 3797 tmp >>= 0x1; 3798 } 3799 3800 /* Get the PF index within the enabled functions */ 3801 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 3802 tmp = reg_function_hide & eng_mask & low_pfs_mask; 3803 while (tmp) { 3804 if (tmp & 0x1) 3805 enabled_func_idx--; 3806 tmp >>= 0x1; 3807 } 3808 } 3809 3810 p_hwfn->num_funcs_on_engine = num_funcs; 3811 p_hwfn->enabled_func_idx = enabled_func_idx; 3812 3813 #ifndef ASIC_ONLY 3814 if (CHIP_REV_IS_FPGA(p_dev)) { 3815 DP_NOTICE(p_hwfn, false, 3816 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n"); 3817 p_hwfn->num_funcs_on_engine = 4; 3818 } 3819 #endif 3820 3821 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 3822 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 3823 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id, 3824 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 3825 } 3826 3827 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn, 3828 struct ecore_ptt *p_ptt) 3829 { 3830 struct ecore_dev *p_dev = p_hwfn->p_dev; 3831 u32 port_mode; 3832 3833 #ifndef ASIC_ONLY 3834 /* Read the port mode */ 3835 if (CHIP_REV_IS_FPGA(p_dev)) 3836 port_mode = 4; 3837 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev)) 3838 /* In CMT on emulation, assume 1 port */ 3839 port_mode = 1; 3840 else 3841 #endif 3842 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB); 3843 3844 if (port_mode < 3) { 3845 p_dev->num_ports_in_engine = 1; 3846 } else if (port_mode <= 5) { 3847 p_dev->num_ports_in_engine = 2; 3848 } else { 3849 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n", 3850 p_dev->num_ports_in_engine); 3851 3852 /* Default num_ports_in_engine to something */ 3853 p_dev->num_ports_in_engine = 1; 3854 } 3855 } 3856 3857 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn, 3858 struct ecore_ptt *p_ptt) 3859 { 3860 struct ecore_dev *p_dev = p_hwfn->p_dev; 3861 u32 port; 3862 int i; 3863 3864 p_dev->num_ports_in_engine = 0; 3865 3866 #ifndef ASIC_ONLY 3867 if (CHIP_REV_IS_EMUL(p_dev)) { 3868 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED); 3869 switch ((port & 0xf000) >> 12) { 3870 case 1: 3871 p_dev->num_ports_in_engine = 1; 3872 break; 3873 case 3: 3874 p_dev->num_ports_in_engine = 2; 3875 break; 3876 case 0xf: 3877 p_dev->num_ports_in_engine = 4; 3878 break; 3879 default: 3880 DP_NOTICE(p_hwfn, false, 3881 "Unknown port mode in ECO_RESERVED %08x\n", 3882 port); 3883 } 3884 } else 3885 #endif 3886 for (i = 0; i < MAX_NUM_PORTS_K2; i++) { 3887 port = ecore_rd(p_hwfn, p_ptt, 3888 CNIG_REG_NIG_PORT0_CONF_K2_E5 + 3889 (i * 4)); 3890 if (port & 1) 3891 p_dev->num_ports_in_engine++; 3892 } 3893 3894 if (!p_dev->num_ports_in_engine) { 3895 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n"); 3896 3897 /* Default num_ports_in_engine to something */ 3898 p_dev->num_ports_in_engine = 1; 3899 } 3900 } 3901 3902 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn, 3903 struct ecore_ptt *p_ptt) 3904 { 3905 struct ecore_dev *p_dev = p_hwfn->p_dev; 3906 3907 /* Determine the number of ports per engine */ 3908 if (ECORE_IS_BB(p_dev)) 3909 ecore_hw_info_port_num_bb(p_hwfn, p_ptt); 3910 else 3911 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt); 3912 3913 /* Get the total number of ports of the device */ 3914 if (ECORE_IS_CMT(p_dev)) { 3915 /* In CMT there is always only one port */ 3916 p_dev->num_ports = 1; 3917 #ifndef ASIC_ONLY 3918 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) { 3919 p_dev->num_ports = p_dev->num_ports_in_engine * 3920 ecore_device_num_engines(p_dev); 3921 #endif 3922 } else { 3923 u32 addr, global_offsize, global_addr; 3924 3925 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 3926 PUBLIC_GLOBAL); 3927 global_offsize = ecore_rd(p_hwfn, p_ptt, addr); 3928 global_addr = SECTION_ADDR(global_offsize, 0); 3929 addr = global_addr + OFFSETOF(struct public_global, max_ports); 3930 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr); 3931 } 3932 } 3933 3934 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn, 3935 struct ecore_ptt *p_ptt) 3936 { 3937 struct ecore_mcp_link_capabilities *p_caps; 3938 u32 eee_status; 3939 3940 p_caps = &p_hwfn->mcp_info->link_capabilities; 3941 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED) 3942 return; 3943 3944 p_caps->eee_speed_caps = 0; 3945 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 3946 OFFSETOF(struct public_port, eee_status)); 3947 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >> 3948 EEE_SUPPORTED_SPEED_OFFSET; 3949 if (eee_status & EEE_1G_SUPPORTED) 3950 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV; 3951 if (eee_status & EEE_10G_ADV) 3952 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV; 3953 } 3954 3955 static enum _ecore_status_t 3956 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 3957 enum ecore_pci_personality personality, 3958 struct ecore_hw_prepare_params *p_params) 3959 { 3960 bool drv_resc_alloc = p_params->drv_resc_alloc; 3961 enum _ecore_status_t rc; 3962 3963 if (IS_ECORE_PACING(p_hwfn)) { 3964 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV, 3965 "Skipping IOV as packet pacing is requested\n"); 3966 } 3967 3968 /* Since all information is common, only first hwfns should do this */ 3969 if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) { 3970 rc = ecore_iov_hw_info(p_hwfn); 3971 if (rc != ECORE_SUCCESS) { 3972 if (p_params->b_relaxed_probe) 3973 p_params->p_relaxed_res = 3974 ECORE_HW_PREPARE_BAD_IOV; 3975 else 3976 return rc; 3977 } 3978 } 3979 3980 if (IS_LEAD_HWFN(p_hwfn)) 3981 ecore_hw_info_port_num(p_hwfn, p_ptt); 3982 3983 ecore_mcp_get_capabilities(p_hwfn, p_ptt); 3984 3985 #ifndef ASIC_ONLY 3986 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) { 3987 #endif 3988 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params); 3989 if (rc != ECORE_SUCCESS) 3990 return rc; 3991 #ifndef ASIC_ONLY 3992 } 3993 #endif 3994 3995 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt); 3996 if (rc != ECORE_SUCCESS) { 3997 if (p_params->b_relaxed_probe) 3998 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU; 3999 else 4000 return rc; 4001 } 4002 4003 #ifndef ASIC_ONLY 4004 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) { 4005 #endif 4006 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, 4007 p_hwfn->mcp_info->func_info.mac, ETH_ALEN); 4008 #ifndef ASIC_ONLY 4009 } else { 4010 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 }; 4011 4012 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN); 4013 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id; 4014 } 4015 #endif 4016 4017 if (ecore_mcp_is_init(p_hwfn)) { 4018 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET) 4019 p_hwfn->hw_info.ovlan = 4020 p_hwfn->mcp_info->func_info.ovlan; 4021 4022 ecore_mcp_cmd_port_init(p_hwfn, p_ptt); 4023 4024 ecore_mcp_get_eee_caps(p_hwfn, p_ptt); 4025 4026 ecore_mcp_read_ufp_config(p_hwfn, p_ptt); 4027 } 4028 4029 if (personality != ECORE_PCI_DEFAULT) { 4030 p_hwfn->hw_info.personality = personality; 4031 } else if (ecore_mcp_is_init(p_hwfn)) { 4032 enum ecore_pci_personality protocol; 4033 4034 protocol = p_hwfn->mcp_info->func_info.protocol; 4035 p_hwfn->hw_info.personality = protocol; 4036 } 4037 4038 #ifndef ASIC_ONLY 4039 /* To overcome ILT lack for emulation, until at least until we'll have 4040 * a definite answer from system about it, allow only PF0 to be RoCE. 4041 */ 4042 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) { 4043 if (!p_hwfn->rel_pf_id) 4044 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE; 4045 else 4046 p_hwfn->hw_info.personality = ECORE_PCI_ETH; 4047 } 4048 #endif 4049 4050 /* although in BB some constellations may support more than 4 tcs, 4051 * that can result in performance penalty in some cases. 4 4052 * represents a good tradeoff between performance and flexibility. 4053 */ 4054 if (IS_ECORE_PACING(p_hwfn)) 4055 p_hwfn->hw_info.num_hw_tc = 1; 4056 else 4057 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 4058 4059 /* start out with a single active tc. This can be increased either 4060 * by dcbx negotiation or by upper layer driver 4061 */ 4062 p_hwfn->hw_info.num_active_tc = 1; 4063 4064 ecore_get_num_funcs(p_hwfn, p_ptt); 4065 4066 if (ecore_mcp_is_init(p_hwfn)) 4067 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 4068 4069 /* In case of forcing the driver's default resource allocation, calling 4070 * ecore_hw_get_resc() should come after initializing the personality 4071 * and after getting the number of functions, since the calculation of 4072 * the resources/features depends on them. 4073 * This order is not harmful if not forcing. 4074 */ 4075 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc); 4076 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) { 4077 rc = ECORE_SUCCESS; 4078 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP; 4079 } 4080 4081 return rc; 4082 } 4083 4084 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn, 4085 struct ecore_ptt *p_ptt) 4086 { 4087 struct ecore_dev *p_dev = p_hwfn->p_dev; 4088 u16 device_id_mask; 4089 u32 tmp; 4090 4091 /* Read Vendor Id / Device Id */ 4092 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET, 4093 &p_dev->vendor_id); 4094 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET, 4095 &p_dev->device_id); 4096 4097 /* Determine type */ 4098 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK; 4099 switch (device_id_mask) { 4100 case ECORE_DEV_ID_MASK_BB: 4101 p_dev->type = ECORE_DEV_TYPE_BB; 4102 break; 4103 case ECORE_DEV_ID_MASK_AH: 4104 p_dev->type = ECORE_DEV_TYPE_AH; 4105 break; 4106 default: 4107 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n", 4108 p_dev->device_id); 4109 return ECORE_ABORTED; 4110 } 4111 4112 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 4113 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM); 4114 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 4115 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV); 4116 4117 /* Learn number of HW-functions */ 4118 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 4119 4120 if (tmp & (1 << p_hwfn->rel_pf_id)) { 4121 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n"); 4122 p_dev->num_hwfns = 2; 4123 } else { 4124 p_dev->num_hwfns = 1; 4125 } 4126 4127 #ifndef ASIC_ONLY 4128 if (CHIP_REV_IS_EMUL(p_dev)) { 4129 /* For some reason we have problems with this register 4130 * in B0 emulation; Simply assume no CMT 4131 */ 4132 DP_NOTICE(p_dev->hwfns, false, 4133 "device on emul - assume no CMT\n"); 4134 p_dev->num_hwfns = 1; 4135 } 4136 #endif 4137 4138 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG); 4139 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID); 4140 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 4141 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL); 4142 4143 DP_INFO(p_dev->hwfns, 4144 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n", 4145 ECORE_IS_BB(p_dev) ? "BB" : "AH", 4146 'A' + p_dev->chip_rev, (int)p_dev->chip_metal, 4147 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id, 4148 p_dev->chip_metal); 4149 4150 if (ECORE_IS_BB_A0(p_dev)) { 4151 DP_NOTICE(p_dev->hwfns, false, 4152 "The chip type/rev (BB A0) is not supported!\n"); 4153 return ECORE_ABORTED; 4154 } 4155 #ifndef ASIC_ONLY 4156 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev)) 4157 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1); 4158 4159 if (CHIP_REV_IS_EMUL(p_dev)) { 4160 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED); 4161 if (tmp & (1 << 29)) { 4162 DP_NOTICE(p_hwfn, false, 4163 "Emulation: Running on a FULL build\n"); 4164 p_dev->b_is_emul_full = true; 4165 } else { 4166 DP_NOTICE(p_hwfn, false, 4167 "Emulation: Running on a REDUCED build\n"); 4168 } 4169 } 4170 #endif 4171 4172 return ECORE_SUCCESS; 4173 } 4174 4175 #ifndef LINUX_REMOVE 4176 void ecore_prepare_hibernate(struct ecore_dev *p_dev) 4177 { 4178 int j; 4179 4180 if (IS_VF(p_dev)) 4181 return; 4182 4183 for_each_hwfn(p_dev, j) { 4184 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 4185 4186 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 4187 "Mark hw/fw uninitialized\n"); 4188 4189 p_hwfn->hw_init_done = false; 4190 4191 ecore_ptt_invalidate(p_hwfn); 4192 } 4193 } 4194 #endif 4195 4196 static enum _ecore_status_t 4197 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, 4198 void OSAL_IOMEM * p_regview, 4199 void OSAL_IOMEM * p_doorbells, 4200 struct ecore_hw_prepare_params *p_params) 4201 { 4202 struct ecore_mdump_retain_data mdump_retain; 4203 struct ecore_dev *p_dev = p_hwfn->p_dev; 4204 struct ecore_mdump_info mdump_info; 4205 enum _ecore_status_t rc = ECORE_SUCCESS; 4206 4207 /* Split PCI bars evenly between hwfns */ 4208 p_hwfn->regview = p_regview; 4209 p_hwfn->doorbells = p_doorbells; 4210 4211 if (IS_VF(p_dev)) 4212 return ecore_vf_hw_prepare(p_hwfn); 4213 4214 /* Validate that chip access is feasible */ 4215 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 4216 DP_ERR(p_hwfn, 4217 "Reading the ME register returns all Fs; Preventing further chip access\n"); 4218 if (p_params->b_relaxed_probe) 4219 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME; 4220 return ECORE_INVAL; 4221 } 4222 4223 get_function_id(p_hwfn); 4224 4225 /* Allocate PTT pool */ 4226 rc = ecore_ptt_pool_alloc(p_hwfn); 4227 if (rc) { 4228 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n"); 4229 if (p_params->b_relaxed_probe) 4230 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM; 4231 goto err0; 4232 } 4233 4234 /* Allocate the main PTT */ 4235 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 4236 4237 /* First hwfn learns basic information, e.g., number of hwfns */ 4238 if (!p_hwfn->my_id) { 4239 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 4240 if (rc != ECORE_SUCCESS) { 4241 if (p_params->b_relaxed_probe) 4242 p_params->p_relaxed_res = 4243 ECORE_HW_PREPARE_FAILED_DEV; 4244 goto err1; 4245 } 4246 } 4247 4248 ecore_hw_hwfn_prepare(p_hwfn); 4249 4250 /* Initialize MCP structure */ 4251 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 4252 if (rc) { 4253 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n"); 4254 if (p_params->b_relaxed_probe) 4255 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM; 4256 goto err1; 4257 } 4258 4259 /* Read the device configuration information from the HW and SHMEM */ 4260 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, 4261 p_params->personality, p_params); 4262 if (rc) { 4263 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n"); 4264 goto err2; 4265 } 4266 4267 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is 4268 * called, since among others it sets the ports number in an engine. 4269 */ 4270 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) && 4271 !p_dev->recov_in_prog) { 4272 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 4273 if (rc != ECORE_SUCCESS) 4274 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n"); 4275 4276 /* Workaround for MFW issue where PF FLR does not cleanup 4277 * IGU block 4278 */ 4279 if (!(p_hwfn->mcp_info->capabilities & 4280 FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP)) 4281 ecore_pf_flr_igu_cleanup(p_hwfn); 4282 } 4283 4284 /* Check if mdump logs/data are present and update the epoch value */ 4285 if (IS_LEAD_HWFN(p_hwfn)) { 4286 #ifndef ASIC_ONLY 4287 if (!CHIP_REV_IS_EMUL(p_dev)) { 4288 #endif 4289 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt, 4290 &mdump_info); 4291 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs) 4292 DP_NOTICE(p_hwfn, false, 4293 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n"); 4294 4295 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt, 4296 &mdump_retain); 4297 if (rc == ECORE_SUCCESS && mdump_retain.valid) 4298 DP_NOTICE(p_hwfn, false, 4299 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n", 4300 mdump_retain.epoch, mdump_retain.pf, 4301 mdump_retain.status); 4302 4303 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt, 4304 p_params->epoch); 4305 #ifndef ASIC_ONLY 4306 } 4307 #endif 4308 } 4309 4310 /* Allocate the init RT array and initialize the init-ops engine */ 4311 rc = ecore_init_alloc(p_hwfn); 4312 if (rc) { 4313 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n"); 4314 if (p_params->b_relaxed_probe) 4315 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM; 4316 goto err2; 4317 } 4318 #ifndef ASIC_ONLY 4319 if (CHIP_REV_IS_FPGA(p_dev)) { 4320 DP_NOTICE(p_hwfn, false, 4321 "FPGA: workaround; Prevent DMAE parities\n"); 4322 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5, 4323 7); 4324 4325 DP_NOTICE(p_hwfn, false, 4326 "FPGA: workaround: Set VF bar0 size\n"); 4327 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 4328 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4); 4329 } 4330 #endif 4331 4332 return rc; 4333 err2: 4334 if (IS_LEAD_HWFN(p_hwfn)) 4335 ecore_iov_free_hw_info(p_dev); 4336 ecore_mcp_free(p_hwfn); 4337 err1: 4338 ecore_hw_hwfn_free(p_hwfn); 4339 err0: 4340 return rc; 4341 } 4342 4343 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, 4344 struct ecore_hw_prepare_params *p_params) 4345 { 4346 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 4347 enum _ecore_status_t rc; 4348 4349 p_dev->chk_reg_fifo = p_params->chk_reg_fifo; 4350 p_dev->allow_mdump = p_params->allow_mdump; 4351 p_hwfn->b_en_pacing = p_params->b_en_pacing; 4352 p_dev->b_is_target = p_params->b_is_target; 4353 4354 if (p_params->b_relaxed_probe) 4355 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS; 4356 4357 /* Store the precompiled init data ptrs */ 4358 if (IS_PF(p_dev)) 4359 ecore_init_iro_array(p_dev); 4360 4361 /* Initialize the first hwfn - will learn number of hwfns */ 4362 rc = ecore_hw_prepare_single(p_hwfn, 4363 p_dev->regview, 4364 p_dev->doorbells, p_params); 4365 if (rc != ECORE_SUCCESS) 4366 return rc; 4367 4368 p_params->personality = p_hwfn->hw_info.personality; 4369 4370 /* initilalize 2nd hwfn if necessary */ 4371 if (ECORE_IS_CMT(p_dev)) { 4372 void OSAL_IOMEM *p_regview, *p_doorbell; 4373 u8 OSAL_IOMEM *addr; 4374 4375 /* adjust bar offset for second engine */ 4376 addr = (u8 OSAL_IOMEM *)p_dev->regview + 4377 ecore_hw_bar_size(p_hwfn, 4378 p_hwfn->p_main_ptt, 4379 BAR_ID_0) / 2; 4380 p_regview = (void OSAL_IOMEM *)addr; 4381 4382 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + 4383 ecore_hw_bar_size(p_hwfn, 4384 p_hwfn->p_main_ptt, 4385 BAR_ID_1) / 2; 4386 p_doorbell = (void OSAL_IOMEM *)addr; 4387 4388 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing; 4389 /* prepare second hw function */ 4390 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview, 4391 p_doorbell, p_params); 4392 4393 /* in case of error, need to free the previously 4394 * initiliazed hwfn 0. 4395 */ 4396 if (rc != ECORE_SUCCESS) { 4397 if (p_params->b_relaxed_probe) 4398 p_params->p_relaxed_res = 4399 ECORE_HW_PREPARE_FAILED_ENG2; 4400 4401 if (IS_PF(p_dev)) { 4402 ecore_init_free(p_hwfn); 4403 ecore_mcp_free(p_hwfn); 4404 ecore_hw_hwfn_free(p_hwfn); 4405 } else { 4406 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n"); 4407 } 4408 return rc; 4409 } 4410 } 4411 4412 return rc; 4413 } 4414 4415 void ecore_hw_remove(struct ecore_dev *p_dev) 4416 { 4417 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 4418 int i; 4419 4420 if (IS_PF(p_dev)) 4421 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 4422 ECORE_OV_DRIVER_STATE_NOT_LOADED); 4423 4424 for_each_hwfn(p_dev, i) { 4425 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 4426 4427 if (IS_VF(p_dev)) { 4428 ecore_vf_pf_release(p_hwfn); 4429 continue; 4430 } 4431 4432 ecore_init_free(p_hwfn); 4433 ecore_hw_hwfn_free(p_hwfn); 4434 ecore_mcp_free(p_hwfn); 4435 4436 #ifdef CONFIG_ECORE_LOCK_ALLOC 4437 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock); 4438 #endif 4439 } 4440 4441 ecore_iov_free_hw_info(p_dev); 4442 } 4443 4444 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev, 4445 struct ecore_chain *p_chain) 4446 { 4447 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL; 4448 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 4449 struct ecore_chain_next *p_next; 4450 u32 size, i; 4451 4452 if (!p_virt) 4453 return; 4454 4455 size = p_chain->elem_size * p_chain->usable_per_page; 4456 4457 for (i = 0; i < p_chain->page_cnt; i++) { 4458 if (!p_virt) 4459 break; 4460 4461 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size); 4462 p_virt_next = p_next->next_virt; 4463 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 4464 4465 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys, 4466 ECORE_CHAIN_PAGE_SIZE); 4467 4468 p_virt = p_virt_next; 4469 p_phys = p_phys_next; 4470 } 4471 } 4472 4473 static void ecore_chain_free_single(struct ecore_dev *p_dev, 4474 struct ecore_chain *p_chain) 4475 { 4476 if (!p_chain->p_virt_addr) 4477 return; 4478 4479 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr, 4480 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE); 4481 } 4482 4483 static void ecore_chain_free_pbl(struct ecore_dev *p_dev, 4484 struct ecore_chain *p_chain) 4485 { 4486 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 4487 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table; 4488 u32 page_cnt = p_chain->page_cnt, i, pbl_size; 4489 4490 if (!pp_virt_addr_tbl) 4491 return; 4492 4493 if (!p_pbl_virt) 4494 goto out; 4495 4496 for (i = 0; i < page_cnt; i++) { 4497 if (!pp_virt_addr_tbl[i]) 4498 break; 4499 4500 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i], 4501 *(dma_addr_t *)p_pbl_virt, 4502 ECORE_CHAIN_PAGE_SIZE); 4503 4504 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE; 4505 } 4506 4507 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE; 4508 4509 if (!p_chain->b_external_pbl) 4510 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table, 4511 p_chain->pbl_sp.p_phys_table, pbl_size); 4512 out: 4513 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl); 4514 } 4515 4516 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 4517 { 4518 switch (p_chain->mode) { 4519 case ECORE_CHAIN_MODE_NEXT_PTR: 4520 ecore_chain_free_next_ptr(p_dev, p_chain); 4521 break; 4522 case ECORE_CHAIN_MODE_SINGLE: 4523 ecore_chain_free_single(p_dev, p_chain); 4524 break; 4525 case ECORE_CHAIN_MODE_PBL: 4526 ecore_chain_free_pbl(p_dev, p_chain); 4527 break; 4528 } 4529 } 4530 4531 static enum _ecore_status_t 4532 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev, 4533 enum ecore_chain_cnt_type cnt_type, 4534 osal_size_t elem_size, u32 page_cnt) 4535 { 4536 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 4537 4538 /* The actual chain size can be larger than the maximal possible value 4539 * after rounding up the requested elements number to pages, and after 4540 * taking into acount the unusuable elements (next-ptr elements). 4541 * The size of a "u16" chain can be (U16_MAX + 1) since the chain 4542 * size/capacity fields are of a u32 type. 4543 */ 4544 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 && 4545 chain_size > ((u32)ECORE_U16_MAX + 1)) || 4546 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 && 4547 chain_size > ECORE_U32_MAX)) { 4548 DP_NOTICE(p_dev, true, 4549 "The actual chain size (0x%lx) is larger than the maximal possible value\n", 4550 (unsigned long)chain_size); 4551 return ECORE_INVAL; 4552 } 4553 4554 return ECORE_SUCCESS; 4555 } 4556 4557 static enum _ecore_status_t 4558 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 4559 { 4560 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL; 4561 dma_addr_t p_phys = 0; 4562 u32 i; 4563 4564 for (i = 0; i < p_chain->page_cnt; i++) { 4565 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, 4566 ECORE_CHAIN_PAGE_SIZE); 4567 if (!p_virt) { 4568 DP_NOTICE(p_dev, false, 4569 "Failed to allocate chain memory\n"); 4570 return ECORE_NOMEM; 4571 } 4572 4573 if (i == 0) { 4574 ecore_chain_init_mem(p_chain, p_virt, p_phys); 4575 ecore_chain_reset(p_chain); 4576 } else { 4577 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev, 4578 p_virt, p_phys); 4579 } 4580 4581 p_virt_prev = p_virt; 4582 } 4583 /* Last page's next element should point to the beginning of the 4584 * chain. 4585 */ 4586 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev, 4587 p_chain->p_virt_addr, 4588 p_chain->p_phys_addr); 4589 4590 return ECORE_SUCCESS; 4591 } 4592 4593 static enum _ecore_status_t 4594 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 4595 { 4596 dma_addr_t p_phys = 0; 4597 void *p_virt = OSAL_NULL; 4598 4599 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE); 4600 if (!p_virt) { 4601 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n"); 4602 return ECORE_NOMEM; 4603 } 4604 4605 ecore_chain_init_mem(p_chain, p_virt, p_phys); 4606 ecore_chain_reset(p_chain); 4607 4608 return ECORE_SUCCESS; 4609 } 4610 4611 static enum _ecore_status_t 4612 ecore_chain_alloc_pbl(struct ecore_dev *p_dev, 4613 struct ecore_chain *p_chain, 4614 struct ecore_chain_ext_pbl *ext_pbl) 4615 { 4616 u32 page_cnt = p_chain->page_cnt, size, i; 4617 dma_addr_t p_phys = 0, p_pbl_phys = 0; 4618 void **pp_virt_addr_tbl = OSAL_NULL; 4619 u8 *p_pbl_virt = OSAL_NULL; 4620 void *p_virt = OSAL_NULL; 4621 4622 size = page_cnt * sizeof(*pp_virt_addr_tbl); 4623 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size); 4624 if (!pp_virt_addr_tbl) { 4625 DP_NOTICE(p_dev, false, 4626 "Failed to allocate memory for the chain virtual addresses table\n"); 4627 return ECORE_NOMEM; 4628 } 4629 4630 /* The allocation of the PBL table is done with its full size, since it 4631 * is expected to be successive. 4632 * ecore_chain_init_pbl_mem() is called even in a case of an allocation 4633 * failure, since pp_virt_addr_tbl was previously allocated, and it 4634 * should be saved to allow its freeing during the error flow. 4635 */ 4636 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE; 4637 4638 if (ext_pbl == OSAL_NULL) { 4639 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size); 4640 } else { 4641 p_pbl_virt = ext_pbl->p_pbl_virt; 4642 p_pbl_phys = ext_pbl->p_pbl_phys; 4643 p_chain->b_external_pbl = true; 4644 } 4645 4646 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 4647 pp_virt_addr_tbl); 4648 if (!p_pbl_virt) { 4649 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n"); 4650 return ECORE_NOMEM; 4651 } 4652 4653 for (i = 0; i < page_cnt; i++) { 4654 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, 4655 ECORE_CHAIN_PAGE_SIZE); 4656 if (!p_virt) { 4657 DP_NOTICE(p_dev, false, 4658 "Failed to allocate chain memory\n"); 4659 return ECORE_NOMEM; 4660 } 4661 4662 if (i == 0) { 4663 ecore_chain_init_mem(p_chain, p_virt, p_phys); 4664 ecore_chain_reset(p_chain); 4665 } 4666 4667 /* Fill the PBL table with the physical address of the page */ 4668 *(dma_addr_t *)p_pbl_virt = p_phys; 4669 /* Keep the virtual address of the page */ 4670 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 4671 4672 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE; 4673 } 4674 4675 return ECORE_SUCCESS; 4676 } 4677 4678 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev, 4679 enum ecore_chain_use_mode intended_use, 4680 enum ecore_chain_mode mode, 4681 enum ecore_chain_cnt_type cnt_type, 4682 u32 num_elems, osal_size_t elem_size, 4683 struct ecore_chain *p_chain, 4684 struct ecore_chain_ext_pbl *ext_pbl) 4685 { 4686 u32 page_cnt; 4687 enum _ecore_status_t rc = ECORE_SUCCESS; 4688 4689 if (mode == ECORE_CHAIN_MODE_SINGLE) 4690 page_cnt = 1; 4691 else 4692 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 4693 4694 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size, 4695 page_cnt); 4696 if (rc) { 4697 DP_NOTICE(p_dev, false, 4698 "Cannot allocate a chain with the given arguments:\n" 4699 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 4700 intended_use, mode, cnt_type, num_elems, elem_size); 4701 return rc; 4702 } 4703 4704 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use, 4705 mode, cnt_type, p_dev->dp_ctx); 4706 4707 switch (mode) { 4708 case ECORE_CHAIN_MODE_NEXT_PTR: 4709 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain); 4710 break; 4711 case ECORE_CHAIN_MODE_SINGLE: 4712 rc = ecore_chain_alloc_single(p_dev, p_chain); 4713 break; 4714 case ECORE_CHAIN_MODE_PBL: 4715 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl); 4716 break; 4717 } 4718 if (rc) 4719 goto nomem; 4720 4721 return ECORE_SUCCESS; 4722 4723 nomem: 4724 ecore_chain_free(p_dev, p_chain); 4725 return rc; 4726 } 4727 4728 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn, 4729 u16 src_id, u16 *dst_id) 4730 { 4731 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) { 4732 u16 min, max; 4733 4734 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE); 4735 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE); 4736 DP_NOTICE(p_hwfn, true, 4737 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 4738 src_id, min, max); 4739 4740 return ECORE_INVAL; 4741 } 4742 4743 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id; 4744 4745 return ECORE_SUCCESS; 4746 } 4747 4748 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn, 4749 u8 src_id, u8 *dst_id) 4750 { 4751 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) { 4752 u8 min, max; 4753 4754 min = (u8)RESC_START(p_hwfn, ECORE_VPORT); 4755 max = min + RESC_NUM(p_hwfn, ECORE_VPORT); 4756 DP_NOTICE(p_hwfn, true, 4757 "vport id [%d] is not valid, available indices [%d - %d]\n", 4758 src_id, min, max); 4759 4760 return ECORE_INVAL; 4761 } 4762 4763 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id; 4764 4765 return ECORE_SUCCESS; 4766 } 4767 4768 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn, 4769 u8 src_id, u8 *dst_id) 4770 { 4771 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) { 4772 u8 min, max; 4773 4774 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG); 4775 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG); 4776 DP_NOTICE(p_hwfn, true, 4777 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 4778 src_id, min, max); 4779 4780 return ECORE_INVAL; 4781 } 4782 4783 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id; 4784 4785 return ECORE_SUCCESS; 4786 } 4787 4788 static enum _ecore_status_t 4789 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn, 4790 struct ecore_ptt *p_ptt, u32 high, u32 low, 4791 u32 *p_entry_num) 4792 { 4793 u32 en; 4794 int i; 4795 4796 /* Find a free entry and utilize it */ 4797 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 4798 en = ecore_rd(p_hwfn, p_ptt, 4799 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + 4800 i * sizeof(u32)); 4801 if (en) 4802 continue; 4803 ecore_wr(p_hwfn, p_ptt, 4804 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 4805 2 * i * sizeof(u32), low); 4806 ecore_wr(p_hwfn, p_ptt, 4807 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 4808 (2 * i + 1) * sizeof(u32), high); 4809 ecore_wr(p_hwfn, p_ptt, 4810 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + 4811 i * sizeof(u32), 0); 4812 ecore_wr(p_hwfn, p_ptt, 4813 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + 4814 i * sizeof(u32), 0); 4815 ecore_wr(p_hwfn, p_ptt, 4816 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + 4817 i * sizeof(u32), 1); 4818 break; 4819 } 4820 4821 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 4822 return ECORE_NORESOURCES; 4823 4824 *p_entry_num = i; 4825 4826 return ECORE_SUCCESS; 4827 } 4828 4829 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn, 4830 struct ecore_ptt *p_ptt, u8 *p_filter) 4831 { 4832 u32 high, low, entry_num; 4833 enum _ecore_status_t rc = ECORE_SUCCESS; 4834 4835 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, 4836 &p_hwfn->p_dev->mf_bits)) 4837 return ECORE_SUCCESS; 4838 4839 high = p_filter[1] | (p_filter[0] << 8); 4840 low = p_filter[5] | (p_filter[4] << 8) | 4841 (p_filter[3] << 16) | (p_filter[2] << 24); 4842 4843 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) 4844 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low, 4845 &entry_num); 4846 if (rc != ECORE_SUCCESS) { 4847 DP_NOTICE(p_hwfn, false, 4848 "Failed to find an empty LLH filter to utilize\n"); 4849 return rc; 4850 } 4851 4852 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 4853 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n", 4854 p_filter[0], p_filter[1], p_filter[2], p_filter[3], 4855 p_filter[4], p_filter[5], entry_num); 4856 4857 return rc; 4858 } 4859 4860 static enum _ecore_status_t 4861 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn, 4862 struct ecore_ptt *p_ptt, u32 high, u32 low, 4863 u32 *p_entry_num) 4864 { 4865 int i; 4866 4867 /* Find the entry and clean it */ 4868 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 4869 if (ecore_rd(p_hwfn, p_ptt, 4870 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 4871 2 * i * sizeof(u32)) != low) 4872 continue; 4873 if (ecore_rd(p_hwfn, p_ptt, 4874 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 4875 (2 * i + 1) * sizeof(u32)) != high) 4876 continue; 4877 4878 ecore_wr(p_hwfn, p_ptt, 4879 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0); 4880 ecore_wr(p_hwfn, p_ptt, 4881 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 4882 2 * i * sizeof(u32), 0); 4883 ecore_wr(p_hwfn, p_ptt, 4884 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 4885 (2 * i + 1) * sizeof(u32), 0); 4886 break; 4887 } 4888 4889 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 4890 return ECORE_INVAL; 4891 4892 *p_entry_num = i; 4893 4894 return ECORE_SUCCESS; 4895 } 4896 4897 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn, 4898 struct ecore_ptt *p_ptt, u8 *p_filter) 4899 { 4900 u32 high, low, entry_num; 4901 enum _ecore_status_t rc = ECORE_SUCCESS; 4902 4903 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, 4904 &p_hwfn->p_dev->mf_bits)) 4905 return; 4906 4907 high = p_filter[1] | (p_filter[0] << 8); 4908 low = p_filter[5] | (p_filter[4] << 8) | 4909 (p_filter[3] << 16) | (p_filter[2] << 24); 4910 4911 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) 4912 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high, 4913 low, &entry_num); 4914 if (rc != ECORE_SUCCESS) { 4915 DP_NOTICE(p_hwfn, false, 4916 "Tried to remove a non-configured filter\n"); 4917 return; 4918 } 4919 4920 4921 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 4922 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n", 4923 p_filter[0], p_filter[1], p_filter[2], p_filter[3], 4924 p_filter[4], p_filter[5], entry_num); 4925 } 4926 4927 static enum _ecore_status_t 4928 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn, 4929 struct ecore_ptt *p_ptt, 4930 enum ecore_llh_port_filter_type_t type, 4931 u32 high, u32 low, u32 *p_entry_num) 4932 { 4933 u32 en; 4934 int i; 4935 4936 /* Find a free entry and utilize it */ 4937 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 4938 en = ecore_rd(p_hwfn, p_ptt, 4939 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + 4940 i * sizeof(u32)); 4941 if (en) 4942 continue; 4943 ecore_wr(p_hwfn, p_ptt, 4944 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 4945 2 * i * sizeof(u32), low); 4946 ecore_wr(p_hwfn, p_ptt, 4947 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 4948 (2 * i + 1) * sizeof(u32), high); 4949 ecore_wr(p_hwfn, p_ptt, 4950 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + 4951 i * sizeof(u32), 1); 4952 ecore_wr(p_hwfn, p_ptt, 4953 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + 4954 i * sizeof(u32), 1 << type); 4955 ecore_wr(p_hwfn, p_ptt, 4956 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1); 4957 break; 4958 } 4959 4960 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 4961 return ECORE_NORESOURCES; 4962 4963 *p_entry_num = i; 4964 4965 return ECORE_SUCCESS; 4966 } 4967 4968 enum _ecore_status_t 4969 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn, 4970 struct ecore_ptt *p_ptt, 4971 u16 source_port_or_eth_type, 4972 u16 dest_port, 4973 enum ecore_llh_port_filter_type_t type) 4974 { 4975 u32 high, low, entry_num; 4976 enum _ecore_status_t rc = ECORE_SUCCESS; 4977 4978 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, 4979 &p_hwfn->p_dev->mf_bits)) 4980 return rc; 4981 4982 high = 0; 4983 low = 0; 4984 4985 switch (type) { 4986 case ECORE_LLH_FILTER_ETHERTYPE: 4987 high = source_port_or_eth_type; 4988 break; 4989 case ECORE_LLH_FILTER_TCP_SRC_PORT: 4990 case ECORE_LLH_FILTER_UDP_SRC_PORT: 4991 low = source_port_or_eth_type << 16; 4992 break; 4993 case ECORE_LLH_FILTER_TCP_DEST_PORT: 4994 case ECORE_LLH_FILTER_UDP_DEST_PORT: 4995 low = dest_port; 4996 break; 4997 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 4998 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 4999 low = (source_port_or_eth_type << 16) | dest_port; 5000 break; 5001 default: 5002 DP_NOTICE(p_hwfn, true, 5003 "Non valid LLH protocol filter type %d\n", type); 5004 return ECORE_INVAL; 5005 } 5006 5007 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) 5008 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type, 5009 high, low, &entry_num); 5010 if (rc != ECORE_SUCCESS) { 5011 DP_NOTICE(p_hwfn, false, 5012 "Failed to find an empty LLH filter to utilize\n"); 5013 return rc; 5014 } 5015 switch (type) { 5016 case ECORE_LLH_FILTER_ETHERTYPE: 5017 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 5018 "ETH type %x is added at %d\n", 5019 source_port_or_eth_type, entry_num); 5020 break; 5021 case ECORE_LLH_FILTER_TCP_SRC_PORT: 5022 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 5023 "TCP src port %x is added at %d\n", 5024 source_port_or_eth_type, entry_num); 5025 break; 5026 case ECORE_LLH_FILTER_UDP_SRC_PORT: 5027 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 5028 "UDP src port %x is added at %d\n", 5029 source_port_or_eth_type, entry_num); 5030 break; 5031 case ECORE_LLH_FILTER_TCP_DEST_PORT: 5032 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 5033 "TCP dst port %x is added at %d\n", dest_port, 5034 entry_num); 5035 break; 5036 case ECORE_LLH_FILTER_UDP_DEST_PORT: 5037 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 5038 "UDP dst port %x is added at %d\n", dest_port, 5039 entry_num); 5040 break; 5041 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 5042 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 5043 "TCP src/dst ports %x/%x are added at %d\n", 5044 source_port_or_eth_type, dest_port, entry_num); 5045 break; 5046 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 5047 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 5048 "UDP src/dst ports %x/%x are added at %d\n", 5049 source_port_or_eth_type, dest_port, entry_num); 5050 break; 5051 } 5052 5053 return rc; 5054 } 5055 5056 static enum _ecore_status_t 5057 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn, 5058 struct ecore_ptt *p_ptt, 5059 enum ecore_llh_port_filter_type_t type, 5060 u32 high, u32 low, u32 *p_entry_num) 5061 { 5062 int i; 5063 5064 /* Find the entry and clean it */ 5065 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 5066 if (!ecore_rd(p_hwfn, p_ptt, 5067 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + 5068 i * sizeof(u32))) 5069 continue; 5070 if (!ecore_rd(p_hwfn, p_ptt, 5071 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + 5072 i * sizeof(u32))) 5073 continue; 5074 if (!(ecore_rd(p_hwfn, p_ptt, 5075 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + 5076 i * sizeof(u32)) & (1 << type))) 5077 continue; 5078 if (ecore_rd(p_hwfn, p_ptt, 5079 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 5080 2 * i * sizeof(u32)) != low) 5081 continue; 5082 if (ecore_rd(p_hwfn, p_ptt, 5083 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 5084 (2 * i + 1) * sizeof(u32)) != high) 5085 continue; 5086 5087 ecore_wr(p_hwfn, p_ptt, 5088 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0); 5089 ecore_wr(p_hwfn, p_ptt, 5090 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + 5091 i * sizeof(u32), 0); 5092 ecore_wr(p_hwfn, p_ptt, 5093 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + 5094 i * sizeof(u32), 0); 5095 ecore_wr(p_hwfn, p_ptt, 5096 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 5097 2 * i * sizeof(u32), 0); 5098 ecore_wr(p_hwfn, p_ptt, 5099 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 5100 (2 * i + 1) * sizeof(u32), 0); 5101 break; 5102 } 5103 5104 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 5105 return ECORE_INVAL; 5106 5107 *p_entry_num = i; 5108 5109 return ECORE_SUCCESS; 5110 } 5111 5112 void 5113 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn, 5114 struct ecore_ptt *p_ptt, 5115 u16 source_port_or_eth_type, 5116 u16 dest_port, 5117 enum ecore_llh_port_filter_type_t type) 5118 { 5119 u32 high, low, entry_num; 5120 enum _ecore_status_t rc = ECORE_SUCCESS; 5121 5122 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, 5123 &p_hwfn->p_dev->mf_bits)) 5124 return; 5125 5126 high = 0; 5127 low = 0; 5128 5129 switch (type) { 5130 case ECORE_LLH_FILTER_ETHERTYPE: 5131 high = source_port_or_eth_type; 5132 break; 5133 case ECORE_LLH_FILTER_TCP_SRC_PORT: 5134 case ECORE_LLH_FILTER_UDP_SRC_PORT: 5135 low = source_port_or_eth_type << 16; 5136 break; 5137 case ECORE_LLH_FILTER_TCP_DEST_PORT: 5138 case ECORE_LLH_FILTER_UDP_DEST_PORT: 5139 low = dest_port; 5140 break; 5141 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 5142 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 5143 low = (source_port_or_eth_type << 16) | dest_port; 5144 break; 5145 default: 5146 DP_NOTICE(p_hwfn, true, 5147 "Non valid LLH protocol filter type %d\n", type); 5148 return; 5149 } 5150 5151 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) 5152 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type, 5153 high, low, 5154 &entry_num); 5155 if (rc != ECORE_SUCCESS) { 5156 DP_NOTICE(p_hwfn, false, 5157 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n", 5158 type, source_port_or_eth_type, dest_port); 5159 return; 5160 } 5161 5162 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 5163 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n", 5164 type, source_port_or_eth_type, dest_port, entry_num); 5165 } 5166 5167 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn, 5168 struct ecore_ptt *p_ptt) 5169 { 5170 int i; 5171 5172 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 5173 return; 5174 5175 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 5176 ecore_wr(p_hwfn, p_ptt, 5177 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + 5178 i * sizeof(u32), 0); 5179 ecore_wr(p_hwfn, p_ptt, 5180 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 5181 2 * i * sizeof(u32), 0); 5182 ecore_wr(p_hwfn, p_ptt, 5183 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 5184 (2 * i + 1) * sizeof(u32), 0); 5185 } 5186 } 5187 5188 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn, 5189 struct ecore_ptt *p_ptt) 5190 { 5191 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, 5192 &p_hwfn->p_dev->mf_bits) && 5193 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, 5194 &p_hwfn->p_dev->mf_bits)) 5195 return; 5196 5197 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev)) 5198 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt); 5199 } 5200 5201 enum _ecore_status_t 5202 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn, 5203 struct ecore_ptt *p_ptt) 5204 { 5205 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) { 5206 ecore_wr(p_hwfn, p_ptt, 5207 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 5208 1 << p_hwfn->abs_pf_id / 2); 5209 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0); 5210 return ECORE_SUCCESS; 5211 } 5212 5213 DP_NOTICE(p_hwfn, false, 5214 "This function can't be set as default\n"); 5215 return ECORE_INVAL; 5216 } 5217 5218 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn, 5219 struct ecore_ptt *p_ptt, 5220 u32 hw_addr, void *p_eth_qzone, 5221 osal_size_t eth_qzone_size, 5222 u8 timeset) 5223 { 5224 struct coalescing_timeset *p_coal_timeset; 5225 5226 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) { 5227 DP_NOTICE(p_hwfn, true, 5228 "Coalescing configuration not enabled\n"); 5229 return ECORE_INVAL; 5230 } 5231 5232 p_coal_timeset = p_eth_qzone; 5233 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size); 5234 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 5235 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 5236 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 5237 5238 return ECORE_SUCCESS; 5239 } 5240 5241 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn, 5242 u16 rx_coal, u16 tx_coal, 5243 void *p_handle) 5244 { 5245 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle; 5246 enum _ecore_status_t rc = ECORE_SUCCESS; 5247 struct ecore_ptt *p_ptt; 5248 5249 /* TODO - Configuring a single queue's coalescing but 5250 * claiming all queues are abiding same configuration 5251 * for PF and VF both. 5252 */ 5253 5254 if (IS_VF(p_hwfn->p_dev)) 5255 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal, 5256 tx_coal, p_cid); 5257 5258 p_ptt = ecore_ptt_acquire(p_hwfn); 5259 if (!p_ptt) 5260 return ECORE_AGAIN; 5261 5262 if (rx_coal) { 5263 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid); 5264 if (rc) 5265 goto out; 5266 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal; 5267 } 5268 5269 if (tx_coal) { 5270 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid); 5271 if (rc) 5272 goto out; 5273 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal; 5274 } 5275 out: 5276 ecore_ptt_release(p_hwfn, p_ptt); 5277 5278 return rc; 5279 } 5280 5281 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn, 5282 struct ecore_ptt *p_ptt, 5283 u16 coalesce, 5284 struct ecore_queue_cid *p_cid) 5285 { 5286 struct ustorm_eth_queue_zone eth_qzone; 5287 u8 timeset, timer_res; 5288 u32 address; 5289 enum _ecore_status_t rc; 5290 5291 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 5292 if (coalesce <= 0x7F) { 5293 timer_res = 0; 5294 } else if (coalesce <= 0xFF) { 5295 timer_res = 1; 5296 } else if (coalesce <= 0x1FF) { 5297 timer_res = 2; 5298 } else { 5299 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 5300 return ECORE_INVAL; 5301 } 5302 timeset = (u8)(coalesce >> timer_res); 5303 5304 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, 5305 p_cid->sb_igu_id, false); 5306 if (rc != ECORE_SUCCESS) 5307 goto out; 5308 5309 address = BAR0_MAP_REG_USDM_RAM + 5310 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 5311 5312 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 5313 sizeof(struct ustorm_eth_queue_zone), timeset); 5314 if (rc != ECORE_SUCCESS) 5315 goto out; 5316 5317 out: 5318 return rc; 5319 } 5320 5321 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn, 5322 struct ecore_ptt *p_ptt, 5323 u16 coalesce, 5324 struct ecore_queue_cid *p_cid) 5325 { 5326 struct xstorm_eth_queue_zone eth_qzone; 5327 u8 timeset, timer_res; 5328 u32 address; 5329 enum _ecore_status_t rc; 5330 5331 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 5332 if (coalesce <= 0x7F) { 5333 timer_res = 0; 5334 } else if (coalesce <= 0xFF) { 5335 timer_res = 1; 5336 } else if (coalesce <= 0x1FF) { 5337 timer_res = 2; 5338 } else { 5339 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 5340 return ECORE_INVAL; 5341 } 5342 5343 timeset = (u8)(coalesce >> timer_res); 5344 5345 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, 5346 p_cid->sb_igu_id, true); 5347 if (rc != ECORE_SUCCESS) 5348 goto out; 5349 5350 address = BAR0_MAP_REG_XSDM_RAM + 5351 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 5352 5353 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 5354 sizeof(struct xstorm_eth_queue_zone), timeset); 5355 out: 5356 return rc; 5357 } 5358 5359 /* Calculate final WFQ values for all vports and configure it. 5360 * After this configuration each vport must have 5361 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT 5362 */ 5363 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn, 5364 struct ecore_ptt *p_ptt, 5365 u32 min_pf_rate) 5366 { 5367 struct init_qm_vport_params *vport_params; 5368 int i; 5369 5370 vport_params = p_hwfn->qm_info.qm_vport_params; 5371 5372 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5373 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 5374 5375 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) / 5376 min_pf_rate; 5377 ecore_init_vport_wfq(p_hwfn, p_ptt, 5378 vport_params[i].first_tx_pq_id, 5379 vport_params[i].vport_wfq); 5380 } 5381 } 5382 5383 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn) 5384 { 5385 int i; 5386 5387 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 5388 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 5389 } 5390 5391 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn, 5392 struct ecore_ptt *p_ptt) 5393 { 5394 struct init_qm_vport_params *vport_params; 5395 int i; 5396 5397 vport_params = p_hwfn->qm_info.qm_vport_params; 5398 5399 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5400 ecore_init_wfq_default_param(p_hwfn); 5401 ecore_init_vport_wfq(p_hwfn, p_ptt, 5402 vport_params[i].first_tx_pq_id, 5403 vport_params[i].vport_wfq); 5404 } 5405 } 5406 5407 /* This function performs several validations for WFQ 5408 * configuration and required min rate for a given vport 5409 * 1. req_rate must be greater than one percent of min_pf_rate. 5410 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 5411 * rates to get less than one percent of min_pf_rate. 5412 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 5413 */ 5414 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn, 5415 u16 vport_id, u32 req_rate, 5416 u32 min_pf_rate) 5417 { 5418 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 5419 int non_requested_count = 0, req_count = 0, i, num_vports; 5420 5421 num_vports = p_hwfn->qm_info.num_vports; 5422 5423 /* Accounting for the vports which are configured for WFQ explicitly */ 5424 5425 for (i = 0; i < num_vports; i++) { 5426 u32 tmp_speed; 5427 5428 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) { 5429 req_count++; 5430 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 5431 total_req_min_rate += tmp_speed; 5432 } 5433 } 5434 5435 /* Include current vport data as well */ 5436 req_count++; 5437 total_req_min_rate += req_rate; 5438 non_requested_count = num_vports - req_count; 5439 5440 /* validate possible error cases */ 5441 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) { 5442 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 5443 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 5444 vport_id, req_rate, min_pf_rate); 5445 return ECORE_INVAL; 5446 } 5447 5448 /* TBD - for number of vports greater than 100 */ 5449 if (num_vports > ECORE_WFQ_UNIT) { 5450 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 5451 "Number of vports is greater than %d\n", 5452 ECORE_WFQ_UNIT); 5453 return ECORE_INVAL; 5454 } 5455 5456 if (total_req_min_rate > min_pf_rate) { 5457 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 5458 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 5459 total_req_min_rate, min_pf_rate); 5460 return ECORE_INVAL; 5461 } 5462 5463 /* Data left for non requested vports */ 5464 total_left_rate = min_pf_rate - total_req_min_rate; 5465 left_rate_per_vp = total_left_rate / non_requested_count; 5466 5467 /* validate if non requested get < 1% of min bw */ 5468 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) { 5469 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 5470 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 5471 left_rate_per_vp, min_pf_rate); 5472 return ECORE_INVAL; 5473 } 5474 5475 /* now req_rate for given vport passes all scenarios. 5476 * assign final wfq rates to all vports. 5477 */ 5478 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 5479 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 5480 5481 for (i = 0; i < num_vports; i++) { 5482 if (p_hwfn->qm_info.wfq_data[i].configured) 5483 continue; 5484 5485 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 5486 } 5487 5488 return ECORE_SUCCESS; 5489 } 5490 5491 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn, 5492 struct ecore_ptt *p_ptt, 5493 u16 vp_id, u32 rate) 5494 { 5495 struct ecore_mcp_link_state *p_link; 5496 int rc = ECORE_SUCCESS; 5497 5498 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output; 5499 5500 if (!p_link->min_pf_rate) { 5501 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 5502 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 5503 return rc; 5504 } 5505 5506 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 5507 5508 if (rc == ECORE_SUCCESS) 5509 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, 5510 p_link->min_pf_rate); 5511 else 5512 DP_NOTICE(p_hwfn, false, 5513 "Validation failed while configuring min rate\n"); 5514 5515 return rc; 5516 } 5517 5518 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn, 5519 struct ecore_ptt *p_ptt, 5520 u32 min_pf_rate) 5521 { 5522 bool use_wfq = false; 5523 int rc = ECORE_SUCCESS; 5524 u16 i; 5525 5526 /* Validate all pre configured vports for wfq */ 5527 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5528 u32 rate; 5529 5530 if (!p_hwfn->qm_info.wfq_data[i].configured) 5531 continue; 5532 5533 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 5534 use_wfq = true; 5535 5536 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 5537 if (rc != ECORE_SUCCESS) { 5538 DP_NOTICE(p_hwfn, false, 5539 "WFQ validation failed while configuring min rate\n"); 5540 break; 5541 } 5542 } 5543 5544 if (rc == ECORE_SUCCESS && use_wfq) 5545 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 5546 else 5547 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt); 5548 5549 return rc; 5550 } 5551 5552 /* Main API for ecore clients to configure vport min rate. 5553 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 5554 * rate - Speed in Mbps needs to be assigned to a given vport. 5555 */ 5556 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate) 5557 { 5558 int i, rc = ECORE_INVAL; 5559 5560 /* TBD - for multiple hardware functions - that is 100 gig */ 5561 if (ECORE_IS_CMT(p_dev)) { 5562 DP_NOTICE(p_dev, false, 5563 "WFQ configuration is not supported for this device\n"); 5564 return rc; 5565 } 5566 5567 for_each_hwfn(p_dev, i) { 5568 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 5569 struct ecore_ptt *p_ptt; 5570 5571 p_ptt = ecore_ptt_acquire(p_hwfn); 5572 if (!p_ptt) 5573 return ECORE_TIMEOUT; 5574 5575 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 5576 5577 if (rc != ECORE_SUCCESS) { 5578 ecore_ptt_release(p_hwfn, p_ptt); 5579 return rc; 5580 } 5581 5582 ecore_ptt_release(p_hwfn, p_ptt); 5583 } 5584 5585 return rc; 5586 } 5587 5588 /* API to configure WFQ from mcp link change */ 5589 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, 5590 struct ecore_ptt *p_ptt, 5591 u32 min_pf_rate) 5592 { 5593 int i; 5594 5595 /* TBD - for multiple hardware functions - that is 100 gig */ 5596 if (ECORE_IS_CMT(p_dev)) { 5597 DP_VERBOSE(p_dev, ECORE_MSG_LINK, 5598 "WFQ configuration is not supported for this device\n"); 5599 return; 5600 } 5601 5602 for_each_hwfn(p_dev, i) { 5603 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 5604 5605 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 5606 min_pf_rate); 5607 } 5608 } 5609 5610 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn, 5611 struct ecore_ptt *p_ptt, 5612 struct ecore_mcp_link_state *p_link, 5613 u8 max_bw) 5614 { 5615 int rc = ECORE_SUCCESS; 5616 5617 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 5618 5619 if (!p_link->line_speed && (max_bw != 100)) 5620 return rc; 5621 5622 p_link->speed = (p_link->line_speed * max_bw) / 100; 5623 p_hwfn->qm_info.pf_rl = p_link->speed; 5624 5625 /* Since the limiter also affects Tx-switched traffic, we don't want it 5626 * to limit such traffic in case there's no actual limit. 5627 * In that case, set limit to imaginary high boundary. 5628 */ 5629 if (max_bw == 100) 5630 p_hwfn->qm_info.pf_rl = 100000; 5631 5632 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 5633 p_hwfn->qm_info.pf_rl); 5634 5635 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 5636 "Configured MAX bandwidth to be %08x Mb/sec\n", 5637 p_link->speed); 5638 5639 return rc; 5640 } 5641 5642 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 5643 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw) 5644 { 5645 int i, rc = ECORE_INVAL; 5646 5647 if (max_bw < 1 || max_bw > 100) { 5648 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n"); 5649 return rc; 5650 } 5651 5652 for_each_hwfn(p_dev, i) { 5653 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 5654 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev); 5655 struct ecore_mcp_link_state *p_link; 5656 struct ecore_ptt *p_ptt; 5657 5658 p_link = &p_lead->mcp_info->link_output; 5659 5660 p_ptt = ecore_ptt_acquire(p_hwfn); 5661 if (!p_ptt) 5662 return ECORE_TIMEOUT; 5663 5664 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt, 5665 p_link, max_bw); 5666 5667 ecore_ptt_release(p_hwfn, p_ptt); 5668 5669 if (rc != ECORE_SUCCESS) 5670 break; 5671 } 5672 5673 return rc; 5674 } 5675 5676 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn, 5677 struct ecore_ptt *p_ptt, 5678 struct ecore_mcp_link_state *p_link, 5679 u8 min_bw) 5680 { 5681 int rc = ECORE_SUCCESS; 5682 5683 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 5684 p_hwfn->qm_info.pf_wfq = min_bw; 5685 5686 if (!p_link->line_speed) 5687 return rc; 5688 5689 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 5690 5691 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 5692 5693 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 5694 "Configured MIN bandwidth to be %d Mb/sec\n", 5695 p_link->min_pf_rate); 5696 5697 return rc; 5698 } 5699 5700 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 5701 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw) 5702 { 5703 int i, rc = ECORE_INVAL; 5704 5705 if (min_bw < 1 || min_bw > 100) { 5706 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n"); 5707 return rc; 5708 } 5709 5710 for_each_hwfn(p_dev, i) { 5711 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 5712 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev); 5713 struct ecore_mcp_link_state *p_link; 5714 struct ecore_ptt *p_ptt; 5715 5716 p_link = &p_lead->mcp_info->link_output; 5717 5718 p_ptt = ecore_ptt_acquire(p_hwfn); 5719 if (!p_ptt) 5720 return ECORE_TIMEOUT; 5721 5722 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt, 5723 p_link, min_bw); 5724 if (rc != ECORE_SUCCESS) { 5725 ecore_ptt_release(p_hwfn, p_ptt); 5726 return rc; 5727 } 5728 5729 if (p_link->min_pf_rate) { 5730 u32 min_rate = p_link->min_pf_rate; 5731 5732 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn, 5733 p_ptt, 5734 min_rate); 5735 } 5736 5737 ecore_ptt_release(p_hwfn, p_ptt); 5738 } 5739 5740 return rc; 5741 } 5742 5743 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 5744 { 5745 struct ecore_mcp_link_state *p_link; 5746 5747 p_link = &p_hwfn->mcp_info->link_output; 5748 5749 if (p_link->min_pf_rate) 5750 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt); 5751 5752 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0, 5753 sizeof(*p_hwfn->qm_info.wfq_data) * 5754 p_hwfn->qm_info.num_vports); 5755 } 5756 5757 int ecore_device_num_engines(struct ecore_dev *p_dev) 5758 { 5759 return ECORE_IS_BB(p_dev) ? 2 : 1; 5760 } 5761 5762 int ecore_device_num_ports(struct ecore_dev *p_dev) 5763 { 5764 return p_dev->num_ports; 5765 } 5766 5767 void ecore_set_fw_mac_addr(__le16 *fw_msb, 5768 __le16 *fw_mid, 5769 __le16 *fw_lsb, 5770 u8 *mac) 5771 { 5772 ((u8 *)fw_msb)[0] = mac[1]; 5773 ((u8 *)fw_msb)[1] = mac[0]; 5774 ((u8 *)fw_mid)[0] = mac[3]; 5775 ((u8 *)fw_mid)[1] = mac[2]; 5776 ((u8 *)fw_lsb)[0] = mac[5]; 5777 ((u8 *)fw_lsb)[1] = mac[4]; 5778 } 5779