1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017-2021 Marvell International Ltd. 3 * Copyright(c) 2017-2021 Semihalf. 4 * All rights reserved. 5 */ 6 7 #include <rte_string_fns.h> 8 #include <ethdev_driver.h> 9 #include <rte_kvargs.h> 10 #include <rte_log.h> 11 #include <rte_malloc.h> 12 #include <rte_bus_vdev.h> 13 14 #include <fcntl.h> 15 #include <linux/ethtool.h> 16 #include <linux/sockios.h> 17 #include <net/if.h> 18 #include <net/if_arp.h> 19 #include <sys/ioctl.h> 20 #include <sys/socket.h> 21 #include <sys/stat.h> 22 #include <sys/types.h> 23 24 #include <rte_mvep_common.h> 25 #include "mrvl_ethdev.h" 26 #include "mrvl_qos.h" 27 #include "mrvl_flow.h" 28 #include "mrvl_mtr.h" 29 #include "mrvl_tm.h" 30 31 /* bitmask with reserved hifs */ 32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F 33 /* bitmask with reserved bpools */ 34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 35 /* bitmask with reserved kernel RSS tables */ 36 #define MRVL_MUSDK_RSS_RESERVED 0x0F 37 /* maximum number of available hifs */ 38 #define MRVL_MUSDK_HIFS_MAX 9 39 40 /* prefetch shift */ 41 #define MRVL_MUSDK_PREFETCH_SHIFT 2 42 43 /* TCAM has 25 entries reserved for uc/mc filter entries 44 * + 1 for primary mac address 45 */ 46 #define MRVL_MAC_ADDRS_MAX (1 + 25) 47 #define MRVL_MATCH_LEN 16 48 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) 49 /* Maximum allowable packet size */ 50 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE) 51 52 #define MRVL_IFACE_NAME_ARG "iface" 53 #define MRVL_CFG_ARG "cfg" 54 55 #define MRVL_ARP_LENGTH 28 56 57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL 58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000 59 60 /** Port Rx offload capabilities */ 61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \ 62 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 63 DEV_RX_OFFLOAD_CHECKSUM) 64 65 /** Port Tx offloads capabilities */ 66 #define MRVL_TX_OFFLOAD_CHECKSUM (DEV_TX_OFFLOAD_IPV4_CKSUM | \ 67 DEV_TX_OFFLOAD_UDP_CKSUM | \ 68 DEV_TX_OFFLOAD_TCP_CKSUM) 69 #define MRVL_TX_OFFLOADS (MRVL_TX_OFFLOAD_CHECKSUM | \ 70 DEV_TX_OFFLOAD_MULTI_SEGS) 71 72 #define MRVL_TX_PKT_OFFLOADS (PKT_TX_IP_CKSUM | \ 73 PKT_TX_TCP_CKSUM | \ 74 PKT_TX_UDP_CKSUM) 75 76 static const char * const valid_args[] = { 77 MRVL_IFACE_NAME_ARG, 78 MRVL_CFG_ARG, 79 NULL 80 }; 81 82 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED; 83 static struct pp2_hif *hifs[RTE_MAX_LCORE]; 84 static int used_bpools[PP2_NUM_PKT_PROC] = { 85 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED 86 }; 87 88 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; 89 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; 90 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; 91 static int dummy_pool_id[PP2_NUM_PKT_PROC]; 92 struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC] = {0}; 93 94 struct mrvl_ifnames { 95 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; 96 int idx; 97 }; 98 99 /* 100 * To use buffer harvesting based on loopback port shadow queue structure 101 * was introduced for buffers information bookkeeping. 102 * 103 * Before sending the packet, related buffer information (pp2_buff_inf) is 104 * stored in shadow queue. After packet is transmitted no longer used 105 * packet buffer is released back to it's original hardware pool, 106 * on condition it originated from interface. 107 * In case it was generated by application itself i.e: mbuf->port field is 108 * 0xff then its released to software mempool. 109 */ 110 struct mrvl_shadow_txq { 111 int head; /* write index - used when sending buffers */ 112 int tail; /* read index - used when releasing buffers */ 113 u16 size; /* queue occupied size */ 114 u16 num_to_release; /* number of descriptors sent, that can be 115 * released 116 */ 117 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */ 118 }; 119 120 struct mrvl_rxq { 121 struct mrvl_priv *priv; 122 struct rte_mempool *mp; 123 int queue_id; 124 int port_id; 125 int cksum_enabled; 126 uint64_t bytes_recv; 127 uint64_t drop_mac; 128 }; 129 130 struct mrvl_txq { 131 struct mrvl_priv *priv; 132 int queue_id; 133 int port_id; 134 uint64_t bytes_sent; 135 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; 136 int tx_deferred_start; 137 }; 138 139 static int mrvl_lcore_first; 140 static int mrvl_lcore_last; 141 static int mrvl_dev_num; 142 143 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); 144 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, 145 struct pp2_hif *hif, unsigned int core_id, 146 struct mrvl_shadow_txq *sq, int qid, int force); 147 148 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 149 uint16_t nb_pkts); 150 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 151 uint16_t nb_pkts); 152 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev); 153 static void mrvl_deinit_pp2(void); 154 static void mrvl_deinit_hifs(void); 155 156 static int 157 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 158 uint32_t index, uint32_t vmdq __rte_unused); 159 static int 160 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 161 static int 162 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 163 static int mrvl_promiscuous_enable(struct rte_eth_dev *dev); 164 static int mrvl_allmulticast_enable(struct rte_eth_dev *dev); 165 static int 166 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); 167 168 #define MRVL_XSTATS_TBL_ENTRY(name) { \ 169 #name, offsetof(struct pp2_ppio_statistics, name), \ 170 sizeof(((struct pp2_ppio_statistics *)0)->name) \ 171 } 172 173 /* Table with xstats data */ 174 static struct { 175 const char *name; 176 unsigned int offset; 177 unsigned int size; 178 } mrvl_xstats_tbl[] = { 179 MRVL_XSTATS_TBL_ENTRY(rx_bytes), 180 MRVL_XSTATS_TBL_ENTRY(rx_packets), 181 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets), 182 MRVL_XSTATS_TBL_ENTRY(rx_errors), 183 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped), 184 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped), 185 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped), 186 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped), 187 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped), 188 MRVL_XSTATS_TBL_ENTRY(tx_bytes), 189 MRVL_XSTATS_TBL_ENTRY(tx_packets), 190 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets), 191 MRVL_XSTATS_TBL_ENTRY(tx_errors) 192 }; 193 194 static inline int 195 mrvl_reserve_bit(int *bitmap, int max) 196 { 197 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); 198 199 if (n >= max) 200 return -1; 201 202 *bitmap |= 1 << n; 203 204 return n; 205 } 206 207 static int 208 mrvl_pp2_fixup_init(void) 209 { 210 struct pp2_bpool_params bpool_params; 211 char name[15]; 212 int err, i; 213 214 memset(dummy_pool, 0, sizeof(dummy_pool)); 215 for (i = 0; i < pp2_get_num_inst(); i++) { 216 dummy_pool_id[i] = mrvl_reserve_bit(&used_bpools[i], 217 PP2_BPOOL_NUM_POOLS); 218 if (dummy_pool_id[i] < 0) { 219 MRVL_LOG(ERR, "Can't find free pool\n"); 220 return -1; 221 } 222 223 memset(name, 0, sizeof(name)); 224 snprintf(name, sizeof(name), "pool-%d:%d", i, dummy_pool_id[i]); 225 memset(&bpool_params, 0, sizeof(bpool_params)); 226 bpool_params.match = name; 227 bpool_params.buff_len = MRVL_PKT_OFFS; 228 bpool_params.dummy_short_pool = 1; 229 err = pp2_bpool_init(&bpool_params, &dummy_pool[i]); 230 if (err != 0 || !dummy_pool[i]) { 231 MRVL_LOG(ERR, "BPool init failed!\n"); 232 used_bpools[i] &= ~(1 << dummy_pool_id[i]); 233 return -1; 234 } 235 } 236 237 return 0; 238 } 239 240 /** 241 * Initialize packet processor. 242 * 243 * @return 244 * 0 on success, negative error value otherwise. 245 */ 246 static int 247 mrvl_init_pp2(void) 248 { 249 struct pp2_init_params init_params; 250 int err; 251 252 memset(&init_params, 0, sizeof(init_params)); 253 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; 254 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; 255 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; 256 if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs) 257 memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs, 258 sizeof(struct pp2_parse_udfs)); 259 err = pp2_init(&init_params); 260 if (err != 0) { 261 MRVL_LOG(ERR, "PP2 init failed"); 262 return -1; 263 } 264 265 err = mrvl_pp2_fixup_init(); 266 if (err != 0) { 267 MRVL_LOG(ERR, "PP2 fixup init failed"); 268 return -1; 269 } 270 271 return 0; 272 } 273 274 static void 275 mrvl_pp2_fixup_deinit(void) 276 { 277 int i; 278 279 for (i = 0; i < PP2_NUM_PKT_PROC; i++) { 280 if (!dummy_pool[i]) 281 continue; 282 pp2_bpool_deinit(dummy_pool[i]); 283 used_bpools[i] &= ~(1 << dummy_pool_id[i]); 284 } 285 } 286 287 /** 288 * Deinitialize packet processor. 289 * 290 * @return 291 * 0 on success, negative error value otherwise. 292 */ 293 static void 294 mrvl_deinit_pp2(void) 295 { 296 mrvl_pp2_fixup_deinit(); 297 pp2_deinit(); 298 } 299 300 static inline void 301 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf) 302 { 303 sq->ent[sq->head].buff.cookie = (uint64_t)buf; 304 sq->ent[sq->head].buff.addr = buf ? 305 rte_mbuf_data_iova_default(buf) : 0; 306 307 sq->ent[sq->head].bpool = 308 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS || 309 buf->refcnt > 1)) ? NULL : 310 mrvl_port_to_bpool_lookup[buf->port]; 311 312 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; 313 sq->size++; 314 } 315 316 /** 317 * Deinitialize per-lcore MUSDK hardware interfaces (hifs). 318 */ 319 static void 320 mrvl_deinit_hifs(void) 321 { 322 int i; 323 324 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { 325 if (hifs[i]) 326 pp2_hif_deinit(hifs[i]); 327 } 328 used_hifs = MRVL_MUSDK_HIFS_RESERVED; 329 memset(hifs, 0, sizeof(hifs)); 330 } 331 332 static inline void 333 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf) 334 { 335 pp2_ppio_outq_desc_reset(desc); 336 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf)); 337 pp2_ppio_outq_desc_set_pkt_offset(desc, 0); 338 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf)); 339 } 340 341 static inline int 342 mrvl_get_bpool_size(int pp2_id, int pool_id) 343 { 344 int i; 345 int size = 0; 346 347 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) 348 size += mrvl_port_bpool_size[pp2_id][pool_id][i]; 349 350 return size; 351 } 352 353 static int 354 mrvl_init_hif(int core_id) 355 { 356 struct pp2_hif_params params; 357 char match[MRVL_MATCH_LEN]; 358 int ret; 359 360 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); 361 if (ret < 0) { 362 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 363 return ret; 364 } 365 366 snprintf(match, sizeof(match), "hif-%d", ret); 367 memset(¶ms, 0, sizeof(params)); 368 params.match = match; 369 params.out_size = MRVL_PP2_AGGR_TXQD_MAX; 370 ret = pp2_hif_init(¶ms, &hifs[core_id]); 371 if (ret) { 372 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id); 373 return ret; 374 } 375 376 return 0; 377 } 378 379 static inline struct pp2_hif* 380 mrvl_get_hif(struct mrvl_priv *priv, int core_id) 381 { 382 int ret; 383 384 if (likely(hifs[core_id] != NULL)) 385 return hifs[core_id]; 386 387 rte_spinlock_lock(&priv->lock); 388 389 ret = mrvl_init_hif(core_id); 390 if (ret < 0) { 391 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id); 392 goto out; 393 } 394 395 if (core_id < mrvl_lcore_first) 396 mrvl_lcore_first = core_id; 397 398 if (core_id > mrvl_lcore_last) 399 mrvl_lcore_last = core_id; 400 out: 401 rte_spinlock_unlock(&priv->lock); 402 403 return hifs[core_id]; 404 } 405 406 /** 407 * Set tx burst function according to offload flag 408 * 409 * @param dev 410 * Pointer to Ethernet device structure. 411 */ 412 static void 413 mrvl_set_tx_function(struct rte_eth_dev *dev) 414 { 415 struct mrvl_priv *priv = dev->data->dev_private; 416 417 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 418 if (priv->multiseg) { 419 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n"); 420 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst; 421 } else { 422 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n"); 423 dev->tx_pkt_burst = mrvl_tx_pkt_burst; 424 } 425 } 426 427 /** 428 * Configure rss based on dpdk rss configuration. 429 * 430 * @param priv 431 * Pointer to private structure. 432 * @param rss_conf 433 * Pointer to RSS configuration. 434 * 435 * @return 436 * 0 on success, negative error value otherwise. 437 */ 438 static int 439 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) 440 { 441 if (rss_conf->rss_key) 442 MRVL_LOG(WARNING, "Changing hash key is not supported"); 443 444 if (rss_conf->rss_hf == 0) { 445 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 446 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) { 447 priv->ppio_params.inqs_params.hash_type = 448 PP2_PPIO_HASH_T_2_TUPLE; 449 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { 450 priv->ppio_params.inqs_params.hash_type = 451 PP2_PPIO_HASH_T_5_TUPLE; 452 priv->rss_hf_tcp = 1; 453 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { 454 priv->ppio_params.inqs_params.hash_type = 455 PP2_PPIO_HASH_T_5_TUPLE; 456 priv->rss_hf_tcp = 0; 457 } else { 458 return -EINVAL; 459 } 460 461 return 0; 462 } 463 464 /** 465 * Ethernet device configuration. 466 * 467 * Prepare the driver for a given number of TX and RX queues and 468 * configure RSS. 469 * 470 * @param dev 471 * Pointer to Ethernet device structure. 472 * 473 * @return 474 * 0 on success, negative error value otherwise. 475 */ 476 static int 477 mrvl_dev_configure(struct rte_eth_dev *dev) 478 { 479 struct mrvl_priv *priv = dev->data->dev_private; 480 int ret; 481 482 if (priv->ppio) { 483 MRVL_LOG(INFO, "Device reconfiguration is not supported"); 484 return -EINVAL; 485 } 486 487 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE && 488 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { 489 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d", 490 dev->data->dev_conf.rxmode.mq_mode); 491 return -EINVAL; 492 } 493 494 if (dev->data->dev_conf.rxmode.split_hdr_size) { 495 MRVL_LOG(INFO, "Split headers not supported"); 496 return -EINVAL; 497 } 498 499 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 500 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - 501 MRVL_PP2_ETH_HDRS_LEN; 502 if (dev->data->mtu > priv->max_mtu) { 503 MRVL_LOG(ERR, "inherit MTU %u from max_rx_pkt_len %u is larger than max_mtu %u\n", 504 dev->data->mtu, 505 dev->data->dev_conf.rxmode.max_rx_pkt_len, 506 priv->max_mtu); 507 return -EINVAL; 508 } 509 } 510 511 if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 512 priv->multiseg = 1; 513 514 ret = mrvl_configure_rxqs(priv, dev->data->port_id, 515 dev->data->nb_rx_queues); 516 if (ret < 0) 517 return ret; 518 519 ret = mrvl_configure_txqs(priv, dev->data->port_id, 520 dev->data->nb_tx_queues); 521 if (ret < 0) 522 return ret; 523 524 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; 525 priv->ppio_params.maintain_stats = 1; 526 priv->nb_rx_queues = dev->data->nb_rx_queues; 527 528 ret = mrvl_tm_init(dev); 529 if (ret < 0) 530 return ret; 531 532 if (dev->data->nb_rx_queues == 1 && 533 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 534 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue"); 535 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; 536 537 return 0; 538 } 539 540 return mrvl_configure_rss(priv, 541 &dev->data->dev_conf.rx_adv_conf.rss_conf); 542 } 543 544 /** 545 * DPDK callback to change the MTU. 546 * 547 * Setting the MTU affects hardware MRU (packets larger than the MRU 548 * will be dropped). 549 * 550 * @param dev 551 * Pointer to Ethernet device structure. 552 * @param mtu 553 * New MTU. 554 * 555 * @return 556 * 0 on success, negative error value otherwise. 557 */ 558 static int 559 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 560 { 561 struct mrvl_priv *priv = dev->data->dev_private; 562 uint16_t mru; 563 uint16_t mbuf_data_size = 0; /* SW buffer size */ 564 int ret; 565 566 mru = MRVL_PP2_MTU_TO_MRU(mtu); 567 /* 568 * min_rx_buf_size is equal to mbuf data size 569 * if pmd didn't set it differently 570 */ 571 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 572 /* Prevent PMD from: 573 * - setting mru greater than the mbuf size resulting in 574 * hw and sw buffer size mismatch 575 * - setting mtu that requires the support of scattered packets 576 * when this feature has not been enabled/supported so far 577 * (TODO check scattered_rx flag here once scattered RX is supported). 578 */ 579 if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) { 580 mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS; 581 mtu = MRVL_PP2_MRU_TO_MTU(mru); 582 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted " 583 "by current mbuf size: %u. Set MTU to %u, MRU to %u", 584 mbuf_data_size, mtu, mru); 585 } 586 587 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) { 588 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru); 589 return -EINVAL; 590 } 591 592 dev->data->mtu = mtu; 593 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE; 594 595 if (!priv->ppio) 596 return 0; 597 598 ret = pp2_ppio_set_mru(priv->ppio, mru); 599 if (ret) { 600 MRVL_LOG(ERR, "Failed to change MRU"); 601 return ret; 602 } 603 604 ret = pp2_ppio_set_mtu(priv->ppio, mtu); 605 if (ret) { 606 MRVL_LOG(ERR, "Failed to change MTU"); 607 return ret; 608 } 609 610 return 0; 611 } 612 613 /** 614 * DPDK callback to bring the link up. 615 * 616 * @param dev 617 * Pointer to Ethernet device structure. 618 * 619 * @return 620 * 0 on success, negative error value otherwise. 621 */ 622 static int 623 mrvl_dev_set_link_up(struct rte_eth_dev *dev) 624 { 625 struct mrvl_priv *priv = dev->data->dev_private; 626 int ret; 627 628 if (!priv->ppio) { 629 dev->data->dev_link.link_status = ETH_LINK_UP; 630 return 0; 631 } 632 633 ret = pp2_ppio_enable(priv->ppio); 634 if (ret) 635 return ret; 636 637 /* 638 * mtu/mru can be updated if pp2_ppio_enable() was called at least once 639 * as pp2_ppio_enable() changes port->t_mode from default 0 to 640 * PP2_TRAFFIC_INGRESS_EGRESS. 641 * 642 * Set mtu to default DPDK value here. 643 */ 644 ret = mrvl_mtu_set(dev, dev->data->mtu); 645 if (ret) { 646 pp2_ppio_disable(priv->ppio); 647 return ret; 648 } 649 650 dev->data->dev_link.link_status = ETH_LINK_UP; 651 return 0; 652 } 653 654 /** 655 * DPDK callback to bring the link down. 656 * 657 * @param dev 658 * Pointer to Ethernet device structure. 659 * 660 * @return 661 * 0 on success, negative error value otherwise. 662 */ 663 static int 664 mrvl_dev_set_link_down(struct rte_eth_dev *dev) 665 { 666 struct mrvl_priv *priv = dev->data->dev_private; 667 int ret; 668 669 if (!priv->ppio) { 670 dev->data->dev_link.link_status = ETH_LINK_DOWN; 671 return 0; 672 } 673 ret = pp2_ppio_disable(priv->ppio); 674 if (ret) 675 return ret; 676 677 dev->data->dev_link.link_status = ETH_LINK_DOWN; 678 return 0; 679 } 680 681 /** 682 * DPDK callback to start tx queue. 683 * 684 * @param dev 685 * Pointer to Ethernet device structure. 686 * @param queue_id 687 * Transmit queue index. 688 * 689 * @return 690 * 0 on success, negative error value otherwise. 691 */ 692 static int 693 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id) 694 { 695 struct mrvl_priv *priv = dev->data->dev_private; 696 int ret; 697 698 if (!priv) 699 return -EPERM; 700 701 /* passing 1 enables given tx queue */ 702 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1); 703 if (ret) { 704 MRVL_LOG(ERR, "Failed to start txq %d", queue_id); 705 return ret; 706 } 707 708 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 709 710 return 0; 711 } 712 713 /** 714 * DPDK callback to stop tx queue. 715 * 716 * @param dev 717 * Pointer to Ethernet device structure. 718 * @param queue_id 719 * Transmit queue index. 720 * 721 * @return 722 * 0 on success, negative error value otherwise. 723 */ 724 static int 725 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id) 726 { 727 struct mrvl_priv *priv = dev->data->dev_private; 728 int ret; 729 730 if (!priv->ppio) 731 return -EPERM; 732 733 /* passing 0 disables given tx queue */ 734 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0); 735 if (ret) { 736 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id); 737 return ret; 738 } 739 740 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 741 742 return 0; 743 } 744 745 /** 746 * Populate VLAN Filter configuration. 747 * 748 * @param dev 749 * Pointer to Ethernet device structure. 750 * @param on 751 * Toggle filter. 752 * 753 * @return 754 * 0 on success, negative error value otherwise. 755 */ 756 static int mrvl_populate_vlan_table(struct rte_eth_dev *dev, int on) 757 { 758 uint32_t j; 759 int ret; 760 struct rte_vlan_filter_conf *vfc; 761 762 vfc = &dev->data->vlan_filter_conf; 763 for (j = 0; j < RTE_DIM(vfc->ids); j++) { 764 uint64_t vlan; 765 uint64_t vbit; 766 uint64_t ids = vfc->ids[j]; 767 768 if (ids == 0) 769 continue; 770 771 while (ids) { 772 vlan = 64 * j; 773 /* count trailing zeroes */ 774 vbit = ~ids & (ids - 1); 775 /* clear least significant bit set */ 776 ids ^= (ids ^ (ids - 1)) ^ vbit; 777 for (; vbit; vlan++) 778 vbit >>= 1; 779 ret = mrvl_vlan_filter_set(dev, vlan, on); 780 if (ret) { 781 MRVL_LOG(ERR, "Failed to setup VLAN filter\n"); 782 return ret; 783 } 784 } 785 } 786 787 return 0; 788 } 789 790 /** 791 * DPDK callback to start the device. 792 * 793 * @param dev 794 * Pointer to Ethernet device structure. 795 * 796 * @return 797 * 0 on success, negative errno value on failure. 798 */ 799 static int 800 mrvl_dev_start(struct rte_eth_dev *dev) 801 { 802 struct mrvl_priv *priv = dev->data->dev_private; 803 char match[MRVL_MATCH_LEN]; 804 int ret = 0, i, def_init_size; 805 struct rte_ether_addr *mac_addr; 806 807 if (priv->ppio) 808 return mrvl_dev_set_link_up(dev); 809 810 snprintf(match, sizeof(match), "ppio-%d:%d", 811 priv->pp_id, priv->ppio_id); 812 priv->ppio_params.match = match; 813 priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH; 814 priv->forward_bad_frames = 0; 815 priv->fill_bpool_buffs = MRVL_BURST_SIZE; 816 817 if (mrvl_cfg) { 818 priv->ppio_params.eth_start_hdr = 819 mrvl_cfg->port[dev->data->port_id].eth_start_hdr; 820 priv->forward_bad_frames = 821 mrvl_cfg->port[dev->data->port_id].forward_bad_frames; 822 priv->fill_bpool_buffs = 823 mrvl_cfg->port[dev->data->port_id].fill_bpool_buffs; 824 } 825 826 /* 827 * Calculate the minimum bpool size for refill feature as follows: 828 * 2 default burst sizes multiply by number of rx queues. 829 * If the bpool size will be below this value, new buffers will 830 * be added to the pool. 831 */ 832 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; 833 834 /* In case initial bpool size configured in queues setup is 835 * smaller than minimum size add more buffers 836 */ 837 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; 838 if (priv->bpool_init_size < def_init_size) { 839 int buffs_to_add = def_init_size - priv->bpool_init_size; 840 841 priv->bpool_init_size += buffs_to_add; 842 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); 843 if (ret) 844 MRVL_LOG(ERR, "Failed to add buffers to bpool"); 845 } 846 847 /* 848 * Calculate the maximum bpool size for refill feature as follows: 849 * maximum number of descriptors in rx queue multiply by number 850 * of rx queues plus minimum bpool size. 851 * In case the bpool size will exceed this value, superfluous buffers 852 * will be removed 853 */ 854 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + 855 priv->bpool_min_size; 856 857 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); 858 if (ret) { 859 MRVL_LOG(ERR, "Failed to init ppio"); 860 return ret; 861 } 862 863 /* 864 * In case there are some some stale uc/mc mac addresses flush them 865 * here. It cannot be done during mrvl_dev_close() as port information 866 * is already gone at that point (due to pp2_ppio_deinit() in 867 * mrvl_dev_stop()). 868 */ 869 if (!priv->uc_mc_flushed) { 870 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1); 871 if (ret) { 872 MRVL_LOG(ERR, 873 "Failed to flush uc/mc filter list"); 874 goto out; 875 } 876 priv->uc_mc_flushed = 1; 877 } 878 879 ret = mrvl_mtu_set(dev, dev->data->mtu); 880 if (ret) 881 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu); 882 883 if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0])) 884 mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]); 885 886 for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) { 887 mac_addr = &dev->data->mac_addrs[i]; 888 889 /* skip zero address */ 890 if (rte_is_zero_ether_addr(mac_addr)) 891 continue; 892 893 mrvl_mac_addr_add(dev, mac_addr, i, 0); 894 } 895 896 if (dev->data->all_multicast == 1) 897 mrvl_allmulticast_enable(dev); 898 899 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 900 ret = mrvl_populate_vlan_table(dev, 1); 901 if (ret) { 902 MRVL_LOG(ERR, "Failed to populate VLAN table"); 903 goto out; 904 } 905 } 906 907 /* For default QoS config, don't start classifier. */ 908 if (mrvl_cfg && 909 mrvl_cfg->port[dev->data->port_id].use_qos_global_defaults == 0) { 910 ret = mrvl_start_qos_mapping(priv); 911 if (ret) { 912 MRVL_LOG(ERR, "Failed to setup QoS mapping"); 913 goto out; 914 } 915 } 916 917 ret = pp2_ppio_set_loopback(priv->ppio, dev->data->dev_conf.lpbk_mode); 918 if (ret) { 919 MRVL_LOG(ERR, "Failed to set loopback"); 920 goto out; 921 } 922 923 if (dev->data->promiscuous == 1) 924 mrvl_promiscuous_enable(dev); 925 926 if (priv->flow_ctrl) { 927 ret = mrvl_flow_ctrl_set(dev, &priv->fc_conf); 928 if (ret) { 929 MRVL_LOG(ERR, "Failed to configure flow control"); 930 goto out; 931 } 932 priv->flow_ctrl = 0; 933 } 934 935 if (dev->data->dev_link.link_status == ETH_LINK_UP) { 936 ret = mrvl_dev_set_link_up(dev); 937 if (ret) { 938 MRVL_LOG(ERR, "Failed to set link up"); 939 dev->data->dev_link.link_status = ETH_LINK_DOWN; 940 goto out; 941 } 942 } 943 944 /* start tx queues */ 945 for (i = 0; i < dev->data->nb_tx_queues; i++) { 946 struct mrvl_txq *txq = dev->data->tx_queues[i]; 947 948 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 949 950 if (!txq->tx_deferred_start) 951 continue; 952 953 /* 954 * All txqs are started by default. Stop them 955 * so that tx_deferred_start works as expected. 956 */ 957 ret = mrvl_tx_queue_stop(dev, i); 958 if (ret) 959 goto out; 960 } 961 962 mrvl_flow_init(dev); 963 mrvl_mtr_init(dev); 964 mrvl_set_tx_function(dev); 965 966 return 0; 967 out: 968 MRVL_LOG(ERR, "Failed to start device"); 969 pp2_ppio_deinit(priv->ppio); 970 return ret; 971 } 972 973 /** 974 * Flush receive queues. 975 * 976 * @param dev 977 * Pointer to Ethernet device structure. 978 */ 979 static void 980 mrvl_flush_rx_queues(struct rte_eth_dev *dev) 981 { 982 int i; 983 984 MRVL_LOG(INFO, "Flushing rx queues"); 985 for (i = 0; i < dev->data->nb_rx_queues; i++) { 986 int ret, num; 987 988 do { 989 struct mrvl_rxq *q = dev->data->rx_queues[i]; 990 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX]; 991 992 num = MRVL_PP2_RXD_MAX; 993 ret = pp2_ppio_recv(q->priv->ppio, 994 q->priv->rxq_map[q->queue_id].tc, 995 q->priv->rxq_map[q->queue_id].inq, 996 descs, (uint16_t *)&num); 997 } while (ret == 0 && num); 998 } 999 } 1000 1001 /** 1002 * Flush transmit shadow queues. 1003 * 1004 * @param dev 1005 * Pointer to Ethernet device structure. 1006 */ 1007 static void 1008 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) 1009 { 1010 int i, j; 1011 struct mrvl_txq *txq; 1012 1013 MRVL_LOG(INFO, "Flushing tx shadow queues"); 1014 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1015 txq = (struct mrvl_txq *)dev->data->tx_queues[i]; 1016 1017 for (j = 0; j < RTE_MAX_LCORE; j++) { 1018 struct mrvl_shadow_txq *sq; 1019 1020 if (!hifs[j]) 1021 continue; 1022 1023 sq = &txq->shadow_txqs[j]; 1024 mrvl_free_sent_buffers(txq->priv->ppio, 1025 hifs[j], j, sq, txq->queue_id, 1); 1026 while (sq->tail != sq->head) { 1027 uint64_t addr = cookie_addr_high | 1028 sq->ent[sq->tail].buff.cookie; 1029 rte_pktmbuf_free( 1030 (struct rte_mbuf *)addr); 1031 sq->tail = (sq->tail + 1) & 1032 MRVL_PP2_TX_SHADOWQ_MASK; 1033 } 1034 memset(sq, 0, sizeof(*sq)); 1035 } 1036 } 1037 } 1038 1039 /** 1040 * Flush hardware bpool (buffer-pool). 1041 * 1042 * @param dev 1043 * Pointer to Ethernet device structure. 1044 */ 1045 static void 1046 mrvl_flush_bpool(struct rte_eth_dev *dev) 1047 { 1048 struct mrvl_priv *priv = dev->data->dev_private; 1049 struct pp2_hif *hif; 1050 uint32_t num; 1051 int ret; 1052 unsigned int core_id = rte_lcore_id(); 1053 1054 if (core_id == LCORE_ID_ANY) 1055 core_id = rte_get_main_lcore(); 1056 1057 hif = mrvl_get_hif(priv, core_id); 1058 1059 ret = pp2_bpool_get_num_buffs(priv->bpool, &num); 1060 if (ret) { 1061 MRVL_LOG(ERR, "Failed to get bpool buffers number"); 1062 return; 1063 } 1064 1065 while (num--) { 1066 struct pp2_buff_inf inf; 1067 uint64_t addr; 1068 1069 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); 1070 if (ret) 1071 break; 1072 1073 addr = cookie_addr_high | inf.cookie; 1074 rte_pktmbuf_free((struct rte_mbuf *)addr); 1075 } 1076 } 1077 1078 /** 1079 * DPDK callback to stop the device. 1080 * 1081 * @param dev 1082 * Pointer to Ethernet device structure. 1083 */ 1084 static int 1085 mrvl_dev_stop(struct rte_eth_dev *dev) 1086 { 1087 return mrvl_dev_set_link_down(dev); 1088 } 1089 1090 /** 1091 * DPDK callback to close the device. 1092 * 1093 * @param dev 1094 * Pointer to Ethernet device structure. 1095 */ 1096 static int 1097 mrvl_dev_close(struct rte_eth_dev *dev) 1098 { 1099 struct mrvl_priv *priv = dev->data->dev_private; 1100 size_t i; 1101 1102 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1103 return 0; 1104 1105 mrvl_flush_rx_queues(dev); 1106 mrvl_flush_tx_shadow_queues(dev); 1107 mrvl_flow_deinit(dev); 1108 mrvl_mtr_deinit(dev); 1109 1110 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) { 1111 struct pp2_ppio_tc_params *tc_params = 1112 &priv->ppio_params.inqs_params.tcs_params[i]; 1113 1114 if (tc_params->inqs_params) { 1115 rte_free(tc_params->inqs_params); 1116 tc_params->inqs_params = NULL; 1117 } 1118 } 1119 1120 if (priv->cls_tbl) { 1121 pp2_cls_tbl_deinit(priv->cls_tbl); 1122 priv->cls_tbl = NULL; 1123 } 1124 1125 if (priv->qos_tbl) { 1126 pp2_cls_qos_tbl_deinit(priv->qos_tbl); 1127 priv->qos_tbl = NULL; 1128 } 1129 1130 mrvl_flush_bpool(dev); 1131 mrvl_tm_deinit(dev); 1132 1133 if (priv->ppio) { 1134 pp2_ppio_deinit(priv->ppio); 1135 priv->ppio = NULL; 1136 } 1137 1138 /* policer must be released after ppio deinitialization */ 1139 if (priv->default_policer) { 1140 pp2_cls_plcr_deinit(priv->default_policer); 1141 priv->default_policer = NULL; 1142 } 1143 1144 1145 if (priv->bpool) { 1146 pp2_bpool_deinit(priv->bpool); 1147 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 1148 priv->bpool = NULL; 1149 } 1150 1151 mrvl_dev_num--; 1152 1153 if (mrvl_dev_num == 0) { 1154 MRVL_LOG(INFO, "Perform MUSDK deinit"); 1155 mrvl_deinit_hifs(); 1156 mrvl_deinit_pp2(); 1157 rte_mvep_deinit(MVEP_MOD_T_PP2); 1158 } 1159 1160 return 0; 1161 } 1162 1163 /** 1164 * DPDK callback to retrieve physical link information. 1165 * 1166 * @param dev 1167 * Pointer to Ethernet device structure. 1168 * @param wait_to_complete 1169 * Wait for request completion (ignored). 1170 * 1171 * @return 1172 * 0 on success, negative error value otherwise. 1173 */ 1174 static int 1175 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 1176 { 1177 /* 1178 * TODO 1179 * once MUSDK provides necessary API use it here 1180 */ 1181 struct mrvl_priv *priv = dev->data->dev_private; 1182 struct ethtool_cmd edata; 1183 struct ifreq req; 1184 int ret, fd, link_up; 1185 1186 if (!priv->ppio) 1187 return -EPERM; 1188 1189 edata.cmd = ETHTOOL_GSET; 1190 1191 strcpy(req.ifr_name, dev->data->name); 1192 req.ifr_data = (void *)&edata; 1193 1194 fd = socket(AF_INET, SOCK_DGRAM, 0); 1195 if (fd == -1) 1196 return -EFAULT; 1197 1198 ret = ioctl(fd, SIOCETHTOOL, &req); 1199 if (ret == -1) { 1200 close(fd); 1201 return -EFAULT; 1202 } 1203 1204 close(fd); 1205 1206 switch (ethtool_cmd_speed(&edata)) { 1207 case SPEED_10: 1208 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M; 1209 break; 1210 case SPEED_100: 1211 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M; 1212 break; 1213 case SPEED_1000: 1214 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G; 1215 break; 1216 case SPEED_2500: 1217 dev->data->dev_link.link_speed = ETH_SPEED_NUM_2_5G; 1218 break; 1219 case SPEED_10000: 1220 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G; 1221 break; 1222 default: 1223 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE; 1224 } 1225 1226 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX : 1227 ETH_LINK_HALF_DUPLEX; 1228 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG : 1229 ETH_LINK_FIXED; 1230 pp2_ppio_get_link_state(priv->ppio, &link_up); 1231 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 1232 1233 return 0; 1234 } 1235 1236 /** 1237 * DPDK callback to enable promiscuous mode. 1238 * 1239 * @param dev 1240 * Pointer to Ethernet device structure. 1241 * 1242 * @return 1243 * 0 on success, negative error value otherwise. 1244 */ 1245 static int 1246 mrvl_promiscuous_enable(struct rte_eth_dev *dev) 1247 { 1248 struct mrvl_priv *priv = dev->data->dev_private; 1249 int ret; 1250 1251 if (priv->isolated) 1252 return -ENOTSUP; 1253 1254 if (!priv->ppio) 1255 return 0; 1256 1257 ret = pp2_ppio_set_promisc(priv->ppio, 1); 1258 if (ret) { 1259 MRVL_LOG(ERR, "Failed to enable promiscuous mode"); 1260 return -EAGAIN; 1261 } 1262 1263 return 0; 1264 } 1265 1266 /** 1267 * DPDK callback to enable allmulti mode. 1268 * 1269 * @param dev 1270 * Pointer to Ethernet device structure. 1271 * 1272 * @return 1273 * 0 on success, negative error value otherwise. 1274 */ 1275 static int 1276 mrvl_allmulticast_enable(struct rte_eth_dev *dev) 1277 { 1278 struct mrvl_priv *priv = dev->data->dev_private; 1279 int ret; 1280 1281 if (priv->isolated) 1282 return -ENOTSUP; 1283 1284 if (!priv->ppio) 1285 return 0; 1286 1287 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); 1288 if (ret) { 1289 MRVL_LOG(ERR, "Failed enable all-multicast mode"); 1290 return -EAGAIN; 1291 } 1292 1293 return 0; 1294 } 1295 1296 /** 1297 * DPDK callback to disable promiscuous mode. 1298 * 1299 * @param dev 1300 * Pointer to Ethernet device structure. 1301 * 1302 * @return 1303 * 0 on success, negative error value otherwise. 1304 */ 1305 static int 1306 mrvl_promiscuous_disable(struct rte_eth_dev *dev) 1307 { 1308 struct mrvl_priv *priv = dev->data->dev_private; 1309 int ret; 1310 1311 if (priv->isolated) 1312 return -ENOTSUP; 1313 1314 if (!priv->ppio) 1315 return 0; 1316 1317 ret = pp2_ppio_set_promisc(priv->ppio, 0); 1318 if (ret) { 1319 MRVL_LOG(ERR, "Failed to disable promiscuous mode"); 1320 return -EAGAIN; 1321 } 1322 1323 return 0; 1324 } 1325 1326 /** 1327 * DPDK callback to disable allmulticast mode. 1328 * 1329 * @param dev 1330 * Pointer to Ethernet device structure. 1331 * 1332 * @return 1333 * 0 on success, negative error value otherwise. 1334 */ 1335 static int 1336 mrvl_allmulticast_disable(struct rte_eth_dev *dev) 1337 { 1338 struct mrvl_priv *priv = dev->data->dev_private; 1339 int ret; 1340 1341 if (priv->isolated) 1342 return -ENOTSUP; 1343 1344 if (!priv->ppio) 1345 return 0; 1346 1347 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); 1348 if (ret) { 1349 MRVL_LOG(ERR, "Failed to disable all-multicast mode"); 1350 return -EAGAIN; 1351 } 1352 1353 return 0; 1354 } 1355 1356 /** 1357 * DPDK callback to remove a MAC address. 1358 * 1359 * @param dev 1360 * Pointer to Ethernet device structure. 1361 * @param index 1362 * MAC address index. 1363 */ 1364 static void 1365 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 1366 { 1367 struct mrvl_priv *priv = dev->data->dev_private; 1368 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1369 int ret; 1370 1371 if (priv->isolated) 1372 return; 1373 1374 if (!priv->ppio) 1375 return; 1376 1377 ret = pp2_ppio_remove_mac_addr(priv->ppio, 1378 dev->data->mac_addrs[index].addr_bytes); 1379 if (ret) { 1380 rte_ether_format_addr(buf, sizeof(buf), 1381 &dev->data->mac_addrs[index]); 1382 MRVL_LOG(ERR, "Failed to remove mac %s", buf); 1383 } 1384 } 1385 1386 /** 1387 * DPDK callback to add a MAC address. 1388 * 1389 * @param dev 1390 * Pointer to Ethernet device structure. 1391 * @param mac_addr 1392 * MAC address to register. 1393 * @param index 1394 * MAC address index. 1395 * @param vmdq 1396 * VMDq pool index to associate address with (unused). 1397 * 1398 * @return 1399 * 0 on success, negative error value otherwise. 1400 */ 1401 static int 1402 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1403 uint32_t index, uint32_t vmdq __rte_unused) 1404 { 1405 struct mrvl_priv *priv = dev->data->dev_private; 1406 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1407 int ret; 1408 1409 if (priv->isolated) 1410 return -ENOTSUP; 1411 1412 if (!priv->ppio) 1413 return 0; 1414 1415 if (index == 0) 1416 /* For setting index 0, mrvl_mac_addr_set() should be used.*/ 1417 return -1; 1418 1419 /* 1420 * Maximum number of uc addresses can be tuned via kernel module mvpp2x 1421 * parameter uc_filter_max. Maximum number of mc addresses is then 1422 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and 1423 * 21 respectively. 1424 * 1425 * If more than uc_filter_max uc addresses were added to filter list 1426 * then NIC will switch to promiscuous mode automatically. 1427 * 1428 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses 1429 * were added to filter list then NIC will switch to all-multicast mode 1430 * automatically. 1431 */ 1432 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes); 1433 if (ret) { 1434 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1435 MRVL_LOG(ERR, "Failed to add mac %s", buf); 1436 return -1; 1437 } 1438 1439 return 0; 1440 } 1441 1442 /** 1443 * DPDK callback to set the primary MAC address. 1444 * 1445 * @param dev 1446 * Pointer to Ethernet device structure. 1447 * @param mac_addr 1448 * MAC address to register. 1449 * 1450 * @return 1451 * 0 on success, negative error value otherwise. 1452 */ 1453 static int 1454 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1455 { 1456 struct mrvl_priv *priv = dev->data->dev_private; 1457 int ret; 1458 1459 if (priv->isolated) 1460 return -ENOTSUP; 1461 1462 if (!priv->ppio) 1463 return 0; 1464 1465 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); 1466 if (ret) { 1467 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 1468 rte_ether_format_addr(buf, sizeof(buf), mac_addr); 1469 MRVL_LOG(ERR, "Failed to set mac to %s", buf); 1470 } 1471 1472 return ret; 1473 } 1474 1475 /** 1476 * DPDK callback to get device statistics. 1477 * 1478 * @param dev 1479 * Pointer to Ethernet device structure. 1480 * @param stats 1481 * Stats structure output buffer. 1482 * 1483 * @return 1484 * 0 on success, negative error value otherwise. 1485 */ 1486 static int 1487 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1488 { 1489 struct mrvl_priv *priv = dev->data->dev_private; 1490 struct pp2_ppio_statistics ppio_stats; 1491 uint64_t drop_mac = 0; 1492 unsigned int i, idx, ret; 1493 1494 if (!priv->ppio) 1495 return -EPERM; 1496 1497 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1498 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1499 struct pp2_ppio_inq_statistics rx_stats; 1500 1501 if (!rxq) 1502 continue; 1503 1504 idx = rxq->queue_id; 1505 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1506 MRVL_LOG(ERR, 1507 "rx queue %d stats out of range (0 - %d)", 1508 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1509 continue; 1510 } 1511 1512 ret = pp2_ppio_inq_get_statistics(priv->ppio, 1513 priv->rxq_map[idx].tc, 1514 priv->rxq_map[idx].inq, 1515 &rx_stats, 0); 1516 if (unlikely(ret)) { 1517 MRVL_LOG(ERR, 1518 "Failed to update rx queue %d stats", idx); 1519 break; 1520 } 1521 1522 stats->q_ibytes[idx] = rxq->bytes_recv; 1523 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac; 1524 stats->q_errors[idx] = rx_stats.drop_early + 1525 rx_stats.drop_fullq + 1526 rx_stats.drop_bm + 1527 rxq->drop_mac; 1528 stats->ibytes += rxq->bytes_recv; 1529 drop_mac += rxq->drop_mac; 1530 } 1531 1532 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1533 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1534 struct pp2_ppio_outq_statistics tx_stats; 1535 1536 if (!txq) 1537 continue; 1538 1539 idx = txq->queue_id; 1540 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { 1541 MRVL_LOG(ERR, 1542 "tx queue %d stats out of range (0 - %d)", 1543 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); 1544 } 1545 1546 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx, 1547 &tx_stats, 0); 1548 if (unlikely(ret)) { 1549 MRVL_LOG(ERR, 1550 "Failed to update tx queue %d stats", idx); 1551 break; 1552 } 1553 1554 stats->q_opackets[idx] = tx_stats.deq_desc; 1555 stats->q_obytes[idx] = txq->bytes_sent; 1556 stats->obytes += txq->bytes_sent; 1557 } 1558 1559 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1560 if (unlikely(ret)) { 1561 MRVL_LOG(ERR, "Failed to update port statistics"); 1562 return ret; 1563 } 1564 1565 stats->ipackets += ppio_stats.rx_packets - drop_mac; 1566 stats->opackets += ppio_stats.tx_packets; 1567 stats->imissed += ppio_stats.rx_fullq_dropped + 1568 ppio_stats.rx_bm_dropped + 1569 ppio_stats.rx_early_dropped + 1570 ppio_stats.rx_fifo_dropped + 1571 ppio_stats.rx_cls_dropped; 1572 stats->ierrors = drop_mac; 1573 1574 return 0; 1575 } 1576 1577 /** 1578 * DPDK callback to clear device statistics. 1579 * 1580 * @param dev 1581 * Pointer to Ethernet device structure. 1582 * 1583 * @return 1584 * 0 on success, negative error value otherwise. 1585 */ 1586 static int 1587 mrvl_stats_reset(struct rte_eth_dev *dev) 1588 { 1589 struct mrvl_priv *priv = dev->data->dev_private; 1590 int i; 1591 1592 if (!priv->ppio) 1593 return 0; 1594 1595 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1596 struct mrvl_rxq *rxq = dev->data->rx_queues[i]; 1597 1598 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc, 1599 priv->rxq_map[i].inq, NULL, 1); 1600 rxq->bytes_recv = 0; 1601 rxq->drop_mac = 0; 1602 } 1603 1604 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1605 struct mrvl_txq *txq = dev->data->tx_queues[i]; 1606 1607 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1); 1608 txq->bytes_sent = 0; 1609 } 1610 1611 return pp2_ppio_get_statistics(priv->ppio, NULL, 1); 1612 } 1613 1614 /** 1615 * DPDK callback to get extended statistics. 1616 * 1617 * @param dev 1618 * Pointer to Ethernet device structure. 1619 * @param stats 1620 * Pointer to xstats table. 1621 * @param n 1622 * Number of entries in xstats table. 1623 * @return 1624 * Negative value on error, number of read xstats otherwise. 1625 */ 1626 static int 1627 mrvl_xstats_get(struct rte_eth_dev *dev, 1628 struct rte_eth_xstat *stats, unsigned int n) 1629 { 1630 struct mrvl_priv *priv = dev->data->dev_private; 1631 struct pp2_ppio_statistics ppio_stats; 1632 unsigned int i; 1633 1634 if (!stats) 1635 return 0; 1636 1637 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); 1638 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) { 1639 uint64_t val; 1640 1641 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t)) 1642 val = *(uint32_t *)((uint8_t *)&ppio_stats + 1643 mrvl_xstats_tbl[i].offset); 1644 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t)) 1645 val = *(uint64_t *)((uint8_t *)&ppio_stats + 1646 mrvl_xstats_tbl[i].offset); 1647 else 1648 return -EINVAL; 1649 1650 stats[i].id = i; 1651 stats[i].value = val; 1652 } 1653 1654 return n; 1655 } 1656 1657 /** 1658 * DPDK callback to reset extended statistics. 1659 * 1660 * @param dev 1661 * Pointer to Ethernet device structure. 1662 * 1663 * @return 1664 * 0 on success, negative error value otherwise. 1665 */ 1666 static int 1667 mrvl_xstats_reset(struct rte_eth_dev *dev) 1668 { 1669 return mrvl_stats_reset(dev); 1670 } 1671 1672 /** 1673 * DPDK callback to get extended statistics names. 1674 * 1675 * @param dev (unused) 1676 * Pointer to Ethernet device structure. 1677 * @param xstats_names 1678 * Pointer to xstats names table. 1679 * @param size 1680 * Size of the xstats names table. 1681 * @return 1682 * Number of read names. 1683 */ 1684 static int 1685 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1686 struct rte_eth_xstat_name *xstats_names, 1687 unsigned int size) 1688 { 1689 unsigned int i; 1690 1691 if (!xstats_names) 1692 return RTE_DIM(mrvl_xstats_tbl); 1693 1694 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++) 1695 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name, 1696 RTE_ETH_XSTATS_NAME_SIZE); 1697 1698 return size; 1699 } 1700 1701 /** 1702 * DPDK callback to get information about the device. 1703 * 1704 * @param dev 1705 * Pointer to Ethernet device structure (unused). 1706 * @param info 1707 * Info structure output buffer. 1708 */ 1709 static int 1710 mrvl_dev_infos_get(struct rte_eth_dev *dev, 1711 struct rte_eth_dev_info *info) 1712 { 1713 struct mrvl_priv *priv = dev->data->dev_private; 1714 1715 info->speed_capa = ETH_LINK_SPEED_10M | 1716 ETH_LINK_SPEED_100M | 1717 ETH_LINK_SPEED_1G | 1718 ETH_LINK_SPEED_2_5G | 1719 ETH_LINK_SPEED_10G; 1720 1721 info->max_rx_queues = MRVL_PP2_RXQ_MAX; 1722 info->max_tx_queues = MRVL_PP2_TXQ_MAX; 1723 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX; 1724 1725 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX; 1726 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN; 1727 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN; 1728 1729 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX; 1730 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; 1731 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; 1732 1733 info->rx_offload_capa = MRVL_RX_OFFLOADS; 1734 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; 1735 1736 info->tx_offload_capa = MRVL_TX_OFFLOADS; 1737 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; 1738 1739 info->flow_type_rss_offloads = ETH_RSS_IPV4 | 1740 ETH_RSS_NONFRAG_IPV4_TCP | 1741 ETH_RSS_NONFRAG_IPV4_UDP; 1742 1743 /* By default packets are dropped if no descriptors are available */ 1744 info->default_rxconf.rx_drop_en = 1; 1745 1746 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; 1747 info->max_mtu = priv->max_mtu; 1748 1749 return 0; 1750 } 1751 1752 /** 1753 * Return supported packet types. 1754 * 1755 * @param dev 1756 * Pointer to Ethernet device structure (unused). 1757 * 1758 * @return 1759 * Const pointer to the table with supported packet types. 1760 */ 1761 static const uint32_t * 1762 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 1763 { 1764 static const uint32_t ptypes[] = { 1765 RTE_PTYPE_L2_ETHER, 1766 RTE_PTYPE_L2_ETHER_VLAN, 1767 RTE_PTYPE_L2_ETHER_QINQ, 1768 RTE_PTYPE_L3_IPV4, 1769 RTE_PTYPE_L3_IPV4_EXT, 1770 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1771 RTE_PTYPE_L3_IPV6, 1772 RTE_PTYPE_L3_IPV6_EXT, 1773 RTE_PTYPE_L2_ETHER_ARP, 1774 RTE_PTYPE_L4_TCP, 1775 RTE_PTYPE_L4_UDP 1776 }; 1777 1778 return ptypes; 1779 } 1780 1781 /** 1782 * DPDK callback to get information about specific receive queue. 1783 * 1784 * @param dev 1785 * Pointer to Ethernet device structure. 1786 * @param rx_queue_id 1787 * Receive queue index. 1788 * @param qinfo 1789 * Receive queue information structure. 1790 */ 1791 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 1792 struct rte_eth_rxq_info *qinfo) 1793 { 1794 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id]; 1795 struct mrvl_priv *priv = dev->data->dev_private; 1796 int inq = priv->rxq_map[rx_queue_id].inq; 1797 int tc = priv->rxq_map[rx_queue_id].tc; 1798 struct pp2_ppio_tc_params *tc_params = 1799 &priv->ppio_params.inqs_params.tcs_params[tc]; 1800 1801 qinfo->mp = q->mp; 1802 qinfo->nb_desc = tc_params->inqs_params[inq].size; 1803 } 1804 1805 /** 1806 * DPDK callback to get information about specific transmit queue. 1807 * 1808 * @param dev 1809 * Pointer to Ethernet device structure. 1810 * @param tx_queue_id 1811 * Transmit queue index. 1812 * @param qinfo 1813 * Transmit queue information structure. 1814 */ 1815 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, 1816 struct rte_eth_txq_info *qinfo) 1817 { 1818 struct mrvl_priv *priv = dev->data->dev_private; 1819 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id]; 1820 1821 qinfo->nb_desc = 1822 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size; 1823 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1824 } 1825 1826 /** 1827 * DPDK callback to Configure a VLAN filter. 1828 * 1829 * @param dev 1830 * Pointer to Ethernet device structure. 1831 * @param vlan_id 1832 * VLAN ID to filter. 1833 * @param on 1834 * Toggle filter. 1835 * 1836 * @return 1837 * 0 on success, negative error value otherwise. 1838 */ 1839 static int 1840 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1841 { 1842 struct mrvl_priv *priv = dev->data->dev_private; 1843 1844 if (priv->isolated) 1845 return -ENOTSUP; 1846 1847 if (!priv->ppio) 1848 return 0; 1849 1850 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : 1851 pp2_ppio_remove_vlan(priv->ppio, vlan_id); 1852 } 1853 1854 /** 1855 * DPDK callback to Configure VLAN offload. 1856 * 1857 * @param dev 1858 * Pointer to Ethernet device structure. 1859 * @param mask 1860 * VLAN offload mask. 1861 * 1862 * @return 1863 * 0 on success, negative error value otherwise. 1864 */ 1865 static int mrvl_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1866 { 1867 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1868 int ret; 1869 1870 if (mask & ETH_VLAN_STRIP_MASK) 1871 MRVL_LOG(ERR, "VLAN stripping is not supported\n"); 1872 1873 if (mask & ETH_VLAN_FILTER_MASK) { 1874 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1875 ret = mrvl_populate_vlan_table(dev, 1); 1876 else 1877 ret = mrvl_populate_vlan_table(dev, 0); 1878 1879 if (ret) 1880 return ret; 1881 } 1882 1883 if (mask & ETH_VLAN_EXTEND_MASK) 1884 MRVL_LOG(ERR, "Extend VLAN not supported\n"); 1885 1886 return 0; 1887 } 1888 1889 /** 1890 * Release buffers to hardware bpool (buffer-pool) 1891 * 1892 * @param rxq 1893 * Receive queue pointer. 1894 * @param num 1895 * Number of buffers to release to bpool. 1896 * 1897 * @return 1898 * 0 on success, negative error value otherwise. 1899 */ 1900 static int 1901 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) 1902 { 1903 struct buff_release_entry entries[num]; 1904 struct rte_mbuf *mbufs[num]; 1905 int i, ret; 1906 unsigned int core_id; 1907 struct pp2_hif *hif; 1908 struct pp2_bpool *bpool; 1909 1910 core_id = rte_lcore_id(); 1911 if (core_id == LCORE_ID_ANY) 1912 core_id = rte_get_main_lcore(); 1913 1914 hif = mrvl_get_hif(rxq->priv, core_id); 1915 if (!hif) 1916 return -1; 1917 1918 bpool = rxq->priv->bpool; 1919 1920 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); 1921 if (ret) 1922 return ret; 1923 1924 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID) 1925 cookie_addr_high = 1926 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK; 1927 1928 for (i = 0; i < num; i++) { 1929 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK) 1930 != cookie_addr_high) { 1931 MRVL_LOG(ERR, 1932 "mbuf virtual addr high is out of range " 1933 "0x%x instead of 0x%x\n", 1934 (uint32_t)((uint64_t)mbufs[i] >> 32), 1935 (uint32_t)(cookie_addr_high >> 32)); 1936 goto out; 1937 } 1938 1939 entries[i].buff.addr = 1940 rte_mbuf_data_iova_default(mbufs[i]); 1941 entries[i].buff.cookie = (uintptr_t)mbufs[i]; 1942 entries[i].bpool = bpool; 1943 } 1944 1945 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i); 1946 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i; 1947 1948 if (i != num) 1949 goto out; 1950 1951 return 0; 1952 out: 1953 for (; i < num; i++) 1954 rte_pktmbuf_free(mbufs[i]); 1955 1956 return -1; 1957 } 1958 1959 /** 1960 * DPDK callback to configure the receive queue. 1961 * 1962 * @param dev 1963 * Pointer to Ethernet device structure. 1964 * @param idx 1965 * RX queue index. 1966 * @param desc 1967 * Number of descriptors to configure in queue. 1968 * @param socket 1969 * NUMA socket on which memory must be allocated. 1970 * @param conf 1971 * Thresholds parameters. 1972 * @param mp 1973 * Memory pool for buffer allocations. 1974 * 1975 * @return 1976 * 0 on success, negative error value otherwise. 1977 */ 1978 static int 1979 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 1980 unsigned int socket, 1981 const struct rte_eth_rxconf *conf, 1982 struct rte_mempool *mp) 1983 { 1984 struct mrvl_priv *priv = dev->data->dev_private; 1985 struct mrvl_rxq *rxq; 1986 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp); 1987 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 1988 int ret, tc, inq; 1989 uint64_t offloads; 1990 1991 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads; 1992 1993 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { 1994 /* 1995 * Unknown TC mapping, mapping will not have a correct queue. 1996 */ 1997 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu", 1998 idx, priv->ppio_id); 1999 return -EFAULT; 2000 } 2001 2002 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - 2003 MRVL_PKT_EFFEC_OFFS + RTE_ETHER_CRC_LEN; 2004 if (frame_size < max_rx_pkt_len) { 2005 MRVL_LOG(WARNING, 2006 "Mbuf size must be increased to %u bytes to hold up " 2007 "to %u bytes of data.", 2008 buf_size + max_rx_pkt_len - frame_size, 2009 max_rx_pkt_len); 2010 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2011 MRVL_LOG(INFO, "Setting max rx pkt len to %u", 2012 dev->data->dev_conf.rxmode.max_rx_pkt_len); 2013 } 2014 2015 if (dev->data->rx_queues[idx]) { 2016 rte_free(dev->data->rx_queues[idx]); 2017 dev->data->rx_queues[idx] = NULL; 2018 } 2019 2020 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket); 2021 if (!rxq) 2022 return -ENOMEM; 2023 2024 rxq->priv = priv; 2025 rxq->mp = mp; 2026 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM; 2027 rxq->queue_id = idx; 2028 rxq->port_id = dev->data->port_id; 2029 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; 2030 2031 tc = priv->rxq_map[rxq->queue_id].tc, 2032 inq = priv->rxq_map[rxq->queue_id].inq; 2033 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size = 2034 desc; 2035 2036 ret = mrvl_fill_bpool(rxq, desc); 2037 if (ret) { 2038 rte_free(rxq); 2039 return ret; 2040 } 2041 2042 priv->bpool_init_size += desc; 2043 2044 dev->data->rx_queues[idx] = rxq; 2045 2046 return 0; 2047 } 2048 2049 /** 2050 * DPDK callback to release the receive queue. 2051 * 2052 * @param rxq 2053 * Generic receive queue pointer. 2054 */ 2055 static void 2056 mrvl_rx_queue_release(void *rxq) 2057 { 2058 struct mrvl_rxq *q = rxq; 2059 struct pp2_ppio_tc_params *tc_params; 2060 int i, num, tc, inq; 2061 struct pp2_hif *hif; 2062 unsigned int core_id = rte_lcore_id(); 2063 2064 if (core_id == LCORE_ID_ANY) 2065 core_id = rte_get_main_lcore(); 2066 2067 if (!q) 2068 return; 2069 2070 hif = mrvl_get_hif(q->priv, core_id); 2071 2072 if (!hif) 2073 return; 2074 2075 tc = q->priv->rxq_map[q->queue_id].tc; 2076 inq = q->priv->rxq_map[q->queue_id].inq; 2077 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc]; 2078 num = tc_params->inqs_params[inq].size; 2079 for (i = 0; i < num; i++) { 2080 struct pp2_buff_inf inf; 2081 uint64_t addr; 2082 2083 pp2_bpool_get_buff(hif, q->priv->bpool, &inf); 2084 addr = cookie_addr_high | inf.cookie; 2085 rte_pktmbuf_free((struct rte_mbuf *)addr); 2086 } 2087 2088 rte_free(q); 2089 } 2090 2091 /** 2092 * DPDK callback to configure the transmit queue. 2093 * 2094 * @param dev 2095 * Pointer to Ethernet device structure. 2096 * @param idx 2097 * Transmit queue index. 2098 * @param desc 2099 * Number of descriptors to configure in the queue. 2100 * @param socket 2101 * NUMA socket on which memory must be allocated. 2102 * @param conf 2103 * Tx queue configuration parameters. 2104 * 2105 * @return 2106 * 0 on success, negative error value otherwise. 2107 */ 2108 static int 2109 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 2110 unsigned int socket, 2111 const struct rte_eth_txconf *conf) 2112 { 2113 struct mrvl_priv *priv = dev->data->dev_private; 2114 struct mrvl_txq *txq; 2115 2116 if (dev->data->tx_queues[idx]) { 2117 rte_free(dev->data->tx_queues[idx]); 2118 dev->data->tx_queues[idx] = NULL; 2119 } 2120 2121 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket); 2122 if (!txq) 2123 return -ENOMEM; 2124 2125 txq->priv = priv; 2126 txq->queue_id = idx; 2127 txq->port_id = dev->data->port_id; 2128 txq->tx_deferred_start = conf->tx_deferred_start; 2129 dev->data->tx_queues[idx] = txq; 2130 2131 priv->ppio_params.outqs_params.outqs_params[idx].size = desc; 2132 2133 return 0; 2134 } 2135 2136 /** 2137 * DPDK callback to release the transmit queue. 2138 * 2139 * @param txq 2140 * Generic transmit queue pointer. 2141 */ 2142 static void 2143 mrvl_tx_queue_release(void *txq) 2144 { 2145 struct mrvl_txq *q = txq; 2146 2147 if (!q) 2148 return; 2149 2150 rte_free(q); 2151 } 2152 2153 /** 2154 * DPDK callback to get flow control configuration. 2155 * 2156 * @param dev 2157 * Pointer to Ethernet device structure. 2158 * @param fc_conf 2159 * Pointer to the flow control configuration. 2160 * 2161 * @return 2162 * 0 on success, negative error value otherwise. 2163 */ 2164 static int 2165 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2166 { 2167 struct mrvl_priv *priv = dev->data->dev_private; 2168 int ret, en; 2169 2170 if (!priv->ppio) { 2171 memcpy(fc_conf, &priv->fc_conf, sizeof(struct rte_eth_fc_conf)); 2172 return 0; 2173 } 2174 2175 fc_conf->autoneg = 1; 2176 ret = pp2_ppio_get_rx_pause(priv->ppio, &en); 2177 if (ret) { 2178 MRVL_LOG(ERR, "Failed to read rx pause state"); 2179 return ret; 2180 } 2181 2182 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE; 2183 2184 ret = pp2_ppio_get_tx_pause(priv->ppio, &en); 2185 if (ret) { 2186 MRVL_LOG(ERR, "Failed to read tx pause state"); 2187 return ret; 2188 } 2189 2190 if (en) { 2191 if (fc_conf->mode == RTE_FC_NONE) 2192 fc_conf->mode = RTE_FC_TX_PAUSE; 2193 else 2194 fc_conf->mode = RTE_FC_FULL; 2195 } 2196 2197 return 0; 2198 } 2199 2200 /** 2201 * DPDK callback to set flow control configuration. 2202 * 2203 * @param dev 2204 * Pointer to Ethernet device structure. 2205 * @param fc_conf 2206 * Pointer to the flow control configuration. 2207 * 2208 * @return 2209 * 0 on success, negative error value otherwise. 2210 */ 2211 static int 2212 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2213 { 2214 struct mrvl_priv *priv = dev->data->dev_private; 2215 struct pp2_ppio_tx_pause_params mrvl_pause_params; 2216 int ret; 2217 int rx_en, tx_en; 2218 2219 if (fc_conf->high_water || 2220 fc_conf->low_water || 2221 fc_conf->pause_time || 2222 fc_conf->mac_ctrl_frame_fwd) { 2223 MRVL_LOG(ERR, "Flowctrl parameter is not supported"); 2224 2225 return -EINVAL; 2226 } 2227 2228 if (fc_conf->autoneg == 0) { 2229 MRVL_LOG(ERR, "Flowctrl Autoneg disable is not supported"); 2230 return -EINVAL; 2231 } 2232 2233 if (!priv->ppio) { 2234 memcpy(&priv->fc_conf, fc_conf, sizeof(struct rte_eth_fc_conf)); 2235 priv->flow_ctrl = 1; 2236 return 0; 2237 } 2238 2239 switch (fc_conf->mode) { 2240 case RTE_FC_FULL: 2241 rx_en = 1; 2242 tx_en = 1; 2243 break; 2244 case RTE_FC_TX_PAUSE: 2245 rx_en = 0; 2246 tx_en = 1; 2247 break; 2248 case RTE_FC_RX_PAUSE: 2249 rx_en = 1; 2250 tx_en = 0; 2251 break; 2252 case RTE_FC_NONE: 2253 rx_en = 0; 2254 tx_en = 0; 2255 break; 2256 default: 2257 MRVL_LOG(ERR, "Incorrect Flow control flag (%d)", 2258 fc_conf->mode); 2259 return -EINVAL; 2260 } 2261 2262 /* Set RX flow control */ 2263 ret = pp2_ppio_set_rx_pause(priv->ppio, rx_en); 2264 if (ret) { 2265 MRVL_LOG(ERR, "Failed to change RX flowctrl"); 2266 return ret; 2267 } 2268 2269 /* Set TX flow control */ 2270 mrvl_pause_params.en = tx_en; 2271 /* all inqs participate in xon/xoff decision */ 2272 mrvl_pause_params.use_tc_pause_inqs = 0; 2273 ret = pp2_ppio_set_tx_pause(priv->ppio, &mrvl_pause_params); 2274 if (ret) { 2275 MRVL_LOG(ERR, "Failed to change TX flowctrl"); 2276 return ret; 2277 } 2278 2279 return 0; 2280 } 2281 2282 /** 2283 * Update RSS hash configuration 2284 * 2285 * @param dev 2286 * Pointer to Ethernet device structure. 2287 * @param rss_conf 2288 * Pointer to RSS configuration. 2289 * 2290 * @return 2291 * 0 on success, negative error value otherwise. 2292 */ 2293 static int 2294 mrvl_rss_hash_update(struct rte_eth_dev *dev, 2295 struct rte_eth_rss_conf *rss_conf) 2296 { 2297 struct mrvl_priv *priv = dev->data->dev_private; 2298 2299 if (priv->isolated) 2300 return -ENOTSUP; 2301 2302 return mrvl_configure_rss(priv, rss_conf); 2303 } 2304 2305 /** 2306 * DPDK callback to get RSS hash configuration. 2307 * 2308 * @param dev 2309 * Pointer to Ethernet device structure. 2310 * @rss_conf 2311 * Pointer to RSS configuration. 2312 * 2313 * @return 2314 * Always 0. 2315 */ 2316 static int 2317 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, 2318 struct rte_eth_rss_conf *rss_conf) 2319 { 2320 struct mrvl_priv *priv = dev->data->dev_private; 2321 enum pp2_ppio_hash_type hash_type = 2322 priv->ppio_params.inqs_params.hash_type; 2323 2324 rss_conf->rss_key = NULL; 2325 2326 if (hash_type == PP2_PPIO_HASH_T_NONE) 2327 rss_conf->rss_hf = 0; 2328 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) 2329 rss_conf->rss_hf = ETH_RSS_IPV4; 2330 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) 2331 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP; 2332 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) 2333 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP; 2334 2335 return 0; 2336 } 2337 2338 /** 2339 * DPDK callback to get rte_flow callbacks. 2340 * 2341 * @param dev 2342 * Pointer to the device structure. 2343 * @param filer_type 2344 * Flow filter type. 2345 * @param filter_op 2346 * Flow filter operation. 2347 * @param arg 2348 * Pointer to pass the flow ops. 2349 * 2350 * @return 2351 * 0 on success, negative error value otherwise. 2352 */ 2353 static int 2354 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused, 2355 enum rte_filter_type filter_type, 2356 enum rte_filter_op filter_op, void *arg) 2357 { 2358 switch (filter_type) { 2359 case RTE_ETH_FILTER_GENERIC: 2360 if (filter_op != RTE_ETH_FILTER_GET) 2361 return -EINVAL; 2362 *(const void **)arg = &mrvl_flow_ops; 2363 return 0; 2364 default: 2365 MRVL_LOG(WARNING, "Filter type (%d) not supported", 2366 filter_type); 2367 return -EINVAL; 2368 } 2369 } 2370 2371 /** 2372 * DPDK callback to get rte_mtr callbacks. 2373 * 2374 * @param dev 2375 * Pointer to the device structure. 2376 * @param ops 2377 * Pointer to pass the mtr ops. 2378 * 2379 * @return 2380 * Always 0. 2381 */ 2382 static int 2383 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2384 { 2385 *(const void **)ops = &mrvl_mtr_ops; 2386 2387 return 0; 2388 } 2389 2390 /** 2391 * DPDK callback to get rte_tm callbacks. 2392 * 2393 * @param dev 2394 * Pointer to the device structure. 2395 * @param ops 2396 * Pointer to pass the tm ops. 2397 * 2398 * @return 2399 * Always 0. 2400 */ 2401 static int 2402 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2403 { 2404 *(const void **)ops = &mrvl_tm_ops; 2405 2406 return 0; 2407 } 2408 2409 static const struct eth_dev_ops mrvl_ops = { 2410 .dev_configure = mrvl_dev_configure, 2411 .dev_start = mrvl_dev_start, 2412 .dev_stop = mrvl_dev_stop, 2413 .dev_set_link_up = mrvl_dev_set_link_up, 2414 .dev_set_link_down = mrvl_dev_set_link_down, 2415 .dev_close = mrvl_dev_close, 2416 .link_update = mrvl_link_update, 2417 .promiscuous_enable = mrvl_promiscuous_enable, 2418 .allmulticast_enable = mrvl_allmulticast_enable, 2419 .promiscuous_disable = mrvl_promiscuous_disable, 2420 .allmulticast_disable = mrvl_allmulticast_disable, 2421 .mac_addr_remove = mrvl_mac_addr_remove, 2422 .mac_addr_add = mrvl_mac_addr_add, 2423 .mac_addr_set = mrvl_mac_addr_set, 2424 .mtu_set = mrvl_mtu_set, 2425 .stats_get = mrvl_stats_get, 2426 .stats_reset = mrvl_stats_reset, 2427 .xstats_get = mrvl_xstats_get, 2428 .xstats_reset = mrvl_xstats_reset, 2429 .xstats_get_names = mrvl_xstats_get_names, 2430 .dev_infos_get = mrvl_dev_infos_get, 2431 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get, 2432 .rxq_info_get = mrvl_rxq_info_get, 2433 .txq_info_get = mrvl_txq_info_get, 2434 .vlan_filter_set = mrvl_vlan_filter_set, 2435 .vlan_offload_set = mrvl_vlan_offload_set, 2436 .tx_queue_start = mrvl_tx_queue_start, 2437 .tx_queue_stop = mrvl_tx_queue_stop, 2438 .rx_queue_setup = mrvl_rx_queue_setup, 2439 .rx_queue_release = mrvl_rx_queue_release, 2440 .tx_queue_setup = mrvl_tx_queue_setup, 2441 .tx_queue_release = mrvl_tx_queue_release, 2442 .flow_ctrl_get = mrvl_flow_ctrl_get, 2443 .flow_ctrl_set = mrvl_flow_ctrl_set, 2444 .rss_hash_update = mrvl_rss_hash_update, 2445 .rss_hash_conf_get = mrvl_rss_hash_conf_get, 2446 .filter_ctrl = mrvl_eth_filter_ctrl, 2447 .mtr_ops_get = mrvl_mtr_ops_get, 2448 .tm_ops_get = mrvl_tm_ops_get, 2449 }; 2450 2451 /** 2452 * Return packet type information and l3/l4 offsets. 2453 * 2454 * @param desc 2455 * Pointer to the received packet descriptor. 2456 * @param l3_offset 2457 * l3 packet offset. 2458 * @param l4_offset 2459 * l4 packet offset. 2460 * 2461 * @return 2462 * Packet type information. 2463 */ 2464 static inline uint64_t 2465 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, 2466 uint8_t *l3_offset, uint8_t *l4_offset) 2467 { 2468 enum pp2_inq_l3_type l3_type; 2469 enum pp2_inq_l4_type l4_type; 2470 enum pp2_inq_vlan_tag vlan_tag; 2471 uint64_t packet_type; 2472 2473 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); 2474 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); 2475 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag); 2476 2477 packet_type = RTE_PTYPE_L2_ETHER; 2478 2479 switch (vlan_tag) { 2480 case PP2_INQ_VLAN_TAG_SINGLE: 2481 packet_type |= RTE_PTYPE_L2_ETHER_VLAN; 2482 break; 2483 case PP2_INQ_VLAN_TAG_DOUBLE: 2484 case PP2_INQ_VLAN_TAG_TRIPLE: 2485 packet_type |= RTE_PTYPE_L2_ETHER_QINQ; 2486 break; 2487 default: 2488 break; 2489 } 2490 2491 switch (l3_type) { 2492 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: 2493 packet_type |= RTE_PTYPE_L3_IPV4; 2494 break; 2495 case PP2_INQ_L3_TYPE_IPV4_OK: 2496 packet_type |= RTE_PTYPE_L3_IPV4_EXT; 2497 break; 2498 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO: 2499 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 2500 break; 2501 case PP2_INQ_L3_TYPE_IPV6_NO_EXT: 2502 packet_type |= RTE_PTYPE_L3_IPV6; 2503 break; 2504 case PP2_INQ_L3_TYPE_IPV6_EXT: 2505 packet_type |= RTE_PTYPE_L3_IPV6_EXT; 2506 break; 2507 case PP2_INQ_L3_TYPE_ARP: 2508 packet_type |= RTE_PTYPE_L2_ETHER_ARP; 2509 /* 2510 * In case of ARP l4_offset is set to wrong value. 2511 * Set it to proper one so that later on mbuf->l3_len can be 2512 * calculated subtracting l4_offset and l3_offset. 2513 */ 2514 *l4_offset = *l3_offset + MRVL_ARP_LENGTH; 2515 break; 2516 default: 2517 break; 2518 } 2519 2520 switch (l4_type) { 2521 case PP2_INQ_L4_TYPE_TCP: 2522 packet_type |= RTE_PTYPE_L4_TCP; 2523 break; 2524 case PP2_INQ_L4_TYPE_UDP: 2525 packet_type |= RTE_PTYPE_L4_UDP; 2526 break; 2527 default: 2528 break; 2529 } 2530 2531 return packet_type; 2532 } 2533 2534 /** 2535 * Get offload information from the received packet descriptor. 2536 * 2537 * @param desc 2538 * Pointer to the received packet descriptor. 2539 * 2540 * @return 2541 * Mbuf offload flags. 2542 */ 2543 static inline uint64_t 2544 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc, uint64_t packet_type) 2545 { 2546 uint64_t flags = 0; 2547 enum pp2_inq_desc_status status; 2548 2549 if (RTE_ETH_IS_IPV4_HDR(packet_type)) { 2550 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); 2551 if (unlikely(status != PP2_DESC_ERR_OK)) 2552 flags |= PKT_RX_IP_CKSUM_BAD; 2553 else 2554 flags |= PKT_RX_IP_CKSUM_GOOD; 2555 } 2556 2557 if (((packet_type & RTE_PTYPE_L4_UDP) == RTE_PTYPE_L4_UDP) || 2558 ((packet_type & RTE_PTYPE_L4_TCP) == RTE_PTYPE_L4_TCP)) { 2559 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); 2560 if (unlikely(status != PP2_DESC_ERR_OK)) 2561 flags |= PKT_RX_L4_CKSUM_BAD; 2562 else 2563 flags |= PKT_RX_L4_CKSUM_GOOD; 2564 } 2565 2566 return flags; 2567 } 2568 2569 /** 2570 * DPDK callback for receive. 2571 * 2572 * @param rxq 2573 * Generic pointer to the receive queue. 2574 * @param rx_pkts 2575 * Array to store received packets. 2576 * @param nb_pkts 2577 * Maximum number of packets in array. 2578 * 2579 * @return 2580 * Number of packets successfully received. 2581 */ 2582 static uint16_t 2583 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 2584 { 2585 struct mrvl_rxq *q = rxq; 2586 struct pp2_ppio_desc descs[nb_pkts]; 2587 struct pp2_bpool *bpool; 2588 int i, ret, rx_done = 0; 2589 int num; 2590 struct pp2_hif *hif; 2591 unsigned int core_id = rte_lcore_id(); 2592 2593 hif = mrvl_get_hif(q->priv, core_id); 2594 2595 if (unlikely(!q->priv->ppio || !hif)) 2596 return 0; 2597 2598 bpool = q->priv->bpool; 2599 2600 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc, 2601 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts); 2602 if (unlikely(ret < 0)) 2603 return 0; 2604 2605 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts; 2606 2607 for (i = 0; i < nb_pkts; i++) { 2608 struct rte_mbuf *mbuf; 2609 uint8_t l3_offset, l4_offset; 2610 enum pp2_inq_desc_status status; 2611 uint64_t addr; 2612 2613 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2614 struct pp2_ppio_desc *pref_desc; 2615 u64 pref_addr; 2616 2617 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2618 pref_addr = cookie_addr_high | 2619 pp2_ppio_inq_desc_get_cookie(pref_desc); 2620 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr)); 2621 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr)); 2622 } 2623 2624 addr = cookie_addr_high | 2625 pp2_ppio_inq_desc_get_cookie(&descs[i]); 2626 mbuf = (struct rte_mbuf *)addr; 2627 rte_pktmbuf_reset(mbuf); 2628 2629 /* drop packet in case of mac, overrun or resource error */ 2630 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); 2631 if ((unlikely(status != PP2_DESC_ERR_OK)) && 2632 !(q->priv->forward_bad_frames)) { 2633 struct pp2_buff_inf binf = { 2634 .addr = rte_mbuf_data_iova_default(mbuf), 2635 .cookie = (uint64_t)mbuf, 2636 }; 2637 2638 pp2_bpool_put_buff(hif, bpool, &binf); 2639 mrvl_port_bpool_size 2640 [bpool->pp2_id][bpool->id][core_id]++; 2641 q->drop_mac++; 2642 continue; 2643 } 2644 2645 mbuf->data_off += MRVL_PKT_EFFEC_OFFS; 2646 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]); 2647 mbuf->data_len = mbuf->pkt_len; 2648 mbuf->port = q->port_id; 2649 mbuf->packet_type = 2650 mrvl_desc_to_packet_type_and_offset(&descs[i], 2651 &l3_offset, 2652 &l4_offset); 2653 mbuf->l2_len = l3_offset; 2654 mbuf->l3_len = l4_offset - l3_offset; 2655 2656 if (likely(q->cksum_enabled)) 2657 mbuf->ol_flags = 2658 mrvl_desc_to_ol_flags(&descs[i], 2659 mbuf->packet_type); 2660 2661 rx_pkts[rx_done++] = mbuf; 2662 q->bytes_recv += mbuf->pkt_len; 2663 } 2664 2665 if (rte_spinlock_trylock(&q->priv->lock) == 1) { 2666 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id); 2667 2668 if (unlikely(num <= q->priv->bpool_min_size || 2669 (!rx_done && num < q->priv->bpool_init_size))) { 2670 mrvl_fill_bpool(q, q->priv->fill_bpool_buffs); 2671 } else if (unlikely(num > q->priv->bpool_max_size)) { 2672 int i; 2673 int pkt_to_remove = num - q->priv->bpool_init_size; 2674 struct rte_mbuf *mbuf; 2675 struct pp2_buff_inf buff; 2676 2677 for (i = 0; i < pkt_to_remove; i++) { 2678 ret = pp2_bpool_get_buff(hif, bpool, &buff); 2679 if (ret) 2680 break; 2681 mbuf = (struct rte_mbuf *) 2682 (cookie_addr_high | buff.cookie); 2683 rte_pktmbuf_free(mbuf); 2684 } 2685 mrvl_port_bpool_size 2686 [bpool->pp2_id][bpool->id][core_id] -= i; 2687 } 2688 rte_spinlock_unlock(&q->priv->lock); 2689 } 2690 2691 return rx_done; 2692 } 2693 2694 /** 2695 * Prepare offload information. 2696 * 2697 * @param ol_flags 2698 * Offload flags. 2699 * @param l3_type 2700 * Pointer to the pp2_ouq_l3_type structure. 2701 * @param l4_type 2702 * Pointer to the pp2_outq_l4_type structure. 2703 * @param gen_l3_cksum 2704 * Will be set to 1 in case l3 checksum is computed. 2705 * @param l4_cksum 2706 * Will be set to 1 in case l4 checksum is computed. 2707 */ 2708 static inline void 2709 mrvl_prepare_proto_info(uint64_t ol_flags, 2710 enum pp2_outq_l3_type *l3_type, 2711 enum pp2_outq_l4_type *l4_type, 2712 int *gen_l3_cksum, 2713 int *gen_l4_cksum) 2714 { 2715 /* 2716 * Based on ol_flags prepare information 2717 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor 2718 * for offloading. 2719 * in most of the checksum cases ipv4 must be set, so this is the 2720 * default value 2721 */ 2722 *l3_type = PP2_OUTQ_L3_TYPE_IPV4; 2723 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0; 2724 2725 if (ol_flags & PKT_TX_IPV6) { 2726 *l3_type = PP2_OUTQ_L3_TYPE_IPV6; 2727 /* no checksum for ipv6 header */ 2728 *gen_l3_cksum = 0; 2729 } 2730 2731 if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) { 2732 *l4_type = PP2_OUTQ_L4_TYPE_TCP; 2733 *gen_l4_cksum = 1; 2734 } else if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM) { 2735 *l4_type = PP2_OUTQ_L4_TYPE_UDP; 2736 *gen_l4_cksum = 1; 2737 } else { 2738 *l4_type = PP2_OUTQ_L4_TYPE_OTHER; 2739 /* no checksum for other type */ 2740 *gen_l4_cksum = 0; 2741 } 2742 } 2743 2744 /** 2745 * Release already sent buffers to bpool (buffer-pool). 2746 * 2747 * @param ppio 2748 * Pointer to the port structure. 2749 * @param hif 2750 * Pointer to the MUSDK hardware interface. 2751 * @param sq 2752 * Pointer to the shadow queue. 2753 * @param qid 2754 * Queue id number. 2755 * @param force 2756 * Force releasing packets. 2757 */ 2758 static inline void 2759 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, 2760 unsigned int core_id, struct mrvl_shadow_txq *sq, 2761 int qid, int force) 2762 { 2763 struct buff_release_entry *entry; 2764 uint16_t nb_done = 0, num = 0, skip_bufs = 0; 2765 int i; 2766 2767 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); 2768 2769 sq->num_to_release += nb_done; 2770 2771 if (likely(!force && 2772 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE)) 2773 return; 2774 2775 nb_done = sq->num_to_release; 2776 sq->num_to_release = 0; 2777 2778 for (i = 0; i < nb_done; i++) { 2779 entry = &sq->ent[sq->tail + num]; 2780 if (unlikely(!entry->buff.addr)) { 2781 MRVL_LOG(ERR, 2782 "Shadow memory @%d: cookie(%lx), pa(%lx)!", 2783 sq->tail, (u64)entry->buff.cookie, 2784 (u64)entry->buff.addr); 2785 skip_bufs = 1; 2786 goto skip; 2787 } 2788 2789 if (unlikely(!entry->bpool)) { 2790 struct rte_mbuf *mbuf; 2791 2792 mbuf = (struct rte_mbuf *)entry->buff.cookie; 2793 rte_pktmbuf_free(mbuf); 2794 skip_bufs = 1; 2795 goto skip; 2796 } 2797 2798 mrvl_port_bpool_size 2799 [entry->bpool->pp2_id][entry->bpool->id][core_id]++; 2800 num++; 2801 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE)) 2802 goto skip; 2803 continue; 2804 skip: 2805 if (likely(num)) 2806 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2807 num += skip_bufs; 2808 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2809 sq->size -= num; 2810 num = 0; 2811 skip_bufs = 0; 2812 } 2813 2814 if (likely(num)) { 2815 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num); 2816 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; 2817 sq->size -= num; 2818 } 2819 } 2820 2821 /** 2822 * DPDK callback for transmit. 2823 * 2824 * @param txq 2825 * Generic pointer transmit queue. 2826 * @param tx_pkts 2827 * Packets to transmit. 2828 * @param nb_pkts 2829 * Number of packets in array. 2830 * 2831 * @return 2832 * Number of packets successfully transmitted. 2833 */ 2834 static uint16_t 2835 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 2836 { 2837 struct mrvl_txq *q = txq; 2838 struct mrvl_shadow_txq *sq; 2839 struct pp2_hif *hif; 2840 struct pp2_ppio_desc descs[nb_pkts]; 2841 unsigned int core_id = rte_lcore_id(); 2842 int i, bytes_sent = 0; 2843 uint16_t num, sq_free_size; 2844 uint64_t addr; 2845 2846 hif = mrvl_get_hif(q->priv, core_id); 2847 sq = &q->shadow_txqs[core_id]; 2848 2849 if (unlikely(!q->priv->ppio || !hif)) 2850 return 0; 2851 2852 if (sq->size) 2853 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2854 sq, q->queue_id, 0); 2855 2856 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2857 if (unlikely(nb_pkts > sq_free_size)) 2858 nb_pkts = sq_free_size; 2859 2860 for (i = 0; i < nb_pkts; i++) { 2861 struct rte_mbuf *mbuf = tx_pkts[i]; 2862 int gen_l3_cksum, gen_l4_cksum; 2863 enum pp2_outq_l3_type l3_type; 2864 enum pp2_outq_l4_type l4_type; 2865 2866 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2867 struct rte_mbuf *pref_pkt_hdr; 2868 2869 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2870 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2871 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2872 } 2873 2874 mrvl_fill_shadowq(sq, mbuf); 2875 mrvl_fill_desc(&descs[i], mbuf); 2876 2877 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 2878 /* 2879 * in case unsupported ol_flags were passed 2880 * do not update descriptor offload information 2881 */ 2882 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS)) 2883 continue; 2884 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type, 2885 &gen_l3_cksum, &gen_l4_cksum); 2886 2887 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, 2888 mbuf->l2_len, 2889 mbuf->l2_len + mbuf->l3_len, 2890 gen_l3_cksum, gen_l4_cksum); 2891 } 2892 2893 num = nb_pkts; 2894 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts); 2895 /* number of packets that were not sent */ 2896 if (unlikely(num > nb_pkts)) { 2897 for (i = nb_pkts; i < num; i++) { 2898 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 2899 MRVL_PP2_TX_SHADOWQ_MASK; 2900 addr = sq->ent[sq->head].buff.cookie; 2901 bytes_sent -= 2902 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); 2903 } 2904 sq->size -= num - nb_pkts; 2905 } 2906 2907 q->bytes_sent += bytes_sent; 2908 2909 return nb_pkts; 2910 } 2911 2912 /** DPDK callback for S/G transmit. 2913 * 2914 * @param txq 2915 * Generic pointer transmit queue. 2916 * @param tx_pkts 2917 * Packets to transmit. 2918 * @param nb_pkts 2919 * Number of packets in array. 2920 * 2921 * @return 2922 * Number of packets successfully transmitted. 2923 */ 2924 static uint16_t 2925 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, 2926 uint16_t nb_pkts) 2927 { 2928 struct mrvl_txq *q = txq; 2929 struct mrvl_shadow_txq *sq; 2930 struct pp2_hif *hif; 2931 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS]; 2932 struct pp2_ppio_sg_pkts pkts; 2933 uint8_t frags[nb_pkts]; 2934 unsigned int core_id = rte_lcore_id(); 2935 int i, j, bytes_sent = 0; 2936 int tail, tail_first; 2937 uint16_t num, sq_free_size; 2938 uint16_t nb_segs, total_descs = 0; 2939 uint64_t addr; 2940 2941 hif = mrvl_get_hif(q->priv, core_id); 2942 sq = &q->shadow_txqs[core_id]; 2943 pkts.frags = frags; 2944 pkts.num = 0; 2945 2946 if (unlikely(!q->priv->ppio || !hif)) 2947 return 0; 2948 2949 if (sq->size) 2950 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, 2951 sq, q->queue_id, 0); 2952 2953 /* Save shadow queue free size */ 2954 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; 2955 2956 tail = 0; 2957 for (i = 0; i < nb_pkts; i++) { 2958 struct rte_mbuf *mbuf = tx_pkts[i]; 2959 struct rte_mbuf *seg = NULL; 2960 int gen_l3_cksum, gen_l4_cksum; 2961 enum pp2_outq_l3_type l3_type; 2962 enum pp2_outq_l4_type l4_type; 2963 2964 nb_segs = mbuf->nb_segs; 2965 tail_first = tail; 2966 total_descs += nb_segs; 2967 2968 /* 2969 * Check if total_descs does not exceed 2970 * shadow queue free size 2971 */ 2972 if (unlikely(total_descs > sq_free_size)) { 2973 total_descs -= nb_segs; 2974 break; 2975 } 2976 2977 /* Check if nb_segs does not exceed the max nb of desc per 2978 * fragmented packet 2979 */ 2980 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) { 2981 total_descs -= nb_segs; 2982 RTE_LOG(ERR, PMD, 2983 "Too many segments. Packet won't be sent.\n"); 2984 break; 2985 } 2986 2987 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { 2988 struct rte_mbuf *pref_pkt_hdr; 2989 2990 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT]; 2991 rte_mbuf_prefetch_part1(pref_pkt_hdr); 2992 rte_mbuf_prefetch_part2(pref_pkt_hdr); 2993 } 2994 2995 pkts.frags[pkts.num] = nb_segs; 2996 pkts.num++; 2997 2998 seg = mbuf; 2999 for (j = 0; j < nb_segs - 1; j++) { 3000 /* For the subsequent segments, set shadow queue 3001 * buffer to NULL 3002 */ 3003 mrvl_fill_shadowq(sq, NULL); 3004 mrvl_fill_desc(&descs[tail], seg); 3005 3006 tail++; 3007 seg = seg->next; 3008 } 3009 /* Put first mbuf info in last shadow queue entry */ 3010 mrvl_fill_shadowq(sq, mbuf); 3011 /* Update descriptor with last segment */ 3012 mrvl_fill_desc(&descs[tail++], seg); 3013 3014 bytes_sent += rte_pktmbuf_pkt_len(mbuf); 3015 /* In case unsupported ol_flags were passed 3016 * do not update descriptor offload information 3017 */ 3018 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS)) 3019 continue; 3020 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type, 3021 &gen_l3_cksum, &gen_l4_cksum); 3022 3023 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type, 3024 l4_type, mbuf->l2_len, 3025 mbuf->l2_len + mbuf->l3_len, 3026 gen_l3_cksum, gen_l4_cksum); 3027 } 3028 3029 num = total_descs; 3030 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs, 3031 &total_descs, &pkts); 3032 /* number of packets that were not sent */ 3033 if (unlikely(num > total_descs)) { 3034 for (i = total_descs; i < num; i++) { 3035 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & 3036 MRVL_PP2_TX_SHADOWQ_MASK; 3037 3038 addr = sq->ent[sq->head].buff.cookie; 3039 if (addr) 3040 bytes_sent -= 3041 rte_pktmbuf_pkt_len((struct rte_mbuf *) 3042 (cookie_addr_high | addr)); 3043 } 3044 sq->size -= num - total_descs; 3045 nb_pkts = pkts.num; 3046 } 3047 3048 q->bytes_sent += bytes_sent; 3049 3050 return nb_pkts; 3051 } 3052 3053 /** 3054 * Create private device structure. 3055 * 3056 * @param dev_name 3057 * Pointer to the port name passed in the initialization parameters. 3058 * 3059 * @return 3060 * Pointer to the newly allocated private device structure. 3061 */ 3062 static struct mrvl_priv * 3063 mrvl_priv_create(const char *dev_name) 3064 { 3065 struct pp2_bpool_params bpool_params; 3066 char match[MRVL_MATCH_LEN]; 3067 struct mrvl_priv *priv; 3068 uint16_t max_frame_size; 3069 int ret, bpool_bit; 3070 3071 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); 3072 if (!priv) 3073 return NULL; 3074 3075 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name, 3076 &priv->pp_id, &priv->ppio_id); 3077 if (ret) 3078 goto out_free_priv; 3079 3080 ret = pp2_ppio_get_l4_cksum_max_frame_size(priv->pp_id, priv->ppio_id, 3081 &max_frame_size); 3082 if (ret) 3083 goto out_free_priv; 3084 3085 priv->max_mtu = max_frame_size + RTE_ETHER_CRC_LEN - 3086 MRVL_PP2_ETH_HDRS_LEN; 3087 3088 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], 3089 PP2_BPOOL_NUM_POOLS); 3090 if (bpool_bit < 0) 3091 goto out_free_priv; 3092 priv->bpool_bit = bpool_bit; 3093 3094 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id, 3095 priv->bpool_bit); 3096 memset(&bpool_params, 0, sizeof(bpool_params)); 3097 bpool_params.match = match; 3098 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS; 3099 ret = pp2_bpool_init(&bpool_params, &priv->bpool); 3100 if (ret) 3101 goto out_clear_bpool_bit; 3102 3103 priv->ppio_params.type = PP2_PPIO_T_NIC; 3104 rte_spinlock_init(&priv->lock); 3105 3106 return priv; 3107 out_clear_bpool_bit: 3108 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); 3109 out_free_priv: 3110 rte_free(priv); 3111 return NULL; 3112 } 3113 3114 /** 3115 * Create device representing Ethernet port. 3116 * 3117 * @param name 3118 * Pointer to the port's name. 3119 * 3120 * @return 3121 * 0 on success, negative error value otherwise. 3122 */ 3123 static int 3124 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) 3125 { 3126 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0); 3127 struct rte_eth_dev *eth_dev; 3128 struct mrvl_priv *priv; 3129 struct ifreq req; 3130 3131 eth_dev = rte_eth_dev_allocate(name); 3132 if (!eth_dev) 3133 return -ENOMEM; 3134 3135 priv = mrvl_priv_create(name); 3136 if (!priv) { 3137 ret = -ENOMEM; 3138 goto out_free; 3139 } 3140 eth_dev->data->dev_private = priv; 3141 3142 eth_dev->data->mac_addrs = 3143 rte_zmalloc("mac_addrs", 3144 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0); 3145 if (!eth_dev->data->mac_addrs) { 3146 MRVL_LOG(ERR, "Failed to allocate space for eth addrs"); 3147 ret = -ENOMEM; 3148 goto out_free; 3149 } 3150 3151 memset(&req, 0, sizeof(req)); 3152 strcpy(req.ifr_name, name); 3153 ret = ioctl(fd, SIOCGIFHWADDR, &req); 3154 if (ret) 3155 goto out_free; 3156 3157 memcpy(eth_dev->data->mac_addrs[0].addr_bytes, 3158 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN); 3159 3160 eth_dev->device = &vdev->device; 3161 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; 3162 mrvl_set_tx_function(eth_dev); 3163 eth_dev->dev_ops = &mrvl_ops; 3164 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 3165 3166 eth_dev->data->dev_link.link_status = ETH_LINK_UP; 3167 3168 rte_eth_dev_probing_finish(eth_dev); 3169 return 0; 3170 out_free: 3171 rte_eth_dev_release_port(eth_dev); 3172 3173 return ret; 3174 } 3175 3176 /** 3177 * Callback used by rte_kvargs_process() during argument parsing. 3178 * 3179 * @param key 3180 * Pointer to the parsed key (unused). 3181 * @param value 3182 * Pointer to the parsed value. 3183 * @param extra_args 3184 * Pointer to the extra arguments which contains address of the 3185 * table of pointers to parsed interface names. 3186 * 3187 * @return 3188 * Always 0. 3189 */ 3190 static int 3191 mrvl_get_ifnames(const char *key __rte_unused, const char *value, 3192 void *extra_args) 3193 { 3194 struct mrvl_ifnames *ifnames = extra_args; 3195 3196 ifnames->names[ifnames->idx++] = value; 3197 3198 return 0; 3199 } 3200 3201 /** 3202 * DPDK callback to register the virtual device. 3203 * 3204 * @param vdev 3205 * Pointer to the virtual device. 3206 * 3207 * @return 3208 * 0 on success, negative error value otherwise. 3209 */ 3210 static int 3211 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) 3212 { 3213 struct rte_kvargs *kvlist; 3214 struct mrvl_ifnames ifnames; 3215 int ret = -EINVAL; 3216 uint32_t i, ifnum, cfgnum; 3217 const char *params; 3218 3219 params = rte_vdev_device_args(vdev); 3220 if (!params) 3221 return -EINVAL; 3222 3223 kvlist = rte_kvargs_parse(params, valid_args); 3224 if (!kvlist) 3225 return -EINVAL; 3226 3227 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); 3228 if (ifnum > RTE_DIM(ifnames.names)) 3229 goto out_free_kvlist; 3230 3231 ifnames.idx = 0; 3232 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, 3233 mrvl_get_ifnames, &ifnames); 3234 3235 3236 /* 3237 * The below system initialization should be done only once, 3238 * on the first provided configuration file 3239 */ 3240 if (!mrvl_cfg) { 3241 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); 3242 MRVL_LOG(INFO, "Parsing config file!"); 3243 if (cfgnum > 1) { 3244 MRVL_LOG(ERR, "Cannot handle more than one config file!"); 3245 goto out_free_kvlist; 3246 } else if (cfgnum == 1) { 3247 rte_kvargs_process(kvlist, MRVL_CFG_ARG, 3248 mrvl_get_cfg, &mrvl_cfg); 3249 } 3250 } 3251 3252 if (mrvl_dev_num) 3253 goto init_devices; 3254 3255 MRVL_LOG(INFO, "Perform MUSDK initializations"); 3256 3257 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist); 3258 if (ret) 3259 goto out_free_kvlist; 3260 3261 ret = mrvl_init_pp2(); 3262 if (ret) { 3263 MRVL_LOG(ERR, "Failed to init PP!"); 3264 rte_mvep_deinit(MVEP_MOD_T_PP2); 3265 goto out_free_kvlist; 3266 } 3267 3268 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); 3269 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); 3270 3271 mrvl_lcore_first = RTE_MAX_LCORE; 3272 mrvl_lcore_last = 0; 3273 3274 init_devices: 3275 for (i = 0; i < ifnum; i++) { 3276 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]); 3277 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); 3278 if (ret) 3279 goto out_cleanup; 3280 mrvl_dev_num++; 3281 } 3282 3283 rte_kvargs_free(kvlist); 3284 3285 return 0; 3286 out_cleanup: 3287 rte_pmd_mrvl_remove(vdev); 3288 3289 out_free_kvlist: 3290 rte_kvargs_free(kvlist); 3291 3292 return ret; 3293 } 3294 3295 /** 3296 * DPDK callback to remove virtual device. 3297 * 3298 * @param vdev 3299 * Pointer to the removed virtual device. 3300 * 3301 * @return 3302 * 0 on success, negative error value otherwise. 3303 */ 3304 static int 3305 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) 3306 { 3307 uint16_t port_id; 3308 int ret = 0; 3309 3310 RTE_ETH_FOREACH_DEV(port_id) { 3311 if (rte_eth_devices[port_id].device != &vdev->device) 3312 continue; 3313 ret |= rte_eth_dev_close(port_id); 3314 } 3315 3316 return ret == 0 ? 0 : -EIO; 3317 } 3318 3319 static struct rte_vdev_driver pmd_mrvl_drv = { 3320 .probe = rte_pmd_mrvl_probe, 3321 .remove = rte_pmd_mrvl_remove, 3322 }; 3323 3324 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv); 3325 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2); 3326 RTE_LOG_REGISTER(mrvl_logtype, pmd.net.mvpp2, NOTICE); 3327