1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021 6WIND S.A. 3 * Copyright 2021 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RX_H_ 7 #define RTE_PMD_MLX5_RX_H_ 8 9 #include <stdint.h> 10 #include <sys/queue.h> 11 12 #include <rte_mbuf.h> 13 #include <rte_mempool.h> 14 #include <rte_common.h> 15 #include <rte_spinlock.h> 16 17 #include <mlx5_common_mr.h> 18 19 #include "mlx5.h" 20 #include "mlx5_autoconf.h" 21 #include "rte_pmd_mlx5.h" 22 23 /* Support tunnel matching. */ 24 #define MLX5_FLOW_TUNNEL 10 25 26 #define RXQ_PORT(rxq_ctrl) LIST_FIRST(&(rxq_ctrl)->owners)->priv 27 #define RXQ_DEV(rxq_ctrl) ETH_DEV(RXQ_PORT(rxq_ctrl)) 28 #define RXQ_PORT_ID(rxq_ctrl) PORT_ID(RXQ_PORT(rxq_ctrl)) 29 30 /* First entry must be NULL for comparison. */ 31 #define mlx5_mr_btree_len(bt) ((bt)->len - 1) 32 33 struct mlx5_rxq_stats { 34 #ifdef MLX5_PMD_SOFT_COUNTERS 35 uint64_t ipackets; /**< Total of successfully received packets. */ 36 uint64_t ibytes; /**< Total of successfully received bytes. */ 37 #endif 38 uint64_t idropped; /**< Total of packets dropped when RX ring full. */ 39 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */ 40 }; 41 42 /* Compressed CQE context. */ 43 struct rxq_zip { 44 uint16_t ai; /* Array index. */ 45 uint16_t ca; /* Current array index. */ 46 uint16_t na; /* Next array index. */ 47 uint16_t cq_ci; /* The next CQE. */ 48 uint32_t cqe_cnt; /* Number of CQEs. */ 49 }; 50 51 /* Get pointer to the first stride. */ 52 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \ 53 sizeof(struct mlx5_mprq_buf) + \ 54 (strd_n) * \ 55 sizeof(struct rte_mbuf_ext_shared_info) + \ 56 RTE_PKTMBUF_HEADROOM)) 57 58 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 59 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 60 61 enum mlx5_rxq_err_state { 62 MLX5_RXQ_ERR_STATE_NO_ERROR = 0, 63 MLX5_RXQ_ERR_STATE_NEED_RESET, 64 MLX5_RXQ_ERR_STATE_NEED_READY, 65 }; 66 67 enum mlx5_rqx_code { 68 MLX5_RXQ_CODE_EXIT = 0, 69 MLX5_RXQ_CODE_NOMBUF, 70 MLX5_RXQ_CODE_DROPPED, 71 }; 72 73 struct mlx5_eth_rxseg { 74 struct rte_mempool *mp; /**< Memory pool to allocate segment from. */ 75 uint16_t length; /**< Segment data length, configures split point. */ 76 uint16_t offset; /**< Data offset from beginning of mbuf data buffer. */ 77 uint32_t reserved; /**< Reserved field. */ 78 }; 79 80 /* RX queue descriptor. */ 81 struct mlx5_rxq_data { 82 unsigned int csum:1; /* Enable checksum offloading. */ 83 unsigned int hw_timestamp:1; /* Enable HW timestamp. */ 84 unsigned int rt_timestamp:1; /* Realtime timestamp format. */ 85 unsigned int vlan_strip:1; /* Enable VLAN stripping. */ 86 unsigned int crc_present:1; /* CRC must be subtracted. */ 87 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */ 88 unsigned int cqe_n:4; /* Log 2 of CQ elements. */ 89 unsigned int elts_n:4; /* Log 2 of Mbufs. */ 90 unsigned int rss_hash:1; /* RSS hash result is enabled. */ 91 unsigned int mark:1; /* Marked flow available on the queue. */ 92 unsigned int log_strd_num:5; /* Log 2 of the number of stride. */ 93 unsigned int log_strd_sz:4; /* Log 2 of stride size. */ 94 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */ 95 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */ 96 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */ 97 unsigned int lro:1; /* Enable LRO. */ 98 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */ 99 unsigned int mcqe_format:3; /* CQE compression format. */ 100 unsigned int shared:1; /* Shared RXQ. */ 101 unsigned int delay_drop:1; /* Enable delay drop. */ 102 volatile uint32_t *rq_db; 103 volatile uint32_t *cq_db; 104 uint16_t port_id; 105 uint32_t elts_ci; 106 uint32_t rq_ci; 107 uint16_t consumed_strd; /* Number of consumed strides in WQE. */ 108 uint32_t rq_pi; 109 uint32_t cq_ci; 110 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */ 111 uint32_t byte_mask; 112 union { 113 struct rxq_zip zip; /* Compressed context. */ 114 uint16_t decompressed; 115 /* Number of ready mbufs decompressed from the CQ. */ 116 }; 117 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */ 118 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */ 119 volatile void *wqes; 120 volatile struct mlx5_cqe(*cqes)[]; 121 struct rte_mbuf *(*elts)[]; 122 struct mlx5_mprq_buf *(*mprq_bufs)[]; 123 struct rte_mempool *mp; 124 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 125 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */ 126 struct mlx5_dev_ctx_shared *sh; /* Shared context. */ 127 uint16_t idx; /* Queue index. */ 128 struct mlx5_rxq_stats stats; 129 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */ 130 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ 131 struct mlx5_uar_data uar_data; /* CQ doorbell. */ 132 uint32_t cqn; /* CQ number. */ 133 uint8_t cq_arm_sn; /* CQ arm seq number. */ 134 uint32_t tunnel; /* Tunnel information. */ 135 int timestamp_offset; /* Dynamic mbuf field for timestamp. */ 136 uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */ 137 uint64_t flow_meta_mask; 138 int32_t flow_meta_offset; 139 uint32_t flow_meta_port_mask; 140 uint32_t rxseg_n; /* Number of split segment descriptions. */ 141 struct mlx5_eth_rxseg rxseg[MLX5_MAX_RXQ_NSEG]; 142 /* Buffer split segment descriptions - sizes, offsets, pools. */ 143 } __rte_cache_aligned; 144 145 /* RX queue control descriptor. */ 146 struct mlx5_rxq_ctrl { 147 struct mlx5_rxq_data rxq; /* Data path structure. */ 148 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */ 149 LIST_HEAD(priv, mlx5_rxq_priv) owners; /* Owner rxq list. */ 150 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */ 151 struct mlx5_dev_ctx_shared *sh; /* Shared context. */ 152 bool is_hairpin; /* Whether RxQ type is Hairpin. */ 153 unsigned int socket; /* CPU socket ID for allocations. */ 154 LIST_ENTRY(mlx5_rxq_ctrl) share_entry; /* Entry in shared RXQ list. */ 155 uint32_t share_group; /* Group ID of shared RXQ. */ 156 uint16_t share_qid; /* Shared RxQ ID in group. */ 157 unsigned int started:1; /* Whether (shared) RXQ has been started. */ 158 unsigned int irq:1; /* Whether IRQ is enabled. */ 159 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */ 160 uint32_t wqn; /* WQ number. */ 161 uint32_t rxseg_n; /* Number of split segment descriptions. */ 162 struct rte_eth_rxseg_split rxseg[MLX5_MAX_RXQ_NSEG]; 163 /* Saved original buffer split segment configuration. */ 164 uint16_t dump_file_n; /* Number of dump files. */ 165 }; 166 167 /* RX queue private data. */ 168 struct mlx5_rxq_priv { 169 uint16_t idx; /* Queue index. */ 170 uint32_t refcnt; /* Reference counter. */ 171 struct mlx5_rxq_ctrl *ctrl; /* Shared Rx Queue. */ 172 LIST_ENTRY(mlx5_rxq_priv) owner_entry; /* Entry in shared rxq_ctrl. */ 173 struct mlx5_priv *priv; /* Back pointer to private data. */ 174 struct mlx5_devx_rq devx_rq; 175 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ 176 uint32_t hairpin_status; /* Hairpin binding status. */ 177 }; 178 179 /* External RX queue descriptor. */ 180 struct mlx5_external_rxq { 181 uint32_t hw_id; /* Queue index in the Hardware. */ 182 uint32_t refcnt; /* Reference counter. */ 183 }; 184 185 /* mlx5_rxq.c */ 186 187 extern uint8_t rss_hash_default_key[]; 188 189 unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data); 190 int mlx5_mprq_free_mp(struct rte_eth_dev *dev); 191 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev); 192 int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id); 193 int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id); 194 int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id); 195 int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id); 196 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 197 unsigned int socket, const struct rte_eth_rxconf *conf, 198 struct rte_mempool *mp); 199 int mlx5_rx_hairpin_queue_setup 200 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, 201 const struct rte_eth_hairpin_conf *hairpin_conf); 202 void mlx5_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 203 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev); 204 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev); 205 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 206 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); 207 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev); 208 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, 209 uint16_t desc, unsigned int socket, 210 const struct rte_eth_rxconf *conf, 211 const struct rte_eth_rxseg_split *rx_seg, 212 uint16_t n_seg); 213 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new 214 (struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, uint16_t desc, 215 const struct rte_eth_hairpin_conf *hairpin_conf); 216 struct mlx5_rxq_priv *mlx5_rxq_ref(struct rte_eth_dev *dev, uint16_t idx); 217 uint32_t mlx5_rxq_deref(struct rte_eth_dev *dev, uint16_t idx); 218 struct mlx5_rxq_priv *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx); 219 struct mlx5_rxq_ctrl *mlx5_rxq_ctrl_get(struct rte_eth_dev *dev, uint16_t idx); 220 struct mlx5_rxq_data *mlx5_rxq_data_get(struct rte_eth_dev *dev, uint16_t idx); 221 struct mlx5_external_rxq *mlx5_ext_rxq_ref(struct rte_eth_dev *dev, 222 uint16_t idx); 223 uint32_t mlx5_ext_rxq_deref(struct rte_eth_dev *dev, uint16_t idx); 224 struct mlx5_external_rxq *mlx5_ext_rxq_get(struct rte_eth_dev *dev, 225 uint16_t idx); 226 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx); 227 int mlx5_rxq_verify(struct rte_eth_dev *dev); 228 int mlx5_ext_rxq_verify(struct rte_eth_dev *dev); 229 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl); 230 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev); 231 struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev, 232 const uint16_t *queues, 233 uint32_t queues_n); 234 struct mlx5_ind_table_obj *mlx5_ind_table_obj_new(struct rte_eth_dev *dev, 235 const uint16_t *queues, 236 uint32_t queues_n, 237 bool standalone, 238 bool ref_qs); 239 int mlx5_ind_table_obj_release(struct rte_eth_dev *dev, 240 struct mlx5_ind_table_obj *ind_tbl, 241 bool deref_rxqs); 242 int mlx5_ind_table_obj_setup(struct rte_eth_dev *dev, 243 struct mlx5_ind_table_obj *ind_tbl, 244 bool ref_qs); 245 int mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, 246 struct mlx5_ind_table_obj *ind_tbl, 247 uint16_t *queues, const uint32_t queues_n, 248 bool standalone, 249 bool ref_new_qs, bool deref_old_qs); 250 int mlx5_ind_table_obj_attach(struct rte_eth_dev *dev, 251 struct mlx5_ind_table_obj *ind_tbl); 252 int mlx5_ind_table_obj_detach(struct rte_eth_dev *dev, 253 struct mlx5_ind_table_obj *ind_tbl); 254 struct mlx5_list_entry *mlx5_hrxq_create_cb(void *tool_ctx, void *cb_ctx); 255 int mlx5_hrxq_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, 256 void *cb_ctx); 257 void mlx5_hrxq_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry); 258 struct mlx5_list_entry *mlx5_hrxq_clone_cb(void *tool_ctx, 259 struct mlx5_list_entry *entry, 260 void *cb_ctx __rte_unused); 261 void mlx5_hrxq_clone_free_cb(void *tool_ctx __rte_unused, 262 struct mlx5_list_entry *entry); 263 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev, 264 struct mlx5_flow_rss_desc *rss_desc); 265 int mlx5_hrxq_obj_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq); 266 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx); 267 uint32_t mlx5_hrxq_verify(struct rte_eth_dev *dev); 268 bool mlx5_rxq_is_hairpin(struct rte_eth_dev *dev, uint16_t idx); 269 const struct rte_eth_hairpin_conf *mlx5_rxq_get_hairpin_conf 270 (struct rte_eth_dev *dev, uint16_t idx); 271 struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev); 272 void mlx5_drop_action_destroy(struct rte_eth_dev *dev); 273 uint64_t mlx5_get_rx_port_offloads(void); 274 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev); 275 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev); 276 int mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hxrq_idx, 277 const uint8_t *rss_key, uint32_t rss_key_len, 278 uint64_t hash_fields, 279 const uint16_t *queues, uint32_t queues_n); 280 281 /* mlx5_rx.c */ 282 283 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n); 284 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq); 285 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec); 286 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf); 287 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, 288 uint16_t pkts_n); 289 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset); 290 uint32_t mlx5_rx_queue_count(void *rx_queue); 291 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 292 struct rte_eth_rxq_info *qinfo); 293 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, 294 struct rte_eth_burst_mode *mode); 295 int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); 296 297 /* Vectorized version of mlx5_rx.c */ 298 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data); 299 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev); 300 uint16_t mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, 301 uint16_t pkts_n); 302 uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_rxq, struct rte_mbuf **pkts, 303 uint16_t pkts_n); 304 305 static int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq); 306 307 /** 308 * Query LKey for an address on Rx. No need to flush local caches 309 * as the Rx mempool database entries are valid for the lifetime of the queue. 310 * 311 * @param rxq 312 * Pointer to Rx queue structure. 313 * @param addr 314 * Address to search. 315 * 316 * @return 317 * Searched LKey on success, UINT32_MAX on no match. 318 * This function always succeeds on valid input. 319 */ 320 static __rte_always_inline uint32_t 321 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr) 322 { 323 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl; 324 struct rte_mempool *mp; 325 uint32_t lkey; 326 327 /* Linear search on MR cache array. */ 328 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 329 MLX5_MR_CACHE_N, addr); 330 if (likely(lkey != UINT32_MAX)) 331 return lkey; 332 mp = mlx5_rxq_mprq_enabled(rxq) ? rxq->mprq_mp : rxq->mp; 333 return mlx5_mr_mempool2mr_bh(mr_ctrl, mp, addr); 334 } 335 336 /** 337 * Query LKey from a packet buffer for Rx. No need to flush local caches 338 * as the Rx mempool database entries are valid for the lifetime of the queue. 339 * 340 * @param rxq 341 * Pointer to Rx queue structure. 342 * @param mb 343 * Buffer to search the address of. 344 * 345 * @return 346 * Searched LKey on success, UINT32_MAX on no match. 347 * This function always succeeds on valid input. 348 */ 349 static __rte_always_inline uint32_t 350 mlx5_rx_mb2mr(struct mlx5_rxq_data *rxq, struct rte_mbuf *mb) 351 { 352 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl; 353 uintptr_t addr = (uintptr_t)mb->buf_addr; 354 uint32_t lkey; 355 356 /* Linear search on MR cache array. */ 357 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 358 MLX5_MR_CACHE_N, addr); 359 if (likely(lkey != UINT32_MAX)) 360 return lkey; 361 /* Slower search in the mempool database on miss. */ 362 return mlx5_mr_mempool2mr_bh(mr_ctrl, mb->pool, addr); 363 } 364 365 /** 366 * Convert timestamp from HW format to linear counter 367 * from Packet Pacing Clock Queue CQE timestamp format. 368 * 369 * @param sh 370 * Pointer to the device shared context. Might be needed 371 * to convert according current device configuration. 372 * @param ts 373 * Timestamp from CQE to convert. 374 * @return 375 * UTC in nanoseconds 376 */ 377 static __rte_always_inline uint64_t 378 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts) 379 { 380 RTE_SET_USED(sh); 381 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S; 382 } 383 384 /** 385 * Set timestamp in mbuf dynamic field. 386 * 387 * @param mbuf 388 * Structure to write into. 389 * @param offset 390 * Dynamic field offset in mbuf structure. 391 * @param timestamp 392 * Value to write. 393 */ 394 static __rte_always_inline void 395 mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset, 396 rte_mbuf_timestamp_t timestamp) 397 { 398 *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp; 399 } 400 401 /** 402 * Replace MPRQ buffer. 403 * 404 * @param rxq 405 * Pointer to Rx queue structure. 406 * @param rq_idx 407 * RQ index to replace. 408 */ 409 static __rte_always_inline void 410 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx) 411 { 412 const uint32_t strd_n = RTE_BIT32(rxq->log_strd_num); 413 struct mlx5_mprq_buf *rep = rxq->mprq_repl; 414 volatile struct mlx5_wqe_data_seg *wqe = 415 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg; 416 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_idx]; 417 void *addr; 418 419 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) > 1) { 420 MLX5_ASSERT(rep != NULL); 421 /* Replace MPRQ buf. */ 422 (*rxq->mprq_bufs)[rq_idx] = rep; 423 /* Replace WQE. */ 424 addr = mlx5_mprq_buf_addr(rep, strd_n); 425 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr); 426 /* If there's only one MR, no need to replace LKey in WQE. */ 427 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1)) 428 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr); 429 /* Stash a mbuf for next replacement. */ 430 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep))) 431 rxq->mprq_repl = rep; 432 else 433 rxq->mprq_repl = NULL; 434 /* Release the old buffer. */ 435 mlx5_mprq_buf_free(buf); 436 } else if (unlikely(rxq->mprq_repl == NULL)) { 437 struct mlx5_mprq_buf *rep; 438 439 /* 440 * Currently, the MPRQ mempool is out of buffer 441 * and doing memcpy regardless of the size of Rx 442 * packet. Retry allocation to get back to 443 * normal. 444 */ 445 if (!rte_mempool_get(rxq->mprq_mp, (void **)&rep)) 446 rxq->mprq_repl = rep; 447 } 448 } 449 450 /** 451 * Attach or copy MPRQ buffer content to a packet. 452 * 453 * @param rxq 454 * Pointer to Rx queue structure. 455 * @param pkt 456 * Pointer to a packet to fill. 457 * @param len 458 * Packet length. 459 * @param buf 460 * Pointer to a MPRQ buffer to take the data from. 461 * @param strd_idx 462 * Stride index to start from. 463 * @param strd_cnt 464 * Number of strides to consume. 465 */ 466 static __rte_always_inline enum mlx5_rqx_code 467 mprq_buf_to_pkt(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, uint32_t len, 468 struct mlx5_mprq_buf *buf, uint16_t strd_idx, uint16_t strd_cnt) 469 { 470 const uint32_t strd_n = RTE_BIT32(rxq->log_strd_num); 471 const uint16_t strd_sz = RTE_BIT32(rxq->log_strd_sz); 472 const uint16_t strd_shift = 473 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en; 474 const int32_t hdrm_overlap = 475 len + RTE_PKTMBUF_HEADROOM - strd_cnt * strd_sz; 476 const uint32_t offset = strd_idx * strd_sz + strd_shift; 477 void *addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset); 478 479 /* 480 * Memcpy packets to the target mbuf if: 481 * - The size of packet is smaller than mprq_max_memcpy_len. 482 * - Out of buffer in the Mempool for Multi-Packet RQ. 483 * - The packet's stride overlaps a headroom and scatter is off. 484 */ 485 if (len <= rxq->mprq_max_memcpy_len || 486 rxq->mprq_repl == NULL || 487 (hdrm_overlap > 0 && !rxq->strd_scatter_en)) { 488 if (likely(len <= 489 (uint32_t)(pkt->buf_len - RTE_PKTMBUF_HEADROOM))) { 490 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), 491 addr, len); 492 DATA_LEN(pkt) = len; 493 } else if (rxq->strd_scatter_en) { 494 struct rte_mbuf *prev = pkt; 495 uint32_t seg_len = RTE_MIN(len, (uint32_t) 496 (pkt->buf_len - RTE_PKTMBUF_HEADROOM)); 497 uint32_t rem_len = len - seg_len; 498 499 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), 500 addr, seg_len); 501 DATA_LEN(pkt) = seg_len; 502 while (rem_len) { 503 struct rte_mbuf *next = 504 rte_pktmbuf_alloc(rxq->mp); 505 506 if (unlikely(next == NULL)) 507 return MLX5_RXQ_CODE_NOMBUF; 508 NEXT(prev) = next; 509 SET_DATA_OFF(next, 0); 510 addr = RTE_PTR_ADD(addr, seg_len); 511 seg_len = RTE_MIN(rem_len, (uint32_t) 512 (next->buf_len - RTE_PKTMBUF_HEADROOM)); 513 rte_memcpy 514 (rte_pktmbuf_mtod(next, void *), 515 addr, seg_len); 516 DATA_LEN(next) = seg_len; 517 rem_len -= seg_len; 518 prev = next; 519 ++NB_SEGS(pkt); 520 } 521 } else { 522 return MLX5_RXQ_CODE_DROPPED; 523 } 524 } else { 525 rte_iova_t buf_iova; 526 struct rte_mbuf_ext_shared_info *shinfo; 527 uint16_t buf_len = strd_cnt * strd_sz; 528 void *buf_addr; 529 530 /* Increment the refcnt of the whole chunk. */ 531 __atomic_add_fetch(&buf->refcnt, 1, __ATOMIC_RELAXED); 532 MLX5_ASSERT(__atomic_load_n(&buf->refcnt, 533 __ATOMIC_RELAXED) <= strd_n + 1); 534 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM); 535 /* 536 * MLX5 device doesn't use iova but it is necessary in a 537 * case where the Rx packet is transmitted via a 538 * different PMD. 539 */ 540 buf_iova = rte_mempool_virt2iova(buf) + 541 RTE_PTR_DIFF(buf_addr, buf); 542 shinfo = &buf->shinfos[strd_idx]; 543 rte_mbuf_ext_refcnt_set(shinfo, 1); 544 /* 545 * RTE_MBUF_F_EXTERNAL will be set to pkt->ol_flags when 546 * attaching the stride to mbuf and more offload flags 547 * will be added below by calling rxq_cq_to_mbuf(). 548 * Other fields will be overwritten. 549 */ 550 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova, 551 buf_len, shinfo); 552 /* Set mbuf head-room. */ 553 SET_DATA_OFF(pkt, RTE_PKTMBUF_HEADROOM); 554 MLX5_ASSERT(pkt->ol_flags & RTE_MBUF_F_EXTERNAL); 555 MLX5_ASSERT(rte_pktmbuf_tailroom(pkt) >= 556 len - (hdrm_overlap > 0 ? hdrm_overlap : 0)); 557 DATA_LEN(pkt) = len; 558 /* 559 * Copy the last fragment of a packet (up to headroom 560 * size bytes) in case there is a stride overlap with 561 * a next packet's headroom. Allocate a separate mbuf 562 * to store this fragment and link it. Scatter is on. 563 */ 564 if (hdrm_overlap > 0) { 565 MLX5_ASSERT(rxq->strd_scatter_en); 566 struct rte_mbuf *seg = 567 rte_pktmbuf_alloc(rxq->mp); 568 569 if (unlikely(seg == NULL)) 570 return MLX5_RXQ_CODE_NOMBUF; 571 SET_DATA_OFF(seg, 0); 572 rte_memcpy(rte_pktmbuf_mtod(seg, void *), 573 RTE_PTR_ADD(addr, len - hdrm_overlap), 574 hdrm_overlap); 575 DATA_LEN(seg) = hdrm_overlap; 576 DATA_LEN(pkt) = len - hdrm_overlap; 577 NEXT(pkt) = seg; 578 NB_SEGS(pkt) = 2; 579 } 580 } 581 return MLX5_RXQ_CODE_EXIT; 582 } 583 584 /** 585 * Check whether Multi-Packet RQ can be enabled for the device. 586 * 587 * @param dev 588 * Pointer to Ethernet device. 589 * 590 * @return 591 * 1 if supported, negative errno value if not. 592 */ 593 static __rte_always_inline int 594 mlx5_check_mprq_support(struct rte_eth_dev *dev) 595 { 596 struct mlx5_priv *priv = dev->data->dev_private; 597 598 if (priv->config.mprq.enabled && 599 priv->rxqs_n >= priv->config.mprq.min_rxqs_num) 600 return 1; 601 return -ENOTSUP; 602 } 603 604 /** 605 * Check whether Multi-Packet RQ is enabled for the Rx queue. 606 * 607 * @param rxq 608 * Pointer to receive queue structure. 609 * 610 * @return 611 * 0 if disabled, otherwise enabled. 612 */ 613 static __rte_always_inline int 614 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq) 615 { 616 return rxq->log_strd_num > 0; 617 } 618 619 /** 620 * Check whether Multi-Packet RQ is enabled for the device. 621 * 622 * @param dev 623 * Pointer to Ethernet device. 624 * 625 * @return 626 * 0 if disabled, otherwise enabled. 627 */ 628 static __rte_always_inline int 629 mlx5_mprq_enabled(struct rte_eth_dev *dev) 630 { 631 struct mlx5_priv *priv = dev->data->dev_private; 632 uint32_t i; 633 uint16_t n = 0; 634 uint16_t n_ibv = 0; 635 636 if (mlx5_check_mprq_support(dev) < 0) 637 return 0; 638 /* All the configured queues should be enabled. */ 639 for (i = 0; i < priv->rxqs_n; ++i) { 640 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); 641 642 if (rxq_ctrl == NULL || rxq_ctrl->is_hairpin) 643 continue; 644 n_ibv++; 645 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq)) 646 ++n; 647 } 648 /* Multi-Packet RQ can't be partially configured. */ 649 MLX5_ASSERT(n == 0 || n == n_ibv); 650 return n == n_ibv; 651 } 652 653 /** 654 * Check whether given RxQ is external. 655 * 656 * @param dev 657 * Pointer to Ethernet device. 658 * @param queue_idx 659 * Rx queue index. 660 * 661 * @return 662 * True if is external RxQ, otherwise false. 663 */ 664 static __rte_always_inline bool 665 mlx5_is_external_rxq(struct rte_eth_dev *dev, uint16_t queue_idx) 666 { 667 struct mlx5_priv *priv = dev->data->dev_private; 668 struct mlx5_external_rxq *rxq; 669 670 if (!priv->ext_rxqs || queue_idx < MLX5_EXTERNAL_RX_QUEUE_ID_MIN) 671 return false; 672 rxq = &priv->ext_rxqs[queue_idx - MLX5_EXTERNAL_RX_QUEUE_ID_MIN]; 673 return !!__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED); 674 } 675 676 #endif /* RTE_PMD_MLX5_RX_H_ */ 677