1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <netinet/in.h> 9 #include <sys/queue.h> 10 #include <stdalign.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 #include <rte_alarm.h> 15 #include <rte_mtr.h> 16 17 #include <mlx5_glue.h> 18 #include <mlx5_prm.h> 19 20 #include "mlx5.h" 21 22 /* Private rte flow items. */ 23 enum mlx5_rte_flow_item_type { 24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 25 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 29 }; 30 31 /* Private (internal) rte flow actions. */ 32 enum mlx5_rte_flow_action_type { 33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 34 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 35 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 38 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 39 MLX5_RTE_FLOW_ACTION_TYPE_AGE, 40 }; 41 42 #define MLX5_SHARED_ACTION_TYPE_OFFSET 30 43 44 enum { 45 MLX5_SHARED_ACTION_TYPE_RSS, 46 MLX5_SHARED_ACTION_TYPE_AGE, 47 }; 48 49 /* Matches on selected register. */ 50 struct mlx5_rte_flow_item_tag { 51 enum modify_reg id; 52 uint32_t data; 53 }; 54 55 /* Modify selected register. */ 56 struct mlx5_rte_flow_action_set_tag { 57 enum modify_reg id; 58 uint32_t data; 59 }; 60 61 struct mlx5_flow_action_copy_mreg { 62 enum modify_reg dst; 63 enum modify_reg src; 64 }; 65 66 /* Matches on source queue. */ 67 struct mlx5_rte_flow_item_tx_queue { 68 uint32_t queue; 69 }; 70 71 /* Feature name to allocate metadata register. */ 72 enum mlx5_feature_name { 73 MLX5_HAIRPIN_RX, 74 MLX5_HAIRPIN_TX, 75 MLX5_METADATA_RX, 76 MLX5_METADATA_TX, 77 MLX5_METADATA_FDB, 78 MLX5_FLOW_MARK, 79 MLX5_APP_TAG, 80 MLX5_COPY_MARK, 81 MLX5_MTR_COLOR, 82 MLX5_MTR_SFX, 83 MLX5_ASO_FLOW_HIT, 84 }; 85 86 /* Default queue number. */ 87 #define MLX5_RSSQ_DEFAULT_NUM 16 88 89 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 90 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 91 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 92 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 93 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 94 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 95 96 /* Pattern inner Layer bits. */ 97 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 98 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 99 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 100 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 101 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 102 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 103 104 /* Pattern tunnel Layer bits. */ 105 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 106 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 107 #define MLX5_FLOW_LAYER_GRE (1u << 14) 108 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 109 /* List of tunnel Layer bits continued below. */ 110 111 /* General pattern items bits. */ 112 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 113 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 114 #define MLX5_FLOW_ITEM_TAG (1u << 18) 115 #define MLX5_FLOW_ITEM_MARK (1u << 19) 116 117 /* Pattern MISC bits. */ 118 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 119 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 120 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 121 122 /* Pattern tunnel Layer bits (continued). */ 123 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 124 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 125 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 126 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 127 128 /* Queue items. */ 129 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 130 131 /* Pattern tunnel Layer bits (continued). */ 132 #define MLX5_FLOW_LAYER_GTP (1u << 28) 133 134 /* Pattern eCPRI Layer bit. */ 135 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 136 137 /* IPv6 Fragment Extension Header bit. */ 138 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 139 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 140 141 /* Pattern tunnel Layer bits (continued). */ 142 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) 143 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) 144 145 /* Outer Masks. */ 146 #define MLX5_FLOW_LAYER_OUTER_L3 \ 147 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 148 #define MLX5_FLOW_LAYER_OUTER_L4 \ 149 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 150 #define MLX5_FLOW_LAYER_OUTER \ 151 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 152 MLX5_FLOW_LAYER_OUTER_L4) 153 154 /* Tunnel Masks. */ 155 #define MLX5_FLOW_LAYER_TUNNEL \ 156 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 157 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 158 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 159 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 160 161 /* Inner Masks. */ 162 #define MLX5_FLOW_LAYER_INNER_L3 \ 163 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 164 #define MLX5_FLOW_LAYER_INNER_L4 \ 165 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 166 #define MLX5_FLOW_LAYER_INNER \ 167 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 168 MLX5_FLOW_LAYER_INNER_L4) 169 170 /* Layer Masks. */ 171 #define MLX5_FLOW_LAYER_L2 \ 172 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 173 #define MLX5_FLOW_LAYER_L3_IPV4 \ 174 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 175 #define MLX5_FLOW_LAYER_L3_IPV6 \ 176 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 177 #define MLX5_FLOW_LAYER_L3 \ 178 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 179 #define MLX5_FLOW_LAYER_L4 \ 180 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 181 182 /* Actions */ 183 #define MLX5_FLOW_ACTION_DROP (1u << 0) 184 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 185 #define MLX5_FLOW_ACTION_RSS (1u << 2) 186 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 187 #define MLX5_FLOW_ACTION_MARK (1u << 4) 188 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 189 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 190 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 191 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 192 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 193 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 194 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 195 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 196 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 197 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 198 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 199 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 200 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 201 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 202 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 203 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 204 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 205 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 206 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 207 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 208 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 209 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 210 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 211 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 212 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 213 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 214 #define MLX5_FLOW_ACTION_METER (1ull << 31) 215 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 216 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 217 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 218 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 219 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 220 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 221 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 222 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39) 223 224 #define MLX5_FLOW_FATE_ACTIONS \ 225 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 226 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 227 MLX5_FLOW_ACTION_DEFAULT_MISS) 228 229 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 230 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 231 MLX5_FLOW_ACTION_JUMP) 232 233 234 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 235 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 236 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 237 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 238 MLX5_FLOW_ACTION_SET_TP_SRC | \ 239 MLX5_FLOW_ACTION_SET_TP_DST | \ 240 MLX5_FLOW_ACTION_SET_TTL | \ 241 MLX5_FLOW_ACTION_DEC_TTL | \ 242 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 243 MLX5_FLOW_ACTION_SET_MAC_DST | \ 244 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 245 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 246 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 247 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 248 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 249 MLX5_FLOW_ACTION_SET_TAG | \ 250 MLX5_FLOW_ACTION_MARK_EXT | \ 251 MLX5_FLOW_ACTION_SET_META | \ 252 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 253 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \ 254 MLX5_FLOW_ACTION_MODIFY_FIELD) 255 256 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 257 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 258 259 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 260 261 #ifndef IPPROTO_MPLS 262 #define IPPROTO_MPLS 137 263 #endif 264 265 /* UDP port number for MPLS */ 266 #define MLX5_UDP_PORT_MPLS 6635 267 268 /* UDP port numbers for VxLAN. */ 269 #define MLX5_UDP_PORT_VXLAN 4789 270 #define MLX5_UDP_PORT_VXLAN_GPE 4790 271 272 /* UDP port numbers for GENEVE. */ 273 #define MLX5_UDP_PORT_GENEVE 6081 274 275 /* Lowest priority indicator. */ 276 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1) 277 278 /* 279 * Max priority for ingress\egress flow groups 280 * greater than 0 and for any transfer flow group. 281 * From user configation: 0 - 21843. 282 */ 283 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1) 284 285 /* 286 * Number of sub priorities. 287 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 288 * matching on the NIC (firmware dependent) L4 most have the higher priority 289 * followed by L3 and ending with L2. 290 */ 291 #define MLX5_PRIORITY_MAP_L2 2 292 #define MLX5_PRIORITY_MAP_L3 1 293 #define MLX5_PRIORITY_MAP_L4 0 294 #define MLX5_PRIORITY_MAP_MAX 3 295 296 /* Valid layer type for IPV4 RSS. */ 297 #define MLX5_IPV4_LAYER_TYPES \ 298 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 299 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 300 ETH_RSS_NONFRAG_IPV4_OTHER) 301 302 /* IBV hash source bits for IPV4. */ 303 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 304 305 /* Valid layer type for IPV6 RSS. */ 306 #define MLX5_IPV6_LAYER_TYPES \ 307 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 308 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 309 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 310 311 /* IBV hash source bits for IPV6. */ 312 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 313 314 /* IBV hash bits for L3 SRC. */ 315 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 316 317 /* IBV hash bits for L3 DST. */ 318 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 319 320 /* IBV hash bits for TCP. */ 321 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 322 IBV_RX_HASH_DST_PORT_TCP) 323 324 /* IBV hash bits for UDP. */ 325 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 326 IBV_RX_HASH_DST_PORT_UDP) 327 328 /* IBV hash bits for L4 SRC. */ 329 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 330 IBV_RX_HASH_SRC_PORT_UDP) 331 332 /* IBV hash bits for L4 DST. */ 333 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 334 IBV_RX_HASH_DST_PORT_UDP) 335 336 /* Geneve header first 16Bit */ 337 #define MLX5_GENEVE_VER_MASK 0x3 338 #define MLX5_GENEVE_VER_SHIFT 14 339 #define MLX5_GENEVE_VER_VAL(a) \ 340 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 341 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 342 #define MLX5_GENEVE_OPTLEN_SHIFT 8 343 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 344 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 345 #define MLX5_GENEVE_OAMF_MASK 0x1 346 #define MLX5_GENEVE_OAMF_SHIFT 7 347 #define MLX5_GENEVE_OAMF_VAL(a) \ 348 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 349 #define MLX5_GENEVE_CRITO_MASK 0x1 350 #define MLX5_GENEVE_CRITO_SHIFT 6 351 #define MLX5_GENEVE_CRITO_VAL(a) \ 352 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 353 #define MLX5_GENEVE_RSVD_MASK 0x3F 354 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 355 /* 356 * The length of the Geneve options fields, expressed in four byte multiples, 357 * not including the eight byte fixed tunnel. 358 */ 359 #define MLX5_GENEVE_OPT_LEN_0 14 360 #define MLX5_GENEVE_OPT_LEN_1 63 361 362 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ 363 sizeof(struct rte_ipv4_hdr)) 364 /* GTP extension header flag. */ 365 #define MLX5_GTP_EXT_HEADER_FLAG 4 366 367 /* GTP extension header max PDU type value. */ 368 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15 369 370 /* GTP extension header PDU type shift. */ 371 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) 372 373 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 374 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 375 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 376 377 /* Specific item's fields can accept a range of values (using spec and last). */ 378 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 379 #define MLX5_ITEM_RANGE_ACCEPTED true 380 381 /* Software header modify action numbers of a flow. */ 382 #define MLX5_ACT_NUM_MDF_IPV4 1 383 #define MLX5_ACT_NUM_MDF_IPV6 4 384 #define MLX5_ACT_NUM_MDF_MAC 2 385 #define MLX5_ACT_NUM_MDF_VID 1 386 #define MLX5_ACT_NUM_MDF_PORT 2 387 #define MLX5_ACT_NUM_MDF_TTL 1 388 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 389 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 390 #define MLX5_ACT_NUM_MDF_TCPACK 1 391 #define MLX5_ACT_NUM_SET_REG 1 392 #define MLX5_ACT_NUM_SET_TAG 1 393 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 394 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 395 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 396 #define MLX5_ACT_NUM_SET_DSCP 1 397 398 /* Maximum number of fields to modify in MODIFY_FIELD */ 399 #define MLX5_ACT_MAX_MOD_FIELDS 5 400 401 enum mlx5_flow_drv_type { 402 MLX5_FLOW_TYPE_MIN, 403 MLX5_FLOW_TYPE_DV, 404 MLX5_FLOW_TYPE_VERBS, 405 MLX5_FLOW_TYPE_MAX, 406 }; 407 408 /* Fate action type. */ 409 enum mlx5_flow_fate_type { 410 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 411 MLX5_FLOW_FATE_QUEUE, 412 MLX5_FLOW_FATE_JUMP, 413 MLX5_FLOW_FATE_PORT_ID, 414 MLX5_FLOW_FATE_DROP, 415 MLX5_FLOW_FATE_DEFAULT_MISS, 416 MLX5_FLOW_FATE_SHARED_RSS, 417 MLX5_FLOW_FATE_MAX, 418 }; 419 420 /* Matcher PRM representation */ 421 struct mlx5_flow_dv_match_params { 422 size_t size; 423 /**< Size of match value. Do NOT split size and key! */ 424 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 425 /**< Matcher value. This value is used as the mask or as a key. */ 426 }; 427 428 /* Matcher structure. */ 429 struct mlx5_flow_dv_matcher { 430 struct mlx5_cache_entry entry; /**< Pointer to the next element. */ 431 struct mlx5_flow_tbl_resource *tbl; 432 /**< Pointer to the table(group) the matcher associated with. */ 433 void *matcher_object; /**< Pointer to DV matcher */ 434 uint16_t crc; /**< CRC of key. */ 435 uint16_t priority; /**< Priority of matcher. */ 436 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 437 }; 438 439 #define MLX5_ENCAP_MAX_LEN 132 440 441 /* Encap/decap resource structure. */ 442 struct mlx5_flow_dv_encap_decap_resource { 443 struct mlx5_hlist_entry entry; 444 /* Pointer to next element. */ 445 uint32_t refcnt; /**< Reference counter. */ 446 void *action; 447 /**< Encap/decap action object. */ 448 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 449 size_t size; 450 uint8_t reformat_type; 451 uint8_t ft_type; 452 uint64_t flags; /**< Flags for RDMA API. */ 453 uint32_t idx; /**< Index for the index memory pool. */ 454 }; 455 456 /* Tag resource structure. */ 457 struct mlx5_flow_dv_tag_resource { 458 struct mlx5_hlist_entry entry; 459 /**< hash list entry for tag resource, tag value as the key. */ 460 void *action; 461 /**< Tag action object. */ 462 uint32_t refcnt; /**< Reference counter. */ 463 uint32_t idx; /**< Index for the index memory pool. */ 464 uint32_t tag_id; /**< Tag ID. */ 465 }; 466 467 /* 468 * Number of modification commands. 469 * The maximal actions amount in FW is some constant, and it is 16 in the 470 * latest releases. In some old releases, it will be limited to 8. 471 * Since there is no interface to query the capacity, the maximal value should 472 * be used to allow PMD to create the flow. The validation will be done in the 473 * lower driver layer or FW. A failure will be returned if exceeds the maximal 474 * supported actions number on the root table. 475 * On non-root tables, there is no limitation, but 32 is enough right now. 476 */ 477 #define MLX5_MAX_MODIFY_NUM 32 478 #define MLX5_ROOT_TBL_MODIFY_NUM 16 479 480 /* Modify resource structure */ 481 struct mlx5_flow_dv_modify_hdr_resource { 482 struct mlx5_hlist_entry entry; 483 void *action; /**< Modify header action object. */ 484 /* Key area for hash list matching: */ 485 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 486 uint32_t actions_num; /**< Number of modification actions. */ 487 uint64_t flags; /**< Flags for RDMA API. */ 488 struct mlx5_modification_cmd actions[]; 489 /**< Modification actions. */ 490 }; 491 492 /* Modify resource key of the hash organization. */ 493 union mlx5_flow_modify_hdr_key { 494 struct { 495 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 496 uint32_t actions_num:5; /**< Number of modification actions. */ 497 uint32_t group:19; /**< Flow group id. */ 498 uint32_t cksum; /**< Actions check sum. */ 499 }; 500 uint64_t v64; /**< full 64bits value of key */ 501 }; 502 503 /* Jump action resource structure. */ 504 struct mlx5_flow_dv_jump_tbl_resource { 505 void *action; /**< Pointer to the rdma core action. */ 506 }; 507 508 /* Port ID resource structure. */ 509 struct mlx5_flow_dv_port_id_action_resource { 510 struct mlx5_cache_entry entry; 511 void *action; /**< Action object. */ 512 uint32_t port_id; /**< Port ID value. */ 513 uint32_t idx; /**< Indexed pool memory index. */ 514 }; 515 516 /* Push VLAN action resource structure */ 517 struct mlx5_flow_dv_push_vlan_action_resource { 518 struct mlx5_cache_entry entry; /* Cache entry. */ 519 void *action; /**< Action object. */ 520 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 521 rte_be32_t vlan_tag; /**< VLAN tag value. */ 522 uint32_t idx; /**< Indexed pool memory index. */ 523 }; 524 525 /* Metadata register copy table entry. */ 526 struct mlx5_flow_mreg_copy_resource { 527 /* 528 * Hash list entry for copy table. 529 * - Key is 32/64-bit MARK action ID. 530 * - MUST be the first entry. 531 */ 532 struct mlx5_hlist_entry hlist_ent; 533 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 534 /* List entry for device flows. */ 535 uint32_t idx; 536 uint32_t rix_flow; /* Built flow for copy. */ 537 uint32_t mark_id; 538 }; 539 540 /* Table tunnel parameter. */ 541 struct mlx5_flow_tbl_tunnel_prm { 542 const struct mlx5_flow_tunnel *tunnel; 543 uint32_t group_id; 544 bool external; 545 }; 546 547 /* Table data structure of the hash organization. */ 548 struct mlx5_flow_tbl_data_entry { 549 struct mlx5_hlist_entry entry; 550 /**< hash list entry, 64-bits key inside. */ 551 struct mlx5_flow_tbl_resource tbl; 552 /**< flow table resource. */ 553 struct mlx5_cache_list matchers; 554 /**< matchers' header associated with the flow table. */ 555 struct mlx5_flow_dv_jump_tbl_resource jump; 556 /**< jump resource, at most one for each table created. */ 557 uint32_t idx; /**< index for the indexed mempool. */ 558 /**< tunnel offload */ 559 const struct mlx5_flow_tunnel *tunnel; 560 uint32_t group_id; 561 uint32_t external:1; 562 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */ 563 uint32_t is_egress:1; /**< Egress table. */ 564 uint32_t is_transfer:1; /**< Transfer table. */ 565 uint32_t dummy:1; /**< DR table. */ 566 uint32_t reserve:27; /**< Reserved to future using. */ 567 uint32_t table_id; /**< Table ID. */ 568 }; 569 570 /* Sub rdma-core actions list. */ 571 struct mlx5_flow_sub_actions_list { 572 uint32_t actions_num; /**< Number of sample actions. */ 573 uint64_t action_flags; 574 void *dr_queue_action; 575 void *dr_tag_action; 576 void *dr_cnt_action; 577 void *dr_port_id_action; 578 void *dr_encap_action; 579 void *dr_jump_action; 580 }; 581 582 /* Sample sub-actions resource list. */ 583 struct mlx5_flow_sub_actions_idx { 584 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 585 uint32_t rix_tag; /**< Index to the tag action. */ 586 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 587 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 588 uint32_t rix_jump; /**< Index to the jump action resource. */ 589 }; 590 591 /* Sample action resource structure. */ 592 struct mlx5_flow_dv_sample_resource { 593 struct mlx5_cache_entry entry; /**< Cache entry. */ 594 union { 595 void *verbs_action; /**< Verbs sample action object. */ 596 void **sub_actions; /**< Sample sub-action array. */ 597 }; 598 struct rte_eth_dev *dev; /**< Device registers the action. */ 599 uint32_t idx; /** Sample object index. */ 600 uint8_t ft_type; /** Flow Table Type */ 601 uint32_t ft_id; /** Flow Table Level */ 602 uint32_t ratio; /** Sample Ratio */ 603 uint64_t set_action; /** Restore reg_c0 value */ 604 void *normal_path_tbl; /** Flow Table pointer */ 605 struct mlx5_flow_sub_actions_idx sample_idx; 606 /**< Action index resources. */ 607 struct mlx5_flow_sub_actions_list sample_act; 608 /**< Action resources. */ 609 }; 610 611 #define MLX5_MAX_DEST_NUM 2 612 613 /* Destination array action resource structure. */ 614 struct mlx5_flow_dv_dest_array_resource { 615 struct mlx5_cache_entry entry; /**< Cache entry. */ 616 uint32_t idx; /** Destination array action object index. */ 617 uint8_t ft_type; /** Flow Table Type */ 618 uint8_t num_of_dest; /**< Number of destination actions. */ 619 struct rte_eth_dev *dev; /**< Device registers the action. */ 620 void *action; /**< Pointer to the rdma core action. */ 621 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 622 /**< Action index resources. */ 623 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 624 /**< Action resources. */ 625 }; 626 627 /* PMD flow priority for tunnel */ 628 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 629 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 630 631 632 /** Device flow handle structure for DV mode only. */ 633 struct mlx5_flow_handle_dv { 634 /* Flow DV api: */ 635 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 636 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 637 /**< Pointer to modify header resource in cache. */ 638 uint32_t rix_encap_decap; 639 /**< Index to encap/decap resource in cache. */ 640 uint32_t rix_push_vlan; 641 /**< Index to push VLAN action resource in cache. */ 642 uint32_t rix_tag; 643 /**< Index to the tag action. */ 644 uint32_t rix_sample; 645 /**< Index to sample action resource in cache. */ 646 uint32_t rix_dest_array; 647 /**< Index to destination array resource in cache. */ 648 } __rte_packed; 649 650 /** Device flow handle structure: used both for creating & destroying. */ 651 struct mlx5_flow_handle { 652 SILIST_ENTRY(uint32_t)next; 653 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 654 /**< Index to next device flow handle. */ 655 uint64_t layers; 656 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 657 void *drv_flow; /**< pointer to driver flow object. */ 658 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */ 659 uint32_t mark:1; /**< Metadate rxq mark flag. */ 660 uint32_t fate_action:3; /**< Fate action type. */ 661 union { 662 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 663 uint32_t rix_jump; /**< Index to the jump action resource. */ 664 uint32_t rix_port_id_action; 665 /**< Index to port ID action resource. */ 666 uint32_t rix_fate; 667 /**< Generic value indicates the fate action. */ 668 uint32_t rix_default_fate; 669 /**< Indicates default miss fate action. */ 670 uint32_t rix_srss; 671 /**< Indicates shared RSS fate action. */ 672 }; 673 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 674 struct mlx5_flow_handle_dv dvh; 675 #endif 676 } __rte_packed; 677 678 /* 679 * Size for Verbs device flow handle structure only. Do not use the DV only 680 * structure in Verbs. No DV flows attributes will be accessed. 681 * Macro offsetof() could also be used here. 682 */ 683 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 684 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 685 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 686 #else 687 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 688 #endif 689 690 /* 691 * Max number of actions per DV flow. 692 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 693 * in rdma-core file providers/mlx5/verbs.c. 694 */ 695 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 696 697 /** Device flow structure only for DV flow creation. */ 698 struct mlx5_flow_dv_workspace { 699 uint32_t group; /**< The group index. */ 700 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 701 int actions_n; /**< number of actions. */ 702 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 703 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 704 /**< Pointer to encap/decap resource in cache. */ 705 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 706 /**< Pointer to push VLAN action resource in cache. */ 707 struct mlx5_flow_dv_tag_resource *tag_resource; 708 /**< pointer to the tag action. */ 709 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 710 /**< Pointer to port ID action resource. */ 711 struct mlx5_flow_dv_jump_tbl_resource *jump; 712 /**< Pointer to the jump action resource. */ 713 struct mlx5_flow_dv_match_params value; 714 /**< Holds the value that the packet is compared to. */ 715 struct mlx5_flow_dv_sample_resource *sample_res; 716 /**< Pointer to the sample action resource. */ 717 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 718 /**< Pointer to the destination array resource. */ 719 }; 720 721 #ifdef HAVE_INFINIBAND_VERBS_H 722 /* 723 * Maximal Verbs flow specifications & actions size. 724 * Some elements are mutually exclusive, but enough space should be allocated. 725 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 726 * 2. One tunnel header (exception: GRE + MPLS), 727 * SPEC length: GRE == tunnel. 728 * Actions: 1. 1 Mark OR Flag. 729 * 2. 1 Drop (if any). 730 * 3. No limitation for counters, but it makes no sense to support too 731 * many counters in a single device flow. 732 */ 733 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 734 #define MLX5_VERBS_MAX_SPEC_SIZE \ 735 ( \ 736 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 737 sizeof(struct ibv_flow_spec_ipv6) + \ 738 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 739 sizeof(struct ibv_flow_spec_gre) + \ 740 sizeof(struct ibv_flow_spec_mpls)) \ 741 ) 742 #else 743 #define MLX5_VERBS_MAX_SPEC_SIZE \ 744 ( \ 745 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 746 sizeof(struct ibv_flow_spec_ipv6) + \ 747 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 748 sizeof(struct ibv_flow_spec_tunnel)) \ 749 ) 750 #endif 751 752 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 753 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 754 #define MLX5_VERBS_MAX_ACT_SIZE \ 755 ( \ 756 sizeof(struct ibv_flow_spec_action_tag) + \ 757 sizeof(struct ibv_flow_spec_action_drop) + \ 758 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 759 ) 760 #else 761 #define MLX5_VERBS_MAX_ACT_SIZE \ 762 ( \ 763 sizeof(struct ibv_flow_spec_action_tag) + \ 764 sizeof(struct ibv_flow_spec_action_drop) \ 765 ) 766 #endif 767 768 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 769 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 770 771 /** Device flow structure only for Verbs flow creation. */ 772 struct mlx5_flow_verbs_workspace { 773 unsigned int size; /**< Size of the attribute. */ 774 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 775 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 776 /**< Specifications & actions buffer of verbs flow. */ 777 }; 778 #endif /* HAVE_INFINIBAND_VERBS_H */ 779 780 #define MLX5_SCALE_FLOW_GROUP_BIT 0 781 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1 782 783 /** Maximal number of device sub-flows supported. */ 784 #define MLX5_NUM_MAX_DEV_FLOWS 32 785 786 /** Device flow structure. */ 787 __extension__ 788 struct mlx5_flow { 789 struct rte_flow *flow; /**< Pointer to the main flow. */ 790 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 791 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 792 uint64_t act_flags; 793 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 794 bool external; /**< true if the flow is created external to PMD. */ 795 uint8_t ingress:1; /**< 1 if the flow is ingress. */ 796 uint8_t skip_scale:2; 797 /** 798 * Each Bit be set to 1 if Skip the scale the flow group with factor. 799 * If bit0 be set to 1, then skip the scale the original flow group; 800 * If bit1 be set to 1, then skip the scale the jump flow group if 801 * having jump action. 802 * 00: Enable scale in a flow, default value. 803 * 01: Skip scale the flow group with factor, enable scale the group 804 * of jump action. 805 * 10: Enable scale the group with factor, skip scale the group of 806 * jump action. 807 * 11: Skip scale the table with factor both for flow group and jump 808 * group. 809 */ 810 union { 811 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 812 struct mlx5_flow_dv_workspace dv; 813 #endif 814 #ifdef HAVE_INFINIBAND_VERBS_H 815 struct mlx5_flow_verbs_workspace verbs; 816 #endif 817 }; 818 struct mlx5_flow_handle *handle; 819 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 820 const struct mlx5_flow_tunnel *tunnel; 821 }; 822 823 /* Flow meter state. */ 824 #define MLX5_FLOW_METER_DISABLE 0 825 #define MLX5_FLOW_METER_ENABLE 1 826 827 #define MLX5_MAN_WIDTH 8 828 /* Modify this value if enum rte_mtr_color changes. */ 829 #define RTE_MTR_DROPPED RTE_COLORS 830 831 /* Meter policer statistics */ 832 struct mlx5_flow_policer_stats { 833 uint32_t cnt[RTE_COLORS + 1]; 834 /**< Color counter, extra for drop. */ 835 uint64_t stats_mask; 836 /**< Statistics mask for the colors. */ 837 }; 838 839 /* Meter table structure. */ 840 struct mlx5_meter_domain_info { 841 struct mlx5_flow_tbl_resource *tbl; 842 /**< Meter table. */ 843 struct mlx5_flow_tbl_resource *sfx_tbl; 844 /**< Meter suffix table. */ 845 void *any_matcher; 846 /**< Meter color not match default criteria. */ 847 void *color_matcher; 848 /**< Meter color match criteria. */ 849 void *jump_actn; 850 /**< Meter match action. */ 851 void *policer_rules[RTE_MTR_DROPPED + 1]; 852 /**< Meter policer for the match. */ 853 }; 854 855 /* Meter table set for TX RX FDB. */ 856 struct mlx5_meter_domains_infos { 857 uint32_t ref_cnt; 858 /**< Table user count. */ 859 struct mlx5_meter_domain_info egress; 860 /**< TX meter table. */ 861 struct mlx5_meter_domain_info ingress; 862 /**< RX meter table. */ 863 struct mlx5_meter_domain_info transfer; 864 /**< FDB meter table. */ 865 void *drop_actn; 866 /**< Drop action as not matched. */ 867 void *count_actns[RTE_MTR_DROPPED + 1]; 868 /**< Counters for match and unmatched statistics. */ 869 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)]; 870 /**< Flow meter parameter. */ 871 size_t fmp_size; 872 /**< Flow meter parameter size. */ 873 void *meter_action; 874 /**< Flow meter action. */ 875 }; 876 877 /* Meter parameter structure. */ 878 struct mlx5_flow_meter { 879 TAILQ_ENTRY(mlx5_flow_meter) next; 880 /**< Pointer to the next flow meter structure. */ 881 uint32_t idx; /* Index to meter object. */ 882 uint32_t meter_id; 883 /**< Meter id. */ 884 struct mlx5_flow_meter_profile *profile; 885 /**< Meter profile parameters. */ 886 887 rte_spinlock_t sl; /**< Meter action spinlock. */ 888 889 /** Policer actions (per meter output color). */ 890 enum rte_mtr_policer_action action[RTE_COLORS]; 891 892 /** Set of stats counters to be enabled. 893 * @see enum rte_mtr_stats_type 894 */ 895 uint64_t stats_mask; 896 897 /**< Rule applies to ingress traffic. */ 898 uint32_t ingress:1; 899 900 /**< Rule applies to egress traffic. */ 901 uint32_t egress:1; 902 /** 903 * Instead of simply matching the properties of traffic as it would 904 * appear on a given DPDK port ID, enabling this attribute transfers 905 * a flow rule to the lowest possible level of any device endpoints 906 * found in the pattern. 907 * 908 * When supported, this effectively enables an application to 909 * re-route traffic not necessarily intended for it (e.g. coming 910 * from or addressed to different physical ports, VFs or 911 * applications) at the device level. 912 * 913 * It complements the behavior of some pattern items such as 914 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 915 * 916 * When transferring flow rules, ingress and egress attributes keep 917 * their original meaning, as if processing traffic emitted or 918 * received by the application. 919 */ 920 uint32_t transfer:1; 921 struct mlx5_meter_domains_infos *mfts; 922 /**< Flow table created for this meter. */ 923 struct mlx5_flow_policer_stats policer_stats; 924 /**< Meter policer statistics. */ 925 uint32_t ref_cnt; 926 /**< Use count. */ 927 uint32_t active_state:1; 928 /**< Meter state. */ 929 uint32_t shared:1; 930 /**< Meter shared or not. */ 931 }; 932 933 /* RFC2697 parameter structure. */ 934 struct mlx5_flow_meter_srtcm_rfc2697_prm { 935 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */ 936 uint32_t cbs_exponent:5; 937 uint32_t cbs_mantissa:8; 938 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */ 939 uint32_t cir_exponent:5; 940 uint32_t cir_mantissa:8; 941 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */ 942 uint32_t ebs_exponent:5; 943 uint32_t ebs_mantissa:8; 944 }; 945 946 /* Flow meter profile structure. */ 947 struct mlx5_flow_meter_profile { 948 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 949 /**< Pointer to the next flow meter structure. */ 950 uint32_t meter_profile_id; /**< Profile id. */ 951 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 952 union { 953 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 954 /**< srtcm_rfc2697 struct. */ 955 }; 956 uint32_t ref_cnt; /**< Use count. */ 957 }; 958 959 #define MLX5_MAX_TUNNELS 256 960 #define MLX5_TNL_MISS_RULE_PRIORITY 3 961 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 962 963 /* 964 * When tunnel offload is active, all JUMP group ids are converted 965 * using the same method. That conversion is applied both to tunnel and 966 * regular rule types. 967 * Group ids used in tunnel rules are relative to it's tunnel (!). 968 * Application can create number of steer rules, using the same 969 * tunnel, with different group id in each rule. 970 * Each tunnel stores its groups internally in PMD tunnel object. 971 * Groups used in regular rules do not belong to any tunnel and are stored 972 * in tunnel hub. 973 */ 974 975 struct mlx5_flow_tunnel { 976 LIST_ENTRY(mlx5_flow_tunnel) chain; 977 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 978 uint32_t tunnel_id; /** unique tunnel ID */ 979 uint32_t refctn; 980 struct rte_flow_action action; 981 struct rte_flow_item item; 982 struct mlx5_hlist *groups; /** tunnel groups */ 983 }; 984 985 /** PMD tunnel related context */ 986 struct mlx5_flow_tunnel_hub { 987 /* Tunnels list 988 * Access to the list MUST be MT protected 989 */ 990 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 991 /* protect access to the tunnels list */ 992 rte_spinlock_t sl; 993 struct mlx5_hlist *groups; /** non tunnel groups */ 994 }; 995 996 /* convert jump group to flow table ID in tunnel rules */ 997 struct tunnel_tbl_entry { 998 struct mlx5_hlist_entry hash; 999 uint32_t flow_table; 1000 uint32_t tunnel_id; 1001 uint32_t group; 1002 }; 1003 1004 static inline uint32_t 1005 tunnel_id_to_flow_tbl(uint32_t id) 1006 { 1007 return id | (1u << 16); 1008 } 1009 1010 static inline uint32_t 1011 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 1012 { 1013 return flow_tbl & ~(1u << 16); 1014 } 1015 1016 union tunnel_tbl_key { 1017 uint64_t val; 1018 struct { 1019 uint32_t tunnel_id; 1020 uint32_t group; 1021 }; 1022 }; 1023 1024 static inline struct mlx5_flow_tunnel_hub * 1025 mlx5_tunnel_hub(struct rte_eth_dev *dev) 1026 { 1027 struct mlx5_priv *priv = dev->data->dev_private; 1028 return priv->sh->tunnel_hub; 1029 } 1030 1031 static inline bool 1032 is_tunnel_offload_active(struct rte_eth_dev *dev) 1033 { 1034 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1035 struct mlx5_priv *priv = dev->data->dev_private; 1036 return !!priv->config.dv_miss_info; 1037 #else 1038 RTE_SET_USED(dev); 1039 return false; 1040 #endif 1041 } 1042 1043 static inline bool 1044 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev, 1045 __rte_unused const struct rte_flow_attr *attr, 1046 __rte_unused const struct rte_flow_item items[], 1047 __rte_unused const struct rte_flow_action actions[]) 1048 { 1049 return (items[0].type == (typeof(items[0].type)) 1050 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL); 1051 } 1052 1053 static inline bool 1054 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev, 1055 __rte_unused const struct rte_flow_attr *attr, 1056 __rte_unused const struct rte_flow_item items[], 1057 __rte_unused const struct rte_flow_action actions[]) 1058 { 1059 return (actions[0].type == (typeof(actions[0].type)) 1060 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET); 1061 } 1062 1063 static inline const struct mlx5_flow_tunnel * 1064 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 1065 { 1066 return actions[0].conf; 1067 } 1068 1069 static inline const struct mlx5_flow_tunnel * 1070 flow_items_to_tunnel(const struct rte_flow_item items[]) 1071 { 1072 return items[0].spec; 1073 } 1074 1075 /* Flow structure. */ 1076 struct rte_flow { 1077 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 1078 uint32_t dev_handles; 1079 /**< Device flow handles that are part of the flow. */ 1080 uint32_t drv_type:2; /**< Driver type. */ 1081 uint32_t tunnel:1; 1082 uint32_t meter:16; /**< Holds flow meter id. */ 1083 uint32_t rix_mreg_copy; 1084 /**< Index to metadata register copy table resource. */ 1085 uint32_t counter; /**< Holds flow counter. */ 1086 uint32_t tunnel_id; /**< Tunnel id */ 1087 uint32_t age; /**< Holds ASO age bit index. */ 1088 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ 1089 } __rte_packed; 1090 1091 /* 1092 * Define list of valid combinations of RX Hash fields 1093 * (see enum ibv_rx_hash_fields). 1094 */ 1095 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 1096 #define MLX5_RSS_HASH_IPV4_TCP \ 1097 (MLX5_RSS_HASH_IPV4 | \ 1098 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1099 #define MLX5_RSS_HASH_IPV4_UDP \ 1100 (MLX5_RSS_HASH_IPV4 | \ 1101 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1102 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 1103 #define MLX5_RSS_HASH_IPV6_TCP \ 1104 (MLX5_RSS_HASH_IPV6 | \ 1105 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 1106 #define MLX5_RSS_HASH_IPV6_UDP \ 1107 (MLX5_RSS_HASH_IPV6 | \ 1108 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 1109 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4 1110 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4 1111 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6 1112 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6 1113 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \ 1114 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP) 1115 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \ 1116 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP) 1117 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \ 1118 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP) 1119 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \ 1120 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP) 1121 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \ 1122 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP) 1123 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \ 1124 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP) 1125 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \ 1126 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP) 1127 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \ 1128 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) 1129 #define MLX5_RSS_HASH_NONE 0ULL 1130 1131 /* array of valid combinations of RX Hash fields for RSS */ 1132 static const uint64_t mlx5_rss_hash_fields[] = { 1133 MLX5_RSS_HASH_IPV4, 1134 MLX5_RSS_HASH_IPV4_TCP, 1135 MLX5_RSS_HASH_IPV4_UDP, 1136 MLX5_RSS_HASH_IPV6, 1137 MLX5_RSS_HASH_IPV6_TCP, 1138 MLX5_RSS_HASH_IPV6_UDP, 1139 MLX5_RSS_HASH_NONE, 1140 }; 1141 1142 /* Shared RSS action structure */ 1143 struct mlx5_shared_action_rss { 1144 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */ 1145 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1146 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1147 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1148 struct mlx5_ind_table_obj *ind_tbl; 1149 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */ 1150 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1151 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1152 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */ 1153 }; 1154 1155 struct rte_flow_shared_action { 1156 uint32_t id; 1157 }; 1158 1159 /* Thread specific flow workspace intermediate data. */ 1160 struct mlx5_flow_workspace { 1161 /* If creating another flow in same thread, push new as stack. */ 1162 struct mlx5_flow_workspace *prev; 1163 struct mlx5_flow_workspace *next; 1164 uint32_t inuse; /* can't create new flow with current. */ 1165 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1166 struct mlx5_flow_rss_desc rss_desc; 1167 uint32_t rssq_num; /* Allocated queue num in rss_desc. */ 1168 uint32_t flow_idx; /* Intermediate device flow index. */ 1169 }; 1170 1171 struct mlx5_flow_split_info { 1172 bool external; 1173 /**< True if flow is created by request external to PMD. */ 1174 uint8_t skip_scale; /**< Skip the scale the table with factor. */ 1175 uint32_t flow_idx; /**< This memory pool index to the flow. */ 1176 uint32_t prefix_mark; /**< Prefix subflow mark flag. */ 1177 uint64_t prefix_layers; /**< Prefix subflow layers. */ 1178 }; 1179 1180 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1181 const struct rte_flow_attr *attr, 1182 const struct rte_flow_item items[], 1183 const struct rte_flow_action actions[], 1184 bool external, 1185 int hairpin, 1186 struct rte_flow_error *error); 1187 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1188 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1189 const struct rte_flow_item items[], 1190 const struct rte_flow_action actions[], struct rte_flow_error *error); 1191 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1192 struct mlx5_flow *dev_flow, 1193 const struct rte_flow_attr *attr, 1194 const struct rte_flow_item items[], 1195 const struct rte_flow_action actions[], 1196 struct rte_flow_error *error); 1197 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1198 struct rte_flow_error *error); 1199 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1200 struct rte_flow *flow); 1201 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1202 struct rte_flow *flow); 1203 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1204 struct rte_flow *flow, 1205 const struct rte_flow_action *actions, 1206 void *data, 1207 struct rte_flow_error *error); 1208 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 1209 (struct rte_eth_dev *dev, 1210 const struct mlx5_flow_meter *fm); 1211 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1212 struct mlx5_meter_domains_infos *tbls); 1213 typedef int (*mlx5_flow_create_policer_rules_t) 1214 (struct rte_eth_dev *dev, 1215 struct mlx5_flow_meter *fm, 1216 const struct rte_flow_attr *attr); 1217 typedef int (*mlx5_flow_destroy_policer_rules_t) 1218 (struct rte_eth_dev *dev, 1219 const struct mlx5_flow_meter *fm, 1220 const struct rte_flow_attr *attr); 1221 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1222 (struct rte_eth_dev *dev); 1223 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1224 uint32_t cnt); 1225 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1226 uint32_t cnt, 1227 bool clear, uint64_t *pkts, 1228 uint64_t *bytes); 1229 typedef int (*mlx5_flow_get_aged_flows_t) 1230 (struct rte_eth_dev *dev, 1231 void **context, 1232 uint32_t nb_contexts, 1233 struct rte_flow_error *error); 1234 typedef int (*mlx5_flow_action_validate_t) 1235 (struct rte_eth_dev *dev, 1236 const struct rte_flow_shared_action_conf *conf, 1237 const struct rte_flow_action *action, 1238 struct rte_flow_error *error); 1239 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t) 1240 (struct rte_eth_dev *dev, 1241 const struct rte_flow_shared_action_conf *conf, 1242 const struct rte_flow_action *action, 1243 struct rte_flow_error *error); 1244 typedef int (*mlx5_flow_action_destroy_t) 1245 (struct rte_eth_dev *dev, 1246 struct rte_flow_shared_action *action, 1247 struct rte_flow_error *error); 1248 typedef int (*mlx5_flow_action_update_t) 1249 (struct rte_eth_dev *dev, 1250 struct rte_flow_shared_action *action, 1251 const void *action_conf, 1252 struct rte_flow_error *error); 1253 typedef int (*mlx5_flow_action_query_t) 1254 (struct rte_eth_dev *dev, 1255 const struct rte_flow_shared_action *action, 1256 void *data, 1257 struct rte_flow_error *error); 1258 typedef int (*mlx5_flow_sync_domain_t) 1259 (struct rte_eth_dev *dev, 1260 uint32_t domains, 1261 uint32_t flags); 1262 1263 struct mlx5_flow_driver_ops { 1264 mlx5_flow_validate_t validate; 1265 mlx5_flow_prepare_t prepare; 1266 mlx5_flow_translate_t translate; 1267 mlx5_flow_apply_t apply; 1268 mlx5_flow_remove_t remove; 1269 mlx5_flow_destroy_t destroy; 1270 mlx5_flow_query_t query; 1271 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1272 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1273 mlx5_flow_create_policer_rules_t create_policer_rules; 1274 mlx5_flow_destroy_policer_rules_t destroy_policer_rules; 1275 mlx5_flow_counter_alloc_t counter_alloc; 1276 mlx5_flow_counter_free_t counter_free; 1277 mlx5_flow_counter_query_t counter_query; 1278 mlx5_flow_get_aged_flows_t get_aged_flows; 1279 mlx5_flow_action_validate_t action_validate; 1280 mlx5_flow_action_create_t action_create; 1281 mlx5_flow_action_destroy_t action_destroy; 1282 mlx5_flow_action_update_t action_update; 1283 mlx5_flow_action_query_t action_query; 1284 mlx5_flow_sync_domain_t sync_domain; 1285 }; 1286 1287 /* mlx5_flow.c */ 1288 1289 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1290 __extension__ 1291 struct flow_grp_info { 1292 uint64_t external:1; 1293 uint64_t transfer:1; 1294 uint64_t fdb_def_rule:1; 1295 /* force standard group translation */ 1296 uint64_t std_tbl_fix:1; 1297 uint64_t skip_scale:2; 1298 }; 1299 1300 static inline bool 1301 tunnel_use_standard_attr_group_translate 1302 (struct rte_eth_dev *dev, 1303 const struct mlx5_flow_tunnel *tunnel, 1304 const struct rte_flow_attr *attr, 1305 const struct rte_flow_item items[], 1306 const struct rte_flow_action actions[]) 1307 { 1308 bool verdict; 1309 1310 if (!is_tunnel_offload_active(dev)) 1311 /* no tunnel offload API */ 1312 verdict = true; 1313 else if (tunnel) { 1314 /* 1315 * OvS will use jump to group 0 in tunnel steer rule. 1316 * If tunnel steer rule starts from group 0 (attr.group == 0) 1317 * that 0 group must be translated with standard method. 1318 * attr.group == 0 in tunnel match rule translated with tunnel 1319 * method 1320 */ 1321 verdict = !attr->group && 1322 is_flow_tunnel_steer_rule(dev, attr, items, actions); 1323 } else { 1324 /* 1325 * non-tunnel group translation uses standard method for 1326 * root group only: attr.group == 0 1327 */ 1328 verdict = !attr->group; 1329 } 1330 1331 return verdict; 1332 } 1333 1334 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1335 const struct mlx5_flow_tunnel *tunnel, 1336 uint32_t group, uint32_t *table, 1337 const struct flow_grp_info *flags, 1338 struct rte_flow_error *error); 1339 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1340 int tunnel, uint64_t layer_types, 1341 uint64_t hash_fields); 1342 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1343 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1344 uint32_t subpriority); 1345 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1346 const struct rte_flow_attr *attr); 1347 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1348 const struct rte_flow_attr *attr, 1349 uint32_t subpriority); 1350 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1351 enum mlx5_feature_name feature, 1352 uint32_t id, 1353 struct rte_flow_error *error); 1354 const struct rte_flow_action *mlx5_flow_find_action 1355 (const struct rte_flow_action *actions, 1356 enum rte_flow_action_type action); 1357 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1358 const struct rte_flow_action *action, 1359 struct rte_flow_error *error); 1360 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1361 const struct rte_flow_attr *attr, 1362 struct rte_flow_error *error); 1363 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1364 const struct rte_flow_attr *attr, 1365 struct rte_flow_error *error); 1366 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1367 const struct rte_flow_attr *attr, 1368 struct rte_flow_error *error); 1369 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1370 uint64_t action_flags, 1371 const struct rte_flow_attr *attr, 1372 struct rte_flow_error *error); 1373 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1374 uint64_t action_flags, 1375 struct rte_eth_dev *dev, 1376 const struct rte_flow_attr *attr, 1377 struct rte_flow_error *error); 1378 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1379 uint64_t action_flags, 1380 struct rte_eth_dev *dev, 1381 const struct rte_flow_attr *attr, 1382 uint64_t item_flags, 1383 struct rte_flow_error *error); 1384 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1385 const struct rte_flow_attr *attr, 1386 struct rte_flow_error *error); 1387 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1388 const struct rte_flow_attr *attributes, 1389 struct rte_flow_error *error); 1390 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1391 const uint8_t *mask, 1392 const uint8_t *nic_mask, 1393 unsigned int size, 1394 bool range_accepted, 1395 struct rte_flow_error *error); 1396 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1397 uint64_t item_flags, bool ext_vlan_sup, 1398 struct rte_flow_error *error); 1399 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1400 uint64_t item_flags, 1401 uint8_t target_protocol, 1402 struct rte_flow_error *error); 1403 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1404 uint64_t item_flags, 1405 const struct rte_flow_item *gre_item, 1406 struct rte_flow_error *error); 1407 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1408 uint64_t item_flags, 1409 uint64_t last_item, 1410 uint16_t ether_type, 1411 const struct rte_flow_item_ipv4 *acc_mask, 1412 bool range_accepted, 1413 struct rte_flow_error *error); 1414 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1415 uint64_t item_flags, 1416 uint64_t last_item, 1417 uint16_t ether_type, 1418 const struct rte_flow_item_ipv6 *acc_mask, 1419 struct rte_flow_error *error); 1420 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1421 const struct rte_flow_item *item, 1422 uint64_t item_flags, 1423 uint64_t prev_layer, 1424 struct rte_flow_error *error); 1425 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1426 uint64_t item_flags, 1427 uint8_t target_protocol, 1428 const struct rte_flow_item_tcp *flow_mask, 1429 struct rte_flow_error *error); 1430 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1431 uint64_t item_flags, 1432 uint8_t target_protocol, 1433 struct rte_flow_error *error); 1434 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1435 uint64_t item_flags, 1436 struct rte_eth_dev *dev, 1437 struct rte_flow_error *error); 1438 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1439 uint64_t item_flags, 1440 struct rte_flow_error *error); 1441 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1442 uint64_t item_flags, 1443 struct rte_eth_dev *dev, 1444 struct rte_flow_error *error); 1445 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1446 uint64_t item_flags, 1447 uint8_t target_protocol, 1448 struct rte_flow_error *error); 1449 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1450 uint64_t item_flags, 1451 uint8_t target_protocol, 1452 struct rte_flow_error *error); 1453 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1454 uint64_t item_flags, 1455 uint8_t target_protocol, 1456 struct rte_flow_error *error); 1457 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1458 uint64_t item_flags, 1459 struct rte_eth_dev *dev, 1460 struct rte_flow_error *error); 1461 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 1462 uint64_t last_item, 1463 const struct rte_flow_item *geneve_item, 1464 struct rte_eth_dev *dev, 1465 struct rte_flow_error *error); 1466 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1467 uint64_t item_flags, 1468 uint64_t last_item, 1469 uint16_t ether_type, 1470 const struct rte_flow_item_ecpri *acc_mask, 1471 struct rte_flow_error *error); 1472 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 1473 (struct rte_eth_dev *dev, 1474 const struct mlx5_flow_meter *fm); 1475 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1476 struct mlx5_meter_domains_infos *tbl); 1477 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 1478 struct mlx5_flow_meter *fm, 1479 const struct rte_flow_attr *attr); 1480 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 1481 struct mlx5_flow_meter *fm, 1482 const struct rte_flow_attr *attr); 1483 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1484 struct rte_mtr_error *error); 1485 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1486 int mlx5_shared_action_flush(struct rte_eth_dev *dev); 1487 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1488 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1489 1490 /* Hash list callbacks for flow tables: */ 1491 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list, 1492 uint64_t key, void *entry_ctx); 1493 int flow_dv_tbl_match_cb(struct mlx5_hlist *list, 1494 struct mlx5_hlist_entry *entry, uint64_t key, 1495 void *cb_ctx); 1496 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list, 1497 struct mlx5_hlist_entry *entry); 1498 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1499 uint32_t table_id, uint8_t egress, uint8_t transfer, 1500 bool external, const struct mlx5_flow_tunnel *tunnel, 1501 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error); 1502 1503 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list, 1504 uint64_t key, void *cb_ctx); 1505 int flow_dv_tag_match_cb(struct mlx5_hlist *list, 1506 struct mlx5_hlist_entry *entry, uint64_t key, 1507 void *cb_ctx); 1508 void flow_dv_tag_remove_cb(struct mlx5_hlist *list, 1509 struct mlx5_hlist_entry *entry); 1510 1511 int flow_dv_modify_match_cb(struct mlx5_hlist *list, 1512 struct mlx5_hlist_entry *entry, 1513 uint64_t key, void *cb_ctx); 1514 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list, 1515 uint64_t key, void *ctx); 1516 void flow_dv_modify_remove_cb(struct mlx5_hlist *list, 1517 struct mlx5_hlist_entry *entry); 1518 1519 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list, 1520 uint64_t key, void *ctx); 1521 int flow_dv_mreg_match_cb(struct mlx5_hlist *list, 1522 struct mlx5_hlist_entry *entry, uint64_t key, 1523 void *cb_ctx); 1524 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list, 1525 struct mlx5_hlist_entry *entry); 1526 1527 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list, 1528 struct mlx5_hlist_entry *entry, 1529 uint64_t key, void *cb_ctx); 1530 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list, 1531 uint64_t key, void *cb_ctx); 1532 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list, 1533 struct mlx5_hlist_entry *entry); 1534 1535 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list, 1536 struct mlx5_cache_entry *entry, void *ctx); 1537 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list, 1538 struct mlx5_cache_entry *entry, void *ctx); 1539 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list, 1540 struct mlx5_cache_entry *entry); 1541 1542 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list, 1543 struct mlx5_cache_entry *entry, void *cb_ctx); 1544 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list, 1545 struct mlx5_cache_entry *entry, void *cb_ctx); 1546 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list, 1547 struct mlx5_cache_entry *entry); 1548 1549 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list, 1550 struct mlx5_cache_entry *entry, void *cb_ctx); 1551 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb 1552 (struct mlx5_cache_list *list, 1553 struct mlx5_cache_entry *entry, void *cb_ctx); 1554 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list, 1555 struct mlx5_cache_entry *entry); 1556 1557 int flow_dv_sample_match_cb(struct mlx5_cache_list *list, 1558 struct mlx5_cache_entry *entry, void *cb_ctx); 1559 struct mlx5_cache_entry *flow_dv_sample_create_cb 1560 (struct mlx5_cache_list *list, 1561 struct mlx5_cache_entry *entry, void *cb_ctx); 1562 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list, 1563 struct mlx5_cache_entry *entry); 1564 1565 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list, 1566 struct mlx5_cache_entry *entry, void *cb_ctx); 1567 struct mlx5_cache_entry *flow_dv_dest_array_create_cb 1568 (struct mlx5_cache_list *list, 1569 struct mlx5_cache_entry *entry, void *cb_ctx); 1570 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list, 1571 struct mlx5_cache_entry *entry); 1572 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, 1573 uint32_t age_idx); 1574 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev, 1575 const struct rte_flow_item *item, 1576 struct rte_flow_error *error); 1577 1578 void flow_release_workspace(void *data); 1579 int mlx5_flow_os_init_workspace_once(void); 1580 void *mlx5_flow_os_get_specific_workspace(void); 1581 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data); 1582 void mlx5_flow_os_release_workspace(void); 1583 1584 1585 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1586