1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_FLOW_H_ 6 #define RTE_PMD_MLX5_FLOW_H_ 7 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <sys/queue.h> 12 13 #include <rte_alarm.h> 14 #include <rte_mtr.h> 15 16 #include <mlx5_glue.h> 17 #include <mlx5_prm.h> 18 19 #include "mlx5.h" 20 21 /* Private rte flow items. */ 22 enum mlx5_rte_flow_item_type { 23 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, 24 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 25 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 26 MLX5_RTE_FLOW_ITEM_TYPE_VLAN, 27 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL, 28 }; 29 30 /* Private (internal) rte flow actions. */ 31 enum mlx5_rte_flow_action_type { 32 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN, 33 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 34 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 35 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 36 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 37 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET, 38 MLX5_RTE_FLOW_ACTION_TYPE_AGE, 39 }; 40 41 #define MLX5_INDIRECT_ACTION_TYPE_OFFSET 30 42 43 enum { 44 MLX5_INDIRECT_ACTION_TYPE_RSS, 45 MLX5_INDIRECT_ACTION_TYPE_AGE, 46 }; 47 48 /* Matches on selected register. */ 49 struct mlx5_rte_flow_item_tag { 50 enum modify_reg id; 51 uint32_t data; 52 }; 53 54 /* Modify selected register. */ 55 struct mlx5_rte_flow_action_set_tag { 56 enum modify_reg id; 57 uint8_t offset; 58 uint8_t length; 59 uint32_t data; 60 }; 61 62 struct mlx5_flow_action_copy_mreg { 63 enum modify_reg dst; 64 enum modify_reg src; 65 }; 66 67 /* Matches on source queue. */ 68 struct mlx5_rte_flow_item_tx_queue { 69 uint32_t queue; 70 }; 71 72 /* Feature name to allocate metadata register. */ 73 enum mlx5_feature_name { 74 MLX5_HAIRPIN_RX, 75 MLX5_HAIRPIN_TX, 76 MLX5_METADATA_RX, 77 MLX5_METADATA_TX, 78 MLX5_METADATA_FDB, 79 MLX5_FLOW_MARK, 80 MLX5_APP_TAG, 81 MLX5_COPY_MARK, 82 MLX5_MTR_COLOR, 83 MLX5_MTR_ID, 84 MLX5_ASO_FLOW_HIT, 85 }; 86 87 /* Default queue number. */ 88 #define MLX5_RSSQ_DEFAULT_NUM 16 89 90 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0) 91 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1) 92 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2) 93 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3) 94 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4) 95 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5) 96 97 /* Pattern inner Layer bits. */ 98 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6) 99 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7) 100 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8) 101 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9) 102 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10) 103 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11) 104 105 /* Pattern tunnel Layer bits. */ 106 #define MLX5_FLOW_LAYER_VXLAN (1u << 12) 107 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) 108 #define MLX5_FLOW_LAYER_GRE (1u << 14) 109 #define MLX5_FLOW_LAYER_MPLS (1u << 15) 110 /* List of tunnel Layer bits continued below. */ 111 112 /* General pattern items bits. */ 113 #define MLX5_FLOW_ITEM_METADATA (1u << 16) 114 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17) 115 #define MLX5_FLOW_ITEM_TAG (1u << 18) 116 #define MLX5_FLOW_ITEM_MARK (1u << 19) 117 118 /* Pattern MISC bits. */ 119 #define MLX5_FLOW_LAYER_ICMP (1u << 20) 120 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21) 121 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22) 122 123 /* Pattern tunnel Layer bits (continued). */ 124 #define MLX5_FLOW_LAYER_IPIP (1u << 23) 125 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24) 126 #define MLX5_FLOW_LAYER_NVGRE (1u << 25) 127 #define MLX5_FLOW_LAYER_GENEVE (1u << 26) 128 129 /* Queue items. */ 130 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27) 131 132 /* Pattern tunnel Layer bits (continued). */ 133 #define MLX5_FLOW_LAYER_GTP (1u << 28) 134 135 /* Pattern eCPRI Layer bit. */ 136 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29) 137 138 /* IPv6 Fragment Extension Header bit. */ 139 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) 140 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) 141 142 /* Pattern tunnel Layer bits (continued). */ 143 #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) 144 #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) 145 146 /* Outer Masks. */ 147 #define MLX5_FLOW_LAYER_OUTER_L3 \ 148 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) 149 #define MLX5_FLOW_LAYER_OUTER_L4 \ 150 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP) 151 #define MLX5_FLOW_LAYER_OUTER \ 152 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \ 153 MLX5_FLOW_LAYER_OUTER_L4) 154 155 /* Tunnel Masks. */ 156 #define MLX5_FLOW_LAYER_TUNNEL \ 157 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ 158 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ 159 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \ 160 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP) 161 162 /* Inner Masks. */ 163 #define MLX5_FLOW_LAYER_INNER_L3 \ 164 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 165 #define MLX5_FLOW_LAYER_INNER_L4 \ 166 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP) 167 #define MLX5_FLOW_LAYER_INNER \ 168 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \ 169 MLX5_FLOW_LAYER_INNER_L4) 170 171 /* Layer Masks. */ 172 #define MLX5_FLOW_LAYER_L2 \ 173 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2) 174 #define MLX5_FLOW_LAYER_L3_IPV4 \ 175 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4) 176 #define MLX5_FLOW_LAYER_L3_IPV6 \ 177 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6) 178 #define MLX5_FLOW_LAYER_L3 \ 179 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6) 180 #define MLX5_FLOW_LAYER_L4 \ 181 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4) 182 183 /* Actions */ 184 #define MLX5_FLOW_ACTION_DROP (1u << 0) 185 #define MLX5_FLOW_ACTION_QUEUE (1u << 1) 186 #define MLX5_FLOW_ACTION_RSS (1u << 2) 187 #define MLX5_FLOW_ACTION_FLAG (1u << 3) 188 #define MLX5_FLOW_ACTION_MARK (1u << 4) 189 #define MLX5_FLOW_ACTION_COUNT (1u << 5) 190 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6) 191 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) 192 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) 193 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) 194 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) 195 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) 196 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) 197 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) 198 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) 199 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) 200 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) 201 #define MLX5_FLOW_ACTION_JUMP (1u << 17) 202 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18) 203 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) 204 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) 205 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) 206 #define MLX5_FLOW_ACTION_ENCAP (1u << 22) 207 #define MLX5_FLOW_ACTION_DECAP (1u << 23) 208 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) 209 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) 210 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) 211 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) 212 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) 213 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) 214 #define MLX5_FLOW_ACTION_SET_META (1ull << 30) 215 #define MLX5_FLOW_ACTION_METER (1ull << 31) 216 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) 217 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) 218 #define MLX5_FLOW_ACTION_AGE (1ull << 34) 219 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) 220 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36) 221 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37) 222 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38) 223 #define MLX5_FLOW_ACTION_MODIFY_FIELD (1ull << 39) 224 225 #define MLX5_FLOW_FATE_ACTIONS \ 226 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ 227 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ 228 MLX5_FLOW_ACTION_DEFAULT_MISS) 229 230 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ 231 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ 232 MLX5_FLOW_ACTION_JUMP) 233 234 235 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \ 236 MLX5_FLOW_ACTION_SET_IPV4_DST | \ 237 MLX5_FLOW_ACTION_SET_IPV6_SRC | \ 238 MLX5_FLOW_ACTION_SET_IPV6_DST | \ 239 MLX5_FLOW_ACTION_SET_TP_SRC | \ 240 MLX5_FLOW_ACTION_SET_TP_DST | \ 241 MLX5_FLOW_ACTION_SET_TTL | \ 242 MLX5_FLOW_ACTION_DEC_TTL | \ 243 MLX5_FLOW_ACTION_SET_MAC_SRC | \ 244 MLX5_FLOW_ACTION_SET_MAC_DST | \ 245 MLX5_FLOW_ACTION_INC_TCP_SEQ | \ 246 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \ 247 MLX5_FLOW_ACTION_INC_TCP_ACK | \ 248 MLX5_FLOW_ACTION_DEC_TCP_ACK | \ 249 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \ 250 MLX5_FLOW_ACTION_SET_TAG | \ 251 MLX5_FLOW_ACTION_MARK_EXT | \ 252 MLX5_FLOW_ACTION_SET_META | \ 253 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \ 254 MLX5_FLOW_ACTION_SET_IPV6_DSCP | \ 255 MLX5_FLOW_ACTION_MODIFY_FIELD) 256 257 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \ 258 MLX5_FLOW_ACTION_OF_PUSH_VLAN) 259 260 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP) 261 262 #ifndef IPPROTO_MPLS 263 #define IPPROTO_MPLS 137 264 #endif 265 266 /* UDP port number for MPLS */ 267 #define MLX5_UDP_PORT_MPLS 6635 268 269 /* UDP port numbers for VxLAN. */ 270 #define MLX5_UDP_PORT_VXLAN 4789 271 #define MLX5_UDP_PORT_VXLAN_GPE 4790 272 273 /* UDP port numbers for GENEVE. */ 274 #define MLX5_UDP_PORT_GENEVE 6081 275 276 /* Lowest priority indicator. */ 277 #define MLX5_FLOW_LOWEST_PRIO_INDICATOR ((uint32_t)-1) 278 279 /* 280 * Max priority for ingress\egress flow groups 281 * greater than 0 and for any transfer flow group. 282 * From user configation: 0 - 21843. 283 */ 284 #define MLX5_NON_ROOT_FLOW_MAX_PRIO (21843 + 1) 285 286 /* 287 * Number of sub priorities. 288 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct 289 * matching on the NIC (firmware dependent) L4 most have the higher priority 290 * followed by L3 and ending with L2. 291 */ 292 #define MLX5_PRIORITY_MAP_L2 2 293 #define MLX5_PRIORITY_MAP_L3 1 294 #define MLX5_PRIORITY_MAP_L4 0 295 #define MLX5_PRIORITY_MAP_MAX 3 296 297 /* Valid layer type for IPV4 RSS. */ 298 #define MLX5_IPV4_LAYER_TYPES \ 299 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \ 300 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \ 301 ETH_RSS_NONFRAG_IPV4_OTHER) 302 303 /* IBV hash source bits for IPV4. */ 304 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 305 306 /* Valid layer type for IPV6 RSS. */ 307 #define MLX5_IPV6_LAYER_TYPES \ 308 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \ 309 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \ 310 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER) 311 312 /* IBV hash source bits for IPV6. */ 313 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 314 315 /* IBV hash bits for L3 SRC. */ 316 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6) 317 318 /* IBV hash bits for L3 DST. */ 319 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6) 320 321 /* IBV hash bits for TCP. */ 322 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 323 IBV_RX_HASH_DST_PORT_TCP) 324 325 /* IBV hash bits for UDP. */ 326 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \ 327 IBV_RX_HASH_DST_PORT_UDP) 328 329 /* IBV hash bits for L4 SRC. */ 330 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \ 331 IBV_RX_HASH_SRC_PORT_UDP) 332 333 /* IBV hash bits for L4 DST. */ 334 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \ 335 IBV_RX_HASH_DST_PORT_UDP) 336 337 /* Geneve header first 16Bit */ 338 #define MLX5_GENEVE_VER_MASK 0x3 339 #define MLX5_GENEVE_VER_SHIFT 14 340 #define MLX5_GENEVE_VER_VAL(a) \ 341 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK)) 342 #define MLX5_GENEVE_OPTLEN_MASK 0x3F 343 #define MLX5_GENEVE_OPTLEN_SHIFT 8 344 #define MLX5_GENEVE_OPTLEN_VAL(a) \ 345 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK)) 346 #define MLX5_GENEVE_OAMF_MASK 0x1 347 #define MLX5_GENEVE_OAMF_SHIFT 7 348 #define MLX5_GENEVE_OAMF_VAL(a) \ 349 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK)) 350 #define MLX5_GENEVE_CRITO_MASK 0x1 351 #define MLX5_GENEVE_CRITO_SHIFT 6 352 #define MLX5_GENEVE_CRITO_VAL(a) \ 353 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK)) 354 #define MLX5_GENEVE_RSVD_MASK 0x3F 355 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK)) 356 /* 357 * The length of the Geneve options fields, expressed in four byte multiples, 358 * not including the eight byte fixed tunnel. 359 */ 360 #define MLX5_GENEVE_OPT_LEN_0 14 361 #define MLX5_GENEVE_OPT_LEN_1 63 362 363 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ 364 sizeof(struct rte_ipv4_hdr)) 365 /* GTP extension header flag. */ 366 #define MLX5_GTP_EXT_HEADER_FLAG 4 367 368 /* GTP extension header max PDU type value. */ 369 #define MLX5_GTP_EXT_MAX_PDU_TYPE 15 370 371 /* GTP extension header PDU type shift. */ 372 #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) 373 374 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ 375 #define MLX5_IPV4_FRAG_OFFSET_MASK \ 376 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) 377 378 /* Specific item's fields can accept a range of values (using spec and last). */ 379 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false 380 #define MLX5_ITEM_RANGE_ACCEPTED true 381 382 /* Software header modify action numbers of a flow. */ 383 #define MLX5_ACT_NUM_MDF_IPV4 1 384 #define MLX5_ACT_NUM_MDF_IPV6 4 385 #define MLX5_ACT_NUM_MDF_MAC 2 386 #define MLX5_ACT_NUM_MDF_VID 1 387 #define MLX5_ACT_NUM_MDF_PORT 2 388 #define MLX5_ACT_NUM_MDF_TTL 1 389 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL 390 #define MLX5_ACT_NUM_MDF_TCPSEQ 1 391 #define MLX5_ACT_NUM_MDF_TCPACK 1 392 #define MLX5_ACT_NUM_SET_REG 1 393 #define MLX5_ACT_NUM_SET_TAG 1 394 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG 395 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG 396 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG 397 #define MLX5_ACT_NUM_SET_DSCP 1 398 399 /* Maximum number of fields to modify in MODIFY_FIELD */ 400 #define MLX5_ACT_MAX_MOD_FIELDS 5 401 402 enum mlx5_flow_drv_type { 403 MLX5_FLOW_TYPE_MIN, 404 MLX5_FLOW_TYPE_DV, 405 MLX5_FLOW_TYPE_VERBS, 406 MLX5_FLOW_TYPE_MAX, 407 }; 408 409 /* Fate action type. */ 410 enum mlx5_flow_fate_type { 411 MLX5_FLOW_FATE_NONE, /* Egress flow. */ 412 MLX5_FLOW_FATE_QUEUE, 413 MLX5_FLOW_FATE_JUMP, 414 MLX5_FLOW_FATE_PORT_ID, 415 MLX5_FLOW_FATE_DROP, 416 MLX5_FLOW_FATE_DEFAULT_MISS, 417 MLX5_FLOW_FATE_SHARED_RSS, 418 MLX5_FLOW_FATE_MAX, 419 }; 420 421 /* Matcher PRM representation */ 422 struct mlx5_flow_dv_match_params { 423 size_t size; 424 /**< Size of match value. Do NOT split size and key! */ 425 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; 426 /**< Matcher value. This value is used as the mask or as a key. */ 427 }; 428 429 /* Matcher structure. */ 430 struct mlx5_flow_dv_matcher { 431 struct mlx5_cache_entry entry; /**< Pointer to the next element. */ 432 struct mlx5_flow_tbl_resource *tbl; 433 /**< Pointer to the table(group) the matcher associated with. */ 434 void *matcher_object; /**< Pointer to DV matcher */ 435 uint16_t crc; /**< CRC of key. */ 436 uint16_t priority; /**< Priority of matcher. */ 437 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */ 438 }; 439 440 #define MLX5_ENCAP_MAX_LEN 132 441 442 /* Encap/decap resource structure. */ 443 struct mlx5_flow_dv_encap_decap_resource { 444 struct mlx5_hlist_entry entry; 445 /* Pointer to next element. */ 446 uint32_t refcnt; /**< Reference counter. */ 447 void *action; 448 /**< Encap/decap action object. */ 449 uint8_t buf[MLX5_ENCAP_MAX_LEN]; 450 size_t size; 451 uint8_t reformat_type; 452 uint8_t ft_type; 453 uint64_t flags; /**< Flags for RDMA API. */ 454 uint32_t idx; /**< Index for the index memory pool. */ 455 }; 456 457 /* Tag resource structure. */ 458 struct mlx5_flow_dv_tag_resource { 459 struct mlx5_hlist_entry entry; 460 /**< hash list entry for tag resource, tag value as the key. */ 461 void *action; 462 /**< Tag action object. */ 463 uint32_t refcnt; /**< Reference counter. */ 464 uint32_t idx; /**< Index for the index memory pool. */ 465 uint32_t tag_id; /**< Tag ID. */ 466 }; 467 468 /* 469 * Number of modification commands. 470 * The maximal actions amount in FW is some constant, and it is 16 in the 471 * latest releases. In some old releases, it will be limited to 8. 472 * Since there is no interface to query the capacity, the maximal value should 473 * be used to allow PMD to create the flow. The validation will be done in the 474 * lower driver layer or FW. A failure will be returned if exceeds the maximal 475 * supported actions number on the root table. 476 * On non-root tables, there is no limitation, but 32 is enough right now. 477 */ 478 #define MLX5_MAX_MODIFY_NUM 32 479 #define MLX5_ROOT_TBL_MODIFY_NUM 16 480 481 /* Modify resource structure */ 482 struct mlx5_flow_dv_modify_hdr_resource { 483 struct mlx5_hlist_entry entry; 484 void *action; /**< Modify header action object. */ 485 /* Key area for hash list matching: */ 486 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 487 uint32_t actions_num; /**< Number of modification actions. */ 488 uint64_t flags; /**< Flags for RDMA API. */ 489 struct mlx5_modification_cmd actions[]; 490 /**< Modification actions. */ 491 }; 492 493 /* Modify resource key of the hash organization. */ 494 union mlx5_flow_modify_hdr_key { 495 struct { 496 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */ 497 uint32_t actions_num:5; /**< Number of modification actions. */ 498 uint32_t group:19; /**< Flow group id. */ 499 uint32_t cksum; /**< Actions check sum. */ 500 }; 501 uint64_t v64; /**< full 64bits value of key */ 502 }; 503 504 /* Jump action resource structure. */ 505 struct mlx5_flow_dv_jump_tbl_resource { 506 void *action; /**< Pointer to the rdma core action. */ 507 }; 508 509 /* Port ID resource structure. */ 510 struct mlx5_flow_dv_port_id_action_resource { 511 struct mlx5_cache_entry entry; 512 void *action; /**< Action object. */ 513 uint32_t port_id; /**< Port ID value. */ 514 uint32_t idx; /**< Indexed pool memory index. */ 515 }; 516 517 /* Push VLAN action resource structure */ 518 struct mlx5_flow_dv_push_vlan_action_resource { 519 struct mlx5_cache_entry entry; /* Cache entry. */ 520 void *action; /**< Action object. */ 521 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */ 522 rte_be32_t vlan_tag; /**< VLAN tag value. */ 523 uint32_t idx; /**< Indexed pool memory index. */ 524 }; 525 526 /* Metadata register copy table entry. */ 527 struct mlx5_flow_mreg_copy_resource { 528 /* 529 * Hash list entry for copy table. 530 * - Key is 32/64-bit MARK action ID. 531 * - MUST be the first entry. 532 */ 533 struct mlx5_hlist_entry hlist_ent; 534 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next; 535 /* List entry for device flows. */ 536 uint32_t idx; 537 uint32_t rix_flow; /* Built flow for copy. */ 538 uint32_t mark_id; 539 }; 540 541 /* Table tunnel parameter. */ 542 struct mlx5_flow_tbl_tunnel_prm { 543 const struct mlx5_flow_tunnel *tunnel; 544 uint32_t group_id; 545 bool external; 546 }; 547 548 /* Table data structure of the hash organization. */ 549 struct mlx5_flow_tbl_data_entry { 550 struct mlx5_hlist_entry entry; 551 /**< hash list entry, 64-bits key inside. */ 552 struct mlx5_flow_tbl_resource tbl; 553 /**< flow table resource. */ 554 struct mlx5_cache_list matchers; 555 /**< matchers' header associated with the flow table. */ 556 struct mlx5_flow_dv_jump_tbl_resource jump; 557 /**< jump resource, at most one for each table created. */ 558 uint32_t idx; /**< index for the indexed mempool. */ 559 /**< tunnel offload */ 560 const struct mlx5_flow_tunnel *tunnel; 561 uint32_t group_id; 562 uint32_t external:1; 563 uint32_t tunnel_offload:1; /* Tunnel offlod table or not. */ 564 uint32_t is_egress:1; /**< Egress table. */ 565 uint32_t is_transfer:1; /**< Transfer table. */ 566 uint32_t dummy:1; /**< DR table. */ 567 uint32_t id:22; /**< Table ID. */ 568 uint32_t reserve:5; /**< Reserved to future using. */ 569 uint32_t level; /**< Table level. */ 570 }; 571 572 /* Sub rdma-core actions list. */ 573 struct mlx5_flow_sub_actions_list { 574 uint32_t actions_num; /**< Number of sample actions. */ 575 uint64_t action_flags; 576 void *dr_queue_action; 577 void *dr_tag_action; 578 void *dr_cnt_action; 579 void *dr_port_id_action; 580 void *dr_encap_action; 581 void *dr_jump_action; 582 }; 583 584 /* Sample sub-actions resource list. */ 585 struct mlx5_flow_sub_actions_idx { 586 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 587 uint32_t rix_tag; /**< Index to the tag action. */ 588 uint32_t rix_port_id_action; /**< Index to port ID action resource. */ 589 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */ 590 uint32_t rix_jump; /**< Index to the jump action resource. */ 591 }; 592 593 /* Sample action resource structure. */ 594 struct mlx5_flow_dv_sample_resource { 595 struct mlx5_cache_entry entry; /**< Cache entry. */ 596 union { 597 void *verbs_action; /**< Verbs sample action object. */ 598 void **sub_actions; /**< Sample sub-action array. */ 599 }; 600 struct rte_eth_dev *dev; /**< Device registers the action. */ 601 uint32_t idx; /** Sample object index. */ 602 uint8_t ft_type; /** Flow Table Type */ 603 uint32_t ft_id; /** Flow Table Level */ 604 uint32_t ratio; /** Sample Ratio */ 605 uint64_t set_action; /** Restore reg_c0 value */ 606 void *normal_path_tbl; /** Flow Table pointer */ 607 struct mlx5_flow_sub_actions_idx sample_idx; 608 /**< Action index resources. */ 609 struct mlx5_flow_sub_actions_list sample_act; 610 /**< Action resources. */ 611 }; 612 613 #define MLX5_MAX_DEST_NUM 2 614 615 /* Destination array action resource structure. */ 616 struct mlx5_flow_dv_dest_array_resource { 617 struct mlx5_cache_entry entry; /**< Cache entry. */ 618 uint32_t idx; /** Destination array action object index. */ 619 uint8_t ft_type; /** Flow Table Type */ 620 uint8_t num_of_dest; /**< Number of destination actions. */ 621 struct rte_eth_dev *dev; /**< Device registers the action. */ 622 void *action; /**< Pointer to the rdma core action. */ 623 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM]; 624 /**< Action index resources. */ 625 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM]; 626 /**< Action resources. */ 627 }; 628 629 /* PMD flow priority for tunnel */ 630 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ 631 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) 632 633 634 /** Device flow handle structure for DV mode only. */ 635 struct mlx5_flow_handle_dv { 636 /* Flow DV api: */ 637 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */ 638 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 639 /**< Pointer to modify header resource in cache. */ 640 uint32_t rix_encap_decap; 641 /**< Index to encap/decap resource in cache. */ 642 uint32_t rix_push_vlan; 643 /**< Index to push VLAN action resource in cache. */ 644 uint32_t rix_tag; 645 /**< Index to the tag action. */ 646 uint32_t rix_sample; 647 /**< Index to sample action resource in cache. */ 648 uint32_t rix_dest_array; 649 /**< Index to destination array resource in cache. */ 650 } __rte_packed; 651 652 /** Device flow handle structure: used both for creating & destroying. */ 653 struct mlx5_flow_handle { 654 SILIST_ENTRY(uint32_t)next; 655 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */ 656 /**< Index to next device flow handle. */ 657 uint64_t layers; 658 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */ 659 void *drv_flow; /**< pointer to driver flow object. */ 660 uint32_t split_flow_id:27; /**< Sub flow unique match flow id. */ 661 uint32_t is_meter_flow_id:1; /**< Indate if flow_id is for meter. */ 662 uint32_t mark:1; /**< Metadate rxq mark flag. */ 663 uint32_t fate_action:3; /**< Fate action type. */ 664 union { 665 uint32_t rix_hrxq; /**< Hash Rx queue object index. */ 666 uint32_t rix_jump; /**< Index to the jump action resource. */ 667 uint32_t rix_port_id_action; 668 /**< Index to port ID action resource. */ 669 uint32_t rix_fate; 670 /**< Generic value indicates the fate action. */ 671 uint32_t rix_default_fate; 672 /**< Indicates default miss fate action. */ 673 uint32_t rix_srss; 674 /**< Indicates shared RSS fate action. */ 675 }; 676 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 677 struct mlx5_flow_handle_dv dvh; 678 #endif 679 } __rte_packed; 680 681 /* 682 * Size for Verbs device flow handle structure only. Do not use the DV only 683 * structure in Verbs. No DV flows attributes will be accessed. 684 * Macro offsetof() could also be used here. 685 */ 686 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 687 #define MLX5_FLOW_HANDLE_VERBS_SIZE \ 688 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) 689 #else 690 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle)) 691 #endif 692 693 /* 694 * Max number of actions per DV flow. 695 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 696 * in rdma-core file providers/mlx5/verbs.c. 697 */ 698 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 699 700 /** Device flow structure only for DV flow creation. */ 701 struct mlx5_flow_dv_workspace { 702 uint32_t group; /**< The group index. */ 703 uint32_t table_id; /**< Flow table identifier. */ 704 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */ 705 int actions_n; /**< number of actions. */ 706 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */ 707 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 708 /**< Pointer to encap/decap resource in cache. */ 709 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res; 710 /**< Pointer to push VLAN action resource in cache. */ 711 struct mlx5_flow_dv_tag_resource *tag_resource; 712 /**< pointer to the tag action. */ 713 struct mlx5_flow_dv_port_id_action_resource *port_id_action; 714 /**< Pointer to port ID action resource. */ 715 struct mlx5_flow_dv_jump_tbl_resource *jump; 716 /**< Pointer to the jump action resource. */ 717 struct mlx5_flow_dv_match_params value; 718 /**< Holds the value that the packet is compared to. */ 719 struct mlx5_flow_dv_sample_resource *sample_res; 720 /**< Pointer to the sample action resource. */ 721 struct mlx5_flow_dv_dest_array_resource *dest_array_res; 722 /**< Pointer to the destination array resource. */ 723 }; 724 725 #ifdef HAVE_INFINIBAND_VERBS_H 726 /* 727 * Maximal Verbs flow specifications & actions size. 728 * Some elements are mutually exclusive, but enough space should be allocated. 729 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers. 730 * 2. One tunnel header (exception: GRE + MPLS), 731 * SPEC length: GRE == tunnel. 732 * Actions: 1. 1 Mark OR Flag. 733 * 2. 1 Drop (if any). 734 * 3. No limitation for counters, but it makes no sense to support too 735 * many counters in a single device flow. 736 */ 737 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 738 #define MLX5_VERBS_MAX_SPEC_SIZE \ 739 ( \ 740 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 741 sizeof(struct ibv_flow_spec_ipv6) + \ 742 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 743 sizeof(struct ibv_flow_spec_gre) + \ 744 sizeof(struct ibv_flow_spec_mpls)) \ 745 ) 746 #else 747 #define MLX5_VERBS_MAX_SPEC_SIZE \ 748 ( \ 749 (2 * (sizeof(struct ibv_flow_spec_eth) + \ 750 sizeof(struct ibv_flow_spec_ipv6) + \ 751 sizeof(struct ibv_flow_spec_tcp_udp)) + \ 752 sizeof(struct ibv_flow_spec_tunnel)) \ 753 ) 754 #endif 755 756 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \ 757 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 758 #define MLX5_VERBS_MAX_ACT_SIZE \ 759 ( \ 760 sizeof(struct ibv_flow_spec_action_tag) + \ 761 sizeof(struct ibv_flow_spec_action_drop) + \ 762 sizeof(struct ibv_flow_spec_counter_action) * 4 \ 763 ) 764 #else 765 #define MLX5_VERBS_MAX_ACT_SIZE \ 766 ( \ 767 sizeof(struct ibv_flow_spec_action_tag) + \ 768 sizeof(struct ibv_flow_spec_action_drop) \ 769 ) 770 #endif 771 772 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \ 773 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE) 774 775 /** Device flow structure only for Verbs flow creation. */ 776 struct mlx5_flow_verbs_workspace { 777 unsigned int size; /**< Size of the attribute. */ 778 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */ 779 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; 780 /**< Specifications & actions buffer of verbs flow. */ 781 }; 782 #endif /* HAVE_INFINIBAND_VERBS_H */ 783 784 #define MLX5_SCALE_FLOW_GROUP_BIT 0 785 #define MLX5_SCALE_JUMP_FLOW_GROUP_BIT 1 786 787 /** Maximal number of device sub-flows supported. */ 788 #define MLX5_NUM_MAX_DEV_FLOWS 32 789 790 /** Device flow structure. */ 791 __extension__ 792 struct mlx5_flow { 793 struct rte_flow *flow; /**< Pointer to the main flow. */ 794 uint32_t flow_idx; /**< The memory pool index to the main flow. */ 795 uint64_t hash_fields; /**< Hash Rx queue hash fields. */ 796 uint64_t act_flags; 797 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */ 798 bool external; /**< true if the flow is created external to PMD. */ 799 uint8_t ingress:1; /**< 1 if the flow is ingress. */ 800 uint8_t skip_scale:2; 801 /** 802 * Each Bit be set to 1 if Skip the scale the flow group with factor. 803 * If bit0 be set to 1, then skip the scale the original flow group; 804 * If bit1 be set to 1, then skip the scale the jump flow group if 805 * having jump action. 806 * 00: Enable scale in a flow, default value. 807 * 01: Skip scale the flow group with factor, enable scale the group 808 * of jump action. 809 * 10: Enable scale the group with factor, skip scale the group of 810 * jump action. 811 * 11: Skip scale the table with factor both for flow group and jump 812 * group. 813 */ 814 union { 815 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 816 struct mlx5_flow_dv_workspace dv; 817 #endif 818 #ifdef HAVE_INFINIBAND_VERBS_H 819 struct mlx5_flow_verbs_workspace verbs; 820 #endif 821 }; 822 struct mlx5_flow_handle *handle; 823 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ 824 const struct mlx5_flow_tunnel *tunnel; 825 }; 826 827 /* Flow meter state. */ 828 #define MLX5_FLOW_METER_DISABLE 0 829 #define MLX5_FLOW_METER_ENABLE 1 830 831 #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u 832 #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u 833 834 #define MLX5_MAN_WIDTH 8 835 /* Legacy Meter parameter structure. */ 836 struct mlx5_legacy_flow_meter { 837 struct mlx5_flow_meter_info fm; 838 /* Must be the first in struct. */ 839 TAILQ_ENTRY(mlx5_legacy_flow_meter) next; 840 /**< Pointer to the next flow meter structure. */ 841 uint32_t meter_id; 842 /**< Meter id. */ 843 uint32_t idx; /* Index to meter object. */ 844 }; 845 846 #define MLX5_MAX_TUNNELS 256 847 #define MLX5_TNL_MISS_RULE_PRIORITY 3 848 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac 849 850 /* 851 * When tunnel offload is active, all JUMP group ids are converted 852 * using the same method. That conversion is applied both to tunnel and 853 * regular rule types. 854 * Group ids used in tunnel rules are relative to it's tunnel (!). 855 * Application can create number of steer rules, using the same 856 * tunnel, with different group id in each rule. 857 * Each tunnel stores its groups internally in PMD tunnel object. 858 * Groups used in regular rules do not belong to any tunnel and are stored 859 * in tunnel hub. 860 */ 861 862 struct mlx5_flow_tunnel { 863 LIST_ENTRY(mlx5_flow_tunnel) chain; 864 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */ 865 uint32_t tunnel_id; /** unique tunnel ID */ 866 uint32_t refctn; 867 struct rte_flow_action action; 868 struct rte_flow_item item; 869 struct mlx5_hlist *groups; /** tunnel groups */ 870 }; 871 872 /** PMD tunnel related context */ 873 struct mlx5_flow_tunnel_hub { 874 /* Tunnels list 875 * Access to the list MUST be MT protected 876 */ 877 LIST_HEAD(, mlx5_flow_tunnel) tunnels; 878 /* protect access to the tunnels list */ 879 rte_spinlock_t sl; 880 struct mlx5_hlist *groups; /** non tunnel groups */ 881 }; 882 883 /* convert jump group to flow table ID in tunnel rules */ 884 struct tunnel_tbl_entry { 885 struct mlx5_hlist_entry hash; 886 uint32_t flow_table; 887 uint32_t tunnel_id; 888 uint32_t group; 889 }; 890 891 static inline uint32_t 892 tunnel_id_to_flow_tbl(uint32_t id) 893 { 894 return id | (1u << 16); 895 } 896 897 static inline uint32_t 898 tunnel_flow_tbl_to_id(uint32_t flow_tbl) 899 { 900 return flow_tbl & ~(1u << 16); 901 } 902 903 union tunnel_tbl_key { 904 uint64_t val; 905 struct { 906 uint32_t tunnel_id; 907 uint32_t group; 908 }; 909 }; 910 911 static inline struct mlx5_flow_tunnel_hub * 912 mlx5_tunnel_hub(struct rte_eth_dev *dev) 913 { 914 struct mlx5_priv *priv = dev->data->dev_private; 915 return priv->sh->tunnel_hub; 916 } 917 918 static inline bool 919 is_tunnel_offload_active(struct rte_eth_dev *dev) 920 { 921 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 922 struct mlx5_priv *priv = dev->data->dev_private; 923 return !!priv->config.dv_miss_info; 924 #else 925 RTE_SET_USED(dev); 926 return false; 927 #endif 928 } 929 930 static inline bool 931 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev, 932 __rte_unused const struct rte_flow_attr *attr, 933 __rte_unused const struct rte_flow_item items[], 934 __rte_unused const struct rte_flow_action actions[]) 935 { 936 return (items[0].type == (typeof(items[0].type)) 937 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL); 938 } 939 940 static inline bool 941 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev, 942 __rte_unused const struct rte_flow_attr *attr, 943 __rte_unused const struct rte_flow_item items[], 944 __rte_unused const struct rte_flow_action actions[]) 945 { 946 return (actions[0].type == (typeof(actions[0].type)) 947 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET); 948 } 949 950 static inline const struct mlx5_flow_tunnel * 951 flow_actions_to_tunnel(const struct rte_flow_action actions[]) 952 { 953 return actions[0].conf; 954 } 955 956 static inline const struct mlx5_flow_tunnel * 957 flow_items_to_tunnel(const struct rte_flow_item items[]) 958 { 959 return items[0].spec; 960 } 961 962 /* Flow structure. */ 963 struct rte_flow { 964 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */ 965 uint32_t dev_handles; 966 /**< Device flow handles that are part of the flow. */ 967 uint32_t drv_type:2; /**< Driver type. */ 968 uint32_t tunnel:1; 969 uint32_t meter:24; /**< Holds flow meter id. */ 970 uint32_t rix_mreg_copy; 971 /**< Index to metadata register copy table resource. */ 972 uint32_t counter; /**< Holds flow counter. */ 973 uint32_t tunnel_id; /**< Tunnel id */ 974 uint32_t age; /**< Holds ASO age bit index. */ 975 uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ 976 } __rte_packed; 977 978 /* 979 * Define list of valid combinations of RX Hash fields 980 * (see enum ibv_rx_hash_fields). 981 */ 982 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4) 983 #define MLX5_RSS_HASH_IPV4_TCP \ 984 (MLX5_RSS_HASH_IPV4 | \ 985 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 986 #define MLX5_RSS_HASH_IPV4_UDP \ 987 (MLX5_RSS_HASH_IPV4 | \ 988 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 989 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6) 990 #define MLX5_RSS_HASH_IPV6_TCP \ 991 (MLX5_RSS_HASH_IPV6 | \ 992 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_DST_PORT_TCP) 993 #define MLX5_RSS_HASH_IPV6_UDP \ 994 (MLX5_RSS_HASH_IPV6 | \ 995 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_DST_PORT_UDP) 996 #define MLX5_RSS_HASH_IPV4_SRC_ONLY IBV_RX_HASH_SRC_IPV4 997 #define MLX5_RSS_HASH_IPV4_DST_ONLY IBV_RX_HASH_DST_IPV4 998 #define MLX5_RSS_HASH_IPV6_SRC_ONLY IBV_RX_HASH_SRC_IPV6 999 #define MLX5_RSS_HASH_IPV6_DST_ONLY IBV_RX_HASH_DST_IPV6 1000 #define MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY \ 1001 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_UDP) 1002 #define MLX5_RSS_HASH_IPV4_UDP_DST_ONLY \ 1003 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_UDP) 1004 #define MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY \ 1005 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_UDP) 1006 #define MLX5_RSS_HASH_IPV6_UDP_DST_ONLY \ 1007 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_UDP) 1008 #define MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY \ 1009 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_SRC_PORT_TCP) 1010 #define MLX5_RSS_HASH_IPV4_TCP_DST_ONLY \ 1011 (MLX5_RSS_HASH_IPV4 | IBV_RX_HASH_DST_PORT_TCP) 1012 #define MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY \ 1013 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_SRC_PORT_TCP) 1014 #define MLX5_RSS_HASH_IPV6_TCP_DST_ONLY \ 1015 (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) 1016 #define MLX5_RSS_HASH_NONE 0ULL 1017 1018 /* array of valid combinations of RX Hash fields for RSS */ 1019 static const uint64_t mlx5_rss_hash_fields[] = { 1020 MLX5_RSS_HASH_IPV4, 1021 MLX5_RSS_HASH_IPV4_TCP, 1022 MLX5_RSS_HASH_IPV4_UDP, 1023 MLX5_RSS_HASH_IPV6, 1024 MLX5_RSS_HASH_IPV6_TCP, 1025 MLX5_RSS_HASH_IPV6_UDP, 1026 MLX5_RSS_HASH_NONE, 1027 }; 1028 1029 /* Shared RSS action structure */ 1030 struct mlx5_shared_action_rss { 1031 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */ 1032 uint32_t refcnt; /**< Atomically accessed refcnt. */ 1033 struct rte_flow_action_rss origin; /**< Original rte RSS action. */ 1034 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1035 struct mlx5_ind_table_obj *ind_tbl; 1036 /**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */ 1037 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN]; 1038 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */ 1039 rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */ 1040 }; 1041 1042 struct rte_flow_action_handle { 1043 uint32_t id; 1044 }; 1045 1046 /* Thread specific flow workspace intermediate data. */ 1047 struct mlx5_flow_workspace { 1048 /* If creating another flow in same thread, push new as stack. */ 1049 struct mlx5_flow_workspace *prev; 1050 struct mlx5_flow_workspace *next; 1051 uint32_t inuse; /* can't create new flow with current. */ 1052 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS]; 1053 struct mlx5_flow_rss_desc rss_desc; 1054 uint32_t rssq_num; /* Allocated queue num in rss_desc. */ 1055 uint32_t flow_idx; /* Intermediate device flow index. */ 1056 struct mlx5_flow_meter_info *fm; /* Pointer to the meter in flow. */ 1057 }; 1058 1059 struct mlx5_flow_split_info { 1060 bool external; 1061 /**< True if flow is created by request external to PMD. */ 1062 uint8_t skip_scale; /**< Skip the scale the table with factor. */ 1063 uint32_t flow_idx; /**< This memory pool index to the flow. */ 1064 uint32_t prefix_mark; /**< Prefix subflow mark flag. */ 1065 uint64_t prefix_layers; /**< Prefix subflow layers. */ 1066 uint32_t table_id; /**< Flow table identifier. */ 1067 }; 1068 1069 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, 1070 const struct rte_flow_attr *attr, 1071 const struct rte_flow_item items[], 1072 const struct rte_flow_action actions[], 1073 bool external, 1074 int hairpin, 1075 struct rte_flow_error *error); 1076 typedef struct mlx5_flow *(*mlx5_flow_prepare_t) 1077 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr, 1078 const struct rte_flow_item items[], 1079 const struct rte_flow_action actions[], struct rte_flow_error *error); 1080 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev, 1081 struct mlx5_flow *dev_flow, 1082 const struct rte_flow_attr *attr, 1083 const struct rte_flow_item items[], 1084 const struct rte_flow_action actions[], 1085 struct rte_flow_error *error); 1086 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow, 1087 struct rte_flow_error *error); 1088 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev, 1089 struct rte_flow *flow); 1090 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev, 1091 struct rte_flow *flow); 1092 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev, 1093 struct rte_flow *flow, 1094 const struct rte_flow_action *actions, 1095 void *data, 1096 struct rte_flow_error *error); 1097 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t) 1098 (struct rte_eth_dev *dev); 1099 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev, 1100 struct mlx5_meter_domains_infos *tbls); 1101 typedef uint32_t (*mlx5_flow_mtr_alloc_t) 1102 (struct rte_eth_dev *dev); 1103 typedef void (*mlx5_flow_mtr_free_t)(struct rte_eth_dev *dev, 1104 uint32_t mtr_idx); 1105 typedef uint32_t (*mlx5_flow_counter_alloc_t) 1106 (struct rte_eth_dev *dev); 1107 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev, 1108 uint32_t cnt); 1109 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev, 1110 uint32_t cnt, 1111 bool clear, uint64_t *pkts, 1112 uint64_t *bytes); 1113 typedef int (*mlx5_flow_get_aged_flows_t) 1114 (struct rte_eth_dev *dev, 1115 void **context, 1116 uint32_t nb_contexts, 1117 struct rte_flow_error *error); 1118 typedef int (*mlx5_flow_action_validate_t) 1119 (struct rte_eth_dev *dev, 1120 const struct rte_flow_indir_action_conf *conf, 1121 const struct rte_flow_action *action, 1122 struct rte_flow_error *error); 1123 typedef struct rte_flow_action_handle *(*mlx5_flow_action_create_t) 1124 (struct rte_eth_dev *dev, 1125 const struct rte_flow_indir_action_conf *conf, 1126 const struct rte_flow_action *action, 1127 struct rte_flow_error *error); 1128 typedef int (*mlx5_flow_action_destroy_t) 1129 (struct rte_eth_dev *dev, 1130 struct rte_flow_action_handle *action, 1131 struct rte_flow_error *error); 1132 typedef int (*mlx5_flow_action_update_t) 1133 (struct rte_eth_dev *dev, 1134 struct rte_flow_action_handle *action, 1135 const void *update, 1136 struct rte_flow_error *error); 1137 typedef int (*mlx5_flow_action_query_t) 1138 (struct rte_eth_dev *dev, 1139 const struct rte_flow_action_handle *action, 1140 void *data, 1141 struct rte_flow_error *error); 1142 typedef int (*mlx5_flow_sync_domain_t) 1143 (struct rte_eth_dev *dev, 1144 uint32_t domains, 1145 uint32_t flags); 1146 1147 struct mlx5_flow_driver_ops { 1148 mlx5_flow_validate_t validate; 1149 mlx5_flow_prepare_t prepare; 1150 mlx5_flow_translate_t translate; 1151 mlx5_flow_apply_t apply; 1152 mlx5_flow_remove_t remove; 1153 mlx5_flow_destroy_t destroy; 1154 mlx5_flow_query_t query; 1155 mlx5_flow_create_mtr_tbls_t create_mtr_tbls; 1156 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls; 1157 mlx5_flow_mtr_alloc_t create_meter; 1158 mlx5_flow_mtr_free_t free_meter; 1159 mlx5_flow_counter_alloc_t counter_alloc; 1160 mlx5_flow_counter_free_t counter_free; 1161 mlx5_flow_counter_query_t counter_query; 1162 mlx5_flow_get_aged_flows_t get_aged_flows; 1163 mlx5_flow_action_validate_t action_validate; 1164 mlx5_flow_action_create_t action_create; 1165 mlx5_flow_action_destroy_t action_destroy; 1166 mlx5_flow_action_update_t action_update; 1167 mlx5_flow_action_query_t action_query; 1168 mlx5_flow_sync_domain_t sync_domain; 1169 }; 1170 1171 /* mlx5_flow.c */ 1172 1173 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void); 1174 __extension__ 1175 struct flow_grp_info { 1176 uint64_t external:1; 1177 uint64_t transfer:1; 1178 uint64_t fdb_def_rule:1; 1179 /* force standard group translation */ 1180 uint64_t std_tbl_fix:1; 1181 uint64_t skip_scale:2; 1182 }; 1183 1184 static inline bool 1185 tunnel_use_standard_attr_group_translate 1186 (struct rte_eth_dev *dev, 1187 const struct mlx5_flow_tunnel *tunnel, 1188 const struct rte_flow_attr *attr, 1189 const struct rte_flow_item items[], 1190 const struct rte_flow_action actions[]) 1191 { 1192 bool verdict; 1193 1194 if (!is_tunnel_offload_active(dev)) 1195 /* no tunnel offload API */ 1196 verdict = true; 1197 else if (tunnel) { 1198 /* 1199 * OvS will use jump to group 0 in tunnel steer rule. 1200 * If tunnel steer rule starts from group 0 (attr.group == 0) 1201 * that 0 group must be translated with standard method. 1202 * attr.group == 0 in tunnel match rule translated with tunnel 1203 * method 1204 */ 1205 verdict = !attr->group && 1206 is_flow_tunnel_steer_rule(dev, attr, items, actions); 1207 } else { 1208 /* 1209 * non-tunnel group translation uses standard method for 1210 * root group only: attr.group == 0 1211 */ 1212 verdict = !attr->group; 1213 } 1214 1215 return verdict; 1216 } 1217 1218 /** 1219 * Get DV flow aso meter by index. 1220 * 1221 * @param[in] dev 1222 * Pointer to the Ethernet device structure. 1223 * @param[in] idx 1224 * mlx5 flow aso meter index in the container. 1225 * @param[out] ppool 1226 * mlx5 flow aso meter pool in the container, 1227 * 1228 * @return 1229 * Pointer to the aso meter, NULL otherwise. 1230 */ 1231 static inline struct mlx5_aso_mtr * 1232 mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx) 1233 { 1234 struct mlx5_aso_mtr_pool *pool; 1235 struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng; 1236 1237 /* Decrease to original index. */ 1238 idx--; 1239 MLX5_ASSERT(idx / MLX5_ASO_MTRS_PER_POOL < mtrmng->n); 1240 pool = mtrmng->pools[idx / MLX5_ASO_MTRS_PER_POOL]; 1241 return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL]; 1242 } 1243 1244 int mlx5_flow_group_to_table(struct rte_eth_dev *dev, 1245 const struct mlx5_flow_tunnel *tunnel, 1246 uint32_t group, uint32_t *table, 1247 const struct flow_grp_info *flags, 1248 struct rte_flow_error *error); 1249 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1250 int tunnel, uint64_t layer_types, 1251 uint64_t hash_fields); 1252 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 1253 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 1254 uint32_t subpriority); 1255 uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1256 const struct rte_flow_attr *attr); 1257 uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1258 const struct rte_flow_attr *attr, 1259 uint32_t subpriority); 1260 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1261 enum mlx5_feature_name feature, 1262 uint32_t id, 1263 struct rte_flow_error *error); 1264 const struct rte_flow_action *mlx5_flow_find_action 1265 (const struct rte_flow_action *actions, 1266 enum rte_flow_action_type action); 1267 int mlx5_validate_action_rss(struct rte_eth_dev *dev, 1268 const struct rte_flow_action *action, 1269 struct rte_flow_error *error); 1270 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev, 1271 const struct rte_flow_attr *attr, 1272 struct rte_flow_error *error); 1273 int mlx5_flow_validate_action_drop(uint64_t action_flags, 1274 const struct rte_flow_attr *attr, 1275 struct rte_flow_error *error); 1276 int mlx5_flow_validate_action_flag(uint64_t action_flags, 1277 const struct rte_flow_attr *attr, 1278 struct rte_flow_error *error); 1279 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1280 uint64_t action_flags, 1281 const struct rte_flow_attr *attr, 1282 struct rte_flow_error *error); 1283 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1284 uint64_t action_flags, 1285 struct rte_eth_dev *dev, 1286 const struct rte_flow_attr *attr, 1287 struct rte_flow_error *error); 1288 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1289 uint64_t action_flags, 1290 struct rte_eth_dev *dev, 1291 const struct rte_flow_attr *attr, 1292 uint64_t item_flags, 1293 struct rte_flow_error *error); 1294 int mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1295 const struct rte_flow_attr *attr, 1296 struct rte_flow_error *error); 1297 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1298 const struct rte_flow_attr *attributes, 1299 struct rte_flow_error *error); 1300 int mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1301 const uint8_t *mask, 1302 const uint8_t *nic_mask, 1303 unsigned int size, 1304 bool range_accepted, 1305 struct rte_flow_error *error); 1306 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1307 uint64_t item_flags, bool ext_vlan_sup, 1308 struct rte_flow_error *error); 1309 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1310 uint64_t item_flags, 1311 uint8_t target_protocol, 1312 struct rte_flow_error *error); 1313 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1314 uint64_t item_flags, 1315 const struct rte_flow_item *gre_item, 1316 struct rte_flow_error *error); 1317 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1318 uint64_t item_flags, 1319 uint64_t last_item, 1320 uint16_t ether_type, 1321 const struct rte_flow_item_ipv4 *acc_mask, 1322 bool range_accepted, 1323 struct rte_flow_error *error); 1324 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1325 uint64_t item_flags, 1326 uint64_t last_item, 1327 uint16_t ether_type, 1328 const struct rte_flow_item_ipv6 *acc_mask, 1329 struct rte_flow_error *error); 1330 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev, 1331 const struct rte_flow_item *item, 1332 uint64_t item_flags, 1333 uint64_t prev_layer, 1334 struct rte_flow_error *error); 1335 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1336 uint64_t item_flags, 1337 uint8_t target_protocol, 1338 const struct rte_flow_item_tcp *flow_mask, 1339 struct rte_flow_error *error); 1340 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1341 uint64_t item_flags, 1342 uint8_t target_protocol, 1343 struct rte_flow_error *error); 1344 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1345 uint64_t item_flags, 1346 struct rte_eth_dev *dev, 1347 struct rte_flow_error *error); 1348 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1349 uint64_t item_flags, 1350 struct rte_flow_error *error); 1351 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1352 uint64_t item_flags, 1353 struct rte_eth_dev *dev, 1354 struct rte_flow_error *error); 1355 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1356 uint64_t item_flags, 1357 uint8_t target_protocol, 1358 struct rte_flow_error *error); 1359 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1360 uint64_t item_flags, 1361 uint8_t target_protocol, 1362 struct rte_flow_error *error); 1363 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1364 uint64_t item_flags, 1365 uint8_t target_protocol, 1366 struct rte_flow_error *error); 1367 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 1368 uint64_t item_flags, 1369 struct rte_eth_dev *dev, 1370 struct rte_flow_error *error); 1371 int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 1372 uint64_t last_item, 1373 const struct rte_flow_item *geneve_item, 1374 struct rte_eth_dev *dev, 1375 struct rte_flow_error *error); 1376 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 1377 uint64_t item_flags, 1378 uint64_t last_item, 1379 uint16_t ether_type, 1380 const struct rte_flow_item_ecpri *acc_mask, 1381 struct rte_flow_error *error); 1382 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls 1383 (struct rte_eth_dev *dev); 1384 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 1385 struct mlx5_meter_domains_infos *tbl); 1386 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1387 struct rte_mtr_error *error); 1388 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); 1389 int mlx5_action_handle_flush(struct rte_eth_dev *dev); 1390 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); 1391 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); 1392 1393 /* Hash list callbacks for flow tables: */ 1394 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list, 1395 uint64_t key, void *entry_ctx); 1396 int flow_dv_tbl_match_cb(struct mlx5_hlist *list, 1397 struct mlx5_hlist_entry *entry, uint64_t key, 1398 void *cb_ctx); 1399 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list, 1400 struct mlx5_hlist_entry *entry); 1401 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev, 1402 uint32_t table_level, uint8_t egress, uint8_t transfer, 1403 bool external, const struct mlx5_flow_tunnel *tunnel, 1404 uint32_t group_id, uint8_t dummy, 1405 uint32_t table_id, struct rte_flow_error *error); 1406 1407 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list, 1408 uint64_t key, void *cb_ctx); 1409 int flow_dv_tag_match_cb(struct mlx5_hlist *list, 1410 struct mlx5_hlist_entry *entry, uint64_t key, 1411 void *cb_ctx); 1412 void flow_dv_tag_remove_cb(struct mlx5_hlist *list, 1413 struct mlx5_hlist_entry *entry); 1414 1415 int flow_dv_modify_match_cb(struct mlx5_hlist *list, 1416 struct mlx5_hlist_entry *entry, 1417 uint64_t key, void *cb_ctx); 1418 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list, 1419 uint64_t key, void *ctx); 1420 void flow_dv_modify_remove_cb(struct mlx5_hlist *list, 1421 struct mlx5_hlist_entry *entry); 1422 1423 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list, 1424 uint64_t key, void *ctx); 1425 int flow_dv_mreg_match_cb(struct mlx5_hlist *list, 1426 struct mlx5_hlist_entry *entry, uint64_t key, 1427 void *cb_ctx); 1428 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list, 1429 struct mlx5_hlist_entry *entry); 1430 1431 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list, 1432 struct mlx5_hlist_entry *entry, 1433 uint64_t key, void *cb_ctx); 1434 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list, 1435 uint64_t key, void *cb_ctx); 1436 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list, 1437 struct mlx5_hlist_entry *entry); 1438 1439 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list, 1440 struct mlx5_cache_entry *entry, void *ctx); 1441 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list, 1442 struct mlx5_cache_entry *entry, void *ctx); 1443 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list, 1444 struct mlx5_cache_entry *entry); 1445 1446 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list, 1447 struct mlx5_cache_entry *entry, void *cb_ctx); 1448 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list, 1449 struct mlx5_cache_entry *entry, void *cb_ctx); 1450 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list, 1451 struct mlx5_cache_entry *entry); 1452 1453 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list, 1454 struct mlx5_cache_entry *entry, void *cb_ctx); 1455 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb 1456 (struct mlx5_cache_list *list, 1457 struct mlx5_cache_entry *entry, void *cb_ctx); 1458 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list, 1459 struct mlx5_cache_entry *entry); 1460 1461 int flow_dv_sample_match_cb(struct mlx5_cache_list *list, 1462 struct mlx5_cache_entry *entry, void *cb_ctx); 1463 struct mlx5_cache_entry *flow_dv_sample_create_cb 1464 (struct mlx5_cache_list *list, 1465 struct mlx5_cache_entry *entry, void *cb_ctx); 1466 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list, 1467 struct mlx5_cache_entry *entry); 1468 1469 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list, 1470 struct mlx5_cache_entry *entry, void *cb_ctx); 1471 struct mlx5_cache_entry *flow_dv_dest_array_create_cb 1472 (struct mlx5_cache_list *list, 1473 struct mlx5_cache_entry *entry, void *cb_ctx); 1474 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list, 1475 struct mlx5_cache_entry *entry); 1476 struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev, 1477 uint32_t age_idx); 1478 int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev, 1479 const struct rte_flow_item *item, 1480 struct rte_flow_error *error); 1481 void flow_release_workspace(void *data); 1482 int mlx5_flow_os_init_workspace_once(void); 1483 void *mlx5_flow_os_get_specific_workspace(void); 1484 int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data); 1485 void mlx5_flow_os_release_workspace(void); 1486 uint32_t mlx5_flow_mtr_alloc(struct rte_eth_dev *dev); 1487 void mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx); 1488 #endif /* RTE_PMD_MLX5_FLOW_H_ */ 1489