1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <netinet/in.h> 14 #include <sys/queue.h> 15 16 #include <rte_pci.h> 17 #include <rte_ether.h> 18 #include <rte_ethdev_driver.h> 19 #include <rte_rwlock.h> 20 #include <rte_interrupts.h> 21 #include <rte_errno.h> 22 #include <rte_flow.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 30 #include "mlx5_defs.h" 31 #include "mlx5_utils.h" 32 #include "mlx5_os.h" 33 #include "mlx5_autoconf.h" 34 35 36 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 37 38 enum mlx5_ipool_index { 39 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 40 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 41 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 42 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 43 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 44 MLX5_IPOOL_JUMP, /* Pool for jump resource. */ 45 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 46 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 47 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 48 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 49 #endif 50 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 51 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 52 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 53 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 54 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 55 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 56 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 57 MLX5_IPOOL_MAX, 58 }; 59 60 /* 61 * There are three reclaim memory mode supported. 62 * 0(none) means no memory reclaim. 63 * 1(light) means only PMD level reclaim. 64 * 2(aggressive) means both PMD and rdma-core level reclaim. 65 */ 66 enum mlx5_reclaim_mem_mode { 67 MLX5_RCM_NONE, /* Don't reclaim memory. */ 68 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 69 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 70 }; 71 72 /* Hash and cache list callback context. */ 73 struct mlx5_flow_cb_ctx { 74 struct rte_eth_dev *dev; 75 struct rte_flow_error *error; 76 void *data; 77 }; 78 79 /* Device attributes used in mlx5 PMD */ 80 struct mlx5_dev_attr { 81 uint64_t device_cap_flags_ex; 82 int max_qp_wr; 83 int max_sge; 84 int max_cq; 85 int max_qp; 86 int max_cqe; 87 uint32_t max_pd; 88 uint32_t max_mr; 89 uint32_t max_srq; 90 uint32_t max_srq_wr; 91 uint32_t raw_packet_caps; 92 uint32_t max_rwq_indirection_table_size; 93 uint32_t max_tso; 94 uint32_t tso_supported_qpts; 95 uint64_t flags; 96 uint64_t comp_mask; 97 uint32_t sw_parsing_offloads; 98 uint32_t min_single_stride_log_num_of_bytes; 99 uint32_t max_single_stride_log_num_of_bytes; 100 uint32_t min_single_wqe_log_num_of_strides; 101 uint32_t max_single_wqe_log_num_of_strides; 102 uint32_t stride_supported_qpts; 103 uint32_t tunnel_offloads_caps; 104 char fw_ver[64]; 105 }; 106 107 /** Data associated with devices to spawn. */ 108 struct mlx5_dev_spawn_data { 109 uint32_t ifindex; /**< Network interface index. */ 110 uint32_t max_port; /**< Device maximal port index. */ 111 uint32_t phys_port; /**< Device physical port index. */ 112 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 113 struct mlx5_switch_info info; /**< Switch information. */ 114 void *phys_dev; /**< Associated physical device. */ 115 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 116 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 117 }; 118 119 /** Key string for IPC. */ 120 #define MLX5_MP_NAME "net_mlx5_mp" 121 122 123 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 124 125 /* Shared data between primary and secondary processes. */ 126 struct mlx5_shared_data { 127 rte_spinlock_t lock; 128 /* Global spinlock for primary and secondary processes. */ 129 int init_done; /* Whether primary has done initialization. */ 130 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 131 struct mlx5_dev_list mem_event_cb_list; 132 rte_rwlock_t mem_event_rwlock; 133 }; 134 135 /* Per-process data structure, not visible to other processes. */ 136 struct mlx5_local_data { 137 int init_done; /* Whether a secondary has done initialization. */ 138 }; 139 140 extern struct mlx5_shared_data *mlx5_shared_data; 141 142 /* Dev ops structs */ 143 extern const struct eth_dev_ops mlx5_os_dev_ops; 144 extern const struct eth_dev_ops mlx5_os_dev_sec_ops; 145 extern const struct eth_dev_ops mlx5_os_dev_ops_isolate; 146 147 struct mlx5_counter_ctrl { 148 /* Name of the counter. */ 149 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 150 /* Name of the counter on the device table. */ 151 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 152 uint32_t dev:1; /**< Nonzero for dev counters. */ 153 }; 154 155 struct mlx5_xstats_ctrl { 156 /* Number of device stats. */ 157 uint16_t stats_n; 158 /* Number of device stats identified by PMD. */ 159 uint16_t mlx5_stats_n; 160 /* Index in the device counters table. */ 161 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 162 uint64_t base[MLX5_MAX_XSTATS]; 163 uint64_t xstats[MLX5_MAX_XSTATS]; 164 uint64_t hw_stats[MLX5_MAX_XSTATS]; 165 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 166 }; 167 168 struct mlx5_stats_ctrl { 169 /* Base for imissed counter. */ 170 uint64_t imissed_base; 171 uint64_t imissed; 172 }; 173 174 /* Default PMD specific parameter value. */ 175 #define MLX5_ARG_UNSET (-1) 176 177 #define MLX5_LRO_SUPPORTED(dev) \ 178 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 179 180 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 181 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 182 183 /* Maximal size of aggregated LRO packet. */ 184 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 185 186 /* Maximal number of segments to split. */ 187 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 188 189 /* LRO configurations structure. */ 190 struct mlx5_lro_config { 191 uint32_t supported:1; /* Whether LRO is supported. */ 192 uint32_t timeout; /* User configuration. */ 193 }; 194 195 /* 196 * Device configuration structure. 197 * 198 * Merged configuration from: 199 * 200 * - Device capabilities, 201 * - User device parameters disabled features. 202 */ 203 struct mlx5_dev_config { 204 unsigned int hw_csum:1; /* Checksum offload is supported. */ 205 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 206 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 207 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 208 unsigned int hw_padding:1; /* End alignment padding is supported. */ 209 unsigned int vf:1; /* This is a VF. */ 210 unsigned int tunnel_en:1; 211 /* Whether tunnel stateless offloads are supported. */ 212 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 213 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 214 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 215 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 216 unsigned int tso:1; /* Whether TSO is supported. */ 217 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 218 unsigned int mr_ext_memseg_en:1; 219 /* Whether memseg should be extended for MR creation. */ 220 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 221 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 222 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 223 unsigned int dv_flow_en:1; /* Enable DV flow. */ 224 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 225 unsigned int lacp_by_user:1; 226 /* Enable user to manage LACP traffic. */ 227 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 228 unsigned int devx:1; /* Whether devx interface is available or not. */ 229 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 230 unsigned int reclaim_mode:2; /* Memory reclaim mode. */ 231 unsigned int rt_timestamp:1; /* realtime timestamp format. */ 232 unsigned int sys_mem_en:1; /* The default memory allocator. */ 233 unsigned int decap_en:1; /* Whether decap will be used or not. */ 234 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ 235 struct { 236 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 237 unsigned int stride_num_n; /* Number of strides. */ 238 unsigned int stride_size_n; /* Size of a stride. */ 239 unsigned int min_stride_size_n; /* Min size of a stride. */ 240 unsigned int max_stride_size_n; /* Max size of a stride. */ 241 unsigned int max_memcpy_len; 242 /* Maximum packet size to memcpy Rx packets. */ 243 unsigned int min_rxqs_num; 244 /* Rx queue count threshold to enable MPRQ. */ 245 } mprq; /* Configurations for Multi-Packet RQ. */ 246 int mps; /* Multi-packet send supported mode. */ 247 int dbnc; /* Skip doorbell register write barrier. */ 248 unsigned int flow_prio; /* Number of flow priorities. */ 249 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 250 /* Availibility of mreg_c's. */ 251 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 252 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 253 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 254 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 255 int txqs_inline; /* Queue number threshold for inlining. */ 256 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 257 int txq_inline_max; /* Max packet size for inlining with SEND. */ 258 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 259 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 260 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 261 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 262 struct mlx5_lro_config lro; /* LRO configuration. */ 263 }; 264 265 266 /* Structure for VF VLAN workaround. */ 267 struct mlx5_vf_vlan { 268 uint32_t tag:12; 269 uint32_t created:1; 270 }; 271 272 /* Flow drop context necessary due to Verbs API. */ 273 struct mlx5_drop { 274 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 275 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 276 }; 277 278 #define MLX5_COUNTERS_PER_POOL 512 279 #define MLX5_MAX_PENDING_QUERIES 4 280 #define MLX5_CNT_CONTAINER_RESIZE 64 281 #define MLX5_CNT_SHARED_OFFSET 0x80000000 282 #define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET)) 283 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 284 MLX5_CNT_BATCH_OFFSET) 285 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 286 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 287 288 #define MLX5_CNT_LEN(pool) \ 289 (MLX5_CNT_SIZE + \ 290 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 291 #define MLX5_POOL_GET_CNT(pool, index) \ 292 ((struct mlx5_flow_counter *) \ 293 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 294 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 295 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 296 MLX5_CNT_LEN(pool))) 297 /* 298 * The pool index and offset of counter in the pool array makes up the 299 * counter index. In case the counter is from pool 0 and offset 0, it 300 * should plus 1 to avoid index 0, since 0 means invalid counter index 301 * currently. 302 */ 303 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 304 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 305 #define MLX5_CNT_TO_AGE(cnt) \ 306 ((struct mlx5_age_param *)((cnt) + 1)) 307 /* 308 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 309 * defines. The pool size is 512, pool index should never reach 310 * INT16_MAX. 311 */ 312 #define POOL_IDX_INVALID UINT16_MAX 313 314 /* Age status. */ 315 enum { 316 AGE_FREE, /* Initialized state. */ 317 AGE_CANDIDATE, /* Counter assigned to flows. */ 318 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 319 }; 320 321 enum mlx5_counter_type { 322 MLX5_COUNTER_TYPE_ORIGIN, 323 MLX5_COUNTER_TYPE_AGE, 324 MLX5_COUNTER_TYPE_MAX, 325 }; 326 327 /* Counter age parameter. */ 328 struct mlx5_age_param { 329 uint16_t state; /**< Age state (atomically accessed). */ 330 uint16_t port_id; /**< Port id of the counter. */ 331 uint32_t timeout:24; /**< Aging timeout in seconds. */ 332 uint32_t sec_since_last_hit; 333 /**< Time in seconds since last hit (atomically accessed). */ 334 void *context; /**< Flow counter age context. */ 335 }; 336 337 struct flow_counter_stats { 338 uint64_t hits; 339 uint64_t bytes; 340 }; 341 342 /* Shared counters information for counters. */ 343 struct mlx5_flow_counter_shared { 344 uint32_t id; /**< User counter ID. */ 345 }; 346 347 /* Shared counter configuration. */ 348 struct mlx5_shared_counter_conf { 349 struct rte_eth_dev *dev; /* The device shared counter belongs to. */ 350 uint32_t id; /* The shared counter ID. */ 351 }; 352 353 struct mlx5_flow_counter_pool; 354 /* Generic counters information. */ 355 struct mlx5_flow_counter { 356 union { 357 /* 358 * User-defined counter shared info is only used during 359 * counter active time. And aging counter sharing is not 360 * supported, so active shared counter will not be chained 361 * to the aging list. For shared counter, only when it is 362 * released, the TAILQ entry memory will be used, at that 363 * time, shared memory is not used anymore. 364 * 365 * Similarly to none-batch counter dcs, since it doesn't 366 * support aging, while counter is allocated, the entry 367 * memory is not used anymore. In this case, as bytes 368 * memory is used only when counter is allocated, and 369 * entry memory is used only when counter is free. The 370 * dcs pointer can be saved to these two different place 371 * at different stage. It will eliminate the individual 372 * counter extend struct. 373 */ 374 TAILQ_ENTRY(mlx5_flow_counter) next; 375 /**< Pointer to the next flow counter structure. */ 376 struct { 377 struct mlx5_flow_counter_shared shared_info; 378 /**< Shared counter information. */ 379 void *dcs_when_active; 380 /* 381 * For non-batch mode, the dcs will be saved 382 * here when the counter is free. 383 */ 384 }; 385 }; 386 union { 387 uint64_t hits; /**< Reset value of hits packets. */ 388 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 389 }; 390 union { 391 uint64_t bytes; /**< Reset value of bytes. */ 392 void *dcs_when_free; 393 /* 394 * For non-batch mode, the dcs will be saved here 395 * when the counter is free. 396 */ 397 }; 398 void *action; /**< Pointer to the dv action. */ 399 }; 400 401 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 402 403 /* Generic counter pool structure - query is in pool resolution. */ 404 struct mlx5_flow_counter_pool { 405 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 406 struct mlx5_counters counters[2]; /* Free counter list. */ 407 struct mlx5_devx_obj *min_dcs; 408 /* The devx object of the minimum counter ID. */ 409 uint64_t time_of_last_age_check; 410 /* System time (from rte_rdtsc()) read in the last aging check. */ 411 uint32_t index:30; /* Pool index in container. */ 412 uint32_t is_aged:1; /* Pool with aging counter. */ 413 volatile uint32_t query_gen:1; /* Query round. */ 414 rte_spinlock_t sl; /* The pool lock. */ 415 rte_spinlock_t csl; /* The pool counter free list lock. */ 416 struct mlx5_counter_stats_raw *raw; 417 struct mlx5_counter_stats_raw *raw_hw; 418 /* The raw on HW working. */ 419 }; 420 421 /* Memory management structure for group of counter statistics raws. */ 422 struct mlx5_counter_stats_mem_mng { 423 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 424 struct mlx5_counter_stats_raw *raws; 425 struct mlx5_devx_obj *dm; 426 void *umem; 427 }; 428 429 /* Raw memory structure for the counter statistics values of a pool. */ 430 struct mlx5_counter_stats_raw { 431 LIST_ENTRY(mlx5_counter_stats_raw) next; 432 struct mlx5_counter_stats_mem_mng *mem_mng; 433 volatile struct flow_counter_stats *data; 434 }; 435 436 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 437 438 /* Counter global management structure. */ 439 struct mlx5_flow_counter_mng { 440 volatile uint16_t n_valid; /* Number of valid pools. */ 441 uint16_t n; /* Number of pools. */ 442 uint16_t last_pool_idx; /* Last used pool index */ 443 int min_id; /* The minimum counter ID in the pools. */ 444 int max_id; /* The maximum counter ID in the pools. */ 445 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 446 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 447 /* The counter free list lock. */ 448 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 449 /* Free counter list. */ 450 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 451 struct mlx5_counter_stats_mem_mng *mem_mng; 452 /* Hold the memory management for the next allocated pools raws. */ 453 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 454 uint8_t pending_queries; 455 uint16_t pool_index; 456 uint8_t query_thread_on; 457 bool relaxed_ordering_read; 458 bool relaxed_ordering_write; 459 bool counter_fallback; /* Use counter fallback management. */ 460 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 461 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 462 }; 463 464 /* ASO structures. */ 465 #define MLX5_ASO_QUEUE_LOG_DESC 10 466 467 struct mlx5_aso_cq { 468 uint16_t log_desc_n; 469 uint32_t cq_ci:24; 470 struct mlx5_devx_obj *cq; 471 struct mlx5dv_devx_umem *umem_obj; 472 union { 473 volatile void *umem_buf; 474 volatile struct mlx5_cqe *cqes; 475 }; 476 volatile uint32_t *db_rec; 477 uint64_t errors; 478 }; 479 480 struct mlx5_aso_devx_mr { 481 void *buf; 482 uint64_t length; 483 struct mlx5dv_devx_umem *umem; 484 struct mlx5_devx_obj *mkey; 485 bool is_indirect; 486 }; 487 488 struct mlx5_aso_sq_elem { 489 struct mlx5_aso_age_pool *pool; 490 uint16_t burst_size; 491 }; 492 493 struct mlx5_aso_sq { 494 uint16_t log_desc_n; 495 struct mlx5_aso_cq cq; 496 struct mlx5_devx_obj *sq; 497 struct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */ 498 union { 499 volatile void *umem_buf; 500 volatile struct mlx5_aso_wqe *wqes; 501 }; 502 volatile uint32_t *db_rec; 503 volatile uint64_t *uar_addr; 504 struct mlx5_aso_devx_mr mr; 505 uint16_t pi; 506 uint32_t head; 507 uint32_t tail; 508 uint32_t sqn; 509 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 510 uint16_t next; /* Pool index of the next pool to query. */ 511 }; 512 513 struct mlx5_aso_age_action { 514 LIST_ENTRY(mlx5_aso_age_action) next; 515 void *dr_action; 516 uint32_t refcnt; 517 /* Following fields relevant only when action is active. */ 518 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 519 struct mlx5_age_param age_params; 520 }; 521 522 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 523 524 struct mlx5_aso_age_pool { 525 struct mlx5_devx_obj *flow_hit_aso_obj; 526 uint16_t index; /* Pool index in pools array. */ 527 uint64_t time_of_last_age_check; /* In seconds. */ 528 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 529 }; 530 531 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 532 533 struct mlx5_aso_age_mng { 534 struct mlx5_aso_age_pool **pools; 535 uint16_t n; /* Total number of pools. */ 536 uint16_t next; /* Number of pools in use, index of next free pool. */ 537 rte_spinlock_t resize_sl; /* Lock for resize objects. */ 538 rte_spinlock_t free_sl; /* Lock for free list access. */ 539 struct aso_age_list free; /* Free age actions list - ready to use. */ 540 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 541 }; 542 543 #define MLX5_AGE_EVENT_NEW 1 544 #define MLX5_AGE_TRIGGER 2 545 #define MLX5_AGE_SET(age_info, BIT) \ 546 ((age_info)->flags |= (1 << (BIT))) 547 #define MLX5_AGE_GET(age_info, BIT) \ 548 ((age_info)->flags & (1 << (BIT))) 549 #define GET_PORT_AGE_INFO(priv) \ 550 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 551 /* Current time in seconds. */ 552 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 553 554 /* Aging information for per port. */ 555 struct mlx5_age_info { 556 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 557 struct mlx5_counters aged_counters; /* Aged counter list. */ 558 struct aso_age_list aged_aso; /* Aged ASO actions list. */ 559 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 560 }; 561 562 /* Per port data of shared IB device. */ 563 struct mlx5_dev_shared_port { 564 uint32_t ih_port_id; 565 uint32_t devx_ih_port_id; 566 /* 567 * Interrupt handler port_id. Used by shared interrupt 568 * handler to find the corresponding rte_eth device 569 * by IB port index. If value is equal or greater 570 * RTE_MAX_ETHPORTS it means there is no subhandler 571 * installed for specified IB port index. 572 */ 573 struct mlx5_age_info age_info; 574 /* Aging information for per port. */ 575 }; 576 577 /* Table key of the hash organization. */ 578 union mlx5_flow_tbl_key { 579 struct { 580 /* Table ID should be at the lowest address. */ 581 uint32_t table_id; /**< ID of the table. */ 582 uint16_t dummy; /**< Dummy table for DV API. */ 583 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */ 584 uint8_t direction; /**< 1 - egress, 0 - ingress. */ 585 }; 586 uint64_t v64; /**< full 64bits value of key */ 587 }; 588 589 /* Table structure. */ 590 struct mlx5_flow_tbl_resource { 591 void *obj; /**< Pointer to DR table object. */ 592 uint32_t refcnt; /**< Reference counter. */ 593 }; 594 595 #define MLX5_MAX_TABLES UINT16_MAX 596 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 597 /* Reserve the last two tables for metadata register copy. */ 598 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 599 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 600 /* Tables for metering splits should be added here. */ 601 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3) 602 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4) 603 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_METER 604 #define MLX5_MAX_TABLES_FDB UINT16_MAX 605 #define MLX5_FLOW_TABLE_FACTOR 10 606 607 /* ID generation structure. */ 608 struct mlx5_flow_id_pool { 609 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 610 uint32_t base_index; 611 /**< The next index that can be used without any free elements. */ 612 uint32_t *curr; /**< Pointer to the index to pop. */ 613 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 614 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 615 }; 616 617 /* Tx pacing queue structure - for Clock and Rearm queues. */ 618 struct mlx5_txpp_wq { 619 /* Completion Queue related data.*/ 620 struct mlx5_devx_obj *cq; 621 void *cq_umem; 622 union { 623 volatile void *cq_buf; 624 volatile struct mlx5_cqe *cqes; 625 }; 626 volatile uint32_t *cq_dbrec; 627 uint32_t cq_ci:24; 628 uint32_t arm_sn:2; 629 /* Send Queue related data.*/ 630 struct mlx5_devx_obj *sq; 631 void *sq_umem; 632 union { 633 volatile void *sq_buf; 634 volatile struct mlx5_wqe *wqes; 635 }; 636 uint16_t sq_size; /* Number of WQEs in the queue. */ 637 uint16_t sq_ci; /* Next WQE to execute. */ 638 volatile uint32_t *sq_dbrec; 639 }; 640 641 /* Tx packet pacing internal timestamp. */ 642 struct mlx5_txpp_ts { 643 uint64_t ci_ts; 644 uint64_t ts; 645 }; 646 647 /* Tx packet pacing structure. */ 648 struct mlx5_dev_txpp { 649 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 650 uint32_t refcnt; /* Pacing reference counter. */ 651 uint32_t freq; /* Timestamp frequency, Hz. */ 652 uint32_t tick; /* Completion tick duration in nanoseconds. */ 653 uint32_t test; /* Packet pacing test mode. */ 654 int32_t skew; /* Scheduling skew. */ 655 struct rte_intr_handle intr_handle; /* Periodic interrupt. */ 656 void *echan; /* Event Channel. */ 657 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 658 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 659 void *pp; /* Packet pacing context. */ 660 uint16_t pp_id; /* Packet pacing context index. */ 661 uint16_t ts_n; /* Number of captured timestamps. */ 662 uint16_t ts_p; /* Pointer to statisticks timestamp. */ 663 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 664 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 665 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 666 /* Statistics counters. */ 667 uint64_t err_miss_int; /* Missed service interrupt. */ 668 uint64_t err_rearm_queue; /* Rearm Queue errors. */ 669 uint64_t err_clock_queue; /* Clock Queue errors. */ 670 uint64_t err_ts_past; /* Timestamp in the past. */ 671 uint64_t err_ts_future; /* Timestamp in the distant future. */ 672 }; 673 674 /* Supported flex parser profile ID. */ 675 enum mlx5_flex_parser_profile_id { 676 MLX5_FLEX_PARSER_ECPRI_0 = 0, 677 MLX5_FLEX_PARSER_MAX = 8, 678 }; 679 680 /* Sample ID information of flex parser structure. */ 681 struct mlx5_flex_parser_profiles { 682 uint32_t num; /* Actual number of samples. */ 683 uint32_t ids[8]; /* Sample IDs for this profile. */ 684 uint8_t offset[8]; /* Bytes offset of each parser. */ 685 void *obj; /* Flex parser node object. */ 686 }; 687 688 /* 689 * Shared Infiniband device context for Master/Representors 690 * which belong to same IB device with multiple IB ports. 691 **/ 692 struct mlx5_dev_ctx_shared { 693 LIST_ENTRY(mlx5_dev_ctx_shared) next; 694 uint32_t refcnt; 695 uint16_t bond_dev; /* Bond primary device id. */ 696 uint32_t devx:1; /* Opened with DV. */ 697 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 698 uint32_t eqn; /* Event Queue number. */ 699 uint32_t max_port; /* Maximal IB device port index. */ 700 void *ctx; /* Verbs/DV/DevX context. */ 701 void *pd; /* Protection Domain. */ 702 uint32_t pdn; /* Protection Domain number. */ 703 uint32_t tdn; /* Transport Domain number. */ 704 char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */ 705 char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */ 706 struct mlx5_dev_attr device_attr; /* Device properties. */ 707 int numa_node; /* Numa node of backing physical device. */ 708 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; 709 /**< Called by memory event callback. */ 710 struct mlx5_mr_share_cache share_cache; 711 /* Packet pacing related structure. */ 712 struct mlx5_dev_txpp txpp; 713 /* Shared DV/DR flow data section. */ 714 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 715 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 716 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 717 void *fdb_domain; /* FDB Direct Rules name space handle. */ 718 void *rx_domain; /* RX Direct Rules name space handle. */ 719 void *tx_domain; /* TX Direct Rules name space handle. */ 720 #ifndef RTE_ARCH_64 721 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 722 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 723 /* UAR same-page access control required in 32bit implementations. */ 724 #endif 725 struct mlx5_hlist *flow_tbls; 726 struct mlx5_flow_tunnel_hub *tunnel_hub; 727 /* Direct Rules tables for FDB, NIC TX+RX */ 728 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ 729 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 730 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 731 struct mlx5_hlist *modify_cmds; 732 struct mlx5_hlist *tag_table; 733 struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */ 734 struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */ 735 struct mlx5_cache_list sample_action_list; /* List of sample actions. */ 736 struct mlx5_cache_list dest_array_list; 737 /* List of destination array actions. */ 738 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 739 void *default_miss_action; /* Default miss action. */ 740 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 741 /* Memory Pool for mlx5 flow resources. */ 742 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ 743 /* Shared interrupt handler section. */ 744 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 745 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 746 void *devx_comp; /* DEVX async comp obj. */ 747 struct mlx5_devx_obj *tis; /* TIS object. */ 748 struct mlx5_devx_obj *td; /* Transport domain. */ 749 void *tx_uar; /* Tx/packet pacing shared UAR. */ 750 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX]; 751 /* Flex parser profiles information. */ 752 void *devx_rx_uar; /* DevX UAR for Rx. */ 753 struct mlx5_aso_age_mng *aso_age_mng; 754 /* Management data for aging mechanism using ASO Flow Hit. */ 755 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 756 }; 757 758 /* Per-process private structure. */ 759 struct mlx5_proc_priv { 760 size_t uar_table_sz; 761 /* Size of UAR register table. */ 762 void *uar_table[]; 763 /* Table of UAR registers for each process. */ 764 }; 765 766 /* MTR profile list. */ 767 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 768 /* MTR list. */ 769 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); 770 771 /* RSS description. */ 772 struct mlx5_flow_rss_desc { 773 uint32_t level; 774 uint32_t queue_num; /**< Number of entries in @p queue. */ 775 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 776 uint64_t hash_fields; /* Verbs Hash fields. */ 777 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 778 uint32_t key_len; /**< RSS hash key len. */ 779 uint32_t tunnel; /**< Queue in tunnel. */ 780 uint32_t shared_rss; /**< Shared RSS index. */ 781 struct mlx5_ind_table_obj *ind_tbl; 782 /**< Indirection table for shared RSS hash RX queues. */ 783 union { 784 uint16_t *queue; /**< Destination queues. */ 785 const uint16_t *const_q; /**< Const pointer convert. */ 786 }; 787 }; 788 789 #define MLX5_PROC_PRIV(port_id) \ 790 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 791 792 /* Verbs/DevX Rx queue elements. */ 793 struct mlx5_rxq_obj { 794 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 795 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 796 int fd; /* File descriptor for event channel */ 797 RTE_STD_C11 798 union { 799 struct { 800 void *wq; /* Work Queue. */ 801 void *ibv_cq; /* Completion Queue. */ 802 void *ibv_channel; 803 }; 804 struct { 805 struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */ 806 struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */ 807 void *devx_channel; 808 }; 809 }; 810 }; 811 812 /* Indirection table. */ 813 struct mlx5_ind_table_obj { 814 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 815 uint32_t refcnt; /* Reference counter. */ 816 RTE_STD_C11 817 union { 818 void *ind_table; /**< Indirection table. */ 819 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 820 }; 821 uint32_t queues_n; /**< Number of queues in the list. */ 822 uint16_t *queues; /**< Queue list. */ 823 }; 824 825 /* Hash Rx queue. */ 826 __extension__ 827 struct mlx5_hrxq { 828 struct mlx5_cache_entry entry; /* Cache entry. */ 829 uint32_t standalone:1; /* This object used in shared action. */ 830 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 831 RTE_STD_C11 832 union { 833 void *qp; /* Verbs queue pair. */ 834 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 835 }; 836 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 837 void *action; /* DV QP action pointer. */ 838 #endif 839 uint64_t hash_fields; /* Verbs Hash fields. */ 840 uint32_t rss_key_len; /* Hash key length in bytes. */ 841 uint32_t idx; /* Hash Rx queue index. */ 842 uint8_t rss_key[]; /* Hash key. */ 843 }; 844 845 /* Verbs/DevX Tx queue elements. */ 846 struct mlx5_txq_obj { 847 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 848 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 849 RTE_STD_C11 850 union { 851 struct { 852 void *cq; /* Completion Queue. */ 853 void *qp; /* Queue Pair. */ 854 }; 855 struct { 856 struct mlx5_devx_obj *sq; 857 /* DevX object for Sx queue. */ 858 struct mlx5_devx_obj *tis; /* The TIS object. */ 859 }; 860 struct { 861 struct rte_eth_dev *dev; 862 struct mlx5_devx_obj *cq_devx; 863 void *cq_umem; 864 void *cq_buf; 865 int64_t cq_dbrec_offset; 866 struct mlx5_devx_dbr_page *cq_dbrec_page; 867 struct mlx5_devx_obj *sq_devx; 868 void *sq_umem; 869 void *sq_buf; 870 int64_t sq_dbrec_offset; 871 struct mlx5_devx_dbr_page *sq_dbrec_page; 872 }; 873 }; 874 }; 875 876 enum mlx5_rxq_modify_type { 877 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 878 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 879 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 880 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 881 }; 882 883 enum mlx5_txq_modify_type { 884 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 885 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 886 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 887 }; 888 889 /* HW objects operations structure. */ 890 struct mlx5_obj_ops { 891 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on); 892 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 893 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 894 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type); 895 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); 896 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 897 struct mlx5_ind_table_obj *ind_tbl); 898 int (*ind_table_modify)(struct rte_eth_dev *dev, 899 const unsigned int log_n, 900 const uint16_t *queues, const uint32_t queues_n, 901 struct mlx5_ind_table_obj *ind_tbl); 902 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 903 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 904 int tunnel __rte_unused); 905 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 906 const uint8_t *rss_key, 907 uint64_t hash_fields, 908 const struct mlx5_ind_table_obj *ind_tbl); 909 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 910 int (*drop_action_create)(struct rte_eth_dev *dev); 911 void (*drop_action_destroy)(struct rte_eth_dev *dev); 912 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 913 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 914 enum mlx5_txq_modify_type type, uint8_t dev_port); 915 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 916 }; 917 918 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 919 920 struct mlx5_priv { 921 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 922 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 923 uint32_t dev_port; /* Device port number. */ 924 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 925 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 926 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 927 /* Bit-field of MAC addresses owned by the PMD. */ 928 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 929 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 930 /* Device properties. */ 931 uint16_t mtu; /* Configured MTU. */ 932 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 933 unsigned int representor:1; /* Device is a port representor. */ 934 unsigned int master:1; /* Device is a E-Switch master. */ 935 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 936 unsigned int mtr_en:1; /* Whether support meter. */ 937 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 938 unsigned int sampler_en:1; /* Whether support sampler. */ 939 uint16_t domain_id; /* Switch domain identifier. */ 940 uint16_t vport_id; /* Associated VF vport index (if any). */ 941 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 942 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 943 int32_t representor_id; /* Port representor identifier. */ 944 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */ 945 unsigned int if_index; /* Associated kernel network device index. */ 946 uint32_t bond_ifindex; /**< Bond interface index. */ 947 char bond_name[IF_NAMESIZE]; /**< Bond interface name. */ 948 /* RX/TX queues. */ 949 unsigned int rxqs_n; /* RX queues array size. */ 950 unsigned int txqs_n; /* TX queues array size. */ 951 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 952 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 953 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 954 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 955 unsigned int (*reta_idx)[]; /* RETA index table. */ 956 unsigned int reta_idx_n; /* RETA index size. */ 957 struct mlx5_drop drop_queue; /* Flow drop queues. */ 958 uint32_t flows; /* RTE Flow rules. */ 959 uint32_t ctrl_flows; /* Control flow rules. */ 960 rte_spinlock_t flow_list_lock; 961 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 962 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 963 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 964 struct mlx5_cache_list hrxqs; /* Hash Rx queues. */ 965 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 966 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 967 /* Indirection tables. */ 968 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 969 /* Pointer to next element. */ 970 uint32_t refcnt; /**< Reference counter. */ 971 /**< Verbs modify header action object. */ 972 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 973 uint8_t max_lro_msg_size; 974 /* Tags resources cache. */ 975 uint32_t link_speed_capa; /* Link speed capabilities. */ 976 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 977 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 978 struct mlx5_dev_config config; /* Device configuration. */ 979 /* Context for Verbs allocator. */ 980 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 981 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 982 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ 983 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 984 struct mlx5_hlist *mreg_cp_tbl; 985 /* Hash table of Rx metadata register copy table. */ 986 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 987 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 988 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ 989 struct mlx5_flow_meters flow_meters; /* MTR list. */ 990 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 991 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 992 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 993 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 994 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 995 uint32_t rss_shared_actions; /* RSS shared actions. */ 996 }; 997 998 #define PORT_ID(priv) ((priv)->dev_data->port_id) 999 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 1000 1001 struct rte_hairpin_peer_info { 1002 uint32_t qp_id; 1003 uint32_t vhca_id; 1004 uint16_t peer_q; 1005 uint16_t tx_explicit; 1006 uint16_t manual_bind; 1007 }; 1008 1009 /* mlx5.c */ 1010 1011 int mlx5_getenv_int(const char *); 1012 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 1013 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 1014 struct rte_eth_udp_tunnel *udp_tunnel); 1015 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); 1016 int mlx5_dev_close(struct rte_eth_dev *dev); 1017 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 1018 1019 /* Macro to iterate over all valid ports for mlx5 driver. */ 1020 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ 1021 for (port_id = mlx5_eth_find_next(0, pci_dev); \ 1022 port_id < RTE_MAX_ETHPORTS; \ 1023 port_id = mlx5_eth_find_next(port_id + 1, pci_dev)) 1024 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); 1025 struct mlx5_dev_ctx_shared * 1026 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1027 const struct mlx5_dev_config *config); 1028 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 1029 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 1030 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 1031 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1032 struct mlx5_dev_config *config); 1033 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 1034 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 1035 struct mlx5_dev_config *config); 1036 int mlx5_dev_configure(struct rte_eth_dev *dev); 1037 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 1038 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 1039 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1040 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1041 struct rte_eth_hairpin_cap *cap); 1042 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 1043 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 1044 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 1045 1046 /* mlx5_ethdev.c */ 1047 1048 int mlx5_dev_configure(struct rte_eth_dev *dev); 1049 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, 1050 size_t fw_size); 1051 int mlx5_dev_infos_get(struct rte_eth_dev *dev, 1052 struct rte_eth_dev_info *info); 1053 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 1054 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1055 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1056 struct rte_eth_hairpin_cap *cap); 1057 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 1058 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 1059 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 1060 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 1061 1062 /* mlx5_ethdev_os.c */ 1063 1064 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 1065 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 1066 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 1067 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1068 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 1069 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1070 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 1071 struct rte_eth_fc_conf *fc_conf); 1072 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 1073 struct rte_eth_fc_conf *fc_conf); 1074 void mlx5_dev_interrupt_handler(void *arg); 1075 void mlx5_dev_interrupt_handler_devx(void *arg); 1076 int mlx5_set_link_down(struct rte_eth_dev *dev); 1077 int mlx5_set_link_up(struct rte_eth_dev *dev); 1078 int mlx5_is_removed(struct rte_eth_dev *dev); 1079 int mlx5_sysfs_switch_info(unsigned int ifindex, 1080 struct mlx5_switch_info *info); 1081 void mlx5_translate_port_name(const char *port_name_in, 1082 struct mlx5_switch_info *port_info_out); 1083 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 1084 rte_intr_callback_fn cb_fn, void *cb_arg); 1085 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 1086 char *ifname); 1087 int mlx5_get_module_info(struct rte_eth_dev *dev, 1088 struct rte_eth_dev_module_info *modinfo); 1089 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 1090 struct rte_dev_eeprom_info *info); 1091 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 1092 const char *ctr_name, uint64_t *stat); 1093 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 1094 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 1095 void mlx5_os_stats_init(struct rte_eth_dev *dev); 1096 1097 /* mlx5_mac.c */ 1098 1099 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1100 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1101 uint32_t index, uint32_t vmdq); 1102 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 1103 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 1104 struct rte_ether_addr *mc_addr_set, 1105 uint32_t nb_mc_addr); 1106 1107 /* mlx5_rss.c */ 1108 1109 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 1110 struct rte_eth_rss_conf *rss_conf); 1111 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 1112 struct rte_eth_rss_conf *rss_conf); 1113 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 1114 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 1115 struct rte_eth_rss_reta_entry64 *reta_conf, 1116 uint16_t reta_size); 1117 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 1118 struct rte_eth_rss_reta_entry64 *reta_conf, 1119 uint16_t reta_size); 1120 1121 /* mlx5_rxmode.c */ 1122 1123 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 1124 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 1125 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 1126 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 1127 1128 /* mlx5_stats.c */ 1129 1130 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 1131 int mlx5_stats_reset(struct rte_eth_dev *dev); 1132 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1133 unsigned int n); 1134 int mlx5_xstats_reset(struct rte_eth_dev *dev); 1135 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1136 struct rte_eth_xstat_name *xstats_names, 1137 unsigned int n); 1138 1139 /* mlx5_vlan.c */ 1140 1141 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 1142 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 1143 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 1144 1145 /* mlx5_vlan_os.c */ 1146 1147 void mlx5_vlan_vmwa_exit(void *ctx); 1148 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 1149 struct mlx5_vf_vlan *vf_vlan); 1150 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 1151 struct mlx5_vf_vlan *vf_vlan); 1152 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 1153 1154 /* mlx5_trigger.c */ 1155 1156 int mlx5_dev_start(struct rte_eth_dev *dev); 1157 int mlx5_dev_stop(struct rte_eth_dev *dev); 1158 int mlx5_traffic_enable(struct rte_eth_dev *dev); 1159 void mlx5_traffic_disable(struct rte_eth_dev *dev); 1160 int mlx5_traffic_restart(struct rte_eth_dev *dev); 1161 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 1162 struct rte_hairpin_peer_info *current_info, 1163 struct rte_hairpin_peer_info *peer_info, 1164 uint32_t direction); 1165 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 1166 struct rte_hairpin_peer_info *peer_info, 1167 uint32_t direction); 1168 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 1169 uint32_t direction); 1170 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 1171 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 1172 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 1173 size_t len, uint32_t direction); 1174 1175 /* mlx5_flow.c */ 1176 1177 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 1178 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 1179 void mlx5_flow_print(struct rte_flow *flow); 1180 int mlx5_flow_validate(struct rte_eth_dev *dev, 1181 const struct rte_flow_attr *attr, 1182 const struct rte_flow_item items[], 1183 const struct rte_flow_action actions[], 1184 struct rte_flow_error *error); 1185 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 1186 const struct rte_flow_attr *attr, 1187 const struct rte_flow_item items[], 1188 const struct rte_flow_action actions[], 1189 struct rte_flow_error *error); 1190 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 1191 struct rte_flow_error *error); 1192 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active); 1193 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 1194 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 1195 const struct rte_flow_action *action, void *data, 1196 struct rte_flow_error *error); 1197 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 1198 struct rte_flow_error *error); 1199 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 1200 enum rte_filter_type filter_type, 1201 enum rte_filter_op filter_op, 1202 void *arg); 1203 int mlx5_flow_start_default(struct rte_eth_dev *dev); 1204 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 1205 int mlx5_flow_verify(struct rte_eth_dev *dev); 1206 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 1207 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 1208 struct rte_flow_item_eth *eth_spec, 1209 struct rte_flow_item_eth *eth_mask, 1210 struct rte_flow_item_vlan *vlan_spec, 1211 struct rte_flow_item_vlan *vlan_mask); 1212 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 1213 struct rte_flow_item_eth *eth_spec, 1214 struct rte_flow_item_eth *eth_mask); 1215 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 1216 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 1217 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 1218 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 1219 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 1220 uint64_t async_id, int status); 1221 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 1222 void mlx5_flow_query_alarm(void *arg); 1223 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 1224 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 1225 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 1226 bool clear, uint64_t *pkts, uint64_t *bytes); 1227 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, 1228 struct rte_flow_error *error); 1229 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 1230 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 1231 uint32_t nb_contexts, struct rte_flow_error *error); 1232 1233 /* mlx5_mp_os.c */ 1234 1235 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 1236 const void *peer); 1237 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 1238 const void *peer); 1239 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 1240 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 1241 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 1242 enum mlx5_mp_req_type req_type); 1243 1244 /* mlx5_socket.c */ 1245 1246 int mlx5_pmd_socket_init(void); 1247 1248 /* mlx5_flow_meter.c */ 1249 1250 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 1251 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv, 1252 uint32_t meter_id); 1253 struct mlx5_flow_meter *mlx5_flow_meter_attach 1254 (struct mlx5_priv *priv, 1255 uint32_t meter_id, 1256 const struct rte_flow_attr *attr, 1257 struct rte_flow_error *error); 1258 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); 1259 1260 /* mlx5_os.c */ 1261 struct rte_pci_driver; 1262 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr); 1263 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 1264 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 1265 const struct mlx5_dev_config *config, 1266 struct mlx5_dev_ctx_shared *sh); 1267 int mlx5_os_get_pdn(void *pd, uint32_t *pdn); 1268 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1269 struct rte_pci_device *pci_dev); 1270 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 1271 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 1272 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 1273 mlx5_dereg_mr_t *dereg_mr_cb); 1274 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1275 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1276 uint32_t index); 1277 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 1278 struct rte_ether_addr *mac_addr, 1279 int vf_index); 1280 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 1281 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 1282 int mlx5_os_set_nonblock_channel_fd(int fd); 1283 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 1284 1285 /* mlx5_txpp.c */ 1286 1287 int mlx5_txpp_start(struct rte_eth_dev *dev); 1288 void mlx5_txpp_stop(struct rte_eth_dev *dev); 1289 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 1290 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 1291 struct rte_eth_xstat *stats, 1292 unsigned int n, unsigned int n_used); 1293 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 1294 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 1295 struct rte_eth_xstat_name *xstats_names, 1296 unsigned int n, unsigned int n_used); 1297 void mlx5_txpp_interrupt_handler(void *cb_arg); 1298 1299 /* mlx5_rxtx.c */ 1300 1301 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 1302 1303 /* mlx5_flow_age.c */ 1304 1305 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh); 1306 int mlx5_aso_queue_start(struct mlx5_dev_ctx_shared *sh); 1307 int mlx5_aso_queue_stop(struct mlx5_dev_ctx_shared *sh); 1308 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh); 1309 1310 #endif /* RTE_PMD_MLX5_H_ */ 1311