1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <net/if.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 /* Verbs header. */ 18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 19 #ifdef PEDANTIC 20 #pragma GCC diagnostic ignored "-Wpedantic" 21 #endif 22 #include <infiniband/verbs.h> 23 #ifdef PEDANTIC 24 #pragma GCC diagnostic error "-Wpedantic" 25 #endif 26 27 #include <rte_pci.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_rwlock.h> 31 #include <rte_interrupts.h> 32 #include <rte_errno.h> 33 #include <rte_flow.h> 34 35 #include <mlx5_glue.h> 36 #include <mlx5_devx_cmds.h> 37 #include <mlx5_prm.h> 38 #include <mlx5_nl.h> 39 #include <mlx5_common_mp.h> 40 #include <mlx5_common_mr.h> 41 42 #include "mlx5_defs.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_os.h" 45 #include "mlx5_autoconf.h" 46 47 enum mlx5_ipool_index { 48 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 49 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 50 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 51 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 52 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 53 MLX5_IPOOL_JUMP, /* Pool for jump resource. */ 54 #endif 55 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 56 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 57 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 58 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 59 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 60 MLX5_IPOOL_MAX, 61 }; 62 63 /* 64 * There are three reclaim memory mode supported. 65 * 0(none) means no memory reclaim. 66 * 1(light) means only PMD level reclaim. 67 * 2(aggressive) means both PMD and rdma-core level reclaim. 68 */ 69 enum mlx5_reclaim_mem_mode { 70 MLX5_RCM_NONE, /* Don't reclaim memory. */ 71 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 72 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 73 }; 74 75 /* Device attributes used in mlx5 PMD */ 76 struct mlx5_dev_attr { 77 uint64_t device_cap_flags_ex; 78 int max_qp_wr; 79 int max_sge; 80 int max_cq; 81 int max_qp; 82 uint32_t raw_packet_caps; 83 uint32_t max_rwq_indirection_table_size; 84 uint32_t max_tso; 85 uint32_t tso_supported_qpts; 86 uint64_t flags; 87 uint64_t comp_mask; 88 uint32_t sw_parsing_offloads; 89 uint32_t min_single_stride_log_num_of_bytes; 90 uint32_t max_single_stride_log_num_of_bytes; 91 uint32_t min_single_wqe_log_num_of_strides; 92 uint32_t max_single_wqe_log_num_of_strides; 93 uint32_t stride_supported_qpts; 94 uint32_t tunnel_offloads_caps; 95 char fw_ver[64]; 96 }; 97 98 /** Data associated with devices to spawn. */ 99 struct mlx5_dev_spawn_data { 100 uint32_t ifindex; /**< Network interface index. */ 101 uint32_t max_port; /**< Device maximal port index. */ 102 uint32_t phys_port; /**< Device physical port index. */ 103 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 104 struct mlx5_switch_info info; /**< Switch information. */ 105 void *phys_dev; /**< Associated physical device. */ 106 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 107 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 108 }; 109 110 /** Key string for IPC. */ 111 #define MLX5_MP_NAME "net_mlx5_mp" 112 113 114 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 115 116 /* Shared data between primary and secondary processes. */ 117 struct mlx5_shared_data { 118 rte_spinlock_t lock; 119 /* Global spinlock for primary and secondary processes. */ 120 int init_done; /* Whether primary has done initialization. */ 121 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 122 struct mlx5_dev_list mem_event_cb_list; 123 rte_rwlock_t mem_event_rwlock; 124 }; 125 126 /* Per-process data structure, not visible to other processes. */ 127 struct mlx5_local_data { 128 int init_done; /* Whether a secondary has done initialization. */ 129 }; 130 131 extern struct mlx5_shared_data *mlx5_shared_data; 132 extern struct rte_pci_driver mlx5_driver; 133 134 /* Dev ops structs */ 135 extern const struct eth_dev_ops mlx5_os_dev_ops; 136 extern const struct eth_dev_ops mlx5_os_dev_sec_ops; 137 extern const struct eth_dev_ops mlx5_os_dev_ops_isolate; 138 139 struct mlx5_counter_ctrl { 140 /* Name of the counter. */ 141 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 142 /* Name of the counter on the device table. */ 143 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 144 uint32_t dev:1; /**< Nonzero for dev counters. */ 145 }; 146 147 struct mlx5_xstats_ctrl { 148 /* Number of device stats. */ 149 uint16_t stats_n; 150 /* Number of device stats identified by PMD. */ 151 uint16_t mlx5_stats_n; 152 /* Index in the device counters table. */ 153 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 154 uint64_t base[MLX5_MAX_XSTATS]; 155 uint64_t xstats[MLX5_MAX_XSTATS]; 156 uint64_t hw_stats[MLX5_MAX_XSTATS]; 157 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 158 }; 159 160 struct mlx5_stats_ctrl { 161 /* Base for imissed counter. */ 162 uint64_t imissed_base; 163 uint64_t imissed; 164 }; 165 166 /* Default PMD specific parameter value. */ 167 #define MLX5_ARG_UNSET (-1) 168 169 #define MLX5_LRO_SUPPORTED(dev) \ 170 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 171 172 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 173 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 174 175 /* Maximal size of aggregated LRO packet. */ 176 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 177 178 /* LRO configurations structure. */ 179 struct mlx5_lro_config { 180 uint32_t supported:1; /* Whether LRO is supported. */ 181 uint32_t timeout; /* User configuration. */ 182 }; 183 184 /* 185 * Device configuration structure. 186 * 187 * Merged configuration from: 188 * 189 * - Device capabilities, 190 * - User device parameters disabled features. 191 */ 192 struct mlx5_dev_config { 193 unsigned int hw_csum:1; /* Checksum offload is supported. */ 194 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 195 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 196 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 197 unsigned int hw_padding:1; /* End alignment padding is supported. */ 198 unsigned int vf:1; /* This is a VF. */ 199 unsigned int tunnel_en:1; 200 /* Whether tunnel stateless offloads are supported. */ 201 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 202 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 203 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 204 unsigned int tso:1; /* Whether TSO is supported. */ 205 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 206 unsigned int mr_ext_memseg_en:1; 207 /* Whether memseg should be extended for MR creation. */ 208 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 209 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 210 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 211 unsigned int dv_flow_en:1; /* Enable DV flow. */ 212 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 213 unsigned int lacp_by_user:1; 214 /* Enable user to manage LACP traffic. */ 215 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 216 unsigned int devx:1; /* Whether devx interface is available or not. */ 217 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 218 unsigned int reclaim_mode:2; /* Memory reclaim mode. */ 219 struct { 220 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 221 unsigned int stride_num_n; /* Number of strides. */ 222 unsigned int stride_size_n; /* Size of a stride. */ 223 unsigned int min_stride_size_n; /* Min size of a stride. */ 224 unsigned int max_stride_size_n; /* Max size of a stride. */ 225 unsigned int max_memcpy_len; 226 /* Maximum packet size to memcpy Rx packets. */ 227 unsigned int min_rxqs_num; 228 /* Rx queue count threshold to enable MPRQ. */ 229 } mprq; /* Configurations for Multi-Packet RQ. */ 230 int mps; /* Multi-packet send supported mode. */ 231 int dbnc; /* Skip doorbell register write barrier. */ 232 unsigned int flow_prio; /* Number of flow priorities. */ 233 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 234 /* Availibility of mreg_c's. */ 235 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 236 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 237 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 238 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 239 int txqs_inline; /* Queue number threshold for inlining. */ 240 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 241 int txq_inline_max; /* Max packet size for inlining with SEND. */ 242 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 243 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 244 struct mlx5_lro_config lro; /* LRO configuration. */ 245 }; 246 247 248 /** 249 * Type of object being allocated. 250 */ 251 enum mlx5_verbs_alloc_type { 252 MLX5_VERBS_ALLOC_TYPE_NONE, 253 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 254 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 255 }; 256 257 /* Structure for VF VLAN workaround. */ 258 struct mlx5_vf_vlan { 259 uint32_t tag:12; 260 uint32_t created:1; 261 }; 262 263 /** 264 * Verbs allocator needs a context to know in the callback which kind of 265 * resources it is allocating. 266 */ 267 struct mlx5_verbs_alloc_ctx { 268 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 269 const void *obj; /* Pointer to the DPDK object. */ 270 }; 271 272 /* Flow drop context necessary due to Verbs API. */ 273 struct mlx5_drop { 274 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 275 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 276 }; 277 278 #define MLX5_COUNTERS_PER_POOL 512 279 #define MLX5_MAX_PENDING_QUERIES 4 280 #define MLX5_CNT_CONTAINER_RESIZE 64 281 #define MLX5_CNT_AGE_OFFSET 0x80000000 282 #define CNT_SIZE (sizeof(struct mlx5_flow_counter)) 283 #define CNTEXT_SIZE (sizeof(struct mlx5_flow_counter_ext)) 284 #define AGE_SIZE (sizeof(struct mlx5_age_param)) 285 #define MLX5_AGING_TIME_DELAY 7 286 #define CNT_POOL_TYPE_EXT (1 << 0) 287 #define CNT_POOL_TYPE_AGE (1 << 1) 288 #define IS_EXT_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_EXT) 289 #define IS_AGE_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_AGE) 290 #define MLX_CNT_IS_AGE(counter) ((counter) & MLX5_CNT_AGE_OFFSET ? 1 : 0) 291 #define MLX5_CNT_LEN(pool) \ 292 (CNT_SIZE + \ 293 (IS_AGE_POOL(pool) ? AGE_SIZE : 0) + \ 294 (IS_EXT_POOL(pool) ? CNTEXT_SIZE : 0)) 295 #define MLX5_POOL_GET_CNT(pool, index) \ 296 ((struct mlx5_flow_counter *) \ 297 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 298 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 299 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 300 MLX5_CNT_LEN(pool))) 301 /* 302 * The pool index and offset of counter in the pool array makes up the 303 * counter index. In case the counter is from pool 0 and offset 0, it 304 * should plus 1 to avoid index 0, since 0 means invalid counter index 305 * currently. 306 */ 307 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 308 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 309 #define MLX5_CNT_TO_CNT_EXT(pool, cnt) \ 310 ((struct mlx5_flow_counter_ext *)\ 311 ((uint8_t *)((cnt) + 1) + \ 312 (IS_AGE_POOL(pool) ? AGE_SIZE : 0))) 313 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \ 314 MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset))) 315 #define MLX5_CNT_TO_AGE(cnt) \ 316 ((struct mlx5_age_param *)((cnt) + 1)) 317 /* 318 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 319 * defines. The pool size is 512, pool index should never reach 320 * INT16_MAX. 321 */ 322 #define POOL_IDX_INVALID UINT16_MAX 323 324 struct mlx5_flow_counter_pool; 325 326 /*age status*/ 327 enum { 328 AGE_FREE, /* Initialized state. */ 329 AGE_CANDIDATE, /* Counter assigned to flows. */ 330 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 331 }; 332 333 #define MLX5_CNT_CONTAINER(sh, batch, age) (&(sh)->cmng.ccont \ 334 [(batch) * 2 + (age)]) 335 336 enum { 337 MLX5_CCONT_TYPE_SINGLE, 338 MLX5_CCONT_TYPE_SINGLE_FOR_AGE, 339 MLX5_CCONT_TYPE_BATCH, 340 MLX5_CCONT_TYPE_BATCH_FOR_AGE, 341 MLX5_CCONT_TYPE_MAX, 342 }; 343 344 /* Counter age parameter. */ 345 struct mlx5_age_param { 346 rte_atomic16_t state; /**< Age state. */ 347 uint16_t port_id; /**< Port id of the counter. */ 348 uint32_t timeout:15; /**< Age timeout in unit of 0.1sec. */ 349 uint32_t expire:16; /**< Expire time(0.1sec) in the future. */ 350 void *context; /**< Flow counter age context. */ 351 }; 352 353 struct flow_counter_stats { 354 uint64_t hits; 355 uint64_t bytes; 356 }; 357 358 struct mlx5_flow_counter_pool; 359 /* Generic counters information. */ 360 struct mlx5_flow_counter { 361 TAILQ_ENTRY(mlx5_flow_counter) next; 362 /**< Pointer to the next flow counter structure. */ 363 union { 364 uint64_t hits; /**< Reset value of hits packets. */ 365 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 366 }; 367 uint64_t bytes; /**< Reset value of bytes. */ 368 void *action; /**< Pointer to the dv action. */ 369 }; 370 371 /* Extend counters information for none batch counters. */ 372 struct mlx5_flow_counter_ext { 373 uint32_t shared:1; /**< Share counter ID with other flow rules. */ 374 uint32_t batch: 1; 375 /**< Whether the counter was allocated by batch command. */ 376 uint32_t ref_cnt:30; /**< Reference counter. */ 377 uint32_t id; /**< User counter ID. */ 378 union { /**< Holds the counters for the rule. */ 379 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 380 struct ibv_counter_set *cs; 381 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 382 struct ibv_counters *cs; 383 #endif 384 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */ 385 }; 386 }; 387 388 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 389 390 /* Generic counter pool structure - query is in pool resolution. */ 391 struct mlx5_flow_counter_pool { 392 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 393 struct mlx5_counters counters[2]; /* Free counter list. */ 394 union { 395 struct mlx5_devx_obj *min_dcs; 396 rte_atomic64_t a64_dcs; 397 }; 398 /* The devx object of the minimum counter ID. */ 399 uint32_t index:29; /* Pool index in container. */ 400 uint32_t type:2; /* Memory type behind the counter array. */ 401 volatile uint32_t query_gen:1; /* Query round. */ 402 rte_spinlock_t sl; /* The pool lock. */ 403 struct mlx5_counter_stats_raw *raw; 404 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ 405 }; 406 407 struct mlx5_counter_stats_raw; 408 409 /* Memory management structure for group of counter statistics raws. */ 410 struct mlx5_counter_stats_mem_mng { 411 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 412 struct mlx5_counter_stats_raw *raws; 413 struct mlx5_devx_obj *dm; 414 void *umem; 415 }; 416 417 /* Raw memory structure for the counter statistics values of a pool. */ 418 struct mlx5_counter_stats_raw { 419 LIST_ENTRY(mlx5_counter_stats_raw) next; 420 int min_dcs_id; 421 struct mlx5_counter_stats_mem_mng *mem_mng; 422 volatile struct flow_counter_stats *data; 423 }; 424 425 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 426 427 /* Container structure for counter pools. */ 428 struct mlx5_pools_container { 429 rte_atomic16_t n_valid; /* Number of valid pools. */ 430 uint16_t n; /* Number of pools. */ 431 uint16_t last_pool_idx; /* Last used pool index */ 432 int min_id; /* The minimum counter ID in the pools. */ 433 int max_id; /* The maximum counter ID in the pools. */ 434 rte_spinlock_t resize_sl; /* The resize lock. */ 435 rte_spinlock_t csl; /* The counter free list lock. */ 436 struct mlx5_counters counters; /* Free counter list. */ 437 struct mlx5_counter_pools pool_list; /* Counter pool list. */ 438 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 439 struct mlx5_counter_stats_mem_mng *mem_mng; 440 /* Hold the memory management for the next allocated pools raws. */ 441 }; 442 443 /* Counter global management structure. */ 444 struct mlx5_flow_counter_mng { 445 struct mlx5_pools_container ccont[MLX5_CCONT_TYPE_MAX]; 446 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 447 uint8_t pending_queries; 448 uint8_t batch; 449 uint16_t pool_index; 450 uint8_t age; 451 uint8_t query_thread_on; 452 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 453 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 454 }; 455 456 /* Default miss action resource structure. */ 457 struct mlx5_flow_default_miss_resource { 458 void *action; /* Pointer to the rdma-core action. */ 459 rte_atomic32_t refcnt; /* Default miss action reference counter. */ 460 }; 461 462 #define MLX5_AGE_EVENT_NEW 1 463 #define MLX5_AGE_TRIGGER 2 464 #define MLX5_AGE_SET(age_info, BIT) \ 465 ((age_info)->flags |= (1 << (BIT))) 466 #define MLX5_AGE_GET(age_info, BIT) \ 467 ((age_info)->flags & (1 << (BIT))) 468 #define GET_PORT_AGE_INFO(priv) \ 469 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 470 471 /* Aging information for per port. */ 472 struct mlx5_age_info { 473 uint8_t flags; /*Indicate if is new event or need be trigered*/ 474 struct mlx5_counters aged_counters; /* Aged flow counter list. */ 475 rte_spinlock_t aged_sl; /* Aged flow counter list lock. */ 476 }; 477 478 /* Per port data of shared IB device. */ 479 struct mlx5_dev_shared_port { 480 uint32_t ih_port_id; 481 uint32_t devx_ih_port_id; 482 /* 483 * Interrupt handler port_id. Used by shared interrupt 484 * handler to find the corresponding rte_eth device 485 * by IB port index. If value is equal or greater 486 * RTE_MAX_ETHPORTS it means there is no subhandler 487 * installed for specified IB port index. 488 */ 489 struct mlx5_age_info age_info; 490 /* Aging information for per port. */ 491 }; 492 493 /* Table key of the hash organization. */ 494 union mlx5_flow_tbl_key { 495 struct { 496 /* Table ID should be at the lowest address. */ 497 uint32_t table_id; /**< ID of the table. */ 498 uint16_t reserved; /**< must be zero for comparison. */ 499 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */ 500 uint8_t direction; /**< 1 - egress, 0 - ingress. */ 501 }; 502 uint64_t v64; /**< full 64bits value of key */ 503 }; 504 505 /* Table structure. */ 506 struct mlx5_flow_tbl_resource { 507 void *obj; /**< Pointer to DR table object. */ 508 rte_atomic32_t refcnt; /**< Reference counter. */ 509 }; 510 511 #define MLX5_MAX_TABLES UINT16_MAX 512 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3) 513 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2) 514 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 515 /* Reserve the last two tables for metadata register copy. */ 516 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 517 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 518 /* Tables for metering splits should be added here. */ 519 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3) 520 #define MLX5_MAX_TABLES_FDB UINT16_MAX 521 522 /* ID generation structure. */ 523 struct mlx5_flow_id_pool { 524 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 525 uint32_t base_index; 526 /**< The next index that can be used without any free elements. */ 527 uint32_t *curr; /**< Pointer to the index to pop. */ 528 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 529 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 530 }; 531 532 /* 533 * Shared Infiniband device context for Master/Representors 534 * which belong to same IB device with multiple IB ports. 535 **/ 536 struct mlx5_dev_ctx_shared { 537 LIST_ENTRY(mlx5_dev_ctx_shared) next; 538 uint32_t refcnt; 539 uint32_t devx:1; /* Opened with DV. */ 540 uint32_t max_port; /* Maximal IB device port index. */ 541 void *ctx; /* Verbs/DV/DevX context. */ 542 void *pd; /* Protection Domain. */ 543 uint32_t pdn; /* Protection Domain number. */ 544 uint32_t tdn; /* Transport Domain number. */ 545 char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */ 546 char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */ 547 struct mlx5_dev_attr device_attr; /* Device properties. */ 548 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; 549 /**< Called by memory event callback. */ 550 struct mlx5_mr_share_cache share_cache; 551 /* Shared DV/DR flow data section. */ 552 pthread_mutex_t dv_mutex; /* DV context mutex. */ 553 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 554 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 555 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 556 uint32_t dv_refcnt; /* DV/DR data reference counter. */ 557 void *fdb_domain; /* FDB Direct Rules name space handle. */ 558 void *rx_domain; /* RX Direct Rules name space handle. */ 559 void *tx_domain; /* TX Direct Rules name space handle. */ 560 struct mlx5_hlist *flow_tbls; 561 /* Direct Rules tables for FDB, NIC TX+RX */ 562 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ 563 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 564 uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */ 565 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds; 566 struct mlx5_hlist *tag_table; 567 uint32_t port_id_action_list; /* List of port ID actions. */ 568 uint32_t push_vlan_action_list; /* List of push VLAN actions. */ 569 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 570 struct mlx5_flow_default_miss_resource default_miss; 571 /* Default miss action resource structure. */ 572 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 573 /* Memory Pool for mlx5 flow resources. */ 574 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ 575 /* Shared interrupt handler section. */ 576 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 577 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 578 void *devx_comp; /* DEVX async comp obj. */ 579 struct mlx5_devx_obj *tis; /* TIS object. */ 580 struct mlx5_devx_obj *td; /* Transport domain. */ 581 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */ 582 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 583 }; 584 585 /* Per-process private structure. */ 586 struct mlx5_proc_priv { 587 size_t uar_table_sz; 588 /* Size of UAR register table. */ 589 void *uar_table[]; 590 /* Table of UAR registers for each process. */ 591 }; 592 593 /* MTR profile list. */ 594 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 595 /* MTR list. */ 596 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); 597 598 #define MLX5_PROC_PRIV(port_id) \ 599 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 600 601 struct mlx5_priv { 602 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 603 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 604 uint32_t dev_port; /* Device port number. */ 605 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 606 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 607 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 608 /* Bit-field of MAC addresses owned by the PMD. */ 609 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 610 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 611 /* Device properties. */ 612 uint16_t mtu; /* Configured MTU. */ 613 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 614 unsigned int representor:1; /* Device is a port representor. */ 615 unsigned int master:1; /* Device is a E-Switch master. */ 616 unsigned int dr_shared:1; /* DV/DR data is shared. */ 617 unsigned int counter_fallback:1; /* Use counter fallback management. */ 618 unsigned int mtr_en:1; /* Whether support meter. */ 619 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 620 uint16_t domain_id; /* Switch domain identifier. */ 621 uint16_t vport_id; /* Associated VF vport index (if any). */ 622 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 623 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 624 int32_t representor_id; /* Port representor identifier. */ 625 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */ 626 unsigned int if_index; /* Associated kernel network device index. */ 627 /* RX/TX queues. */ 628 unsigned int rxqs_n; /* RX queues array size. */ 629 unsigned int txqs_n; /* TX queues array size. */ 630 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 631 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 632 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 633 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 634 unsigned int (*reta_idx)[]; /* RETA index table. */ 635 unsigned int reta_idx_n; /* RETA index size. */ 636 struct mlx5_drop drop_queue; /* Flow drop queues. */ 637 uint32_t flows; /* RTE Flow rules. */ 638 uint32_t ctrl_flows; /* Control flow rules. */ 639 void *inter_flows; /* Intermediate resources for flow creation. */ 640 void *rss_desc; /* Intermediate rss description resources. */ 641 int flow_idx; /* Intermediate device flow index. */ 642 int flow_nested_idx; /* Intermediate device flow index, nested. */ 643 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 644 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 645 uint32_t hrxqs; /* Verbs Hash Rx queues. */ 646 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 647 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 648 /* Indirection tables. */ 649 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 650 /* Pointer to next element. */ 651 rte_atomic32_t refcnt; /**< Reference counter. */ 652 struct ibv_flow_action *verbs_action; 653 /**< Verbs modify header action object. */ 654 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 655 uint8_t max_lro_msg_size; 656 /* Tags resources cache. */ 657 uint32_t link_speed_capa; /* Link speed capabilities. */ 658 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 659 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 660 struct mlx5_dev_config config; /* Device configuration. */ 661 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 662 /* Context for Verbs allocator. */ 663 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 664 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 665 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ 666 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 667 struct mlx5_flow_id_pool *qrss_id_pool; 668 struct mlx5_hlist *mreg_cp_tbl; 669 /* Hash table of Rx metadata register copy table. */ 670 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 671 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 672 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ 673 struct mlx5_flow_meters flow_meters; /* MTR list. */ 674 #ifndef RTE_ARCH_64 675 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 676 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 677 /* UAR same-page access control required in 32bit implementations. */ 678 #endif 679 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 680 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 681 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 682 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 683 }; 684 685 #define PORT_ID(priv) ((priv)->dev_data->port_id) 686 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 687 688 /* mlx5.c */ 689 690 int mlx5_getenv_int(const char *); 691 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 692 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 693 struct rte_eth_udp_tunnel *udp_tunnel); 694 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); 695 void mlx5_dev_close(struct rte_eth_dev *dev); 696 697 /* Macro to iterate over all valid ports for mlx5 driver. */ 698 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ 699 for (port_id = mlx5_eth_find_next(0, pci_dev); \ 700 port_id < RTE_MAX_ETHPORTS; \ 701 port_id = mlx5_eth_find_next(port_id + 1, pci_dev)) 702 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); 703 struct mlx5_dev_ctx_shared * 704 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 705 const struct mlx5_dev_config *config); 706 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 707 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 708 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 709 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 710 struct mlx5_dev_config *config); 711 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 712 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 713 struct mlx5_dev_config *config); 714 int mlx5_init_once(void); 715 int mlx5_dev_configure(struct rte_eth_dev *dev); 716 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 717 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 718 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 719 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 720 struct rte_eth_hairpin_cap *cap); 721 722 /* mlx5_ethdev.c */ 723 724 int mlx5_dev_configure(struct rte_eth_dev *dev); 725 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, 726 size_t fw_size); 727 int mlx5_dev_infos_get(struct rte_eth_dev *dev, 728 struct rte_eth_dev_info *info); 729 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 730 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 731 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 732 struct rte_eth_hairpin_cap *cap); 733 734 /* mlx5_ethdev_os.c */ 735 736 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); 737 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 738 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); 739 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 740 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, 741 unsigned int flags); 742 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 743 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 744 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 745 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status); 746 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 747 struct rte_eth_fc_conf *fc_conf); 748 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 749 struct rte_eth_fc_conf *fc_conf); 750 void mlx5_dev_link_status_handler(void *arg); 751 void mlx5_dev_interrupt_handler(void *arg); 752 void mlx5_dev_interrupt_handler_devx(void *arg); 753 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev); 754 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev); 755 int mlx5_set_link_down(struct rte_eth_dev *dev); 756 int mlx5_set_link_up(struct rte_eth_dev *dev); 757 int mlx5_is_removed(struct rte_eth_dev *dev); 758 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 759 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 760 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 761 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 762 int mlx5_sysfs_switch_info(unsigned int ifindex, 763 struct mlx5_switch_info *info); 764 void mlx5_sysfs_check_switch_info(bool device_dir, 765 struct mlx5_switch_info *switch_info); 766 void mlx5_translate_port_name(const char *port_name_in, 767 struct mlx5_switch_info *port_info_out); 768 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 769 rte_intr_callback_fn cb_fn, void *cb_arg); 770 int mlx5_get_module_info(struct rte_eth_dev *dev, 771 struct rte_eth_dev_module_info *modinfo); 772 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 773 struct rte_dev_eeprom_info *info); 774 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 775 776 /* mlx5_mac.c */ 777 778 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 779 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 780 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 781 uint32_t index, uint32_t vmdq); 782 struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init 783 (struct rte_eth_dev *dev, uint32_t ifindex); 784 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 785 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 786 struct rte_ether_addr *mc_addr_set, 787 uint32_t nb_mc_addr); 788 789 /* mlx5_rss.c */ 790 791 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 792 struct rte_eth_rss_conf *rss_conf); 793 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 794 struct rte_eth_rss_conf *rss_conf); 795 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 796 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 797 struct rte_eth_rss_reta_entry64 *reta_conf, 798 uint16_t reta_size); 799 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 800 struct rte_eth_rss_reta_entry64 *reta_conf, 801 uint16_t reta_size); 802 803 /* mlx5_rxmode.c */ 804 805 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 806 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 807 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 808 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 809 810 /* mlx5_stats.c */ 811 812 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 813 int mlx5_stats_reset(struct rte_eth_dev *dev); 814 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 815 unsigned int n); 816 int mlx5_xstats_reset(struct rte_eth_dev *dev); 817 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 818 struct rte_eth_xstat_name *xstats_names, 819 unsigned int n); 820 821 /* mlx5_vlan.c */ 822 823 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 824 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 825 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 826 void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx); 827 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 828 struct mlx5_vf_vlan *vf_vlan); 829 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 830 struct mlx5_vf_vlan *vf_vlan); 831 832 /* mlx5_trigger.c */ 833 834 int mlx5_dev_start(struct rte_eth_dev *dev); 835 void mlx5_dev_stop(struct rte_eth_dev *dev); 836 int mlx5_traffic_enable(struct rte_eth_dev *dev); 837 void mlx5_traffic_disable(struct rte_eth_dev *dev); 838 int mlx5_traffic_restart(struct rte_eth_dev *dev); 839 840 /* mlx5_flow.c */ 841 842 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 843 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 844 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 845 void mlx5_flow_print(struct rte_flow *flow); 846 int mlx5_flow_validate(struct rte_eth_dev *dev, 847 const struct rte_flow_attr *attr, 848 const struct rte_flow_item items[], 849 const struct rte_flow_action actions[], 850 struct rte_flow_error *error); 851 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 852 const struct rte_flow_attr *attr, 853 const struct rte_flow_item items[], 854 const struct rte_flow_action actions[], 855 struct rte_flow_error *error); 856 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 857 struct rte_flow_error *error); 858 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active); 859 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 860 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 861 const struct rte_flow_action *action, void *data, 862 struct rte_flow_error *error); 863 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 864 struct rte_flow_error *error); 865 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 866 enum rte_filter_type filter_type, 867 enum rte_filter_op filter_op, 868 void *arg); 869 int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list); 870 void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list); 871 int mlx5_flow_start_default(struct rte_eth_dev *dev); 872 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 873 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev); 874 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev); 875 int mlx5_flow_verify(struct rte_eth_dev *dev); 876 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 877 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 878 struct rte_flow_item_eth *eth_spec, 879 struct rte_flow_item_eth *eth_mask, 880 struct rte_flow_item_vlan *vlan_spec, 881 struct rte_flow_item_vlan *vlan_mask); 882 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 883 struct rte_flow_item_eth *eth_spec, 884 struct rte_flow_item_eth *eth_mask); 885 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 886 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 887 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 888 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 889 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 890 uint64_t async_id, int status); 891 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 892 void mlx5_flow_query_alarm(void *arg); 893 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 894 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 895 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 896 bool clear, uint64_t *pkts, uint64_t *bytes); 897 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, 898 struct rte_flow_error *error); 899 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 900 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 901 uint32_t nb_contexts, struct rte_flow_error *error); 902 903 /* mlx5_mp.c */ 904 int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer); 905 int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer); 906 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev); 907 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev); 908 909 /* mlx5_socket.c */ 910 911 int mlx5_pmd_socket_init(void); 912 913 /* mlx5_flow_meter.c */ 914 915 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 916 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv, 917 uint32_t meter_id); 918 struct mlx5_flow_meter *mlx5_flow_meter_attach 919 (struct mlx5_priv *priv, 920 uint32_t meter_id, 921 const struct rte_flow_attr *attr, 922 struct rte_flow_error *error); 923 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); 924 925 /* mlx5_os.c */ 926 struct rte_pci_driver; 927 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr); 928 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 929 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 930 const struct mlx5_dev_config *config, 931 struct mlx5_dev_ctx_shared *sh); 932 int mlx5_os_get_pdn(void *pd, uint32_t *pdn); 933 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 934 struct rte_pci_device *pci_dev); 935 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 936 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 937 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 938 const char *ctr_name, uint64_t *stat); 939 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 940 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 941 void mlx5_os_stats_init(struct rte_eth_dev *dev); 942 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 943 mlx5_dereg_mr_t *dereg_mr_cb); 944 #endif /* RTE_PMD_MLX5_H_ */ 945