1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <net/if.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 /* Verbs header. */ 18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 19 #ifdef PEDANTIC 20 #pragma GCC diagnostic ignored "-Wpedantic" 21 #endif 22 #include <infiniband/verbs.h> 23 #ifdef PEDANTIC 24 #pragma GCC diagnostic error "-Wpedantic" 25 #endif 26 27 #include <rte_pci.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_rwlock.h> 31 #include <rte_interrupts.h> 32 #include <rte_errno.h> 33 #include <rte_flow.h> 34 35 #include "mlx5_utils.h" 36 #include "mlx5_mr.h" 37 #include "mlx5_autoconf.h" 38 #include "mlx5_defs.h" 39 #include "mlx5_glue.h" 40 41 enum { 42 PCI_VENDOR_ID_MELLANOX = 0x15b3, 43 }; 44 45 enum { 46 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 47 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 49 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 50 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 51 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 53 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 55 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 56 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 57 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 58 }; 59 60 /* Request types for IPC. */ 61 enum mlx5_mp_req_type { 62 MLX5_MP_REQ_VERBS_CMD_FD = 1, 63 MLX5_MP_REQ_CREATE_MR, 64 MLX5_MP_REQ_START_RXTX, 65 MLX5_MP_REQ_STOP_RXTX, 66 MLX5_MP_REQ_QUEUE_STATE_MODIFY, 67 }; 68 69 struct mlx5_mp_arg_queue_state_modify { 70 uint8_t is_wq; /* Set if WQ. */ 71 uint16_t queue_id; /* DPDK queue ID. */ 72 enum ibv_wq_state state; /* WQ requested state. */ 73 }; 74 75 /* Pameters for IPC. */ 76 struct mlx5_mp_param { 77 enum mlx5_mp_req_type type; 78 int port_id; 79 int result; 80 RTE_STD_C11 81 union { 82 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */ 83 struct mlx5_mp_arg_queue_state_modify state_modify; 84 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */ 85 } args; 86 }; 87 88 /** Request timeout for IPC. */ 89 #define MLX5_MP_REQ_TIMEOUT_SEC 5 90 91 /** Key string for IPC. */ 92 #define MLX5_MP_NAME "net_mlx5_mp" 93 94 /* Recognized Infiniband device physical port name types. */ 95 enum mlx5_phys_port_name_type { 96 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 97 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 98 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 99 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 100 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 101 }; 102 103 /** Switch information returned by mlx5_nl_switch_info(). */ 104 struct mlx5_switch_info { 105 uint32_t master:1; /**< Master device. */ 106 uint32_t representor:1; /**< Representor device. */ 107 enum mlx5_phys_port_name_type name_type; /** < Port name type. */ 108 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 109 int32_t port_name; /**< Representor port name. */ 110 uint64_t switch_id; /**< Switch identifier. */ 111 }; 112 113 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared); 114 115 /* Shared data between primary and secondary processes. */ 116 struct mlx5_shared_data { 117 rte_spinlock_t lock; 118 /* Global spinlock for primary and secondary processes. */ 119 int init_done; /* Whether primary has done initialization. */ 120 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 121 struct mlx5_dev_list mem_event_cb_list; 122 rte_rwlock_t mem_event_rwlock; 123 }; 124 125 /* Per-process data structure, not visible to other processes. */ 126 struct mlx5_local_data { 127 int init_done; /* Whether a secondary has done initialization. */ 128 }; 129 130 extern struct mlx5_shared_data *mlx5_shared_data; 131 132 struct mlx5_counter_ctrl { 133 /* Name of the counter. */ 134 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 135 /* Name of the counter on the device table. */ 136 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 137 uint32_t ib:1; /**< Nonzero for IB counters. */ 138 }; 139 140 struct mlx5_xstats_ctrl { 141 /* Number of device stats. */ 142 uint16_t stats_n; 143 /* Number of device stats identified by PMD. */ 144 uint16_t mlx5_stats_n; 145 /* Index in the device counters table. */ 146 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 147 uint64_t base[MLX5_MAX_XSTATS]; 148 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 149 }; 150 151 struct mlx5_stats_ctrl { 152 /* Base for imissed counter. */ 153 uint64_t imissed_base; 154 }; 155 156 /* devX creation object */ 157 struct mlx5_devx_obj { 158 struct mlx5dv_devx_obj *obj; /* The DV object. */ 159 int id; /* The object ID. */ 160 }; 161 162 struct mlx5_devx_mkey_attr { 163 uint64_t addr; 164 uint64_t size; 165 uint32_t umem_id; 166 uint32_t pd; 167 }; 168 169 /* HCA supports this number of time periods for LRO. */ 170 #define MLX5_LRO_NUM_SUPP_PERIODS 4 171 172 /* HCA attributes. */ 173 struct mlx5_hca_attr { 174 uint32_t eswitch_manager:1; 175 uint32_t flow_counters_dump:1; 176 uint8_t flow_counter_bulk_alloc_bitmap; 177 uint32_t eth_net_offloads:1; 178 uint32_t eth_virt:1; 179 uint32_t wqe_vlan_insert:1; 180 uint32_t wqe_inline_mode:2; 181 uint32_t vport_inline_mode:3; 182 uint32_t lro_cap:1; 183 uint32_t tunnel_lro_gre:1; 184 uint32_t tunnel_lro_vxlan:1; 185 uint32_t lro_max_msg_sz_mode:2; 186 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 187 }; 188 189 /* Flow list . */ 190 TAILQ_HEAD(mlx5_flows, rte_flow); 191 192 /* Default PMD specific parameter value. */ 193 #define MLX5_ARG_UNSET (-1) 194 195 #define MLX5_LRO_SUPPORTED(dev) \ 196 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 197 198 /* LRO configurations structure. */ 199 struct mlx5_lro_config { 200 uint32_t supported:1; /* Whether LRO is supported. */ 201 uint32_t timeout; /* User configuration. */ 202 }; 203 204 /* 205 * Device configuration structure. 206 * 207 * Merged configuration from: 208 * 209 * - Device capabilities, 210 * - User device parameters disabled features. 211 */ 212 struct mlx5_dev_config { 213 unsigned int hw_csum:1; /* Checksum offload is supported. */ 214 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 215 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 216 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 217 unsigned int hw_padding:1; /* End alignment padding is supported. */ 218 unsigned int vf:1; /* This is a VF. */ 219 unsigned int tunnel_en:1; 220 /* Whether tunnel stateless offloads are supported. */ 221 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 222 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 223 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 224 unsigned int tso:1; /* Whether TSO is supported. */ 225 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 226 unsigned int mr_ext_memseg_en:1; 227 /* Whether memseg should be extended for MR creation. */ 228 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 229 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 230 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 231 unsigned int dv_flow_en:1; /* Enable DV flow. */ 232 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 233 unsigned int devx:1; /* Whether devx interface is available or not. */ 234 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 235 struct { 236 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 237 unsigned int stride_num_n; /* Number of strides. */ 238 unsigned int min_stride_size_n; /* Min size of a stride. */ 239 unsigned int max_stride_size_n; /* Max size of a stride. */ 240 unsigned int max_memcpy_len; 241 /* Maximum packet size to memcpy Rx packets. */ 242 unsigned int min_rxqs_num; 243 /* Rx queue count threshold to enable MPRQ. */ 244 } mprq; /* Configurations for Multi-Packet RQ. */ 245 int mps; /* Multi-packet send supported mode. */ 246 unsigned int flow_prio; /* Number of flow priorities. */ 247 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 248 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 249 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 250 int txqs_inline; /* Queue number threshold for inlining. */ 251 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 252 int txq_inline_max; /* Max packet size for inlining with SEND. */ 253 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 254 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 255 struct mlx5_lro_config lro; /* LRO configuration. */ 256 }; 257 258 struct mlx5_devx_wq_attr { 259 uint32_t wq_type:4; 260 uint32_t wq_signature:1; 261 uint32_t end_padding_mode:2; 262 uint32_t cd_slave:1; 263 uint32_t hds_skip_first_sge:1; 264 uint32_t log2_hds_buf_size:3; 265 uint32_t page_offset:5; 266 uint32_t lwm:16; 267 uint32_t pd:24; 268 uint32_t uar_page:24; 269 uint64_t dbr_addr; 270 uint32_t hw_counter; 271 uint32_t sw_counter; 272 uint32_t log_wq_stride:4; 273 uint32_t log_wq_pg_sz:5; 274 uint32_t log_wq_sz:5; 275 uint32_t dbr_umem_valid:1; 276 uint32_t wq_umem_valid:1; 277 uint32_t log_hairpin_num_packets:5; 278 uint32_t log_hairpin_data_sz:5; 279 uint32_t single_wqe_log_num_of_strides:4; 280 uint32_t two_byte_shift_en:1; 281 uint32_t single_stride_log_num_of_bytes:3; 282 uint32_t dbr_umem_id; 283 uint32_t wq_umem_id; 284 uint64_t wq_umem_offset; 285 }; 286 287 /* Create RQ attributes structure, used by create RQ operation. */ 288 struct mlx5_devx_create_rq_attr { 289 uint32_t rlky:1; 290 uint32_t delay_drop_en:1; 291 uint32_t scatter_fcs:1; 292 uint32_t vsd:1; 293 uint32_t mem_rq_type:4; 294 uint32_t state:4; 295 uint32_t flush_in_error_en:1; 296 uint32_t hairpin:1; 297 uint32_t user_index:24; 298 uint32_t cqn:24; 299 uint32_t counter_set_id:8; 300 uint32_t rmpn:24; 301 struct mlx5_devx_wq_attr wq_attr; 302 }; 303 304 /* Modify RQ attributes structure, used by modify RQ operation. */ 305 struct mlx5_devx_modify_rq_attr { 306 uint32_t rqn:24; 307 uint32_t rq_state:4; /* Current RQ state. */ 308 uint32_t state:4; /* Required RQ state. */ 309 uint32_t scatter_fcs:1; 310 uint32_t vsd:1; 311 uint32_t counter_set_id:8; 312 uint32_t hairpin_peer_sq:24; 313 uint32_t hairpin_peer_vhca:16; 314 uint64_t modify_bitmask; 315 uint32_t lwm:16; /* Contained WQ lwm. */ 316 }; 317 318 struct mlx5_rx_hash_field_select { 319 uint32_t l3_prot_type:1; 320 uint32_t l4_prot_type:1; 321 uint32_t selected_fields:30; 322 }; 323 324 /* TIR attributes structure, used by TIR operations. */ 325 struct mlx5_devx_tir_attr { 326 uint32_t disp_type:4; 327 uint32_t lro_timeout_period_usecs:16; 328 uint32_t lro_enable_mask:4; 329 uint32_t lro_max_msg_sz:8; 330 uint32_t inline_rqn:24; 331 uint32_t rx_hash_symmetric:1; 332 uint32_t tunneled_offload_en:1; 333 uint32_t indirect_table:24; 334 uint32_t rx_hash_fn:4; 335 uint32_t self_lb_block:2; 336 uint32_t transport_domain:24; 337 uint32_t rx_hash_toeplitz_key[10]; 338 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 339 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 340 }; 341 342 /* RQT attributes structure, used by RQT operations. */ 343 struct mlx5_devx_rqt_attr { 344 uint32_t rqt_max_size:16; 345 uint32_t rqt_actual_size:16; 346 uint32_t rq_list[]; 347 }; 348 349 /** 350 * Type of object being allocated. 351 */ 352 enum mlx5_verbs_alloc_type { 353 MLX5_VERBS_ALLOC_TYPE_NONE, 354 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 355 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 356 }; 357 358 /** 359 * Verbs allocator needs a context to know in the callback which kind of 360 * resources it is allocating. 361 */ 362 struct mlx5_verbs_alloc_ctx { 363 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 364 const void *obj; /* Pointer to the DPDK object. */ 365 }; 366 367 LIST_HEAD(mlx5_mr_list, mlx5_mr); 368 369 /* Flow drop context necessary due to Verbs API. */ 370 struct mlx5_drop { 371 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 372 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 373 }; 374 375 #define MLX5_COUNTERS_PER_POOL 512 376 #define MLX5_MAX_PENDING_QUERIES 4 377 378 struct mlx5_flow_counter_pool; 379 380 struct flow_counter_stats { 381 uint64_t hits; 382 uint64_t bytes; 383 }; 384 385 /* Counters information. */ 386 struct mlx5_flow_counter { 387 TAILQ_ENTRY(mlx5_flow_counter) next; 388 /**< Pointer to the next flow counter structure. */ 389 uint32_t shared:1; /**< Share counter ID with other flow rules. */ 390 uint32_t batch: 1; 391 /**< Whether the counter was allocated by batch command. */ 392 uint32_t ref_cnt:30; /**< Reference counter. */ 393 uint32_t id; /**< Counter ID. */ 394 union { /**< Holds the counters for the rule. */ 395 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 396 struct ibv_counter_set *cs; 397 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 398 struct ibv_counters *cs; 399 #endif 400 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */ 401 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */ 402 }; 403 union { 404 uint64_t hits; /**< Reset value of hits packets. */ 405 int64_t query_gen; /**< Generation of the last release. */ 406 }; 407 uint64_t bytes; /**< Reset value of bytes. */ 408 void *action; /**< Pointer to the dv action. */ 409 }; 410 411 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 412 413 /* Counter pool structure - query is in pool resolution. */ 414 struct mlx5_flow_counter_pool { 415 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 416 struct mlx5_counters counters; /* Free counter list. */ 417 union { 418 struct mlx5_devx_obj *min_dcs; 419 rte_atomic64_t a64_dcs; 420 }; 421 /* The devx object of the minimum counter ID. */ 422 rte_atomic64_t query_gen; 423 uint32_t n_counters: 16; /* Number of devx allocated counters. */ 424 rte_spinlock_t sl; /* The pool lock. */ 425 struct mlx5_counter_stats_raw *raw; 426 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ 427 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */ 428 }; 429 430 struct mlx5_counter_stats_raw; 431 432 /* Memory management structure for group of counter statistics raws. */ 433 struct mlx5_counter_stats_mem_mng { 434 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 435 struct mlx5_counter_stats_raw *raws; 436 struct mlx5_devx_obj *dm; 437 struct mlx5dv_devx_umem *umem; 438 }; 439 440 /* Raw memory structure for the counter statistics values of a pool. */ 441 struct mlx5_counter_stats_raw { 442 LIST_ENTRY(mlx5_counter_stats_raw) next; 443 int min_dcs_id; 444 struct mlx5_counter_stats_mem_mng *mem_mng; 445 volatile struct flow_counter_stats *data; 446 }; 447 448 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 449 450 /* Container structure for counter pools. */ 451 struct mlx5_pools_container { 452 rte_atomic16_t n_valid; /* Number of valid pools. */ 453 uint16_t n; /* Number of pools. */ 454 struct mlx5_counter_pools pool_list; /* Counter pool list. */ 455 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 456 struct mlx5_counter_stats_mem_mng *init_mem_mng; 457 /* Hold the memory management for the next allocated pools raws. */ 458 }; 459 460 /* Counter global management structure. */ 461 struct mlx5_flow_counter_mng { 462 uint8_t mhi[2]; /* master \ host container index. */ 463 struct mlx5_pools_container ccont[2 * 2]; 464 /* 2 containers for single and for batch for double-buffer. */ 465 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 466 uint8_t pending_queries; 467 uint8_t batch; 468 uint16_t pool_index; 469 uint8_t query_thread_on; 470 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 471 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 472 }; 473 474 /* Per port data of shared IB device. */ 475 struct mlx5_ibv_shared_port { 476 uint32_t ih_port_id; 477 /* 478 * Interrupt handler port_id. Used by shared interrupt 479 * handler to find the corresponding rte_eth device 480 * by IB port index. If value is equal or greater 481 * RTE_MAX_ETHPORTS it means there is no subhandler 482 * installed for specified IB port index. 483 */ 484 }; 485 486 /* Table structure. */ 487 struct mlx5_flow_tbl_resource { 488 void *obj; /**< Pointer to DR table object. */ 489 rte_atomic32_t refcnt; /**< Reference counter. */ 490 }; 491 492 #define MLX5_MAX_TABLES 1024 493 #define MLX5_MAX_TABLES_FDB 32 494 #define MLX5_GROUP_FACTOR 1 495 496 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */ 497 #define MLX5_DBR_SIZE 8 498 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE) 499 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64) 500 501 struct mlx5_devx_dbr_page { 502 /* Door-bell records, must be first member in structure. */ 503 uint8_t dbrs[MLX5_DBR_PAGE_SIZE]; 504 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */ 505 struct mlx5dv_devx_umem *umem; 506 uint32_t dbr_count; /* Number of door-bell records in use. */ 507 /* 1 bit marks matching door-bell is in use. */ 508 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE]; 509 }; 510 511 /* 512 * Shared Infiniband device context for Master/Representors 513 * which belong to same IB device with multiple IB ports. 514 **/ 515 struct mlx5_ibv_shared { 516 LIST_ENTRY(mlx5_ibv_shared) next; 517 uint32_t refcnt; 518 uint32_t devx:1; /* Opened with DV. */ 519 uint32_t max_port; /* Maximal IB device port index. */ 520 struct ibv_context *ctx; /* Verbs/DV context. */ 521 struct ibv_pd *pd; /* Protection Domain. */ 522 uint32_t pdn; /* Protection Domain number. */ 523 uint32_t tdn; /* Transport Domain number. */ 524 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */ 525 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ 526 struct ibv_device_attr_ex device_attr; /* Device properties. */ 527 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 528 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb; 529 /**< Called by memory event callback. */ 530 struct { 531 uint32_t dev_gen; /* Generation number to flush local caches. */ 532 rte_rwlock_t rwlock; /* MR Lock. */ 533 struct mlx5_mr_btree cache; /* Global MR cache table. */ 534 struct mlx5_mr_list mr_list; /* Registered MR list. */ 535 struct mlx5_mr_list mr_free_list; /* Freed MR list. */ 536 } mr; 537 /* Shared DV/DR flow data section. */ 538 pthread_mutex_t dv_mutex; /* DV context mutex. */ 539 uint32_t dv_refcnt; /* DV/DR data reference counter. */ 540 void *fdb_domain; /* FDB Direct Rules name space handle. */ 541 struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB]; 542 /* FDB Direct Rules tables. */ 543 void *rx_domain; /* RX Direct Rules name space handle. */ 544 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES]; 545 /* RX Direct Rules tables. */ 546 void *tx_domain; /* TX Direct Rules name space handle. */ 547 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES]; 548 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ 549 /* TX Direct Rules tables/ */ 550 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; 551 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps; 552 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds; 553 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags; 554 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl; 555 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource) 556 port_id_action_list; /* List of port ID actions. */ 557 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 558 /* Shared interrupt handler section. */ 559 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */ 560 uint32_t intr_cnt; /* Interrupt handler reference counter. */ 561 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 562 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 563 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */ 564 struct mlx5_ibv_shared_port port[]; /* per device port data array. */ 565 }; 566 567 /* Per-process private structure. */ 568 struct mlx5_proc_priv { 569 size_t uar_table_sz; 570 /* Size of UAR register table. */ 571 void *uar_table[]; 572 /* Table of UAR registers for each process. */ 573 }; 574 575 #define MLX5_PROC_PRIV(port_id) \ 576 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 577 578 struct mlx5_priv { 579 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 580 struct mlx5_ibv_shared *sh; /* Shared IB device context. */ 581 uint32_t ibv_port; /* IB device port number. */ 582 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 583 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 584 /* Bit-field of MAC addresses owned by the PMD. */ 585 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 586 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 587 /* Device properties. */ 588 uint16_t mtu; /* Configured MTU. */ 589 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 590 unsigned int representor:1; /* Device is a port representor. */ 591 unsigned int master:1; /* Device is a E-Switch master. */ 592 unsigned int dr_shared:1; /* DV/DR data is shared. */ 593 unsigned int counter_fallback:1; /* Use counter fallback management. */ 594 uint16_t domain_id; /* Switch domain identifier. */ 595 uint16_t vport_id; /* Associated VF vport index (if any). */ 596 int32_t representor_id; /* Port representor identifier. */ 597 unsigned int if_index; /* Associated kernel network device index. */ 598 /* RX/TX queues. */ 599 unsigned int rxqs_n; /* RX queues array size. */ 600 unsigned int txqs_n; /* TX queues array size. */ 601 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 602 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 603 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 604 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 605 unsigned int (*reta_idx)[]; /* RETA index table. */ 606 unsigned int reta_idx_n; /* RETA index size. */ 607 struct mlx5_drop drop_queue; /* Flow drop queues. */ 608 struct mlx5_flows flows; /* RTE Flow rules. */ 609 struct mlx5_flows ctrl_flows; /* Control flow rules. */ 610 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 611 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 612 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ 613 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 614 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */ 615 /* Indirection tables. */ 616 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 617 /* Pointer to next element. */ 618 rte_atomic32_t refcnt; /**< Reference counter. */ 619 struct ibv_flow_action *verbs_action; 620 /**< Verbs modify header action object. */ 621 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 622 uint8_t max_lro_msg_size; 623 /* Tags resources cache. */ 624 uint32_t link_speed_capa; /* Link speed capabilities. */ 625 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 626 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 627 struct mlx5_dev_config config; /* Device configuration. */ 628 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 629 /* Context for Verbs allocator. */ 630 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 631 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 632 uint32_t nl_sn; /* Netlink message sequence number. */ 633 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */ 634 #ifndef RTE_ARCH_64 635 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 636 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 637 /* UAR same-page access control required in 32bit implementations. */ 638 #endif 639 }; 640 641 #define PORT_ID(priv) ((priv)->dev_data->port_id) 642 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 643 644 /* mlx5.c */ 645 646 int mlx5_getenv_int(const char *); 647 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 648 int64_t mlx5_get_dbr(struct rte_eth_dev *dev, 649 struct mlx5_devx_dbr_page **dbr_page); 650 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, 651 uint64_t offset); 652 653 /* mlx5_ethdev.c */ 654 655 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); 656 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]); 657 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 658 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); 659 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 660 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, 661 unsigned int flags); 662 int mlx5_dev_configure(struct rte_eth_dev *dev); 663 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 664 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 665 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 666 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 667 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 668 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status); 669 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 670 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 671 struct rte_eth_fc_conf *fc_conf); 672 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 673 struct rte_eth_fc_conf *fc_conf); 674 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device, 675 struct rte_pci_addr *pci_addr); 676 void mlx5_dev_link_status_handler(void *arg); 677 void mlx5_dev_interrupt_handler(void *arg); 678 void mlx5_dev_interrupt_handler_devx(void *arg); 679 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev); 680 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev); 681 int mlx5_set_link_down(struct rte_eth_dev *dev); 682 int mlx5_set_link_up(struct rte_eth_dev *dev); 683 int mlx5_is_removed(struct rte_eth_dev *dev); 684 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 685 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 686 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev, 687 uint16_t *port_list, 688 unsigned int port_list_n); 689 int mlx5_port_to_eswitch_info(uint16_t port, uint16_t *es_domain_id, 690 uint16_t *es_port_id); 691 int mlx5_sysfs_switch_info(unsigned int ifindex, 692 struct mlx5_switch_info *info); 693 void mlx5_sysfs_check_switch_info(bool device_dir, 694 struct mlx5_switch_info *switch_info); 695 void mlx5_nl_check_switch_info(bool nun_vf_set, 696 struct mlx5_switch_info *switch_info); 697 void mlx5_translate_port_name(const char *port_name_in, 698 struct mlx5_switch_info *port_info_out); 699 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 700 rte_intr_callback_fn cb_fn, void *cb_arg); 701 702 /* mlx5_mac.c */ 703 704 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 705 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 706 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 707 uint32_t index, uint32_t vmdq); 708 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 709 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 710 struct rte_ether_addr *mc_addr_set, 711 uint32_t nb_mc_addr); 712 713 /* mlx5_rss.c */ 714 715 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 716 struct rte_eth_rss_conf *rss_conf); 717 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 718 struct rte_eth_rss_conf *rss_conf); 719 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 720 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 721 struct rte_eth_rss_reta_entry64 *reta_conf, 722 uint16_t reta_size); 723 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 724 struct rte_eth_rss_reta_entry64 *reta_conf, 725 uint16_t reta_size); 726 727 /* mlx5_rxmode.c */ 728 729 void mlx5_promiscuous_enable(struct rte_eth_dev *dev); 730 void mlx5_promiscuous_disable(struct rte_eth_dev *dev); 731 void mlx5_allmulticast_enable(struct rte_eth_dev *dev); 732 void mlx5_allmulticast_disable(struct rte_eth_dev *dev); 733 734 /* mlx5_stats.c */ 735 736 void mlx5_stats_init(struct rte_eth_dev *dev); 737 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 738 void mlx5_stats_reset(struct rte_eth_dev *dev); 739 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 740 unsigned int n); 741 void mlx5_xstats_reset(struct rte_eth_dev *dev); 742 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 743 struct rte_eth_xstat_name *xstats_names, 744 unsigned int n); 745 746 /* mlx5_vlan.c */ 747 748 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 749 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 750 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 751 752 /* mlx5_trigger.c */ 753 754 int mlx5_dev_start(struct rte_eth_dev *dev); 755 void mlx5_dev_stop(struct rte_eth_dev *dev); 756 int mlx5_traffic_enable(struct rte_eth_dev *dev); 757 void mlx5_traffic_disable(struct rte_eth_dev *dev); 758 int mlx5_traffic_restart(struct rte_eth_dev *dev); 759 760 /* mlx5_flow.c */ 761 762 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 763 void mlx5_flow_print(struct rte_flow *flow); 764 int mlx5_flow_validate(struct rte_eth_dev *dev, 765 const struct rte_flow_attr *attr, 766 const struct rte_flow_item items[], 767 const struct rte_flow_action actions[], 768 struct rte_flow_error *error); 769 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 770 const struct rte_flow_attr *attr, 771 const struct rte_flow_item items[], 772 const struct rte_flow_action actions[], 773 struct rte_flow_error *error); 774 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 775 struct rte_flow_error *error); 776 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list); 777 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 778 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 779 const struct rte_flow_action *action, void *data, 780 struct rte_flow_error *error); 781 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 782 struct rte_flow_error *error); 783 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 784 enum rte_filter_type filter_type, 785 enum rte_filter_op filter_op, 786 void *arg); 787 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list); 788 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list); 789 int mlx5_flow_verify(struct rte_eth_dev *dev); 790 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 791 struct rte_flow_item_eth *eth_spec, 792 struct rte_flow_item_eth *eth_mask, 793 struct rte_flow_item_vlan *vlan_spec, 794 struct rte_flow_item_vlan *vlan_mask); 795 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 796 struct rte_flow_item_eth *eth_spec, 797 struct rte_flow_item_eth *eth_mask); 798 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 799 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 800 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh, 801 uint64_t async_id, int status); 802 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh); 803 void mlx5_flow_query_alarm(void *arg); 804 805 /* mlx5_mp.c */ 806 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev); 807 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev); 808 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr); 809 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev); 810 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev, 811 struct mlx5_mp_arg_queue_state_modify *sm); 812 int mlx5_mp_init_primary(void); 813 void mlx5_mp_uninit_primary(void); 814 int mlx5_mp_init_secondary(void); 815 void mlx5_mp_uninit_secondary(void); 816 817 /* mlx5_nl.c */ 818 819 int mlx5_nl_init(int protocol); 820 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 821 uint32_t index); 822 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 823 uint32_t index); 824 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev); 825 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev); 826 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable); 827 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable); 828 unsigned int mlx5_nl_portnum(int nl, const char *name); 829 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex); 830 int mlx5_nl_switch_info(int nl, unsigned int ifindex, 831 struct mlx5_switch_info *info); 832 833 /* mlx5_devx_cmds.c */ 834 835 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, 836 uint32_t bulk_sz); 837 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 838 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 839 int clear, uint32_t n_counters, 840 uint64_t *pkts, uint64_t *bytes, 841 uint32_t mkey, void *addr, 842 struct mlx5dv_devx_cmd_comp *cmd_comp, 843 uint64_t async_id); 844 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx, 845 struct mlx5_hca_attr *attr); 846 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx, 847 struct mlx5_devx_mkey_attr *attr); 848 int mlx5_devx_get_out_command_status(void *out); 849 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num, 850 uint32_t *tis_td); 851 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx, 852 struct mlx5_devx_create_rq_attr *rq_attr, 853 int socket); 854 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 855 struct mlx5_devx_modify_rq_attr *rq_attr); 856 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx, 857 struct mlx5_devx_tir_attr *tir_attr); 858 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx, 859 struct mlx5_devx_rqt_attr *rqt_attr); 860 861 #endif /* RTE_PMD_MLX5_H_ */ 862