1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/rtnetlink.h> 17 18 /* Verbs header. */ 19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic ignored "-Wpedantic" 22 #endif 23 #include <infiniband/verbs.h> 24 #ifdef PEDANTIC 25 #pragma GCC diagnostic error "-Wpedantic" 26 #endif 27 28 #include <rte_malloc.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_pci.h> 32 #include <rte_bus_pci.h> 33 #include <rte_common.h> 34 #include <rte_config.h> 35 #include <rte_eal_memconfig.h> 36 #include <rte_kvargs.h> 37 #include <rte_rwlock.h> 38 #include <rte_spinlock.h> 39 #include <rte_string_fns.h> 40 #include <rte_alarm.h> 41 42 #include "mlx5.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_rxtx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_defs.h" 47 #include "mlx5_glue.h" 48 #include "mlx5_mr.h" 49 #include "mlx5_flow.h" 50 51 /* Device parameter to enable RX completion queue compression. */ 52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 53 54 /* Device parameter to enable RX completion entry padding to 128B. */ 55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en" 56 57 /* Device parameter to enable padding Rx packet to cacheline size. */ 58 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 59 60 /* Device parameter to enable Multi-Packet Rx queue. */ 61 #define MLX5_RX_MPRQ_EN "mprq_en" 62 63 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 64 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 65 66 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 67 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 68 69 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 70 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 71 72 /* Device parameter to configure inline send. Deprecated, ignored.*/ 73 #define MLX5_TXQ_INLINE "txq_inline" 74 75 /* Device parameter to limit packet size to inline with ordinary SEND. */ 76 #define MLX5_TXQ_INLINE_MAX "txq_inline_max" 77 78 /* Device parameter to configure minimal data size to inline. */ 79 #define MLX5_TXQ_INLINE_MIN "txq_inline_min" 80 81 /* Device parameter to limit packet size to inline with Enhanced MPW. */ 82 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" 83 84 /* 85 * Device parameter to configure the number of TX queues threshold for 86 * enabling inline send. 87 */ 88 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 89 90 /* 91 * Device parameter to configure the number of TX queues threshold for 92 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). 93 */ 94 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 95 96 /* Device parameter to enable multi-packet send WQEs. */ 97 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 98 99 /* 100 * Device parameter to include 2 dsegs in the title WQEBB. 101 * Deprecated, ignored. 102 */ 103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 104 105 /* 106 * Device parameter to limit the size of inlining packet. 107 * Deprecated, ignored. 108 */ 109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 110 111 /* 112 * Device parameter to enable hardware Tx vector. 113 * Deprecated, ignored (no vectorized Tx routines anymore). 114 */ 115 #define MLX5_TX_VEC_EN "tx_vec_en" 116 117 /* Device parameter to enable hardware Rx vector. */ 118 #define MLX5_RX_VEC_EN "rx_vec_en" 119 120 /* Allow L3 VXLAN flow creation. */ 121 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 122 123 /* Activate DV E-Switch flow steering. */ 124 #define MLX5_DV_ESW_EN "dv_esw_en" 125 126 /* Activate DV flow steering. */ 127 #define MLX5_DV_FLOW_EN "dv_flow_en" 128 129 /* Activate Netlink support in VF mode. */ 130 #define MLX5_VF_NL_EN "vf_nl_en" 131 132 /* Enable extending memsegs when creating a MR. */ 133 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en" 134 135 /* Select port representors to instantiate. */ 136 #define MLX5_REPRESENTOR "representor" 137 138 /* Device parameter to configure the maximum number of dump files per queue. */ 139 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 140 141 /* Configure timeout of LRO session (in microseconds). */ 142 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" 143 144 #ifndef HAVE_IBV_MLX5_MOD_MPW 145 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 146 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 147 #endif 148 149 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 150 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 151 #endif 152 153 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 154 155 /* Shared memory between primary and secondary processes. */ 156 struct mlx5_shared_data *mlx5_shared_data; 157 158 /* Spinlock for mlx5_shared_data allocation. */ 159 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 160 161 /* Process local data for secondary processes. */ 162 static struct mlx5_local_data mlx5_local_data; 163 164 /** Driver-specific log messages type. */ 165 int mlx5_logtype; 166 167 /** Data associated with devices to spawn. */ 168 struct mlx5_dev_spawn_data { 169 uint32_t ifindex; /**< Network interface index. */ 170 uint32_t max_port; /**< IB device maximal port index. */ 171 uint32_t ibv_port; /**< IB device physical port index. */ 172 struct mlx5_switch_info info; /**< Switch information. */ 173 struct ibv_device *ibv_dev; /**< Associated IB device. */ 174 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 175 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 176 }; 177 178 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER(); 179 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER; 180 181 /** 182 * Initialize the counters management structure. 183 * 184 * @param[in] sh 185 * Pointer to mlx5_ibv_shared object to free 186 */ 187 static void 188 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh) 189 { 190 uint8_t i; 191 192 TAILQ_INIT(&sh->cmng.flow_counters); 193 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) 194 TAILQ_INIT(&sh->cmng.ccont[i].pool_list); 195 } 196 197 /** 198 * Destroy all the resources allocated for a counter memory management. 199 * 200 * @param[in] mng 201 * Pointer to the memory management structure. 202 */ 203 static void 204 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) 205 { 206 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; 207 208 LIST_REMOVE(mng, next); 209 claim_zero(mlx5_devx_cmd_destroy(mng->dm)); 210 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem)); 211 rte_free(mem); 212 } 213 214 /** 215 * Close and release all the resources of the counters management. 216 * 217 * @param[in] sh 218 * Pointer to mlx5_ibv_shared object to free. 219 */ 220 static void 221 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh) 222 { 223 struct mlx5_counter_stats_mem_mng *mng; 224 uint8_t i; 225 int j; 226 int retries = 1024; 227 228 rte_errno = 0; 229 while (--retries) { 230 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); 231 if (rte_errno != EINPROGRESS) 232 break; 233 rte_pause(); 234 } 235 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) { 236 struct mlx5_flow_counter_pool *pool; 237 uint32_t batch = !!(i % 2); 238 239 if (!sh->cmng.ccont[i].pools) 240 continue; 241 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list); 242 while (pool) { 243 if (batch) { 244 if (pool->min_dcs) 245 claim_zero 246 (mlx5_devx_cmd_destroy(pool->min_dcs)); 247 } 248 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { 249 if (pool->counters_raw[j].action) 250 claim_zero 251 (mlx5_glue->destroy_flow_action 252 (pool->counters_raw[j].action)); 253 if (!batch && pool->counters_raw[j].dcs) 254 claim_zero(mlx5_devx_cmd_destroy 255 (pool->counters_raw[j].dcs)); 256 } 257 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, 258 next); 259 rte_free(pool); 260 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list); 261 } 262 rte_free(sh->cmng.ccont[i].pools); 263 } 264 mng = LIST_FIRST(&sh->cmng.mem_mngs); 265 while (mng) { 266 mlx5_flow_destroy_counter_stat_mem_mng(mng); 267 mng = LIST_FIRST(&sh->cmng.mem_mngs); 268 } 269 memset(&sh->cmng, 0, sizeof(sh->cmng)); 270 } 271 272 /** 273 * Extract pdn of PD object using DV API. 274 * 275 * @param[in] pd 276 * Pointer to the verbs PD object. 277 * @param[out] pdn 278 * Pointer to the PD object number variable. 279 * 280 * @return 281 * 0 on success, error value otherwise. 282 */ 283 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 284 static int 285 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused) 286 { 287 struct mlx5dv_obj obj; 288 struct mlx5dv_pd pd_info; 289 int ret = 0; 290 291 obj.pd.in = pd; 292 obj.pd.out = &pd_info; 293 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 294 if (ret) { 295 DRV_LOG(DEBUG, "Fail to get PD object info"); 296 return ret; 297 } 298 *pdn = pd_info.pdn; 299 return 0; 300 } 301 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 302 303 /** 304 * Allocate shared IB device context. If there is multiport device the 305 * master and representors will share this context, if there is single 306 * port dedicated IB device, the context will be used by only given 307 * port due to unification. 308 * 309 * Routine first searches the context for the specified IB device name, 310 * if found the shared context assumed and reference counter is incremented. 311 * If no context found the new one is created and initialized with specified 312 * IB device context and parameters. 313 * 314 * @param[in] spawn 315 * Pointer to the IB device attributes (name, port, etc). 316 * 317 * @return 318 * Pointer to mlx5_ibv_shared object on success, 319 * otherwise NULL and rte_errno is set. 320 */ 321 static struct mlx5_ibv_shared * 322 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn) 323 { 324 struct mlx5_ibv_shared *sh; 325 int err = 0; 326 uint32_t i; 327 328 assert(spawn); 329 /* Secondary process should not create the shared context. */ 330 assert(rte_eal_process_type() == RTE_PROC_PRIMARY); 331 pthread_mutex_lock(&mlx5_ibv_list_mutex); 332 /* Search for IB context by device name. */ 333 LIST_FOREACH(sh, &mlx5_ibv_list, next) { 334 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) { 335 sh->refcnt++; 336 goto exit; 337 } 338 } 339 /* No device found, we have to create new shared context. */ 340 assert(spawn->max_port); 341 sh = rte_zmalloc("ethdev shared ib context", 342 sizeof(struct mlx5_ibv_shared) + 343 spawn->max_port * 344 sizeof(struct mlx5_ibv_shared_port), 345 RTE_CACHE_LINE_SIZE); 346 if (!sh) { 347 DRV_LOG(ERR, "shared context allocation failure"); 348 rte_errno = ENOMEM; 349 goto exit; 350 } 351 /* Try to open IB device with DV first, then usual Verbs. */ 352 errno = 0; 353 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev); 354 if (sh->ctx) { 355 sh->devx = 1; 356 DRV_LOG(DEBUG, "DevX is supported"); 357 } else { 358 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev); 359 if (!sh->ctx) { 360 err = errno ? errno : ENODEV; 361 goto error; 362 } 363 DRV_LOG(DEBUG, "DevX is NOT supported"); 364 } 365 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr); 366 if (err) { 367 DRV_LOG(DEBUG, "ibv_query_device_ex() failed"); 368 goto error; 369 } 370 sh->refcnt = 1; 371 sh->max_port = spawn->max_port; 372 strncpy(sh->ibdev_name, sh->ctx->device->name, 373 sizeof(sh->ibdev_name)); 374 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path, 375 sizeof(sh->ibdev_path)); 376 sh->pci_dev = spawn->pci_dev; 377 pthread_mutex_init(&sh->intr_mutex, NULL); 378 /* 379 * Setting port_id to max unallowed value means 380 * there is no interrupt subhandler installed for 381 * the given port index i. 382 */ 383 for (i = 0; i < sh->max_port; i++) 384 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 385 sh->pd = mlx5_glue->alloc_pd(sh->ctx); 386 if (sh->pd == NULL) { 387 DRV_LOG(ERR, "PD allocation failure"); 388 err = ENOMEM; 389 goto error; 390 } 391 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 392 err = mlx5_get_pdn(sh->pd, &sh->pdn); 393 if (err) { 394 DRV_LOG(ERR, "Fail to extract pdn from PD"); 395 goto error; 396 } 397 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 398 /* 399 * Once the device is added to the list of memory event 400 * callback, its global MR cache table cannot be expanded 401 * on the fly because of deadlock. If it overflows, lookup 402 * should be done by searching MR list linearly, which is slow. 403 * 404 * At this point the device is not added to the memory 405 * event list yet, context is just being created. 406 */ 407 err = mlx5_mr_btree_init(&sh->mr.cache, 408 MLX5_MR_BTREE_CACHE_N * 2, 409 sh->pci_dev->device.numa_node); 410 if (err) { 411 err = rte_errno; 412 goto error; 413 } 414 mlx5_flow_counters_mng_init(sh); 415 /* Add device to memory callback list. */ 416 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 417 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 418 sh, mem_event_cb); 419 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 420 /* Add context to the global device list. */ 421 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next); 422 exit: 423 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 424 return sh; 425 error: 426 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 427 assert(sh); 428 if (sh->pd) 429 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 430 if (sh->ctx) 431 claim_zero(mlx5_glue->close_device(sh->ctx)); 432 rte_free(sh); 433 assert(err > 0); 434 rte_errno = err; 435 return NULL; 436 } 437 438 /** 439 * Free shared IB device context. Decrement counter and if zero free 440 * all allocated resources and close handles. 441 * 442 * @param[in] sh 443 * Pointer to mlx5_ibv_shared object to free 444 */ 445 static void 446 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh) 447 { 448 pthread_mutex_lock(&mlx5_ibv_list_mutex); 449 #ifndef NDEBUG 450 /* Check the object presence in the list. */ 451 struct mlx5_ibv_shared *lctx; 452 453 LIST_FOREACH(lctx, &mlx5_ibv_list, next) 454 if (lctx == sh) 455 break; 456 assert(lctx); 457 if (lctx != sh) { 458 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 459 goto exit; 460 } 461 #endif 462 assert(sh); 463 assert(sh->refcnt); 464 /* Secondary process should not free the shared context. */ 465 assert(rte_eal_process_type() == RTE_PROC_PRIMARY); 466 if (--sh->refcnt) 467 goto exit; 468 /* Release created Memory Regions. */ 469 mlx5_mr_release(sh); 470 /* Remove from memory callback device list. */ 471 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 472 LIST_REMOVE(sh, mem_event_cb); 473 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 474 /* Remove context from the global device list. */ 475 LIST_REMOVE(sh, next); 476 /* 477 * Ensure there is no async event handler installed. 478 * Only primary process handles async device events. 479 **/ 480 mlx5_flow_counters_mng_close(sh); 481 assert(!sh->intr_cnt); 482 if (sh->intr_cnt) 483 mlx5_intr_callback_unregister 484 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh); 485 pthread_mutex_destroy(&sh->intr_mutex); 486 if (sh->pd) 487 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 488 if (sh->ctx) 489 claim_zero(mlx5_glue->close_device(sh->ctx)); 490 rte_free(sh); 491 exit: 492 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 493 } 494 495 /** 496 * Initialize DR related data within private structure. 497 * Routine checks the reference counter and does actual 498 * resources creation/initialization only if counter is zero. 499 * 500 * @param[in] priv 501 * Pointer to the private device data structure. 502 * 503 * @return 504 * Zero on success, positive error code otherwise. 505 */ 506 static int 507 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 508 { 509 #ifdef HAVE_MLX5DV_DR 510 struct mlx5_ibv_shared *sh = priv->sh; 511 int err = 0; 512 void *domain; 513 514 assert(sh); 515 if (sh->dv_refcnt) { 516 /* Shared DV/DR structures is already initialized. */ 517 sh->dv_refcnt++; 518 priv->dr_shared = 1; 519 return 0; 520 } 521 /* Reference counter is zero, we should initialize structures. */ 522 domain = mlx5_glue->dr_create_domain(sh->ctx, 523 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 524 if (!domain) { 525 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 526 err = errno; 527 goto error; 528 } 529 sh->rx_domain = domain; 530 domain = mlx5_glue->dr_create_domain(sh->ctx, 531 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 532 if (!domain) { 533 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 534 err = errno; 535 goto error; 536 } 537 pthread_mutex_init(&sh->dv_mutex, NULL); 538 sh->tx_domain = domain; 539 #ifdef HAVE_MLX5DV_DR_ESWITCH 540 if (priv->config.dv_esw_en) { 541 domain = mlx5_glue->dr_create_domain 542 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 543 if (!domain) { 544 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 545 err = errno; 546 goto error; 547 } 548 sh->fdb_domain = domain; 549 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 550 } 551 #endif 552 sh->dv_refcnt++; 553 priv->dr_shared = 1; 554 return 0; 555 556 error: 557 /* Rollback the created objects. */ 558 if (sh->rx_domain) { 559 mlx5_glue->dr_destroy_domain(sh->rx_domain); 560 sh->rx_domain = NULL; 561 } 562 if (sh->tx_domain) { 563 mlx5_glue->dr_destroy_domain(sh->tx_domain); 564 sh->tx_domain = NULL; 565 } 566 if (sh->fdb_domain) { 567 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 568 sh->fdb_domain = NULL; 569 } 570 if (sh->esw_drop_action) { 571 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 572 sh->esw_drop_action = NULL; 573 } 574 return err; 575 #else 576 (void)priv; 577 return 0; 578 #endif 579 } 580 581 /** 582 * Destroy DR related data within private structure. 583 * 584 * @param[in] priv 585 * Pointer to the private device data structure. 586 */ 587 static void 588 mlx5_free_shared_dr(struct mlx5_priv *priv) 589 { 590 #ifdef HAVE_MLX5DV_DR 591 struct mlx5_ibv_shared *sh; 592 593 if (!priv->dr_shared) 594 return; 595 priv->dr_shared = 0; 596 sh = priv->sh; 597 assert(sh); 598 assert(sh->dv_refcnt); 599 if (sh->dv_refcnt && --sh->dv_refcnt) 600 return; 601 if (sh->rx_domain) { 602 mlx5_glue->dr_destroy_domain(sh->rx_domain); 603 sh->rx_domain = NULL; 604 } 605 if (sh->tx_domain) { 606 mlx5_glue->dr_destroy_domain(sh->tx_domain); 607 sh->tx_domain = NULL; 608 } 609 #ifdef HAVE_MLX5DV_DR_ESWITCH 610 if (sh->fdb_domain) { 611 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 612 sh->fdb_domain = NULL; 613 } 614 if (sh->esw_drop_action) { 615 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 616 sh->esw_drop_action = NULL; 617 } 618 #endif 619 pthread_mutex_destroy(&sh->dv_mutex); 620 #else 621 (void)priv; 622 #endif 623 } 624 625 /** 626 * Initialize shared data between primary and secondary process. 627 * 628 * A memzone is reserved by primary process and secondary processes attach to 629 * the memzone. 630 * 631 * @return 632 * 0 on success, a negative errno value otherwise and rte_errno is set. 633 */ 634 static int 635 mlx5_init_shared_data(void) 636 { 637 const struct rte_memzone *mz; 638 int ret = 0; 639 640 rte_spinlock_lock(&mlx5_shared_data_lock); 641 if (mlx5_shared_data == NULL) { 642 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 643 /* Allocate shared memory. */ 644 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 645 sizeof(*mlx5_shared_data), 646 SOCKET_ID_ANY, 0); 647 if (mz == NULL) { 648 DRV_LOG(ERR, 649 "Cannot allocate mlx5 shared data\n"); 650 ret = -rte_errno; 651 goto error; 652 } 653 mlx5_shared_data = mz->addr; 654 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 655 rte_spinlock_init(&mlx5_shared_data->lock); 656 } else { 657 /* Lookup allocated shared memory. */ 658 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 659 if (mz == NULL) { 660 DRV_LOG(ERR, 661 "Cannot attach mlx5 shared data\n"); 662 ret = -rte_errno; 663 goto error; 664 } 665 mlx5_shared_data = mz->addr; 666 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 667 } 668 } 669 error: 670 rte_spinlock_unlock(&mlx5_shared_data_lock); 671 return ret; 672 } 673 674 /** 675 * Retrieve integer value from environment variable. 676 * 677 * @param[in] name 678 * Environment variable name. 679 * 680 * @return 681 * Integer value, 0 if the variable is not set. 682 */ 683 int 684 mlx5_getenv_int(const char *name) 685 { 686 const char *val = getenv(name); 687 688 if (val == NULL) 689 return 0; 690 return atoi(val); 691 } 692 693 /** 694 * Verbs callback to allocate a memory. This function should allocate the space 695 * according to the size provided residing inside a huge page. 696 * Please note that all allocation must respect the alignment from libmlx5 697 * (i.e. currently sysconf(_SC_PAGESIZE)). 698 * 699 * @param[in] size 700 * The size in bytes of the memory to allocate. 701 * @param[in] data 702 * A pointer to the callback data. 703 * 704 * @return 705 * Allocated buffer, NULL otherwise and rte_errno is set. 706 */ 707 static void * 708 mlx5_alloc_verbs_buf(size_t size, void *data) 709 { 710 struct mlx5_priv *priv = data; 711 void *ret; 712 size_t alignment = sysconf(_SC_PAGESIZE); 713 unsigned int socket = SOCKET_ID_ANY; 714 715 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 716 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 717 718 socket = ctrl->socket; 719 } else if (priv->verbs_alloc_ctx.type == 720 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 721 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 722 723 socket = ctrl->socket; 724 } 725 assert(data != NULL); 726 ret = rte_malloc_socket(__func__, size, alignment, socket); 727 if (!ret && size) 728 rte_errno = ENOMEM; 729 return ret; 730 } 731 732 /** 733 * Verbs callback to free a memory. 734 * 735 * @param[in] ptr 736 * A pointer to the memory to free. 737 * @param[in] data 738 * A pointer to the callback data. 739 */ 740 static void 741 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 742 { 743 assert(data != NULL); 744 rte_free(ptr); 745 } 746 747 /** 748 * DPDK callback to add udp tunnel port 749 * 750 * @param[in] dev 751 * A pointer to eth_dev 752 * @param[in] udp_tunnel 753 * A pointer to udp tunnel 754 * 755 * @return 756 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise. 757 */ 758 int 759 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, 760 struct rte_eth_udp_tunnel *udp_tunnel) 761 { 762 assert(udp_tunnel != NULL); 763 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN && 764 udp_tunnel->udp_port == 4789) 765 return 0; 766 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE && 767 udp_tunnel->udp_port == 4790) 768 return 0; 769 return -ENOTSUP; 770 } 771 772 /** 773 * Initialize process private data structure. 774 * 775 * @param dev 776 * Pointer to Ethernet device structure. 777 * 778 * @return 779 * 0 on success, a negative errno value otherwise and rte_errno is set. 780 */ 781 int 782 mlx5_proc_priv_init(struct rte_eth_dev *dev) 783 { 784 struct mlx5_priv *priv = dev->data->dev_private; 785 struct mlx5_proc_priv *ppriv; 786 size_t ppriv_size; 787 788 /* 789 * UAR register table follows the process private structure. BlueFlame 790 * registers for Tx queues are stored in the table. 791 */ 792 ppriv_size = 793 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); 794 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size, 795 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 796 if (!ppriv) { 797 rte_errno = ENOMEM; 798 return -rte_errno; 799 } 800 ppriv->uar_table_sz = ppriv_size; 801 dev->process_private = ppriv; 802 return 0; 803 } 804 805 /** 806 * Un-initialize process private data structure. 807 * 808 * @param dev 809 * Pointer to Ethernet device structure. 810 */ 811 static void 812 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 813 { 814 if (!dev->process_private) 815 return; 816 rte_free(dev->process_private); 817 dev->process_private = NULL; 818 } 819 820 /** 821 * DPDK callback to close the device. 822 * 823 * Destroy all queues and objects, free memory. 824 * 825 * @param dev 826 * Pointer to Ethernet device structure. 827 */ 828 static void 829 mlx5_dev_close(struct rte_eth_dev *dev) 830 { 831 struct mlx5_priv *priv = dev->data->dev_private; 832 unsigned int i; 833 int ret; 834 835 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 836 dev->data->port_id, 837 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : "")); 838 /* In case mlx5_dev_stop() has not been called. */ 839 mlx5_dev_interrupt_handler_uninstall(dev); 840 mlx5_traffic_disable(dev); 841 mlx5_flow_flush(dev, NULL); 842 /* Prevent crashes when queues are still in use. */ 843 dev->rx_pkt_burst = removed_rx_burst; 844 dev->tx_pkt_burst = removed_tx_burst; 845 rte_wmb(); 846 /* Disable datapath on secondary process. */ 847 mlx5_mp_req_stop_rxtx(dev); 848 if (priv->rxqs != NULL) { 849 /* XXX race condition if mlx5_rx_burst() is still running. */ 850 usleep(1000); 851 for (i = 0; (i != priv->rxqs_n); ++i) 852 mlx5_rxq_release(dev, i); 853 priv->rxqs_n = 0; 854 priv->rxqs = NULL; 855 } 856 if (priv->txqs != NULL) { 857 /* XXX race condition if mlx5_tx_burst() is still running. */ 858 usleep(1000); 859 for (i = 0; (i != priv->txqs_n); ++i) 860 mlx5_txq_release(dev, i); 861 priv->txqs_n = 0; 862 priv->txqs = NULL; 863 } 864 mlx5_proc_priv_uninit(dev); 865 mlx5_mprq_free_mp(dev); 866 mlx5_free_shared_dr(priv); 867 if (priv->rss_conf.rss_key != NULL) 868 rte_free(priv->rss_conf.rss_key); 869 if (priv->reta_idx != NULL) 870 rte_free(priv->reta_idx); 871 if (priv->config.vf) 872 mlx5_nl_mac_addr_flush(dev); 873 if (priv->nl_socket_route >= 0) 874 close(priv->nl_socket_route); 875 if (priv->nl_socket_rdma >= 0) 876 close(priv->nl_socket_rdma); 877 if (priv->vmwa_context) 878 mlx5_vlan_vmwa_exit(priv->vmwa_context); 879 if (priv->sh) { 880 /* 881 * Free the shared context in last turn, because the cleanup 882 * routines above may use some shared fields, like 883 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing 884 * ifindex if Netlink fails. 885 */ 886 mlx5_free_shared_ibctx(priv->sh); 887 priv->sh = NULL; 888 } 889 ret = mlx5_hrxq_verify(dev); 890 if (ret) 891 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 892 dev->data->port_id); 893 ret = mlx5_ind_table_obj_verify(dev); 894 if (ret) 895 DRV_LOG(WARNING, "port %u some indirection table still remain", 896 dev->data->port_id); 897 ret = mlx5_rxq_obj_verify(dev); 898 if (ret) 899 DRV_LOG(WARNING, "port %u some Rx queue objects still remain", 900 dev->data->port_id); 901 ret = mlx5_rxq_verify(dev); 902 if (ret) 903 DRV_LOG(WARNING, "port %u some Rx queues still remain", 904 dev->data->port_id); 905 ret = mlx5_txq_ibv_verify(dev); 906 if (ret) 907 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 908 dev->data->port_id); 909 ret = mlx5_txq_verify(dev); 910 if (ret) 911 DRV_LOG(WARNING, "port %u some Tx queues still remain", 912 dev->data->port_id); 913 ret = mlx5_flow_verify(dev); 914 if (ret) 915 DRV_LOG(WARNING, "port %u some flows still remain", 916 dev->data->port_id); 917 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 918 unsigned int c = 0; 919 uint16_t port_id; 920 921 RTE_ETH_FOREACH_DEV_OF(port_id, dev->device) { 922 struct mlx5_priv *opriv = 923 rte_eth_devices[port_id].data->dev_private; 924 925 if (!opriv || 926 opriv->domain_id != priv->domain_id || 927 &rte_eth_devices[port_id] == dev) 928 continue; 929 ++c; 930 } 931 if (!c) 932 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 933 } 934 memset(priv, 0, sizeof(*priv)); 935 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 936 /* 937 * Reset mac_addrs to NULL such that it is not freed as part of 938 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 939 * it is freed when dev_private is freed. 940 */ 941 dev->data->mac_addrs = NULL; 942 } 943 944 const struct eth_dev_ops mlx5_dev_ops = { 945 .dev_configure = mlx5_dev_configure, 946 .dev_start = mlx5_dev_start, 947 .dev_stop = mlx5_dev_stop, 948 .dev_set_link_down = mlx5_set_link_down, 949 .dev_set_link_up = mlx5_set_link_up, 950 .dev_close = mlx5_dev_close, 951 .promiscuous_enable = mlx5_promiscuous_enable, 952 .promiscuous_disable = mlx5_promiscuous_disable, 953 .allmulticast_enable = mlx5_allmulticast_enable, 954 .allmulticast_disable = mlx5_allmulticast_disable, 955 .link_update = mlx5_link_update, 956 .stats_get = mlx5_stats_get, 957 .stats_reset = mlx5_stats_reset, 958 .xstats_get = mlx5_xstats_get, 959 .xstats_reset = mlx5_xstats_reset, 960 .xstats_get_names = mlx5_xstats_get_names, 961 .fw_version_get = mlx5_fw_version_get, 962 .dev_infos_get = mlx5_dev_infos_get, 963 .read_clock = mlx5_read_clock, 964 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 965 .vlan_filter_set = mlx5_vlan_filter_set, 966 .rx_queue_setup = mlx5_rx_queue_setup, 967 .tx_queue_setup = mlx5_tx_queue_setup, 968 .rx_queue_release = mlx5_rx_queue_release, 969 .tx_queue_release = mlx5_tx_queue_release, 970 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 971 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 972 .mac_addr_remove = mlx5_mac_addr_remove, 973 .mac_addr_add = mlx5_mac_addr_add, 974 .mac_addr_set = mlx5_mac_addr_set, 975 .set_mc_addr_list = mlx5_set_mc_addr_list, 976 .mtu_set = mlx5_dev_set_mtu, 977 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 978 .vlan_offload_set = mlx5_vlan_offload_set, 979 .reta_update = mlx5_dev_rss_reta_update, 980 .reta_query = mlx5_dev_rss_reta_query, 981 .rss_hash_update = mlx5_rss_hash_update, 982 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 983 .filter_ctrl = mlx5_dev_filter_ctrl, 984 .rx_descriptor_status = mlx5_rx_descriptor_status, 985 .tx_descriptor_status = mlx5_tx_descriptor_status, 986 .rx_queue_count = mlx5_rx_queue_count, 987 .rx_queue_intr_enable = mlx5_rx_intr_enable, 988 .rx_queue_intr_disable = mlx5_rx_intr_disable, 989 .is_removed = mlx5_is_removed, 990 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 991 }; 992 993 /* Available operations from secondary process. */ 994 static const struct eth_dev_ops mlx5_dev_sec_ops = { 995 .stats_get = mlx5_stats_get, 996 .stats_reset = mlx5_stats_reset, 997 .xstats_get = mlx5_xstats_get, 998 .xstats_reset = mlx5_xstats_reset, 999 .xstats_get_names = mlx5_xstats_get_names, 1000 .fw_version_get = mlx5_fw_version_get, 1001 .dev_infos_get = mlx5_dev_infos_get, 1002 .rx_descriptor_status = mlx5_rx_descriptor_status, 1003 .tx_descriptor_status = mlx5_tx_descriptor_status, 1004 }; 1005 1006 /* Available operations in flow isolated mode. */ 1007 const struct eth_dev_ops mlx5_dev_ops_isolate = { 1008 .dev_configure = mlx5_dev_configure, 1009 .dev_start = mlx5_dev_start, 1010 .dev_stop = mlx5_dev_stop, 1011 .dev_set_link_down = mlx5_set_link_down, 1012 .dev_set_link_up = mlx5_set_link_up, 1013 .dev_close = mlx5_dev_close, 1014 .promiscuous_enable = mlx5_promiscuous_enable, 1015 .promiscuous_disable = mlx5_promiscuous_disable, 1016 .allmulticast_enable = mlx5_allmulticast_enable, 1017 .allmulticast_disable = mlx5_allmulticast_disable, 1018 .link_update = mlx5_link_update, 1019 .stats_get = mlx5_stats_get, 1020 .stats_reset = mlx5_stats_reset, 1021 .xstats_get = mlx5_xstats_get, 1022 .xstats_reset = mlx5_xstats_reset, 1023 .xstats_get_names = mlx5_xstats_get_names, 1024 .fw_version_get = mlx5_fw_version_get, 1025 .dev_infos_get = mlx5_dev_infos_get, 1026 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 1027 .vlan_filter_set = mlx5_vlan_filter_set, 1028 .rx_queue_setup = mlx5_rx_queue_setup, 1029 .tx_queue_setup = mlx5_tx_queue_setup, 1030 .rx_queue_release = mlx5_rx_queue_release, 1031 .tx_queue_release = mlx5_tx_queue_release, 1032 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 1033 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 1034 .mac_addr_remove = mlx5_mac_addr_remove, 1035 .mac_addr_add = mlx5_mac_addr_add, 1036 .mac_addr_set = mlx5_mac_addr_set, 1037 .set_mc_addr_list = mlx5_set_mc_addr_list, 1038 .mtu_set = mlx5_dev_set_mtu, 1039 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 1040 .vlan_offload_set = mlx5_vlan_offload_set, 1041 .filter_ctrl = mlx5_dev_filter_ctrl, 1042 .rx_descriptor_status = mlx5_rx_descriptor_status, 1043 .tx_descriptor_status = mlx5_tx_descriptor_status, 1044 .rx_queue_intr_enable = mlx5_rx_intr_enable, 1045 .rx_queue_intr_disable = mlx5_rx_intr_disable, 1046 .is_removed = mlx5_is_removed, 1047 }; 1048 1049 /** 1050 * Verify and store value for device argument. 1051 * 1052 * @param[in] key 1053 * Key argument to verify. 1054 * @param[in] val 1055 * Value associated with key. 1056 * @param opaque 1057 * User data. 1058 * 1059 * @return 1060 * 0 on success, a negative errno value otherwise and rte_errno is set. 1061 */ 1062 static int 1063 mlx5_args_check(const char *key, const char *val, void *opaque) 1064 { 1065 struct mlx5_dev_config *config = opaque; 1066 unsigned long tmp; 1067 1068 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 1069 if (!strcmp(MLX5_REPRESENTOR, key)) 1070 return 0; 1071 errno = 0; 1072 tmp = strtoul(val, NULL, 0); 1073 if (errno) { 1074 rte_errno = errno; 1075 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 1076 return -rte_errno; 1077 } 1078 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 1079 config->cqe_comp = !!tmp; 1080 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) { 1081 config->cqe_pad = !!tmp; 1082 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 1083 config->hw_padding = !!tmp; 1084 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 1085 config->mprq.enabled = !!tmp; 1086 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 1087 config->mprq.stride_num_n = tmp; 1088 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 1089 config->mprq.max_memcpy_len = tmp; 1090 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 1091 config->mprq.min_rxqs_num = tmp; 1092 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 1093 DRV_LOG(WARNING, "%s: deprecated parameter," 1094 " converted to txq_inline_max", key); 1095 config->txq_inline_max = tmp; 1096 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { 1097 config->txq_inline_max = tmp; 1098 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { 1099 config->txq_inline_min = tmp; 1100 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { 1101 config->txq_inline_mpw = tmp; 1102 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 1103 config->txqs_inline = tmp; 1104 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 1105 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1106 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 1107 config->mps = !!tmp; 1108 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 1109 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1110 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 1111 DRV_LOG(WARNING, "%s: deprecated parameter," 1112 " converted to txq_inline_mpw", key); 1113 config->txq_inline_mpw = tmp; 1114 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 1115 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1116 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 1117 config->rx_vec_en = !!tmp; 1118 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 1119 config->l3_vxlan_en = !!tmp; 1120 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 1121 config->vf_nl_en = !!tmp; 1122 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 1123 config->dv_esw_en = !!tmp; 1124 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 1125 config->dv_flow_en = !!tmp; 1126 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) { 1127 config->mr_ext_memseg_en = !!tmp; 1128 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 1129 config->max_dump_files_num = tmp; 1130 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { 1131 config->lro.timeout = tmp; 1132 } else { 1133 DRV_LOG(WARNING, "%s: unknown parameter", key); 1134 rte_errno = EINVAL; 1135 return -rte_errno; 1136 } 1137 return 0; 1138 } 1139 1140 /** 1141 * Parse device parameters. 1142 * 1143 * @param config 1144 * Pointer to device configuration structure. 1145 * @param devargs 1146 * Device arguments structure. 1147 * 1148 * @return 1149 * 0 on success, a negative errno value otherwise and rte_errno is set. 1150 */ 1151 static int 1152 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 1153 { 1154 const char **params = (const char *[]){ 1155 MLX5_RXQ_CQE_COMP_EN, 1156 MLX5_RXQ_CQE_PAD_EN, 1157 MLX5_RXQ_PKT_PAD_EN, 1158 MLX5_RX_MPRQ_EN, 1159 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 1160 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 1161 MLX5_RXQS_MIN_MPRQ, 1162 MLX5_TXQ_INLINE, 1163 MLX5_TXQ_INLINE_MIN, 1164 MLX5_TXQ_INLINE_MAX, 1165 MLX5_TXQ_INLINE_MPW, 1166 MLX5_TXQS_MIN_INLINE, 1167 MLX5_TXQS_MAX_VEC, 1168 MLX5_TXQ_MPW_EN, 1169 MLX5_TXQ_MPW_HDR_DSEG_EN, 1170 MLX5_TXQ_MAX_INLINE_LEN, 1171 MLX5_TX_VEC_EN, 1172 MLX5_RX_VEC_EN, 1173 MLX5_L3_VXLAN_EN, 1174 MLX5_VF_NL_EN, 1175 MLX5_DV_ESW_EN, 1176 MLX5_DV_FLOW_EN, 1177 MLX5_MR_EXT_MEMSEG_EN, 1178 MLX5_REPRESENTOR, 1179 MLX5_MAX_DUMP_FILES_NUM, 1180 MLX5_LRO_TIMEOUT_USEC, 1181 NULL, 1182 }; 1183 struct rte_kvargs *kvlist; 1184 int ret = 0; 1185 int i; 1186 1187 if (devargs == NULL) 1188 return 0; 1189 /* Following UGLY cast is done to pass checkpatch. */ 1190 kvlist = rte_kvargs_parse(devargs->args, params); 1191 if (kvlist == NULL) { 1192 rte_errno = EINVAL; 1193 return -rte_errno; 1194 } 1195 /* Process parameters. */ 1196 for (i = 0; (params[i] != NULL); ++i) { 1197 if (rte_kvargs_count(kvlist, params[i])) { 1198 ret = rte_kvargs_process(kvlist, params[i], 1199 mlx5_args_check, config); 1200 if (ret) { 1201 rte_errno = EINVAL; 1202 rte_kvargs_free(kvlist); 1203 return -rte_errno; 1204 } 1205 } 1206 } 1207 rte_kvargs_free(kvlist); 1208 return 0; 1209 } 1210 1211 static struct rte_pci_driver mlx5_driver; 1212 1213 /** 1214 * PMD global initialization. 1215 * 1216 * Independent from individual device, this function initializes global 1217 * per-PMD data structures distinguishing primary and secondary processes. 1218 * Hence, each initialization is called once per a process. 1219 * 1220 * @return 1221 * 0 on success, a negative errno value otherwise and rte_errno is set. 1222 */ 1223 static int 1224 mlx5_init_once(void) 1225 { 1226 struct mlx5_shared_data *sd; 1227 struct mlx5_local_data *ld = &mlx5_local_data; 1228 int ret = 0; 1229 1230 if (mlx5_init_shared_data()) 1231 return -rte_errno; 1232 sd = mlx5_shared_data; 1233 assert(sd); 1234 rte_spinlock_lock(&sd->lock); 1235 switch (rte_eal_process_type()) { 1236 case RTE_PROC_PRIMARY: 1237 if (sd->init_done) 1238 break; 1239 LIST_INIT(&sd->mem_event_cb_list); 1240 rte_rwlock_init(&sd->mem_event_rwlock); 1241 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 1242 mlx5_mr_mem_event_cb, NULL); 1243 ret = mlx5_mp_init_primary(); 1244 if (ret) 1245 goto out; 1246 sd->init_done = true; 1247 break; 1248 case RTE_PROC_SECONDARY: 1249 if (ld->init_done) 1250 break; 1251 ret = mlx5_mp_init_secondary(); 1252 if (ret) 1253 goto out; 1254 ++sd->secondary_cnt; 1255 ld->init_done = true; 1256 break; 1257 default: 1258 break; 1259 } 1260 out: 1261 rte_spinlock_unlock(&sd->lock); 1262 return ret; 1263 } 1264 1265 /** 1266 * Configures the minimal amount of data to inline into WQE 1267 * while sending packets. 1268 * 1269 * - the txq_inline_min has the maximal priority, if this 1270 * key is specified in devargs 1271 * - if DevX is enabled the inline mode is queried from the 1272 * device (HCA attributes and NIC vport context if needed). 1273 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4LX 1274 * and none (0 bytes) for other NICs 1275 * 1276 * @param spawn 1277 * Verbs device parameters (name, port, switch_info) to spawn. 1278 * @param config 1279 * Device configuration parameters. 1280 */ 1281 static void 1282 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1283 struct mlx5_dev_config *config) 1284 { 1285 if (config->txq_inline_min != MLX5_ARG_UNSET) { 1286 /* Application defines size of inlined data explicitly. */ 1287 switch (spawn->pci_dev->id.device_id) { 1288 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 1289 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1290 if (config->txq_inline_min < 1291 (int)MLX5_INLINE_HSIZE_L2) { 1292 DRV_LOG(DEBUG, 1293 "txq_inline_mix aligned to minimal" 1294 " ConnectX-4 required value %d", 1295 (int)MLX5_INLINE_HSIZE_L2); 1296 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1297 } 1298 break; 1299 } 1300 goto exit; 1301 } 1302 if (config->hca_attr.eth_net_offloads) { 1303 /* We have DevX enabled, inline mode queried successfully. */ 1304 switch (config->hca_attr.wqe_inline_mode) { 1305 case MLX5_CAP_INLINE_MODE_L2: 1306 /* outer L2 header must be inlined. */ 1307 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1308 goto exit; 1309 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: 1310 /* No inline data are required by NIC. */ 1311 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1312 config->hw_vlan_insert = 1313 config->hca_attr.wqe_vlan_insert; 1314 DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); 1315 goto exit; 1316 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: 1317 /* inline mode is defined by NIC vport context. */ 1318 if (!config->hca_attr.eth_virt) 1319 break; 1320 switch (config->hca_attr.vport_inline_mode) { 1321 case MLX5_INLINE_MODE_NONE: 1322 config->txq_inline_min = 1323 MLX5_INLINE_HSIZE_NONE; 1324 goto exit; 1325 case MLX5_INLINE_MODE_L2: 1326 config->txq_inline_min = 1327 MLX5_INLINE_HSIZE_L2; 1328 goto exit; 1329 case MLX5_INLINE_MODE_IP: 1330 config->txq_inline_min = 1331 MLX5_INLINE_HSIZE_L3; 1332 goto exit; 1333 case MLX5_INLINE_MODE_TCP_UDP: 1334 config->txq_inline_min = 1335 MLX5_INLINE_HSIZE_L4; 1336 goto exit; 1337 case MLX5_INLINE_MODE_INNER_L2: 1338 config->txq_inline_min = 1339 MLX5_INLINE_HSIZE_INNER_L2; 1340 goto exit; 1341 case MLX5_INLINE_MODE_INNER_IP: 1342 config->txq_inline_min = 1343 MLX5_INLINE_HSIZE_INNER_L3; 1344 goto exit; 1345 case MLX5_INLINE_MODE_INNER_TCP_UDP: 1346 config->txq_inline_min = 1347 MLX5_INLINE_HSIZE_INNER_L4; 1348 goto exit; 1349 } 1350 } 1351 } 1352 /* 1353 * We get here if we are unable to deduce 1354 * inline data size with DevX. Try PCI ID 1355 * to determine old NICs. 1356 */ 1357 switch (spawn->pci_dev->id.device_id) { 1358 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 1359 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1360 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 1361 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1362 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1363 config->hw_vlan_insert = 0; 1364 break; 1365 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 1366 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1367 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 1368 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1369 /* 1370 * These NICs support VLAN insertion from WQE and 1371 * report the wqe_vlan_insert flag. But there is the bug 1372 * and PFC control may be broken, so disable feature. 1373 */ 1374 config->hw_vlan_insert = 0; 1375 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1376 break; 1377 default: 1378 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1379 break; 1380 } 1381 exit: 1382 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); 1383 } 1384 1385 /** 1386 * Allocate page of door-bells and register it using DevX API. 1387 * 1388 * @param [in] dev 1389 * Pointer to Ethernet device. 1390 * 1391 * @return 1392 * Pointer to new page on success, NULL otherwise. 1393 */ 1394 static struct mlx5_devx_dbr_page * 1395 mlx5_alloc_dbr_page(struct rte_eth_dev *dev) 1396 { 1397 struct mlx5_priv *priv = dev->data->dev_private; 1398 struct mlx5_devx_dbr_page *page; 1399 1400 /* Allocate space for door-bell page and management data. */ 1401 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page), 1402 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 1403 if (!page) { 1404 DRV_LOG(ERR, "port %u cannot allocate dbr page", 1405 dev->data->port_id); 1406 return NULL; 1407 } 1408 /* Register allocated memory. */ 1409 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs, 1410 MLX5_DBR_PAGE_SIZE, 0); 1411 if (!page->umem) { 1412 DRV_LOG(ERR, "port %u cannot umem reg dbr page", 1413 dev->data->port_id); 1414 rte_free(page); 1415 return NULL; 1416 } 1417 return page; 1418 } 1419 1420 /** 1421 * Find the next available door-bell, allocate new page if needed. 1422 * 1423 * @param [in] dev 1424 * Pointer to Ethernet device. 1425 * @param [out] dbr_page 1426 * Door-bell page containing the page data. 1427 * 1428 * @return 1429 * Door-bell address offset on success, a negative error value otherwise. 1430 */ 1431 int64_t 1432 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page) 1433 { 1434 struct mlx5_priv *priv = dev->data->dev_private; 1435 struct mlx5_devx_dbr_page *page = NULL; 1436 uint32_t i, j; 1437 1438 LIST_FOREACH(page, &priv->dbrpgs, next) 1439 if (page->dbr_count < MLX5_DBR_PER_PAGE) 1440 break; 1441 if (!page) { /* No page with free door-bell exists. */ 1442 page = mlx5_alloc_dbr_page(dev); 1443 if (!page) /* Failed to allocate new page. */ 1444 return (-1); 1445 LIST_INSERT_HEAD(&priv->dbrpgs, page, next); 1446 } 1447 /* Loop to find bitmap part with clear bit. */ 1448 for (i = 0; 1449 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX; 1450 i++) 1451 ; /* Empty. */ 1452 /* Find the first clear bit. */ 1453 j = rte_bsf64(~page->dbr_bitmap[i]); 1454 assert(i < (MLX5_DBR_PER_PAGE / 64)); 1455 page->dbr_bitmap[i] |= (1 << j); 1456 page->dbr_count++; 1457 *dbr_page = page; 1458 return (((i * 64) + j) * sizeof(uint64_t)); 1459 } 1460 1461 /** 1462 * Release a door-bell record. 1463 * 1464 * @param [in] dev 1465 * Pointer to Ethernet device. 1466 * @param [in] umem_id 1467 * UMEM ID of page containing the door-bell record to release. 1468 * @param [in] offset 1469 * Offset of door-bell record in page. 1470 * 1471 * @return 1472 * 0 on success, a negative error value otherwise. 1473 */ 1474 int32_t 1475 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset) 1476 { 1477 struct mlx5_priv *priv = dev->data->dev_private; 1478 struct mlx5_devx_dbr_page *page = NULL; 1479 int ret = 0; 1480 1481 LIST_FOREACH(page, &priv->dbrpgs, next) 1482 /* Find the page this address belongs to. */ 1483 if (page->umem->umem_id == umem_id) 1484 break; 1485 if (!page) 1486 return -EINVAL; 1487 page->dbr_count--; 1488 if (!page->dbr_count) { 1489 /* Page not used, free it and remove from list. */ 1490 LIST_REMOVE(page, next); 1491 if (page->umem) 1492 ret = -mlx5_glue->devx_umem_dereg(page->umem); 1493 rte_free(page); 1494 } else { 1495 /* Mark in bitmap that this door-bell is not in use. */ 1496 offset /= MLX5_DBR_SIZE; 1497 int i = offset / 64; 1498 int j = offset % 64; 1499 1500 page->dbr_bitmap[i] &= ~(1 << j); 1501 } 1502 return ret; 1503 } 1504 1505 /** 1506 * Spawn an Ethernet device from Verbs information. 1507 * 1508 * @param dpdk_dev 1509 * Backing DPDK device. 1510 * @param spawn 1511 * Verbs device parameters (name, port, switch_info) to spawn. 1512 * @param config 1513 * Device configuration parameters. 1514 * 1515 * @return 1516 * A valid Ethernet device object on success, NULL otherwise and rte_errno 1517 * is set. The following errors are defined: 1518 * 1519 * EBUSY: device is not supposed to be spawned. 1520 * EEXIST: device is already spawned 1521 */ 1522 static struct rte_eth_dev * 1523 mlx5_dev_spawn(struct rte_device *dpdk_dev, 1524 struct mlx5_dev_spawn_data *spawn, 1525 struct mlx5_dev_config config) 1526 { 1527 const struct mlx5_switch_info *switch_info = &spawn->info; 1528 struct mlx5_ibv_shared *sh = NULL; 1529 struct ibv_port_attr port_attr; 1530 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 1531 struct rte_eth_dev *eth_dev = NULL; 1532 struct mlx5_priv *priv = NULL; 1533 int err = 0; 1534 unsigned int hw_padding = 0; 1535 unsigned int mps; 1536 unsigned int cqe_comp; 1537 unsigned int cqe_pad = 0; 1538 unsigned int tunnel_en = 0; 1539 unsigned int mpls_en = 0; 1540 unsigned int swp = 0; 1541 unsigned int mprq = 0; 1542 unsigned int mprq_min_stride_size_n = 0; 1543 unsigned int mprq_max_stride_size_n = 0; 1544 unsigned int mprq_min_stride_num_n = 0; 1545 unsigned int mprq_max_stride_num_n = 0; 1546 struct rte_ether_addr mac; 1547 char name[RTE_ETH_NAME_MAX_LEN]; 1548 int own_domain_id = 0; 1549 uint16_t port_id; 1550 unsigned int i; 1551 1552 /* Determine if this port representor is supposed to be spawned. */ 1553 if (switch_info->representor && dpdk_dev->devargs) { 1554 struct rte_eth_devargs eth_da; 1555 1556 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 1557 if (err) { 1558 rte_errno = -err; 1559 DRV_LOG(ERR, "failed to process device arguments: %s", 1560 strerror(rte_errno)); 1561 return NULL; 1562 } 1563 for (i = 0; i < eth_da.nb_representor_ports; ++i) 1564 if (eth_da.representor_ports[i] == 1565 (uint16_t)switch_info->port_name) 1566 break; 1567 if (i == eth_da.nb_representor_ports) { 1568 rte_errno = EBUSY; 1569 return NULL; 1570 } 1571 } 1572 /* Build device name. */ 1573 if (!switch_info->representor) 1574 strlcpy(name, dpdk_dev->name, sizeof(name)); 1575 else 1576 snprintf(name, sizeof(name), "%s_representor_%u", 1577 dpdk_dev->name, switch_info->port_name); 1578 /* check if the device is already spawned */ 1579 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1580 rte_errno = EEXIST; 1581 return NULL; 1582 } 1583 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1584 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1585 eth_dev = rte_eth_dev_attach_secondary(name); 1586 if (eth_dev == NULL) { 1587 DRV_LOG(ERR, "can not attach rte ethdev"); 1588 rte_errno = ENOMEM; 1589 return NULL; 1590 } 1591 eth_dev->device = dpdk_dev; 1592 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1593 err = mlx5_proc_priv_init(eth_dev); 1594 if (err) 1595 return NULL; 1596 /* Receive command fd from primary process */ 1597 err = mlx5_mp_req_verbs_cmd_fd(eth_dev); 1598 if (err < 0) 1599 return NULL; 1600 /* Remap UAR for Tx queues. */ 1601 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1602 if (err) 1603 return NULL; 1604 /* 1605 * Ethdev pointer is still required as input since 1606 * the primary device is not accessible from the 1607 * secondary process. 1608 */ 1609 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1610 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1611 return eth_dev; 1612 } 1613 sh = mlx5_alloc_shared_ibctx(spawn); 1614 if (!sh) 1615 return NULL; 1616 config.devx = sh->devx; 1617 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 1618 config.dest_tir = 1; 1619 #endif 1620 #ifdef HAVE_IBV_MLX5_MOD_SWP 1621 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 1622 #endif 1623 /* 1624 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1625 * as all ConnectX-5 devices. 1626 */ 1627 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1628 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1629 #endif 1630 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1631 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1632 #endif 1633 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 1634 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1635 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1636 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1637 mps = MLX5_MPW_ENHANCED; 1638 } else { 1639 DRV_LOG(DEBUG, "MPW is supported"); 1640 mps = MLX5_MPW; 1641 } 1642 } else { 1643 DRV_LOG(DEBUG, "MPW isn't supported"); 1644 mps = MLX5_MPW_DISABLED; 1645 } 1646 #ifdef HAVE_IBV_MLX5_MOD_SWP 1647 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1648 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1649 DRV_LOG(DEBUG, "SWP support: %u", swp); 1650 #endif 1651 config.swp = !!swp; 1652 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1653 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1654 struct mlx5dv_striding_rq_caps mprq_caps = 1655 dv_attr.striding_rq_caps; 1656 1657 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1658 mprq_caps.min_single_stride_log_num_of_bytes); 1659 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1660 mprq_caps.max_single_stride_log_num_of_bytes); 1661 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1662 mprq_caps.min_single_wqe_log_num_of_strides); 1663 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1664 mprq_caps.max_single_wqe_log_num_of_strides); 1665 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1666 mprq_caps.supported_qpts); 1667 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1668 mprq = 1; 1669 mprq_min_stride_size_n = 1670 mprq_caps.min_single_stride_log_num_of_bytes; 1671 mprq_max_stride_size_n = 1672 mprq_caps.max_single_stride_log_num_of_bytes; 1673 mprq_min_stride_num_n = 1674 mprq_caps.min_single_wqe_log_num_of_strides; 1675 mprq_max_stride_num_n = 1676 mprq_caps.max_single_wqe_log_num_of_strides; 1677 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1678 mprq_min_stride_num_n); 1679 } 1680 #endif 1681 if (RTE_CACHE_LINE_SIZE == 128 && 1682 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 1683 cqe_comp = 0; 1684 else 1685 cqe_comp = 1; 1686 config.cqe_comp = cqe_comp; 1687 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 1688 /* Whether device supports 128B Rx CQE padding. */ 1689 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 1690 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 1691 #endif 1692 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1693 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1694 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1695 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1696 (dv_attr.tunnel_offloads_caps & 1697 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 1698 } 1699 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1700 tunnel_en ? "" : "not "); 1701 #else 1702 DRV_LOG(WARNING, 1703 "tunnel offloading disabled due to old OFED/rdma-core version"); 1704 #endif 1705 config.tunnel_en = tunnel_en; 1706 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1707 mpls_en = ((dv_attr.tunnel_offloads_caps & 1708 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1709 (dv_attr.tunnel_offloads_caps & 1710 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1711 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1712 mpls_en ? "" : "not "); 1713 #else 1714 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1715 " old OFED/rdma-core version or firmware configuration"); 1716 #endif 1717 config.mpls_en = mpls_en; 1718 /* Check port status. */ 1719 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr); 1720 if (err) { 1721 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1722 goto error; 1723 } 1724 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1725 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1726 err = EINVAL; 1727 goto error; 1728 } 1729 if (port_attr.state != IBV_PORT_ACTIVE) 1730 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1731 mlx5_glue->port_state_str(port_attr.state), 1732 port_attr.state); 1733 /* Allocate private eth device data. */ 1734 priv = rte_zmalloc("ethdev private structure", 1735 sizeof(*priv), 1736 RTE_CACHE_LINE_SIZE); 1737 if (priv == NULL) { 1738 DRV_LOG(ERR, "priv allocation failure"); 1739 err = ENOMEM; 1740 goto error; 1741 } 1742 priv->sh = sh; 1743 priv->ibv_port = spawn->ibv_port; 1744 priv->mtu = RTE_ETHER_MTU; 1745 #ifndef RTE_ARCH_64 1746 /* Initialize UAR access locks for 32bit implementations. */ 1747 rte_spinlock_init(&priv->uar_lock_cq); 1748 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 1749 rte_spinlock_init(&priv->uar_lock[i]); 1750 #endif 1751 /* Some internal functions rely on Netlink sockets, open them now. */ 1752 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1753 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1754 priv->nl_sn = 0; 1755 priv->representor = !!switch_info->representor; 1756 priv->master = !!switch_info->master; 1757 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1758 /* 1759 * Currently we support single E-Switch per PF configurations 1760 * only and vport_id field contains the vport index for 1761 * associated VF, which is deduced from representor port name. 1762 * For example, let's have the IB device port 10, it has 1763 * attached network device eth0, which has port name attribute 1764 * pf0vf2, we can deduce the VF number as 2, and set vport index 1765 * as 3 (2+1). This assigning schema should be changed if the 1766 * multiple E-Switch instances per PF configurations or/and PCI 1767 * subfunctions are added. 1768 */ 1769 priv->vport_id = switch_info->representor ? 1770 switch_info->port_name + 1 : -1; 1771 /* representor_id field keeps the unmodified port/VF index. */ 1772 priv->representor_id = switch_info->representor ? 1773 switch_info->port_name : -1; 1774 /* 1775 * Look for sibling devices in order to reuse their switch domain 1776 * if any, otherwise allocate one. 1777 */ 1778 RTE_ETH_FOREACH_DEV_OF(port_id, dpdk_dev) { 1779 const struct mlx5_priv *opriv = 1780 rte_eth_devices[port_id].data->dev_private; 1781 1782 if (!opriv || 1783 opriv->domain_id == 1784 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1785 continue; 1786 priv->domain_id = opriv->domain_id; 1787 break; 1788 } 1789 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1790 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1791 if (err) { 1792 err = rte_errno; 1793 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1794 strerror(rte_errno)); 1795 goto error; 1796 } 1797 own_domain_id = 1; 1798 } 1799 err = mlx5_args(&config, dpdk_dev->devargs); 1800 if (err) { 1801 err = rte_errno; 1802 DRV_LOG(ERR, "failed to process device arguments: %s", 1803 strerror(rte_errno)); 1804 goto error; 1805 } 1806 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1807 IBV_DEVICE_RAW_IP_CSUM); 1808 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1809 (config.hw_csum ? "" : "not ")); 1810 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1811 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1812 DRV_LOG(DEBUG, "counters are not supported"); 1813 #endif 1814 #ifndef HAVE_IBV_FLOW_DV_SUPPORT 1815 if (config.dv_flow_en) { 1816 DRV_LOG(WARNING, "DV flow is not supported"); 1817 config.dv_flow_en = 0; 1818 } 1819 #endif 1820 config.ind_table_max_size = 1821 sh->device_attr.rss_caps.max_rwq_indirection_table_size; 1822 /* 1823 * Remove this check once DPDK supports larger/variable 1824 * indirection tables. 1825 */ 1826 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1827 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1828 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1829 config.ind_table_max_size); 1830 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1831 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1832 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1833 (config.hw_vlan_strip ? "" : "not ")); 1834 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1835 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1836 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1837 (config.hw_fcs_strip ? "" : "not ")); 1838 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1839 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1840 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1841 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1842 IBV_DEVICE_PCI_WRITE_END_PADDING); 1843 #endif 1844 if (config.hw_padding && !hw_padding) { 1845 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1846 config.hw_padding = 0; 1847 } else if (config.hw_padding) { 1848 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1849 } 1850 config.tso = (sh->device_attr.tso_caps.max_tso > 0 && 1851 (sh->device_attr.tso_caps.supported_qpts & 1852 (1 << IBV_QPT_RAW_PACKET))); 1853 if (config.tso) 1854 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso; 1855 /* 1856 * MPW is disabled by default, while the Enhanced MPW is enabled 1857 * by default. 1858 */ 1859 if (config.mps == MLX5_ARG_UNSET) 1860 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1861 MLX5_MPW_DISABLED; 1862 else 1863 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1864 DRV_LOG(INFO, "%sMPS is %s", 1865 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1866 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1867 if (config.cqe_comp && !cqe_comp) { 1868 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1869 config.cqe_comp = 0; 1870 } 1871 if (config.cqe_pad && !cqe_pad) { 1872 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1873 config.cqe_pad = 0; 1874 } else if (config.cqe_pad) { 1875 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1876 } 1877 if (config.devx) { 1878 priv->counter_fallback = 0; 1879 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr); 1880 if (err) { 1881 err = -err; 1882 goto error; 1883 } 1884 if (!config.hca_attr.flow_counters_dump) 1885 priv->counter_fallback = 1; 1886 #ifndef HAVE_IBV_DEVX_ASYNC 1887 priv->counter_fallback = 1; 1888 #endif 1889 if (priv->counter_fallback) 1890 DRV_LOG(INFO, "Use fall-back DV counter management\n"); 1891 /* Check for LRO support. */ 1892 if (config.dest_tir && config.hca_attr.lro_cap) { 1893 /* TBD check tunnel lro caps. */ 1894 config.lro.supported = config.hca_attr.lro_cap; 1895 DRV_LOG(DEBUG, "Device supports LRO"); 1896 /* 1897 * If LRO timeout is not configured by application, 1898 * use the minimal supported value. 1899 */ 1900 if (!config.lro.timeout) 1901 config.lro.timeout = 1902 config.hca_attr.lro_timer_supported_periods[0]; 1903 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1904 config.lro.timeout); 1905 } 1906 } 1907 if (config.mprq.enabled && mprq) { 1908 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1909 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1910 config.mprq.stride_num_n = 1911 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1912 mprq_min_stride_num_n); 1913 DRV_LOG(WARNING, 1914 "the number of strides" 1915 " for Multi-Packet RQ is out of range," 1916 " setting default value (%u)", 1917 1 << config.mprq.stride_num_n); 1918 } 1919 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1920 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1921 } else if (config.mprq.enabled && !mprq) { 1922 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1923 config.mprq.enabled = 0; 1924 } 1925 if (config.max_dump_files_num == 0) 1926 config.max_dump_files_num = 128; 1927 eth_dev = rte_eth_dev_allocate(name); 1928 if (eth_dev == NULL) { 1929 DRV_LOG(ERR, "can not allocate rte ethdev"); 1930 err = ENOMEM; 1931 goto error; 1932 } 1933 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 1934 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1935 if (priv->representor) { 1936 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1937 eth_dev->data->representor_id = priv->representor_id; 1938 } 1939 /* 1940 * Store associated network device interface index. This index 1941 * is permanent throughout the lifetime of device. So, we may store 1942 * the ifindex here and use the cached value further. 1943 */ 1944 assert(spawn->ifindex); 1945 priv->if_index = spawn->ifindex; 1946 eth_dev->data->dev_private = priv; 1947 priv->dev_data = eth_dev->data; 1948 eth_dev->data->mac_addrs = priv->mac; 1949 eth_dev->device = dpdk_dev; 1950 /* Configure the first MAC address by default. */ 1951 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1952 DRV_LOG(ERR, 1953 "port %u cannot get MAC address, is mlx5_en" 1954 " loaded? (errno: %s)", 1955 eth_dev->data->port_id, strerror(rte_errno)); 1956 err = ENODEV; 1957 goto error; 1958 } 1959 DRV_LOG(INFO, 1960 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1961 eth_dev->data->port_id, 1962 mac.addr_bytes[0], mac.addr_bytes[1], 1963 mac.addr_bytes[2], mac.addr_bytes[3], 1964 mac.addr_bytes[4], mac.addr_bytes[5]); 1965 #ifndef NDEBUG 1966 { 1967 char ifname[IF_NAMESIZE]; 1968 1969 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1970 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1971 eth_dev->data->port_id, ifname); 1972 else 1973 DRV_LOG(DEBUG, "port %u ifname is unknown", 1974 eth_dev->data->port_id); 1975 } 1976 #endif 1977 /* Get actual MTU if possible. */ 1978 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1979 if (err) { 1980 err = rte_errno; 1981 goto error; 1982 } 1983 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1984 priv->mtu); 1985 /* Initialize burst functions to prevent crashes before link-up. */ 1986 eth_dev->rx_pkt_burst = removed_rx_burst; 1987 eth_dev->tx_pkt_burst = removed_tx_burst; 1988 eth_dev->dev_ops = &mlx5_dev_ops; 1989 /* Register MAC address. */ 1990 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1991 if (config.vf && config.vf_nl_en) 1992 mlx5_nl_mac_addr_sync(eth_dev); 1993 TAILQ_INIT(&priv->flows); 1994 TAILQ_INIT(&priv->ctrl_flows); 1995 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1996 struct mlx5dv_ctx_allocators alctr = { 1997 .alloc = &mlx5_alloc_verbs_buf, 1998 .free = &mlx5_free_verbs_buf, 1999 .data = priv, 2000 }; 2001 mlx5_glue->dv_set_context_attr(sh->ctx, 2002 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2003 (void *)((uintptr_t)&alctr)); 2004 /* Bring Ethernet device up. */ 2005 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 2006 eth_dev->data->port_id); 2007 mlx5_set_link_up(eth_dev); 2008 /* 2009 * Even though the interrupt handler is not installed yet, 2010 * interrupts will still trigger on the async_fd from 2011 * Verbs context returned by ibv_open_device(). 2012 */ 2013 mlx5_link_update(eth_dev, 0); 2014 #ifdef HAVE_MLX5DV_DR_ESWITCH 2015 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en && 2016 (switch_info->representor || switch_info->master))) 2017 config.dv_esw_en = 0; 2018 #else 2019 config.dv_esw_en = 0; 2020 #endif 2021 /* Detect minimal data bytes to inline. */ 2022 mlx5_set_min_inline(spawn, &config); 2023 /* Store device configuration on private structure. */ 2024 priv->config = config; 2025 /* Create context for virtual machine VLAN workaround. */ 2026 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 2027 if (config.dv_flow_en) { 2028 err = mlx5_alloc_shared_dr(priv); 2029 if (err) 2030 goto error; 2031 } 2032 /* Supported Verbs flow priority number detection. */ 2033 err = mlx5_flow_discover_priorities(eth_dev); 2034 if (err < 0) { 2035 err = -err; 2036 goto error; 2037 } 2038 priv->config.flow_prio = err; 2039 return eth_dev; 2040 error: 2041 if (priv) { 2042 if (priv->sh) 2043 mlx5_free_shared_dr(priv); 2044 if (priv->nl_socket_route >= 0) 2045 close(priv->nl_socket_route); 2046 if (priv->nl_socket_rdma >= 0) 2047 close(priv->nl_socket_rdma); 2048 if (priv->vmwa_context) 2049 mlx5_vlan_vmwa_exit(priv->vmwa_context); 2050 if (own_domain_id) 2051 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 2052 rte_free(priv); 2053 if (eth_dev != NULL) 2054 eth_dev->data->dev_private = NULL; 2055 } 2056 if (eth_dev != NULL) { 2057 /* mac_addrs must not be freed alone because part of dev_private */ 2058 eth_dev->data->mac_addrs = NULL; 2059 rte_eth_dev_release_port(eth_dev); 2060 } 2061 if (sh) 2062 mlx5_free_shared_ibctx(sh); 2063 assert(err > 0); 2064 rte_errno = err; 2065 return NULL; 2066 } 2067 2068 /** 2069 * Comparison callback to sort device data. 2070 * 2071 * This is meant to be used with qsort(). 2072 * 2073 * @param a[in] 2074 * Pointer to pointer to first data object. 2075 * @param b[in] 2076 * Pointer to pointer to second data object. 2077 * 2078 * @return 2079 * 0 if both objects are equal, less than 0 if the first argument is less 2080 * than the second, greater than 0 otherwise. 2081 */ 2082 static int 2083 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 2084 { 2085 const struct mlx5_switch_info *si_a = 2086 &((const struct mlx5_dev_spawn_data *)a)->info; 2087 const struct mlx5_switch_info *si_b = 2088 &((const struct mlx5_dev_spawn_data *)b)->info; 2089 int ret; 2090 2091 /* Master device first. */ 2092 ret = si_b->master - si_a->master; 2093 if (ret) 2094 return ret; 2095 /* Then representor devices. */ 2096 ret = si_b->representor - si_a->representor; 2097 if (ret) 2098 return ret; 2099 /* Unidentified devices come last in no specific order. */ 2100 if (!si_a->representor) 2101 return 0; 2102 /* Order representors by name. */ 2103 return si_a->port_name - si_b->port_name; 2104 } 2105 2106 /** 2107 * DPDK callback to register a PCI device. 2108 * 2109 * This function spawns Ethernet devices out of a given PCI device. 2110 * 2111 * @param[in] pci_drv 2112 * PCI driver structure (mlx5_driver). 2113 * @param[in] pci_dev 2114 * PCI device information. 2115 * 2116 * @return 2117 * 0 on success, a negative errno value otherwise and rte_errno is set. 2118 */ 2119 static int 2120 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2121 struct rte_pci_device *pci_dev) 2122 { 2123 struct ibv_device **ibv_list; 2124 /* 2125 * Number of found IB Devices matching with requested PCI BDF. 2126 * nd != 1 means there are multiple IB devices over the same 2127 * PCI device and we have representors and master. 2128 */ 2129 unsigned int nd = 0; 2130 /* 2131 * Number of found IB device Ports. nd = 1 and np = 1..n means 2132 * we have the single multiport IB device, and there may be 2133 * representors attached to some of found ports. 2134 */ 2135 unsigned int np = 0; 2136 /* 2137 * Number of DPDK ethernet devices to Spawn - either over 2138 * multiple IB devices or multiple ports of single IB device. 2139 * Actually this is the number of iterations to spawn. 2140 */ 2141 unsigned int ns = 0; 2142 struct mlx5_dev_config dev_config; 2143 int ret; 2144 2145 ret = mlx5_init_once(); 2146 if (ret) { 2147 DRV_LOG(ERR, "unable to init PMD global data: %s", 2148 strerror(rte_errno)); 2149 return -rte_errno; 2150 } 2151 assert(pci_drv == &mlx5_driver); 2152 errno = 0; 2153 ibv_list = mlx5_glue->get_device_list(&ret); 2154 if (!ibv_list) { 2155 rte_errno = errno ? errno : ENOSYS; 2156 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 2157 return -rte_errno; 2158 } 2159 /* 2160 * First scan the list of all Infiniband devices to find 2161 * matching ones, gathering into the list. 2162 */ 2163 struct ibv_device *ibv_match[ret + 1]; 2164 int nl_route = -1; 2165 int nl_rdma = -1; 2166 unsigned int i; 2167 2168 while (ret-- > 0) { 2169 struct rte_pci_addr pci_addr; 2170 2171 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 2172 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 2173 continue; 2174 if (pci_dev->addr.domain != pci_addr.domain || 2175 pci_dev->addr.bus != pci_addr.bus || 2176 pci_dev->addr.devid != pci_addr.devid || 2177 pci_dev->addr.function != pci_addr.function) 2178 continue; 2179 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2180 ibv_list[ret]->name); 2181 ibv_match[nd++] = ibv_list[ret]; 2182 } 2183 ibv_match[nd] = NULL; 2184 if (!nd) { 2185 /* No device matches, just complain and bail out. */ 2186 mlx5_glue->free_device_list(ibv_list); 2187 DRV_LOG(WARNING, 2188 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2189 " are kernel drivers loaded?", 2190 pci_dev->addr.domain, pci_dev->addr.bus, 2191 pci_dev->addr.devid, pci_dev->addr.function); 2192 rte_errno = ENOENT; 2193 ret = -rte_errno; 2194 return ret; 2195 } 2196 nl_route = mlx5_nl_init(NETLINK_ROUTE); 2197 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2198 if (nd == 1) { 2199 /* 2200 * Found single matching device may have multiple ports. 2201 * Each port may be representor, we have to check the port 2202 * number and check the representors existence. 2203 */ 2204 if (nl_rdma >= 0) 2205 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2206 if (!np) 2207 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2208 " ports number", ibv_match[0]->name); 2209 } 2210 /* 2211 * Now we can determine the maximal 2212 * amount of devices to be spawned. 2213 */ 2214 struct mlx5_dev_spawn_data list[np ? np : nd]; 2215 2216 if (np > 1) { 2217 /* 2218 * Single IB device with multiple ports found, 2219 * it may be E-Switch master device and representors. 2220 * We have to perform identification trough the ports. 2221 */ 2222 assert(nl_rdma >= 0); 2223 assert(ns == 0); 2224 assert(nd == 1); 2225 for (i = 1; i <= np; ++i) { 2226 list[ns].max_port = np; 2227 list[ns].ibv_port = i; 2228 list[ns].ibv_dev = ibv_match[0]; 2229 list[ns].eth_dev = NULL; 2230 list[ns].pci_dev = pci_dev; 2231 list[ns].ifindex = mlx5_nl_ifindex 2232 (nl_rdma, list[ns].ibv_dev->name, i); 2233 if (!list[ns].ifindex) { 2234 /* 2235 * No network interface index found for the 2236 * specified port, it means there is no 2237 * representor on this port. It's OK, 2238 * there can be disabled ports, for example 2239 * if sriov_numvfs < sriov_totalvfs. 2240 */ 2241 continue; 2242 } 2243 ret = -1; 2244 if (nl_route >= 0) 2245 ret = mlx5_nl_switch_info 2246 (nl_route, 2247 list[ns].ifindex, 2248 &list[ns].info); 2249 if (ret || (!list[ns].info.representor && 2250 !list[ns].info.master)) { 2251 /* 2252 * We failed to recognize representors with 2253 * Netlink, let's try to perform the task 2254 * with sysfs. 2255 */ 2256 ret = mlx5_sysfs_switch_info 2257 (list[ns].ifindex, 2258 &list[ns].info); 2259 } 2260 if (!ret && (list[ns].info.representor ^ 2261 list[ns].info.master)) 2262 ns++; 2263 } 2264 if (!ns) { 2265 DRV_LOG(ERR, 2266 "unable to recognize master/representors" 2267 " on the IB device with multiple ports"); 2268 rte_errno = ENOENT; 2269 ret = -rte_errno; 2270 goto exit; 2271 } 2272 } else { 2273 /* 2274 * The existence of several matching entries (nd > 1) means 2275 * port representors have been instantiated. No existing Verbs 2276 * call nor sysfs entries can tell them apart, this can only 2277 * be done through Netlink calls assuming kernel drivers are 2278 * recent enough to support them. 2279 * 2280 * In the event of identification failure through Netlink, 2281 * try again through sysfs, then: 2282 * 2283 * 1. A single IB device matches (nd == 1) with single 2284 * port (np=0/1) and is not a representor, assume 2285 * no switch support. 2286 * 2287 * 2. Otherwise no safe assumptions can be made; 2288 * complain louder and bail out. 2289 */ 2290 np = 1; 2291 for (i = 0; i != nd; ++i) { 2292 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2293 list[ns].max_port = 1; 2294 list[ns].ibv_port = 1; 2295 list[ns].ibv_dev = ibv_match[i]; 2296 list[ns].eth_dev = NULL; 2297 list[ns].pci_dev = pci_dev; 2298 list[ns].ifindex = 0; 2299 if (nl_rdma >= 0) 2300 list[ns].ifindex = mlx5_nl_ifindex 2301 (nl_rdma, list[ns].ibv_dev->name, 1); 2302 if (!list[ns].ifindex) { 2303 char ifname[IF_NAMESIZE]; 2304 2305 /* 2306 * Netlink failed, it may happen with old 2307 * ib_core kernel driver (before 4.16). 2308 * We can assume there is old driver because 2309 * here we are processing single ports IB 2310 * devices. Let's try sysfs to retrieve 2311 * the ifindex. The method works for 2312 * master device only. 2313 */ 2314 if (nd > 1) { 2315 /* 2316 * Multiple devices found, assume 2317 * representors, can not distinguish 2318 * master/representor and retrieve 2319 * ifindex via sysfs. 2320 */ 2321 continue; 2322 } 2323 ret = mlx5_get_master_ifname 2324 (ibv_match[i]->ibdev_path, &ifname); 2325 if (!ret) 2326 list[ns].ifindex = 2327 if_nametoindex(ifname); 2328 if (!list[ns].ifindex) { 2329 /* 2330 * No network interface index found 2331 * for the specified device, it means 2332 * there it is neither representor 2333 * nor master. 2334 */ 2335 continue; 2336 } 2337 } 2338 ret = -1; 2339 if (nl_route >= 0) 2340 ret = mlx5_nl_switch_info 2341 (nl_route, 2342 list[ns].ifindex, 2343 &list[ns].info); 2344 if (ret || (!list[ns].info.representor && 2345 !list[ns].info.master)) { 2346 /* 2347 * We failed to recognize representors with 2348 * Netlink, let's try to perform the task 2349 * with sysfs. 2350 */ 2351 ret = mlx5_sysfs_switch_info 2352 (list[ns].ifindex, 2353 &list[ns].info); 2354 } 2355 if (!ret && (list[ns].info.representor ^ 2356 list[ns].info.master)) { 2357 ns++; 2358 } else if ((nd == 1) && 2359 !list[ns].info.representor && 2360 !list[ns].info.master) { 2361 /* 2362 * Single IB device with 2363 * one physical port and 2364 * attached network device. 2365 * May be SRIOV is not enabled 2366 * or there is no representors. 2367 */ 2368 DRV_LOG(INFO, "no E-Switch support detected"); 2369 ns++; 2370 break; 2371 } 2372 } 2373 if (!ns) { 2374 DRV_LOG(ERR, 2375 "unable to recognize master/representors" 2376 " on the multiple IB devices"); 2377 rte_errno = ENOENT; 2378 ret = -rte_errno; 2379 goto exit; 2380 } 2381 } 2382 assert(ns); 2383 /* 2384 * Sort list to probe devices in natural order for users convenience 2385 * (i.e. master first, then representors from lowest to highest ID). 2386 */ 2387 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2388 /* Default configuration. */ 2389 dev_config = (struct mlx5_dev_config){ 2390 .hw_padding = 0, 2391 .mps = MLX5_ARG_UNSET, 2392 .rx_vec_en = 1, 2393 .txq_inline_max = MLX5_ARG_UNSET, 2394 .txq_inline_min = MLX5_ARG_UNSET, 2395 .txq_inline_mpw = MLX5_ARG_UNSET, 2396 .txqs_inline = MLX5_ARG_UNSET, 2397 .vf_nl_en = 1, 2398 .mr_ext_memseg_en = 1, 2399 .mprq = { 2400 .enabled = 0, /* Disabled by default. */ 2401 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 2402 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 2403 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 2404 }, 2405 .dv_esw_en = 1, 2406 }; 2407 /* Device specific configuration. */ 2408 switch (pci_dev->id.device_id) { 2409 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2410 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2411 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2412 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2413 dev_config.vf = 1; 2414 break; 2415 default: 2416 break; 2417 } 2418 for (i = 0; i != ns; ++i) { 2419 uint32_t restore; 2420 2421 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2422 &list[i], 2423 dev_config); 2424 if (!list[i].eth_dev) { 2425 if (rte_errno != EBUSY && rte_errno != EEXIST) 2426 break; 2427 /* Device is disabled or already spawned. Ignore it. */ 2428 continue; 2429 } 2430 restore = list[i].eth_dev->data->dev_flags; 2431 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2432 /* Restore non-PCI flags cleared by the above call. */ 2433 list[i].eth_dev->data->dev_flags |= restore; 2434 rte_eth_dev_probing_finish(list[i].eth_dev); 2435 } 2436 if (i != ns) { 2437 DRV_LOG(ERR, 2438 "probe of PCI device " PCI_PRI_FMT " aborted after" 2439 " encountering an error: %s", 2440 pci_dev->addr.domain, pci_dev->addr.bus, 2441 pci_dev->addr.devid, pci_dev->addr.function, 2442 strerror(rte_errno)); 2443 ret = -rte_errno; 2444 /* Roll back. */ 2445 while (i--) { 2446 if (!list[i].eth_dev) 2447 continue; 2448 mlx5_dev_close(list[i].eth_dev); 2449 /* mac_addrs must not be freed because in dev_private */ 2450 list[i].eth_dev->data->mac_addrs = NULL; 2451 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2452 } 2453 /* Restore original error. */ 2454 rte_errno = -ret; 2455 } else { 2456 ret = 0; 2457 } 2458 exit: 2459 /* 2460 * Do the routine cleanup: 2461 * - close opened Netlink sockets 2462 * - free the Infiniband device list 2463 */ 2464 if (nl_rdma >= 0) 2465 close(nl_rdma); 2466 if (nl_route >= 0) 2467 close(nl_route); 2468 assert(ibv_list); 2469 mlx5_glue->free_device_list(ibv_list); 2470 return ret; 2471 } 2472 2473 /** 2474 * DPDK callback to remove a PCI device. 2475 * 2476 * This function removes all Ethernet devices belong to a given PCI device. 2477 * 2478 * @param[in] pci_dev 2479 * Pointer to the PCI device. 2480 * 2481 * @return 2482 * 0 on success, the function cannot fail. 2483 */ 2484 static int 2485 mlx5_pci_remove(struct rte_pci_device *pci_dev) 2486 { 2487 uint16_t port_id; 2488 2489 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 2490 rte_eth_dev_close(port_id); 2491 return 0; 2492 } 2493 2494 static const struct rte_pci_id mlx5_pci_id_map[] = { 2495 { 2496 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2497 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 2498 }, 2499 { 2500 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2501 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 2502 }, 2503 { 2504 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2505 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 2506 }, 2507 { 2508 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2509 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 2510 }, 2511 { 2512 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2513 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 2514 }, 2515 { 2516 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2517 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 2518 }, 2519 { 2520 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2521 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 2522 }, 2523 { 2524 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2525 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 2526 }, 2527 { 2528 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2529 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 2530 }, 2531 { 2532 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2533 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 2534 }, 2535 { 2536 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2537 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 2538 }, 2539 { 2540 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2541 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 2542 }, 2543 { 2544 .vendor_id = 0 2545 } 2546 }; 2547 2548 static struct rte_pci_driver mlx5_driver = { 2549 .driver = { 2550 .name = MLX5_DRIVER_NAME 2551 }, 2552 .id_table = mlx5_pci_id_map, 2553 .probe = mlx5_pci_probe, 2554 .remove = mlx5_pci_remove, 2555 .dma_map = mlx5_dma_map, 2556 .dma_unmap = mlx5_dma_unmap, 2557 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | 2558 RTE_PCI_DRV_PROBE_AGAIN, 2559 }; 2560 2561 #ifdef RTE_IBVERBS_LINK_DLOPEN 2562 2563 /** 2564 * Suffix RTE_EAL_PMD_PATH with "-glue". 2565 * 2566 * This function performs a sanity check on RTE_EAL_PMD_PATH before 2567 * suffixing its last component. 2568 * 2569 * @param buf[out] 2570 * Output buffer, should be large enough otherwise NULL is returned. 2571 * @param size 2572 * Size of @p out. 2573 * 2574 * @return 2575 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 2576 */ 2577 static char * 2578 mlx5_glue_path(char *buf, size_t size) 2579 { 2580 static const char *const bad[] = { "/", ".", "..", NULL }; 2581 const char *path = RTE_EAL_PMD_PATH; 2582 size_t len = strlen(path); 2583 size_t off; 2584 int i; 2585 2586 while (len && path[len - 1] == '/') 2587 --len; 2588 for (off = len; off && path[off - 1] != '/'; --off) 2589 ; 2590 for (i = 0; bad[i]; ++i) 2591 if (!strncmp(path + off, bad[i], (int)(len - off))) 2592 goto error; 2593 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 2594 if (i == -1 || (size_t)i >= size) 2595 goto error; 2596 return buf; 2597 error: 2598 DRV_LOG(ERR, 2599 "unable to append \"-glue\" to last component of" 2600 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 2601 " please re-configure DPDK"); 2602 return NULL; 2603 } 2604 2605 /** 2606 * Initialization routine for run-time dependency on rdma-core. 2607 */ 2608 static int 2609 mlx5_glue_init(void) 2610 { 2611 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 2612 const char *path[] = { 2613 /* 2614 * A basic security check is necessary before trusting 2615 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 2616 */ 2617 (geteuid() == getuid() && getegid() == getgid() ? 2618 getenv("MLX5_GLUE_PATH") : NULL), 2619 /* 2620 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 2621 * variant, otherwise let dlopen() look up libraries on its 2622 * own. 2623 */ 2624 (*RTE_EAL_PMD_PATH ? 2625 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 2626 }; 2627 unsigned int i = 0; 2628 void *handle = NULL; 2629 void **sym; 2630 const char *dlmsg; 2631 2632 while (!handle && i != RTE_DIM(path)) { 2633 const char *end; 2634 size_t len; 2635 int ret; 2636 2637 if (!path[i]) { 2638 ++i; 2639 continue; 2640 } 2641 end = strpbrk(path[i], ":;"); 2642 if (!end) 2643 end = path[i] + strlen(path[i]); 2644 len = end - path[i]; 2645 ret = 0; 2646 do { 2647 char name[ret + 1]; 2648 2649 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 2650 (int)len, path[i], 2651 (!len || *(end - 1) == '/') ? "" : "/"); 2652 if (ret == -1) 2653 break; 2654 if (sizeof(name) != (size_t)ret + 1) 2655 continue; 2656 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 2657 name); 2658 handle = dlopen(name, RTLD_LAZY); 2659 break; 2660 } while (1); 2661 path[i] = end + 1; 2662 if (!*end) 2663 ++i; 2664 } 2665 if (!handle) { 2666 rte_errno = EINVAL; 2667 dlmsg = dlerror(); 2668 if (dlmsg) 2669 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 2670 goto glue_error; 2671 } 2672 sym = dlsym(handle, "mlx5_glue"); 2673 if (!sym || !*sym) { 2674 rte_errno = EINVAL; 2675 dlmsg = dlerror(); 2676 if (dlmsg) 2677 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 2678 goto glue_error; 2679 } 2680 mlx5_glue = *sym; 2681 return 0; 2682 glue_error: 2683 if (handle) 2684 dlclose(handle); 2685 DRV_LOG(WARNING, 2686 "cannot initialize PMD due to missing run-time dependency on" 2687 " rdma-core libraries (libibverbs, libmlx5)"); 2688 return -rte_errno; 2689 } 2690 2691 #endif 2692 2693 /** 2694 * Driver initialization routine. 2695 */ 2696 RTE_INIT(rte_mlx5_pmd_init) 2697 { 2698 /* Initialize driver log type. */ 2699 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 2700 if (mlx5_logtype >= 0) 2701 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 2702 2703 /* Build the static tables for Verbs conversion. */ 2704 mlx5_set_ptype_table(); 2705 mlx5_set_cksum_table(); 2706 mlx5_set_swp_types_table(); 2707 /* 2708 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 2709 * huge pages. Calling ibv_fork_init() during init allows 2710 * applications to use fork() safely for purposes other than 2711 * using this PMD, which is not supported in forked processes. 2712 */ 2713 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 2714 /* Match the size of Rx completion entry to the size of a cacheline. */ 2715 if (RTE_CACHE_LINE_SIZE == 128) 2716 setenv("MLX5_CQE_SIZE", "128", 0); 2717 /* 2718 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 2719 * cleanup all the Verbs resources even when the device was removed. 2720 */ 2721 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 2722 #ifdef RTE_IBVERBS_LINK_DLOPEN 2723 if (mlx5_glue_init()) 2724 return; 2725 assert(mlx5_glue); 2726 #endif 2727 #ifndef NDEBUG 2728 /* Glue structure must not contain any NULL pointers. */ 2729 { 2730 unsigned int i; 2731 2732 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 2733 assert(((const void *const *)mlx5_glue)[i]); 2734 } 2735 #endif 2736 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 2737 DRV_LOG(ERR, 2738 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 2739 mlx5_glue->version, MLX5_GLUE_VERSION); 2740 return; 2741 } 2742 mlx5_glue->fork_init(); 2743 rte_pci_register(&mlx5_driver); 2744 } 2745 2746 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 2747 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 2748 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 2749